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This tutorial briefly describes the ISE synthesis/simulation suite, from Xilinx, a design software for CPLD/FPGA-based circuits. The description is based on ISE 11.1 WebPack, available free of charge at www.xilinx.com. The registered multiplexer of Figure C.1 will be used as an example. Only VHDL input will be considered. The tutorial is divided into eight parts: 1. Introduction 2. Starting a New Project 3. Synthesizing the Design 4. Inspecting Synthesis Results 5. Simulating the Circuit with ISim 6. Simulating the Circuit with ModelSim 7. Making pin assignments 8. Physically Implementing the Design
1. Introduction ISE 11.1 allows integrated synthesis and simulation as follows. Synthesis: With XST (Xilinx Synthesis Technology), Precision RTL (from Mentor Graphics), or Synplify (from Synopsys). Simulation: With ISim (ISE Simulator, from Xilinx), ModelSim (from Mentor Graphics), NC-Sim (from Cadence), or VCS (from Synopsys) After a survey with ISE users, Xilinx decided, in version 11.1 (2009), to remove the waveform generator from its simulator. This means that manual graphical inputs (which can be very helpful in the classroom, particularly in the beginning of VHDL/Verilog courses) are no longer possible (only stimuli from testbench files can now be entered into the simulator). To compensate for the limitation above, we have included, in the ModelSim tutorial (Appendix D), some Tcl commands to construct script files so the user can still employ that kind of simulation (though it would be much simpler with a properly designed GUI, as in Quartus II). The registered multiplexer studied in Section 10.5 (repeated in Figure C.1 below) will be used in this tutorial. Its design and test files are the following: Design file: reg_mux.vhd, seen in Section 10.5.
Testbench file: reg_mux_tb.vhd, with one option (without automated verification) seen in Example 10.4 and another (with automated verification) seen in Example 10.6. The former will be employed here.a(3:0) b(3:0) c(3:0) d(3:0)registered multiplexer (reg_mux.vhd)
0 1 2 3
Figure C.1
2. Starting a New Project a) Create a directory where all the design files should be located (work library). Copy the files reg_mux.vhd and reg_mux_tb.vhd mentioned above to that directory. If they were not typed yet, the ISE text editor can be used (step 2f ahead). b) Launch ISE. c) Select File > New Project, which will open the Create New Project dialog of Figure C.2(a). Enter the project name and location (note that the project name is automatically copied to the project location). Click Next, which opens the dialog of Figure C.2(b).
Figure C.2
d) In the Device Properties dialog (Figure C.2(b)), select the device, the synthesizer (XST), the simulator (ISim we will deal with ModelSim too later), and the language (VHDL). Click Next and Finish until the Project Navigator (Figure C.3) is opened. e) Observe the Project Navigators four windows: Sources, Processes, Transcript, and Workspace. Make sure that Sources for is set to Implementation. f) Open the design (reg_mux.vhd) and testbench (reg_mux_tb.vhd) files (they will be displayed in the Workspace window). If they were not typed yet, click or select File > New > Text File to enter each file.
Processes window
Transcript window
Figure C.3
3. Synthesizing the Design a) First, we must define the project sources, which are the two files prepared above. Select Project > Add Source, highlight reg_mux.vhd and click Open. This opens the dialog of Figure C.4(a). In the Association field, select All. Do the same for reg_mux_tb.vhd, now selecting Simulation in the Association field, as shown in Figure C.4(b).
Figure C.4
Note 1: The first of the files above is the source for synthesis, while the second is the source for simulation. Consequently, if one prefers, the latter can be included later (in Section 5 or 6). Note 2: If at any point you need to remove sources from the project, proceed as follows. To remove a design file: In the Source for field of the Sources window, select Implementation. Right-click the file name and select Remove. To remove a testbench file: In the Source for field of the Sources window, select Behavioral Simulation. Rightclick the file name and select Remove. b) Next, set the synthesis effort. Select Project > Design Goals & Strategies and choose Balanced. c) The design is now ready to be synthesized. At this point, the Processes window will look like that in Figure C.5. Note that under the synthesis process there are four possible actions. For example, if the input files are still being debugged, one might prefer to run just the Check Syntax module. To synthesize the circuit, doubleclick Synthesize XST. Some of the results from the synthesis process will be examined in the next section. Note: At any point you can restart the whole process by selecting Project > Cleanup Project Files, which will delete the files created by ISE (but not the design and testbench files).
Figure C.5
4. Inspecting Synthesis Results The synthesis reports contain several pieces of valuable information, some of which are examined below. a) Design parameters: On the upper left corner of the Workspace window select Design Overview > Summary. The result is partially shown in Figure C.6. Observe in the Project Status table the name of the design, the device used, and the design goal (Balanced). b) Device utilization: In the Device Utilization Summary table of figure C.6 observe that 4 slices were used (out of 768 available in the chosen device), 4 flip-flops were inferred (as expected), and that the circuit requires 27 pins (expected: 4x4+2+1 inputs + 2x4 outputs = 27).
Figure C.6
c) RTL view: Double-click View RTL Schematic in Figure C.5 or select Tools > Schematic Viewer > RTL. The Create RTL Schematic dialog will be opened. Click the + icon next to Signal, select all signals in the list, then click Add to copy the signals to the column on the right. Finally, click Create Schematic. The result is shown in Figure C.7(a). Note that this circuit coincides with that in Figure C.1. This is how our circuit was understood by the synthesizer (after optimization and place & route it might look a little different, but obviously still with the same functionalities).
Figure C.7
d) Technology view: Double-click View Technology Schematic in Figure C.5 or select Tools > Schematic Viewer > Technology, then proceed as in step 4c above, which will cause the final circuit to be exhibited (Figure C.7(b)). e) Timing analysis: Select Tools > Timing Analyzer > Post-Place & Route. After the process is concluded, check in the Report Navigation the time values in Setup/Hold to clock clk and in Pad to pad (a few ns are generally reported), which help give an initial rough idea about the designs maximum speed. 5. Simulating the Circuit with ISim a) If not done yet, enter the source file for simulation (in this tutorial, it was done in step 3a). b) We must choose between functional or timing simulation. The former checks only the design functionalities, while the latter includes also the devices internal propagation delays, thus representing the actual circuit. - For functional simulation, continue in step 5c below. - For timing simulation, go to step 5d. c) Functional simulation: In the Sources window of the Project Navigator, select Behavioral Simulation in the Sources for field (as shown in the upper part of Figure C.8(a)). Then highlight the testbench file, which will cause the ISim menu to be exhibited in the Processes window (lower part of Figure C.8(a)). Double-click Simulate Behavioral Model in the Processes window. This will start ISim, which displays the waveforms window of Figure C.8(b). When done, go to step 5e. d) Timingsimulation: In the Sources window of the Project Navigator, select Post-Route Simulation in the Sources for field (as shown in the upper part of Figure C.8(c)). Then highlight the testbench file, which will cause the ISim menu to be exhibited in the Processes window (lower part of Figure C.8(c)). Double-click Simulate Post-Place & Route Model in the Processes window. This will start ISim, which displays the waveform window of Figure C.8(d). e) In Figure C.8(b) or C.8(d) (depending on the simulation type), select all signals but clk and change their radix to unsigned decimal (right-click a signal name and select Radix > Unsigned Decimal). f) Click the Zoom to Full View icon to see the whole plot. Note that the simulation time interval (0.8 us in this example) can be changed to any other value.
(a) (c)
(b) (d)
Figure C.8
g) Examine the results in Figure C.8(b). Note particularly the following: - They coincide with the results in Example 10.4. - If it is a functional simulation (Figure C.8(b)), there are no time delays between input and output transitions. - If it is a timing simulation (Figure C8(d)), then there are time delays between input and output transitions. For example, the marker and cursor in the figure show a 6.2 ns time delay between the clock transition and the change in y. h) To get acquainted with ISim, practice with the Run and Zoom controllers. For example, click the Run for the , followed by the Zoom to Full View icon , to see that the simulation advances another Time Specified icon 0.8 us. Now click the Restart icon , followed by and . i) Practice also with: (for example, select x and then click one of these icons and observe the - Previous/Next Transition icons corresponding time value at the cursor foot). . - Go to Time 0 and Go to the Latest Time icons - Cursor and time markers .
6. Simulating the Circuit with ModelSim a) If not done yet, enter the source file for simulation (in this tutorial, it was done in step 3a). b) In the simulation above, ISim was used. To change to ModelSim, right-click anywhere in the Sources window and select Design Properties, which opens a dialog similar to that in Figure C.2(b). In the Simulator field, select the ModelSim version available. c) Now proceed as in Section 5 above to run either functional or timing simulation. When ModelSim is started, follow the ModelSim tutorial of Appendix D. Note: If ISE is unable to find the ModelSim executable file, select Edit > Preferences and enter the full path to the executable file in the Model Tech Simulator field. 7. Making Pin AssignmentsSynthesis,
a) Start the PlanAhead component of ISE by selecting Tools > PlanAhead > I/O Pin Planning (PlanAhead) Postwhich opens the PlanAhead navigator of Figure C.9. b) To have the I/O pins placed automatically, select Tools > Auto-Place I/O Ports. Click Next and Finish. Observe that device pins are assigned to all 27 circuit ports. Note: To remove all pin assignments, select Tools > Clear Placement Constraints and just follow the dialogs. c) In the I/O Ports window of the PlanAhead navigator (Figure C.9), click any port name and observe that it is highlighted in both the Device and the Package floorplan windows.
d) To change pin assignments, use again the I/O Ports window. Double-click the port name (say, a[0]) or any other position in that line, which will cause that specific port to be displayed in the I/O Port Properties window. In the Site field, enter the desired pin name, then click Apply. If that pin is available, the assignment will be accepted. e) When done making manual pin assignments, run Tools > DRC to check (fix) any inconsistencies, then recompile the design (step 3c).
Figure C.9
8. Physical Implementation a) Connect the development board containing the target CPLD or FPGA device to your computer and turn the power on the board on. b) In the Sources for field of the Sources window select Implementation. c) Still in the Sources window, highlight the design file (reg_mux.vhd), which will cause the menu shown in the Processes window of Figure C.5 to be displayed. d) In the Processes window, double-click Implement Design. e) Next, double-click Generate Programming File. f) Finally, double-click Configure Target Device, which starts the iMPACT tool, responsible for configuring the device (iMPACT requires some setups, like the chain type Boundary Scan, for example; details about iMPACT are available at the Xilinx website).


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Buis, Alena. "'A Story of Struggle and Splendid Courage': Anne Savage's Broadcasts of The Development of Art in Canada." In Rethinking Professionalism: Women and Art in Canada, 1850-1970, edited by Kristina Huneault and Janice Anderson, 106–131. Montreal and Kingston: McGill-Queen's University Press, 2012.
Hayes, Janet. "A Study of the Effects of Acculturation on Sex-Role Attitudes of Chinese Couples, and the Subsequent Impact of These Sex-Role Attitudes on Couple's Household Task Sharing & Decision Making." Research paper, Concordia University, 1995.
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text: Only one can survive – which would you choose? Published: 29 May 2013 Updated: 20 November 2014 The BMF or MAG, you decide... pollcomment By MCN The voice of motorcycling since 1955 Other pages you might like ... NewsArticles VideoVideos Police deploy clever tech to crack crime Britain's leading bike crime expert says that despite a reduction in UK thefts, it's still a massive... In this week's MCN paper: Guy Martin's Great Escape In your new edition of Motor Cycle News this week we've got the biggest stories in biking along with... Hickman set to put Norton on top: Smiths racing to develop Superlight Peter Hickman will bid to win the Lightweight TT in 2020 onboard a Smiths Racing-prepared Norton... Vredestein Centauro ST: new kid on the block This is Vredestein's first big bike radial tyre. The Dutch firm, better known in the car world, have... BMW's E-Power Roadster could be their missing link BMW have been quietly working on an electric motorcycle project for the last two years. The result... Eisenberg V8: 480bhp twin 'Busa-engined beast Speed record breaking superstar and general madman Zef Eisenberg has taken all of his high-speed... WSB: Scheib joins Orelac Racing VerdNatura for 2020 season Maximilian Scheib will contest his first full season in the World Superbike Championship next year... Get down and dirty today with MCN's best off-road bikes While winter may put a chill and a dampener on road and track motorcycling it remains a great time... DR Big appeal for £109 a month? 2020 Suzuki V-Strom 1050 PCP rates revealed You can get a 2020 Suzuki V-Strom 1050 on the firm's Flexible Finance scheme (a PCP agreement) for... Weekly wind-on: the biggest news in motorbikes from the past week This week on MCN we've seen lots of news from Triumph as they unveiled a new model, announced their... Want to learn how your R1M really rides? Get on track with the 2020 Yamaha Racing Experience days If you've placed an order for a new Yamaha R1M, the company would like to invite you to one of two... Video: Kawasaki Z650 cleans up for Euro5 Just like lots of new bikes this year, the updates to the 2020 Kawasaki Z650 are designed to squeeze... Lexmoto LXR 380 sportsbike is the firm's first A2-friendly model Introducing the Lexmoto LXR 380; a brand-new A2-compliant sportsbike costing £2399 less than the... Michelin reveal gripping new range for 2020 Michelin have just rolled out a raft of new road and track tyre options for 2020, covering... MCN Fleet: Honda CBR650R tyre comparison One of the drawbacks of the Honda CBR650R was the factory's choice of OE tyres. The Dunlop D214... MCN Fleet: Final Farewell for Ducati Diavel 1260S It's been an interesting year of riding; not my most enjoyable but that's not the fault of the... Old tech punches clever on 1800cc air-cooled BMW R18 boxer concept BMW's forthcoming R18 cruiser range is one of the biggest motorcycling moves that the German giant... A change is better than a rest for #ride5000miles fans It's easy sticking to what you know, but some #ride5000miles members have bucked the trend this year... Giacomo Agostini museum opens in 15-time world champion's home town A museum celebrating the racing achievements of 15-time world champion, Giacomo Agostini, has today... Kymco RevoNEX electric naked set for 2021 release Kymco have created the RevoNEX, an electric naked which they say will be on sale in 2021. The... Share this article ... Advertisement


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text:
The River Parrett flows through the counties of Dorset and Somerset in South West England, from its source in the Thorney Mills springs in the hills around Chedington in Dorset. Flowing northwest through Somerset and the Somerset Levels to its mouth at Burnham-on-Sea, into the Bridgwater Bay nature reserve on the Bristol Channel, the Parrett and its tributaries drain an area of 660 square miles (1,700 km2) – about 50 per cent of Somerset's land area, with a population of 300,000.
The Parrett's main tributaries include the Rivers Tone, Isle, and Yeo, and the River Cary via the King's Sedgemoor Drain. The 37-mile (60 km) long river is tidal for 19 miles (31 km) up to Oath. The fall of the river between Langport and Bridgwater is only 1 foot per mile (0.2 m/km), so it is prone to frequent flooding in winter and during high tides. Many approaches have been tried since at least the medieval period to reduce the incidence and effect of floods and to drain the surrounding fields.
In Anglo-Saxon times the river formed a boundary between Wessex and Dumnonia. It later served the Port of Bridgwater, and enabled cargoes to be transported inland. The arrival of the railways led to a decline in commercial shipping, and the only working docks are at Dunball. Man's influence on the river has left a legacy of bridges and industrial artefacts. The Parrett along with its connected waterways and network of drains supports an ecosystem that includes several rare species of flora and fauna. The River Parrett Trail has been established along the banks of the river.
Parrett is an English surname. Notable persons with the name include:
Standing on the corner
Plastic cup in her hand
Standing on the corner
Saving for some gin
You don't need to ask where she's been or what's up
She'll gladly tell you all about the life she had
Before she had the cup
Standing by the window
Glass of milk in his hand
What could I have done what could I have said
Broken glass spilled milk lying on the floor looking dead
Window pain
Cutting through the rain looks so easy
Frame by frame
Looking for a name to claim on a breezy afternoon
And the ends coming soon
So many people hold a cup
So many die drinking milk in front of a window
I once knew a woman who got in the way
Of the intentions of a windy day
Don't hold a cup in any season
Don't make me choose between rhyme or reason
Don't drink that milk in front of that window


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Dr. Lou Welcome3 books in series
Oath of Office Publisher's Summary
From the New York Times best-selling author of A Heartbeat Away and The Last Surgeon comes a shocking new novel at the crossroads of politics and medicine.
What if a well respected doctor inexplicably goes on a murderous rampage? When Dr. John Meacham goes on a shooting spree, his business partner, staff, and two patients are killed in the bloodbath. Then Meacham turns the gun on himself.
The blame falls on Dr. Lou Welcome. Welcome worked with Meacham years before as a counselor after John's medical license had been revoked for drug addiction. Lou knew that John was an excellent doctor and deserved to be practicing medicine, and fought hard for his license to be restored. After hearing the news of the violent outburst, Lou is in shock like everyone else, but mostly he's incredulous. When he begins to look into it further, the terrifying evidence he finds takes him down a path to an unspeakable conspiracy that seems to lead directly to the White House and those in the highest positions of power.
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Political Suicide
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Lou Welcome, from Palmer's bestselling Oath of Office, is back in this heart stopping medical thriller. A desperate phone call embroils Lou in scandal and murder involving Dr. Gary McHugh, known around the Capital as the "society doc." Lou has been supervising McHugh, formerly a black-out drinker, through his work with the Physician Wellness Office. McHugh has been very cavalier about his recovery, barely attending AA and refusing a sponsor. But Lou sees progress, and the two men are becoming friends.
Political Suicide
- Narrated by: Robert Petkoff
- Length: 10 hrs and 24 mins
- Release date: 11-12-2012
- Language: English
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Excellent location and beautiful hotel with amazing, helpful and friendly staff.
Clean, modern, excellent staff. Contained in room fridge. Great location


text: ubZcdn 0 Posted April 14, 2013 I'm not sure if this is the right place to post this. I'm trying to find a cool modpack with some specific things. First of all, the Platform-Site is really cool, but I'm really missing some Search options for the modpacks. So if you know a modpack which fulfill following conditions, please tell me: - mc v. 1.4.7 Client & Server - I love a high mod-count, but also good server-stability. I know a no-error-guarantee is impossible, but the modpack should be kinda well tested. - The idea of Tekkit Lite, that you can build a factory, that does everything for you is awesome. So nearly everything what is in there should be in that modpack, too. If there is missing something, just tell me, and maybe tell me why. - Added Metallurgy2 in a smart way to make things easier. I don't want additional iron-furnaces that confuse new players with weird Recipes. And no duplicates of copper and other ores in caves. Most important things are the crushers, platinum chests and the new piston-recipes. Rest is optional. Nether and EndOres are cool. Maybe Celenegil and Tartarite. - Why is nearly nobody using the simple "Backpack"-Mod? - Maybe Forestry? But not that important, because that mod can be very broken I think? - Some cool RPG or Magic Additions. I don't know if DivineRPG is a good idea, maybe there are other cool things. - If you want surprise me with other cool stuff - I will probably play with 5 - 12 people Maybe I expect too much. But thank you in advance and best regards (English isn't my first Language) Quote Share this post Link to post Share on other sites


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The School of Economics invites staff and students to attend a public lecture with Rt Hon. Lord Willetts, an English Conservative Party politician who from 1992 to 2015 was the Member of Parliament for Havant in Hampshire.
David was the Minister of State for Universities and Science from 2010 until July 2014 and became a member of the House of Lords in 2015. He is currently the chairman of the Resolution Foundation, a think-tank that works to improve the living standards of those in Britain on low to middle income.
This lecture will be held in A41, Sir Clive Granger Building on Tuesday 27 November, 17.00-18.00. All welcome, no booking required.
Tags: conservative party, economics, parliament, politician
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