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We present a model for dislocation array image effects during epilayer island growth. Misfit dislocations often appear at an interface between phases, to accommodate a lattice mismatch. In many situations, such as early film growth, one of the phases may be discontinuous, leaving the interface region clearly bounded. The structure of such a finite interface differs from the normally-modeled infinite boundary because of end effects near the edges of the islands. We have modeled the dislocation structure of such a finite interface in MBE-grown InAs islands on GaP, and compare our results to high-resolution images of the same structure. The 11% misfit causes dislocation introduction from the outset of growth. Islands containing between 4 and 14 dislocations were examined, and dislocation spacings were found to be enlarged near the island perimeters. The model provides a clear understanding of this and other effects.
This paper presents a multiple magnetoelastic (ME) biosensor system for in-situ detection of S. typhimurium and B. anthracis spores in a flowing bacterial/spore suspension (5 x 101 - 5 x 108 cfu/ml). The ME biosensor was formed by immobilizing filamentous phage (specific to each detection target) on the ME platforms. An alternating magnetic field was used to resonate the ME biosensor to determine its resonance frequency. When cells/spores are bound to a ME biosensor surface, the additional mass of the cells/spores causes a decrease in the resonance frequency of the biosensor. The detection system was composed of a control sensor, an E2 phage-based biosensor (specific to S. typhimurium) and a JRB7 phage-based biosensor (specific to B. anthracis spores). The frequency response curves of the ME biosensors as a function of exposure time were then measured and the detection limit of the ME biosensor was observed to be 5 x 103 cfu/ml. The results show that phage-based ME biosensors can detect multiple pathogens simultaneously and offer good performance, including good sensitivity and rapid detection.
Magnetoelastic materials are amorphous, ferromagnetic alloys that usually include a combination of iron, nickel, molybdenum and boron. Magnetoelastic biosensors are mass sensitive devices comprised of a magnetoelastic material that serves as the transducer and bacteriophage as the bio-recognition element. By applying a time varying magnetic field, the magnetoelastic sensor thin films can be made to oscillate, with the fundamental resonant frequency of oscillations depends on the physical dimensions and properties of the material. The change in the resonance frequency of these mass based sensors can be used to evaluate the amount of analyte attached on the sensor surface. Filamentous bacteriophage specific to S. typhimurium was used as a bio-recognition element in order to ensure specific and selective binding of bacteria onto the sensor surface. The sensitivity of magnetoelastic materials is known to be dependent on the physical dimensions of the material. An increase in sensitivity from 159Hz/decade for a 2mm sensor to 770Hz/decade for a 1mm sensor and 1100Hz/decade for a 500micron sensor was observed. The sensors were characterized by scanning electron microscopy (SEM) analysis assayed biosensors to provide visual verification of frequency responses and an insight into the characteristics of the distribution of phage on the sensor surface. The magnetoelastic sensors immobilized with filamentous phage are suitable for specific and selective detection of target analyte in different media. Certain modifications to the measurement circuit resulted in better signal to noise ratios for sensors with smaller dimensions (L<1mm). This was achieved by tuning the circuit resonance close to that of the sensor. According to models and preliminary tests, this method was anticipated in about a 5 times increase in signals for a 200×40×6microns. This technique and further studies into the design and modification of the measurement circuits could yield better, sensitive responses for sensors with smaller dimensions. The magnetoelastic materials offer further advantages of potential miniaturization, contact-less nature and ease of operation.
Maternal under-nutrition (MUN) during gestation results in growth-restricted newborns with reduced glomerular number and subsequent hypertension. We investigated dysregulation of glial derived neurotrophic factor (GDNF) and MAPK–ERK (mitogen-activated protein kinase–extracellular signal-regulated protein kinase) signal pathway gene expression following MUN. MUN rats were 50% food restricted from embryonic day 10 till postnatal day 1. Kidneys were harvested at embryonic day (E)20, and postnatal days (P)1 and 21. Kidney protein expression was determined by Western blot. At E20, protein expression of growth factor receptor alpha 1 (GFRα1) and phosphorylated ERK1/2 and mitogen-activated protein kinase kinase (MEK)1/2 were reduced significantly, and immunohistochemistry confirmed reduction of phosphorylated ERK (pERK) with maintenance of pERK localization. Total MEK and ERK were unchanged. At P1, only GFRα1 and pERK1/2 were reduced significantly while at P21, expression of all growth factors except total MEK was unchanged. Total MEK was increased. Glomerular number was decreased by 19% in P21 kidneys and blood pressure was increased in 12-week-old rats. In conclusion, GDNF and MAPK–ERK signaling are dysregulated during active nephrogenesis in fetal and early newborn offspring kidneys in the MUN model. This may be a key mechanism in reduced offspring nephrogenesis and programmed hypertension.
1. The interrelationship between cholesterol and vitamin A metabolism has been studied in rats.
2. The effect of cholesterol feeding in increasing the liver storage of cholesterol w-as enhanced during vitamin A deficiency.
3. This effect was due to an increased rate of absorption of cholesterol and not due to a decreased turnover rate.
4. Feeding of high levels of vitamin A markedly depressed the cholesterol absorption; however, its turnover was unaffected.
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Panasonic TH-43FX600A (43")
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DE112008003520B4 - System and method for fast platform hibernation and recovery - Google PatentsSystem and method for fast platform hibernation and recovery
- Publication number
- Authority
- Germany
- Prior art keywords
- volatile memory
- system
- memory
- processor
- system context
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
- G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of power-saving mode
An apparatus comprising: processor cores; volatile memory, which operates as a system memory for the processor cores; a smaller nonvolatile memory to hold system context information copied from the volatile memory; a larger nonvolatile memory to hold an operating system, programs and data for use by the processor cores; power management logic to control at least some aspects of power management; and an embedded processor for controlling the transfer of system context data between the volatile memory and the smaller nonvolatile memory, the embedded processor being independent of the processor cores and a platform state of the device; wherein, in response to an instruction to suspend a volatile memory and change a power state, the device causes a system context to be backed up by the operating system in a contiguous area of the volatile memory and provides an adjustment to indicate a deep sleep state, the setting causes an interruption that causes ...
- Embodiments of the invention generally relate to hibernation and recovery in a computer platform.
- Computer systems typically have certain low power states called S-states, including S3 and S4. S3 is sometimes referred to as standby, sleep, or suspend to RAM. State S3 is a sleep state in which the operating system (OS) secures its context in a physical memory (Dynamic Random Access Memory) (DRAM) and places the system in an suspended state. Open documents and programs (applications) used at the time S3 was entered, or at least some of the programs are also backed up in the DRAM during the suspended state. Contents of some chipset registers can also be written to the DRAM. The physical memory DRAM is sometimes called main memory or system memory. During this suspended state, all power is removed from the hardware of the platform, with the exception of the DRAM and a small amount of circuitry used to wake up the system later. The S3 performance state provides relatively fast suspend and resume (wake-up) time due to its ability to back up and recover the OS context and previously used programs and documents from the high-speed DRAM memory.
- S4 is sometimes referred to as rest (deep sleep hibernate), safe sleep, or suspend to disk. In S4, the OS context and open documents and programs (or part of it) are backed up to a hard disk drive (HDD) rather than the fast DRAM memory. This allows for higher energy savings than the S3 state because the DRAM is not kept powered. However, there are longer waiting times due to the slow read and write access times of the HDD. Typical rest and recovery times at S4 are on the order of a few tens of seconds.
- While some 10 seconds generally do not seem to take much time, for a user waiting for his or her computer to enter hibernation or be taken out of hibernation, it may seem like a long time. Further, although the amount of energy needed to keep the DRAMs in operation for a short period of time is not large, it may have a significant effect on the charge in a battery over a longer period of time.
- The
- The
- According to the invention this object is achieved by a device according to claim 1 and a method according to claim 10. The respective subclaims relate to advantageous developments of the device or of the method.
- The inventions will be more fully understood from the detailed description given hereinafter and from the accompanying drawings of embodiments of the inventions, which, however, should not be construed as limiting the inventions to the particular embodiments as described; but merely for explanation and understanding.
1FIG. 10 is a block diagram illustration of a computer system according to some embodiments. FIG.
2FIG. 10 is a cross-sectional view of a mobile computer according to some embodiments. FIG.
3FIG. 12 illustrates flowcharts of a fast hibernation and fast hibernation recovery path according to some embodiments.
4- 710 are each a block diagram illustration of a computer system according to some embodiments.
- Some embodiments of the invention include circuitry and techniques to enable a new fast sleep process in which a system context is written to nonvolatile memory (the smaller nonvolatile memory or NVRAM) that has a lower capacity than another nonvolatile memory (FIG. the larger non-volatile memory or hard disk drive) used to store at least one operating system, programs and data. When resuming from a fast sleep state, the system context is read from the smaller non-volatile memory and used to restore the operation of a computer system. In some embodiments, the system context is completely transferred from the DRAM system memory to the smaller nonvolatile memory and completely transferred from the smaller nonvolatile memory to the DRAM system memory upon resumption. In further embodiments, the system context may partially come from a different memory, such as chipset registers, and be written back directly into these registers instead of going through the DRAM indirectly.
- In some embodiments, in the fast idle state process, the transfer from the DRAM system memory to the smaller nonvolatile memory occurs even after processor cores and other system components such as a hard disk and a display screen have been shut down. This allows the user of the computer to have the perception that the computer system is quickly shut down, even though the system context transmission has not yet ended. Accordingly, embodiments improve the user's perception of the responsiveness of the system. This gives the user greater satisfaction. This is in contrast to the prior art transition to S4 in which the processor copies the entire context to the hard disk drive (HDD) before the host system or partition enters hibernation and shuts down.
- In some embodiments, the fast idle state process may occur with an operating system (OS) designed for states S3 and S4, but not specifically configured for the fast idle state process. This can be done by having the BIOS and / or other mechanism respond to an instruction to suspend RAM (S3) by placing the processor in system management mode (SMM) and transitioning from DRAM system memory is controlled to the smaller nonvolatile memory and then a sleep type is changed to a sleep state. In these embodiments, the process may be "transparent" for some OSs.
- Regarding
1includes a system 12a processor 14using a platform controller hub (PCH - Platform Controller Hub) 16and a system memory (DRAM) 20is coupled. The processor 14includes cores 22a central processing unit (CPU) and a non-core 26, The term non-kernel is not meant to have a limited definition, but is a generic term that refers to parts of the processor with different interface and control circuits that are not part of the kernel. The non-core 26includes an integrated memory controller 28to the system memory 20to control. The system memory 20includes an area 30for holding commands for a system management mode (SMM). The SMM may correspond to prior art SMM techniques or new SMM techniques or a similar type of mode. A nonvolatile memory (NVRAM) 38is through a controller 34with a PCH 16coupled. In some embodiments, the NVRAM includes 38a fast flash and the controller 34is a NAND controller. In some embodiments, the controller may 34an embedded processor as described below. A hard drive 42is with the PCH 16coupled and holds an operating system, programs and data for the processor 14,
- In some embodiments, some of the contents of the hard disk may be
42be used by other components of the system. The NVRAM 38has considerably less storage capacity than the hard disk drive 42but has faster access than the hard disk drive 42, Accordingly, the NVRAM 38be referred to as a smaller non-volatile memory and the hard disk drive 42may be referred to as a larger nonvolatile memory. A basic input / output system (BIOS) 48provides BIOS commands to the system. A wake-up circuit 50can be energized during hibernation to enable recovery. In some embodiments, the components of the system become the 1held in a housing, such as a mobile computer.
2illustrates a mobile computer 62with a base part 64and a lid 66holding a display screen 68contains. The base part 64includes a system like the one of 1, The base part 64includes a switch 70to detect if the lid is opened and closed. The base section 64also includes buttons 72(such as for a keyboard or other keys, such as an on and off button) and a control device 94for a cursor. A command to change a power state (such as a "standby" command, also called a RAM or an S3 command, or in other embodiments, a fast idle command) may be initiated differently, depending on the embodiments and embodiments Embodiments of the embodiments. Examples of ways in which a power state change command may be initiated include one or more of the following: closing a lid, pressing an on / off button, pressing another button, performing control clicks with the cursor on a pull down menu or on an icon or other ways. A wake-up event (resume command) to cause the system to resume from hibernation may be initiated in a variety of ways, as well as depending on the embodiments and the embodiments of the embodiments. Examples of ways in which a resume command may be initiated include one or more of the following: opening a lid, pressing an on / off button, pressing another button, performing control clicks with a cursor, or other ways. In practice, there may be fewer ways to take up the job since it is desirable that the system be substantially completely shut down. In some embodiments, the only way to initiate a resume command is to press the power button.
- Regarding
2includes a power management unit 44Advanced Configuration & Power Interface (ACPI) block registers, although in other embodiments ACPI registers are not used. Various ACPI specifications have been released, including a revised version 3.0b dated October 10, 2006, available for download at www.acpi.info. There are also ACPI tables in software held in DRAM. As is known in the art, the BIOS of the system begins execution when the computer system is powered up. The BIOS of the system may be platform and chipset specific firmware and direct platform and chipset specific information through the APCI tables (in the DRAM).
- The ACPI registers include a register called the sleep type register (SLP_TYPE) and a sleep enable register (SLP_EN). Assume that a 01 in the sleep type register indicates the suspension and an 02 in the sleep type register indicates the sleep state. When a user chooses to suspend, the OS searches the ACPI table and sees that suspending means that bits 01 are written to the sleep type register. The OS programs this value into the sleep type register. When the OS is ready to go to suspend, it sets the / the bits to enable sleep. After the OS has set the sleep enable bit, the hardware takes over, and the PCH
16turns off the platform as described below.
- The system may be configured such that when a user chooses to suspend RAM (S3), the system actually makes the transition to a fast idle state. Alternatively, the transition to a fast sleep state may be an express option to the user. The following describes techniques for selecting a RAM suspend (S3) and retry later, but performing a fast hibernate and resume from hibernation later.
- An embedded processor (EP), like the embedded processor
34, could be an existing Manageability Engine (ME) in the chipset or any other processing engine (including host CPU high privilege modes) in the platform having access to the physical DRAM and a portion of the non-volatile memory, such as a flash, has. The EP 34can retrieve its code from either the flash or the physical memory and its execution is independent of the processor cores or the state of the host platform. This allows the EP 34Externally performs handling functions for the platform when the cores of the host are not running. Only the presence of an embedded processor in a chip of a computer system is not new, but it is believed that using an embedded processor is new as described herein.
- The NVRAM
38can hold its context without any external energy. Flash technology is an example of this type of memory and is used in almost all platforms to store bootstrap code (BIOS) and configuration data. The size of this memory may depend on the size of the bootstrap code of the platform and any other information that may be necessary to store while not powering the platform. The EP 34can also use the NVRAM to store its code and data. The NVRAM 38may include a flash memory such as a "fast flash" according to a currently available technology or a fast flash available in the future. The NVRAM 38can be used to store data in addition to the system context. If all other things are the same, NVRAM with faster access times is preferred. In some embodiments, the NVRAM has 38a capacity at least as large as that of the DRAM system memory 20and, in some embodiments, much larger than the DRAM system memory 20is.
3FIG. 12 is an overview of examples of a flowchart of a fast hibernation way and a hibernation recovery chart. FIG. The details may differ in the various embodiments. In the examples of 3represents the block 80the OS of the host. Hibernation data is stored in system memory DRAM 20(some can be written before the fast sleep command and some afterwards). Prior to a fast hibernate command (which may be the same as a S3 command), the platform (the host) is in state SO and the handler (ME) (the embedded processor 34be or may include) is in a state M0. The sleep type register is set to fast S4, which may be the same as S3 for some systems. When the sleep enable register is set to 1, a hardware interrupt is generated which causes the embedded processor 34the hibernation data from system memory DRAM 20in the fast flash NVRAM 38copied. The state of the platform host is then fast S4 and the ME has state M1.
- Once the copy is complete, the ME has the M-out state, and the wake-up logic
84is on. The awakening logic 84can the wake-up circuit 50be or include you. There can be different types of wake-up logic. The wake-up circuit 50may include one or more of a physical power button, a special button, a cursor control unit, a universal serial bus (USB) unit, a lid opening detector, or anything else.
- Once all the context associated with OS Hibernation has been copied to the fast NVRAM unit, the EP puts the DRAM of the system in a de-energized state and shuts itself off. At this point, only the minimum circuitry required to wake the system will retain power and the system will have completely hibernated.
- In the example of a resume route, if the wake-up logic
84enabled, the embedded processor copies 34the hibernation data on the fast flash MVRAM 38in the system memory DRAM 20, The BIOS then jumps to a wake-up vector of the OS.
- In some embodiments, in response to a power state change command, the OS writes to the sleep type register and the sleep enable register. There is a separate strategy in the BIOS. The BIOS may have a setup option where a user selects what command S3 would be to begin the fast transition to hibernation - so that when the OS wants to suspend RAM, the platform goes into hibernation. In some embodiments, the OS is unaware that a fast sleep transition is occurring and recognizes that an S3 change is occurring. In some embodiments, the BIOS facilitates the fast transition to hibernation as follows. A trigger is set so that when the OS writes to the Enable sleep bit, control is passed to the BIOS. (In some embodiments, the PCH supports
16a hardware SMM trigger.) A system management mode (SMM) takes control away from the OS in response to the SMM pin being activated. The SMM may be a prior art SMM or a modified new SMM. In some embodiments, the processor includes 14an SMM pin - which, when asserted, causes the processor core to enter an SMM mode. The processor cores pause and jump into the SMRAM area 30of the DRAM 20, The SMRAM area 30belongs to the BIOS, which can install the contents when driving up. If the SMM is asserted, the CPU takes its commands from the SMRAM 30, At the end of the SMM instructions, there may be a resume command to return to the OS.
- In some embodiments, the sleep type of suspend register for the RAM S3 to go to sleep is changed to DISC S4 (eg, 01 in 02) after the contents of the DRAM
20to the NVRAM 38are transferred. After the change in the Sleep Type tab, the OS continues to operate as if the system were in S3, and the BIOS continues to operate as if the system were in Hibernate mode, causing the system with fewer exceptions, as discussed, to off. In this sense, in some embodiments, the OS is "outwitted" and thinks the system is in the S3 when it is actually in a fast sleep state. This forces the hardware platform to transition to the lower sleep state S4, however, it does not force the OS to copy to the hard disk drive, as the OS thinks the platform is in an idle state. Accordingly, the shutdown process is much faster than in the case of the prior art S4. The process is even faster when the transition from context happens while much of the rest of the system is shutting down and after.
- Some aspects of transition to fast sleep for some embodiments are described as follows, but in other embodiments, the details are different.
- 1. The OS initiates a transition to fast hibernation by backing up its current state in a fixed contiguous area of the DRAM. This hibernation area includes a wake-up vector for the OS as well as hardware and software context for restoring the system upon recovery.
- 2. The OS sets the bits SLP_TYPE and SLP_EN in the chipset (PCH
16) to indicate to the chipset hardware that it wishes to sleep.
- 3. Setting the SLP_EN causes a hardware interrupt in the EP
34, The EP 34evaluate the interruption and notice that the system wants to go to the deep sleep state. The EP 34initiates a partial shutdown of the platform by shutting down the processor cores 22and the entire platform hardware visible to the user, with only the DRAM 20remains energized. Note that this could alternatively be triggered after a certain time delay (eg, 15 minutes), thus allowing the system to use the usual S3 for short duration sleep intervals, and the idle state function after a prolonged S3 interval (FIG. eg 15 minutes).
- 4. The EP
34copies the OS Hibernate data area from the system DRAM 20in the fast NVRAM memory 38via its internal SRAM buffer 82(in the 2shown).
- 5. The EP
34make the awakening logic 84ready to wake up from sleep.
- 6. The EP
34drives the DRAM 20down and puts itself in the off state.
- 7. At this point, the entire system is shut down, with the exception of minimal hardware needed to wake up the system.
- When a wake-up event occurs (initiate a resume command), the EP will turn off
34first and immediately initializes the system memory DRAM 20and begins restoring the DRAM context of the OS from the NVRAM fast unit 38, In some embodiments, this recovery of the DRAM occurs even before the processor begins executing the system code of the BIOS. While the BIOS is following its regular hibernation resumption path, the EP stops 34continue the OS context in the DRAM 20her, and if the BIOS 48completed its initialization of the processor, chipset and other platform components, the EP has 34already finished restoring the entire context to recover after hibernation for the OS in the DRAM. The BIOS 48terminates its execution and passes control to the OS's idle wake-up vector, which was originally embedded within the context for restoring the OS from dormant to DRAM and has been restored by the EP along with the rest of the idle state data. As soon as it gets control, the wakeup code for the OS immediately starts execution from the DRAM 20and restores the remaining OS components using hibernation recovery data in the DRAM. In further embodiments, the details are different.
- In some embodiments, when resuming from a fast idle state, the BIOS begins to execute and initialize system components, including the DRAM
20which is initialized since power had been turned off. The NVRAM 38is also initialized. Once the memory is initialized, at least some of the contents of the NVRAM become 38in the DRAM 20copied. A software switch in BIOS is performed from idle (S4) flow to a suspend (S3) flow. The BIOS then jumps to an S3_Aufweck_Vector. At this time has the OS, what it needs to continue with a S3_waking the OS.
- In some embodiments, there are additional processing agents to further accelerate the resume flow by adding compression hardware or to add security functionality by adding cryptographic capabilities.
- Some aspects of hibernation recovery for some embodiments are described as follows, but in other embodiments, the details are different.
- 1. A user activity causes a wake-up event, which causes the EP
34and the processor 14wake up.
- 2. The EP
34detects that the system is waking up from a fast hibernate event, and therefore initializes the memory and begins copying Hibernate Recovery Context of the OS from the NVRAM 38in the DRAM memory 20via its internal SRAM buffer 82,
- 3. The CPU comes out of reset and starts to run the BIOS system code. The BIOS performs its hibernation resume path and finally gives control to the wakeup vector for the OS in the DRAM, which has now been recovered from the EP.
- 4. At this point, control enters the wake-up vector of the OS in the DRAM and the OS begins to restore its state by using hibernation resumption data in the system memory.
- Because read and write access times to the NVRAM
38much faster than the read and write access times to the hard disk drive 42For example, the exposure and recovery times are much shorter in embodiments of the invention than in S4 exposure to DISC and the resumption of the prior art.
- Embodiments may provide a combination of faster response time to suspend and resume, and longer battery life because almost the entire system is switched off between hibernation and resumption.
4illustrates a system similar to that of the 1is, however, by the NVRAM controller (for example, the embedded processor) 134in the non-core 126of the processor 114is located, coupled with the PCH 132, The BIOS 148may be the same or slightly different from the BIOS 48be.
5illustrates a system that is the same as that of the 4, except that a PM unit 244in the non-core 220of the processor 214instead of in the PCH 232is included. There may be another PM unit in the PCH 232give. The BIOS 248may be the same or slightly different from the BIOS 48be. Power management logic may be included in a combination of the processor and the PCH or in one or the other.
6illustrates a system similar to that of the 1is, however, by having two processors 314-1and 314-2there, the non-cores 326-1and 326-2with IMCs 28-1and 28-2include, which with save 20-1and 20-2(with areas 30-1and 30-2) are each coupled as shown. The processors 314-1and 314-2are with the PCH 316coupled. The processors 314-1and 314-2, the non-cores 326-1and 326-2, the controller 334, the PM unit 344, the BIOS 348may be the same or different from the processor 14, the non-core 20, the controller 34, the PM unit 44and the BIOS 48be.
7illustrates a system similar to that of the 1is, except that the memory controller 428in a controller hub 416instead of in the non-core 426of the processor 414located. The memory controller 428, the BIOS 448and the power management unit 444may be the same or different from the memory controller 28, the BIOS 48and the power management unit 44be.
- In the figures, the different occurrences of CPU cores
22, Memory controller 28, Controller 34, Storage 20and area 30, NVRAM 38and hard drive 42be the same or it may differ.
- During some prior art normal S4 resume processes, the BIOS may take up to 10-15 seconds to initialize the system before handing control to a load unit for the OS. In some embodiments, in the fast idle state, the BIOS switches from the S4 to the S3 path once the DRAM context has been re-established (via the CPU SMM or the EP). This allows the BIOS to take the faster (for example, a few hundred milliseconds) S3 resume path and quickly jump to a wake-up vector for the OS. In further embodiments, the details are different.
- The invention is not limited to use with any particular operating system. Some embodiments may be used with Microsoft Windows, Vista, Mac OSs.
- The sleep type register and the sleep enable register may be physically separate registers or portions of a larger register.
- The NVRAM
38can be altogether in one physical location or distributed over physically different locations.
- The "logic" referred to herein may be implemented in circuitry, software, microcode, or a combination thereof.
- The shapes and relative sizes of the blocks in the figures are not meant to show actual shapes and relative sizes. An actual implementation could include additional components and connections between components that are not illustrated in the figures.
- One embodiment is an implementation or example of the inventions. The reference in the specification to "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments, in at least some embodiments, but not necessarily is included in all embodiments. The various occurrence of "one embodiment" or "some embodiments" does not necessarily always refer to the same embodiments.
- When it is said that the element "A" is coupled to the element "B", the element A may be directly coupled to the element B or may be indirectly coupled, for example via an element C.
- When the specification or claims indicate that a component, feature, structure, process or property A "causes" a component, feature, structure, process or property B, this means that "A" is at least a partial cause for "B" is that there may also be at least one other component, feature, structure, process, or property that aids in invoking "B". Similarly, A responds to B, not that it does not respond to C.
- When the description indicates that a component, feature, structure, process, or property may "include," "may," or "could," it is not necessary that the particular component, feature, structure, the process or property is included. When the description or claim refers to "an" element, it does not mean that there is only one such element.
Claims (12)
- Apparatus comprising: Processor cores; volatile memory, which operates as a system memory for the processor cores; a smaller nonvolatile memory to hold system context information copied from the volatile memory; a larger nonvolatile memory to hold an operating system, programs and data for use by the processor cores; power management logic to control at least some aspects of power management; and an embedded processor for controlling the transfer of system context data between the volatile memory and the smaller nonvolatile memory, the embedded processor being independent of the processor cores and a platform state of the device; wherein, in response to an instruction to suspend a volatile memory and change a power state, the device causes a system context to be backed up by the operating system in a contiguous area of the volatile memory and provides an adjustment to indicate a deep sleep state, wherein the setting causes an interrupt that causes the embedded processor to power off the processor cores and copy the system context from the volatile memory to the smaller non-volatile memory, then the embedded processor shuts down the volatile memory and set the embedded processor to a shutdown state; and in response to a resume command, waking the embedded processor and processor cores, the embedded processor initializes the volatile memory and copies at least a portion of the system context from the smaller nonvolatile memory to the volatile memory.
- The apparatus of claim 1, wherein the power management logic operates such that the operating system detects the suspension of the operation of the volatile memory when, in effect, the system context is stored in the smaller non-volatile memory, then the volatile memory is shut down by the embedded processor.
- The apparatus of claim 1, wherein the processor cores are powered down before the embedded processor copying the system context from the volatile memory into the smaller non-volatile memory has completed.
- The apparatus of claim 1, wherein in response to the command to change a power state, the system initially performs a task of exposing the volatile memory, the system context being stored in the volatile memory, and then, if there is no activity within a volatile memory certain period of time, the system context is stored in the smaller nonvolatile memory.
- The apparatus of claim 4, wherein the processor cores are turned off before completing the dropping of the system context in the smaller nonvolatile memory.
- The apparatus of claim 1, further comprising a non-core portion of a processor and wherein the embedded processor copies the system context from the volatile memory to the smaller non-volatile memory through the non-core.
- The apparatus of claim 6, wherein at least a portion of the power management logic is included in the processor.
- The apparatus of claim 1, further comprising a BIOS, and wherein the BIOS effects copying the system context from the volatile memory to the smaller nonvolatile memory and then copying the system context from the volatile memory to the smaller nonvolatile memory, and the BIOS causes a change in a sleep type register from a volatile memory suspend state to a sleep state.
- The apparatus of claim 8, further comprising a BIOS, wherein the BIOS causes the change in the bits of the sleep type register.
- A method comprising: Receiving a volatile memory suspension instruction and changing a power state for a device, the device comprising a volatile memory for operating as system memory for processor cores, a smaller non-volatile memory for holding system context information copied from the volatile memory, and a larger non-volatile memory for Holding an operating system containing programs and data for use by processor cores; Operating so that the operating system recognizes the step of suspending a volatile memory, comprising: Causing a system context to be backed up by the operating system in a contiguous area of the volatile memory, and providing a setting for indicating a deep sleep state, the setting causing an interrupt that causes an embedded processor to power off the processor cores and disable the system context copies volatile memory to the smaller nonvolatile memory, then the embedded processor shuts down the volatile memory and places the embedded processor in a shutdown state; and in response to a resume command, the embedded processor and processor cores are woken up and the embedded processor initializes the volatile memory and copies at least a portion of the system context from the smaller nonvolatile memory to the volatile memory.
- The method of claim 10, further comprising turning off processor cores prior to completing the dropping of the system context.
- The method of claim 10, wherein, in response to the instruction to suspend volatile memory and to change a power state, an operation to suspend the volatile memory is performed, wherein the system context is stored in the volatile memory, and then if there is no activity within a certain amount of time, the system context is stored in the smaller non-volatile memory.
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5/20/94: Edgar Martinez doubles down the left field line at the Kingdome off of Roger PavlikCheck out http://MLB.com/video for more!About MLB.com: Former Commissioner Allan H. (Bud) Selig announced on January 19, 2000, that the 30 Major League Club owners voted unanimously to centralize all of Baseball's Internet operations into an independent technology company. Major League Baseball Advanced Media (MLBAM) was formed and charged with developing, building and managing the most comprehensive baseball experience available on the Internet. In August 2002, MLB.com streamed the first-ever live full length MLB game over the Internet when the Texas Rangers and New York Yankees faced off at Yankee Stadium. Since that time, millions of baseball fans around the world have subscribed to MLB.TV, the live video streaming product that airs every game in HD to nearly 400 different devices. MLB.com also provides an array of mobile apps for fans to choose from, including At Bat, the highest-grossing iOS sports app of all-time. MLB.com also provides fans with a stable of Club beat reporters and award-winning national columnists, the largest contingent of baseball reporters under one roof, that deliver over 100 original articles every day. MLB.com also offers extensive historical information and footage, online ticket sales, official baseball merchandise, authenticated memorabilia and collectibles and fantasy games.Major League Baseball consists of 30 teams split between the American and National Leagues. The American League consists of the following teams: Baltimore Orioles; Boston Red Sox; Chicago White Sox; Cleveland Indians; Detroit Tigers; Houston Astros; Kansas City Royals; Los Angeles Angels ; Minnesota Twins; New York Yankees; Oakland Athletics; Seattle Mariners; Tampa Bay Rays; Texas Rangers; and Toronto Blue Jays. The National League, originally founded in 1876, consists of the following teams: Arizona Diamondbacks; Atlanta Braves; Chicago Cubs; Cincinnati Reds; Colorado Rockies; Los Angeles Dodgers; Miami Marlins; Milwaukee Brewers; New York Mets; Philadelphia Phillies; Pittsburgh Pirates; San Diego Padres; San Francisco Giants; St. Louis Cardinals; and Washington Nationals.Visit MLB.com: http://mlb.mlb.com Subscribe to MLB.TV: http://mlb.tv Download MLB.com At Bat: http://mlb.mlb.com/mobile/atbat Download MLB.com Ballpark: http://mlb.mlb.com/mobile/attheballpark Download MLB.com Clubhouse: http://mlb.com/clubhouse Play Beat The Streak: http://mlb.mlb.com/bts Get MLB Tickets: http://mlb.mlb.com/tickets Get Official MLB Merchandise: http://mlb.mlb.com/shop Connect with us:YouTube: http://youtube.com/MLB Facebook: http://facebook.com/mlb Instagram: http://instagram.com/mlb Twitter: http://twitter.com/mlb Pinterest: http://pinterest.com/mlbofficial Tumblr: http://mlb.tumblr.com Google+: http://plus.google.com/+MLB
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: Edgar doubles down the line, scores Griffey
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Explore window materials or choose the style of window for your home.
Make a grand entrance with a new 5 Star Door.
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Credit is subject to application and affordability. Terms and conditions apply. £1000 minimum order value applies to all finance plans, with a maximum loan value of £50,000 and a minimum deposit of £99.00. Authorised and regulated by the Financial Conduct Authority. 5 Star Construction Services Limited, Worcester Road, Kidderminster DY10 1JR. Company Number 07576276 is a credit broker and is authorised and regulated by the Financial Conduct Authority. Credit provided by Hitachi Personal Finance, a trading style of Hitachi Capital (UK) PLC, authorised and regulated by the Financial Conduct Authority (Register no. 704348).


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Reliable and efficient Man & van service available for collection and deliveries and light Removals in Canterbury and the surrounding areas.
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On the Water
Boating, Fishing & Diving
Get on the water to make the most of your trip to Naples, Marco Island and the Everglades. Cruise Paradise Coast waterways by boat, kayak or canoe (bring your own or rent one). Spend the day catching your dinner – there's plenty of saltwater and freshwater action. No matter what you do, it's just another day in paradise.
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Tour The Glades - Private Wildlife Tours
104 Buckner Ave South
Everglades City, FL 34139
Thank you for choosing Tour The Glades, your exclusive, private tour operator in the Everglades!...More Info
Calusa Island Marina
385 Angler Dr.
Goodland, FL 34140
Full service marina in Goodland on Marco Island. Boat rentals, dry rack storage for boats to 40 feet, transient and long term wet slips for vessels t...More Info
Paddle Marco
909 Collier Ct
Paddleboard & Kayak rentals include free delivery & pickup to any home, condo or park on Marco Island....More Info
Florida Adventures and Rentals
909 Collier Ct
Marco Island, FL 34145
Florida Adventures and Rentals is a family owned company passionate about sharing the best adventures Marco Island has to offer....More Info
Jenny's Eco Everglades Wilderness Tours
32016 Tamiami Trl. E.
Everglades, FL 34139
Guided kayak and hiking wildlife eco-tours led by a former park ranger in the heart of the Everglades....More Info
Everglades National Park Gulf Coast Visitor Center
815 Oyster Bar Ln.
Everglades City, FL 34139
The Gulf Coast Visitor Center serves as the gateway for exploring the Ten Thousand Islands, a maze of mangrove islands and waterways that extends to F...More Info
Everglades Adventures
107 Camellia St. (for GPS units, use 603 Collier Ave.; destination will be on the right)
Everglades City, FL 34139
Paddle with a naturalist guide on an unforgettable journey into the amazing Florida Everglades. Glide through sun-dappled mangrove tunnels while spott...More Info
Pelican Pier Marina
1085 Bald Eagle Dr.
Marco Island, FL 34145
please contact for more informationMore Info
Caxambas Pass Park & Marina
909 Collier Ct.
Marco Island, FL 34145
Caxambas Park & Marina is a beautiful public water access point located on upscale Marco Island. The 4-acre park has ample parking, concessions fo...More Info
Rose Marina
951 Bald Eagle Dr.
Marco Island, FL 34145
Serving boaters since 1966. Rental boats, bait, and tackle. Marco Island's largest fishing and eco-tour charter boat fleet....More Info


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Humour from The Cheese Grater features satirical news articles, fake (and often libellous) interviews, funny adverts for questionable products, surreal excursions into B-List celebrities' lives, and soul-searching cartoons.
82 posts
Cringe! You kinda asked for it
This appeared in CG 65.
Students' Union under fire as emotional support dog exposes harsh treatment
Students' Union UCL has come under fire this week after reports of mistreatment from one of its recent guests. Gruffles,…
Puzzlemaster Wendy's Suko Puzzler
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In the bleak midwinter The IOE made moan The building's slowly crumbling Like an old grey stone Concrete is piling…
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This article appeared in CG Issue 64.
Smashed Avocado
Darcy Bounsall This cartoon appeared in CG Issue 64.
A sneak peak into our next issue…
This article appeared in CG Issue 64.


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Explore Gallery of Cute Medium Haircuts For Heart Shaped Faces
Showing Photo About Best and Newest Cute Medium Haircuts For Heart Shaped Faces in 26 Perfect Medium Hairstyles For Heart Shaped Faces (Updated For 2019)
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4. Poor signal can also be attributable to the radio module of the machine. Then you could have to interchange your authentic car radio player. 5. Violation of insurance coverage phrases and warranties Why to Go to Local Garages for Car Repair? Popularity of the supplier
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45 year-old Dentist Jarvis from Trout Lake, enjoys to spend some time gardening, . and home brewing. Just had a family trip to My Son Sanctuary.


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Posted 26 Days Ago
Job ID: 1604814
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December 12, 2019
Programming & Development
Database Design & Administration
This is for my dad website in Switzerland. He's having issues with his seo, would be about 7hrs per week, I m guessing for now.
Thank you
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Junior SEO - First Phase.
FixedPrice | Not SurePosted: December 08, 2019
basic insurance website
wordpress + woo + seo +react
FixedPrice | $250-$500Posted: December 08, 2019


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IMPORTANT INFO: As the intention of this event is not only to have fun, but also to raise funds to support important childhood cancer research, participants are asked to consider doing some very easy fundraising using the following link. Check it out! Due to a donation from a generous supporter which covers all of Cure4Cam's expenses, 100% of funds donated through this race will go to fund valuable childhood cancer research! http://pedal4cam.everydayhero.do


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108 MITTON Street South, Sarnia, Ontario
$170,000 - For Sale
Modern, 'Mitton Village' area, handicapped accessible office, ideal for lawyers, accountants etc. Building currently has 5 offices, a kitchenette & 2 bathrooms. Building has new roof (in last 5 yrs) & has a monitored security system. Ample on-street parking & nearby municipal parking lot. Parking at back of building is possible for a monthly fee. Price plus HST.
Property Details
- Property Address:108 MITTON Street South, Sarnia, Ontario
- Property Type:Commercial
- Lot Size:35.01 ft Frontage
- Sewage Type:Sanitary
- Water Type:Municipal
- Taxes:$3,891 (2019)
- Structure Type:Office Space
- Building Age:Unknown
- Heating Type:Forced Air, Furnace, Natural Gas
- Flooring:Carpeted,Ceramic/Porcelain
Request Information
108 MITTON Street South, Sarnia, Ontario
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Set your own price
Courses are divided into 25-mins trial lesson and 50-mins private lesson. You can have the full control to adjust your tuition fees at any stage you want.
Courses are divided into 25-mins trial lesson and 50-mins private lesson. You can have the full control to adjust your tuition fees at any stage you want.
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🌍Years of living/volunteering experience overseas. 🎓Phonics; Conversational/Travel/Business English; TOEIC/TOEFL. ✔CELTA qualified 🔥I design courses to meet your personal needs and level, come try a lesson with me! I hope to see you in class.
Born in Taiwan and raised in the United States, I am a native English speaker with an American accent. I am also fluent in Mandarin Chinese . Please wait for me to agree upon and confirm a time with you before clicking "schedule class."
Hi, this is Edes from UK and HK☺. I provide IELTS , FUN Kid's lessons and ADULT "GET YOU TO SPEAK" and Cantonese Lesson😎. No matter you want to impress your boyfriend or take IELTS, share your goals with me and we will work on it together💪💪
Hi, guys. How's it going? I'm Ally. 📫 Based in Taiwan ✅ MBA degree from the USA ✅ Travelholic (20 countries accomplished) I have more than 5 years of teaching experience. No pressure in my lesson. Talk about anything and everything. Easy peasy
• Increased confidence in speaking and listening skills. • Pronunciation techniques to reduce your accent and sound more native. • Cultural competencies like small talk, interpersonal communication, and business communication skills.
It took me years to have the courage to talk in English so i assume it wouldn't be easy for you guys.
I am studying Tesol as Master Degree in Taiwan. I have been teaching English for 3 years.
Hello! I specialize in spoken English preparing people for IELTS and Cambridge English exams using a Method called the "Callan Method" Which is an intensive, but fun way to learn English. Bringing the student up to European C2 standard.
I am a professional English Teacher with Master's Degree and over 6 years of experience. I have neutral accent so it's easier for students to understand me. I am always patient with my students and do my best to keep them smiling during the class.