text:
by Bernard Seiso Akamine
Haebaru Club
HUOA President Albert Miyasato's mention of an editorial in The Hawaii Herald in his November President's Message prompted Haebaru Club member Bernard Akamine to share this essay with Uchinanchu.
Recently I overheard an elderly nisei Yamatunchu lady telling another Yamatunchu lady, "Come to my house this weekend; I'm going to make pig's feet soup. I learned how to make it from my daughter-in-law."
How times have changed, I thought to myself. When I was growing up, we were ridiculed by our peers because we were Okinawan. We were teased, "Okinawa ken ken buta kau kau." Although I did not understand the meaning behind it, the sing-song derogatory intonation provoked feelings of hurt and anger.
Near most kitchen doors was hung a square five-gallon can with a lid into which our mothers dropped kitchen scraps and leftovers for the hog farmers to feed to their pigs. These cans were called buta kau kau (pig food) cans. Were we Okinawans being reduced to pig slop?
In my adult years I learned that the early Yamatunchu in Hawaii never ate pork, while pork was and still is an Okinawan delicacy. Another translation for "buta kau kau" is "eat pork." So, while it was true that we Okinawans ate pork, the teasing became malicious because of the double meaning of buta kau kau. Thus the seeds of cultural shame were planted for those of us of Okinawan descent.
One incident that I will never forget occurred when I was leaving Oahu for basic training in 1944. Twenty-five to 30 of us inductees were standing in box cars without roofs or seats as the train slowly made its way to the harbor. I was standing in the second row and had a good view of the passing scenery. The train made a stop in Pearl City. There was a crowd of people — mostly mothers looking for their sons. A woman carrying a furoshiki approached our box car. I knew right away she was Okinawan because of the tattoos on her fingers. My mouth watered as I imagined the delicious contents of the furoshiki and looked around me for the lucky fellow. The woman spotted her son who was standing next to me. He saw her, too, and as she called his name, instead of returning her greeting, he turned away and worked himself into the middle of the car. Suddenly, the train started to move. The woman ran after the train, yelling, "Akishamiyoo! (Oh my gosh!) Akishamiyoo!" I, being Okinawan, knew how her son felt. The nisei were already facing discrimination because they were Japanese. As Okinawans, our troubles were multiplied.
Fifty-six years later, I am proud to be Okinawan. But I often wonder if that mother and her son ever got together after the war.
Bernard Seiso Akamine is a member of Haebaru Club. He served with the 100th Infantry Battalion in Europe during World War II.


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US20040236815A1 - Three level direct communication connections between neighboring multiple context processing elements - Google PatentsThree level direct communication connections between neighboring multiple context processing elements Download PDF
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
- This application is a continuation of U.S. application number 09/364,838 entitled THREE LEVEL DIRECT COMMUNICATION CONNECTIONS BETWEEN NEIGHBORING MULTIPLE CONTEXT PROCESSING ELEMENTS, filed on Jul. 30, 1999, the contents of which is expressly incorporated by reference as though set forth in full.[0001]
- This invention relates to array based computing devices. More particularly, this invention relates to a network for configuration of multiple context processing elements. [0002]
- Advances in semiconductor technology have greatly increased the processing power of a single chip general-purpose computing device. The relatively slow increase in inter-chip communication bandwidth requires modern high performance devices to use as much of the potential on-chip processing power as possible. This results in large, dense integrated circuit devices and a large design space of processing architectures. This design space is generally viewed in terms of granularity, wherein granularity dictates that designers have the option of building very large processing units, or many smaller ones, in the same silicon area. Traditional architectures are either very coarse grain, like microprocessors, or very fine grain, like field programmable gate arrays (FPGAs). [0003]
- Microprocessors, as coarse grain architecture devices, incorporate a few large processing units that operate on wide data words, each unit being hardwired to perform a defined set of instructions on these data words. Generally, each unit is optimized for a different set of instructions, such as integer and floating point, and the units are generally hardwired to operate in parallel. The hardwired nature of these units allows for very rapid instruction execution. In fact, a great deal of area on modern microprocessor chips is dedicated to cache memories in order to support a very high rate of instruction issue. Thus, the devices efficiently handle very dynamic instruction streams. [0004]
- Most of the silicon area of modern microprocessors is dedicated to storing data and instructions and to control circuitry. Therefore, most of the silicon area is dedicated to allowing computational tasks to heavily reuse the small active portion of the silicon, the arithmetic logic units (ALUs). Consequently very little of the capacity inherent in a processor gets applied to the problem; most of the capacity goes into supporting a high diversity of operations. [0005]
- Field programmable gate arrays, as very fine grain devices, incorporate a large number of very small processing elements. These elements are arranged in a configurable interconnected network. The configuration data used to define the functionality of the processing units and the network can be thought of as a very large semantically powerful instruction word allowing nearly any operation to be described and mapped to hardware. [0006]
- Conventional FPGAs allow finer granularity control over processor operations, and dedicate a minimal area to instruction distribution. Consequently, they can deliver more computations per unit of silicon than processors, on a wide range of operations. However, the lack of resources for instruction distribution in a network of prior art conventional FPGAs make them efficient only when the functional diversity is low, that is when the same operation is required repeatedly and that entire operation can be fit spatially onto the FPGAs in the system. [0007]
- Furthermore, in prior art FPGA networks, retiming of data is often required in order to delay data. This delay is required because data that is produced by one processing element during one clock cycle may not be required by another processing element until several clock cycles after the clock cycle in which it was made available. One prior art technique for dealing with this problem is to configure some processing elements to function as memory devices to store this data. Another prior art technique configures processing elements as delay registers to be used in the FPGA network. The problem with both of these prior art technique is that valuable silicon is wasted by using processing elements as memory and delay registers. [0008]
- Dynamically programmable gate arrays (DPGAs) dedicate a modest amount of on-chip area to store additional instructions allowing them to support higher operational diversity than traditional FPGAs. However, the silicon area necessary to support this diversity must be dedicated at fabrication time and consumes area whether or not the additional diversity is required. The amount of diversity supported, that is, the number of instructions supported, is also fixed at fabrication time. Furthermore, when regular data path operations are required all instruction stores are required to be programmed with the same data using a global signal broadcast to all DPGAs. [0009]
- The limitations present in the prior art FPGA and DPGA networks in the form of limited control over configuration of the individual FPGAs and DPGAs of the network severely limits the functional diversity of the networks. For example, in one prior art FPGA network, all FPGAs must be configured at the same time to contain the same configurations. Consequently, rather than separate the resources for instruction storage and distribution from the resources for data storage and computation, and dedicate silicon resources to each of these resources at fabrication time, there is a need for an architecture that unifies these resources. Once unified, traditional instruction and control resources can be decomposed along with computing resources and can be deployed in an application specific manner. Chip capacity can be selectively deployed to dynamically support active computation or control reuse of computational resources depending on the needs of the application and the available hardware resources. [0010]
- A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level [0011] 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.
- Each multiple context processing element in a networked array of multiple context processing elements has an assigned physical identification. This physical identification may be assigned at the time of network development. Virtual identifications may also be assigned to a number of the multiple context processing elements. Data is transmitted to at least one of the multiple context processing elements of the array. The data comprises control data, configuration data, an address mask, and a destination identification. The transmitted data is also used to select whether the physical identification or the virtual identification will be used to select multiple context processing elements for manipulation. [0012]
- The transmitted address mask is applied to the physical or virtual identification and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification of a multiple context processing element matches the masked destination identification, at least one of the number of multiple context processing elements are manipulated in response to the transmitted data. Manipulation comprises programming a multiple context processing element with at least one configuration memory context and selecting a configuration memory context to control the functioning of the multiple context processing element. The manipulation may occur while the multiple context processing element is executing a present function. The manipulated multiple context processing elements define at least one region of the networked array, the region having an arbitrary shape. [0013]
- These and other features, aspects, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description and appended claims which follow.[0014]
- The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which: [0015]
- FIG. 1 is the overall chip architecture of one embodiment. This chip architecture comprises many highly integrated components. [0016]
- FIG. 2 is an eight bit MCPE core of one embodiment of the present invention. [0017]
- FIG. 3 is a data flow diagram of the MCPE of one embodiment. [0018]
- FIG. 4 is the level [0019] 1 network of one embodiment.
- FIG. 5 is the level [0020] 2 network of one embodiment.
- FIG. 6 is the level [0021] 3 network of one embodiment.
- FIG. 7 is a diagram of features of an array node of a level [0022] 3 network.
- FIG. 8 is an embodiment of a switch architecture of MCPE input switch. [0023]
- FIG. 9 illustrates a selection between eight level [0024] 3 inputs using a single input switch.
- FIG. 10 shows an encoding of configuration words for a level [0025] 3 network.
- FIG. 11 is an embodiment of an output driver of a level [0026] 3 network.
- FIG. 12 shows inputs to a multiplexor of the output driver of FIG. 11. [0027]
- FIG. 13 is a diagram of an embodiment of a configuration input selector of a level [0028] 3 network.
- FIG. 14 shows an encoding for a selection among #[0029] 3 connections and #4 connections of a level 3 network.
- FIG. 15 is the broadcast, or configuration, network used in one embodiment. [0030]
- FIG. 16 is an encoding of the configuration byte stream as received by the CNI in one embodiment. [0031]
- FIG. 17 is an encoding of the command/context byte in one embodiment. [0032]
- FIG. 18 is the MCPE configuration memory structure of one embodiment. [0033]
- FIG. 19 shows the major components of the MCPE control logic of one embodiment. [0034]
- FIG. 20 is the FSM of the MCPE controller of one embodiment.[0035]
- A unified configuration and control network for multiple context processing elements is described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the present invention. [0036]
- FIG. 1 is the overall chip architecture of one embodiment. This chip architecture comprises many highly integrated components. While prior art chip architectures fix resources at fabrication time, specifically instruction source and distribution, the chip architecture of the present invention is flexible. This architecture uses flexible instruction distribution that allows position independent configuration and control of a number of multiple context processing elements (MCPEs) resulting in superior performance provided by the MCPEs. The flexible architecture of the present invention uses local and global control to provide selective configuration and control of each MCPE in an array; the selective configuration and control occurs concurrently with present function execution in the MCPEs. [0037]
- The chip of one embodiment of the present invention is composed of, but not limited to, a 10×10 array of identical eight-bit functional units, or MCPEs [0038] 102, which are connected through a reconfigurable interconnect network. The MCPEs 102 serve as building blocks out of which a wide variety of computing structures may be created. The array size may vary between 2×2 MCPEs and 16×16 MCPEs, or even more depending upon the allowable die area and the desired performance. A perimeter network ring, or a ring of network wires and switches that surrounds the core array, provides the interconnect between the MCPEs and perimeter functional blocks.
- Surrounding the array are several specialized units that may perform functions that are too difficult or expensive to decompose into the array. These specialized units may be coupled to the array using selected MCPEs from the array. These specialized units can include large memory blocks called configurable memory blocks [0039] 104. In one embodiment these configurable memory blocks 104 comprise eight blocks, two per side, of 4 kilobyte memory blocks. Other specialized units include at least one configurable instruction decoder 106.
- Furthermore, the perimeter area holds the various interfaces that the chip of one embodiment uses to communicate with the outside world including: input/output (I/O) ports; a peripheral component interface (PCI) controller, which may be a standard 32-bit PCI interface; one or more synchronous burst static random access memory (SRAM) controllers; a programming controller that is the boot-up and master control block for the configuration network; a master clock input and phase-locked loop (PLL) control/configuration; a Joint Test Action Group (JTAG) test access port connected to all the serial scan chains on the chip; and I/O pins that are the actual pins that connect to the outside world. [0040]
- FIG. 2 is an eight bit MCPE core of one embodiment of the present invention. Primarily the MCPE core comprises memory block [0041] 210 and basic ALU core 220. The main memory block 210 is a 256 word by eight bit wide memory, which is arranged to be used in either single or dual port modes. In dual port mode the memory size is reduced to 128 words in order to be able to perform two simultaneous read operations without increasing the read latency of the memory. Network port A 222, network port B 224, ALU function port 232, control logic 214 and 234, and memory function port 212 each have configuration memories (not shown) associated with them. The configuration memories of these elements are distributed and are coupled to a Configuration Network Interface (CNI) (not shown) in one embodiment. These connections may be serial connections but are not so limited. The CNI couples all configuration memories associated with network port A 222, network port B 224, ALU function port 232, control logic 214 and 234, and memory function port 212 thereby controlling these configuration memories. The distributed configuration memory stores configuration words that control the configuration of the interconnections. The configuration memory also stores configuration information for the control architecture. Optionally it can also be a multiple context memory that receives context selecting signals broadcast globally and locally from a variety of sources.
- The structure of each MCPE allows for a great deal of flexibility when using the MCPEs to create networked processing structures. FIG. 3 is a data flow diagram of the MCPE of one embodiment. The major components of the MCPE include static random access memory (SRAM) main memory [0042] 302, ALU with multiplier and accumulate unit 304, network ports 306, and control logic 308. The solid lines mark data flow paths while the dashed lines mark control paths; all of the lines are one or more bits wide in one embodiment. There is a great deal of flexibility available within the MCPE because most of the major components may serve several different functions depending on the MCPE configuration.
- The MCPE main memory [0043] 302 is a group of 256 eight bit SRAM cells that can operate in one of four modes. It takes in up to two eight bit addresses from A and B address/data ports, depending upon the mode of operation. It also takes in up to four bytes of data, which can be from four floating ports, the B address/data port, the ALU output, or the high byte from the multiplier. The main memory 302 outputs up to four bytes of data. Two of these bytes, memory A and B, are available to the MCPE's ALU and can be directly driven onto the level 2 network. The other two bytes, memory C and D, are only available to the network. The output of the memory function port 306 controls the cycle-by-cycle operation of the memory 302 and the internal MCPE data paths as well as the operation of some parts of the ALU 304 and the control logic 308. The MCPE main memory may also be implemented as a static register file in order to save power.
- Each MCPE contains a computational unit [0044] 304 comprised of three semi-independent functional blocks. The three semi-independent functional blocks comprise an eight bit wide ALU, an 8×8 to sixteen bit multiplier, and a sixteen bit accumulator. The ALU block, in one embodiment, performs logical, shift, arithmetic, and multiplication operations, but is not so limited. The ALU function port 306 specifies the cycle-by-cycle operation of the computational unit. The computational units in orthogonally adjacent MCPEs can be chained to form wider-word data paths.
- The MCPE network ports connect the MCPE network to the internal MCPE logic (memory, ALU, and control). There are eight ports in each MCPE, each serving a different set of purposes. The eight ports comprise two address/data ports, two function ports, and four floating ports. The two address/data ports feed addresses and data into the MCPE memories and ALU. The two function ports feed instructions into the MCPE logic. The four floating ports may serve multiple functions. The determination of what function they are serving is made by the configuration of the receivers of their data. [0045]
- The MCPEs of one embodiment are the building blocks out of which more complex processing structures may be created. The structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks do join at the MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level [0046] 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 drivers and switches.
- For purposes of discussion the networks are identified as a level [0047] 1, level 2, and level 3 networks and corresponding signals transmitted thereon as first signals, second signals and third signals, respectively. However, this form of identification for purposes of discussions does not dictate the ordering of transmission of the signals.
- FIG. 4 is the level [0048] 1 network of one embodiment. The level 1 network, or bit-wide local interconnect, consists of direct point-to-point communications between each MCPE 702 and the eight nearest neighbors 704. Each MCPE 702 can output up to 12 values comprising two in each of the orthogonal directions, and one in each diagonal. The level 1 network carries bit-oriented control signals between these local groups of MCPEs. The connections of level 1 only travel one MCPE away, but the values can be routed through the level 1 switched mesh structure to other MCPEs 706. Each connection consists of a separate input and output wire. Configuration for this network is stored along with MCPE configuration.
- FIG. 5 is the level [0049] 2 network of one embodiment. The level 2 network, or byte-wide local interconnect, is used to carry data, instructions, or addresses in local groups of MCPEs 650. It is a byte-wide version of level 1 having additional connections. This level uses relatively short wires linked through a set of switches. The level 2 network is the primary means of local and semi-local MCPE communication, and level 2 does require routing. Using the level 2 network each MCPE 650 can output up to 16 values, at least two in each of the orthogonal directions and at least one in each diagonal. Each connection consists of separate input and output wires. These connections only travel one MCPE away, but the values can be routed through level 2 switches to other MCPEs. Preferably configuration for this network is also stored along with MCPE configuration.
- FIG. 6 is the level [0050] 3 network of one embodiment. In this one embodiment, the level 3 network comprises connections 852 of four channels between each pair of MCPEs 854 and 856 arranged along the major axes of the MCPE array providing for communication of data, instructions, and addresses from a single MCPE or a logical grouping of MCPEs to a periphery component or different MCPE group. In one embodiment, the data includes configuration data for the MCPEs. These connections can be byte serial or byte parallel. Communication in the level 3 network is bi-directional by nature. For example, a connection to a periphery memory requires that data be both read and written. In one embodiment, to reduce the number of physical channels required in the network and the size of the level 3 MCPE switches, the level 3 network is physically bidirectional. If the level 3 network is not bidirectional, physical up channels and down channels are required for logical read/write connections. Multiplexing onto a single bus is latency expensive, but saves on critical wire resources. In cases where parallelism is needed, two channels may be used.
- The level [0051] 3 network in the MCPE array consists of connections of four channels between each pair of MCPEs arranged along the major axes of the two dimensional mesh. In one embodiment, each connection consists of an 8-bit bidirectional port (implying tri-state drivers on the outputs) with two directional sideband bits for signaling.
- At the physical layer, the sideband bits indicate when a given direction is driving its value. Sideband bits are also interpreted by the endpoints of a given level [0052] 3 circuit to enable higher layer protocol information to be encoded. In one embodiment, a sideband bit is driven if and only if a value is currently being driven. This means that unless there is a software error, the sideband bits should never be driven in both directions simultaneously. An error signal is asserted by the driver logic if this event ever occurs dynamically.
- In one embodiment, the bidirectional data busses are named: L[0053] 3_N1, L3_N2, L3_N3, L3_N4, L3_El, etc. The sideband signals are labeled L3_N1out, etc. for upstream (outgoing) connections and L3_N1in for downstream (incoming) connections. In one embodiment, the level 3 wires, unlike level 1 and level 2 wires, are not numbered clockwise around the cell, but are numbered according to the X or Y distance from the southwest (SW) corner. This is done so that all "#1" connections connect straight through to another "#1" connection.
- In one embodiment, level [0054] 3 physical connections are capable of supporting unidirectional and bidirectional communication. Level 3 connections include 8, 16, 24 and 32 bit wide links made up of byte-wide channels. The level 3 network may be byte serial or word serial, that is, words may be sequentialized down a byte-wide channel or sent down a word-wide channel.
- In one embodiment, logical connections between two level [0055] 3 nodes may be characterized as static and unidirectional, as asynchronous and unidirectional or as asynchronous and directional.
- In the case of static unidirectional connections, the network channel is always moving data in a single direction to an endpoint that has information (acquired at compile time) regarding what to do with the data. Latency and a data stream structure is predetermined. [0056]
- In the case of asynchronous unidirectional connections, the network starts in a "ready to send" state and the data is intended to move in one direction (single value, packet or full stream). The receiving endpoint then sends a "go ahead" signal which starts the transfer. The data arrives either a known or unknown number of cycles later, depending upon endpoint configuration. When the number of cycles is unknown, a sideband bit indicates valid data. If the local unit cannot directly respond to the sideband bit, the local unit may remain in a halt state until the bit arrives. When the number of cycles is known, the execution unit may be scheduled unless execution starts on receipt of data (that is, unless a data driven architecture has been defined in software). The connection is pre-configured by a software construct not pertinent to the present invention. [0057]
- In the case of asynchronous directional transfer, the destination node sends a packet of data to the source. A control bit remains asserted as long as the data sent remains valid. The source port receives the packet of data and interprets it as data, control information or as an identification address that tells the port if it is the port asked to return data. The source port determines whether it is the port asked to return data by interpreting additional control or target address words. The source port then returns a packet or stream of data in response to the received packet. The initiator has control of the logical network connection. [0058]
- In one embodiment, the level [0059] 3 network is dynamically routable, which supports position independence of hardware modules. Configuration of a dynamically routable level 3 network is separate from the main MCPE configuration. A connection between two endpoints through a series of level 3 array and periphery nodes is called a "circuit" and may be set up and taken down by the configuration network. In one embodiment, each connection 852 consists of an 8-bit bidirectional port.
- The MCPE node connects to [0060] 16 busses, four in each cardinal direction. Each bus is associated with an output driver. Selected subsets of the incoming busses are fed to a set of four switches. The major features of an array node are illustrated in FIG. 7. The level 3 configuration input selector 1102 receives downstream signals 1122 and data 1124 and outputs configuration data to the CNI. The level 3 routing switches 1104 receive downstream signals 1122 and data 1124 and send outputs to the input ports and to the control reduce input. Data 1124 may also be output from level 3 routing switches 1104. The L3 output selectors 1106 receive signals from the floating ports, memories A, B, C, and D, and the ALU, and output signals to the output drivers 1128. The control reduce input is connected to output drivers 1128. Level 3 output drivers 1128 output upstream signals 1126 and data 1124. Level 3 output drivers 1128 also receive data 1124.
- The level [0061] 3 routing switches 1104 provide limited connectivity between routing tracks in the horizontal and vertical directions as well as 'capture'values that can be fed into the MCPE input ports. The drivers on each side select the value to drive onto the level 3 busses, a set of four MCPE output selectors and inputs from the opposite side.
- Two of the "tracks" in each direction (tracks #[0062] 3 and #4) provide inputs to the configuration network for configuring the MCPE. Debugging readout is supported by replacing one of the MCPE Mem inputs to the #4 output selector switch with configuration data and configuring the level 3 nodes to create a circuit to the appropriate output port.
- There are four level [0063] 3 routing switches in each MCPE, each one associated with one of the four level 3 connections on each side of the MCPE. One embodiment of a routing switch architecture is shown in FIG. 8. The level 3 routing switch 1200 includes a single switch which selects between eight level 3 inputs, as shown in FIG. 9. L3_SW1 takes its input from W1, W2, N1, N2, E1, E2, S1, and S2, while L3_SW2 takes its input from W2, W3, N2, N3, E2, E3, S2, and S3, etc. This pattern allows the signals on the level 3 wires to change "tracks".
- In one embodiment, the switch [0064] 1200 outputs 8 bits of data, in addition to the associated downstream (incoming) sideband signal. These four outputs are fed into the MCPE input ports and to the four output drivers associated with the inputs of the switch (L3_SW1 outputs to W1, N1, E1, S1, while L3_SW2 outputs to W2, N2, E2, S2, etc.).
- The input selection is made by two configuration words which control multiplexor [0065] 1210: L3sw*13 def (Default Selection) and L3sw*_rev (Reverse Selection). The first, default selection is the normal mode. The reverse selection is used when an level 3 connection "turns around". This occurs when the default direction sideband bit, which is selected by the multiplexor 1202, is low, while the sideband bit in the reverse direction, which is selected by the multiplexor 1204, is high and the 13sw*_reven (reverse enable) configuration bit is high. In all other cases, the switch selection is performed by the default configuration.
- The selection logic also produces eight bits of "driver flags". One bit is sent to each driver associated with the switch's input. Each bit is set to zero unless the switch is currently using that line's input, in which case the bit is set to one. The drivers use this bit to determine whether or not the connection is being "turned around". [0066]
- The configuration select logic [0067] 1206 also produces an error flag when both selected sideband bits are high. This signal is propagated to an output pin of the chip so that the external system can determine that an error has occurred. In addition, the flag sets a register that is part of the global debugging scan chain so that the location of the error can be determined. The error flag does not stop the operation of the chip in any way.
- In one embodiment, there are four MCPE output selectors in each MCPE, labeled L[0068] 3out1, L3out2, L3out3, and L3out4. In one embodiment, each MCPE output selector is a 4-input, 1-output, 8-bit-wide multiplexor. The output selectors take the floating port outputs and direct outputs of the MCPE and select four busses (memory, ALU, accumulator high byte) which are fed into the level 3 drivers. The output selectors are controlled by the two-bit configuration words L3outl-sel, L3out2-sel, L3out3-sel, and L3out4-sel. One encoding of these words is shown in FIG. 10.
- In one embodiment, there are 16 level [0069] 3 output drivers in each MCPE, one for each level 3 line. FIG. 11 shows the architecture of one embodiment of an output driver. The main data path consists of a single selector multiplexor 1302 and a register 1312. The inputs to the multiplexor 1302 are different for each driver. The inputs to the multiplexor 1302 are shown in FIG. 12. The register 1312 is selected when the configuration bit "regen" is set high. The selection of which input is output is made by the four incoming sideband bits 1316.
- The four incoming sideband bits [0070] 1316 are bit-wise ANDed with the inversion of the driver flags from the switches and a configuration mask by logic 1306. Logic 1306 outputs a result to the decoder 1304 and to OR gate 1308. The result is used to select which inputs to a driver are allowed to drive. If the mask is all zeros, the driver will never drive. Also, if a driver flag goes high, the input of the switch that generated the flag will be ignored.
- The resulting four bits are used in a one-hot encoding of the input selector. If more than one bit is high at the same time, the decoder outputs an error flag [0071] 1322 and the Data 0 input is selected. This selection mechanism allows a level 3 connection that has multiple receivers to be "turned around" by one of them.
- If any of the masked sideband bits is high, then the driver assumes that it is driving. This bit is sent out as the upstream sideband bit [0072] 1324. The drive logic block 1326 checks to see if the downstream block is also asserted using downstream sideband bit 1320. If it is, the drive logic does not enable the output driver and also asserts the error flag 1322. Otherwise, the output driver is enabled. Error flag 1322 functions in the same way as error flags in the switches.
- In one embodiment, the L[0073] 3out4 selector has a special function during configuration reads When a read operation is initiated, the MCPE's CNI block will switch the MemD input to L3out4 to its own configuration output. It will also replace the reduce control[4] sideband bit with its own sideband output. L3out4 and the output drivers must be properly configured in order for this data to be sent out on the network; the CNI does not change the network settings in this mode.
- In one embodiment, the configuration input selector is a special level [0074] 3 switch that is used only to input configuration data into the MCPE's CNI. FIG. 13 shows an architecture of a configuration input selector 1400. Configuration input selector 1400 includes two multiplexors 1402 and 1404 that use a single configuration word to select from the incoming #3 and #4 connections. Two words are sent to the CNI, which chooses one of them. FIG. 14 shows an encoding for a selection among #3 connections and #4 connections.
- In one embodiment, each MCPE has a single register that will set to one whenever any of the error flags in the MCPE go high for a full cycle. The register is visible on the scan chain of the chip and provides external visibility to the level [0075] 3 error flags. The register will remain set until a full chip reset occurs. In one embodiment, there are a total of 20 error flags in the MCPE: 16 level 3 driver error flags and four level 3 switch error flags.
- FIG. 15 is the broadcast, or configuration, network used in one embodiment. This broadcast network is an H-tree network structure with a single source and multiple receivers in which individual MCPEs [0076] 1002 may be written to. In one embodiment, the broadcast network is the mechanism by which configuration data for the level 3 network drivers and switches is communicated, while the level 3 network is the mechanism by which the MCPEs are configured. In other embodiments, the broadcast network is the mechanism by which both the MCPEs and the perimeter units are configured programmed.
- The broadcast network in one embodiment comprises a nine bit broadcast channel that is structured to both program and control the on-chip MCPE [0077] 1002 configuration memories. The broadcast network comprises a central source, or Configuration Network Source (CNS) 1004, and one Configuration Network Interface (CNI) block 1006 for each major component, or one in each MCPE with others assigned to individual or groups of non-MCPE blocks. The CN11006 comprises a hardwired finite state machine, several state registers, and an eight bit loadable clearable counter used to maintain timing. The CNS 1004 broadcasts to the CNIs 1006 on the chip according to a specific protocol. The network is arranged so that the CNIs 1006 of one embodiment receive the broadcast within the same clock cycle. This allows the broadcast network to be used as a global synchronization mechanism as it has a fixed latency to all parts of the chip. Therefore, the broadcast network functions primarily to program the level 3 network, and to prepare receiving CNIs for configuration transactions. Typically, the bulk of configuration data is carried over the level 3 network, however the broadcast network can also perform that function. The broadcast network has overriding authority over any other programmable action on the chip.
- A CNI block is the receiving end of the broadcast network. Each CNI has two addresses: a physical, hardwired address and a virtual, programmable address. The latter can be used with a broadcast mask that allows multiple CNIs to receive the same control and programming signals. A single CNI is associated with each MCPE in the networked MCPE array. This CNI controls the reading and writing of the configuration of the MCPE contexts, the MCPE main memory, and the MCPE configuration controller. [0078]
- The CNS [0079] 1004 broadcasts a data stream to the CNIs 1006 that comprises the data necessary to configure the MCPEs 1002. In one embodiment, this data comprises configuration data, address mask data, and destination identification data. FIG. 16 is the encoding of the configuration byte stream as received by the CNI in one embodiment. The first four bytes are a combination of mask and address where both mask and address are 15 bit values. The address bits are only tested when the corresponding mask is set to "1". The high bit of the Address High Byte is a Virtual/Physical identification selection. When set to "1", the masked address is compared to the MCPE virtual, or programmable, identification; when set to "0" the masked address is compared to the MCPE physical address. This address scheme applies to a CNI block whether or not it is in an MCPE.
- Following the masked address is a command/context byte which specifies which memory will be read from or written to by the byte stream. FIG. 17 is the encoding of the command/context byte in one embodiment. Following the command/context byte is a byte count value. The byte count indicates the number of bytes that will follow. [0080]
- FIG. 18 is the MCPE configuration memory structure of one embodiment. Each MCPE has four major contexts [0081] 402-408 of configuration memory. Each context contains a complete set of data to fully describe the operation of the MCPE, including the local network switching. In one embodiment two of the contexts are hardwired and two are programmable. Each of these contexts includes two independently writeable minor contexts. In the programmable major contexts the minor contexts are a duplication of part of the MCPE configuration consisting primarily of the port configurations. In the hardwired major contexts the minor contexts may change more than just the port configurations. The switching of these minor contexts is also controlled by the configuration control. The minor contexts are identical in structure but contain different run-time configurations. This allows a greater degree of configuration flexibility because it is possible to dynamically swap some parts of the configuration without requiring memories to store extra major contexts. These minor contexts allow extra flexibility for important parts of the configuration while saving the extra memory available for those parts that don't need to be as flexible. A configuration controller 410 finite state machine (FSM) determines which context is active on each cycle. Furthermore, a global configuration network can force the FSM to change contexts.
- The first two major contexts ([0082] 0 and 1) may be hardwired, or set during the design of the chip, although they are not so limited. Major context 0 is a reset state that serves two primary roles depending on the minor context. Major context 1 is a local stall mode. When a MCPE is placed into major context 1 it continues to use the configuration setting of the last non-context 1 cycle and all internal registers are frozen. This mode allows running programs to stall as a freeze state in which no operations occur but allows programming and scan chain readout, for debugging, to occur.
- Minor context [0083] 0 is a clear mode. Minor context 0 resets all MCPE registers to zero, and serves as the primary reset mode of the chip. Minor context 0 also freezes the MCPE but leaves the main memory active to be read and written over by the configuration network.
- Minor context [0084] 1 is a freeze mode. In this mode the internal MCPE registers are frozen while holding their last stored value; this includes the finite state machine state register. This mode can be used as a way to turn off MCPE's that are not in use or as a reset state. Minor context 1 is useful to avoid unnecessary power consumption in unused MCPEs because the memory enable is turned off during this mode.
- Major contexts [0085] 2 and 3 are programmable contexts for user defined operations. In addition to the four major contexts the MCPE contains some configurations that do not switch under the control of the configuration controller. These include the MCPE's identification number and the configuration for the controller itself.
- FIG. 19 shows the major components of the MCPE control logic structure of one embodiment. The Control Tester [0086] 602 takes the output of the ALU for two bytes from floating ports 604 and 606, plus the left and right carryout bits, and performs a configurable test on them. The result is one bit indicating that the comparison matched. This bit is referred to as the control bit. This Control Tester serves two main purposes. First it acts as a programmable condition code generator testing the ALU output for any condition that the application needs to test for. Secondly, since these control bits can be grouped and sent out across the level 2 and 3 networks, this unit can be used to perform a second or later stage reduction on a set of control bits/data generated by other MCPE's.
- The level [0087] 1 network 608 carries the control bits. As previously discussed, the level 1 network 608 consists of direct point-to-point communications between every MCPE and it's 12 nearest neighbors. Thus, each MCPE will receive 13 control bits (12 neighbors and it's own) from the level 1 network. These 13 control bits are fed into the Control Reduce block 610 and the MCPE input ports 612. The Control Reduce block 610 allows the control information to rapidly effect neighboring MCPEs. The MCPE input ports allow the application to send the control data across the normal network wires so they can cover long distances. In addition the control bits can be fed into MCPEs so they can be manipulated as normal data.
- The Control Reduce block [0088] 610 performs a simple selection on either the control words coming from the level 1 control network, the level 3 network, or two of the floating ports. The selection control is part of the MCPE configuration. The Control Reduce block 610 selection results in the output of five bits. Two of the output bits are fed into the MCPE configuration controller 614. One output bit is made available to the level 1 network, and one output bit is made available to the level 3 network.
- The MCPE configuration controller [0089] 614 selects on a cycle-by-cycle basis which context, major or minor, will control the MCPE's activities. The controller consists of a finite state machine (FSM) that is an active controller and not just a lookup table. The FSM allows a combination of local and global control over time that changes. This means that an application may run for a period based on the local control of the FSM while receiving global control signals that reconfigure the MCPE, or a block of MCPEs, to perform different functions during the next clock cycle. The FSM provides for local configuration and control by locally maintaining a current configuration context for control of the MCPE. The FSM provides for global configuration and control by providing the ability to multiplex and change between different configuration contexts of the MCPE on each different clock cycle in response to signals broadcast over a network. This configuration and control of the MCPE is powerful because it allows an MCPE to maintain control during each clock cycle based on a locally maintained configuration context while providing for concurrent global on-the-fly reconfiguration of each MCPE. This architecture significantly changes the area impact and characterization of an MCPE array while increasing the efficiency of the array without wasting other MCPEs to perform the configuration and control functions.
- FIG. 20 is the FSM of the MCPE configuration controller of one embodiment. In controlling the functioning of the MCPE, control information [0090] 2004 is received by the FSM 2002 in the form of state information from at least one surrounding MCPE in the networked array. This control information is in the form of two bits received from the Control Reduce block of the MCPE control logic structure. In one embodiment, the FSM also has three state bits that directly control the major and minor configuration contexts for the particular MCPE. The FSM maintains the data of the current MCPE configuration by using a feedback path 2006 to feed back the current configuration state of the MCPE of the most recent clock cycle. The feedback path 2006 is not limited to a single path. The FSM selects one of the available configuration memory contexts for use by the corresponding MCPE during the next clock cycle in response to the received state information from the surrounding MCPEs and the current configuration data. This selection is output from the FSM in the form of a configuration control signal 2008. The selection of a configuration memory context for use during the next clock cycle occurs, in one embodiment, during the execution of the configuration memory context selected for the current clock cycle.
- The present invention has been described with reference to specific exemplary embodiments. Various modifications and changes may be made to these embodiments by one of ordinary skill in the art without departing from the broader spirit and scope of the invention as set forth in the following claims. [0091]
Claims (28)
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text:
Warning on Jerky Treats from the FDA
The Food and Drug Administration issued an alert to consumers this week about the illnesses and deaths tied to jerky treats from China. Nearly 600 pets have died and over 3,600 have reported illness after eating chicken, duck and sweet potato jerky treats. The biggest problem is they cannot figure out the cause when testing contaminants.
Rest assured, we've researched our food and treat sources and we do not carry these treats or any treats made in China for that matter. But we know that many pups just love those jerky treats, so we sniffed out the best alternative made right here in the USA.
Bixby Jerky treats are available in a delicious chicken flavor and they have 2 healthy formulas: Hip and Joint or Skin and Coat. Both are free of wheat, corn, soy, preservatives and animal byproducts.
Also a Chicken jerky treat, Tuckers, is an all-natural, grain-free, gluten-free treat that is hand rolled in Wisconsin using chicken breast sourced in the United States and Canada. They are even produced under USDA oversight from 100% human grade raw ingredients, so you know they are safe for your pup!
Another taste-tester favorite are Primal Dry Roasted Chicken Shredders. Made with chicken raised in the United States without antibiotics or added hormones, these treats are a healthy, high-protein snack.
And for those sweet potato lovers, we have these delicious Sweet Potato treats. Not only do dogs love them, but they have a pro-biotic coating promotes a healthy gastrointestinal tract in support of your dog`s digestive system.
Whatever you choose to treat your pet, know that you are safe with us! Come by and see us for a taste test sometime!


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We're only a day away from the 15th annual Classic in the Country Challenge in Berlin, Ohio. As you prepare to brace yourself for the pending snow storm that is heading to our area this weekend, snuggle up in a warm blanket and listen to our latest podcast.
One guy who knows his stuff when it comes to high school girls basketball in Northeast Ohio is HOFHuddle.com director and founder Rich Harland. Harland joins Dave Mast and me on this week's podcast to preview teams, players and must-watch matchups in Berlin this weekend at the 2018 Classic in the Country Challenge. Rich also gives us an update on his activities with Hall of Fame Huddle. You can follow Rich Harland on Twitter (@HOFHuddle_Rich).
For more info and how to find tickets for the 2018 Classic in the Country Challenge, the high school girls basketball showcase held at Hiland High School's Perry Reese, Jr. Community Center in Berlin, Ohio, Jan. 13, 14 and 15, go to www.classicinthecountry.org or stay tuned to OhioSportsTicket.com to enjoy our photos, highlights and post-game coverage. With 28 teams featured in 20 games over three days, it is sure to be entertaining.


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[button link="https://www.painted-ladies.com/new-ftc-guidelines-what-this-means-for-painted-ladies/" target="_blank" rel="nofollow color="PL"]Press Sample[/button]
When it comes to beauty must-haves, good looking eyebrows are definitely part of that list. Paula Dorf 2 + 1 For Brows makes having good eyebrows easy, and today I'm going to share an easy guide to grooming your brows.
Since the beginning of my journey as a beauty lover, I've known and used the Paula Dorf brand, knowing it to be high quality makeup that delivers. I've always liked the Paula Dorf products that transform your makeup and help you multi-task with ease.
What I really like about Paula Dorf 2 + 1 For Brows is that it allows you to completely customize your brow color.
This trio, which comes in four different shades, contains a wax along with two brow shades that you can mix and match as you wish. To use the product, mix the powders as desired, then dip your angled brush in to the wax before applying to your brows.
The slightly OCD side of me dislikes changing the color of the wax, but the beauty lover side of me knows it's for the good cause of well-groomed eyebrows.
Here's my easy guide and a video tutorial to creating beautifully groomed brows with Paula Dorf 2 + 1 For Brows in Brunette and Paula Dorf Perfect Brow Brush.
Step 1: Using a spoolie, brush your brows in an upward direction.
Step 2: Using an angled brush that has the product placed on it, I line the underneath of my brows. Some also line the top of their brows, but in my case I prefer just lining the underneath. Use a light hand with your brush when creating the line.
Step 3: Brush the remainder of the brow product throughout your brows to fill in sparse areas.
Step 4: Run the spoolie through your brows one more time to make sure the product is blended.
And you're done!
Just 4 easy steps to creating naturally beautiful, filled in eyebrows that will last all day. Thanks, Paula Dorf! Check out my video where I show you how I use Paula Dorf 2 + 1 Brows.
My Final Thoughts: Paula Dorf 2 + 1 For Brows in Brunette is a new favorite and I'm glad to have it in my makeup kit to create natural, filled-in brows that are perfectly groomed.
Rating: A
Price: $26, use code BROWBRUSH at checkout to receive a FREE Paula Dorf Perfect Brow Brush
Availability: www.pauladorf.com
Cruelty-free? Yes
Paraben-free? No
Gluten-free? Contains Tocopheryl Acetate
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Cory Briggs' real estate
Brian Maienschein, now a friend to big labor
Matt Potter 12:30 p.m., Dec. 11
On Halloween night at around 8 p.m. at the Ocean Beach Farmers' Market, Todo Mundo was performing in the street. A lot of people were wearing costumes, dancing, and enjoying the beautiful music and weather.
Todo Mundo was playing their last song when all of a sudden someone in a zombie costume reached over and grabbed the money that had been collected for the band from a box right in front of the band.
The thief took off running up the middle of the street like a sprinter. Most everyone in the crowd who'd been watching the band saw the brazen act occur. Everybody who saw went wild; even the drummer and singer stopped playing to chase the thief. He was caught and beat up and the money was returned to the kitty.
Note: Though there was a police presence in the area, I didn't witness the thief being taken into custody.
Did anyone call the police and have him arrested??
he got "old fashioned justice"...


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Pond & Water Feature Installation, Maintenance, Repair, & Renovations
Middlebury, IN (Serving Northern Indiana, Michiana Area)
Premiere Aquascapes (reviews)
Middlebury, Elkhart County, Indiana (IN) 46540
CONTACT US Or CALL 574.202.1636
PRIMARY SERVICES AREAS- Northern Indiana, Michiana Area
*Certified Aquascape Contractor
Premiere Aquascapes is a water feature and landscape installation company based out of Middlebury Indiana. We specialize in custom pond and waterfall installation as well as patios, pathways, and outdoor living spaces that surround them.
Wayne Miller started the company in 2011 to bring to life the vision he had; to be able to bring all the joys, sights, and sounds, of water and nature, to his customers in the Michiana area.
The mission statement at Premiere Aquascapes is "Enriching Lives by serving our customers with the highest quality service, integrity and respect".
Our staff will always greet you in a respectful and professional manner and answer any questions or concerns that you might have. All members of our staff attend specialized training sessions throughout each and every year on all types of water features, construction & maintenance. To learn the most innovative techniques and tips from other top professionals in the water feature industry.
Premiere Aquascapes
Informational Links On The Web
P.O.N.D.S. Links
Premiere Aquascapes
Premiere - IN - PCS Services
Fish Ponds
Pondless Waterfalls
Bubbling Fountains
Pond Lifestyle
Service Areas Include Northern Indiana, Michiana Area
Contact us if you don't see your town listed.
Elkhart, Goshen, Bristol, Middlebury, Simonton Lake, Dunlap, Wakarusa, New Paris Benton, Millersburg, Nappanee, South Bend, Mishawaka, Granger, Georgetown, Osceola, New Carlisle, North Liberty, Walkerton, Lakeville, LaPorte, Michigan City, Westville, Rolling Praire, Union Mills, Wanatah, Mill Creek, LaCrosse, Hanna, Kingsford Heights, Michiana Shores, Shipshewana, Topeka, Howe, Lagrange, Wolcottville, Warsaw, Winona Lake, Silver Lake, Syracuse, Pierceton, North Webster, Milford, Leesburg, Claypool, Etna Green, Albion, Kendallville, Avilla, Cromwell, Ligonier, Rome City, Columbia City, Churubusco, Larwill, South Whitley, Fort Wayne, Grabill, Huntertown, Leo, Monroeville, New Haven, Spencerville, Woodburn plus Roanoke & Auburn


text: This 87-foot luxury yacht has three decks packed with leisure and entertainment space. Custom-built in 2013 by Ferretti, the Hot Mess sleeps eight guests surrounded by luxury and relaxation. Take the jet ski out for a spin, sunbathe on the tanning deck, and admire twilight views of Miami from the top deck hot tub.


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WASHINGTON, Sept. 28 - His last book, "State of Fear," was published more than nine months ago, but the reviews were still pouring in on Wednesday, even as Michael Crichton folded his 6-foot-9-inch frame into a seat to testify before the Senate Committee on Environment and Public Works.
"More silly than scary," the flier dropped off by the Natural Resources Defense Council said.
"Notable mainly for its nuttiness," an analysis from the Brookings Institution said.
"Does not reflect scientific fact," the Union of Concerned Scientists said.
For all his previous works as a writer (13 novels, 4 nonfiction books, numerous screenplays) and his prominent career in Hollywood as a writer, producer or director of 13 films and as the creator of the popular television series "ER," little has yanked Mr. Crichton so deeply into political controversy as "State of Fear," an environmental thriller that casts doubt on the widely held notion that human activities contribute to global warming.
It has become a hugely divisive policy issue in recent years, gaining a new urgency, perhaps, by the recent hurricanes that slammed into the Gulf Coast. Many prominent scientists, no friends of Mr. Crichton, to be sure, believe that man-made greenhouse gases are causing the earth to warm and are urging lawmakers to pass new regulations that govern carbon dioxide emissions.
But after considerable study of his own, leading to "State of Fear," Mr. Crichton has concluded that the science is mixed at best, and that lawmakers should take that into consideration when they decide what they might do about it.
His is an unpopular and contrary stance when measured against the judgment of groups like the National Academy of Sciences. But it was not those organizations that asked Mr. Crichton to Washington to counsel Congress on how to consider diverse scientific opinion when making policy. It was the committee chairman, Senator James M. Inhofe, a plainspoken Oklahoma Republican who has unabashedly pronounced global warming "the greatest hoax ever perpetrated on the American people."
In Mr. Crichton, a Harvard medical school graduate who never practiced medicine, he had found a kindred spirit -- and a star witness for his committee.
"I'm excited about this hearing," Mr. Inhofe said, nodding toward Mr. Crichton as the proceedings began. "I think I've read most of his books; I think I've read them all. I enjoyed most 'State of Fear' and made it required reading for this committee."
Over the next two hours, Mr. Crichton and four other witnesses offered their thoughts, Mr. Crichton hewing to his firm belief that lawmakers should examine more closely "whether the methodology of climate science is sufficiently rigorous to yield a reliable result."
He took notes. He raised his hand to make points. He responded to criticism evenly and never lost composure. But it seemed like a lot less fun than winning an Emmy, as he did for "ER," or a citation as one of the "50 Most Beautiful People," as People magazine ranked him in 1992. And all he could do was sit there quietly, as Senator Hillary Rodham Clinton scolded him for views that "muddy the issues around sound science" and Senator Barbara Boxer said, "I think we have to focus on facts, not fiction."
In an interview later, Mr. Crichton said with a pained expression: "Comfortable with this? "I'm very uncomfortable. Who wants this?"
Several of his previous books led to national debates and criticism, he said, recalling "Rising Sun," a murder mystery that suggests that Japan is economically devouring the United States, and "Disclosure," which examines sexual harassment when a woman is the predator. Both became popular movies.
"But this has been worse," he said of the aftermath of "State of Fear."
Still, he retains enough of his scientific background to thrust himself into the debate, insisting that the environmental movement "did a fabulous job in the first 10 years, a pretty good job in the second 10 years and a lousy job in the last 10 years."
As a result, he said, its influence on policy needs to be reined in, at least until alternative views are given equal airing and fair consideration by independent reviewers. Only then, he said, can policy makers make informed decisions.
But he never figured that he would be offering lawmakers an opinion on how they should legislate. His years of writing have taken on a pattern, he said. Research. Write. Move on.
"When I'm finished, I'm done," he said. Except when he's not, which is the case with "State of Fear." But that may not be true for his next book, which is almost complete. "It's extremely uncontroversial," he said, offering no details.
And even though the global warming debate endures, it's not likely that "State of Fear" will, beyond the book. "No studio has optioned it," he said, insisting: "It'll never be made. It's way too red hot."


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Rich Brilliant Willing
Rich Brilliant Willing is America's premier contemporary lighting and furniture design manufacturer. From their Manhattan studio workshop, RBW's creative team oversees every aspect of their unique process, from design to assembly to distribution.
The results are intelligent and iconic; simple yet expressive products that bring out the very best in new living and work environments. In 2011, Rich Brilliant and Willing was awarded an International Contemporary Furniture Fair 'Best New Designer' award and Forbes Magazine's "30 under 30" working in Art & Design.


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Kevin Beaulieu
Computer Science & Philosophy
Columbus, Ohio
What is your main extracurricular activity? Why is it important to you?
I have found reading to be quite a rewarding pastime when I have a break between homeworks and projects. Changes in the trajectory of my life have often been inspired by or accompanied by ideas and subjects I came into contact with through books. I typically read non-fiction, recently primarily in the veins of Zen, physics, and metaphysics. When going about my day, my mind is frequently mulling over, considering and reconsidering ideas in these fields; reading gives me a constant source of new ideas, novel arguments, and different positions to consider as I form my view of the world.
What was your most profound turning point while at Cornell?
There was a moment during the summer between sophomore and junior years, while interning in San Francisco, when I just thought to myself, "I've made it." My whole life up until that point I'd been working hard so that one day I might be able to make a career out of doing what I love, but all of a sudden I realized I was already doing it. It wasn't that I didn't have any goals left for myself, but a sensation that regardless of what the future held, everything would be okay. More than okay. So, having reached this stage, I could stop and consider where I wanted to go next. I think it's important to ask oneself, "If I could do anything in the world, without concern for what obstacles might seem to be in the way of my getting there, what would I do?" It can be easy to cruise through life only ever looking to the short-term, but when you become truly thoughtful about the long-term, you can make extraordinary things happen.
Who or what influenced your Cornell education the most? How or why?
More than any single individual, my greatest influence has been the culture of striving for greatness in everything Cornellians do. I am continually amazed by how normal/routine people here make it seem to do world-class research. For every accomplishment one makes, there is always someone who will take it one step further. Rather than turning campus into a competitive warzone, though, it has the effect of bolstering collaboration and encouragement throughout the community, motivating everyone to continually improve both themselves and the world around them.
What do you value about your liberal arts education?
I think many young STEM (science, technology, engineering, & mathematics) students encounter a choice between two paths of study: diving full-on into their technical discipline or allocating some time to pursue other, perhaps completely unrelated, fields as well. My decision to come to Cornell was largely based on an affinity for the latter option, and I am more than satisfied with that choice. That is not to say one or the other strategy is better; it's simply a matter of which is right for the individual. During the past four years, I have cherished the opportunity to take courses in a number of disciplines. A liberal arts education has given me a variety of perspectives to consider, and the chance to examine the unique questions posed at the intersection of many disciplines.
What are your plans for next year; where do you see yourself in 10 years?
I'll be moving out to San Francisco after graduation to work as a software engineer for Thumbtack, a growing tech company that aims to simplify the process of hiring local professionals and services. I spent the last two summers interning at Thumbtack, so now I'll get the chance to really sink my teeth into the Thumbtack ecosystem and help it as it expands with an ever-increasing energy. If you asked me 10 years ago where I'd be now, I could never have imagined the adventures I've been on, the things I've accomplished, and the people I've had the immense pleasure of getting to know. My life has honestly surpassed my wildest dreams over the past 4 years. So with that in mind, I really have no idea where I'll be in 10 years, but I know it'll be exactly where I need to be at that point in my life. Time is curious in that way; looking back, our current state seems almost inevitable, but looking forward, the future is unknown.


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In an article published Monday by The New Yorker, multiple women who had relationships with Eric T. Schneiderman, the New York attorney general, accused him of physically assaulting them.
Almost immediately after the article was published, calls for Mr. Schneiderman to resign came pouring in from officials, including Gov. Andrew M. Cuomo.
Mr. Schneiderman, 63, has contested the allegations in statements. Still, late on Monday, he announced his resignation.
Here is a look at Mr. Schneiderman's career, including his yearslong defense of women and his rise to prominence as a foil to the Trump administration.
[Read our article about the accusations.]
How he climbed the ladder
Mr. Schneiderman graduated from Amherst College in 1977 and Harvard Law School in 1982, and was a deputy sheriff in Massachusetts in between.
As a public interest lawyer, Mr. Schneiderman represented women seeking access to health clinics, sometimes suing protesters who he said harassed the women outside of the clinics. Along the way, he expressed support for codifying the Roe v. Wade decision into state law.
Mr. Schneiderman also spent 15 years in private practice before leaving to begin a successful campaign for the State Senate. He was elected in 1998 and seated the next year.
On Nov. 2, 2010, he was elected as the 65th attorney general of New York, making him the chief law enforcement officer of the state. He had been up for re-election this year.
Taking on Trump
Mr. Schneiderman was widely seen as harboring ambitions to be governor. He styled himself as a political outsider.
"Where Washington D.C. has failed to lead on the issues that matter, Eric has made clear that New York will provide a road map for the rest of the country," his biography on the attorney general's office website says.
He had also raised his profile nationally in the last year by repeatedly taking on President Trump's agenda in the courts. (Mr. Trump himself has been accused of sexual misconduct, though he has denied the allegations.)
Even before Mr. Trump took office, Mr. Schneiderman had filed a lawsuit against Trump University. And more recently, he had been pushing to change state law so his office could prosecute Mr. Trump's aides if the president pardons them.
"We must ensure that if the president, or any president, issues such pardons, we can use the full force of New York's laws to bring such individuals to justice," Mr. Schneiderman said last month.
Other actions Mr. Schneiderman has taken in opposition to Mr. Trump include a lawsuit filed to block the president's travel ban and a vow to defend the rights of sanctuary cities in his state.
Last June, Mr. Schneiderman helped introduce a bill last year in the State Legislature for cost-free contraception, similar to legislation he had called for in the previous year. But he said last year in an interview that he introduced it again because Mr. Trump's election increased his sense of urgency.
What he has said about women
Mr. Schneiderman had been outspoken about women's issues throughout his career.
In 2010, while he was still a state senator from Manhattan, he introduced a bill to make intentional strangulation to the point of unconsciousness a violent felony. That same year, the National Organization for Women's New York branch endorsed him in his successful bid for attorney general, citing his "unmatched work" in "protecting women who are victims of domestic abuse."
While Mr. Schneiderman was attorney general, his office, for several years, published a "Know Your Rights" brochure for victims of domestic violence.
"We must recognize that our work keeping New Yorkers safe from domestic violence is far from over," Mr. Schneiderman said in the announcement for the 2016 brochure.
Recently, he pushed himself to the forefront of the #MeToo movement, announcing a lawsuit against the company once run by the former filmmaker Harvey Weinstein, who was accused of decades of sexual misconduct.
"We have never seen anything as despicable as what we've seen right here," Mr. Schneiderman said at the time.
At the direction of Governor Cuomo, he was also reviewing the 2015 decision by the Manhattan district attorney, Cyrus R. Vance Jr., not to prosecute Mr. Weinstein after an Italian model accused him of groping her.
[Read more of Eric Schneiderman's own words in defense of women's rights.]


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THE Greens are promising to double Fremantle's tree canopy by 2040 under an "urban forest" plan.
Freo council has already adopted a policy to increase the dire coverage of trees over barren streets, but Greens WA senator Scott Ludlam reckons the issue is so serious it needs federal attention.
Perth's lost 75 per cent of its bushland and about a third of what's left is at risk.
The Greens say this increases the intensity of heatwaves, which kill more Australians than any other natural disaster.
Climate change modelling suggests there'll be twice as many heatwaves in Australia by 2050.
The main measures in the Greens plan are:
• protecting remaining bushland;
• planting green trails through Perth's arteries;
• auditing trees every three years; and,
• $1.2 million a year to facilitate at least 10 per cent of buildings to have a "green" roof, wall or facade.
This week the Greens took the party faithful through the policies and strategy for the coming election, with a green economy the main theme.
The Greens want better investment in public transport, full renewable energy by 2030 and have committed to full social security.
The party's Fremantle candidate Kate Davis introduced the evening, which was held at Victoria Hall.


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Independent PUBLISHER with a book for everyone
Through 349 images, celebrate America in all her glory. Whether it's a piece to hang on a wall, to be worn, or for marketing propaganda, see how sixty-four artists have represented the American flag and other patriotic symbols in their work. The American flag is an iconic image that inspires many, but it has also become a complex and controversial symbol since Congress first adopted it on June 14, 1777. These artists share not only their work but also the inspiration behind the pieces. Whether it's paying homage to a lost generation, remembering 9/11, or simply celebrating American pride, the various cultural and political viewpoints that define the country today are expressed through a variety of art forms—from watercolor paintings to crazy quilts, from oils to matchboxes, and from mixed media to digital. Let these images inspire you.
Size: 8 1/2″ x 11″ | 324 color & 27 b/w images | 144 pp
ISBN13: 9780764349225 | Binding: hard cover
Ashley Rooney can remember, as a small child, parades marching by and everyone saluting the American flag. Today, she lives in Lexington, Massachusetts, about one block away from the Lexington Battle Green, where the first shots were fired for American liberty. The American flag is there among a few flags flown in the United States 24 hours a day –each and every day – by order of the President of the United States. Ashley has had two husbands, as well as her son, serve their country. Stephanie Standish is a printmaker based in Illinois. An active member of various American print communities, she and Ashley produced Contemporary American Print Makers (Schiffer Publishing, 2014), a collection of 75 printmakers and 30 print shops.