text:
|Interrupt scan and processing system for a data processing system
|Woods et al.
|Steering code generating apparatus for use in an input/output processing system
|Patterson et al.
|Interconnecting unit for independently operable data processing systems
|Data acquisition and control system including dynamic interrupt capability
|Davis et al.
|Lange et al.
|Arnold et al.
|Sharp et al.
|Brandsma et al.
|Byrns et al.
|Driscoll, JR.
|Adams, Jr. et al.
|Figueroa et al.
|Cohen et al.
|Schmidt et al.
|Interface control module for modular computer system and plural peripheral devices
This application is a continuation-in-part of application Ser. No. 476,546, filed June 5, 1974, entitled Method Of And Apparatus For Computer-Multi-Processor Communication And Operation, now abandoned.
a plurality of processor units, each unit including at least one processor and having a plurality of coupler interfaces through which data and addresses may be communicated;
at least one random access system memory unit having a plurality of coupler interfaces through which data and addresses may be communicated and through which request signals may be applied to the memory unit;
at least one communications unit interfacing with a plurality of input/output devices and having a plurality of coupler interfaces through which data and addresses may be communicated;
between each processor unit and each of said system memory units, a respective coupler linking a processor interface to a respective memory interface;
between each processor unit and said communications unit, a respective coupler linking a processor interface to a respective communications system interface, each processor unit being freely associable with any of said input/output devices;
between each communications unit and each system memory unit, a respective coupler linking a communications interface to a respective memory interface, said couplers providing a distributed switching network permitting data communication between any pair of said processors, system memory, and communication units; and
at least one addressable, passive task register associated with one of said units for communication through said couplers for registering a variety of task requests, each task request having a corresponding task priority value which is registered with the request, input/output devices operating to directly register corresponding task requests and values, said register being readable by any one of said processors to obtain the highest priority value registered,
whereby a system program incorporating instruction sequences of preselectable length interspersed with instructions effecting reading of said task register will be run by said multi-processor computer system using all available processor units.
a plurality of processor units, each unit having at least one processor and having a plurality of coupler interfaces through which data and addresses may be communicated;
associated with each processor unit, a local memory with which the processor unit can communicate independently of its respective coupler interfaces;
at least one random access system memory having a plurality of coupler interfaces through which data and addresses may be communicated and through which request signals may be applied to the memory;
a communications unit interfacing with a plurality of input/output devices and having a plurality of coupler interfaces through which data and addresses may be communicated;
between each processor unit and said system memory, a respective coupler linking a processor interface to a respective memory interface;
between each processor unit and said communications unit, a respective coupler linking a processor interface to a respective communications unit interface, each processor unit being freely associable with any of said input/output devices; and
at least one addressable, passive task register for registering a plurality of task request values, each value being independently settable and resettable, said task register including means for generating a code representing the highest value set, said register being readable by a processor to obtain said code,
whereby, a system program incorporating instruction sequences of preselectable length interspersed with instructions effecting reading of said task register may be run by said multi-processor computer system using all available processor units.
a plurality of processor units, each unit including at least one processor and having a data transfer bus providing a plurality of coupler interfaces through which data and addresses may be communicated;
associated with each processor, a local random-access memory with which the processor unit can communicate through the respective bus independently of the respective coupler interfaces;
at least one system memory unit having a data transfer bus providing a plurality of coupler interfaces through which data and addresses may be communicated;
between each processor unit bus and said system memory bus, a respective bus coupler linking a processor bus interface to a respective memory bus interface;
at least one communications unit having a data transfer bus adapted to receive means for communicating with a plurality of input/output devices and also a plurality of coupler interfaces through which data and addresses may be communicated;
between each processor unit bus and said communications unit bus, a respective bus coupler linking a processor interface to a respective communications interface, each processor unit being freely associable with any of said input/output devices;
associated with said communications unit, at least one addressable, passive task register for registering a variety of task requests, each task request having a corresponding task priority value which is registered with the request, input/output devices operating to directly register corresponding task requests and values, said register being readable by a processor through the respective bus coupler to obtain the highest priority value registered; and
between each communications unit bus and said system memory bus, a respective bus coupler linking a communications bus interface to a memory bus interface, whereby, a system program incorporating instruction sequences of preselectable length interspersed with instructions effecting reading of said task register will be run by said multi-processor system using all available processors indiscriminately.
an addressable latch including a plurality of individual elements which represent respective priority levels and are individually settable and resettable, said latch including;
decoding means for setting a respective latch element when a task request including a coded priority value is communicated to the device;
priority encoding means for generating an output code representing the highest level latch element which is set;
interface means permitting a processor in the system to read said output code; and
means for resetting the latch element represented by said output code upon reading of the output code by a processor.
This invention relates to multiprocessor computer apparatus and more particularly to such apparatus which avoids any processor hierarchy and also avoids employing any centralized switching system.
As discussed in the above-identified patent application, various multiprocessor arrangements have been proposed heretofore. Various specific earlier attempts at a multiprocessor architecture are discussed in greater detail in the previously identified parent application. That discussion is incorporated herein by reference, but certain general considerations are repeated here for background information. As with the present invention, the purpose of such prior art multiprocessor arrangements was to increase computational power and speed by employing a plurality of processor units which would operate in parallel so as to obtain a data through-put greater than that achievable by a single processor operating at any achievable speed. With a few exceptions, most algorithms and computations typically handled by digital computers are susceptible of parallel processing. Further, since the cost of increasing processor speed increases sharply beyond a predetermined point, it can be shown that throughput above a corresponding level can be achieved more economically by employing a greater number of relatively slow processors than by increasing the speed of a single processor. Heretofore, however, these advantages have not been gained without incurring some considerable penalty in terms of system reliability and increases difficulty in programming. These offsetting penalties were typically due to hierarchial organization of the processors. One characteristic often contributing to reliability problems was the usual organizational arrangement where each communications or input-output device was associated with a given one of the processors. Thus, a failure in that one processor might cause the entire system to be unable to fulfill its overall intended purpose.
Among the several objects of the present invention, it may be noted the provision of a multiprocessor computer apparatus providing increased throughput; the provision of such apparatus which is flexible in capacity; the provision of such apparatus which is highly cost-effective; the provison of such apparatus which is highly reliable; the provision of such apparatus which is inherently modular in nature; and the provision of such apparatus which is of relatively simple and inexpensive construction. Other objects and features will be in part apparent and in part pointed out hereinafter.
Briefly, a computer system in accordance with the present invention involves a plurality of data processor units. The system also involves one or more system memory units of relatively large capacity and one or more communications units comprising the input/output interfaces for the entire system. Separate data couplers are provided between each processor unit and each system memory unit and also between each processor unit and each communications unit and between each communications unit and each system memory unit, thereby forming a distributed and modular data transfer or switching network. A passive task register is provided for registering a variety of task requests and, with each task request, a task priority value. The task register can be read by any processor to obtain the highest priority value registered. Accordingly, a system program incorporating instruction sequences of appropriate length, interspersed with instructions effecting reading of the task register, will be run by the system using all available processor units, essentially indiscriminately.
In accordance with one aspect of the present invention, the individual processors employed are preferably of the type which utilize a single bus through which essentially all data transfers are made. Examples of such processors are the Lockheed SUE™ computer, which utilizes the Lockhead INFIBUS™ data transfer system or the PDP 11 computer of the Digital Equipment Company, which utilizes the UNIBUS™ data transfer system. In systems of this type, essentially all devices and registers are communicated with through the single bus system and are addressed in essentially the same manner as memory locations. In single processor computer systems of this general type, the same bus serves as a communications path for data transfers to input-output devices and to bulk memory, such as tape and disc, as well as to the processor's random access memory.
FIG. 1 is a functional block diagram of multiprocessor computer apparatus in accordance with the present invention;
FIG.2 is a logic diagram of a processor-type bus coupler end employed in the apparatus of FIG. 1;
FIG. 3 is a logic diagram of a memory-type bus coupler end employed in the apparatus of FIG. 1; and
FIG. 4 is a logic diagram of a passive task register employed in the apparatus of FIG. 1.
Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.
In the presently preferred embodiment of the multiprocessor computer apparatus of the present invention, which embodiment is described herein, the individual digital processors are Lockheed SUE™ processors of the so-called mini-computer type. Likewise, Lockheed INFIBUS™ data transfer systems are utilized for local data transfer. Accordingly, the following description assumes a familiarity with these commercially available units and with the interfacing conventions which are employed in communicating with and through these systems. Reference is made in particular to the Lockheed bulletin entitled SUE INFIBUS INTERFACE and designated General System Bulletin G4. Insofar as possible, signal designations and conventions have been utilized in the following description which are the same as or consistent with those employed in the Lockheed bulletin.
As suggested previously, a plurality of Lockheed INFIBUS™ systems are utilized. As is known, the physical configuration of each INFIBUSTM system is that of a back plane into which circuit cards carrying the different devices may be plugged. Although the several bus systems themselves are all essentially similar, the buses may conveniently be grouped into three classes or types in accordance with their utilization in the overall system. Firstly, a substantial number of the buses support processors, i.e. Lockheed SUE™ processors.
In that the bus permits a variety of data transfer paths to be established and permits any devices on the bus to initiate a request for the bus, it can be seen that more than one processor may be coupled to a bus and that each processor will, in effect, regard the other processor as merely another device on the bus, i.e. as it would regard a device of the class normally considered to be a peripheral. The processors may optionally have either a shared memory between them or respective memories considered separated by having different addresses respective to the different processors. With the particular components obtained from the Lockheed company, it has been determined by statistical methods that loss of processor speed due to conflicting requests for the bus is nominal with only two processors on the bus. The use of three processors on a single bus, while possible, is believed to incur a substantial loss in throughput so that increased power is better obtained by adding additional processor buses. Addition of a fourth processor on a single bus incurs an even further penalty so that the effective additional throughput is equivalent to less than one-half of that obtainable from a processor on a separate bus.
In the example illustrated, there are four processor buses 11-14 and each bus supports two processors, designated 21 and 22. Associated with each processor, is a local random-access memory, designated 23 and 24 respectively, each processor obtaining access to its respective memory through the bus which is common to the two processors. The memory units 23 and 24 will typically be of relative small capacity, e.g. 4 K words.
As is understood, there is associated with each INFIBUS™ data transfer system a bus controller unit or arbiter which holds off new requests for the bus in the presence of previously occurring requests or simultaneous requests of higher priority. Likewise, there is associated with each bus a power supply which provides power to the various electronic units coupled to the bus.
Another class of bus or series of buses supports the main system memory. As illustrated, the system memory comprises four 8k memory units 31-34, paired on respective memory buses 35 and 36. A third class of bus or series of buses supports a communications interface or I/O (input/output) unit or system. In the embodiment illustrated, the communications interface comprises a pair of the INFIBUS™ units, which are interconnected by means of Lockheed bus extender units, so as to function essentially as a single bus. The composite extended bus is designated by the reference character 41. The various communications interface units which allow various peripherals, e.g. Teletypes, tape drives, modems and the like, to be coupled to the bus are designated 43-46. Preferably, one of the peripherals coupled to the communications bus is a clock 47 capable of providing various timing signals as described hereinafter.
Data transfers between different types of units or classes of buses are accomplished by means of bus couplers. The bus couplers are constructed so that, at each end, they present themselves to the respective bus as just another device with a corresponding address. Thus, each end of the bus coupler is provided with the means providing an interface compatible with the Lockheed INFIBUS™ systems and thus can initiate a transfer of data on that bus or can be addressed by some other device on the bus responsive to a data transfer request initiated by that other device.
As described previously, the physical configuration of each bus type data transfer system is that of a back plane into which are plugged circuit cards which may carry processor modules; electronic memory units; I/O or modem circuitry; and the like. Correspondingly then, each bus coupler comprises a pair of circuit cards, each card containing the electronics for interfacing with the respective bus, and a flexible cable, connecting the two cards.
In the drawing of FIG. 1, the card at each end of a bus coupler is designated by a code indicating its function as follows
Bcp = bus coupler, processor type end
Bcm = bus coupler, memory type end
The cable connecting the two cards is in each case represented by a single line in the drawing for clarity of illustration.
At the outset, it may be noted that the bus couplers perform the following major functions, although it should be understood that not every bus coupler will in actual operation perform all these functions and that certain additional functions may also be implemented through some of the bus couplers.
Firstly, the bus couplers make available to any of the processors memory locations which are, in fact, directly addressable only to another bus, i.e. different from the bus supporting that processor. The principal way in which this function is utilized is in permitting a processor to read or write data into memory locations in the system memory, i.e. 31-34.
An associated function of the bus couplers is the mapping of memory or transposing of memory addresses so that the system address space may be substantially larger than the range of locations which may be directly addressed using the eighteen bit address scheme of the Lockheed SUE™ processors.
Essentially similar functions are provided between each processor bus 11-14 and the communication bus 41 so that each processor unit can address and receive data from the various input/output devices, e.g. those conventionally considered to be peripherals, as well as any other devices which are coupled to the communications buses.
In the foregoing brief description of each of the bus coupler functions, it has, to some extent, been assumed that the communication was provided at the initiation of a processor, through the respective processor bus, though the flow of data might be in either direction. A further function of bus couplers is, however, to provide for backwards requests. An example of such a backwards request is the use of the bus coupler upon initiation by a device on the communications bus to access memory on a processor bus. Again, the actual flow of data may be in either direction.
The bus couplers connecting the communications bus 41 to the memory buses 35 and 36 are similar to the bus couplers connecting each processor bus to the memory buses and provide essentially analogous functions. For example, the communications bus can request data from memory locations in the system memory and can similarly write into such locations. Thus, the coupler card at the communications end of a communications/system memory bus coupler is generally of the "processor" type rather than the "memory" type. Stated another way, the "forward" direction through these couplers is considered to be from the communications bus to the memory bus.
For the purpose of illustration, it is appropriate to describe in greater detail a bus coupler of the type which extends between a processor bus and one of the system memory buses since the other types of bus couplers are largely lesser included cases, omitting some of the functions of the processor bus/memory bus couplers. As indicated previously, each bus coupler comprises, in the preferred embodiment, a pair of circuit boards linked by a connecting cable. The electronics associated with the processor bus end of such a coupler are illustrated in FIG. 2 and the electronics associated with the system memory end of the bus coupler are diagrammatically illustrated in FIG. 3.
Referring now to FIG. 2, the bus interface electronics are indicated generally at 55, these being the drivers and receivers which permit the bus coupler to drive and receive signals from the bus lines in the same manner as any other device on the bus. Again, reference is made to the Lockheed System Bulletin G4 entitled SUE INFIBUS INTERFACE with respect to the standards to be applied in connecting a device to the Lockheed INFIBUS™ data transfer system. In the preferred embodiment, the circuitry shown in FIG. 2 and particularly by that indicated at 55 was constructed in accordance with the teachings of that handbook, employing to a large extent integrated circuits commercially available from Lockheed Electronics and other vendors.
As is understood, the signals communicated with the bus include an address, designated generally by the reference character A in the drawing; data, generally designated by the reference character D in the drawing; and a variety of control signals, designated by reference character C. Though these control signals are not for the most part involved in the substance of the present invention, they are identified and briefly defined in the following table, essentially the same information being available in the aforementioned Lockheed bulletin.
Rite write operation
Byte byte operation
Hcyc half cycle operation
Mres master reset
Strb address/data strobe
Done successful completion
Quit abnormal completion
Srld access request
Seld device select
Sacr select acknowledge
Pcda/b precedence
Hold defer recognition
As explained hereinafter, some of the signals communicated with the bus are processed or utilized within the bus coupler itself while substantial numbers of these signals are essentially passed directly through the bus coupler. In that the cable which connects the two circuits boards of the bus coupler may traverse a distance which is relatively great as compared with the typical signal path lengths within a single INFIBUS™ structure, the processor bus end of the coupler is provided with appropriate cable driver and receiver electronics, indicated generally at 57. These electronics provide, in conventional manner, the requisite source and load terminating impedances for sending digital signals over a substantial length of cable, the cable itself being indicated at 59. In order to minimize crosstalk and capacitive loading, the cable 59 is preferably of the flat, braided type.
A portion of the address signals, i.e. the higher order bits, are applied to an address recognizer 61. The address recognizer 61 is a decoder which is preset to recognize the address or range of addresses for which the particular bus coupler will be needed to be utilized.
The address recognizer, upon recognizing an address to which the bus coupler should respond, provides various output signals which identify the nature of the address recognized. These various control signals are listed in the following table together with brief description of their functions or significance.
Bakio i/o address
Mapad map address
Segmt common memory address
Loka lock address
These control signals are provided to the control circuitry for the computer end of the bus coupler, this control circuitry being indicated generally at 75.
Of the remaining portion of the address, the less significant bits are passed directly through this end of the bus coupler to the cable driving electronics 57, while certain of the higher order of bits are applied to an address mapping memory 63. The address mapping memory employs these higher order bits of the applied address to select which one of several stored addresses is transmitted out over the cable to the other end of the bus coupler. By this means, the range of addresses which can be reached is effectively expanded. Further, since the address words stored in the mapping memory 63 can be changed under program control, as described hereinafter, the correspondence between local addresses on the processor bus and the actual addresses in main system memory can be easily rearranged or changed.
Data received from the processor bus is applied to a data latch or register 71 so that, as soon as the bus coupler has received and loaded the data, the coupler can release the bus from which the data was received under the direction of the signal LODBF from the control circuitry 87. Again, this is in conformity with the usual practice for connecting devices to the Lockheed INFIBUS™ data transfer system, as described in the previously identified Lockheed handbook. The latched data is then provided to the cable 59 through the cable interface 57. The more significant bits in the data are also made available to the address mapping memory 63. The registers constituting the memory 63 have system addresses which are included within the range of those recognized by the address recognizer 61. When the address recognizer recognizes one of the addresses corresponding to the memory 63, the binary data made available from the data stream on the bus is loaded into the corresponding memory register, i.e. when enabled by the control signal designated RITMAP. Thus, the address mapping memory 63 can be loaded with data representing selected system memory addresses under program control. The entire collection of data and address signals are also applied to parity logic circuitry indicated generally at 77. This parity logic may be generally of the type described in U.S. Pat. No. 4,035,766 issued July 12, 1977 to William B. Barker and entitled Error-Checking Scheme. Assuming that the data includes one or more parity bits, the parity logic independently calculates the parity bit and compares the calculated parity bit with the transmitted parity bit and transmits a parity okay (POK) signal indicating that the parity bit is correct, if that is the case, this signal being provided to the control circuitry 75. If the parity is not correct, the control circuitry generates the signal designated QUIT, which signal may be generated under certain other failure conditions also consistent with the standard interfacing practices of the Lockheed INFIBUS™ system.
In addition to the data address signals which are passed on to the cable interface 57, various control signals are passed on to the cable interface, which control signals represent the state of the computer bus and bus coupler, and for the most part, are signals which correspond essentially directly with the control signals communicated with the corresponding computer bus. These control signals are listed and briefly identified in the following table.
Ctreq transmitted request
Crreq received (backwards) request
Cdone successful completion
Cquit abnormal completion
Chcyc do half cycle operation
Cbyte do byte operation
Clock do lock operation
Crite do write operation
Cpblo/hi parity bits
Cbres reset (remote)
Cpwrp remote power is up
Psin power sense in
Psout power sense out
The memory end of the bus coupler includes an address recognizing decoder 91 which is responsive to the address signals obtained from the cable interface, which decides that this reference is desired for this coupler and not some other. Since the range of addresses available through the corresponding memory bus is typically contiguous and predetermined in nature, the addresses may typically be recognized by means of the most significant bits upon matching with the setting of an address register switch, indicated at 93. Upon obtaining a match, a control signal designated PRMIT is provided to the control circuitry 87, which signal represents that address match has been obtained and that a request is being initiated to the memory bus.
The entire memory data stream is applied to a latch 85 so that when the bus coupler has acquired data from the bus through the bus interface circuitry 80 the memory bus itself can be released so as to be available for other data exchanges within the system memory unit.
In order to provide flexibility in the preselection of the control signals applied to the memory bus in response to various combinations of control signals on the coupler cable, the memory end of the bus coupler preferably allows the state of the control circuitry 87 to be altered and preselected by means of a control register, indicated at 95, which control register may be loaded from the data lines. The loading of this control register is preferably conditioned upon the recognition of an appropriate address and data pattern applied from the memory bus which causes an enabling signal DOSWI to issue from the address recognizer 81 to the control register 95. Accordingly, it may be seen that, by generating the appropriate address and data on the memory bus and by loading into the control register 95, a data format which disables the control circuitry 87, the memory bus may, in effect, cut off the processor at the other end of the cable.
As indicated previously, one aspect of the present invention contemplates that requests for data communications may be initiated at either end of the bus couplers. Accordingly, as illustrated in FIG. 3 the memory end of the bus coupler also includes address recognition circuitry as indicated at 81, and an address mapping memory 83, which memory may be loaded from the more significant bits of the data stream. Upon recognizing an address, the recognizer isues MAKDN to the controller. Control signals from both the bus interface and the cable interface are applied to control circuitry, indicated generally at 87, as with the bus coupler at the processor end.
This facility is used principally in generating so-called backward requests, i.e. requests initiated from the memory buses 35 and 36 or the communication bus 41 directed to a processor bus. A less apparent use for this capability, however, is in enabling a processor on one processor bus to address a processor on another bus. In other words, a processor on one processor bus can communicate through one of the respective bus couplers, to a memory bus and then, on that memory bus, generate a backward request through a bus coupler extending from the memory bus to another processor bus, to a processor on that other bus. In this way, one processor can address the control registers of a processor on a different bus.
As will be understood by those skilled in the art, these facilities mean that one processor, utilizing the appropriate codes, can set the control registers of bus couplers extending to another processor, thereby cutting off the availability of the memory bus to that other processor and, even further, can reach back up through the other processor's bus coupler from the memory buses so as to stop and reset that other processor. From the foregoing, it may be seen that the bus couplers provide a very powerful and flexible means of communications. Virtually any device on any bus may initiate a data exchange in either direction with a device on any other bus, although, in practice, not all paths are typically implemented.
As will be understood, the fastest communications occur when the device addresses another device on the same bus, e.g. a processor entering or extracting data from its own local memory. Thus, the programming of the system is preferably oriented so that most frequently used operations may be implemented entirely from local memory. Each processor does, however, have access to the relatively large system memory. To extract information from the system memory, a processor initiates a request to an address which activates the corresponding bus coupler. This bus coupler, in turn, communicates the request to the memory bus, presenting itself to that bus as though it were a device on the appropriate system memory bus. The data requested is provided to the bus coupler which then releases the memory bus and transmits that information back to the processor bus. While this data exchange procedure is obviously slower than transfers between devices which are, in fact, on the same bus, the time penalty has not been found to be particularly harmful since such accesses are required relatively infrequently in normal programming.
The extreme case of one processor attempting to reset another processor through a data communications path extending through two bus couplers is, or course, relatively slow. However, as will be understood by those skilled in the art, such communication paths will be called upon very infrequently, e.g. only in the event of reinitiating a processor in the group after an electronic or program malfunction of some sort or another.
A distinctive characteristic of this multiprocessor interconnection system is that the switching network which establishes the various data transmission paths is distributed and modular. Specifically, each processor bus has a separate bus coupler extending to each of the memory buses and also to each of the communication buses. Further, each end of each of the bus couplers presents itself to the corresponding bus in the same manner as just another device on that bus. Thus, the interface switching occurs at the end of the bus coupler in a manner entirely consistent with normal single-bus mini-computer systems.
In that this interconnection or switching system is modular and distributed, it is also quite flexible. There is no distinct impediment to adding or subtracting another processor bus, for example, or even another memory bus or communications bus. While the number of bus couplers tends to increase geometrically and there is thus some tradeoff involved in selecting the numbers of processor buses or memory buses and communication buses, there is no abrupt limit or sudden transition in the complexity or effectiveness of the system. Thus, a very high degree of flexibility or expandability is obtainable. An example of a configuration which has evolved using Lockheed components incorporates seven processor buses supporting thirteen processor units, each with an associated 4K local memory. Two system memory buses were used, each bus supporting two 8K memory units. Two expanded communications buses were utilized. This prototype machine was developed by Bolt, Beranek and Newman Inc. for the Advanced Research Projects Agency under Contract Nos. FO8606-75-C-0032 and FO8606-73-C-0027, ARPA Order No. 2351. Many details of the construction of this particular system using Lockheed subsystems are described in Reports Nos. 2930 and 2999 under these contracts. As such detailed information goes beyond the subject of the actual invention and would not be useful in designing a system in accordance with the present invention utilizing other makes of mini-computers, such information is not incorporated in the present specification except by reference to these documents which are of record.
An additional distinguishing characteristic of this interconnection system is that it is essentially non-hierarchical. No one processor is dominant over the others and, in operation, no processor normally exerts control over any of the others. Only in the extreme case, using highly protected code words, is one of the processors allowed, under program control, to stop and reinitiate another procesor or to replace the contents of the other processor's local memory. Likewise, in keeping with the non-hierarchical arrangement of the overall computer system, there is no particular association of each communications device, i.e. tape, drive, Teletypes, modems and the like, with any one processor. Rather, each processor has equal access to every communications device or, viewed from the other end, each communications device has an equal chance of being serviced by any one of the processors.
Rather than using a hierarchical arrangement of the several processors, the apparatus of the present invention employs an essentially passive hardware task registering device. This task registering device has been usefully described, in certain contexts, such as a psuedo-interrupt device (PID) since many of the tasks registered by the device correspond to interrupt signals generated by devices of the types normally considered as peripherals in single processor systems. In the preferred embodiment, the pseudo-interrupt device or task registering device is coupled and supported by each communications bus directly, as indicated at 49 in FIG. 1. As may be seen, there is no processor on the communications bus and interrupt signals generated on that bus by the various peripherals are received by the pseudo-interrupt device in place of such a processor.
In general, the operation of the psuedo-interrupt device is to register the fact that a task request has been made. Along with the fact of the request, the psuedo-interrupt device registers a value, which value indicates or corresponds to the priority level of the particular task request. The circuitry which provides these functions is diagrammed in FIG. 4.
As indicated previously, the pseudo-interrupt device (PID) is associated with and supported by the communications bus. As with most of the other elements of the system, the pseudo-interrupt device presents itself to the respective bus in the same manner as any other device or peripheral. However, as indicated previously, the psuedo-interrupt device is an essentially passive device and thus is only addressed by other devices and does not itself initiate or establish communication links through any bus or bus coupler. Thus, the bus interface indicated at 101 in FIG. 4 may be somewhat simpler in implementation. The psuedo-interrupt device responds to a limited number of addresses and, for this purpose, incorporates an address recognizer, indicated at 103. The address recognizer generates a limited number of control signals enabling corresponding components of the PID in dependence upon the particular address received. As described in greater detail hereinafter, the particular address to which the PID responds indicates whether the device is to register a task or is being read to discover what is the highest level task in the register at that point. Similarly, this information determines whether, after reading the highest level request, that request is to be reset or nullified.
When another device is seeking to enter a task in the task register of PID, seven bits of the data presented to the PID are taken as representing the priority level of the task. The priority level is represented in a conventional binary code so that 128 levels, e.g. zero through 127, are available. In practice, the zero level is always left in a set condition in that this has been found to facilitate programming of the overall system.
The four most significant bits of the priority level are applied to a four to sixteen line decoder 107. Each of the output signals from decoder 107 is applied as an enabling signal to a respective eight bit addressable latch 111-126. The three least significant bits of the priority level are applied in parallel to the address inputs of all of the addressable latches 111-126. The RITE signal which normally comprises part of the data provided over the bus in the Lockheed INFIBUS™ system is employed as the data bit to each of the latches. As will be understood, the latches 111-126 together provide an addressable register comprising a total of 128 individual latches or bits. When the PID is addressed, the address recognizer circuit enables the decoder 107 and a single one of the storage latches corresponding to the particular task priority level will be set to a one or a zero in dependence upon whether the write signal, designated RITE consistent with Lockheed INFIBUS™ convention, was present or absent. As will be understood, the presence of previously set bits within the register does not prevent any other bit from being set. Thus, the register will, at any one time, hold information designating all tasks which have been previously registered and not been taken care of, i.e. reset.
The eight output bits from each addressable latch 111-126 are applied to a respective priority encoder 131-146. Each priority encoder provides a group output signal designated GR if any one of the input signals is set and also provides a three line output which, in binary code, represents the latch address of the highest bit which is set. The group output signals corresponding to the eight most-significant of the latch circuits 111-118 are collected in a priority encoder 147 while the group outputs corresponding to the eight, less-significant latch circuits 119-126 are collected in a second priority encoder 149. The coded outputs from one or the other of the priority encoders 147 and 149 are selected by means of a three bit, two position multiplexer circuit 151, the selection being made under the control of the group output signal from the priority encoder 147 receiving signals from the higher order latches. The group output signal from the priority encoder 147 will be seen to indicate whether any bit is set in the upper half of the latches. If any such bit is set, the three output signals from the multiplexer 151 will represent, in binary code, which one of the latch circuits 111-118 contains the highest level bit.
Three sixteen line-to-one line multiplexer circuits 155-157 are employed to select which one of the priority encoders 131-146 will be read to obtain the three less significant bits defining the highest set level, the most significant bit from each encoder 131-146 being applied to the multiplexer 155; the next most significant bits to the multiplexer 156; and the least significant bit in each three bit code being applied to the multiplexer 157. The output signals from the three-bit, two-input multiplexer 151 are applied in parallel to control the selections made by the multiplexers 155-157.
The full seven bit code representing the highest set level of the individual latches in the latch circuits 111-126 is applied to a storage latch 161 which acquires this data and holds it for application to the data lines back through the bus interface through the multiplexer 106. In that the ripple through or settling time for the decoding network and the priority encoding tree structure may be significant, the latch 161 is normally enabled only following a predetermined delay following recognition of the corresponding address, this delay being provided as indicated at 163.
Summarizing then, the operation of the pseudo-interrupt device (PID) is, in general, as follows.
In order to enter a task into the PID, another device addresses the PID through the communications bus and enters on the bus data lines a value representing the priority level of the task. The address is recognized by the PID which responds by causing the individual latch corresponding to that priority value to be set. While more than one individual latch can be set, the priority tree continuously provides to the output latch 161 a seven bit code which represents the highest value which as been set. Thus, when the PID is interrogated through the bus, the data which is obtained, by the interrogating device through the bus, is the priority level of the task having the highest priority which has been registered. Since this value designation is already present on the data lines, a single step operation can be performed in which the value is read, the decoder 107 is enabled, thereby enabling the latches 111-126, and the RITE signal being at the reset level, so that the identified latch is reset, in effect, cancelling the entry of that task. In a preferred embodiment, this sequence is initiated by addressing the PID through a particular one of its several addresses and the address recognizer includes the minimal control circuitry necessary to effect the desired sequence of operations.
It is believed to be useful to again point out that, although the apparatus shown in FIG. 4 is conveniently referred to as a psuedo-interrupt device, it is, in fact, an essentially passive or slave device, i.e. it does not initiate data transfers on the bus. Rather, other devices can enter tasks in this task register and other devices can then interrogate the task register to find out whether any tasks require attention and to determine the priority level of the most immediate task.
It should also be understood that tasks arising in various different ways can be entered in the psuedo-interrupt device. Many of the tasks will be entered by communcation devices on the communications bus, e.g. Teletype or modems, in essentially the same manner in which they would generate interrupt signals in a conventional single processor computer system. In the simplest case, the bus interface for the peripheral need be modified only to the extent that, in response to an interrupt request from the peripheral, the bus interface outputs a predetermined PID address and a predetermined value designating the task priority level. For the most part, reading of the psuedo-interrupt device will be initiated by one of the processors, i.e. through a bus coupler from the processor bus to the communications bus, the most usual event being that the processor will seek the task having the highest level, and will then go off to perform that task. Upon successfully locating and accepting the task, the processor will reset the corresponding level. In some cases, the priority level may uniquely identify a particular device requiring attention so that the resetting of the priority level can occur simultaneously with the reading and the processor will unambiguously be set upon a task. However, with lower level tasks which do not require as immediate attention, it is entirely possible to utilize the same priority level for several different tasks or several different devices which might register tasks. In this case, the inquiring processor can, after reading the task level, proceed to poll the several task sources which might register tasks at that level. If there is only one such task, the processor can then undertake that task and, in a separate operation, reset the corresponding latch in the task register.
The passive task register arrangement of FIG. 4 also possesses the desirable attribute that tasks can be registered by a processor under program control as well as by communications devices of the type which normally obtain service through interrupt signals. Thus, in programming the overall apparatus of the present invention, programs can conveniently be broken into sequences of optimum length even though an overall sequence is not completed. Upon completion of the short sequence, the program can have the processor set a task priority latch at a level corresponding to the urgency of completion of the rest of the program sequence and store appropriate pointers to enable picking up of the overall task. Having broken off the pre-existing overall sequence, the processor can then poll the PID to see if there are any higher level tasks, and can then pick up either these tasks or return to its original sequence, as required. Further, if the processor which, under program control, set the priority level designating the unfinished program task, has gone off to service a more urgent request, and in the meantime, another processor becomes free and polls the PID, this latter processor can pick up the program task which the first processor had initiated.
With the ability of the processors in the overall system to share programming tasks, it can be seen that the processors, as a group, are treated as a resource to be utilized by the overall system program and the psuedo-interrupt device, each processor being put to work as it becomes available. Further, since there is no heirarchical arrangement of the individual processors and there is no fixed association of any of the communications or other task spawning devices with any one processor, it can be seen that the failure of any one processor does not inherently disable the system but merely reduces the processing power, essentially pro rata.
One of the functions appropriately provided by the clock 47 is to periodically set a predetermined priority level in the task register, which level corresponds to and initiates a program segment which checks the status of all processors and any other components of the system. Assuming that this priority level is one of the highest, its execution is virtually assured if any of the processors are running properly. If no fault is detected, the segment can be quickly completed as understood by those skilled in the art. If faults or stoppages are detected, the program can branch and/or set other priority levels which initiate program sequences for determining the nature of the fault and restarting any processor whose operation may have been stopped by the fault.
As is understood, the processors also may incorporate various "time out" features which operate to detect various types of failures, e.g. those which would lock the processor in an unproductive loop.
In the preferred embodiment illustrated, each processor is, as noted earlier, provided with some local memory. In this local memory is preferably stored an operating program sufficient to enable each processor to look for work, so to speak, plus a sufficient library of programs to enable it to conduct a majority of its tasks without repeated reference to the main system memory. The main system memory then can be utilized for user programs and the like. In general, the contents of the local memories for the several processors will be the same for all processors. However, it should be understood that a part of these memories will also be utilized in running these resource programs and conducting the arithmetic algorithms etc. and thus these portions of the contents of the memories will be continually changing as each processor runs a particular task.
A further advantage of this system organization is that it inherently provides a very great capability and flexibility for avoiding system failures due to failures in individual components. As indicated previously, the mere stopping of any one processor has a relatively insignificant effect on the system in that the processors are utilized as an expandable resource just as different sizes of memory may be utilized in more conventional systems. However, the system also has the possibility of restarting, or in the last analysis, cutting off a processor which behaves erratically. If the system program can detect the failure, e.g. the erratic writing of the processor in improper portions of memory, another processor can address the "sick" processor by addressing the control registers of the "sick" processor indirectly as described previously, i.e. through a data transfer path which includes two bus couplers and a third bus such as a system memory bus. The "sick" processor can in this way be stopped. Further, the correcting processor can attempt to reset the "sick" processor by appropriately loading its control registers and by restoring the background program in the respective local memory. If the failure is a continuing one, however, so that the processor cannot be successfully restarted and function in a normal way, the correcting processor can set the control registers of those bus couplers which permit communications with the processor bus supporting the "sick" processor, so as to block such communications initiated by that processor. The "sick" processor, together with all other devices on the same bus, will thus be cut off and isolated from the rest of the system. Again, however, this loss of resources need not cause the overall system to fail, since the system program can continue to utilize the rest of the processor and memory resources as they become available and can continue to run the system program effectively, although at reduced speed.
As will be understood by those skilled in the art, programming of a new computer system as described herein involves a developmental process extending over an appreciable length of time even though the hardware development may have essentially come to rest and the programming possibilities are manifest. At the time the present specification was being prepared, programming for the thirteen processor prototype machine described earlier herein had progressed to a substantial extent and two assemblers had been written, one adapted for running on a Digital Equipment Corporation PDP-1 computer and one adapted for running on a Digital Equipment Corporation PDP-10 computer. These assemblers and their usage are described in Report No. 2931 under the Advanced Research Projects Agency Contracts identified previously. Again, this detailed information is tied strongly to the particular prototype construction utilizing Lockheed SUE™ computers and is not general to the present invention. Accordingly, this information is incorporated by reference only.
As is brought out in the three ARPA reports referred to in the foregoing specification, the function for which the first multiprocessor prototype was designed was that of an IMP terminal in the ARPA communications network which links a variety of large computer centers spread across the country.
In view of the foregoing, it may be seen that several objects of the present invention are achieved and other advantageous results have been attained.
As various changes could be made in the above constructions without departing from the scope of the invention, it should be understood that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.


text:
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text:
A college baseball player shot to death while out for a jog was targeted by three "bored" teenagers who simply wanted to kill someone, police said.
Chris Lane, a 22-year-old from Australia, was shot and killed Friday afternoon in Duncan, Okla., about 85 miles away from where he played baseball at East Central University in Ada, Okla.
Police Chief Danny Ford told ABC News that Lane was randomly targeted and shot in the back, left to die by the side of the road.
Three teens, ages 15, 16 and 17, were arrested Friday night on first-degree murder charges, Ford said. Their names were not released.
Ford told ABC News that the teens "were bored and just wanted to see someone die" when they spotted Lane jogging alongside the road.
Lane was visiting his girlfriend in Duncan, a community of 24,000 in southern Oklahoma. He died at a local hospital shortly after arrival.
Ford said no one witnessed the shooting but people heard a gunshot and reported a black car speeding from the scene. Surveillance video from businesses recorded the car pulling behind a hotel minutes afterwards.
Three hours later, a tip led authorities to spot the car at a church parking lot, with three teens standing alongside the black Civic Honda.
Chief Ford told ABC a search of the car "found evidence that made us believe they were involved." The Duncan Banner said a dismantled shotgun was found in the back of the vehicle but it was not the gun used to shoot Lane. That weapon has not yet been recovered, police said.
Ford said the suspects were uncooperative at first but later the 17-year-old driver of the car admitted they were at the scene of the shooting and that the 16-year-old pulled the trigger.
Ford said detectives determined that the boys were in a house when they saw Lane leave a nearby home to go jogging.
"It was random," said Ford.
Ford said the shooting has shocked the small town not far from the Texas border.
"I don't think we average one [murder] a year," Ford told ABC. "Basically, we're a rural Oklahoma community."
Details for this story were reported by The Duncan, Okla., Banner and ABC News.


text:
Basic Motorcycle Licensing Class
Mon/Tues, BDECEMBER7-8-C-AM
Price: $295
Deposit: $295
Class Full? Try being a walk-in!
If you want to search for classes in a more detailed way. Please select the following options and click on search to see what classes are available.
Ride Chicago has three locations and offers classes seven days a week.
Select a location and the two consecutive days you wish to ride.
Attend your classroom session.
Classroom is typically held one evening before the riding sessions.
We also offer a Tuesday morning and occasional Saturday morning classroom sessions.
Enjoy two consecutive days of riding at our course!
Licensing tests for our graduates are held at our sites Wednesdays and select Thursday mornings.
If you cannot attend an assigned classroom session, feel free to sign up for the class. Then notify us one week in advance to discuss your options. Classroom sessions are held either Tuesday mornings, Wednesday or Thursday evenings. (Varies seasonally)


text:
Michael Raynis was the man that sealed Harvard's sixth Ivy League championship, defeating his opponent on the last touch of the bout, defeating Yale as Harvard went 5-0 in the tournament.
The Particulars
The Harvard men's and women's fencing teams head to New Haven, Conn. for the 2012 Ivy League Championships Saturday and Sunday.
Rank and File
On Jan. 18 the NCAA posted its 2012 men's and women's fencing rankings. The Harvard men came in at No. 3 in the poll, while the women ranked at No. 7. In the men's poll the Crimson is the second-ranked Ivy League team with Princeton taking the No. 2 spot, meanwhile the situation is almost identical in the women's poll as the Crimson women are the second-ranked Ancient Eight team with Princeton taking the No. 2 spot.
Kaneshige With It
Freshman Brian Kaneshige was one of the Crimson's more impressive fencers in the St. John's Invitational as he recorded the team's best record in the foil grouping at 10-5 and tied for the team lead at the end of the weekend.
Confidence Boost
While the St. Jon's Invitational didn't go as planned for both the men's and women's squads there was one result that was a big confidence boost for the Harvard women's team. In the first match of the afternoon the Crimson defeated No. 1 ranked Penn State, edging the Nittany Lions 14-13. Harvard ended the day with another big win against a tough St. John's team defeating the No. 6 Red Storm 14-13. The women's team went 2-3 but can look back on its experiences in two successful bouts as it moves forward with the fencing season.
About Harvard
The No. 3 men's squad and No. 7 women's team enter the Ivy League tournament coming off a disappointing St. John's invitational after the men went 1-4 and the women went 2-3. Overall though both teams have had successful campaigns with the men accruing a 5-5 record and the women an 8-4 mark.
The women's fencers had gone undefeated as a team until the St. John's open, defeating Temple (16-11), North Carolina (19-8), New York (21-6), Sacred Heart (22-5), Vassar (22-5) and Tufts 22-4). Harvard has received strong play from its top competitors, senior Caroline Vloka and sophomore Alexandra Kiefer but have also been buoyed by the addition of freshman Emma Vaggo. The Kullavik, Sweeden, native has been one of the strongest in the Crimson's epee field, most recently leading the division, going 11-4 which was tied for Harvard's best record during the meet.
The Harvard men are looking to duplicate last year's Ivy Title success as they registered its first Ancient Eight championship since 2006. As far as this year goes, the have men enjoyed similar success early in this campaign winning four out of five dual matches, with its lone loss coming to No. 1 Penn State. The men defeated Vassar (21-6), North Carolina (19-8), New York (21-6) and Sacred Heart (17-10). Like the women's team, the men have seen good production from the usual suspects in Valentine Staller, Ben Cohen and Michael Raynis, and have also received production from freshmen Brian Kanshige and Pergrine Badger. Badger won bronze at the Penn State open to start the season and Kaneshige was one of the Crimson's most impressive fencers at the team's last tournament, the St. John's Open, going 10-5 in five dual matches.
Brown enters the tournament looking for its first Ivy Title in the program's history and having gone 1-4 in last year's edition of the Ancient Eight classic. Most recently the Bears went undefeated at the Eric Sollee Invitational defeating Brandeis, New York University, Johns Hopkins, Haverford and Hunter.
While Columbia has been the class of the Ivy League when it comes to fencing, having won 34 titles in the 74 years the championship has been played; the Lions struggled through last year's Ancient Eight championship going 0-5 in the tournament. 2012 has seen mixed results for the Columbia men as they have gone 6-7, most recently only coming away with one win in the NYU duals, defeating Wayne State, but falling to No. 4 Notre Dame, No. 5 Ohio State and St. John's.
Penn heads to the Ivy Championships with a ton of confidence after going undefeated in 16 matches this season. Two of those wins came against ranked opponents as the Quakers knocked off No. 8 Duke and No. 9 Sacred Heart. Penn placed third in last year's tournament going 3-2. The last time out Penn swept its competition at the Eric Sollee Invite defeating Brandeis, MIT, NYU, Boston College and Johns Hopkins.
The Tigers look to regain their throne after Harvard knocked off Princeton, the defending Ivy League champion headed into last year's tournament. The 2011 squad had a disappointing showing in the 2011 tournament going 2-3 placed fourth behind Penn. The 2012 team looks promising for Princeton as they have gone 14-2 so far this season and look poised for a run at the team's 14th title. The Tigers enter the championship riding four-game win streak defeating Detroit, Lawrence, Cleveland State and UC San Diego.
It was the Bulldog not the Tiger that would be nipping at the heels of the Harvard Crimson at last year's Ivy League tournament. The Crimson was able to fend off its Ivy League rival however, defeating Yale on the last bout and as Harvard went 5-0 to Yale's 4-1 mark. The Bulldogs look even more determined this year to earn its fourth Ivy title in program history, as its gone 9-4 so far during the 2011-12 campaign. Most recently Yale claimed victories over Vassar and Drew on Feb. 4, and has claimed wins against Boston College, UNC and NYU this season.


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OCEAN CITY – The City Council voted unanimously Tuesday approve the Beach Walk Hotel owner's request to apply for the Hazard Mitigation Grant Program (HMGP), which will allow for the elevation of the flood prone building.
Beach Walk Hotel owner Danelle Amos, Planner Robert W. Nelson and Grants Coordinator Wayne Pryor came before the Mayor and Council at Tuesday's work session to discuss the Maryland Emergency Management Agency's (MEMA) program that could provide 75 percent of the funding necessary to raise the building.
According to the FEMA-regulated HMGP website, "the HMGP provides grants to states and local governments to implement long-term hazard mitigation measures after a major disaster declaration."
The program seeks to provide funding to areas after disasters such as flooding. In 2000, the national plan was implemented and trickled down to the local level in July 2004, when the Ocean City HMGP was approved.
The website defines the purpose of the grant program as "to reduce the loss of life and property due to natural disasters and to enable mitigation measure to be implemented during the immediate recovery from a disaster."
Nelson explained that HMGP projects could be funded for acquisition, retrofitting, or elevation. Acquisition applies to real property for willing sellers and demolition or relocation of that properties building to be used for open space. Retrofitting structures helps to minimize damages from high natural hazards. Elevation of buildings or structures, which is what Amos will be applying for, is established for flood prone structures, such as the Beach Walk Hotel.
Pryor explained to the Mayor and Council that although the grant involves a 75/25 split, with 75 percent coming from the HMGP, the city would not be liable for matching the 25 percent.
Nelson informed the council that the grant could be applied to public or to private properties and that all jurisdictions in Maryland were qualified for the $1.25 million grant.
Currently, six applications have been submitted for the HMGP, with Amos included as one of the six.
Pryor explained that although the city was needed as the vehicle for the request, time constraints had made it necessary to turn in the application prior to the city's consent. Pryor assured the Mayor and Council, however, the application could be pulled from review.
Although counties are prioritized each year for the grant money, no applications had been filed yet from the counties with higher priority, placing Amos as an equal candidate.
The Beach Walk Hotel, located on 10th Street, 150 feet from the ocean, is currently valued at $1.77 million as of Jan. 1. If the elevation is approved, Amos will have three years to use the money awarded. Nelson added that the process would be documented for future applicants and used as a model for the town.
Nelson listed the possible affects as, bringing the building to compliance with the building and fire codes, protecting the structure from flooding as well as avoiding repetitive loss from flooding.
If chosen, the property will be the first private property mitigation effort in Ocean City. Although the potential height elevation has not been set yet, Amos estimated that the building would be raised 10 to 12 feet.
The Mayor and Council showed no objections to the effort, approving the request unanimously.


text:
COOLER temperatures are on the way after a wave of thunderstorms and torrential downpours swept parts of Britain.
Intense storms, including hail and strong winds, brought flash floods across large areas of the UK after temperatures peaked at 31.4C in London Heathrow on Wednesday.
Yorkshire escaped the worst of the storms, but in the Western Isles, 31mm of rain fell in an intense burst in the morning, the Met Office said.
Temperatures are due to drop to between 18C and 26C over the coming days, bringing relief for those struggling in the heat.
Met Office meteorologist Alex Burkhill said: "The highest we have seen is 31.4C at Heathrow, which was not quite as warm as Tuesday but not that far off, it was still quite a warm day.
"Most of the thunder moved through the north of the UK but there is still the potential for more showers to kick off.
"Thursday is not looking bad, there could be some showers dotted here and there and then some more showery rain going into Friday.
"The weekend will not be terrible, although not as hot as it has been - there will be bright and sunny breaks when it will be quite warm."
Tuesday was the hottest day of the year so far, when the mercury reached a sweltering 33.5C in Brize Norton, Oxfordshire.
The heatwave is feared to have cost several people their lives and led to an outbreak of violence in London.
Jack Pullen, 16, died while playing with friends in the River Etherow near Hyde, Greater Manchester, on Tuesday.
A 46-year-old man died after jumping into a canal in Burton-on-Trent on Monday night.
A body was recovered from Lammas Lake in Wraysbury, Surrey, on Tuesday evening after police received reports of concern for the safety of a man in the water. Officers were uncertain if the death was weather-related but said the man was with a group of people at the time.
Soldier Josh Hoole, from Ecclefechan near Lockerbie in Scotland, died in Brecon while on a training exercise earlier that day.
The 26-year-old member of The Rifles regiment, stationed at Catterick in North Yorkshire, was on pre-course training for the Platoon Sergeants' Battle Course.
Stifling conditions in London led to an outbreak of disorder at a water fight in Hyde Park as three people, including a police officer, were stabbed, while four officers and a member of the public suffered other injuries.
Thursday's forecast for Yorkshire
Morning sunny spells will lead into a largely fine day, perhaps giving way to isolated showers during the afternoon. Temperatures should not reach recent highs, but should still reach the low twenties degrees Celsius in places, with light winds throughout.
Thursday night
Showers should die away for a time, however cloud amounts should increase later, eventually giving showery rain in places. Temperatures should remain on the warm side given cloud cover.
A little cloudier than recent days, with a little showery rain possible. Becoming brighter later, with isolated sharp showers and more in the way of sunny spells.
Weekend and Monday
Fresher-feeling than recently, but still warm, with Saturday probably the brighter of the weekend days. An area of rain is then expected to move erratically eastwards, before brightening later Monday.


text:
Colorado State gets safety Jyaz Jones back in the fold
He's back.
Initially a Colorado State pledge, safety Jyaz Jones of South Oak Cliff High School in Dallas re-committed to the Rams, according to Rivals.com's CSU-based website GoldAndGreenNews.com.
Jones (6-foot-1 and 180 pounds) had switched from CSU to Iowa (where his brother plays) during the fall. But Jones missed most of his senior season with a variety of injuries and Iowa recently gained the commitment from a high school safety in Washington D.C.
National signing day is Wednesday, and Jones is expected to join another South Oak Cliff player, defensive end Silvester Hayes, among CSU's signees.
Entering the 2013 season, Jones had been rated among the top defensive backs in the state of Texas. He has run the sprints for the track team and recorded five interceptions in 2012 as a junior.
If Jones regains his prior form, he likely would be considered one of the prizes of the Rams' recruiting class.


text:
The definitive iPhone app for learning about and touring Normandy, France, and D-Day sites.
Name: Normandy D-Day 1944
Available for: iOS
What it does: Offers practical travel tips and historical information for visiting the five invasion beaches, pluus 100 other locations throughout Normandy. The information is categorized and color-coded by topic: museums, battlegrounds, memorials, cemeteries, and historical interest.
Cost: $4.99
What's hot: The content was written by journalists who specialize in battlefield tourism, and every location has been visited and researched by the developer, On the Spot Locations. There are also 500 photographs you can zoom into. You can access the information offline and use it online as well (but watch out for roaming troubles). Make sure you take advantage of the "Favorites" section so you can plan your trip in advance.
What's not: It took me a long time to load the app. It is more than 50 megabytes, and you need a Wi-Fi connection to download it. Make sure you do this at home before you take off on your trip. It will save you time and, most likely, be quicker than using the hotel Wi-Fi.
Worth it: Pricey, but it's a great way to learn about the Normandy landing. It's also good for assisting with school history projects or homework.


text:
I fully realize that last week I was bashing modern technology and talking about how out of place I sometimes feel. But today, I'm going to turn that statement right on its head.
Isn't facebook sometimes just so incredible? I mean, sure, I can easily lose hours of my life to looking at photos of old friends who I haven't seen since grade 3. (In fact, as I was typing this I thought of someone from grade 3, opened a new tab and spent 15 minutes looking at old photos of them. Yup, big time sink).
BUT! But, it can also be surprisingly wonderful. For example, 2 weeks ago I was scrolling through my newsfeed and there was a wee little note from the Wise Daughters Craft Market.
"This table loom available to the first person who emails me and promises to make a donation to Japan relief via charity of their choice."
Of course, I emailed right away. From two different accounts.
Sadly, I wasn't the lucky first respondent, but not long after, an email from Mary was in my inbox offering me a second table loom that she had kicking around. What luck!
This weekend, with a big, empty house to myself, I decided to learn how to weave. It went a little something like this…
- A loom. If you don't have a friend willing to give you one, you can check out this great video to learn how to make one from some slabs of wood or a big frame
- Yarn of various colours
- String or hemp
- Scissors
- A chopstick
- A ruler (or in my case, some ruler-sized pieces of cardboard)
- To start, you need to string your loom. Starting on the bottom rung, tie your string/hemp in a double knot. Bring the yarn up away from you and over the top rung. Then bring it back towards you and under. This sounds confusing right? Basically, you want to make a series of figure eights.
- I did 15 or so, then tightened up each strand, and tied it off on the bottom rung. This is your warp.
- A little note – you can also use yarn for your warp (as is shown in these early photos). Unfortunately, mine started to fray a lot, constantly breaking and making the weaving insanely difficult (see photo below). I then decided to switch to hemp, which worked super well. Experiment around and let me know what works for you!
- Another little note. You want to make sure your threads are pretty close together, and evenly spaced.
- Now, if you look down the side of your loom, you should see all the threads in their figure eight pattern. Insert your chopstick between the front threads and back threads, near the top of your loom and pull the chopstick down towards the bottom of the loom. This will increase the tension in each thread, and bring the X where the figure eights cross down towards the bottom of your loom. Leave your chopstick there.
- The weaving itself is quite simple. Just like the woven placemats and the baskets, weaving is an in-out-in-out pattern. If you manually threaded your yarn in and out of each strand of the warp, it would take forever though. That's where the loom comes in. Take your ruler and slide it between the front and back threads, just like you did with your chop stick. Then turn the ruler 90 degrees, so that it's parallel with the table. This will open up a tunnel-like space between the front and back threads. Take a long piece of yarn and pull it through the tunnel, leaving a three inch tail at one end.
- The next row is essentially the same technique, except you want to bring the back threads of the warp to the front and vice versa. Take your ruler and weave it through the warp, doing just this – bringing the threads at the back to the front, and forcing the front threads to go to the back.
- Just like last time, turn the ruler 90 degrees, opening up that tunnel and pass your piece of yarn back through the tunnel. Pull your yarn down to the bottom of your loom, so that it is right on top of the previous thread. Then turn the ruler back to being perpendicular with the table and use the rulers edge to push the stitches down close to each other.
- Keep repeating this pattern over and over again. You can change colours. You can create patterns. Pretty much anything is possible.
- The only issue with using a loom of this size is that (from what I can tell) you can only make items as large as your loom. This is why full sized looms take up whole rooms! My dreams of making a table runner aren't going to quite come true with this, but a table runner for a doll house? A book mark? A doormat even? Those are all totally possible.


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AES10 specifies 62.5/125, or OM1, fiber for use with MADI. However, 50/125 fibers has advantages in bandwidth and distance and is now much more standard than the "old" OM1 standard. I'm not too well versed in fiber, so I'm reticent to use any other cable than what's recommended in the standard, but it would be good to be able to run other things down a fiber installation in the future, such as video.
Will MADI run on 50/125 - OM3 - fiber? Or equivalently, is fiber "backwards-compatible" so to speak?


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Arena football is different. It's the kind of sport where a fan reaches out of the seats to bodily prevent an opposing player from returning a kickoff. And more tellingly, it's the kind of sport where the home team's players then go over to congratulate the fan for interfering with play.
The Jacksonville fan wasn't ejected, but the refs huddled and decided to give Georgia the ball on the 20. I'm not sure what penalty covers this situation — perhaps illegal use of the fans? (Oh, that's awful. Sorry, it's comedy week.) Seattle's 12th man looks like a giant pussy now, as Jacksonville won the game and advances to Arenabowl XXIV.


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The offender must be convicted of a crime that is by its nature a sexual offense, such as:
* O.C.G.A. 16-6-2 Sodomy (against a minor); Aggravated Sodomy (against a minor or an adult)
* O.C.G.A. 16-6-3 Statutory Rape (unless the age of the perpetrator is 18 years of age or younger)
* O.C.G.A. 16-6-4 Child Molestation; Aggravated Child Molestation
* O.C.G.A. 16-6-5 Enticing a child for indecent purposes
* O.C.G.A. 16-6-22.2 Aggravated Sexual Battery
In relation to crimes where the victim is a minor, O.C.G.A. 42-1-12 includes the following offenses under (a)(4)(A):
* (i) Kidnapping of a minor, except by a parent
* (ii) False imprisonment of a minor except by a parent
* (iii) Criminal sexual contact toward a minor
* (iv) Solicitation of a minor to engage in sexual contact
* (v) Use of a minor in sexual performance
* (vi) Solicitation of a minor to practice prostitution
* (vii) Any conduct that by its nature is a sexual offense against a minor
In order for an offender to qualify for registration in the state of Georgia, the offender must either be released from prison or placed on probation, parole or supervised release after July 1, 1996. If an offender who is registered in another state moves to Georgia, the offender is required to register in the state of Georgia.
O.C.G.A. 42-1-12 (i)(3) states "the Georgia Bureau of Investigation or any sheriff maintaining records required under this code section shall release relevant information collected under this code section that is necessary to protect the public." However, due to the fact this information is continually changing, the Walker County Sheriff's Office makes no expressed or implied guarantee concerning the accuracy of this information.


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The Times of India Directory and Year Book Including Who's who
Sir Stanley Reed
Bennett, Coleman., 1922 - India
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Aug. 7, 2006
The Atlantic Sun Conference has announced members of the All-Academic Team for spring sports for 2006.
To qualify a student-athlete must have a minimum 3.0 grade point average in the semester when their respective sports is played.
Lipscomb athletes honored are:
Baseball: David Ayre, Jordan Baron, Jeff Baumgartner, David Becker, Bret Burgess, Preston Embrey, Ryan Mitchell, Cody Morris, Patrick O'Rourke, Jared Pichiottino, Paul Pienette, Nathan Sensing, Robby Smithson and Charles Williams.
Softball: Anna Cleland, Heather Collins, Julia Davidson, Kimberly Jacobson, Leigh Little, Allison Tyree, Ashley Villalpando and Jessica Wilson.
Men's Golf:Josh Dyer, Luke Ficken, Cody Hale, Blake Lannom, Taylor Lewis, Dustin Lynch, Cory Parkinson, Zachary Pharr, Paul Warren.
Women's Golf: Elizabeth Austin, Ashlee Catlin, Marie Fillers, Callie Rice.
Men's Tennis: Colten Jones, Andrew Mizell, William Murrell, Brent Taylor, Jeffrey West.
Women's Tennis: Jamie Aid, Emily Ellis, Olivia Ellis, Casey Hall, Erin Moakler, Mary Beth Muncher.
Men's Track and Field: Timothy Cotton, Weldon Ehlert, Caleb Key, Joe Lohr, Chris Lucas, Matthew McWhirter, Jordan Wilson, Zac Yanis.
Women's Track and Field: Candice Cox, Jill Dyer, Danielle Graham, Paige Griffin, Kelly Houff, Ruth Mick, Elizabeth Schall, Samantha Wood, Susan Worden, Amanda Wright.


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Isla Mágica Theme Park
In Seville you will find the city you're looking for: inviting, with numerous parks for children, and always ready to have fun. Its most popular attractions include the rides and shows in the Isla Mágica park, with its incredible themed settings such as the realm of the pirates, Eldorado and the Maya civilization. Don't miss a day at Seville's water park, and a visit to see the animals at the Zoo.
Other options include a boat trip up the Guadalquivir river so you can see the city in comfort, or a ride around the large urban María Luisa park in a horse-drawn carriage. The park is full of fountains; the younger visitors can watch the pigeons, while the Plaza de España square, right next door, is much loved by everyone. Above all when they find out that several scenes from the film "Star Wars" were shot here.
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SeedingUp International
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Digital content marketing available immediately on SeedingUp.com
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Manage your teliad offers and bookings starting today on SeedingUp, the new web platform for digital content marketing and seeding.
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text: ShareVeteransWelcomeRivier University is committed to working with veterans to help them take full advantage of the benefits they have earned. G.I. Jobs magazine has named Rivier a military friendly school, placing us in the top 15% of colleges, universities and trade schools in the country in working with veterans. We'll help you navigate the admissions and enrollment process as smoothly as possible. We recognize that veterans have a great deal of experience that can translate to college credit: we participate in the CLEP program and accept DANTES and PONSI credits, reducing the time it takes to earn your degree. The Veterans Coordinator for Rivier University is:Sr. Joan JoyalRegistrar's Office(603) firstname.lastname@example.com


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I don't know if you guys consider this a full dinner, but at the very least, this is one of my absolute favorite snacks. I can almost never resist a portobello anything on a restaurant menu — whether it's a salad, burger, or a delicious combo like this!
Chad and I have spent a good deal of the last few weekends househunting (basically everytime we're not working or committed to something else) and it's a long, intense process that so far isn't even close to finishing.
Have any of you guys gone through it? We had a few places we were considering, and they've inevitably sold before we could even decide whether to make an offer! I guess it's good news for the economy, but it's a little stressful for us.
Fingers crossed that we find something soon! I'm really looking forward to living in one place for more than 3 years in a row — I haven't since I was 17!
Portobello Mushroom "Pizza"
4 portobello mushroom caps
8 ounce can store-bought pizza sauce
1/4 cup freshly grated Parmesan cheese
8 ounces mozzarella cheese (pulled apart or thinly sliced)
Preheat oven to 350. Spray rimmed baking sheet with non-stick spray. Clean mushroom caps with paper towel and remove stems. Spoon 1/4 cup tomato sauce into cap. Layer parmesan cheese and then with mozzarella cheese. Bake in oven for 20 minutes. Add two small basil leaves as a garnish. Serve warm.


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All H&R Sway Bar kits have been shot peened and heat treated, and feature
precision forged ends - many applications have multiple end link mounting points
for adjustability. Also included are H&R exclusive bushings made from a Urethane
/ Teflon composite that eliminates squeaks, and don't require lubrication. Ever.
That means no mess, no maintenance-just bolt in H&R Sway Bars and go!
Like all H&R components, H&R Sway Bars are 100% made in Germany, and are
powder coated for long lasting good looks and durability on the street and
About Sway Bars
Suspension tuning doesn't stop with the springs and shocks. To really get your
car dialed in, you'll want to look at a wide range of other components in your
arsenal, including swaybars. Most modern performance-oriented vehicles now come
stock with sway bars. The main purpose of a sway bar is to make the outside
springs seem stiffer in a corner which is ideally what you'd want for the
best performance.
Swaybars are used to counterpart the lean and roll you experience from your
springs. If you are seeking flatter cornering with less wallowing in the turns
then you should definitely be considering sway bars as a crucial upgrade to your
car's suspension components. Sway bars are also often available with adjustment
holes in the end link mounting tabs, which prove to be a useful tool for dialing
in the handling attitude of the car, from understeer to oversteer.
The beauty of upgrading to stiffer sway bars is that they not only have a
minimal impact on ride quality, but also they allow the use of softer springs
so that a car can be set up for a cushier around-town ride and a flatter
cornering attitude. Stiff springs and a very stiff sway bar can reduce body roll
so much that the car's breakaway is hard to predict. Roll gives you some warning
before you run out of grip. Most sway bars can be installed with basic hand
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Make a tee time reservation at one of our great golf courses!Member Tee Times Public Tee Times
Escape to the mountains for a nature-inspired experience at Glade Spring Spa, located in Suncadia Resort. Featuring outdoor mineral salt water soaking pools, steam rooms, saunas and sanctuary relaxation lounges, this 9500 sq. foot spa offers massage, skin care, body treatments, manicures, pedicures (natural nails) and spa cuisine.Make an Appointment
Make a reservation at one of our amazing restaurants!Reserve at Portals Restaurant
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