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2011, 1(2), 277-302; https://doi.org/10.3390/jlpea1020277
Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design
VIRTUS, School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, Singapore
Shobhit University, Meerut 250110, Uttarpradesh, India
Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering Indian Institute of Technology Roorkee, Roorkee 247667, Uttarakhand, India
Author to whom correspondence should be addressed.
Received: 16 May 2011; in revised form: 29 June 2011 / Accepted: 30 June 2011 / Published: 8 July 2011
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.
Keywords:device/circuit co-design; subthreshold logic; ultra low power; asymmetric DGMOSFET; independent gate DGMOSFET; high efficient rectifier for RFID
1. Introduction
One of the primary motivations behind switching technology from bipolar transistors to MOSFETs is that the low power consumption of CMOS circuits along with small size makes integration possible. MOSFETs combined with technology scaling made the IC industry successful because of the reduced power, reduced area, increased speed, and low cost per chip. As the number of transistors that are integrated per chip increases, problems like leakage current, power dissipation, heat removal, cooling techniques, and reliability have been raised. These have increased the demand for power-constrained or energy-constrained design for modern VLSI systems in contrast to previous clock speed driven systems. In addition, there is an increasing class of applications like portable electronics, micro sensors, radio frequency identification (RFID), and implantable biomedical devices, which demand ultra-low power consumption and prolonged battery lifetime. All of these concerns on power reduction motivated the designers to come up with power reduction methods such as supply voltage scaling [1,2], switching activity reduction [3,4], architectural techniques of pipelining and parallelism, computer aided design (CAD) techniques for device sizing and interconnect [5,6], logic optimization [7,8], etc. Among these techniques, the most successfully proven method is the supply voltage scaling, which significantly reduces both active and static components of power. An extreme case in supply voltage scaling is the subthreshold operation where the supply voltage is less than the threshold voltage of devices. It has been proved that minimum energy per operation is achieved by operating circuits in the subthreshold region [9–18]. Sub-threshold circuits operate with a supply voltage that is less than the threshold of the transistors—far below traditional levels and consequently the transistors operate essentially on subthreshold current. While traditional digital logic has relied on running transistors either in the ON state (strong-inversion) or OFF state (subthreshold), sub-threshold circuits are either in an OFF state or a weak-OFF state (still in sub-threshold regime but with weak inversion). Even though subthreshold operation is limited in performance, it remains acceptable for low to medium performance and energy efficient constrained applications such as RFID, wireless micro sensors, biomedical implants, etc.
RFID tags operate in several bands—high-frequency (HF), ultra-high-frequency (UHF) and microwave bands. Transponders that operate at 125 kHz [19] and 13.56 MHz [20] have been deployed for a number of years. Their disadvantage is limited range. Passive transponders that operate in the UHF band have ranges of 7.5–9 m [21,22], and transponders that operate in the microwave band have ranges under 2 m. Karthaus et al. reported a low power RFID chip for UHF with low power consumption. This is achieved by the combination of pulse width modulation on the forward link (base-station to tag) with low RF-off times (no excess voltage droop on the on-chip power capacitor) and phase-shift keying (PSK) on the return link (tag to base-station) [22]. A high level description of a passive RFID chip that implements the EPC Class 0 protocol is provided in Glidden et al. [23]. De Vita et al. provide design criteria for the front-end of passive RFID tags [24]. While the range for passive RFID tags at UHF and microwave is adequate for some applications, greater range is strongly required. Active transponders provide greater range, but they require a battery and accordingly have a limited lifetime. Furthermore the battery should have a small form factor so that it can be seamlessly used in the assembly process for large volume production. The long lifetime (usually in excess of 10 years) and the small battery capacity require ultra-low power consumption on the active transponder to work throughout the full life of the tag.
Various research about CMOS front-ends and CMOS technology for RFID has been published [25–29]. However, very few have considered double-gate MOSFETs (DGMOSFETs) for the ultra low power RFID tag design. While digital system design has continually pushed for the increased speed of minimum size devices, analog designers have often employed longer channels to avoid short channel effects (SCEs) and achieve higher voltage gain. As analog devices are scaled into the nanometer regime, CMOS technologies will require innovative device architectures and design techniques to achieve excellent analog metrics. The usefulness of nonclassical underlap channel architecture to enhance both gain and bandwidth of an OTA, alleviating gain-bandwidth trade-off associated with analog design, has been demonstrated in [30]. Kumar et al. [31] explore applications of independently driven DGMOSFETs (IDGMOSFETs) for low-power and low-voltage analog integrated circuit design. In back-gate configuration, the second gate of DGMOSFET can be used to tune the threshold voltage of the device. A simple and cascode current mirror based on bulk-driven transistor is redesigned with DGMOSFETs and shown to have smaller input voltage drop and lower power consumption. Capability of dynamic threshold tuning is exploited to design an adaptive two-stage operational amplifier (op amp) which can operate at voltages as low as 0.5 V without sacrificing performance parameters.
Freitas et al. [32] explored new capabilities brought on by IDGMOSFETs for analog baseband design. Since the two gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current mirror is redesigned using IDGMOSFETs and it is shown that this structure performs an efficient differential function relating to the potentials applied to the back gates. Being adapted to low-voltage operation and self compensated from input common-mode variations, the differential current mirror is employed for the active loading of a low-voltage fully balanced OTA. Mohankumar et al. investigate the influence of both channel and gate engineering on the analog and RF performances of DGMOSFETs for system-on-chip applications [33]. The gate engineering technique used here is the dual metal gate technology, and the channel engineering technique is the conventional halo doping process.
Much work has also been done to investigate the scope of various multi-gate MOSFET structures. Several implementations of multi-gate structures include Depleted Lean-channel TrAnsistor (DELTA) [34,35], Gate-All Around device (GAA) [36], Silicon-On-Nothing (SON) MOSFET [37–39], Multi-Fin XMOS (MFXMOS) [40], triangular-wire SOI MOSFET [41], n-channel SOI MOSFET [42], quadruple-gate or surrounding-gate devices having a width-to-height ratio much closer to unity [43–46], quantum-wire SOI MOSFET [47,48] trigate MOSFET [49,50], CYNTHIA device (circular-section device) [51,52], pillar surrounding-gate MOSFET (square-section device) [53], planar surrounding-gate devices with square or circular cross sections [54–58]. Although, theoretically surrounding gate MOSFETs might be better suited for subthreshold logic, but at the present stage of research, as per ITRS long term goals, DGMOSFETs probably will replace the existing bulk CMOS in the near future and bulk CMOS scaling trends are not even further included in the ITRS long term goals. With this view, this work focuses on DGMOSFETs for optimal ultra-low power subthreshold circuit design.
In this paper, we will explore the scope of tied/independent gates and symmetric/asymmetric gates of DGMOSFETs with circuit co-design for robust ultra-low power RFIDs. The remainder of this paper is organized as follows. Section 2 presents the background of ultra-low power RFIDs. DGMOSFETs for robust and ultra-low power subthreshold circuit design and comparison with nano-scale bulk CMOS are described in Section 3. Various DGMOSFET configurations with circuit co-design for ultra-low power subthreshold logic design are presented in Section 4. Section 5 describes the implementation of energy-efficient ultra-low power RFID rectifier circuits with various DGMOSFET configurations. Finally, conclusions are offered in Section 6.
2. Background of Ultra-Low Power RFID Design
2.1. General Architecture of RFID Tag
A RFID tag is simply a transceiver (transmitter + receiver). The main difference between the RFID tag and the traditional transceivers is the passive operation, i.e., there is no battery to supply DC voltage to the chip. For this reason, a rectifier for supplying DC voltage is required. A block diagram of a RFID tag is shown in Figure 1. The rectifier block rectifies the input RF signal and generates the needed DC voltage to power the other blocks of the system. The demodulator block acts as a receiver that detects commands sent by a RFID reader. It also extracts the clock from the received RF signal, which is needed to synchronize the RFID with the RFID reader. The control logic block is the digital part of the system which controls all other blocks of the system. It determines when to receive, when to transmit and when to remain idle. It also stores the ID of the tag which is sent to the RFID reader by the modulator. The Internal clock block supplies an internally generated clock to the digital part. The modulator block acts as the transmitter of the system which sends the tag ID to the RFID reader. Decreasing the power consumption of the RFID tag is achieved generally through three ways: (a) Increasing the conversion efficiency of the rectifier, (b) Reducing the power consumption of the RFID tag blocks, and (c) Choosing a suitable communication scheme between the RFID reader and the RFID tag.
2.2. Scope of Weak or Moderate Inversion for RFID Design
The key metrics for RFID design include the transit frequency, the maximum frequency of oscillation, and the minimum noise figure. Moderate inversion or weak inversion operation offers a good trade-off between power consumption, low-voltage operation, noise, and linearity, all being of major importance for designing RFIDs. Several advantages to bias the transistor in moderate or weak inversion [18] for RFIC design are as follows.
- Increase of the current efficiency (measured by the Gm/ID ratio) which results in a further reduction of the power consumption.
- Decrease of the bias voltages results in lower electrical fields within the device. This avoids velocity saturation and hot electron effects. Having no velocity saturation results in transit frequency scaling as 1/L2 compared to only 1/L when velocity saturation is present. This means that scaling is more effective for devices biased in the weak and moderate inversion region than in strong inversion.
- Having no hot electron effects avoids the increase of the noise excess factor.
- The reduction of the bias voltages better accommodates the use of low supply voltages that are imposed by the scaling of UDSM technologies.
3. Double-Gate MOSFETs (DGMOSFETs) for Ultra-Low Power Subthreshold Circuit Design
3.1. Introduction of Double-Gate MOSFETs (DGMOSFETs)
Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a double-gate SOI structure (Figure 2a). Due to the excellent control of the short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50 nm regime [59]. Low subthreshold leakage and higher ON-current in the double-gate devices make them suitable for circuit design in sub-50 nm regime [60,61]. One of the promising structures in the double-gate technology is FinFET [62] due to the simple fabrication process (Figure 2b). Double-gate devices with isolated gates (independent gates) are being developed [63,64]. The independent gate option can be useful for low power and mixed signal applications [64–69]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. ITRS reports also show the inevitable inclusion of DGMOSFETs in upcoming VLSI applications [69].
DGMOSFETs for optimal subthreshold operations have also been considered recently [70–76]. DGMOSFETs are suitable for the sub-threshold operation due to their near ideal subthreshold slope and negligible junction capacitance. Due to the thin, fully depleted silicon body sandwiched between two gates, these devices have an excellent gate control over the channel. Furthermore, the undoped thin silicon body provides negligible source/drain p-n junction capacitance, which largely enhances the circuit performance. In general, DGMOSFETs have the following advantages over bulk CMOS technology:
- Nearly ideal subthreshold slope.
- Small intrinsic gate capacitance.
- Smaller junction capacitances.
- Better immunity to SCEs, although negligible for subthreshold operation.
- Reduced Random dopant fluctuations (RDF) due to undoped or lightly doped body and reduced carrier mobility degradation.
- Higher ION/IOFF ratio.
- Design flexibility at circuit level by symmetric/asymmetric with tied and independent gate options.
3.2. Comparison of Bulk CMOS and DGMOSFETs for Ultra-Low Power Subthreshold Circuit Design
3.2.1. Bulk CMOS and DGMOSFET Device Model Parameters
The international technology roadmap for semiconductors (ITRS), which maps out near- and long-term goals for the semiconductor industry, describes three different devices with different power delay tradeoffs: high performance, low operating power (LOP), and low standby power (LSTP). The LOP and LSTP devices are optimized in a similar manner, although the LSTP device has more stringent leakage constraints. We take bulk CMOS device parameters following [77], in which the authors follow the scaling strategy similar to that of the LSTP device. The scaling strategy is briefly described as follows: The device model has four key scaling parameters: physical gate length (Lpoly), gate-oxide thickness (Tox), substrate doping (Nsub), and peak halo doping (Np,halo). These parameters are most important when determining key device characteristics like Vth, on- current, off- current, and gate capacitance. In addition to these four parameters, Vdd is also used as an additional knob for adjusting performance. All physical dimensions other than Tox (source/drain junction depth, lateral source/drain diffusion, halo dimensions, etc.) scale in proportion to Lpoly. Lpoly is reduced by 30% per generation, which agrees well with recent Lpoly scaling trends. A survey of recent industrial publications shows that Tox has been reduced by ∼10% per generation below the 130 nm technology node [77]. In this strategy, simple assumption that Tox reduces by 10% per generation has been made. With Lpoly and Tox fixed for each generation, the remaining three parameters (Nsub, Np,halo, Vdd) may be tuned to match delay and leakage requirements. The optimization procedure uses delay (τ) as an objective and leakage (Ileak,max) as a constraint (it allows leakage to grow by 25% each generation, reduces Vdd regularly at each generation to control dynamic energy, and optimizes the device for minimum delay under the leakage constraint).
The parameter values for the NFET model at 32-nm node obtained are shown in Table 1. We have considered these device values for our simulations as they are more suitable for low power applications. As for subthreshold operation, since high performance is of secondary importance and low power is of primary concern, we considered the above-mentioned device values given in [77] at 32 nm and generated different SPICE model files for parameter variations from a specific tool called "Nano CMOS" [78] for carrying out simulations. HSPICE simulations have been carried out by setting the above device parameters for 32 nm technology in the Berkeley Predictive technology model [78] by varying different parameters and generating different SPICE model files for each set of parameters.
A compact model for DGMOSFET, akin to the BSIM model for a bulk CMOS and BSIM SOI for a SOI transistor, is not available for the purpose of circuit simulation and technology prediction. Currently, early designs with DGMOSFETs have to resort to the TCAD simulators (MEDICI, Sentaurus, ATLAS, etc.), which are computationally expensive and limit design flexibility. To overcome these barriers, an equivalent subcircuit model for a DGMOSFET device has been proposed in [79]. This circuit model consists of two fully depleted SOI devices for the front and back transistors, respectively. BSIM SOI is used as the model for each device such that this subcircuit is compatible with standard circuit simulators (e.g., SPICE). Two single-gate transistors are used to capture the current conduction controlled by the front and back gate in a DGMOSFET transistor. Each subtransistor has its own definitions of gate voltage (VG), Vth, and Tox. Their sources and drains are electrically connected to form a four-node circuit. Thus, the drain voltage (VD) and the source voltage (VS) are shared. Both subtransistors have the same gate length and width. Since the bottom of a DGMOSFET structure sits on top of a layer of SiO2, the DGMOSFET is inherently an SOI transistor. Furthermore, in the typical process range of a DGMOSFET, Tsi is so thin that the silicon body is fully depleted. Therefore, the fully depleted SOI model of BSIM (BSIM FD SOI) is used as the model basis for each subtransistor. More information about the DGFinFET device model can be found in [79].
To verify the accuracy and flexibility of predictive technology model (PTM), more than thirty sets of IV data at room temperature are collected from publications in [79]. Using the published values for technology specifications (i.e., Leff, Tox, Vth, Rdsw, and Vdd), process and physical parameters are calculated to generate corresponding PTM model files. Predicted I-V characteristics are compared to published data for verification. Even though the DGMOSFET technology is still at an early stage of technology development and thus, shows large divergence in the technology definitions, PTM is flexible enough to capture these process uncertainties. The excellent predictions prove the physicality and scalability of new PTM. HSPICE simulations have been carried out for DGSOI circuits constructed with these devices and compared with bulk CMOS circuits for subthreshold logic.
3.2.2. Comparison of Bulk CMOS and DGMOSFETs
Table 2 summarizes the performance comparisons of DGMOSFET and bulk CMOS circuits for subthreshold logic [14]. We observe that the DGMOSFET inverter power-delay-product (PDP) is approximately 70% lower than the bulk CMOS inverter and 65% lower than the pseudo NMOS inverter. Other logic gates based upon DGMOSFETs have 30–40% better energy efficiency (lower PDP) than equivalent bulk CMOS logic gates in the subthreshold operation, due to the advantages of DGMOSFETs summarized in Section 3.1. Figure 3 compares the variation in the PDP of the DGMOSFET and bulk CMOS circuits with regard to temperature, where better performance and robustness of DGMOSFET subthreshold circuits can be seen. The variation in the PDP of the DGMOSFET and bulk CMOS circuits with respect to supply voltage within the subthreshold region is illustrated in Figure 4 [14]. We also observed that a bulk MOS inverter has relatively poorer robustness in terms of noise margins and functionality compared to the equivalent DGMOSFET inverter as supply voltage scales down. It can be inferred that the suitability of DGMOSFETs for subthreshold logic compared to the bulk CMOS technology shows the possibility of scaling down of supply voltages within subthreshold region without threatening the functionality of circuits for supply voltage as low as 75–100 mV. Figure 5 summarizes the device and circuit level implications of the threshold voltage fluctuations on the bulk CMOS and DGMOSFET technologies. It can be seen that DGMOSFET is the better option for most performance metrics (almost 50% better robustness).
4. Comparison of Various DGMOSFET Configurations for Ultra-Low Power Subthreshold Circuit Design
4.1. Introduction of Various DGMOSFET Configurations
DGMOSFETs can either have a three-terminal (3T) configuration, where both the gates are shorted, or a four-terminal (4T) configuration, where the back-gate bias is fixed and the front gate acts as a control electrode. If the two gates in the DGMOSFETs are tied (3T), an identical voltage can be applied to both gates. Conversely, when the two gates are independent (4T), different voltages can be applied. The asymmetry in the double gate MOSFET can be brought about by a number of ways. It can be done by applying different gate voltages to front and back gates, by assigning variation in oxide thickness to front and back gates. It can also be brought by varying gate material work functions. Independent gate technology offers an extra terminal in DGMOSFET devices at the cost of extra fabrication steps or masks. The extra feature of biasing back and front gates separately offers more flexibility and freedom to circuit designers using DGMOSFET technology. The 4T DGMOSFETs show reduced on-current along with reduced gate capacitance compared to the 3T counterparts. Moreover, 4T DGMOSFETs allow independent biasing of the two gates and offer dynamic threshold-voltage control (DTC) in circuits. Consequently, independent gate technology can be employed to help tradeoff between switching capacitance and leakage with circuit delay. Independent-gate operation benefits in circuits such as schmitt triggers, dynamic logic circuits, and sense amplifiers, and static random-access memory (SRAM) bit-cells as demonstrated recently [69–72].
In this work, we will investigate four types of DGMOSFETs: tied-gate symmetric DGMOSFETs (3TSDG), tied-gate asymmetric DGMOSFETs (3TADG), independent-gate symmetric DGMOSFETs (4TSDG) and independent-gate asymmetric DGMOSFETs (4TADG) as shown in Figure 6.
4.2. Comparison of Various DGMOSFET Configurations
HSPICE simulations have been carried out using Berkeley Predictive Technology Model (BPTM) for 32 nm DGMOSFET to study the symmetric DGMOSFETs (SDG) and asymmetric DGMOSFETs (ADG) devices and circuit performance with tied- and independent-gate options for subthreshold operation. In the following studies, we have primarily considered 4 cases: 3TSDG device (Vfg = Vbg = Vdd & Tfox = Tbox = 1.4 nm), 3TADG device (Vfg = Vbg = Vdd & Tfox ≠ Tbox), 4TSDG device (Vfg = Vdd, Vbg = 0 & Tfox = Tbox = 1.4 nm), and 4TADG device (Vfg = Vdd, Vbg = 0 & Tfox ≠ Tbox). The asymmetric nature of the device is being brought by taking the variation in oxide thickness for front and back gates. 3T implies that a front gate (fg) and a back gate (bg) are tied together to give the same potential while 4T implies front and back gates are applied different potentials. Device parameters extracted from the simulations are summarized in Table 3 [71]. 3TDG have better energy-delay product (EDP) performance metrics than 4TDG feature, due to the larger ION/IOFF ratio values. Asymmetric feature further enhances performance in the 3T option than in the 4T option.
Table 4 shows the comparison of 3TSDG and 3TADG performance for all basic gates and some simple combinational circuits [73]. We observe from the table that 3TADG circuits have approximately 13–14% better power consumption than 3TSDG, 4–5% better speed and 16–18.3% better PDP than 3TSDG based circuits. Table 5 shows the comparison of 4TSDG and 4TADG performance for all basic gates and some simple combinational circuits [73]. We observe from the table that 4TADG circuits only have approximately 0–0.5% better power consumption than 4TSDG, 0–1% better speed and 0.5–1% better PDP than 4TSDG based circuits. Comparison of Table 2 and 3 shows very poor power, delay and PDP performance of 4T option than 3T option for subthreshold logic, particularly as complexity of circuit increases.
Figure 7 shows the variation of ION/IOFF with body thickness for n- DG-MOSFET with different configurations in the subthreshold region of operation. From the figure it can be clearly observed that, in terms of having the highest driving capability, 3TADG is the best and 4TSDG is the worst. It is further observed that 4TSDG and 4TADG have similar pattern and better tolerance for the entire range, where as 3TSDG and 3TADG deviate more as body thickness is varied. Figure 8 shows the variation of subthreshold slope and EDP with varying supply voltage. We find 3T option having better subthreshold slope and EDP values as compared to 4T option in the entire range. Figure 9 compares the PDP variation of 3TSDG, 3TADG, 4TSDG and 4TADG devices with varying temperature in the subthreshold region of operation. Again, better robustness of 4TDG option as compared to 3TSDG and 3TADG option is observed.
4.3. Comparisons of Various DGMOSFET-Based Logic Families
In this section, we study the suitability of various logic families other than static CMOS for energy efficient subthreshold logic. NAND gates were designed with minimum sizing for functionality with various logic families and power, delay, and power delay product comparisons are done.
Table 6 summarizes the suitability of various circuit topologies for ultra-low power subthreshold operation with various configuration of DGMOSFETs [73]. For 3TSDG and 3TADG options, pseudo NMOS logic style shows to be worst in terms of power consumption and sub-CPL(complementary pass transistor logic) and sub-DCVSPG (differential cascode voltage switch pass gate) logic styles are worst in terms of delay. In terms of overall PDP, sub-CMOS shows to be the best option and sub-CPL, sub-domino and sub-DCVSL (differential cascode voltage switch logic) styles almost have a similar energy consumption. For 4TSDG option, in terms of power consumption, sub-CPL and sub-Domino logic styles shows to be better and all others have almost similar power consumption. In terms of overall PDP, sub-CMOS, sub-Domino and sub-SCVSL logic styles have almost similar and minimum energy consumption and sub-CPL and sub-DCVSPG shows to be extremely poor for 4TDG option for subthreshold logic.
5. Ultra-Low Power RFID Rectifiers with Various DGMOSFET Configurations
As the RFID tag is a passive system, DC voltage must be generated to bias the circuits of the tag, which is done by a rectifier. The rectifier converts a received RF signal into DC voltage. The main challenge in designing the RFID rectifier is to generate the required DC power using the low voltage amplitude of the RF signal with acceptable power conversion efficiency.
5.1. Various Rectifier Topologies Implemented with DGMOSFETs
5.1.1. Simple Rectifier
Power conversion efficiency (PCE) of a rectifier is defined by the output power divided by the input power. The PCE of the rectifier circuit is affected by circuit topology, diode-device parameters, input RF signal frequency and amplitude, and output loading conditions. Since the input RF signal of RFIDs in long-range operations is quite small, small turn-on voltage is the most important factor for the diode device. The Schottky diode has been utilized with a multi-stage configuration despite of the additional processing cost because of its small turn-on voltage. The rectifier circuit using the Schottky diode achieves a large PCE, but it is not compatible with the conventional CMOS technology and requires costly fabrication processing. Figure 10a shows a simple rectifier circuit implemented with 3T DGMOSFETs. Diode-connected n-channel and p-channel MOSFETs are connected in series and the internal node is connected to RF input terminal through the coupling capacitor (CC). The PCE is almost determined by the effective on-resistance of the diode-connected MOS transistor. The lower the threshold voltage of the MOS transistor is, the lower the effective on-resistance becomes. Therefore the higher PCE is obtained when the threshold voltage can be lowered. However, the threshold voltage cannot be lowered significantly since the PCE starts to be limited by the leakage current.
5.1.2. Self-Vth Cancellation (SVC) Rectifier
The PCE for a rectifier using a diode-connected MOSFET is generally worse than that of the Schottky diode due to its large threshold voltage (Vth), but when Vth cancellation techniques are utilized, the PCE can be increased dramatically. In order to reduce the effective turn-on voltage for achieving larger PCE, several Vth cancellation schemes have been proposed [80–83]. One uses a switched-capacitor technique to generate DC gate bias voltage from an external power supply [80] and others generate DC gate bias voltage from the output voltage of the rectifiers themselves [81–83]. Figure 10b shows self Vth cancellation (SVC) rectifier circuit implemented with 3T DGMOSFETs. It is the same as the conventional rectifier circuit described in the previous section except that gate electrodes of nMOS transistor and pMOS transistor are connected to the output terminal and ground terminal, respectively. This connection boosts gate-source voltages of nMOS and pMOS transistors as much as the output DC voltage. In other words, threshold voltages of MOS transistors are equivalently decreased by the same amount to the output DC voltage.
5.1.3. Differential Drive Rectifier
The PCE is roughly determined by the effective ON-resistance of the diode-connected MOS transistor and the minimization of the effective threshold voltage of MOS transistors results in a large PCE. However, when the effective threshold voltage of the MOS transistor is too small due to the excessive DC bias voltage, for instance, when it becomes negative, the MOS transistor is always ON and increased reverse leakage current cannot be ignored. If the reverse leakage current is not negligible, it directly results in energy loss since charges flowing in a reverse direction are simply wasted. Therefore, reverse diode loss rapidly increases. In addition, the forward current must be further increased to compensate the reverse leakage current, thus further increasing energy loss. As a result, it is concluded that we cannot achieve a small ON-resistance and a small reverse-leakage current at the same time by "static" Vth cancellation schemes. The differential drive rectifier is an "active" Vth cancellation scheme in which Vth can be minimized in a forward bias condition and be increased in a reverse bias condition automatically by a cross coupled differential circuit configuration [84]. Figure 10c shows the unit stage of the differential drive rectifier circuit with 4T DGMOSFETs and Figure 10d shows the differential drive rectifier circuit implemented with 3T DGMOSFETs.
5.2. Comparison of Various RFID Rectifier Topologies Using DGMOSFETs
The above mentioned rectifier topologies are simulated using HSPICE to analyze the best topology for ultra low power RFID design with highest PCE using DGMOSFET technology. The circuit parameters are as follows: CC = CS = 10 pf and RL = 10 kΩ, W/L ratio for minimum sized devices is 2 and upsized devices is 10, Wp/Wn = 2, f = 100 MHz. Comparison of DC output voltages generated by various rectifier topologies implemented with minimum sized 3T DGMOSFETs with variation in input levels is shown in Figure 11a. Conventional and SVC rectifier topologies have almost similar and lower output voltages in comparison to higher output DC voltage generated by the differential drive rectifier. As the RF input signal amplitude change from 0.1 to 0.9 V (for a power change of 0.5–365 μw), DC output power change by 0.5–139 μw for differential drive rectifier and 1.6 pw–1 μw output power change for a SVC rectifier respectively. As a result, higher PCE values for differential drive rectifier can be seen in Figure 11b. For the same change in input voltage level, the PCE changes by 42–38% for differential drive, 0.04–2.1% for SVC and 0.2–2.1% for simple rectifier topologies. Power consumption comparison of the above rectifier topologies designed by minimum-sized 3T DGMOSFETs is described in Figure 12. SVC and conventional rectifier topologies consume lower power (0.01–36 μw for SVC, 0.01–14 μw for conventional and 0.5–515 μw for differential rectifier topologies.
RF MOS transistors are usually designed as large devices in order to achieve the desired transconductance required to meet the RF requirements. They are usually laid out as multi finger devices, because in deep submicron CMOS processes, the maximum finger length (corresponding to the unit transistor width Wf) is limited. Typical devices have up to 10 or more fingers. Here the above minimum sized devices are upsized (10 times) and simulations are carried out to see the effect of PCE and DC output power generated by the various rectifier topologies, which can be seen in Figure 13. It can be seen that for a differential drive rectifier, although the overall DC output voltage generated by upsized devices increase significantly (from 0.12–1.72 V), but the PCE will still be lower compared to minimum sized devices due to the significant increase in the input power drawn from the signal. However, for SVC and simple rectifier topologies, both the DC output power and PCE increase significantly due to the less number of devices and small input power in comparison to that of upsized differential drive rectifier topology. For SVC, DC output power rise by 91 pw–5.6μw and PCE by 0.2–4.7% and for conventional rectifier, DC output power increase by 296 pw–4.1 μw and PCE change by 1.2–2.2%. This concludes that upsizing is not beneficial for differential drive rectifier both in terms of PCE and power consumption. For SVC and simple rectifier topologies, the PCE increases in power consumption (0.04–66.4 μw for SVC and 0.03–21.2 μw for conventional rectifier).
5.3. Effect of 3T/4T, Symmetric/Asymmetric DGMOSFET Features on Differential Drive Rectifier Topology
In the previous section, various rectifier topologies comparison for 3T DGMOSFETs is done. In this section we explore more on differential drive rectifier topology. Compariosn of DC output voltages generated by differential drive rectifier topoplogy implemented with minimum and upsized 3T/4T DG MOSFETs with variation in RF input levels is presented in Figure 14a. It can be seen that DC output voltages and thus DC power generated by 4T DGMOSFET circuits are smaller in comparison to that of 3T DGMOSFET circuits for both min. size and upsize topologies. This is primarily due to the larger ION/IOFF values of 3T DGMOSFETs than 4T DGMOSFETs. From Table 7, the DC output power generated by the 4T min-size configuration is 96% lower at high input levels and 25% lower at small input power levels than the 3T min-sized configuration. Similarly, the 4T upsized configuration DC output power level is lower by 114% both at lower and higher levels of input power as compared to 3T upsized configuration. Power conversion efficiency (PCE) comparisons of the differential drive rectifier topoplogy implemented with the minimum and upsized 3T/4T DGMOSFETS with variations in RF input levels are demonstrated in Figure 14b. Overall, 4T configuration has lower PCE than 3T configuration, but at very small RF input power levels, we can see the increase in the PCE of the 4T configuration than the 3T one.
Figure 15 shows the DC output voltage and PCE of the differential drive rectifier implemented with 3T/4T, symmetric/asymmetric features of DGMOSFETs. Overall, 3TDG feature has larger DC output levels and PCE than 4T configuration. SDG and ADG have almost similar DC output level generation and PCE values.
6. Conclusions
This paper investigated the scope of various configurations of DGMOSFETs with circuit co-design for ultra-low power RFID. It demonstrated that DGMOSFETs are more promising for future ultra-low power systems in comparison to bulk CMOS. Power, delay, and power-delay-product comparison of DGMOSFET-based logic circuits with bulk CMOS-based ones show that the DGMOSFET-based circuits improve energy efficiency more than 40% in the subthreshold operation. The DGMOSFET-based circuits also have 50% less variation than the bulk CMOS circuits. From the device/circuit performance metrices comparisons between four different DGMOSFET configurations (3TSDG, 3TADG, 4TSDG, and 4TADG), it is observed that the energy-delay-product of the 4T configurations is substantially higher when compared to 3T configuration. This proves that for better overall subthreshold circuit performance, it is preferable to use the 3T configurations over the 4T configurations. The 3TSDG configuration has around 78% better EDP value than the 4TSDG configuration. The PDP comparison of 3T-4T DGMOSFET-based logic families for subthreshold operation reveals that sub-CMOS, sub-Domino and sub-DCVSL logic styles have nearby values and lower energy consumption than the rest logic families. Sub-CPL and sub-DCVSPG designed with 4TDGMOSFETs are extremely poor in terms of PDP in the subthreshold operation. Overall, the 3TDGMOSFET configuration is better suited to RFID rectifiers and digital building blocks operating in the subthreshold region than the 4T configuration.
Figure 3. Comparison of PDP variation with respect to Temperature for 32 nm Bulk CMOS and DGMOSFET Inverters for subthreshold operation (Vdd = 200 mV).
Figure 4. Comparison of PDP variation with respect to Supply Voltage for 32 nm Bulk CMOS and DGMOSFET Inverters for subthreshold operation.
Figure 5. Summary of robustness comparisons of DGMOSFET and Bulk CMOS subthreshold performance metrics with regard to ±10% Vth fluctuations.
Figure 7. The ION/IOFF variation of DG n- MOSFET for different configurations with Tsi for subthreshold operation.
Figure 8. The subthreshold slope and EDP variation of DG n-MOSFET for different configurations with supply voltage for subthreshold operation.
Figure 9. The PDP comparisons of DG n- MOSFET with 3T, 4T, symmetric asymmetric options with temperature for subthreshold operation.
Figure 10. Conventional RFID rectifier implemenation with DGMOSFETs. (a) Simple rectifier with 3TDGMOSFET; (b) SVC rectifier with 3TDGMOSFET; (c) Differential drive rectifier with 4T DGMOSFET; (d) Differential drive rectifier with 3T DGMOSFET.
Figure 11. Comparison of various rectifier topoligies with minimum sized 3T DGMOSFETs as a function of RF input voltage. (a) DC output voltage; (b) PCE.
Figure 12. Comparison of power consumption of different rectifier topoligies with minimum sized 3T DGMOSFETs as a function of RF input voltage.
Figure 13. Comparison of different rectifier topoligies with up-sized 3T DGMOSFETs as a function of RF input voltage. (a) DC output voltage; (b) Power conversion efficiency (PCE).
Figure 14. Comparison of different rectifier topoligies with minimum and up-sized 3T/4T DGMOSFETs as a function of RF input voltage. (a) DC output voltage; (b) PCE.
Figure 15. Comparison of Differential drive rectifier with 3T/4T and symmetric/asymmetric DGMOSFETs as a function of RF input voltage. (a) DC output voltage; (b) PCE.
Table 1. Bulk CMOS and double-gate MOSFET (DGMOSFET) Device default parameter values used for simulations.
|32 nm Bulk CMOS
|32 nm DGNMOSFET
|32 nm DGPMOSFET
|3.3 × 1018
|2 × 1016
|2 × 1016
|Bulk CMOS
|D × 10−9 (s)
|D × 10−12 (s)
|CMOS Inv
|Pseudo NMOS Inv
|2 I/p NAND
|2 I/p NOR
|2 I/p AND
|2 I/p OR
|2 I/p XOR
|2 I/p XNOR
Table 3. Performance metric comparisons of n-DGMOSFET device with symmetric DGMOSFETs (SDG), asymmetric DGMOSFETs (ADG) and the three-terminal (3T) and four-terminal (4T) options under subthreshold operation.
|(Vfg = Vbg = Vdd, Tfox = Tbox = 1.4 nm)
|(Vfg = Vbg = Vdd, Tfox = 1.4 nm, Tbox = 2.8 nm)
|(Vfg = Vdd, Vbg = 0, Tfox = Tbox = 1.4 nm)
|(Vfg = Vdd, Vbg = 0, Tfox = 1.4 nm, Tbox = 2.8 nm)
|ION (μA/μm)
|IOFF (nA/μm)
|gm (μS/μm)
|Cg (af/μm)
|Power (μW/μm)
|Delay factor (ps)
|PDP factor(aJ/μm)
|EDP factor (aJ.ps/μm)
Table 4. Performance comparison of tied-gate symmetric DGMOSFETs (3TSDG) and (tied-gate asymmetric DGMOSFETs) 3TADG subthreshold logic circuits.
10−9 (w)
10−12 (s)
10−9 (w)
|CMOS Inv
|2 I/p NAND
|2 I/p AND
|2 I/p NOR
|2 I/p OR
|2 I/p XOR
|2 I/p XNOR
|Half adder
|Full adder
|2 × 1 Mux
|4 × 1 Mux
Table 5. Performance comparison of independent-gate symmetric DGMOSFETs (4TSDG) and independent-gate asymmetric DGMOSFETs (4TADG) subthreshold logic circuits.
10−9 (w)
10−9 (s)
10−9 (w)
10−9 (s)
|CMOS Inv
|2 I/p NAND
|2 I/p AND
|2 I/p NOR
|2 I/p OR
|2 I/p XOR
|2 I/p XNOR
|Half adder
|Full adder
|2 × 1 Mux
|4 × 1 Mux
|Logic Style
|Sub-static CMOS
|Sub-pseudo NMOS
Table 7. Summary of DC output level and DC output power of 3T/4T minimum and upsized Differential drive rectifier topology.
|RF Input (V)
|3T Min. Size
|3T Upsize
|4T Min. Size
|4T Upsize
|DC Output Level (V)
|DC Power (μw)
|DC Output Level (V)
|DC Power (μw)
|DC Output Level (V)
|DC Power (μw)
|DC Output Level (V)
|DC Power (μw)
|0.1 (small)
|0.9 (large)
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- Nakamoto, H.; Yamazaki, D.; Yamamoto, T.; Kurata, H.; Yamada, S.; Mukaida, K.; Ninomiya, T.; Ohkawa, T.; Masui, S.; Gotoh, K. A passive UHF RF identification CMOS tag IC using ferroelectric RAM in 0.35-μm technology. IEEE J. Solid-State Circuits 2007, 42, 101–110. [Google Scholar]
- Kotani, K.; Ito, T. High Efficiency CMOS Rectifier Circuit with Self-Vth-Cancellation and Power Regulation Functions for UHF RFIDs. Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC '07), 12–14 November 2007; pp. 119–122.
- Kotani, K.; Ito, T. Self-Vth-cancellation high-efficiency CMOS rectifier circuit for UHF RFIDs. IEICE Trans. Electron. 2009, E92-C, 153–160. [Google Scholar]
- Sasaki, A.; Kotani, K.; Ito, T. Differential-Drive CMOS Rectifier for UHF RFIDs with 66% PCE at 12 dBm Input. Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC '08), Fukuoka, Japan, 3–5 November 2008; pp. 105–108.
© 2011 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/).


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I'm a people pleaser. I've wanted to be accepted by the ones around me my whole life. Hell, I went so far as to pledge for a sorority to do so. It wasn't until recently that I realized that I'm worth more than trying to mold myself to be whatever other people wanted. I was the funny girl, the nice girl, the one who paid for other people's meals. Sure, these were things I enjoyed doing, but it was for all the wrong reasons.
When you're a people pleaser, people start to take advantage of you. They think they can treat you like shit because you'll do anything to keep them in your life. And it was true. I allowed people to walk all over me, give me excuses and I'd pretend everything was okay as long as I still had "friends."
I let people treat me like shit because I treated myself like shit.
I'm done with all of that now. I'm done vying for acceptance for people who will never truly accept me. I'm done being an option to people who I make a priority. And I'm done accepting half-assed, so-called apologies.
One thing I learned is that you have to say no. You have to make decisions for yourself and stick to them, not to be an asshole, but because it's the right thing to do for you. Along with this, just because people are sorry – it doesn't mean you have to accept it. You can say no too.
I am open to apologies and I am a very forgiving person, but only when the apology is real. Here are three parts to a true apology:
1. "I'm sorry"
People think that saying sorry is all there is to an apology, but that's not true. While manning up and saying the words is a good start, it's just scratching the surface.
2. "It's my fault."
The point of an apology is to take responsibility for what you've done. If you're not sorry, then don't say it in the first place. Even Justin Bieber says sorry because he knows he let you down. Bieber knows how to say sorry.
The worst kind of apology is ones that go along the lines of "I'm sorry you…" When did this apology become about me? I thought this was about you and what you've done. I recently had someone tell me "I'm sorry you feel that way." Don't be sorry about the way I feel. I'm not sorry about the way I feel, or else I would be apologizing, so why are you apologizing for my emotions?
3. "What can I do to make it right?"
Some people can come up with a solution and say "here's what I will to do make things right," but for me – the resolution of an apology is whether or not the person accepts it, and honestly, the other person really doesn't have to. You're the one that fucked up, so deal with the repercussions.
I think that a major portion of this is being sorry means that you're not going to do it again. How many times do you ask for forgiveness knowing that you're just going to repeat the same actions?
It's something I've learned too. I need to stop apologizing for things I'm not sorry for. If you're not sorry for what you've done, then don't lie about it. Don't give someone a fake "sorry" just so you can feel better about the situation or so that you can look better to other people.
Being a forgiving person is an honorable trait, and it should be valued. But if you're not sorry, don't apologize. If you aren't going to forgive, then don't accept an apology.

subset: commoncrawl


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Holiday Mini Sessions!
Let it snow!!!! My practice mini sessions were lots of fun!! And we got some great images!!! I am looking forward to meeting some great kiddos this coming weekend for my very first official mini session dates!!!
Sweet Session {Rhode Island Photographer}
I love photographing this lovely couple and their fur babies!!!! So glad we did this on Saturday night instead of in yesterday's rain!!!
Fall Portraits {Family Photographer in RI}
This young lady looked so beautiful for her Bat Mitzvah!! It was a great opportunity to get some family photos as well!! Such a nice and photogenic family!!
Senior Photos! {Rhode Island Photography}
It was a glorious September evening when we took these photos! The light was just perfect! The model was pretty perfect too!! 😉
Gone to the Dogs! {Family Portraits in Rhode Island}
This fabulous couple added a third fur baby to their family this year!!! What a cutie!! And they were all so well behaved!!!
It's Great to be ONE!!!! {Rhode Island Family Photography}
I haven't even gotten to his cake smash pics yet but I just had to post a sneak peek of this cute little guy!!!
Holiday Card Photos! {Rhode Island Photography}
Ho!Ho!Ho! These super siblings braved the cold, and some uncomfortable posing to get some really cute shots for Mom's holiday card!!!
And Some More Headshots! {Rhode Island Photographer}
It is always fun to photograph a friend – especially when they are gorgeous! When she's not modeling for me, she is busy with her Discovery Maps business, which currently features some of the best places to visit in Narragansett and Block Island!
'Tis the Season for…Professional Headshots!
I recently had the opportunity to photograph this team of ladies who work for Remax Town and Country.
The weather was a little chilly, but between the gorgeous location and the beautiful smiles on these gals, we got lots of great shots!!
High School Seniors – Oh Boy! {Senior Photography}
I love photographing high school seniors, and so enjoyed meeting this great kid and his mom!


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by Margaret Price for Investors Business Daily via NASDAQ
John Meredith is sure hot on dividend-payers. This year, the retired electronics engineer bought shares in seven dividend-paying companies:AT&T ( T ),Chevron ( CVX ),Cisco Systems ,Coca-Cola ,General Electric ,McDonald's andProcter & Gamble.
Subscribe to our free email newsletter to receive useful tips and valuable financial resources.
Investment Advisory Services Offered Through CUE Financial Group, Inc. a SEC Registered Investment Advisor. Securities Offered Through Foothill Securities Inc., Member FINRA & SIPC. Foothill Securities, CUE Financial and Turning Pointe Wealth Management are not affiliated.
Copyright © 2020 Turning Pointe Wealth Management. All rights reserved.
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Wild Currant & Thyme Candle
Product Details
Amazing high-fragrance candle in a vintage-style olive bucket. This new candle is blended with the highest quality oils for this WILD CURRANT & THYME TONIC fragrance. Smells like a botanical infusion with fragrant restorative properties. The design of the olive bucket allows the light to shine through for a warm and cozy effect.
Approximate burn time is 60 hours.
These candles are amazing!!!
Height 5.75"
Width across top 5.25"


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"After six years, we switched out some members and just lost momentum," says Adam Gimbel of Rookie Card, who'll play their first full RC set in four years at La Mesa's Riviera Supper Club on February 29 (the apropos "leap year" date that also occurs once every four years). "It was hard to motivate to get restarted, so we just never bothered. I got busy with other fun things [Cover Me Badd] that were much easier to get people interested in, so I let that happen for a while."
Over the first few years of the 21st Century, Rookie Card peddled their alt-country-crunchy sound all over town. After their What's on Second? full-length was nominated Best Pop Album at the 2006 San Diego Music Awards, the band went mostly silent, other than a 2008 Whistle Stop set and a 2011 appearance at the Casbah performing Wilco's A.M. album. "The Riviera show will mostly be Rookie Card songs," says Gimbel, "but we're throwing in a few fun covers for those who like to say, 'I love this song.' A couple of people remember our original tunes, but not that many."
One song guaranteed a slot is the closest they've come to a hit single, their obsequious ode to leap-year birthdays, "2/29." "I wasn't born on February 29, and I'd never met anyone who was when I wrote it. But, I thought it might be kinda sad to be born on leap year and wondered if it might make someone sad for their whole life...if you think it's rough being born near Christmas, try coming out on a day that doesn't exist three years out of four."
"I'm aging faster at a quarter of the speed/ my will to live don't have a lifetime guarantee/ I wanna leap off the deep end/ I hope I fall on a weekend."
"The song got mentioned in a syndicated leap-year news story that resulted in articles nationwide," says Gimbel. "In 2008, Dylan [Martinez of Rookie Card] and I filmed ourselves performing the song and uploaded it to YouTube." The clip was viewed around 10,000 times during its first week online.
"When Rookie Card first started doing the song, I'd ask if anyone in the audience was born on February 29. It took two and a half years before a leap-year baby actually showed up!"
More from SDReader
- More stories by Jay Allen Sanford
- Local DJs drive me insane — March 15, 2017
- Rookie vamp — June 5, 2013
- Gimbel's gambit — Feb. 20, 2013
- Ten Years of Blasphemy — Dec. 15, 2010
- Joker Holds Court in Studio — Dec. 29, 2005


text: Features June 2017 Issue As was common at Denver's Stapleton Airport, airliners were struggling with the winds. Dr. Theodore Fujita analyzed the radar data to produce this graph. Windshear Weather In any of its various forms, strong windshear can present an aviation hazard requiring us to make alternate plans. Here's a close look at this sometimes-invisible threat. By Tim Vasquez Last month, "Handling Windshear," described how to recognize, avoid and, handle an encounter with windshear. The focus of that article was the practical side of piloting but we necessarily touched on the basics of the weather behind thunderstorms, microbursts and windshear. Now it's time to dig deeper into that meteorology. To continue reading this article you must be a paid subscriber. Subscribe to IFR Magazine Get the next year of IFR Magazine for just $19.97. Get access to all articles published online. Features, reviews, lesson, quizzes - get it all. That's a savings of more than $14 off the regular rate. Or double your savings and subscribe for 14 issues for just $39.94. Subscribe Get IFR Digital Get 12 months of IFR DIGITAL for just $34. You get unlimited access to everything on the site including each monthly issue as a PDF. Subscribe Subscriber Log In E-Mail Address: Password: Login Forgot your password? Click Here. Already subscribe but haven't registered for all the benefits of the website? Click here.


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The Interior West Forest Inventory and Analysis (FIA) Program collects increment cores as part of regular monitoring. Ring-widths from these increment cores are being digitized and assembled into data products for biogeographical or climatological analyses.
In the Interior West states, FIA collects increment cores on most forested plots. These include cores from the periodic inventories (late 1980s to early 2000s) and from the current annual inventory system in some states. A long-term project was initiated with the goal of digitizing ring-widths from the increment cores, which can be assembled into gridded data products and used for any number of potential analyses.
The project status is active and ongoing, as there are tens-of-thousands of increment cores to process.


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25 Jul
Modern 4-star hotel near Naples central railway station
Base yourself in the historical centre of Naples by staying at this modern 4-star hotel, conveniently set just a few hundred metres from the citys main railway station, Napoli Centrale. Renovated in Art Deco style, the hotel is within easy reach of popular sights including Piazza Garibaldi, as well as many shops, bars and dining options. Relax in the on-site Mediterranean restaurant or make use of the hotels extensive business facilities and convention centre.
Read more »
Read more »


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The New Venture Development is currently working with a number of UMass Lowell startups.
Incubated In-House
AquaTerrene - AquaTerrene is development a portable probe that can perform quick, on-site water analysis, determining concentrations of heavy metals, sediments and soil in samples. The company is currently testing its device out in the field.
Raywatch - Raywatch is currently development a flexible thin film radiation detector for applications in the medical radiation diagnostics and therapeutics space as well as for homeland security, and defense.
Visium Medical - Visium Medical is developing a disposable, low cost, Catheter-based Ultrasound (CBU) platform with first focus on a novel catheter that generates Ultrasound images and monitors temperature from the distal tip. These probes are easy to integrated and to maintain smaller size diameters than other US catheters. Visium Medical will prioritize the cardiology segment, specifically the Afib Ablation segment providing more minimally invasive devices and integration of diagnostic capability with surgical devices for cardiology.
Invitrometrix - Invitrometrix is working on game-changing technology for the pharmaceutical industry. They are developing cell-based sensors that can monitor real-time biological changes, in response to different drugs. The device allows for research on various types of cells, like normal, healthy cells or cancer cells, to pinpoint potential side effects of drugs early on.
Weave Visual Analytics - Weave is building an online platform for data visualization. Users, regardless of their data experience, can render visualizations for any available data. It can also handle multilevel modeling, for more in-depth analytics.
Licensed Start-Ups
For information on any of these companies please contact Nancy Saucier.


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"I love to hear the shofar blast. / Sometimes slow, sometimes fast. / I love to hear the shofar blast. / Happy, happy, happy New Year!" At Albert Einstein Academy, we are happy indeed. In what is now our second week of school, routines are setting in. Rather than indicating rote procedures and predictability, our routines open us up to being amazed. Hearing the shofar is just one example.
We began the Hebrew month of Elul over the weekend. Elul marks the thirty-day period leading up to Rosh HaShanah, the Jewish New Year. To help in preparing for the High Holy Day season, we blow the shofar every morning. On the one hand, the shofar blasts become routine; on the other hand, the shofar blasts are an alarm. Already, our students know the names of the different notes (teki'ah = one solid blast; shevarim = one blast broken into three waves; t'ru'ah = nine staccato blasts; and teki'ah gedolah = one long blast). What they also know, though, is that the blasts are meant to wake us up physically and spiritually. Their eyes opened wide with amazement as we discussed how one can hear, feel, and also focus on the shofar blasts.
Wonder, amazement, and sometimes even awe are integral to learning at Albert Einstein Academy. Just as the shofar can inspire us, so too can a science experiment, a walk around the building, and even a handhold. Our everyday learning is designed to make space for surprises and the deeper learning that goes with them.
This week gave our students a chance to find a rhythm to their day. They now know the flow from one block of classes to another. They have experienced most of our specials. They started getting homework. They are engaging with the topics of their first units. And, they have also made mistakes. The amazing thing about forgetting something at home or forgetting an assignment at Einstein is that the forgetting itself is a lesson. Rather than focus on punitive measures, teachers inquire of our students how the student can learn from the error.
Our Gan friends spent this week adjusting to being dropped off out front. Day by day, our students learned to trust that our school is a great place to be and that their grown-ups will be there at the end of the day. I was so pleased to see the happy smiles of our Gan students helping each other enter the building together. Today, every single one of them made it to the door smiling and talking. Amazing progress that only comes from repeating the daily routine.
Speaking of routine, our 4th and 5th graders found their own surprises in class this week. To better learn the vocabulary and to understand accessibility, the 4th grade Hebrew class walked around the building and found all sort of handicap access. Our 5th grade, in their science class, was shocked to learn that rice and gummies have starch. Routine parts of our curricula were brought alive by teachers and students in a way that makes the learning stick. It may sound routine to have gone to class to learn. At Einstein, routine is amazing. We can't wait for more.


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Properly made sofas, for life.
Long-lasting fabrics, leather all over.
Our stylish sofa sets - from fabric settees to armchairs, and accent chairs to loveseats - are all made from high-quality upholstery fabrics that exceed UK standards. Our leather range is crafted with 100% real leather; we never use inferior materials or fake alternatives. There's a reason why we have such great customer feedback on our sofas; they're built with the utmost care. We only sell sofas we'd be happy to have in our own homes. Plus, we've worked hard to solve the most common sofa problems, helping ours to last for years.
Quality is in our DNA – that's how we craft our exclusive sofas with the greatest attention to detail. From solid hardwood incorporated into the frames, with durable screwed, glued and pinned joints, to high-quality serpentine springs with silencing connections, we make sure our sofas not only look stylish but stand the test of time, too.
Design tips
When planning for a new sofa set, don't forget to measure your room, doorways, stairs, or even your building's lift, compared to the size of your new purchase. If you're buying a sofa bed, remember to check the measurement of the pull-out bed too.
Is your living room on the smaller side? Try mixing up your look with several small sofas, or incorporate armchairs, loveseats, and accent chairs into your arrangement to create more places to relax.
We also offer a wide range of sofa beds, recliners, and corner sofas. Browse our stylish collections today, or check out our sofa guide for tips on how to choose the perfect settee. We've broken down everything you need to know about sofa size, materials, quality, construction and care.
More sofa ideas
Our blog is full of sofa inspiration. Whether you're looking for ideas on how to makeover your living room or need handy tips on how to: mix and match sofas and chairs, we've got it covered. Find out how to decorate with patterned sofas, style your Jasmine sofa and much more.
Sofa on Finance
Spread the cost of your new sofa with our flexible finance options, designed to make buying our beautiful sofas even more affordable. For purchases over £500, pay monthly over up to four years. And for orders over £3,500, enjoy interest-free credit up to three years. Fast, seven working day delivery means there's minimal waiting time, so you can create your dream living room starting with your new sofa right away.
Do you want to know more?
How do I prevent my sofa from wearing and keep it clean?
We can help to keep your sofa looking its best, year after year. We offer a special 5 year Furniture Guard protection plan, so that if anything does happen you can rest easy, knowing your sofa is taken care of. Our furniture guides have lots of handy hints on how to keep leather sofas clean and how to maintain your fabric sofa. We also have special care kits for fabric and leather sofas to help keep you new pieces looking great.
How are your sofas made?
We make all of our sofas with the highest attention to detail. We incorporate solid hardwood into the frames, paying special attention to key stress points. We also use screwed, glued, and pinned joints which prevent warping or creaking in your new sofas. Additionally, we pay careful attention to the little details. We've even created our own bespoke plump-free seat cushion filling for easy maintenance and great looks. Learn more about how we make our sofas here.
- How to choose the right sofa for my home?
Choosing a new settee for your home doesn't need to be stressful! First, think about the size of your room. Knowing the right measurements will help you find the best sofa fit for you, so be sure to look at not just your living room, but also door widths, stairs, or corners.
Once you know what size will work for your home, then think about key design features, such as upholstery fabric, arm design, feet and extra details. Are you designing a multi-purpose space and need a sofa bed? Are you looking for a new sofa to integrate with your existing sofa suite? We have a wide range of leather and fabric sofa styles to choose from, so you're sure to find a look you'll love!
- Which sofas are best for my family?
When choosing the right sofa for your lifestyle, there are a few tricks to keep in mind so you can find the best sofa for your family. First, think about sizing. We offer everything from compact accent chairs to expansive corner sofas, so you can be sure that everyone gets the best seat in the house. Then, consider the upholstery. Darker-coloured fabrics, for example, are great when you have kids, as they can easily disguise everyday mess. If you have pets, velvet can actually be a great upholstery option - the open pile means that kitty's claws won't get stuck in it! And when it comes to long lasting sofas, look to leather. It ages to a beautiful patina, and is easy to keep clean with a durable wipeable surface. Learn more here.
- Which sofas are the best quality?
We only use the best materials in all of our sofa styles. Take our upholstery for example. We use the best fabrics available, and make sure they meet our standards by subjecting them to strict industry testing. And we only ever use 100% real leather. We don't skimp or use lesser materials on the arms of the backs because you can't see them. When you buy a leather couch from us, you can be assured it is always real leather, all over. We even use solid hardwood feet to finish the pieces and match our furniture collections. See more examples of our quality in action here.
- How to choose the right sofa for my home?
Guide to your perfect sofa
Check out our guides below to find out everything you need to know on sofa care, living room design, and more. With great information on both our leather and fabric styles, you'll find out everything you need on our high quality sofas today.
- Served, with love, by Marvin
- Node: ip-10-0-70-177
- Exec Time: 0.1166 secs
- Memory Usage: 8.07 MB


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SharePoint Hide columns on list or library
There are two different ways to hide columns or fields on a list or a library. Conditionally where you only hide the field some of the time (maybe you want to hide the 'Completed Date' column when creating new items), or hiding fields all the time. This tutorial is for hiding a column from all the list or library forms (New, Edit and View).
**The column can still be added to list or library views though if desired.
Reasons you might want to always hide a column
- Make the field hard to edit or change
- You want a workflow to populate or change the field value
- You no longer need a column for new submissions but don't want to delete it and lose all the entered data for the existing submissions
Hiding a column from all list/library forms
1. Go to your list or library, click on the List/Library tab, select List Settings.
2. On the Settings page, click on the Advanced Settings option.
3. On the Advanced Settings page, select Yes for Allow Management of Content Types. Click the OK button to save the setting and return to the Settings page.
4. On the Settings page, you should now see at least 1 content type in the Content Type section. Click on the Content type.
5. On the List Content Type page, click on the Column you want to hide.
6. There will now be 3 column setting options, choose the Hidden option. Click the OK or Save buttons until you return to the main Settings page.
Completed Example: The hidden column can still be shown on views:
But it will not be shown when creating a new item, editing a item, or viewing an item:


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HighlightsSalt Lake City | Jackson | Targhee National Forest | Jackson Hole, Wyoming | Grand Teton National Park | Yellowstone National Park | Glacier National Park | Coeur d'Alene, Idaho | Seattle
Travel Team
If you'd like to chat about this vacation or need help finding one we're very happy to help. The Travel Team.Toll free 1-866-821-6866 Calling from outside the US? firstname.lastname@example.com
Small group adventure vacationYou will be sharing your experiences with a maximum of 13 like minded travelers and you'll have a group leader with you. Whether you are traveling alone or with friends its good value, and a great way to meet new people! While itineraries are pre-planned there is some flexibility and you'll have plenty of privacy. This trip will appeal to travelers of all ages who enjoy meeting new people as well as seeing new places.
Responsible tourism
Yellowstone and Grand Teton wildlife vacation
Carbon reduction
Your vacation will help support local people and conservation. We must also reduce CO2. Learn about the CO2 emissions of this vacation and how to reduce them.
We are committed to offering low impact tours that benefit both the places and communities we visit as well as our travelers. It is important for us all to be aware of the delicate balance that exists in the variety of natural wonders you will visit. National Parks and monuments, archaeological sites and other sensitive areas should and must be treated with respect.
We have created a 'Travelers' Code of Conduct' to help prepare and inform our groups of the various positive or negative effects they could have on a destination. The code includes tips on everything from handling wildlife encounters to how you can help to conserve precious natural resources. Our tour leaders will explain this code of conduct during the first nights orientation talk and encourage you to follow it throughout the tour.
This code includes following the Leave No Trace ethic, this is an international campaign that is designed to help us minimise the impact on the National Parks and other wilderness areas that we visit. Some key guidelines we follow include keeping to existing trails, staying in official campgrounds and disposing of all waste responsibly and recycling whatever we can.
We are proud supporters of Bay Area Wilderness Training (www.bawt.org) a charity based in Oakland California which works to connect disadvantaged children in the local urban area with the great outdoors. Their work helps to provide these young people with life changing experiences which they can
apply to everyday life. Everyone booking with Grand American Adventures has the option to donate £1/$1/1 to support this well-deserved charity and we will match this donation.
Whenever possible, we use local accommodation and activity providers. We also shop locally for groceries, eat in small family-run restaurants and visit local shops whenever possible. This all brings economic benefit to the local communities that we visit.
In Yellowstone, this tour provides employment to local specialist guides such as a wolf tracking guide, geologist guide, and wildlife guide. As well as giving travelers a greater understanding of wildlife in its natural habitat, we view from a safe distance and with minimal impact so as not to upset the balance of nature.
By offering a trip which covers a smaller and more focussed area, we are able to spend more time highlighting the key highlights, whilst avoiding covering large amounts of road miles to visit them.
In Glacier National Park, we hire a specialist ranger guide who is employed by the national park, ensuring that this role and service continues to be offered in the future.
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Highlights

 The hacker group Legion says its members now have their eyes set on sansad.nic.in — which provides email services to government employees

 It's the same group that was behind the four high-profile Twitter account breaches and two data dumps in the past fortnight

 ,
"Next is a dump of sansad-.nic.in emails. Which is — quite big. It includes a lot of _BIG FISH_," a Legion member told Factordaily.com, a tech news website, over an encrypted chat interview.
In another interview, with Washington Post, a Legion member claimed to have access to entire servers, like that of hospital chain Apollo, where J Jayalalithaa was hospitalised before her death.
He said Legion was unsure about releasing data from those servers because it might cause "chaos" in India. The hacker group also claimed that India's digital banking systems are vulnerable to cyber attacks.
"We… ourselves have confidential data pertaining to NPCI /IDRBT (hub servers, and even have the encryption keys/ certificates used by some banks in India," Legion said. However, the group seemed to suggest that it was not particularly keen on exploiting this weakness.
In their interviews with Washington Post and Factor-Daily.com, they also bemoaned the lack of basic data security practices. The hacker who spoke with the Post described the group as a "bunch of computer g33kz addicted to crime and drugz".
Hacker group Legion numbers in the "higher single digits", according to a member of the group. Their objective is to put "as much classified information out in the public domain as possible", he told Washington Post in an interview. In another interview to Factordaily-.com, a Legion member responded to a question about possibly targeting BJP, saying: "We will own them too, when the time is right."
Over the last few days, Legion compromised the accounts of liquor baron Vijay Mallya, Congress vice president Rahul Gandhi, and senior NDTV journalists Ravish Kumar and Barkha Dutt. They published 277 files purported to be documents pertaining to Vijay Mallya's personal and financial dealings. These included credit card bills and scanned copies of his passports. In the case of Dutt, they released a "partial" dump of her emails, 1.2 GB in size. When they breached Gandhi's Twitter account, they threatened to release data on Congress as well.
As for the leaks, the hacker told the Post that the group "ended up with access to over 40k+ servers in India, and we decided — hey, why not write a tool to sift through them for interesting data?" The hacker, who listed progressive house music as a "passion", said artists like Brian Eno, Aphex Twin and Global Communication were "influences". Asked to respond to those who insinuate the group has political motives, the hacker told the Post, "We kindly request them to gas themselves with a balloon filled with zyklon B." Zyklon B is a cyanide-based pesticide. Through their tweets on the compromised Twitter accounts, Legion has also threatened to leak data of former IPL chairperson Lalit Modi.


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Fujifilm is helping make the world a better, healthier, and more interesting place. Learn more about what we're about.
The GF50mmF3.5 R LM WR is the smallest and the lightest (335g) GF lens with a maximum aperture of 3.5 and focal length of 50mm (equivalent to 40mm in the 35mm film format). When attached to the GFX 50R, the combination weighs just 1,110g, making it the lightest GFX kit yet, and the perfect choice for street and travel photography.


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The third book in the series, Without A Summer, was released just a few days ago and it's just as delightful as the previous adventures. Jane and her stoic, Byronic husband Vincent are finally settling down after the Napoleonic Wars. The misery and drama of the last book, Glamour in Glass, are far behind them. This has given Jane time to focus on family. One family member in particular. An invitation to create a special mural in London prompts Jane to take her younger sister Melody with them.
I rather hated Melody in the first two books. She reminds me completely of my own younger sister, and the relationship she had with Jane hit extremely close to home since it so resembled my sister and I. I could fully empathize with Jane over the way Melody treated her, as well as how others treated her as a result. Melody is a great beauty, charming and winsome. In comparison, Jane feels plain and awkward. I can so relate to this. Oh Jane, it's like you're me, if I lived in 1812. Even after finding the love of her life, a man who matched her in both stubbornness and magical skill, Jane still feels painfully plain around her sister. Jane, as we say in 2013, I know that feel.
Without A Summer takes place during the coldest summer England has seen in many, many years. A special group of glamourists (the term for people who can use certain magic in the books) called coldmongers are blamed, even though there is precious little evidence against them. A riot is brewing and Jane and Vincent seem powerless to stop it. While the plight of the coldmongers gets worse, Melody is growing fond of an unsuitable gentleman. Jane has her hands full trying to keep tabs on her sister as well as help the coldmongers. While Jane is preoccupied with Melody, Vincent has family problems of his own. His completely evil father has come back out of the woodwork and is set on tearing Vincent's new life completely to pieces. God, did I hate him. He was a fantastic villain. He was politely vile and conniving.
Jane and Vincent start to lose control and things come to a head when the coldmongers march on Parliament. I wish I could give you more details, dear reader, but I don't want to spoil a single thing! The book was just too amazing and you have to read it.
|Mrs. Kowal, from her website
If you haven't yet discovered these lovely books, I implore you to add them to your reading lists. They are absolutely stunning books, with wonderfully rendered characters. I find myself smiling as I read them, marveling over the world, the magic and the language. Kowal even got me to read and enjoy Jane Austen and fall head over heels for the Regency period! That is no small feat, considering I wrote a paper in college entitled "Why I Hate Jane Austen". (We're all good now, Miss Austen. No hard feelings?)
Happily, it seems there is a fourth book planned and I will have to find a way to be patient. I'm not good at being patient. I shall take a page out of Jane's book and try to behave as a Regency lady and not claw at my screen in agony as I wait for the next volume. See? She's a good influence on me!
Without A Summer is available now. Mary Robinette Kowal's first two books in the series, Shades of Milk and Honey and Glamour in Glass are also available and they are the highest quality of awesome.


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Original copper plate engraving, early 1800's.
Sales price: $1,000.00
Description Guanabanus an original hand colored copper plate engraving botanical print, circa early 1800's. The Title calligraphy is executed in copper leaf with excellent details and coloring. Print laid on board, presented in a 1920's mount with a natural elm burl frame. Image H-16" X W-12" Frame H-30" X W-23.5"


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Hey Everyone!
Welcome to Monday and to another in the ongoing, K'lee and Dale's Cosmic Photo Challenge!
This past Friday, my buddy Dale took on the responsibilities for providing us with a new prompt:
Got to admit…
I wasn't so sure where I wanted to go with this prompt, and more importantly, I didn't have a clue where to turn for a photo or three meant to represent said prompt.
All the doubt over what to do and use disappeared today with a trip down to a spot we here in San Francisco call, The Presidio.
What's cool about this spot is a portion of it is a man-made bird sanctuary, that this time of year provides home and food to one of my favorite flying creatures- Turns.
After a couple hours of photographing these amazing birds, I knew I'd taken at least one shot I could use for this prompt, and here, done in my 'painted graphic style', is a work depicting one Turn offering , The Food of Love to another Turn:
… and I thought a few days ago this post was going to be about… CHOCOLATE!
Ironically, what I saw repeatedly was Seagulls waiting for the moment the Turns went to pass their food… to attempt to snatch it….
Nine times out of ten the Gulls lost out…
So that's my take on Dale's prompt.
How about your take?
I'm looking forward to seeing more of those before the day's done.
Here's to a great week ahead of us all…
K'lee L. © 2018


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- on Miscellaneous Electronics
- Published in issue 7/2006 on page 0
Audible Flasher Warning
If you're a biker or scooter rider you'll know how easy it is to forget to cancel your flashing indicators after turning without an audible reminder. Constantly glancing at indicator lamps is hardly an option; your eyes should be on the road ahead!
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