text:
|Data cache using dynamic frequency based replacement and boundary criteria
|Multi-cache data storage system
|Crane et al.
|Cache tag lookaside
|Bryg et al.
|Virtual memory cache for use in multi-processing systems
|Dashiell et al.
|Computer system employing virtual memory
|Smith et al.
|Eviction control apparatus
|Woffinden et al.
|Virtual memory address translation mechanism with combined hash address table and inverted page table
|Hester et al.
|Method and apparatus for implementing an algorithm associated with stored information
|Goodrich, Jr. et al.
|Peripheral storage system having multiple data transfer rates
|Error processing system using two different types of replace logic
|Takahashi et al.
|I/O Storage controller cache system with prefetch determined by requested record's position within data block
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|Automatic adjustment of the quantity of prefetch data in a disk cache operation
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|Address conversion system
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|Data processing system having an intermediate buffer memory
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|Circuit for implementing a modified LRU replacement algorithm for a cache
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|November, 1987
determining the address of a desired information component;
forcing the presence indicator of a memory location into a second logic state when said extract is loaded into said memory location;
accessing said information component by associatively searching within said high-speed associative memory for an extract with an address that matches the address of said information component;
replacing an old extract selected by a selection algorithm with a new extract if said extract is not found in a memory location within the high-speed associative memory; and
upon use of an extract, maintaining said reference indicator associated with said memory location that contains said extract in said first logic state if a number of extracts stored in said associative memory is less than a given threshold value, the threshold value being less than a maximum capacity value of said associative memory or forcing said reference indicator into a second logic state if the number of extracts stored in said associative memory is at least equal to said threshold value.
a rank is assigned to each memory location in said associative memory;
extracts are initially loaded into memory locations of increasing rank in chronological order; and
a state of the presence indicator whose rank is equal to said threshold value provides an indication that said threshold value has been reached.
if the information component sought is not found in the associative memory, said information component is sought in the main memory;
the extract associated with said information component is loaded into the high-speed associative memory at a location whose rank is determined by said selection algorithm;
the associated presence indicator is forced into said second logic state substantially contemporaneously with said loading; and
a new associative search for the sought information is then performed.
searching, in order of increasing rank, for the first extract whose presence indicator is in said first logic state, or failing that, for the first extract whose reference indicator is in said first logic state.
a main memory;
processing means for accessing said main memory by addressing, wherein an "extract" includes an address and an associated information component, and wherein said processing means includes:
a high-speed associative memory comprising:
a plurality of memory locations for storing a plurality of respective extracts, wherein each memory location is associated with a presence flip-flop and a reference flip-flop, said flip-flops being initially set to a first logic state, said presence flip-flop subsequently being set to a second logic state when an extract is loaded into said memory location;
comparison means, cooperative with said high-speed memory, for providing each memory location with a coincidence signal having a first logic value when the address of an item of sought information matches the address of the extract present in said memory location;
said computer system further comprising:
threshold detection means for furnishing a threshold signal whose logic value indicates whether the number of extracts present in said high-speed associative memory is at least equal to a given threshold value; and
for each extract that is present, a management circuit wherein the associated reference flip-flop is forced into a second logic state when said coincidence signal indicates a match while said threshold signal indicates that the threshold has been reached.
to select a memory location in which an extract not yet present in said high-speed associative memory will be loaded, each presence flip-flop and each reference flip-flop is associated with a propagation circuit that provides a request signal;
a rank is assigned to each memory location so that propagation circuits associated with each presence flip-flop and each reference flip-flop respectively are arranged in cascades;
an output of the propagation circuit associated with a last presence flip-flop is connected to an input of a propagation circuit associated with a first reference flip-flop;
each propagation circuit delivers a signal that indicates that a request exists only if an upstream request signal indicates that a request exists and the associated flip-flop is in said second given logic state;
the propagation circuit associated with a first presence flip-flop continually receives a signal representing the existence of a request; and
each location is associated with a selection circuit for delivering a signal representative of selection of said location when the upstream request signal associated with one of the flip-flops of said location indicates that a request exists while said flip-flop is in a first given state.
a paginated virtual memory mechanism wherein:
said address of each extract is a virtual address;
said associated information component is a real address; and
each memory location of said high-speed associative memory includes a virtual address register and a real address register.
The invention relates to computers and more particularly to facilitating access to information contained in a memory system of a computer.
The central subsystem of a computer generally comprises three types of units: processors, memory modules forming the main memory, and input-output controllers. Usually the processors communicate with the memory modules through a bus that allows addressing and transfer of data between the processors and the main memory. To execute a program instruction, its operands must be located in the main memory. The same is true for successive instructions of the program to be executed. In the case of a multiprocessing system, the memory must be partitioned to allow multiplexing between programs. For this purpose, virtual addressing is generally used in conjunction with a pagination mechanism which includes dividing the addressable space, or "virtual space," into zones of a fixed size called "pages." In a system of this kind, a program being executed addresses a virtual space that corresponds to a real portion of the main memory. Thus, a logical or virtual address is associated with a physical or real address of the main memory.
An instruction that requires addressing contains information that enables the processor executing it to obtain a real address. In general, this virtual address is segmented, i.e., it is composed of a segment number, a page number, and a shift i.e., displacement within the referenced page. The segment number in turn can be subdivided into a segment table number and a shift within this table.
In order to access an item of information in memory associated with this segmented address, several memory accesses are necessary. It is first necessary to access an address space table allocated to the process (program being executed). From this table, using a segment table number, the real address of the corresponding segment table is then obtained. Next, as a function of the shift in the segment table, a segment descriptor is accessed which makes it possible to calculate the real address of a page table. Eventually a real page address is found, using a function of the page number defining the shift within this page table, thereby making it possible to address the memory. The real address of a word or particular byte [8-bit byte] is obtained by concatenation of the real page address with the shift within this page defined by the least significant bits of the virtual address.
A memory access is relatively time consuming, due primarily to the use of a bus that is common to both the processors and the memory module. To improve system performance, the successive memory accesses typically required to obtain a real address are avoided as much as possible. Most processes have a locality property according to which, during a given phase of its execution, the number of pages used by a process is very small relative to the total number of pages allocated to that process.
The locality property can be used to facilitate the translation of a virtual address into a real address by the use of "extracts". Each extract includes a virtual address and an associated real address, and is used by the program during a single execution phase. A plurality of extracts are stored in high-speed memory or in registers. To perform a translation of a virtual address into a real address, a high-speed associative memory is accessed to determine whether the virtual address to be translated is already present in the high-speed memory. If it is, the real address is obtained directly without accessing the main memory.
The locality property motivates the use of cache memories composed of small, high-speed memories in which the pages most recently referenced are stored. The probability that a new reference will relate to an item of information already present in cache memory is high, so the effective access time is reduced. In a manner analogous to the translation of the virtual address into a real address, a cache memory comprises a table containing the real addresses of the pages present in the cache memory. This table, called a directory, can be consulted in an associative fashion to determine whether the information associated with a given real address is contained in the cache memory. If it is, a word or byte is obtained by addressing the cache memory by means of the least significant bits of the virtual address of the word or octet.
Issues related to the translation of addresses will now be discussed, it being understood that the same considerations may apply to cache memories. In both cases, the issue is that of rapidly obtaining information associated with a page address. In the case of translation of an address, the page address is a virtual address and the associated information is the corresponding real address, while in the case of cache memory, the page address is a real address and the associated information includes all the data contained in the page.
As previously discussed, the high-speed translation memory is an associative memory. The memory comprises a given number of registers, or more generally, locations, each capable of storing one extract. Each extract can be accompanied by additional information such as right-of-access indicators or indicators reporting that a write access has been effected in the page associated with the extract. Moreover, each extract is associated with a presence indicator which, for a given logic state, indicates that the associated extract is valid. These presence indicators are, for example, set to zero at initialization, i.e., each time a process is activated in a particular processor. Thus, as the process uses new pages, the associated extracts are loaded into associative memory and the respective presence indicators are simultaneously set to 1. When a memory access must be executed, the virtual address is compared with the virtual address of each extract stored in associative memory. If there is a match between the virtual address being sought and one of the virtual addresses of an extract stored in the memory while its associated presence indicator is set to 1, the corresponding real address can be obtained directly by simply reading the register that contains the real address.
In order for this translation mechanism to be practical, the associative memory must be of limited size. Consequently, for processes with many pages, the associative memory cannot store all the extracts corresponding to these pages. When associative memory is full, the only way to store a new extract therein is to erase an old extract. It is therefore necessary to provide a method for eradicating an old extract and storing a new extract in its place. To accomplish this, a replacement algorithm is used that decides which old extract is to be replaced by a new extract. Many algorithms have already been proposed, for example:
the FIFO ("first in, first out") algorithm, in which the oldest extract is replaced;
the RAND ("random choice") algorithm, in which the extract to be replaced is chosen at random;
the LFU ("least frequently used") algorithm, in which the least frequently used extract is replaced; and
the LRU ("least recently used") algorithm, in which the least recently used extract is replaced. The LRU algorithm theoretically gives good results, but in practice it is preferable to use a simplified version, called the "pseudo-LRU." To generate n extracts, a true LRU requires the presence and management of log2 (n) bits per extract to maintain an ordered history of the uses of the extracts. On the other hand, a pseudo-LRU requires only a single bit per extract, called a reference bit or indicator.
According to the pseudo-LRU algorithm, the reference bit is set to a first logic state (1 for example) when its associated extract is used. When the associative memory is full, all the presence indicators are set to 1, and a new extract must be loaded. The extract to be replaced is the first extract encountered with a reference bit set to 0 according to the chronological order of filling. When saturation is reached, i.e., when all but one of the reference bits are set at 1, the extract whose reference bit is at 0 is replaced by the new extract, and all the reference bits are then reset to 0. Resetting all the reference bits obliterates the history of the use of the extracts.
The loss of the history upon saturation results in a decrease in the efficiency of the algorithm. Moreover, a freshly loaded extract may very likely be reused immediately after being loaded, again resulting in saturation upon the loading of the fresh extract.
To assess the consequences of this loss of history, it is useful to perform simulations of populations consisting of specific processes relating to applications normally handled by the system. It is found, for example, that for a certain population of processes, in 65% of the cases, only 32 extracts are required. This means that 65% of the processes do not require use of the replacement algorithm. On the contrary; the algorithm will be used at least once by 35% of the processes. This means that a loss of history will occur at least once in 35% of the cases.
During a simulation, it has also been found in 90% of the cases, that at a given moment, a program will access one of the last seven extracts called. This result confirms the phenomenon of locality mentioned above. Thus, after the reference bits are reset to 0 after saturation, the only criterion for selecting the extract to be replaced is the position of the extract in the associative memory. However, the location of an extract provides no indication of the time of its last use; it only provides an indication of its first use. Thus, it is quite possible that pages used at the start of the process will be used again a short time before saturation. In this case, after resetting the reference bits to 0, these pages will be eliminated first, even though they have a high probability of being reused very soon thereafter.
One aspect of the invention is a method for rapid access to information stored in the main memory of a computer system, a component of information being located by an address, that component of information and its associated address together being called an "extract". The system includes a high-speed associative memory that includes a plurality of memory locations, each location being capable of storing one extract. Each extract is associated with a presence indicator and a reference indicator initialized to a first logic state, the presence indicator assuming a second logic state when the corresponding extract is present in the high-speed memory. Access to an item of information is accomplished by associatively searching for the extract present in the high-speed memory whose address matches the address of the information sought. The reference indicators undergo a change of state upon use of their respective extracts, the state change being detected and processed by an algorithm for replacing old extracts with new extracts that are being sought and are not yet present in the high-speed memory. The reference indicators are maintained at their initial logic state while the number of extracts present in the high-speed memory is less than a given threshold value. A reference indicator is forced to a second logic state when the associated extract is used, but only if the number of extracts present is at least equal to said threshold value.
Provision is made for the reference indicators to be maintained at their initial states (for example at 0) during the early stages of execution of a process, and for as long as the number of extracts present remains less than a given threshold value. Once the threshold value has been reached, updating the reference indicators takes place normally. Thus, when the associative memory is full, only the extracts used during an execution phase corresponding to the end of filling can have their reference indicators set to a logic state (1 for example) that indicates their use. As a result, on average, a larger number of processes will escape the loss of history due to saturation.
The threshold value is chosen so that the difference between the number of extracts and the number n of locations in the high-speed memory results in a history of sufficient scope to optimize the performance of an intended application.
According to one preferred embodiment of the process of the invention, a rank is assigned to each location in the high-speed memory. Extracts are initially loaded in chronological order into locations of increasing rank. The state of the presence indicator whose rank is equal to the threshold value provides an indication that the threshold value has been reached.
In another aspect of the process of the invention, when an information item being sought cannot be found in the high-speed memory, the information is then sought in the main memory and the corresponding extract is loaded into the high-speed memory at a location whose rank is determined by the loading algorithm. The associated presence indicator is forced to a second logic state in conjunction with the loading. A new associative search for the desired information is then performed.
According to yet another aspect of the process of the invention, the loading algorithm includes the steps of searching, in increasing order, the rank of the first extract whose presence indicator is at a first logic state or, failing that, of the first extract whose reference indicator is at the first logic state.
A further aspect of the invention is an apparatus for implementing the process of the invention. The apparatus includes processing means for accessing "extracts" that each include an address and an associated information component. An extract is accessed by addressing a main memory included in the apparatus. The processing means also includes a high-speed associative memory that has a plurality of locations, each location being capable of storing an extract. Each location is associated with a presence flip-flop and a reference flip-flop, each being initially set to a first logic state. The presence flip-flop is placed at a second logic state when an extract is loaded into the associated location. The high-speed memory cooperates with a comparison means that delivers, for each location, a coincidence signal having a first logic value when the address of an item of sought information coincides with the address of an extract present in the location. The apparatus also includes threshold detection means for furnishing a threshold signal whose logic value indicates whether the number of extracts present in said high-speed memory is at least equal to a given threshold value. For each extract that is present, the state of the associated reference flip-flop is controlled by a management circuit for forcing the reference flip-flop to a second logic state when the coincidence signal indicates a match while the threshold signal indicates that the threshold has been reached.
The invention will be more fully understood from the following detailed description, in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of the processing means of a computer system that incorporates the invention;
FIG. 2 is a schematic diagram of an embodiment of the high-speed associative memory;
FIG. 3 is a schematic diagram of a control circuit of the reference indicators;
FIG. 4 is a schematic diagram of an implementation detail of the control circuit of FIG. 3;
FIG. 5 is a schematic diagram of a management circuit of one of the reference flip-flops;
FIG. 6 is a timing diagram illustrating the operation of the circuits shown in FIGS. 3, 4 and 5;
FIG. 7 is a block diagram of a selection circuit for determining the location of the high-speed associative memory into which a new extract is to be loaded;
FIGS. 8 and 9 are schematic diagrams of the implementation details of the circuit of FIG. 7; and
FIG. 10 is a schematic diagram of a control circuit for loading one of the locations of the high-speed associative memory.
With reference to FIG. 1, a high-speed associative memory 1 is connected so as to communicate with a controller 2 and with a portion of the circuitry 3 of a processor. In traditional fashion, the processor and its circuitry 3 is connected to the main memory (not shown). In particular, the circuitry 3 is a portion of the processor that relates to address translation, and includes an address development unit, generally microprogrammed for calculating the virtual addresses VA of the information sought. The firmware that controls the circuitry 3 executes searches in translation tables to obtain the real addresses as a function of the virtual addresses. This address translation is speeded up by the associative memory that includes a number n of virtual address registers VAR and the same number of real address registers RAR. The associative memory 1 also has a set of n flip-flops BPR associated respectively with the virtual address registers and real address registers. The combination of a virtual address VAi contained in the virtual address register with rank i and a real address RAi contained in the real address register of the same rank, constitutes an extract i. This extract i is associated with a presence indicator PRi whose logic state corresponds to the state of the corresponding presence flip-flop. A comparator 4 is connected to outputs VAi of virtual address registers VAR and receives from the firmware of circuitry 3 the virtual address VA to be translated. Comparison circuit 4 is validated by output signals PRi from the presence flip-flops BPR. Circuit 4 provides coincidence signals HIT i whose logic values represent equality between the virtual address sought and one of the virtual addresses contained in registers VAR. The HITi signals are provided to a validation circuit 8 that furnishes an address validation signal ADVAL to the firmware of circuitry 3, indicating whether address translation was successful.
In the event of a failure, the ADVAL signal initiates a micro-program that searches within the tables for the real address. Once a search has been done, the virtual address VAe and its associated real address RAe are applied respectively to input interfaces 5, 6 of the virtual and real address registers. The virtual and real addresses are then written in one of these registers under the control of write command signals WVRi and WRRi, respectively. If translation is successful, coincidence signals HITi authorize, via interface 7, reading of the real address register containing the translation sought.
Controller 2 comprises a set of reference flip-flops BRF associated respectively with the locations of memory 1, and with the extracts stored within those locations. The state RFi of the flip-flops BRF is determined by a control circuit 9 which receives coincidence signals HITi and which is connected to the outputs RFi of the reference flip-flops BRF. A selection circuit 10 connected to the outputs of presence flip-flop BPR and the reference flip-flops BRF delivers selection signals Si which are applied to a load control circuit 11 that delivers the above-mentioned WVRi and WRRi signals. Selection signals Si determine the virtual and real address registers into which a new extract not present in the table must be loaded. The write commands WVRi and WRRi are determined by the load control circuit 11 as a function of the selection signals Si and common write command signals WRR, WVR that are delivered by the circuitry 3 under control of firmware. The firmware controlling the circuitry 3 also furnishes a signal RS that controls the resetting of the presence and reference flip-flops.
The device in FIG. 1 operates as follows. When a virtual address VA is to be translated, the microsoftware controlling the circuitry 3 places the virtual address at the input of the comparator 4. In the event of a match, the HITi signals validate the real address register containing the translation sought and circuit 8 validates this address by the ADVAL signal. Control circuit 9 reupdates the state of the latter flip-flops as a function of the coincidence signals HITi, the number of extracts present in the high-speed memory, and the previous state RFi of the reference flip-flops. Selection circuit 10 reupdates selection signals Si according to the new state RFi of these flip-flops and the presence indicators PRi, to determine which new registers will receive the next extract.
In the event of a translation failure, the ADVAL signal triggers the microprogram that searches in the tables. Once the search has been executed, the corresponding extract VAe, RAe is presented to the inputs of interfaces 5, 6. Control circuit 11 then locates the extract according to the write signals WRR, WVR and selection signals Si. Once the extract has been loaded into the selected registers, the microsoftware controlling the circuitry 3 makes a new attempt to translate the virtual address to be translated.
According to one feature of this embodiment, control circuit 9 takes into account the number of extracts present in the memory. As long as this number is less than a given threshold value t, reference indicators RFi are kept unchanged and thus preserve the initial state (e.g., 0) which was imposed on them by the RS signal at the beginning of the process, for example, after a dispatch. As soon as the number of extracts present reaches or exceeds the value t, indicators Ri can be modified according to the classical pseudo-LRU algorithm. It will be shown below how this threshold can be detected in practice.
The value of the threshold is determined by searching for the optimum value of the number n-t which corresponds to the number of extracts loaded between the time the threshold is reached and the time when the associative memory is full. To accomplish this, use can be made of statistical data relating to, in particular, the number of extracts used by the processes between two dispatches and the age of the reused pages. Another solution consists of making system operation simulations with characteristic programs, varying the value of the threshold.
As a non-limiting example, for a universal computer of the multiprocessor type with n=32, t may be chosen to equal 24.
FIG. 2 shows the part of memory 1 associated with one of the extracts. The virtual and real addresses of an extract i assumed to be loaded are contained in virtual address register VARi and real address register RARi, respectively. The parallel output VAi of virtual address register VARi is connected to a first input of a comparison circuit 14 of comparator 4 whose second input receives the virtual address to be translated VA that is furnished by register Rc. A presence flip-flop BPRi is connected at its output PRi to the validation input of circuit 14. Output PRi is also connected to controller 2. The output of circuit 14 is connected to the controller 2 to the input of a synchronization gate 17. Gate 17 is synchronized by the first phase CK1 of a clock signal.
The parallel output of real address register RARi is connected to the input of an amplifier 18B validated by output signal RDi from synchronization gate 17. Signal RDi also validates amplifier 18A which receives at its input a voltage corresponding to logic value 1. The signals ADVAL and RAi from amplifiers 18A and 18B are sent to the firmware controlling circuitry 3.
The virtual and real addresses VAe and RAe that are to be loaded into the registers are initially placed in an output register Re of the firmware. The parallel output of register Re is connected to the parallel inputs of register VARi and RARi via amplifiers 15 and 16, respectively. Amplifiers 15 and 16 are validated respectively by signals WVRi and WRRi furnished by controller 2.
The circuit of FIG. 2 operates as follows. A clock (not shown) furnishes a clock signal with two phases CK1 and CK2. During phase CK2, the firmware of circuitry 3 places the virtual address to be translated VA in register Rc. During the next phase CK1, this address is compared in circuit 15 to the virtual address VAi contained in register VARi. If addresses VA and VAi are different, or if presence indicator PRi is at 0, coincidence signal HITi will assume a value of 0. As a result, during phase CK1 amplifiers 18A and 18B are maintained in a state of high impedance.
If, on the other hand, addresses VA and VAi are identical while presence indicator PRi is at 1, coincidence signal HITi assumes a value of 1. Thus, during phase CK1, real address RAi contained in register RARi is transmitted to the firmware of circuitry 3 by means of amplifier 18B. Simultaneously, the ADVAL signal is at 1, thus indicating the success of translation. Note that amplifiers 18A associated with the various memory extracts execute a wired OR function that can advantageously be accomplished by means of a precharged line during phase CK2 and selectively unloaded by one of the signals RDi during phase CK1.
To load a new extract into the high-speed memory, the microsoftware of circuitry 3 first places the virtual address VAe of the extract in register Re and activates the virtual address write control signal WVR of FIG. 1. If register VARi is selected, loading circuit 11 of controller 2 furnishes a WVRi signal which validates amplifier 15. Likewise, the corresponding real address RAe is then placed in output register Re and the WRRi signal validates amplifier 16.
FIG. 3 shows reference flip-flops BRF and their control circuit 9 in greater detail. Control circuit 9 is composed of a common control circuit 19B and an assembly of flip-flop BRF management circuits 19A. With the locations (pairs of registers) of the associative memory being referenced by the subscripts 1, 2, . . . , i, . . . , n, they are associated respectively with flip-flops BRF1, BRF2, . . . , BRFi, . . . , BRFn. Each flip-flop BRFi is controlled by a signal WRFi furnished by an associated management circuit GRF. Outputs RF1, RF2, . . . , RFi, . . . , RFn are connected to common control circuit 19B which furnishes to each management circuit GRF a prepositioning signal V for setting to 1 and a prepositioning signal CL2 for setting to 0. Circuit 19B also receives coincidence signals HIT1, HIT2, . . . , HITi, . . , HITn. Each management circuit GRF receives a signal HLi which is the coincidence signal HITi latched by a flip-flop BHL upon each phase CK1.
The operation of the circuit in FIG. 3 will be explained with the reference to FIGS. 4 and 5 which represent detailed forms of common control circuit 19B and management circuit GRF, respectively. By convention, the explanations will be given in positive logic. Common control circuit 19B of FIG. 3 includes an evaluation circuit 19C, a flip-flop BCL, and a synchronization circuit 19D. Evaluation circuit 19C has an evaluation line CL whose state indicates whether the saturation condition of the high-speed memory has been reached. Circuit 19C consists of a complex logic gate in CMOS technology whose line CL is precharged during phase CK2 by means of PMOS transistors P1 and P2. Line CL is evalutated as a function of signals HITi * and RFi *, respectively, which are the complements of the coincidence signal HITi and the reference signal RFi associated with the extracts contained in the high-speed memory. The state of line CL is latched by the flip-flop BCL upon phase CK1. The flip-flop BCL then provides a latched evaluation signal CL1 at its output.
Line CL is connected to ground VSS via a common NMOS transistor N3 and, for each extract, via the series arrangement including two NMOS transistors N1 and N2 whose gates receive respectively the signals RFi * and HITi * from the associated extract. This arrangement allows the following logic function (evaluated during phase CK1) to be implemented: CL=+* (RFi *.HITi *)
where +* is the NOR function applied to the set of logical products RFi *.HITi *, for all values of i. Transistor N3, blocked during phase CK2, contributes to precharging of line CL.
Thus, from the beginning of operation of the associative memory, when all the indicators are initialized at 0, line CL is unloaded at each evaluation phase provided that the saturation condition is not reached. The saturation condition corresponds to the case where all the reference indicators are at 1 except for the indicator that represents a coincidence event. If the saturation condition is reached, line CL retains logic value 1 during the evaluation phase, thereby reporting that the saturation condition is reached.
Synchronization circuit 19D includes an AND gate 21 with three inputs. A first input of the gate 21 receives the latched evaluation signal CL1, a second input receives phase CK2, and the third input receives an authorization-to-operate signal USE. The signal USE is a command signal furnished by the microsoftware of the circuitry 3.
Circuit 19D also has a NAND gate 20 with three inputs receiving, respectively, clock signal CK2, the command signal USE, and a threshold signal PRt which assumes logic value 1 when the high-speed memory loading threshold is reached. Gate 20 generates a signal V* which is the complement of the prepositioning signal V that sets to 1. Provided the locations are loaded in a given order, the threshold signal can be obtained simply by reading flip-flop BPRt whose rank is equal to the value of threshold t and that which was chosen.
FIG. 5 represents reference flip-flop BRFi and its associated management circuit GRF. Flip-flop BRFi is composed simply of two inverters mounted head-to-tail which furnish reference indicator RFi and its complement RFi *. The state RFi of flip-flop BRFi is controlled by line WRFi. Line WRFi can be unloaded via the series arrangement formed of two NMOS transistors N4, N5 or via an NMOS transistor N6. Transistors N4, N5 and N6 receive at their respective gates the HLi * signal which is the complement of the HLi signal, the CL2 signal, and the RS signal. As a result, line WRFi is unloaded when the RS signal is at 1 or when the CL2 signal is at 1 while the HLi signal is at 0. Thus, flip-flop BRFi is forced to 0 when the saturation condition is detected while the virtual address contained in the associated register does not match the virtual address to be translated.
Line WRFi may be placed at logic value 1 via the series arrangement formed of two PMOS transistors P3, P4 that receive the signals HLi * and V* at their respective gates. As a result of this arrangement, flip-flop BRFi is forced to 1 when signals V and HLi are at 1, i.e., when the virtual address sought matches the virtual address contained in the register, provided that the threshold is reached.
The full operation of the circuits of FIGS. 3, 4 and 5 will now be explained in relation to the timing diagram of FIG. 6. This diagram represents the changes in state over time of the signals CL, CL1, CL2, and V generated by the common control circuit 19B of FIGS. 3 and 4, as well as the signals HITi, HLi, and RFi associated with extract i of the associative memory 1 of FIG. 3. It is assumed that extract i is present, i.e., indicator PRi is at 1. It is also assumed that the threshold has already been reached, i.e., the signal V is at 1 during phase CK2, hence the signal V* is at 0 during this phase. Finally, it is assumed that at initial time t0, the reference indicator RFi and the latched evaluation signal CL1 are both at 0.
Precharging of line CL of circuit 19C starts at time t0 during phase CK2. Starting at time t1, during the following phase CK1, coincidence signal HITi, assumed to have value 1, is evaluated. During this phase, signal HITi is held by flip-flop BHL whose state HLi goes to 1. At the same time, line CL is evaluated. Assuming that saturation is not reached, signal CL goes to 0 and signals CL1 and CL2 also remain at 0. During the next phase CK2, starting at time t2, line CL is once more precharged. Also, with coincidence signal HLi and validation signal V at 1, transistors P3 and P4 of management circuit GRF conduct, and line WRFi is charged to a positive voltage, thus forcing indicator RFi to 1.
During the next phase CK1 after time t3, assuming that there is no match, coincidence signal HITi goes to 0 thus forcing signal HLi to 0. Still assuming that the saturation condition is not reached, line CL is set to 0 during this phase and signals CL1 and CL2 remain at 0. As a result, during the next phase CK2 after time t4, signal CL2 at 0 keeps transistor N5 in a blocked state, thus preventing flip-flop BRFi from being reset to 0.
During the next phase CK1, after time t5, we have assumed that the threshold condition was reached and signal HITi was at 0. As a result, line CL remains high, thereby setting the state CL1 of flip-flop BCL to 1. Thus, during the next phase CK2 after time t6, the prepositioning zero-resetting signal CL2 goes to 1, making transistor N5 conduct. Since signal HLi is at 0, transistor N4 also conducts and line WRFi is unloaded and indicator RFi is reset to 0. The above description shows that the associative memory always operates in accordance with two clock phases, even when the reference indicators must be reset to 0.
FIG. 7 represents selection circuit 10 of FIG. 1. We find presence flip-flops BPR1, BPR2, . . . , BPRi, . . . , BPRn, and reference flip-flops BRF11, BRF2, . . . , BRFi, . . . , BRFn, associated respectively with extracts of rank 1, 2, . . . , i, . . . , n from the associative memory. Each extract i has associated with it a selection cell SC and two propagation circuits PC that propagate a request signal, associated respectively with extract presence and reference flip-flops. Each propagation circuit PC furnishes a request signal VPi or RPi, and receives indicator PRi or RFi, of the associated flip-flop, as well as request signal VPi-1 or RPi-1 from the upstream propagation circuit.
Output VPn of propagation circuit PC associated with presence flip-flop BPRn of the last extract of rank n is applied to the request input of the propagation circuit associated with reference flip-flop BRFi of the first extract. In addition, the request input of propagation circuit PC associated with presence flip-flop BPR1 of the first extract continuously receives a signal representing the existence of a request. In the example shown, we assumed that a request was present when the associated request signal was at 1. Alternatively, the reverse convention could be chosen without thereby departing from the framework of the invention.
Each propagation circuit is designed to deliver a request signal VPi, or RPi, that represents the existence of a request when the upstream request signal VPi-1 or RPi-1 indicates the existence of a request while indicator PRi or RFi is at 1. Moreover, selection cell SC furnishes a selection signal Si representing the selection of an extract i when one of the upstream request signals VPi-1 or RPi-1 reports the existence of a request when the associated flip-flop BPRi or BRFi is at 0.
The circuit in FIG. 7 operates as follows. As a function of the state of the presence and reference flip-flops, the request signal permanently applied to the input of the propagation circuit associated with first presence flip-flop BPR1 propagates stepwise, in increasing extract order, via propagation circuits associated first with the presence flip-flops, then via propagation circuits associated with the reference flip-flops. Propagation of the request signal stops at the propagation circuit that is associated with a presence flip-flop or reference flip-flop which is at 0. The selection cell associated with this extract then places selection signal Si at a specific logic value, indicating that a new extract must be written in the associated registers.
Thus, the circuit of FIG. 7 always allows the location of the associative memory that is to receive a new extract to be pinpointed. The loading algorithm employed by this circuit thus consists of searching, in ascending order according to the ranks assigned to the locations, the first location containing no extract (the first whose presence indicator PRi is set at 0), then the second extract which has not been used recently (the first whose reference indicator RFi is set at 0). According to this arrangement, updating of selection signals Si is automatically controlled by the change in state of the presence and reference flip-flops.
Due to the cascade arrangement of a propagation circuit, its reaction time is fairly long. Fortunately, the selection signals are not utilized until after the search in the tables for a new extract to be loaded, which is also a fairly lengthy operation. However, the slowness of the selection circuit may become cumbersome if the associative memory has a large number of extracts. Thus, to overcome this slowness, and according to one advantageous embodiment of the invention , optimization of the selection cells and propagation circuits is employed to reduce the number of layers of these circuits, thereby increasing operating speed. Accordingly, two different types of cells are provided, each type respectively associated with either odd or even rank locations.
FIG. 8 shows selection cell SCI and propagation circuits PCI associated with an odd-ranked location. Propagation circuits PCI each consist of a NAND gate receiving, at a first input, associated indicator RFi, PRi and at a second input, upstream request signal RPi-1, VPi-1. The PCI gates deliver at their outputs the request signal complements RPi *, VPi *. The SCI cell is a complex logic gate which receives at the input the upstream request signals RPi-1, VPi-1 and complements RFi *, PRi * of indicators RFi, PRi. The SCI gate implements the equation: Si *=(RFi *.RPi-1 +PRi * VPi-1)*
To obtain signal Si, the output Si * of the SCI gate is connected to an inverter.
FIG. 9 shows a selection cell SCP and propagation circuits PCP associated with an even-ranked location. The propagation cells PCP are implemented by NOR gates that receive, at a first input, the complement of associated indicator RFi, PRi and at a second input, the complement RPi-1 *, VPi-1 * of request signal RPi-1, VPi-1 coming from the preceding odd stage. Selection cell SCP is a complex gate receiving at its input indicators RFi, PRi and complements of associated request signals RPi-1, VPi-1. The SCP gate delivers selection signal Si verifying the preceding logical equation. Cells SCI, SCP, and gates SCI, PCP can easily implemented in CMOS technology.
Finally, FIG. 10 represents the circuit for generating write command signals WVRi and WRRi associated with registers VARi and RARi respectively as a function of control signals WVR, WRR and selection signal Si. The circuit in FIG. 10 is made with AND logic gates allowing transmission of common signals for controlling the writing of virtual address WVR or real address WRR, validated by selection signal Si and synchronized by clock phase CK2.
Other modifications and implementations will occur to those skilled in the art without departing from the spirit and the scope of the invention as claimed. Accordingly, the above description is not intended to limit the invention except as indicated in the following claims.


text:
Temperatures aren't the only thing spiking in Illinois this year.
Illinois roadway fatalities have spiked by nine percent through July 2012, as compared to the same period in 2011, a spokesman for the Illinois Department of Transportation confirmed to NBC Chicago.
DOT officials say mild winter weather luring more people onto the roads at the beginning of the year and distracted driving, such as texting or emailing while driving, may be part of the reason for the increase in fatalities in 2012, despite a steady decline in the previous few years, the Chicago Sun-Times reports.
Department of Transportation officials believe distracted driving may have accounted for about 10 percent of the traffic related deaths this year.
There have been 536 traffic crash fatalities in 2012 across the state as of Thursday. The same period in 2011 saw 488 vehicle and motorcycle-related deaths.

subset: commoncrawl


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802.1X allows only Extensible Authentication Protocol over LAN (EAPOL) traffic through the switch port which an unauthenticated client is connected to. Normal traffic can pass through the switch port after authentication is completed successfully.
With 802.1X port-based authentication, network devices have the following device roles:
|Client (Supplicant)
|The device (workstation) that requires access to the LAN. Responds to the requests from the switch. Must be running 802.1X-compliant client software.
|Switch or Access Point (Authenticator)
|Controls the physical access to the network based on the authentication status of the client. Acts as a proxy between the client and authentication server, which requests identity information from the client, verify the information with the authentication server, and relays the response to the client. It is responsible for the re-encapsulation of the EAP and RADIUS frames for communication with a client and an authentication server respectively.
|Authentication Server
|Performs the authentication of the client. It validates the identity of the client and notifies the switch or access point whether the client is authorized to access the network. Currently, the RADIUS security system with EAP extensions is the only supported authentication server.
The EAP Architecture
EAP is designed to run over any link layer and use any number of authentication methods.
IEEE 802.1X Authentication Message Exchange
Below describes a typical WLAN 802.1X authentication process:
1) A wireless client becomes active on the medium. After the IEEE 802.11 WLAN Probe Request/Response, Authentication, and Association processes, the access point forces the port into an unauthorized state, which only 802.1X traffic is forwarded.
2) The access point replies with an EAP-Request Identity message to the wireless client to obtain the client's identity. The wireless client's EAP-Response Identity message, which contains the client's identity, is forwarded to the authentication server.
3) The authentication server authenticates the wireless client and sends an Access Accept (or Access Reject) message to the access point.
4) Upon receiving the Access Accept message, the access point relays the EAP-Success message to the wireless client and transitions the client's port to an authorized state and normal traffic is forwarded.
Note: Below lists the sequence of establishing WLAN connectivity with 802.1X authentication:
Probe Request, Probe Response, Authentication, Association, 802.1X authentication…
When 802.1X is enabled, ports are authenticated before any other L2 or L3 features are enabled.
Note: 802.1X is also considered as an efficient and effective alternative solution to port security.


text:
Craft Book Holders 11" - 48/pkg.
Store craft books/patterns all together with loose-leaf storage.
(37 reviews)
How do you like this product?
Share your thoughts with the Annie's community.
July 27, 2019
I love these for organizing magazines. I mark the binder on the outside so I know what is inside the binder. I subscribe to several quilting magazines and these keep them nice. I also flag (post it flags) so if I pull a binder and see a flag I know that magazine has something I want to make or read etc. These have saved me so much time.
March 16, 2019
I like to keep some of the "Just Cross Stitch" magazines that are designed for Halloween & Christmas. These enable me to keep them in one place in a notebook for easy access.
March 3, 2019
These have been great to use with the clear acid free sleeves for my family genealogy. Items idw to punch holes in which is all of it!! I go through so many of these and I sure was happy to find Annie's!! Thanks again
January 7, 2019
The binder book holders are great for use in music binders when we cannot punch holes in the music. I looked in all the stores in my area, craft stores, office supply stores, etc and none of them carried this item any more. So I looked online and found Annie's. Yayyy!!
September 15, 2018
I have purchased these from another company at more than twice the price. These even had the holes completely punched out no more removing little pieces of plastic. These are great to store your magazines in binders.


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Advance Tickets
You are interested in attending one of our events? Then you have come to the right place!
You are welcome to purchase your admission tickets in advance.
Tickets for all events are available at the Schloss Fasanerie museum ticket desk, which is open Tuesdays to Sundays from 10:00 to 17:00 from April to October.
You can also conveniently order your admission tickets online using the form below. We will then send you a booking reference number and our bank details. Once we have received your payment, we will send you your tickets (postage charges an additional 1.20 euros).
Please call us on 0661 / 9486-0 should you have any further queries or if would like to order tickets over the phone. We are sure you will appreciate that we are unable to reserve tickets for collection on the day.
Museum Schloss Fasanerie
Schloss Fasanerie
36124 Eichenzell
Tel: +49 - (0)661 / 94 86-0
Fax: +49 - (0)661 / 94 86-30
Email: firstname.lastname@example.com


text:
Ease Release 200
Ease Release 200 is an excellent general purpose release agent for making molds and casting parts. This product will release polyurethane elastomers, polyurethane foam, epoxy resin, polyester resins, platinum silicones, rubber and thermoplastic polymers. Ease release 200 is effective on aluminum, chrome, platinum silicone, epoxy, rubber and steel molds.
Ease Release 200 is easy to apply, fast drying and effective over a broad temperature range from 70°F to 500°F.
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text:
Friday, December 31, 2010
If this is your first time to share on Spiritual Sundays, you will find instructions if you click on Linking Info under the header picture.
10 comments:
Happy New Year Charlotte. I only started blogging in July, but because of Spiritual Sundays I've found many beautiful Christian women to share life with. Thank you for that wonderful gift. May the new year find you right in the middle of your destiny. Blessings to you and Ginger and your families.ReplyDelete
Happy New Year to you, too! Thank you, once more, for this weekly gathering place.ReplyDelete
Many thanks, Ginger and Charlotte, for hosting this site. Happy New Year!ReplyDelete
I'm so excited to see what God will do in this brand new year! I know He will use Spiritual Sundays to encourage people to draw closer to Him and walk in His light. God bless you both!ReplyDelete
Charlotte G.
First time linking with SS. Happy New Year to both of you! Thanks for hosting.ReplyDelete
Happy New Year guys...ReplyDelete
May you both be richly blessed in 2011.ReplyDelete
Happy New Year dear Ladies...ReplyDelete
What could be better than to begin a New Year getting married? that is where I was New Year's Eve, on the beach at a wedding.
Later the reception was in the hall of a small country church...nothing could be nicer or more blessed.
Happy New Year to Charlotte and Ginger and your families.ReplyDelete
May this new year keep us all well, safe, healthy and happy in His love.
Happy New Year to you all as well I hope 2011 will be a wonderfilled year for youReplyDelete


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Spies from both sides have infiltrated the enemy camp and will try to betray strategies. But like a battle of old the time and location have been agreed in advance.
Next weekend the port of Genoa, squeezed between the Alps and the Mediterranean, France and Tuscany, will host a showdown between around 100,000 protesters and 15,000 Italian security forces guarding the G8 summit.
Citizens who care about the environment, the poor and the voiceless will hammer on the door of unaccountable moguls who shape the planet's destiny.
Or thugs who crave mayhem will try to stop democratically elected world leaders pondering the problems of the age. Or both.
Genoa will be a crucial test of strength for the anti-globalisation movement. The warriors of Seattle bill this protest as their biggest yet.'We are witnessing the first stirrings of a cultural backlash to globalisation whose effects are likely to be significant and far-reaching,' said Jeremy Rifkin, one of the movement's gurus. 'Local cultures are reawakening every where in the world.' Dialogue between protesters and the Italian government has failed to produce agreement. Leaders of the world's seven most industrialised economies, plus Russia, will meet in the ducal palace. And demonstrators will try to stop them.
'We are going to start a great battle,' said the website of Rete Contro G8, one of the estimated 700 protest groups. A minority have pledged to use violence.
It appears an uneven contest. One of Italy's biggest security operations will mobilise at least 15,000 police and soldiers, including paratroopers and specialists in nuclear, germ and chemical warfare.
Twelve helicopters and four reconnaissance aircraft will zip overhead, warships and mini-submarines will prowl the bay where the 58,600-tonne cruise ship, European Vision, will play host to most of the summit participants.
A battery of Spada ground-to-air missiles will bristle at Christopher Colombus Airport, lest the al-Qaida terrorist group headed by Osama bin Laden tries an airborne spectacular.
For Italy's newly minted Prime Minister, Silvio Berlusconi, Genoa is a chance to strut the world stage. He has micro-managed the preparations, even down to re-arranging the furniture in George Bush's suite.
Nudged by UN chief Kofi Annan and the Pope, the authorities have promised to allow freedom of protest, even to respect and listen to it. 'It will be an open city,' says the mayor. After all Genoa hosted the Crusaders on their way to the holy land.
But the reality is that today's righteous warriors are not welcome. To impede and deter protesters, Italy yesterday suspended the Schengen agreement assuring free movement around the European Union.
Both of Genoa's railway stations will close from Tuesday. Those protesters who make it to the city will be confronted by police with live ammunition, rubber bullets, batons, dogs, horses and armoured personnel carriers.
Already the atmosphere in Genoa is tense. Hospitals have been put on alert, prisons prepared and extra magistrates drafted.
Yesterday police cars lined piazzas and dogs sniffed railings stacked beside fountains. Residents joined tourists heading for the airport, leaving a queasy rearguard to swap rumours. 'A lawyer told me a mass grave has been prepared in the mountains,' said one taxi driver grimly.
It will be a battle of colours. The authorities have declared the historic centre and port area a 1.5 sq mile 'red zone', with the Ducal palace at its heart. This is the forbidden city, off-limits to all except participants, journalists, security forces and residents.
A buffer area known as the 'yellow zone' will allow entry to the uninvited, but can be sealed off within minutes should the need arise.
The demonstrators will be a hotch-potch of environmentalists, anarchists, socialists and those wanting debt relief for the Third World.
'Protests in the 1960s were sparked by one international event - Vietnam,' said Keith Dowding, professor of political science at the London School of Economics. 'Now they are also sparked by an international event - globalisation.
'Another similarity with the Sixties is that today's protesters are middle class. That must be worrying for governments who rely on their middle classes to put them in power and keep their economies running.'
Italy's security services categorise them thus: red for moderates, yellow for passive resisters, blue for the lefties of Italy's social centres and black for revolutionaries.
The black and elements of the blue, a hardcore of around 2,000 Greeks, Basques, Britons, Germans and Italians, are expected to defy the control and peaceful tactics of the umbrella protest group, the Genoa Social Forum.
The GSF's spokesman and effective general, Vittorio Agnoletto, has promised to resist their infiltration but his main job will be using his force of numbers to invade the red zone. Not easy when you have disdained weapons and violence.
One source said the protesters, some impersonating journalists, would create noise, smoke and spectacle to confuse the police before dispatching groups with ladders to scale blockades to selected entrances. But these will be feints, intended to draw police reinforcements. The real targets will be rushed once the opponent is committed elsewhere.
The shock-troops will be the Tute Bianche (White Overalls), whose padding, shields, gas-masks and discipline have made them the stars of other protests worldwide. Electronic experts from each side will try to jam the other's radio frequencies.
A week ahead and steel shutters have already slammed down on some shops; others emit the sound of sawing, where wooden shutters are being prepared. Sirens blare as police cars rush in convoy from one meeting to another.
'If they get through one entrance there'll be a river of them and we'll all be trapped inside the red zone,' said one commander. A bit like waiting for the Zulus at Rorke's Drift? It was a joke but he nodded gravely. 'Exactly.'


text:
Houses divided. Tailgates. Sideline coaching.
Wherever your allegiances lay, it's time to grab the pom poms and plug in the crockpot. Even better, suit up and hit the gridiron, court, pool or gym to hone your own personal athletic goals and enjoy Atlanta's slightly cooler temps. In this issue, learn about how Meetups can help you find your next workout partners or even a kickball team to join nearby.
Our sporty coverage this month brings you an introduction to Brian Gregory, Georgia Tech basketball coach. He gives us an insider's prediction for the Yellow Jacket 2015 season. Closer to home, meet the generous and community-minded Dunwoody High School football coach, Mike Nash. Go Wildcats!
Back on the gridiron, we bring you a peek inside the Georgia Bulldogs Playbook, a book focusing on the greatest plays along with detailed player formations for each play. That's serious business from college football historian Patrick Garbin.
To help you get into the groove, we are thrilled to offer YOU an inside tour of the new College Football Hall of Fame, through the eyes of CEO John Stephenson who grew up in Sandy Springs. Take your family and friends down to explore on a bye day and enjoy 15 percent off with the code LIFESTYLE15. We've got a bit of sports fever this month and are also offering your family a chance to win a Braves package including four terrace level seats, parking pass and access to the 755 Club for the October 1 game against the Washington Nationals. Go to PerimeterNorthLifestyle.com and click on the banner to enter.
Have a sporty month and GO Rocks, Wolverines, Britons and Ducks (Plymouth Salem High School, University of Michigan, Albion College, University of Oregon – my alma maters and home teams!).


text:
Below are the available bulk discount rates for each individual item when you purchase a certain amount
A convenient reference for an office or classroom! This laminated chart is 24" x 33" and is perfect for hanging on the wall in a classroom, physician's office, or pregnancy or STI testing center. It offers a comparison of 9 sexually transmitted infections answering four common questions for each - What is it? - How do you get it? - How will I know if I'm infected? - How it is treated? Quantity discounts available.
Quantity Discounts:
Buy 10-24: $18.99 each
Buy 25+: $15.99 each


text:
During an examination an ultrasound transducer is passed into the rectum of a cow and placed over the reproductive tract. The ultrasound machine displays a black and white image of the ovary or uterus. Ultrasound reveals far more detail than can be gained by traditional rectal palpation. The most practical uses of ultrasound in reproductive management of beef cows are for pregnancy diagnosis and fetal sex determination.
Early Pregnancy Diagnosis
Ultrasound pregnancy diagnosis has been reported to be 100 percent accurate by 20 days after breeding. In real life however, it is more practical to wait until day 25 to 30 of pregnancy to detect an embryo. By that time the embryo is a little larger and more easily spotted on the ultrasound screen. The efficiency (speed with accuracy) of detecting early pregnancy with ultrasound is markedly increased when the embryo can be detected more easily. Therefore, when scanning large numbers of cattle, it is more practical to scan cows that are at least 26 days pregnant.
Pregnancy detection with ultrasound offers several advantages over rectal palpation when used 20 to 100 days after breeding. In addition to allowing earlier detection of pregnancy, fetal aging during that period to predict calving date can be more precise if fetal body parts are measured on the ultrasound screen rather than estimated by hand. Reducing the handling of the pregnant tract by using ultrasound rather than palpation should also reduce the risk of inducing embryonic death when searching for early (< 45-day) pregnancies. After 100 days into pregnancy the fetus has usually descended too far into the cow to be reached with the ultrasound transducer via the rectum, therefore, many of the advantages of ultrasound over rectal palpation by hand are lost after that time.
Accurate early pregnancy diagnosis is valuable in an A.I. breeding program because it can be used to verify early breeding and enable movement of pregnant cows out of confinement, thereby decreasing feed costs. For example, in one large purebred herd on the Oklahoma/Kansas border 1,800 cows are gathered off wheat pastures and confined in pens on Oct. 1 to begin the breeding season.
In the breeding pens the cows are fed harvested feed and supplement. Between 25 and 35 days after A.I. breeding each cow is pregnancy checked with ultrasound, and pregnant cows are quickly moved out of the pens and back onto wheat pasture to reduce feed costs. This ranch paid for a new ultrasound machine with the savings on feed cost after one month.
Ultrasonography offers the unique opportunity of determining if an embryo is alive by viewing the heartbeat of the embryo during pregnancy diagnosis. We have studied embryo loss in beef cows on several ranches. We found that from 25 and 65 days after breeding 4 to 8 percent of the cows that were pregnant lost an embryo. Hence, although early pregnancy diagnosis with ultrasound is possible and has advantages, re-checking pregnancy at 90 days or later is advisable. At the ranch described above cows turned out on wheat pasture were still observed once a day to pick up any heats that occurred due to embryo loss, and they were re-checked by palpation before the calving season started.
If a cow is examined with ultrasound and observed to have a dead embryo in her uterus (no heartbeat) at 25 to 65 days after breeding, we have found that treatment with a drug (e.g., Lutalyse, Prostamate or Estrumate) to regress the corpus luteum and expel the dead embryo is followed by a heat two to seven days later.
Surprisingly, breeding at that heat has been more successful (50 percent preg rate) than we expected. Hence, detection of a dead embryo with ultrasound that might be missed by rectal palpation can be followed quickly by a return to pregnancy if the animal is treated and rebred.
Fetal Sex Determination
One of the most talked about uses of ultrasound technology is for determining the sex of a fetus at 60 to 80 days of pregnancy. Most often this information is used to merchandise cows or heifers more effectively. A cow sold with a heifer calf at side and known to be pregnant carrying another heifer would be a great deal for a buyer looking to build a cowherd. Conversely, pregnant commercial heifers carrying bulls would be a way to maximize return on the investment when every heifer has a steer calf at weaning next year. Either way, the buyer who knows more about the product he is purchasing usually feels more secure about his decision to purchase.
Male and female fetuses can be identified beginning 55 days after breeding by looking for the penis and scrotum on the males and the absence of those structures along with a vulva on the females. The accuracy of fetal sexing is high (> 99 percent) when the procedure is optimized by proper timing. Sex determination prior to 60 days is more difficult because the size of the genital structures is small. Therefore, determining the sex becomes easier as the fetus gets older.
However, the longer the cow is pregnant the greater the chance that the pregnant uterus will descend into the abdominal cavity which makes sexing difficult or impossible. These factors make the best window for fetal sexing occur between 60 and 90 days after breeding.
Cost of Ultrasound
The cost of ultrasound technology will depend on whether a ranch chooses to hire a technician or purchase an ultrasound machine for their own use.
Ultrasound units suitable for on-farm use cost between $5,000 and $12,000. Most farms don't have enough demand to justify that cost, nor do most ranchers have the desire to learn how to operate an ultrasound machine. Therefore, in most cases hiring a technician for occasional work is more sensible.
Hiring a veterinarian to pregnancy check with ultrasound instead of by rectal palpation usually increases the price of pregnancy checking by $1 to $8/head, depending on the number of animals being checked.
Like all management practices, the use of ultrasound is justifiable in some situations, but not others. Knowing and utilizing the advantages of ultrasound will make some progressive producers more successful.
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As I mentioned last year, I use the time waiting for the doorbell to ring to do my yearbook entry. This year, we spent the evening with friends and it completely slipped my mind! 5 days late isn't too bad though.
My activity here was still mostly watching what everyone else does and commenting here and there. I did manage to post 2 projects.
The cutting boards were a big hit. One of them (the largest) stayed here at home and still looks great.
The Something with an R box was one of those long-term gift projects I mentioned last year. I finally finished it and was able to post a blog on its creation. Another gift that was much appreciated…
I sound a little like a broken record (how many people know what that means now?) but I have several projects in the works. Pictures are in the camera – life is a bit busy these days. I'm looking forward to a retirement where I can spend more time on my woodworking.
I continue to enjoy spending time here every morning before I go to work and see the fine work of everyone here.
-- Steve - Impatience is Expensive


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Exquisite Estate Home in the Heart of Southlake is located on the Prestigious White Chapel Boulevard! Location is Everything! This home has been completely transformed with a Multi-Million Dollar Remodel! This estate is on over 5 acres of lush and manicured landscape, offering Over 2000 Sq Ft of Resort Style Outdoor Living Area, Claffey Pool & Spa, Half-Mile Crushed Granite Jogging Trail, 4 Golf T Boxes & Practice Greens, Professional NCAA Sand Volleyball Court and Beautiful Pond with Water Feature & Bridge. Included in the almost 11,000 square ft. home is a 1200 sq ft Private Guest Quarters offering 2 bedrooms, Living Room, Kitchen and Abundant Storage! This Home Offers the Very Best in Luxury Living!
Attached, Circle Drive, Front, Garage, Garage Door Opener, Golf Cart Garage, Oversized
Decorative Lighting, Flat Screen Wiring, High Speed Internet Available, Multiple Staircases, Paneling, Plantation Shutters, Vaulted Ceilings, Wet Bar, Window Coverings
Built-in Coffee Maker, Built-in Icemaker, Built-in Microwave, Built-in Refrigerator/Freezer, Cooktop - Gas, Dishwasher, Disposal, Double Oven, Oven - Gas, Range/Oven-Gas, Refrigerator, Vent Mechanism, Water Line to Refrigerator
Decorative, Gas Logs, Gas Starter, Stone, Wood Burning
Grill, Balcony, Covered Porch(es), Gutters, Lighting System, Outdoor Living Center, Patio Covered, Sprinkler System
Acreage, Interior Lot, Landscaped, Lrg. Backyard Grass, Some Trees, Tank/ Pond
|Price Reduced from $5,600,000 to $5,500,000
|$100,000 (1.79%)
|Price Reduced from $5,900,000 to $5,600,000
|$300,000 (5.08%)
Users may not reproduce or redistribute the data found on this site. The data is for viewing purposes only. Data is deemed reliable, but is not guaranteed accurate by the MLS or NTREIS.
Listing information last updated on January 29th, 2020 at 2:45am CST.


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In the opinion of one of the greatest cryptologists of all time, William F. Friedman, the invention of writing formed the true beginning of civilization. But not too long after writing really got established, various people found a need for writing that could only be read by an intended recipient, but not anyone else.
There were (and are) many ways to conceal writing. There are actually two separate methods generally used for messages: codes, which use symbols or groups of letters to represent words or phrases, and ciphers, where one letter is replaced with another by a either simple or a complex scheme. To those who aren't cryptologists, both codes and ciphers are usually referred to as codes.
Codes, as used in sending messages, may be an easy collection of letters, such as the non-secret SOS, meaning, "I am in difficulty and am requesting assistance." For more complex messages, both the sender and recipient have Code Books. These are listings of letter combinations and what they mean. The sender uses phrases that when strung together comprise the intended message. The recipient checks out the letter groups, and translates them to the phrases, recovering the message.
Radio Orphan Annie appeared on the airwaves beginning in 1931 sponsored by The Wander Company's Ovaltine. The Ovaltine account was handled by Blackett, Sample & Hummert, who also wrote the scripts, and most first developed the idea for offering a decoder. ROA (Radio Orphan Annie - as the show was known) began telling listeners in 1934 to join her Secret Society; an exclusive club in which members could participate in helping Annie solve some of the mysteries with which she found herself faced. It was a brilliant idea by the sponsor to promote Ovaltine. The product was needed for members to get the seal to send away for the necessary premiums. The Radio Orphan Annie Secret Society provided new members with a membership badge and manual. The booklet included a code scheme based on a number sequence that was counted by two's beginning with the number two. Thus, A would equal 2; B would equal 4 and so on up to Z that equaled 52. No odd numbers were used since each letter was its normal position times two.
In 1935 a brass decoder was offered as a premium. The decoder was in fact a cipher disk with a number sequence from 1 to 26 superimposed over a scrambled alphabet outer disk. By turning the inner disk number to the particular code key, one could easily translate any message given. Thus if the code key was Y-19, the number 19 would be paired opposite the letter Y. Then if the first number sequence of the message began with 5, one found the 5 on the badge and looked at what letter was opposite it. The code was not so easily broken since the letters were scrambled on the decoder badge.
However, there were also Code Books used for security. Both military and diplomatic organizations employed these routinely. At least until World War II, Code Books have been considered a very secure means of transmitting messages. However, there are disadvantages with using Code Books. One is that they're relatively bulky, and thus are more difficult to guard than, say, pocket-sized items. Another is that they're easily compromised. If a code book is stolen and photographed or otherwise copied, and then replaced before anyone knows it was missing, then whoever did so will be able to decrypt any message. Code books have been made obsolete as ciphering technology has evolved.
Ciphers have been in use since at least Ancient Rome, and there are indications in ancient writings that they were in use earlier than that. Julius Caesar developed a very elementary cipher, but it seemed to serve him well. What he did was replace every letter in the alphabet with one three places down in position. In this scheme, a=D, b=E, c=F, etc.; thus, "code" would be represented by FRGH. To regain the original message, the recipient just reverses the process. Because of who authored it, the process is called a "Caesar Substitution" cipher.
The Caesar Substitution cipher, and all like it were called "simple substitution" (to the cryptologist, "monalphabetic substitution") because throughout the message, each character was always replaced by the identical cipher character (e.g., in the Caesar Substitution, "F" would always represent "c" throughout the message). An invention by Leon Battista Alberti, an Italian, in the 15th Century, both refined simple substitution ciphers and started a more complex form, known as "polyalphabetic substitution," which is the key to modern methods. What Alberti did was to invent the Cipher Disk.
A Cipher Disk consists of two concentric circular scales, usually both of letters, but one possibly of numbers, with the inner scale on a rotatable disk. This meant that the two scales could be repositioned with respect to each other. If the two disks were both the standard alphabet, and the second alphabet was moved three places over, the result would be the Caesar Substitution. But the two alphabets could be positioned at any of 26 relationships (practically, 25, since one of the positions would result in the "ciphered" message being the same as the original (called "plaintext" by cryptologists). A number of so-called "decoder" devices use a cipher disk as a simple substitution device.
Simple substitution ciphers, though, are relatively easy to crack (cryptanalyze). Since each character in the cipher represents the same letter, the use of statistics can help determine the most likely letters in a message. For example, it's known that the most-used letter in the English language is "e," so by counting all the letters in a message and determining which is the most used character would mean that it might be an "e." In addition to statistics, there are other ways to determine which letters are probably in a message: for instance, every word has a vowel of some sort in it, and so one-letter words are almost certainly vowels ("a" or "i").
|One type of Caesar Substitution was the Vigenére cipher which is the sequence of Caesar ciphers with different transformations. For example, first letter of text is transformed using ROT5, second - using ROT17, etc. The sequence is defined by keyword, where each letter defines needed shift. Phrase LEMON, for example, defines the sequence of ROT11-ROT4-ROT12-ROT14-ROT13, which is repeated until all block of text is encrypted. You can try out the cipher here using either defaults or simply input your own key word and phrase to encode. Click here to try it.
But the cipher disk opened another possibility. Suppose both sender and receiver agree that after every tenth letter, the rotatable disk (called the "rotor" by cryptologists) will be moved one character clockwise. Then, after the first ten letters of the message, all the characters change. And after the second ten letters, the characters change again, and so on. This makes it much harder to cryptanalyze the message, since neither simple statistics nor single- or two-letter words would help as much in a vowel hunt. This polyalphabetic substitution scheme, and other, more complex forms than Alberti developed, form the basis of modern high-security cryptological messaging. (Thomas Jefferson invented one that was more than a century ahead of its time (see left); although forgotten, it was reinvented in time for use in World Wars I and II).
By the 19th Century, polyalphabetic substitution ciphers had evolved. Particularly for battlefield and espionage activities, it was desirable to have a small, easily concealed, device to encipher and decipher messages, and here the cipher disk and some pencil-and-paper schemes developed into Field Cipher devices. Field Ciphers were not intended to be as secure as those between military bases and diplomatic missions, but if they could prevent an adversary from decrypting a message until it was too late, they served their purpose.
In 1867, Charles Wheatstone displayed what he called a Cryptograph. This was a primitive automated Cipher Disk, using two "hands" like those on a clock -- one long and the other short -- connected by gears, used for polyalphabetic messages. The arrangement incremented the smaller hand so that when the larger hand pointed to a letter, the smaller hand would point to its cipher equivalent, which would of course change at each following instance because of the way the gears were arranged.
By World War I, the major powers had extensive cryptological organizations. Possibly the best-known cryptological event of World War I was the Zimmermann Telegram incident. Throughout much of the war, the United States was uninvolved. Although sentiment in the United States had increasingly turned against Germany, to the point where the United States had broken off diplomatic relations, it still remained at peace. The British decrypted a telegram sent by the German Foreign Minister, Arthur Zimmerman, that proposed an alliance with Mexico: if the United States might enter the war, and if Mexico joined in the conflict, Germany would help them gain Texas, New Mexico, and Arizona, once Mexican territory. This decrypted message, attributed to American codebreakers, was released through the country's newspapers, and shortly thereafter resulted in the United States entering the war.
During the war, the United States' War Department founded MI-8, a cryptological group, which deciphered messages during and after the war. By reading enciphered Japanese diplomatic communications in the ensuing peace negotiations, the United States gained a decided advantage in bargaining. When it was later suddenly disbanded by the Secretary of State, who idealistically proclaimed that "Gentlemen shouldn't read each other's mail," the head of MI-8, a talented cryptologist named Herbert O. Yardley, wrote a highly popular and sensational book, The American Black Chamber, detailing the activities of the former group.
World War II employed highly sophisticated ciphers and even more sophisticated cryptanalysis. The Germans had adopted a commercial cipher machine, the Enigma, to military and diplomatic use for messages of the highest security. The machine used multiple rotors with electrical connections to scramble letter substitutions in a highly complex fashion. It had been claimed that to crack the Enigma cipher would take thousands of years at a minimum, and mathematics were presented to substantiate the claim. The Japanese also adopted an Enigma machine variant for its highest cipher messages, as well. However, teams both in Britain and the United States independently began to tackle means of cracking the ciphers.
The British concentrated on the German messages. Building on Enigma-machine components smuggled from the Continent, plus a great deal of inventiveness on the part of the British team, which was located at Bletchley Park in England, the Enigma messages started to be read. Such messages (and the related cipher machines) were designated ULTRA.
The United States, under the directorship of William F. Friedman, one of history's greatest cryptologists, concentrated on the equivalent Japanese system, and cracked their messages. The highest-security cipher messages were designated PURPLE, and the related cipher machine was labeled MAGIC. Cryptanalysis had a significant impact on the war. ULTRA and PURPLE decrypts assisted the Allies in World War II in battle strategies.
Decryption of a lower-level Japanese cipher (designated RED) enabled the United States Navy to prevail at the Battle of Midway. Decryption of a PURPLE message enabled U. S. Air Corps personnel to locate and shoot down Admiral Yamamoto, who was flying to inspect some troops. ULTRA decrypts enabled Allies to intercept and destroy German submarines, a clear reversal to the situation when the war began. ULTRA intercepts helped Field Marshal Montgomery defeat Rommel at El Alamein. General Eisenhower indicated that ULTRA played a decisive role in the European theater. During the war, even more sophisticated cipher development took place. The Bletchley Park researchers developed COLOSSUS, an electronic device, which was a primitive beginning of electronic computers. Developed before the invention of transistors, the COLOSSUS device is considered a milestone in the development of today's computers. Also, William Friedman's group, in particular Frank B. Rowlett, developed a machine similar to, but more flexible than the Enigma device. Called SIGABA (see left), the machine was so successful that during the war, the German cryptanalysts gave up on even recording their intercepts of the messages. They found it impregnable.
After World War II, cryptological research and development didn't cease. The development of the electronic computer led to more complex enciphering schemes than were practical using mechanical components. The newer developments helped both in developing newer, more secure, means of communication, and newer, and more sophisticated ways of cracking secret messages. This has carried through the Cold War to the present day.
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It has been a while since I wrote a post for Lean Directions, but I have not been idle. You can keep up with my thoughts every three weeks on the Gray Blog. Be sure to check out the articles from my co-bloggers while you're there...
Aug 7, 2015
Aug 11, 2014
Leadership style and neural networks - Part 3
A three-blog collaboration continues as Jeff Hajek hosts part 3 of our series on brain research and leadership style choices on his Gotta Go Lean blog. Co-blogging with Matt and Jeff has been rewarding because of the reviewing process before publication and our discussions on the possibilities of team blogging with a number of our colleagues. We didn't identify the way to make a true lean team blog, but worked through a lot of thought-provoking possibilities.
Jul 15, 2014
Leadership style and neural networks - part 2
Matt Wrye is hosting Part two of our neuro-leadership series on his blog, Beyond Lean. Thanks for sharing it with your readers, Matt. And if you don't know Matt or his blog, you are in for a treat.
Jun 24, 2014
Leadership style and neural networks - Part 1
You're probably familiar with the two leadership styles: task/objective-oriented leadership, sometimes called Theory X, or human/emotional-oriented, Theory Y. The American MBO model with its financial and quantitative goals leaves out the human dimension. People-oriented leadership, as exemplified by Toyota, can get better business results.
Task oriented and human oriented domains in the brainResearchers have now found two largely independent neural networks associated with these leadership styles, according to a recently published paper* by Richard Boyatzis, Anthony Jack, and Kylie Rochford of Case Western Reserve University. Functional magnetic resonance imaging (fMRI) has been used to observe the workings of the two networks as subjects in an experiment engaged in leadership simulations., however they did find an objective-oriented neural net, called the task positive network, or TPN, and a social domain, called the default mode network, DMN (it was first believed to be the brain's default state). They found that there is no "leadership" center in the brain. Each network integrates several different regions of the brain.
What's interesting about these findings is that each network actually suppresses the other when it is in use. Practice -- repeated firing of neurons over time -- makes a neural network stronger. The objective-focused leader is making the TPN stronger by using it more often, so the weaker DMN activates thinking about people less often. On the other hand, the people-oriented leader with a dominant DMN network may not do as well with TPN-oriented pursuits of quantitative goals or deadlines.
Does this mean that the management-by-numbers leader can't be a lean leader with active respect for people? The good news is that the brain naturally cycles between the two domains, so nobody's brain is in either mode permanently. Whether instinctively or with practice, the leader can activate the DMN in a situation related to people, and the TPN in problem solving or analytical tasks.
Some comments by lean leaders who previewed this blog post:
Matt Wrye: I find this to be fascinating and enriching as I reflect on my actions as a lean leader. I have never consciously thought about the two types of leadership. It helps me put into perspective situations where I have used TPN or DMN.
Analyzing data to understand value stream flows within a manufacturing facility or planning a week long improvement event are ways I have used TPN. Then I have to turn around and use DMN to help others understand the value stream flows I have discovered or to get others in the improvement event to not fear sharing and implementing their ideas.
Chris Paulsen: This is a very interesting revelation. We have all seen that some leaders have a natural bent towards connecting on a personal level while others are more task oriented. The best leaders are able to find the right balance for their leadership role. The great news is that we naturally cycle between the domains of our brain. This may explain how leaders are able to find a better balance with practice.
I'll be co-blogging this three-part article with Matt Wrye, of Beyond Lean, and Jeff Hajek, of Gotta Go Lean.
For more reading:
* Richard Boyatzis, professor of organizational behavior, Anthony Jack, assistant professor of cognitive science, and Kylie Rochford, a PhD student in organizational behavior, all at Case Western Reserve University, "Antagonistic neural networks underlying differentiated leadership roles." Frontiers of Human Neuroscience, March 4, 2014.
An easier-to-read press release regarding the paper: Case Western Reserve University, "Leaders wired to be task-focused or team-builders, but can be both." Science Daily, March 24, 2014.
Apr 7, 2014
Bad employees
As I discussed in my last post, the article, "Bad to great: The path to scaling up excellence" in the McKinsey Quarterly evoked my ire. In it, the authors discussed how to identify "bad employees" and get rid of them -- the old "bad apple" theory.
Let's look more closely at the destructive behavior the authors illustrated...
Tardy, unhelpful, discourteous salespeople irritate all of us. But how does the company's culture shape that behavior? Are managers late for meetings or prone to canceling them? Do they help frontline salespeople who should help customers? Do they show a lack of respect for salespeople? Are the employees overworked and underpaid, and under stress to perform well anyway? Or what is it about the hiring process that it can't identify people who are not customer-oriented?
A nasty nurse is no asset to the hospital floor. But nurses in a typical hospital are not happy, for a number of reasons. They want to devote their time to caring for patients. Hospitals, however, have inefficient processes that waste their time. Nurses don't want to search for supplies and equipment, wait excessive amounts of time for the doctor or supplies to show up, or rush because shifts are understaffed. And they're understaffed because unhappy frontline nurses find other jobs as soon as they can.
What made the nurse in the story snap at the doctor? A lack of respect for authority?
But doctors often act superior or arrogant. They fail to recognize that nurses are professionals too, usually with college degrees and years of direct patient care experience. The doctors have no monopoly on knowledge. They have no justification for commanding a routine blood draw. Who among us in an understaffed and disorganized workplace would not be out of patience? "Do it yourself" might be mild in comparison to what we would really want to say.
In the case of the thieving employees, supposedly, they were stealing for the thrill of it and status in the shop floor "gang." When the company spoiled the game by letting employees check out equipment for personal use, theft dropped. But maybe the reason theft slowed was not taking out the fun. It would depend on the perception of how management made the change. Was it that they outwitted bad employees? Or did management actually respect employees and trust them to return what they borrowed? If sincere, such a change, especially when accompanied by similar ones, could have simply reduced hostility.
The authors include fear as a reason for expulsion of potentially disruptive employees. But Dr. Deming said, "drive out fear," and he didn't mean to drive out employees who are afraid. Fear is not the fault of employees, and getting rid of them won't get rid of fear.
Later in the article, as I said, the authors come up with some more useful advice. A culture that welcomes admitting mistakes so root causes can be found gets better performance. They also advise, "Employees work harder and more loyally if you explain your actions, talk about how changes will unfold, and treat people with dignity." Management can foster feelings like fear and powerlessness or they can show respect.
What management behaviors create beliefs that are part of the employee subculture? What emotions are connected to those beliefs, and what employee behavior does that drive? If behavior and feelings are the result of a belief that so-called leaders are selfish, dishonest, nasty, and dictatorial, who needs to change their ways first, employees or management?
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Mar 30, 2014
McKinsey proves that today's management culture has a long way to go
The first issue of the McKinsey Quarterly for 2014 was entitled, "Shaping the future of manufacturing." Proof that management culture, however, is still rooted in the past, is made plain in the article "Bad to great: The path to scaling up excellence." Not every article in this issue is backward: several are worth reading. But if this one got past the editor, McKinsey has problems.
In "Bad to great," the authors ask what to do with problem employees. Who are bad employees?
· Employees engaging in "destructive behavior -- selfishness, nastiness, fear, laziness, or dishonesty."
· Salespeople who are "tardy, unhelpful, uncooperative, discourteous to customers, or unproductive."
· Hourly workers like those who stole equipment worth a total of a million dollars every year from their employer.
· Subordinates like the nurse who, when the doctor said, 'Nurse, draw this man's blood,' she replied, 'Why don't you do it yourself?'"
· Salespeople who are "tardy, unhelpful, uncooperative, discourteous to customers, or unproductive."
· Hourly workers like those who stole equipment worth a total of a million dollars every year from their employer.
· Subordinates like the nurse who, when the doctor said, 'Nurse, draw this man's blood,' she replied, 'Why don't you do it yourself?'"
|This file is licensed under the Creative Commons Attribution 2.0 Generic license
In a culture where management labels people "bad" without understanding why they behave as they do, improvement will never stick. It's true that a few employees will resist change or engage in disruptive behavior. Some can be persuaded to at least give change a chance, and some will eventually be helped to find jobs elsewhere. They're not bad people. They just can't adopt the rules of a changed workplace culture.
This article's authors are from Stanford: Huggy Rao is a professor of organizational behavior and human resources and Robert Sutton is a professor in management science and engineering. Their book, Scaling Up Excellence: Getting to More without Settling for Less, has been excerpted for the article. Maybe the excerpt is not representative of the whole book. To be fair, later in the excerpt, they do come up with some alternatives to firing "bad" people.
What bothers me is not that someone has written a wrongheaded article. It is that a consulting firm influencing the largest, most powerful, companies believes an article like this reflects "shaping the future of manufacturing." If this is a product of McKinsey's culture, even if some of its consultants understand lean at its best, lean thinking faces worse barriers than I realized. And if this represents the current thinking at Stanford, we are making little progress. Can't say I'm surprised, but I am disappointed.
Mar 19, 2014
When management doesn't get it
Our last post identified a divide in a corporate culture between management and operational subcultures. I think that the failure to understand the importance of cultural differences is one of the reasons why lean initiatives fail. When lean champions come from operations and engineering, they have different criteria for success than executives do.
We have also talked about seven principles of change* identified by anthropologists that help explain cross-cultural change.
1. Consider your own psychology. Do you believe you have the only right way of seeing things? Is your attitude showing that you think management's beliefs are wrong? Or are they doing things right in the context of a different culture?
2. Beliefs direct behavior. In management's world, people need numbers and reports. Revenue, cost, profit, and growth. They feel no need to see your plant, value stream map, or throughput times.
3. Change must be seen from the point of view of those being asked to change. If the numbers look good, not only will they be rewarded financially, they will also bask in approval and admiration. Managers down the line get promoted. If the CEO gets raked over the coals when business is slipping, blame will be passed down to every level of the organization. If you want to change the way management believes things should be done, they can't be sure what will happen to the numbers. When you start talking about members of management devoting time to learning and coming to the gemba, there's nothing to motivate them.
4. Make no sweeping changes. Introducing a grand system of change can just be too much. This presents a dilemma for introducing change to top management because we know they need to grasp the nature of lean thinking as a system. That's why pilot projects are such a good way to start.
5. A significant change produces emotional tension. Are traditional company leaders heartless, unemotional, inconsiderate people? They may have to present themselves that way to gain and maintain status in a by-the-numbers business culture. Any change will produces fears, uncertainty, and threats to self-esteem.
6. Change often produces stress and frustration. If managers secretly worry that they can't succeed in a lean culture, what will they do? Even if it's only unconsciously, they may obstruct progress. Behind-the-scenes coaching can help. And develop empathy.
7. Harm to people. Persistent and intense stress threatens physical or emotional health, heightening pressure to prevent change. Some people are more vulnerable than they seem, making it important for lean champions to consider emotions as well as the intellect.
Putting yourself in a manager's shoes is easier if you read management books and magazines, as well observe behavior. You can learn more about your industry. To get management's attention, you also need to understanding the quirks and idiosyncrasies of the management culture in your company. If your changes help managers look good and get beat up less often, they will feel safer and put up less resistance.
But first, show them the money.
*Seven principles of cultural change
Principles one and two
Principle three
Principle four
Principles five, six, and seven
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