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This chapter is provided as a preview. Anybody who wants to can access it for free at http://www.EastCoastGames.com . We ask that no copies, physical or electronic; be lent or given. Offering this portion of the novel is expressly prohibited.
Luxury Nashua Secure Hiding Facility of Hunt's Security
As the meeting broke up, Carmen asked Jared, "Can I get a look at the builder code?"
Jared smiled and said, "Sure, Maybe you can find why it won't make hydrogen."
Carmen said, "Well, I doubt I'll be much help, but I'll certainly give it a look. What language is it in?"
Jared said, "It's an interpreted language called FastScript. Have you heard of it?"
She shook her head no.
"It's kind of like Java, but it's not object-oriented. It's also fairly simple, even if it's a tad slow for most uses. Fortunately the builders don't need the extra milliseconds that other languages would allow for."
"Cool; I know Java. It's a required language in high school."
"Really? It's so outdated. I guess it's just because the languages now used are based on it, almost like learning Latin."
Michelle was having a conversation with Sarah, so instead of interrupting they left. Jared picked up the builder and said, "There is a workroom I found down the hall that we can use as a lab for now. We can use a wireless connection to the builder there."
They walked down the corridor going deeper into the facility and came to a door marked 'Workroom D.' Inside the room were several computers, printers, and scanners on various tables. There were two office chairs to every computer. The room was designed in the same style as the hall except that the lighting came from some of the ceiling panels.
Jared walked to one of the computers and initiated a connection with the builder. He brought up the source code on the screen. FastScript was written in source code but translated into a file to execute using an interpreter. Unlike compiled languages, which are compiled into machine language to be run by the hardware of a machine, interpreted languages have interpreters. An interpreter is software that executes a file or set of files.
The source file for the builder was still small. Most of the complicated work was done by hardware, which Jared had an easier time working. While Jared could program, he did not really enjoy it or excel as a programmer.
They started going through the code. Carmen quickly caught on to the language because it was so similar to Java.
Carmen asked, "So what happens when you try to make hydrogen?"
Jared replied, "Well . . . nothing. It doesn't deconstruct atoms, and it doesn't build anything!"
Carmen said, "Do you think it has to do with the fact that hydrogen is the only element that has no protons?"
Jared said, "It could be. I'm really not sure. I tried hard-coding one neutron, but all that happened was that one neutron for each atom of hydrogen was assembled, no electrons or protons were formed."
Carmen said, "Have you tried debugging to see what all the variables are at when you are about to do a build?"
Jared shook his head no. "Let's try it."
FastScript comes with a debugging tool that allows you to place breakpoints wherever you want in the code. When the interpreter reaches the breakpoint, it brings up a debug screen that allows the coder to look at the values of all the variables in the various symbol tables. It also allows you to step through, or run, lines of code that follow the breakpoint line by line. Further, it allows you to run code through the interpreter with the variables as they are at the breakpoint and in this way to change the values of the variables. The debugger also allows users to navigate through the variables and edit them directly.
They placed two calls to the debugger, one before the deconstruct function call and one after the build function call. Jared then programmed the builder to make one atom of hydrogen using the debug version of the code. "Here goes," he said.
The builder powered up. Just before it took apart the needed matter, it stopped and showed the debugger screen on the computer to which they interfaced. They poked around the symbol table looking at all the variables that the functions would use, "Here, look at this!" exclaimed Carmen. "The proton and electron values for hydrogen are both 0 when they should be 1. That explains why it builds nothing! Let's look at the code that initializes it."
They exited the program without finishing its execution. Then Carmen found the BuildElementTable() function.
// This function builds the element table
void BuildElementTable(ElementTable &New)
int Electrons = 1;
While (Electrons++ < 117)
New[Electrons].Electrons = Electrons;
New[Electrons].Protons = Electrons;
"Mr. Miller, look at this."
"Please don't call me Mr. Miller. My father was Mr. Miller. I'm Jared. Please call me Jared."
"Are you sure?"
"Yes, very! Whatever you do, don't call me Dr. Miller . . . that's even worse."
"OK, Dr. Miller," she said with an evil grin.
He teased, "Why was I was showing you this again? . . . So, what do you see?"
"Look at this function," she pointed to the part of the screen that had the BuildElementTable() function. "Electrons is initialized with one, but then in the looping condition it is incremented. So when the first element is run, Electrons is equal to two for helium, and hydrogen is skipped!"
Jared slapped his forehead in the universal sign of oops! "Wow, we're lucky I used FastScript where the default value is zero as opposed to a language like C where the default value is whatever was in the memory location before! It would be almost random. If it had been a random number who knows how many radioactive and dangerous elements I would have made! Thank you so much for finding this!"
Carmen shrugged, "It's an easy mistake to make. It's always the little bugs that take the longest to find. You just needed a fresh pair of eyes."
Jared edited the code so that it was initialized with zero instead of one. "Now we can finally try to make water!" He translated the code and programmed the builder to create a small amount of water. "Here goes." He pointed it towards the floor and pressed the build button. A small amount of water suddenly appeared a foot from the floor and then fell with a splash. "IT WORKS! IT WORKS!" He threw his hands up in the air in enthusiasm. "We better make sure it's really water."
"How?" asked Carmen.
"I guess we can try the old-fashioned way. See if it boils at 100 degrees and freezes at zero. Time for a field trip to the kitchen!"
Jared led them back into the hall to the kitchen. The kitchen was huge. It could easily be used to cook for 1000 people, even though there would be no room for that many people in the facility. There were two long commercial class steel counters, an oven, a set of 12 burners, and a grill. A deep fryer was adjacent to the grill. There was also a commercial mixer. The floor was covered in rough red tiles. The ceiling was cement and had a huge vent for the grill and burners. There was a walk-in refrigerator and a walk-in freezer. There were various pots, pans, and ladles of different sizes hanging above the counters. Beneath one of the counters was a stack of cookie sheets and three mixer bowls. On the end of one counter was a can opener and a large set of knives. There were also some tall brown wooden cabinets, three sinks, and an industrial dishwashing system with a long conveyor belt.
Carmen took two metal pans down. Jared filled them both with water from the builder. Carmen put one pan in the freezer and Jared put the other pan on a burner. After a minute of confusion figuring out which knob was for which burner, he lit the burner. Carmen found a heavy-duty thermometer designed to hang from a lip into a pan. She attached it to the pan.
Jared said, "It looks like it's the right color and texture. Now we just need to wait and see if it really is water."
While they waited Jared asked, "How are your parents going to handle you wanting to disappear with us?"
Carmen blushed, "Don't you know?"
Jared shrugged, "Know what?"
Carmen sighed and said, "I'm an orphan. I thought you knew."
"Oh, I'm so sorry. I didn't know."
"It's alright, my parents died when I was ten. I live in an orphanage."
"May I ask . . . how did they die?"
"It was a car accident. They were heading to work after they dropped me off at school. A truck hit them. The driver fell asleep at the wheel. I guess he was hauling some high tech stuff that was late, and he had been up for 48 hours. A little before lunchtime at my school the police came and took me out of class to tell me. For a while, I blamed myself for their death because I had made us late leaving. I was really depressed, but I finally got over it. I didn't have any family so they put me into the orphanage."
"I'm so sorry."
"It's OK. I really don't remember them that well now. I do miss them from time to time, but I'm past that part of my life."
"I can't imagine what that would have been like. I don't think I could have lived through something like that."
"Well, you have to. I was lucky; I was able to put it past me. Some people I know lost family in similar ways and still can't cope with the loss after years. It seems to affect everybody a little different."
The water started to boil. Jared checked the thermometer and it was 100 degrees. "Perfect. It will be awhile before the other pan freezes. Let's do a pH litmus test and check the density."
"Do you have litmus paper?"
"Yes, a chemist is always prepared." Jared pulled out his wallet where he had several litmus strips and took out one. He wet it with the water and it turned green for a perfectly neutral 7.0 pH. "Excellent, 7!"
"So now we need some metric equipment. I'm guessing you don't store that in your wallet?"
"Nope, but this is a kitchen." They found a scale and a cup that measured in milliliters. They put a cup on the scale and set the scale to zero grams. They then poured some water into the cup. The cup read 105 ml and the scale read 105 grams. "Perfect. I should taste test it!"
"Are you sure?" Carmen shuddered.
Jared took a sip of the water. "Wow, this is pure water. Except . . . Except," he started clutching at his throat. Jared coughed, then fell to the floor. Carmen screamed, and Jared turned over saying, "Just kidding!"
Suddenly the door swung open and Sarah stepped inside holding her gun. Sarah asked, "What happened?"
Jared apologized, "Sorry, it was a bad joke. My bad jokes make people scream!"
Sarah holstered her gun. Jared stood up and Carmen punched him in the arm, "Don't do that again!"
"Ouch! OK, OK!"
Sarah shook her head and left.
Carmen looked at her watch, "I'd better get going. Allegedly pizzas don't deliver themselves!"
"What a nasty lie, obviously perpetrated by rightwing fundamentalist whack jobs! I'll let you know how the freezing goes. Will we see you again tonight?"
"No, I work late. I'll come by tomorrow after I finish some homework."
"OK, thanks for all your help! I guess you'll need Aaron or Sarah to get out."
"OK. Bye."
"Bye," he said as she left. He started putting everything away.
She walked back up the hall towards the exit. She found Sarah, Michelle, and Aaron talking in the meeting room.
"Can one of you lead me out?"
Sarah stood. "I'll take you."
Sarah led Carmen back through the way they had come in. When they got past the antechamber Sarah said, "Now, please remember not to say ANYTHING about the Millers or this facility. If anybody asks, you were hanging out, chilling, or whatever you kids call it now, with Keith."
"Don't worry, Mrs. Hunt, I won't say a thing."
Sarah changed the subject, "So, Kara tells me you're one of the brightest kids in your class."
Carmen shrugged. "There is a kid named Todd that's way ahead of me. In fact, he is way ahead of everybody. He's one of those genius kids that skipped some grades. He's only 14. If he doesn't skip ahead again he will easily be our valedictorian."
"Are you and Todd friends?"
"No, he sticks to himself. Actually, I guess we are both loners in a way. Your daughter though, she's really cool. She must make friends easily."
"I don't think it's so much her as it is how she gets involved with people and things. Like she's in the theater group and takes it very seriously. She spends so much time with it that we barely ever see her. It's almost like . . . never mind. I really shouldn't be saying that."
They continued on in silence. Finally, they got through the small tunnel and Sarah used a remote similar to Aaron's to bring down the fireplace. They both got in and were returned to the living room. Sarah walked her to the door and said, "I would walk to your car with you but they are watching us. You see that van over there?" Sarah pointed to an auto parts van parked across the road.
"Is that CTF?"
"Probably; they might follow you. Be careful, OK? If you need anything or get into trouble use this." She pulled out a small keychain with a red button on it. "If you push the button the microphone inside will be activated and transmit anything it hears through an encrypted transmission to our company through satellite. It will also send your location and body heat to us. As soon as it is pushed somebody from our company will be sent to you as quickly as possible."
Carmen said, "Do I really need it?"
"I hope not, but CTF seems to want Jared, so it's hard to say."
Carmen got into her car and then drove to her work. A white car was behind her during most of her pizza deliveries.
Keith and Kara had gone back into the house almost the minute the meeting ended. On the way there, they discussed what had happened.
"I don't want to go," started Kara.
"I do!"
Keith blushed and said, "Because Carmen is going."
"You like her that much that you'll throw away your life?"
"What life? This isn't life. My life is school. I don't care about school."
"You should care."
"Why? Do I really need to know algebra or chemistry? When will I ever use that?"
"Well, look at Mr. Miller. He uses chemistry."
"Whatever. I don't want to be an inventor. I don't want to be anything. All I know is if Carmen will go, I will go." After a pause, he added, "So why don't you want to go?"
"Because my life is here in the real world; I have plans for my life. I want to be an actress!"
"You know . . . it would be tough staying here without our parents. We would be orphans, or would have to live with Aunt Alexia!"
Kara gasped, "I hate Aunt Alexia! How could they do this to us? Why is this so important?"
"They're right, you know: if that technology gets out, the world will really fall apart."
Kara joked, "Maybe we should use the time machine to prevent Mr. Miller from creating it!"
Keith laughed. Then they headed to their separate rooms.
Kara kept thinking about it. No matter how hard she worked, she might never become a famous actress. Was it really so important to be famous? Maybe in a way this would bring its own kind of fame. She had so many friends though. How could she leave them all? What kind of life would she have living in a cave? Kara tried to imagine life with the builders: being able to make whatever you wanted and not needing to work. Maybe it would be worth it. Maybe the families that were included would be interesting.
When the day ended, Jared and Michelle talked in their bedroom. They smiled at each other and sat side-by-side on the bed. In some ways, they were like they had been when they were still dating. Both were shy and anxious.
They had talked about having children seriously, but the last discussion had been years ago. They liked how much time they had together. They also liked the freedom of Jared being able to work whenever he needed to and for Michelle to have time for writing. She never had any of her work published. She never even had a strict focus. Some days she would write poems, some days she would write short stories, some days she even made books for children that she would give to the local schools. She liked kids; she had been a teacher for a while.
Neither of them knew if they could even have children. They both knew at best they would only get one doctor, the one chosen for the trip, to help them if they had trouble.
"So," said Michelle.
"So," replied Jared.
"We're going to have kids?"
"If that's what you want, Honey."
"I do. It's scary though. What if we can't?"
"Don't worry; if we can't . . . we have Carmen. Plus, we'll probably get enough other couples."
"I like Carmen. She's an orphan, you know?"
He laughed, "Yes . . . I sort of found out by mistake. I asked her how her parents would feel about her going with us."
"No, you didn't!"
"I did," he nodded. "It's OK though, I don't think I upset her. She's not what I would expect an orphan to be like. I've always pictured them as unstable, but Carmen really has it together. I don't think I could have fixed that bug if it wasn't for her!"
She nodded, "You're right. She is stable, and smart." Even though the rooms were fairly noise proof she whispered, "She's more stable than Keith and Kara!"
Jared laughed.
Michelle said, "I should get to know her."
Jared gave her a sly look, "Are you changing the subject."
She poked him, "You're the one that brought her up."
He grinned, "Oh yeah. What were we talking about again?" he said sarcastically.
She gave him a soft slap on the arm.
He turned and hugged her. Jared brushed her hair back and kissed her passionately. That night they tried their best to conceive their first child. They hoped their bodies would be able to make a child for them to love. They hoped for a child to care for, to teach and to play with. Mostly, they hoped for a child who would love them. With all their hearts they hoped they had not waited too long, that there was still time and their bodies could do what they were created for.
Copyright (C) 1998-2001 East Coast Games, Inc. and 2001 - 2006 Forest J. Handford
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|Stephan Michels <step...@apache.org>
|RE: Reason of HTMLSerializer exception
|Fri, 10 Jan 2003 14:07:55 GMT
On Fri, 10 Jan 2003, Carsten Ziegeler wrote: > > -----Original Message----- > > From: Stephan Michels [mailto:firstname.lastname@example.com] > > > > Strange .. Without these libs in WEB-INF/lib/ I don't get this > > exception, and with I got this exception. Hmm. > > > > Do you use tomcat? And when yes, which version? > > > I'm using tomcat 3.3.1 - remember, if you're using tomcat 4.x > you have to copy the cocoon/lib/endorsed jars to tomcat's > common/endorsed directory as Giacomo asked. Okay okay, to repeat (I'm a bit slow today): lib/core -> cocoon/WEB-INF/lib lib/optional -> cocoon/WEB-INF/lib lib/endorsed -> tomcat/common/endorsed Right? Why are the following instruction in build.xml? <copy todir="${build.war}/WEB-INF/lib"> <fileset dir="${lib.dir}/endorsed"> <include name="*.jar"/> <exclude name="servlet*.jar"/> </fileset> To complete my confusion, I'm currently working with java 1.4, which, if I don't make mistakes, have the XML stuff included. So I don't need xml-apis.jar etc. So why to the *grmpf*# get I an exception, when I have the xml apis in WEB-INF. Not my day, really. --------------------------------------------------------------------- To unsubscribe, e-mail: email@example.com For additional commands, email: firstname.lastname@example.com
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> Garden Furniture
> Garden Furniture Sets
This Idle Rose Gypsy 8 Seat Round Set With Taupe Cushions is perfect for all the family to enjoy a spot of alfresco dining on a warm summers evening.more
Idle Rose Gypsy 8 Seat Round Set Features:
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Prices, promotions, styles, and availability may vary. Our local stores do not honor online pricing. Prices and availability of products and services are subject to change without notice. Errors will be corrected where discovered, and Lowe's reserves the right to revoke any stated offer and to correct any errors, inaccuracies or omissions including after an order has been submitted.
Decor Wonderland 23.6-in W x 31.5-in H Rectangular Frameless Bathroom Mirror with Hardware and Polished Edges
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What the cluck! ENORMOUS chicken emerging from a coop leaves viewers baffled (and a little scared!)
By bolodosqui on Mar 20, 2017 | In Gallinas | No Comments »
A freakishly large chicken is taking the internet by storm, leaving viewers scared – and more than a little confused.
The video, first posted on March 17, features a massive chicken struggling to get out of a coop.
With its huge claws and plumes the animal looks more like a dinosaur then a cockerel. Read the rest »


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Women's Voice
Tuesday, May 2 at 1am
All times in Eastern - Change Change | See all stations and times
- Hamilton, New Zealand
- Women , Podcasts
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More informationSix women join voices to celebrate women - our diverse stories, interests, and opinions. Tune into Women's Voice for an uplifting show full of life. Featuring interesting guests, great music and plenty of laughs. Subscribe to the podcasts via iTunes, or listen live every Tuesdays at 5pm, with a repeat on Saturdays at 8am.
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The show doesn't push a specific point of view, but aims to present a wide range of perspectives reflecting the diverse backgrounds of the show hosts and their guests. For this reason, two different presenters will host the show each week.


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The body of Fabrioe Boigeol, 37, was found lying partially under a stripped mattress in a room at the Morgot Resort in Chalong at about 1:45pm.
"Police and forensic investigators are checking CCTV in and around the resort for possible suspects," Phuket Provincial Police Deputy Commander Peerayuth Karajedee told the Phuket Gazette Saturday.
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"Please give us some time, we will have more information soon."
Mr Boigeol checked into the resort on March 6, and had planned to check out on April 21.
The French Embassy has been informed of the death.


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Warranty Information
The manufacturing date can be found in the upper left hand side of the back of the seat.
For any recall information, call the U.S. government's Auto Safety Hotline at:
1-888-327-4236 (TTY: 1-800-424-9153) or go to: http://www.nhtsa.gov
KidsEmbrace™ warrants its products to the original retail purchaser as follows:
LIMITED ONE-YEAR WARRANTYThis product is warranted against defective materials or workmanship for one year from the date of original purchase. Proof of purchase is required. The exclusive remedy for this warranty is that KIDSEmbrace™ will, at its option, provide repair or replacement components for this product or refund the original purchase price of the product. KIDSEmbrace™ reserves the right to discontinue or change fabrics, parts, models or products, or to make substitutions. To make a claim under this warranty, contact KIDSEmbrace™ Customer Service at 1-866-947-3287. Proof of purchase is required. PLEASE COMPLETE ONLINE REGISTRATION OR MAIL THE OWNER REGISTRATION CARD WITHIN (30) DAYS OF PURCHASE.
WARRANTY LIMITATIONSThis warranty does not include damages, which arise from negligence, misuse or use not in accordance with the product instruction. The use of non-KIDSEmbrace™ covers, inserts, toys, accessories, or tightening devices is not approved by KIDSEmbrace™. Their use could take this restraint out of compliance with Federal Safety Regulations or negatively affect the performance in a crash. Their use automatically voids the KIDSEmbrace™ warranty.
LIMITATION OF DAMAGESThe warranty and remedies as set forth above are exclusive and in lieu of all others, oral or written, express or implied. In no event will KIDSEmbrace™ or the retailer selling this product, be liable for any damages, including incidental or consequential damages, arising out of the use or inability to use this product.
LIMITATIONS OF WARRANTIES AND OTHER WARRANTY TERMS AND STATE LAWSAny implied warranties, including implied warranties of merchantability and fitness for a particular purpose, shall be limited to the duration and terms of the express written warranty. Some states do not allow limitations on how long an implied warranty lasts or the exclusion or limitation of incidental or consequential damages, so the above limitations may not apply. This warranty gives you specific legal rights, and you may have other rights, which vary from state to state. Neither KIDSEmbrace™, nor the retailer selling this product, authorizes any person to create for it any other warranty, obligation, or liability in connection with this product.
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text:
CAD Catalog for Parts, User configurable.
This project received 7 bids from talented freelancers with an average bid price of $6141 USD.Get free quotes for a project like this
Project Budget$1000 - $7500 USD
Total Bids7
Project Description
My company currently has a system in place that will generate a CAD model that is then available for download for just about every CAD format for our product. The configurator will generate models to specs entered by the customer that can be viewed in 2D and 3D on our site. The CAD model is then available to view and for download. We would want this project to interface with our database of users, products, and prices for future ecommerce compatibility as well as giving us the ease to change these options in the background.
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For reference we are looking for a system like this:
[url removed, login to view]
I can provide more detail in the future. We are currently looking for qualified web programmers with experience in this type of development. We hope to start development within the next 4 months once we have finalized all of our requirements for the parts. Timeline is negotiable.
Any working examples with references will contacted first.
Skills Required
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|Application number
|Publication date
|Mar 20, 2001
|Filing date
|Jun 19, 1998
|Priority date
|Jun 19, 1998
|Fee status
|Publication number
|Robert Grieb, David M. McWherter, Jr.
|Original Assignee
|Franklin Electronic Publishers Incorporated
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (8), Referenced by (14), Classifications (16), Legal Events (14)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates to an electronic computer processor. In particular, this invention relates to a processor having enhanced instruction set features.
In most processors, the number of available opcodes is limited by the length of the binary word which can be fetched into the instruction register. For instruction registers with a word length of N bits, 2N different opcodes can be read by the processor. Thus an 8 bit opcode set is limited to 256 opcodes. Encoding register designations within the opcodes, requires multiple opcodes for each register operation, leaving fewer opcodes available to encode other operations.
It is a goal of processor design to minimize the amount of time spent fetching data for operations, while keeping a maximum number of opcodes available for instructions.
One known technique is to increase the number of available opcodes by reading two consecutive words from the bus and joining them to form a single opcode. This technique effectively squares the number of available opcodes. But the reading of two words for every opcode slows the operation of the processor.
An alternative technique, disclosed in U.S. Pat. No. 4,346,437 of Blahut et al. and employed in the RCA-CDP1804AC processor, encodes some instructions with a one-word opcode and other instructions with a two-word opcode. Still, processor time is lost reading two opcode words for some of the instructions.
To avoid the proliferation of opcodes for register operations, the RCA-CDP1804AC microprocessor employs a single opcode independent of the register operated on for certain input/output (I/O) and arithmetic logic unit (ALU) instructions. The particular register on which an operation is performed is determined by a 4-bit "X" designator stored in the microprocessor. The value of the X designator is set by the instruction "SET X", which copies the contents of the N register to the X designator. Thus, the X designator enables a single opcode to encode an operation on any register designated by X; however, each time it is necessary to change the value of the X designator, a SET X instruction must be executed, which results in a loss of processor time.
Because operations are frequently performed on data registers, it is desirable for certain instructions to employ a single opcode for every possible combination of instruction and register. This is performed in the RCA-CDP1804AC microprocessor with the use of an "N" register. For each 8-bit opcode fetched by the CDPI804AC, the lower-order 4 bits of the instruction are loaded into the N register, and the value in the N register is used to designate the register operated on by the instruction.
There are processors with differing instruction sets and varying levels of performance. Programs are generally written for a particular processor and often cannot be run on any other processor. However, the development of most application programs requires a large investment of time and money. It is desirable to minimize those development costs should one wish to run a program on an alternative processor different from the one for which the program was designed. These costs of developing new programs can be reduced if the alternative processor is capable of interpreting and executing programs written for the original processor.
In particular, as a result of the popularity and endurance of the 6502 and related processors, a great number of programs have been written employing the 6502 instruction set. With the advance of technology, more sophisticated processors have been developed. It is beneficial, however, to maintain the ability to execute the vast library of programs written for the 6502 processor on a more advanced processor.
A "source" program which has been written for one processor may be executed on an alternative "host" processor with the use of a dispatch loop. A dispatch loop first fetches an opcode of the source program. From a table stored in memory, the dispatch loop then determines the address of a simulation routine consisting of host processor instructions which simulate the actions called for by the source instruction. The host processor jumps to the address of the simulation routine, executes the routine, and returns to the dispatch loop to fetch the next instruction. This technique, while offering accurate and flexible emulation, is particularly slow, in part due to the "overhead" of instructions which must be executed in order to operate the dispatch loop but which do not themselves simulate the source program.
It is known how to overcome the speed problems of the dispatch loop with the use of additional computer hardware componentry, as disclosed in U.S. Pat. Nos. 5,361,389 and 5,408,622, both of Jonathan Fitch. This solution, while improving the speed of emulation, results in a significant increase in hardware complexity, thus contravening the design of a compact computer system at a low cost.
Prior Art Processor—(FIG. 1)
As shown in FIG. 1, in a known computer design, a bus control 12 controls the flow of data, instructions, and addresses between processor 10 and a bus 14. Bus 14 enables communication between components of a computer, including processor 10, read-only memory (ROM) 16, random-access memory (RAM) 18, and input and output devices 20. Routines which direct the operation of processor 10 are stored as series of opcodes in ROM 16 and/or RAM 18. To execute these routines, processor 10 fetches an opcode by sending a memory address over bus 14 to specify a memory location in either ROM 16 or RAM 18. The opcode word at the addressed memory location is then sent over bus 14 to processor 10. An opcode is typically 8 bits, in which case the number of opcodes is limited to 256.
Opcodes fetched from bus 14 are interpreted by an instruction decode unit 22, which determines the operation or operations specified by the opcode. An arithmetic logic unit 24 then carries out the instructions on data contained in registers 26. A set of special purpose registers 28 is also provided, including an instruction pointer IP and a stack pointer SP. Instruction pointer IP supplies the address of the next opcode to be fetched from memory 16, 18 and is incremented (to point to the next opcode) each time an opcode is fetched. Flags 30, including sign flag S, overflow flag V, zero flag Z, and carry flag C are tested in conditional operations.
It is an object of the invention to provide a processor capable of executing a number of instructions greater than the number of the opcode set.
It is another object of the invention to provide a processor capable of executing a program coded for a different processor. In particular, it is an object of the invention to provide such a processor which operates without the need for a dispatch loop or for additional emulation hardware.
It is a related object of this invention to provide the above objects in a mode that optimizes use of memory capacity and does so at a speed of operation acceptable to the user.
In brief, a first feature of this invention increases the number of instructions available from the set of opcodes available. For example, an eight bit opcode size provides 256 opcodes. This invention uses those 256 opcodes to provide more than 256 instructions. Where it is known that a particular pair of instructions (paired instructions) will always appear in sequence, then the second of the two opcodes is used to provide two instructions or functions. When this dual function opcode is fetched, it normally performs a first function. However, if it is to perform its second function, the program calls for first setting a resolving flag to a set state. This setting operation is one of the responses to the execution of the immediately prior one of the paired instructions. As long as the function of the immediately prior opcode never precedes the first function of the dual function opcode, this setting of the resolving flag can be built into the processor.
With the resolving flag in its set state, the fetching of the dual function opcode results in executing the second operation of the dual function opcode. The setting flag is then immediately cleared so that if the next opcode fetched is a dual function opcode, it will execute its first operation. In this fashion, the number of functions or operations performed by a predetermined number of opcodes can be greater than the predetermined number of opcodes.
A second feature of this invention also provides for an increase in opcode functionality; that is, providing more opcode instructions than there are opcodes. The feature is associated with the pushing or popping of data between a stack and a set of registers. The push opcode and the pop opcode are each provided as a generic opcode; that is without any designation of the register from which or to which data is to be copied.
When the generic push opcode is fetched, the processor immediately decrements the stack pointer and copies the data from whatever register is currently pointed to by the register pointer into the stack and then increments the register pointer. Repeated fetching of the push opcode will repeat the sequence as often as required to copy the set of data from a sequence of registers into the stack.
Similarly with respect to the pop opcode, a single generic pop opcode is encoded. When it is fetched, it causes data from the stack to be copied to the register currently designated by the register pointer. The processor then immediately increments both the stack pointer and decrements the register pointer. Thus a series of steps fetching the generic pop opcode will result in copying a series of separate items of data from the stack to a sequence of registers.
In both cases, the register pointer is initialized prior to the first fetch of a sequence of generic push opcodes or a sequence of generic pop opcodes.
A further aspect of this invention which provides for efficient versatility is one that permits a program designed for a particular instruction set to be executed in a host processor designed for a different instruction set. For example, a program for a first instruction set might exist on a card that can be read by a host processor designed to operate with a different instruction set.
The host processor has in memory a set of opcodes which perform the operations, in the host processor, that would be called for by the opcodes in the target program on the card. These host opcodes are in an allocated set of separate addresses. When the target program from the card is to be read into the host processor, a first step is to detect the card and set a simulation flag. When the simulation flag is set, adjustments that may be required are made such as sizing the registers and establishing the flags needed for the simulation mode. Most importantly, a predetermined algorithm is enabled. The pointer for the card opcodes is initialized. A particular simulator opcode (called a jump vector JMPV opcode herein) is generated by the host processor to fetch opcodes from the card (target opcodes), to increment the pointer for the card opcodes, and to apply the algorithm to the target opcode to create a memory address in the host processor.
This algorithm generated host memory address is the first of a subset of host memory addresses that constitutes a handler that performs the target opcode function. Thus a sequence of host processor memory locations may have to be addressed for each target opcode. The simulator opcodes are fetched from the host memory addresses and executed to perform the operation that would have been performed by the corresponding target opcode on the card if the latter were executed in a processor having the instruction set appropriate for the card opcodes.
The JMPV opcode is fetched from the last one of the set of host memory addresses associated with a single target opcode. The JMPV opcode repeats the operation of fetching the next target opcode from the card, incrementing the register pointer for the target program, applying the addressing algorithm and fetching handler opcodes. This JMPV opcode function replaces and thus eliminates the prior art dispatch loop.
FIG. 1 is a block diagram of a computer including a processor according to the prior art.
FIG. 2 is a block diagram of a computer including a processor in accordance with the present invention.
FIG. 3 is a table illustrating opcodes, instructions, and processor operations according to the present invention.
FIG. 4 is a schematic block diagram illustrating the operation of a processor in emulation mode in accordance with the present invention.
FIG. 5 is a simplified flow chart illustrating a technique whereby a single opcode is used to selectively perform two operations, which operations need not be related to one another.
FIG. 6 is a simplified flow chart illustrating a technique whereby a single generic push opcode and a single generic pop opcode can be used to perform the operation of transferring a set of data between a stack and set of registers.
FIG. 7 is a simplified flow chart illustrating a technique for executing a target program designed for a first instruction set on a host processor designed for a second instruction set different from the first instruction set.
As shown in FIG. 2, a bus control 112 controls the flow of data, instructions, and addresses between processor 110 and a bus 14. Bus 14 provides communication between processor 110 and components of a computer as in the prior art (FIG. 1). The stack is incorporated in the RAM 18. Opcodes fetched by processor 110 through bus 14 are interpreted by instruction decode unit 122, which determines the operation or operations specified by the opcode. Arithmetic logic unit 124 then carries out the instructions on data contained in registers 126. Special purpose registers 128 are also provided. An instruction pointer IP, a stack pointer SP and a temporary register T are provided. The set of flags 130 includes sign flag S, overflow flag V, zero flag Z, and carry flag C for use in conditional operations. Additional flags K and BS are provided, and four further flag bits are designated as RP. Flag functions are described below.
Opcodes for operations to be performed on one of the general purpose registers 126 may or may not be encoded with a designation of the specific register on which an operation is to be performed. In processor 110, when the register designation is not encoded in the opcode, the register is designated with the use of the BS and RP flags. As illustrated in FIG. 2, the thirty-two general purpose registers 126 of processor 110 are separated into two sixteen-register banks, "Bank 0" and "Bank 1". Operations performed on registers 126 can be performed only on one or the other of the register banks. The bank that can be operated on is designated by the value of the one-bit bank select flag BS, so that when BS contains "0", a register from Bank 0 is operated on, and when BS contains "1", a register from Bank 1 is operated on. The specific register is then selected from among the sixteen registers in the designated bank by the four-bit register pointer RP. Thus, when BS contains "0" and RP contains hexadecimal "C," register R12 of Bank 0 is selected.
Certain operations performed by ALU 124 are illustrated in FIG. 3 with the use of an arrow notation. ALU 124 evaluates the expression to the right of the arrow and places the results in the location specified to the left of the arrow. When a result is placed in more than one location, all of the locations are listed to the left of the arrow and separated by commas. Multiple steps in an operation are separated by semicolons, with the leftmost steps being performed first. The expression "M(x)" is used to designate a memory location with address x, accessed from RAM or ROM by processor 110 through bus 14. For example, M(T) signifies the memory location whose address is designated by the contents of register T. The expression "R(RP)" signifies the general purpose register designated by the contents of RP. Whenever a register is designated, e.g., by "R5" or "R(RP)," it is understood that the operation is performed on the register bank specified in flag BS.
An exemplary partial set of opcodes executed by processor 110 is illustrated in FIG. 3. Each opcode is illustrated (in hexadecimal notation) with a unique instruction and an operation performed by processor 110. When an assembly program is assembled into an executable program, a line of assembly code (second column of FIG. 3) is encoded by an opcode (first column of FIG. 3). When processor 110 executes the executable program, the opcode is fetched over bus 14 by bus control 112 and decoded by instruction decode unit 122, which determines the operation (third column of FIG. 3) to be performed by arithmetic logic unit 124.
To simplify the description, opcodes are at times described herein as performing an operation, such as adding or moving. It is the processor which performs such operations. The fetching of a particular opcode directs the processor to perform the operations.
Most programs spend most of their time moving data. Thus, a variety of opcodes encoding different MOV instructions has been provided for specific applications. In some cases, it is preferable to encode a specific register number in the opcode of the selected MOV instruction. In other cases, it is preferable to use register pointer RP to designate a particular register. In the case of processor 110, register numbers are specifically encoded in the opcode for MOV instructions which operate on registers R0 through R6. MOV instructions performed on any registers, including R0 through R6 as well as R7 through R15, can be performed by designating the register with register pointer RP.
Processor 110 thus avoids the monopolization of available opcodes that would take place if a register number were encoded in each opcode. A single opcode in processor 110 can be used to encode operations on a variety of registers. Register pointer RP may be set with an opcode 0�7C "RPTR 12", which sets register pointer RP to point to register R12. Each RPTR instruction is provided with a unique opcode. Thus, opcode 0�7C sets RP to 12, 0�7D sets RP to 13, and so on. In executing opcode 0�A7, which encodes the instruction "MOV24 (T),RP", processor 110 moves twenty-four bits of data stored at the memory location addressed by register T (and fetched over bus 14 from RAM or ROM) into whichever register is pointed to by RP. Opcode 0�20 "ADD RP" adds the contents of register T to whichever register is pointed to by RP. Opcode 0�21 "INC RP" increments the contents of whichever register is pointed to by RP. These three exemplary opcodes alone substitute for forty-eight different opcodes that would have been required if the register number for each of registers R0-R15 were encoded in the opcode.
The parsimony of opcodes is not bought, however, at the price of slowing down execution by continually resetting register pointer RP with different values. Processor 110 automatically resets RP upon execution of several of the opcodes. In particular, processor 110 automatically sets RP to point to a register into which data is moved. For example, opcode 0�43 "MOV T,R3" in addition to performing the standard operation of moving the contents of register T into register R3, sets RP to point to register R3.
Opcode 0�68, which encodes the JSR subroutine jump instruction, performs the conventional operations of resetting program counter PC to a target address from register T and writing a return address to the stack pointed to by stack pointer SP. The return address is preferably the address of the opcode which follows the delay slot of the 0�68 JSR opcode. In addition to the conventional operations, opcode 0�68 automatically sets register pointer RP to point to register R8. This enables the subroutine called by JSR opcode 0�68 to preserve the registers, beginning with R8, that the subroutine intends to use during processing but must be restored prior to returning to the calling routine. Since RP is already set to R8, the entry code, or preamble, of the subroutine need only execute one generic push opcode for each such register the subroutine will use during processing. Prior to exiting, the subroutine restores the preserved registers and returns using an RTS to the calling routine. In addition, RTS opcode 0�39 automatically resets RP to point to register R0 so that the calling routine can quickly retrieve any returned values from the called routine.
The Generic Push and Pop Opcodes
PUSH and POP instructions are stack instructions which are commonly used to move data between the registers and the stack. Opcode 0�BC, for example, encodes the instruction "PUSH R4", which pushes the contents of register R4 onto the stack. Similarly, opcode 0�B8 pushes R0, 0�B9 pushes R1, and so on. Rather than encoding a register number in each of the opcodes, the register number is encoded in PUSH instructions only for registers R0 through R6 (opcodes 0�B8 through 0�BE). A single opcode 0�BF "PUSH RP" is available as a generic opcode to push whichever register is pointed to by RP. In addition to performing the push operation, opcode 0�BF decrements the stack pointer prior to the push operation and increments the register pointer after the push operation. The three lowest bits of the (four-bit) register pointer are incremented by one.
A POP instruction is used to move data from the stack to a register. As with the PUSH instruction, opcodes are provided which encode the POP instructions for R0 through R6 (opcodes 0�B0 to 0�B6, respectively). Opcode 0�B7 is used as a generic opcode to pop data from the stack to whichever register is pointed to by RP. In addition to performing the pop operation, opcode 0�B7 decrements the register pointer and increments the stack pointer. The three lowest bits of the register pointer are decremented by one.
The automatic incrementing of the register pointer with PUSH instructions and the automatic decrementing of the register pointer with POP instructions enables the rapid transfer of a series of data between the registers and the stack. For example, to push registers R8 through R13 onto the stack, the following sequence of instructions can be used:
RPTR 8; set the register pointer to 8
PUSH RP; push R8 onto the stack, set RP to 9
PUSH RP; push R9 onto the stack, set RP to 10
PUSH RP; push R10 onto the stack, set RP to 11
PUSH RP; push R11 onto the stack, set RP to 12
PUSH RP; push R12 onto the stack, set RP to 13
PUSH RP; push R13 onto the stack, set RP to 14
Because the register pointer is set automatically with each PUSH instruction, it is not necessary to reset the pointer with a separate RPTR instruction before each PUSH instruction, which would nearly double the number of instructions, nor is it necessary to employ a separate opcode encoding a push instruction for each of registers R8-R13, which would monopolize opcode values. Copying the stack data back into the respective registers is just as straightforward:
RPTR 13; set the register pointer to 13
POP RP; pop data from the stack to R13, set RP to 12
POP RP; a pop data from the stack to R12, set RP to 11
POP RP; pop data from the stack to R11, set RP to 10
POP RP; pop data from the stack to R10, set RP to 9
POP RP; pop data from the stack to R9, set RP to 8
POP RP; pop data from the stack to R8, set RP to 15
Background For Context-Sensitive Decode
In processor 110, jump instructions (such as 0�38 and 0�68, FIG. 3) and branch instructions (such as 0�B0) set the program counter PC to the value stored in the register T, thus causing program execution to continue with the opcode stored at the memory location designated by the T register. The T register is thus employed as a target-address register for jump and branch instructions. In order to set the target register for a jump or branch, the T register is loaded with data representing the target address using a LDT, or "load-T" instruction. LDT is represented by any one of the opcodes 0�C0 through 0�FF, or in binary, 11000000 through 111111111. The two high bits "11" designate the opcode as a LDT opcode, and the six low bits convey a six-bit data word which is loaded into register T.
The K Flag
Processor 110 employs a flag K, which stores a flag value of either "set" or "cleared". The value stored in the K flag is changed by the opcodes fetched by processor 110. Preferably, the K flag is set and cleared by instruction decode unit 122. One group of "setting" opcodes is associated with the "set" value, while another group of "clearing" opcodes is associated with the "cleared" value. Each time processor 110 fetches a setting opcode, the K flag is set, and each time processor 110 fetches a clearing opcode, the K flag is cleared. Some opcodes may neither set nor clear the K flag, leaving the value thereof unchanged.
Dual Function Opcodes
Some opcodes used by processor 110 are associated with more than one operation. Processor 110, upon fetching a dual function opcode, determines which of these operations it is to perform by checking the value of the K flag. One of the possible operations is associated with the "set" state of the K flag, and another of the possible operations is associated with the "cleared" state of the K flag. Upon fetching of a dual function opcode, the instruction decode unit 122 selects the operation associated with the present state of the K flag. The K flag thus serves as a resolving flag by selecting which operation is to be performed by an overloaded opcode. In this technique of "context-sensitive decoding," the instruction set of processor 110 is expanded beyond the number of available opcodes by assigning more than one processor operation to several of the opcodes.
The group of opcodes which set the K flag is preferably the group of opcodes encoding LDT (load-T) operations, while the group of opcodes which clear the K flag comprises nearly all other opcodes. Thus, the K flag is set each time an LDT opcode is executed and cleared each time any opcode other than an LDT opcode is executed.
As discussed above, the T register stores the target address for branch instructions. Thus, it is in general desirable for a LDT instruction, which sets the value of T, to immediately precede a branch instruction, which makes use of the value of T. This common pairing of an LDT instruction with a branch instruction allows branch instructions to be associated with the dual function opcodes. That is, each opcode which encodes a branch instruction also encodes an alternative instruction. The operation which is performed when such an opcode is fetched is determined by the value of the K flag. If the preceding opcode was a LDT opcode, the K flag has the "set" value and a branch operation is performed; if the preceding opcode was not a LDT opcode, the K flag has the "cleared" value and the alternative operation is performed.
For example, as seen in FIG. 3, the dual function opcode 0�B0 encodes the branch instruction "BRA" as well as the stack instruction "POP R0". When the 0�B0 opcode is fetched, processor 110 tests the value of the K flag. If K is set, "BRA" is executed, and if K is cleared, "POP R0" is executed. Preferably, each of the branch instructions shares an opcode with a stack instruction.
Some amount of care must be used when writing programs to be executed on processor 110. For example, an unsuspecting programmer may write a sequence of instructions in assembly such as the following:
To a person reading this code, it is evident that the programmer wants to load the value "31" into the T register, to copy that "31" to the R4 register, and then to branch to an offset address of "31". A simple compiler program, however, converting these instructions into machine language for execution on a computer system, would replace each of the instructions with its associated opcode, resulting in a series of opcodes such as the following:
Processor 110, executing the opcodes, would fetch "0�FF" and perform the "LDT 31" operation as intended. Being a LDT instruction, 0�FF also sets the K flag. The 0�44 opcode is fetched, and "31" is copied to register R4 as intended, but the K flag is cleared since 0�44 is not a load-T instruction. When processor 110 fetches dual function opcode 0�B0, it tests the value of the K flag, finds that it is cleared, and performs a stack operation, rather than the intended branch operation. Thus, instead of performing the operations written by the unwary programmer, processor 110 performs the operations corresponding to a different piece of code:
Although care must be taken to ensure that each branch instruction is immediately preceded by a load-T instruction, this restriction on program structure has been found to be minimal in comparison to the advantages of increasing the number of available processor operations using a given number of opcodes. Of course, a compiler program which compiles code for execution on processor 110 may include functionality to warn a programmer of code that can be misinterpreted, or even automatically to rearrange the code to perform the functions desired by the programmer.
It should again be noted that a few opcodes may themselves neither set nor clear the K flag. In particular, opcodes which explicitly set or clear the flags in the flag register ST do not necessarily change the K flag, although the K flag, being one of the bits of ST, may be set or cleared by such opcodes if a programmer so desires. Such opcodes encode instructions such as "MOV T, ST", "SETF T" (which uses T to set bits in ST), and "CLRF T" (which uses T to clear bits in ST). The opcode corresponding to the RTI "return from interrupt" instruction restores the K flag to its value before the interrupt.
Effect Of K Flag On LDT
The T register is generally 24 bits in length, and thus may accept up to four six-bit words loaded through LDT. All of the LDT opcodes 0�C0 through 0�FF are setting opcodes. When processor 110 executes an LDT opcode, it is first determined whether the K flag is set, i.e., whether the previous opcode was an LDT opcode. If flag K is not in a set state, indicating that the previous opcode was not an LDT opcode, the six-bit data word is simply copied into register T, and register T is sign extended. On the other hand, if flag K is in a set state, indicating that the previous instruction was an LDT opcode, the contents of register T are shifted by six bits to make room for the six-bit data word before the data word is copied to the low six bits of register T.
The JMPV Vector Opcode and Simulation—(FIG. 4)
One embodiment of this invention has been used to execute in a host processor a target 6502 program that is contained on a card. Each opcode on the card is a target opcode. The host processor 410 has in memory 412 a set of opcodes 414 which when appropriately fetched will perform the functions that would be commanded by the set of target opcodes 416 in the program 418 on the card coupled to the host processor. This handler memory 412 contains not only the set of handler opcodes 414 but also an opcode that is called herein a jump vector (JMPV) opcode 420. This jump vector opcode 420 is the simulation opcode that is at the heart of this simulation arrangement.
When the card containing the 6502 program is coupled to the host processor 410, a simulation flag 140 (see FIG. 2) is set. This simulation flag 140 may make certain adjustments that are a function of the relationship between the host processor 410 design and the design appropriate to the 6502 program. These adjustments could include the sizing of registers and establishing the flags needed for the simulation mode.
The coupling of the card to the host processor also results in fetching the jump vector (JMPV) opcode 420. The processor 410 is designed so that the fetching of this JMPV opcode 420 results in the following three steps:
1. The target opcode designated by the program pointer PP is copied into temporary processor associated memory 422.
2. The emulation pointer PP is incremented by one, and
3. A predetermined algorithm in the processor is applied to the value of the particular target opcode that has been placed in temporary memory to provide an appropriate address.
In one embodiment, this algorithm involves a shift of the binary opcode by a predetermined number of digits and the addition of an offset. The result is an instruction pointer IP for the handler memory 412 to access to the first of the handler memory opcodes that perform the function of the target opcode. The particular handler memory opcode is normally only the first of a subset of host handler memory opcodes that are accessed to perform the target opcode function. This is because the simulation function often requires two or more opcodes for execution by the host processor. The required handler opcodes are fetched from memory 412 and executed to perform the operation that would have been performed by the corresponding target opcode if the target opcode was executed on a processor designed for the 6502 processing function.
For example, the instruction pointer IP may increment from opcode OPCD1 through OPCD3 to provide the function of the target opcode INSN3. The IP continues to fetch handler memory opcodes until a JMPV opcode is fetched from handler memory. Thus, the last of the subset of handler memory opcodes in the subset accessed and fetched for the particular target opcode is the JMPV opcode. The JMPV opcode then causes the processor to repeat the function described above in which the now incremented program pointer PP fetches the next opcode from the 6502 program on the card and causes the sequence of functions set forth above to be repeated to provide the next IP address for the next subset of handler memory opcodes.
In summary terms, FIGS. 5, 6 and 7 are flow charts or sequence charts that summarize the main features described in detail above.
FIG. 5 relates to the employment of a dual function opcode in order to extend a number of opcode functions for a fixed number of opcode designations. As indicated at function 600, an opcode is fetched and then as shown at 602, a determination is made as to whether or not the opcode is a setting opcode. If it is not, then as shown at function 604, the opcode is executed and the resolving flag is cleared. As shown at 605, the next opcode can be fetched and a determination is then made at 606 as to whether or not that next opcode is a dual function opcode. If it is not a dual function opcode, then as shown at 608 it is executed. If it is a dual function opcode, then as shown at 610, the first of the two functions are executed because the resolving flag has been cleared. However, if at function 602, the fetched opcode is a setting opcode then as shown at 612 that setting opcode is executed and, because it is a setting opcode, the resolving flag is forced into its set state. As shown at 614, the next opcode fetched is a dual function opcode. It is a dual function opcode because of the program requirement which is that a setting opcode is always followed by a dual function opcode. As shown at 616, because this is a dual function opcode and the setting flag is at said set state, the second function of the dual function opcode is executed and the resolving flag is cleared.
FIG. 6 illustrates the sequence of functions in connection with the push and pop arrangement that also serves to increase the number of opcode functions that can be performed with a limited set of opcodes. As illustrated in FIG. 6, at step 700, an opcode is fetched. As shown at 702, a determination has to be made as to whether this is a generic push opcode or a generic pop opcode. If it is a push opcode, then the stack pointer is decremented 704 and the data from the register that is currently pointed to by the register pointer is copied into the stack as shown at 706. The register pointer then is increased by one as shown at 708 so that the next push opcode can go through the same series of steps. This can be done without the push opcode carrying any register designation. Accordingly, one generic push opcode can perform a series of push functions.
Similarly if the opcode fetched at 700 is determined at 702 to be a generic pop opcode, then at 710 data is copied from the stack to the register; that register being the one currently pointed to by the register pointer. After the data has been copied, as shown at 712, the stack pointer is automatically incremented by one and the register pointer is automatically decremented by one. This places the stack and register pointers in appropriate positions so that if the next opcode fetched is a generic pop opcode the copying procedure can continue using the generic pop opcode until a series of data transfers from stack to register has been completed.
FIG. 7 illustrates the simulation sequence. As shown therein when a card has been inserted into a processor 800, the card header has to be read at 802 to determine at 804 if this card has a predetermined program appropriate for this simulation technique. If it does, then as shown at 806, the simulation flag has to be set in the status register. As shown at 808, a series of adjustments are automatically made including appropriate sizing of registers that are required for the enabling of the algorithm that is involved and establishing of simulated card code flags. As shown at 810, the pointer for the card opcode is initialized and then at 812, the jump vector (JMPV) opcode is fetched. This jump vector opcode is the key simulator opcode. It is executed to perform the functions of fetching a target opcode from the card at 814; incrementing the pointer for the card opcode 816 and applying the algorithm enabled at step 808 to the opcode fetched from the card so as to establish the memory address for the handler opcode at step 818. Then at step 820, the handler opcode is fetched from the memory address established at step 818 and is executed at step 822 to perform all or part of the function of the opcode that was fetched from the card at step 814.
It has to be kept in mind that a plurality of handler opcodes will normally have to be fetched from the memory address to perform the target opcode functions. They are fetched from a plurality of normally sequential memory addresses which are automatically addressed until the two or three or more that have to be fetched are all executed in order to perform the complete function of the target opcode on the card. The last of the opcodes fetched from the group of memory addresses is another jump vector opcode so that the procedure starting with fetching the next opcode from the card (step 814) can occur until the card program has been executed.
Although the invention has been described in terms of particular embodiments and applications, one of ordinary skill in the art, in light of this teaching, can generate additional embodiments and modifications without departing from the spirit of or exceeding the scope of the claimed invention. Accordingly, it is to be understood that the drawings and descriptions herein are proffered by way of example to facilitate comprehension of the invention and should not be construed to limit the scope thereof.
|Cited Patent
|Filing date
|Publication date
|Aug 31, 1979
|Aug 24, 1982
|Bell Telephone Laboratories, Incorporated
|Microcomputer using a double opcode instruction
|Sep 27, 1993
|Nov 1, 1994
|Apple Computer, Inc.
|Apparatus and method for emulation routine instruction issue
|Sep 23, 1993
|Apr 18, 1995
|Apple Computer, Inc.
|Apparatus and method for emulation routine control transfer via host jump instruction creation and insertion
|Jun 10, 1996
|Aug 11, 1998
|Lsi Logic Corporation
|Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
|Nov 25, 1996
|Mar 9, 1999
|Intel Corporation
|Method and apparatus for handling invalid opcode faults via execution of an event-signaling micro-operation
|Mar 31, 1997
|Mar 16, 1999
|Intel Corporation
|Method and apparatus for decoding enhancement instructions using alias encodings
|Jun 12, 1997
|Nov 9, 1999
|Advanced Micro Devices, Inc.
|Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
|Jul 17, 1997
|Jun 13, 2000
|Advanced Micro Devices, Inc.
|Instruction redefinition using model specific registers
|Citing Patent
|Filing date
|Publication date
|May 23, 2002
|Jan 30, 2007
|Adams Phillip M
|CPU life-extension apparatus and method
|Jul 25, 2005
|Sep 8, 2009
|Texas Instruments Incorporated
|Method and system for processing a "WIDE" opcode when it is not used as a prefix for an immediately following opcode
|Jan 12, 2006
|Feb 16, 2010
|Denso Corporation
|Microcomputer and encoding system for instruction code and CPU
|May 29, 2002
|Aug 17, 2010
|Adams Phillip M
|Computer-hardware, life-extension apparatus and method
|Sep 24, 2009
|Aug 2, 2011
|Denso Corporation
|Microcomputer and encoding system for executing peripheral function instructions
|Jul 25, 2005
|Oct 25, 2011
|Texas Instruments Incorporated
|Method and system to emulate an M-bit instruction set
|May 23, 2002
|Nov 27, 2003
|Adams Phillip M.
|CPU life-extension apparatus and method
|May 29, 2002
|Dec 4, 2003
|Adams Phillip M.
|Computer-hardware, life-extension apparatus and method
|Jul 25, 2005
|Feb 2, 2006
|Texas Instruments Incorporated
|Method and system to emulate an M-bit instruction set
|Jul 25, 2005
|Feb 2, 2006
|Texas Instruments Incorporated
|Method and system to disable the "wide" prefix
|Jan 12, 2006
|Jul 20, 2006
|Denso Corporation
|Microcomputer and encoding system for instruction code and CPU
|Jan 23, 2007
|May 24, 2007
|Adams Phillip M
|CPU life-extension apparatus and method
|Jul 2, 2008
|Jun 11, 2009
|Samsung Electronics Co., Ltd.
|On screen display interface for digital broadcast receiving device
|Sep 24, 2009
|Jan 21, 2010
|Denso Corporation
|Microcomputer and encoding system for instruction code and CPU
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Nov 16, 1998
Owner name: FRANKLIN ELECTRONIC PUBLISHERS, INCORPORATED, NEW
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Just like all of you, us at the Bewdly team are in love with, and obsessed with coffee. Is this such a bad thing? Some people would say yes, coffee is a very very bad drug that we need quit (and yes, we agree those people are crazy)(kidding)(not kidding) but actually, studies over time have shown us that drinking coffee is good for your health. And no, that doesn't mean we condone drinking 10 cups of coffee everyday to stay awake, just like any other substance, coffee should be enjoyed in moderation. And by moderation we mean 1-3 cups per day.
Moving on, let's take a look at how research tells us our good old cup of joe is good for our health. We are going to go through the top 4 reasons why coffee is good for you, me, and every other sleep-deprived being on this planet.
Reason number one. Coffee is loaded with nutrients and antioxidants. Yes, you read that right. NUTRIENTS AND ANTIOXIDANTS people. Coffee isn't just black water that tastes like liquid nirvana. It is in fact all of that and a liquid alarm clock providing us with a significant portion of our daily nutrient intake. Who knew?
Number two. Coffee can help you burn fat and improve physical performance. THANK GOD. I've been meaning to trim down before bikini season starts. But how the hell does Coffee get me that? How you may ask, the secret ingredient that most commercial fat burning supplements use is actually caffeine. Caffeine not only raises you metabolism but also increases the oxidation of fatty acids. What does all this mumbo jumbo mean? It means that caffeine stimulates your metabolism to speed up, allowing your body to burn more calories at rest. Meaning you can be sitting on your couch having a Scandal marathon, while drinking some yummy Chocolate Peanut Butter Cup Coffee, and burning more calories than if you weren't drinking any liquid nirvana at all. Cool right? We thought so too.
Three. Coffee Drinkers have a much lower risk of Type 2 Diabetes. I'm sure this hits home for a lot of us with over 300 million people afflicted by type 2 diabetes. So how can coffee possible help lower your risks of contracting this disease? Interestingly enough coffee drinks have a significantly reduced risk of developing this disease with studies showing that 23-67% of them are less likely of becoming diabetic. In another study of 457,922 individuals, each daily cup of coffee was linked to a 7% reduced risk of type 2 diabetes. Amazing right? We know.
Coffee not only tastes amazing but it reduces the risk of disease? Coffee I freaking love you. Even more than I already did. I had no idea that was even possible.
Moving on.
Four. Coffee makes people HAPPY. Coffee makes me HAPPY. Makes me functional and makes me a nice person in the a.m. Without coffee I would most likely have fewer friends at work (especially those who sit next to me) and many more grey hairs because of my crazy colleagues who I hate. They hate me because I haven't had my liquid nirvana. And I hate them because they can't provide me with liquid nirvana. Do you see how many problems this causes? Coffee saves the workplace. Just saying. All in all, coffee and the workplace go together like Peanut Butter and Jelly. Without it, the world would be a much sadder place.
As good as coffee is for you it's very important to remember that all things are good in moderation. drinking way too much coffee can be very harmful so remember to stick to 1-3 cups per day.
Bewdly Coffee Company is proud to endorse this message unlike some other coffee retailers who just want the consumer to drink as much as possible and continue buying.
To conclude, coffee is my best friend (Don't judge me). Who's yours?
- Diana (Avid and Obsessive Coffee Drinker)


text:
Apply for this job
Market Researcher
What you can expect
The Market Researcher will be responsible to drive research initiatives for the business in order to identify new opportunities, customer attitudes, insights, trends and product entry and opportunities in order to deliver business intelligence to the company.
Analysing market trends and competitor landscapes to ensure successful sales development.
Communicating with customers to understand the potential of the business.
Carrying out market surveys in consultation with market developer.
Analyses data from the surveys and provide recommendations.
Prepare presentations regarding research for the various business units.
Ensure a customer focused business environment, taking our business interests into account.
Ensure adherence to and compliance with all our company guidelines and procedures.
What we expect
Diploma in Business studies/ Engineering, Degree qualification will be an added advantage
At least one year of experience in sales and marketing, experience in market research wil be an added advantage
One year experience in the chemical industry
Fluent in written and spoken English language and
Good communication and interpersonal skills
Computer literacy in MS Office Packages
Must have good analystic skills and must be a proactive team player
We offer Responsibility from day one in a challenging work environment and on-the-job training as part of a committed team. Competitive compensation including attractive benefits as well as excellent career opportunities in an international company.


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England today dropped versatile Austin Healey for Saturday's rugby union international against world champion Australia at Twickenham.
England today dropped versatile Austin Healey for Saturday's rugby union international against world champion Australia at Twickenham.
But the Leicester star could be reinstated after tragic news involving winger Ben Cohen, whose father died a month after being assaulted at his own nightclub.
Coach Clive Woodward has chosen the beefier Dan Luger to the smaller but quicker Healey on the wing against the powerful Wallaby lineup although he said he wanted to see Luger and Cohen on the team at the same time.
"Obviously Austin wants to start but the position he is in is a very competitive one," Woodward said when he announced the lineup on Tuesday.
"It is the first time that both Luger and Cohen have been fit at the same time.
"Luger was outstanding in the first test against South Africa and Cohen was outstanding when he came in to replace the injured Luger in the second test."
Healey, who can also play at scrum half or fly half, will be among the substitutes. But, barely an hour after Woodward named the team came the news of the Cohen tragedy.
England team officials said it would be at least 24 hours before they could announce whether Cohen, who was distressed as he left the team hotel, would be able to face Australia.
The rest of the team, whose last outing was a victory over South Africa five months ago, is a familiar lineup.
Kyran Bracken partners Jonny Wilkinson at halfback, Mike Catt is in the center and the pack has team captain Martin Johnson at second row and one of the best back rows in world rugby, Richard Hill, Neil Back and Lawrence Dallaglio.
The starting lineup:
Matt Perry; Dan Luger, Mike Tindall, Mike Catt, Ben Cohen; Jonny Wilkinson, Kyran Bracken; Jason Leonard, Phil Greening, Phil Vickery, Martin Johnson, Danny Grewcock, Richard Hill, Neil Back, Lawrence Dallaglio.Reuse content


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The Now That's College Beer Pong Rules
Beer Pong can be played a million different ways, and we have been playing the same way since high school and here are our "House" Rules.
- 10 cups each side, normal triangle.
- Winners always stay on table and losers have to leave, unless a series has been agreed upon.
- If it is the first game of the night or no winners are present then the two teams must have one player look each other in the eye from across the table and shoot until someone makes a shot and that team starts off with balls.
- Bounces are allowed and if successful 2 cups must be removed. Blocks are allowed but blocker beware because any cups knocked over count too.
- When someone makes a cup, the cup must removed ASAP. If the other teammate is able to make that same cup then the game is over. (Keeps you on your toes)
- Next game must be called.
- 2 re-racks per team per game.
- Girls blow, and guys finger. (Just like in sex)
- If this occurs game is over. #miraclecup


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Music to Your Ears
By Laura Marrich
Scores of Scores
The New Mexico film industry's proverbial belt gets another notch punched in it this week, but it's not what you'll see that's making the state proud—it's what you'll hear. Albuquerque musician Tom Monahan composed the score for Fat Head, a nationally released docu-comedy starring, written and directed by Tom Naughton. The film is a direct challenge to Morgan Spurlock's 2004 Super Size Me (and, indirectly, an homage to Subway's "Jared" ad campaign). It follows Naughton as he eats nothing but fast food for 28 days and loses weight.
Mike Watt
Ex-Minuteman ponders mortality while practicing an opera
By Dan Hinkel
Punk institution Mike Watt considered a lot of influences in designing his third rock opera: Walt Whitman, The Wizard of Oz, Watt's own past recordings, "jackalopes and shit."
Courtesey of Lionel Loueke
Lionel Loueke Trio
African-inflected guitar and telepathy
By Mel Minter
Blending simple, beautiful African melodies with forward-looking harmonies, a deep groove and an unusually percussive repertoire of vocalizations, guitarist Lionel Loueke has quickly captured the imagination of jazz audiences. He's also won the respect of some of its biggest heavyweights, including Terence Blanchard, Herbie Hancock and Wayne Shorter.
Flyer on the Wall
Gypsy, Be Good
Sleestaks, Dead On Point Five, Bat Wings for Lab Rats (featuring Rob of Holiday Sail) and Dynamite Kegs (from Cruces) rock the Launchpad on Thursday, April 16. The Gypsy Queens, a lady gang of inked Good Samaritans, will make a special appearance to raise awareness for Walk MS, coming up on Saturday, April 18, at Tiguex Park. The show is 21+, cover TBA. (Laura Marrich)
Sonic ReducerYeah Yeah Yeahs It's Blitz! · The Thermals Now We Can See · Death Cab For Cutie "The Open Door EP"
The band that helped bring New York rock back from the dead has decided it wants to make new wave disco jams. It's Blitz! proves the Yeah Yeah Yeahs can take a daring leap and land safely on the other side. The new format still carries the same high energy and adolescent volatility that characterizes the band's previous two releases, but this record trades buzz guitar for synthesizer. Many groups change their stripes, but the result doesn't pan out. Others keep their one trick going until fans eventually grow tired. The successful reinvention is the ultimate trick. It's Blitz! pulls it off with grace. (SM)
Courtesy of the artist
EVENT HORIZON (Friday, Apr 28)
Make Your Own Rock 'n' Roll
Nizhoni Girls • The Flossies • indie, rock • Midnight Stew • Nite Kidz • Lilith • shoegaze • Litter Brain
By August March
The poster for the concert happening at Moonlight Lounge on Friday, April 28, depicts a lonesome hogan placed in the midst of a black and white desolation. Flying out from a chimney on the traditional Diné dwelling is a plume of colorful smoke that names some of the bands that make that large sacred expanse to Burque's west much more than a monochromatic desert. The smoky color of music pervades that realm, and now it's drifting our way. With music by rez rebels Nizhóní Girls, The Flossies, Midnight Stew, Nite Kidz, Lilith and Burque's own DIY punk powerhouse Litter Brain, this is going to be a concert guaranteed to give listeners a solid and soulfully sonic indication of how powerful the voices—and electric guitars and synths and drums—from our Native American neighbors and fellow punk rockers can be. The bands will be performing during this year's Gathering of Nations Pow Wow to raise funds for the upcoming Asdzaa Warrior Fest. Join in on this rocking revelation for only $5 and a valid 21+ ID. Doors are at 8pm; the righteous ritual begins at 9pm.
NEWSLETTERS Great Alibi stories, events and deals delivered to your inbox each week. No fooling!
Today's Events
Raye Zaragoza • folk • Pretty Leaf & the Stardust • Moonchild • Garry Martin Beasley at Tractor Brewing Wells Park
Jorge Ramirez • piano • Stephen Dakin at Uptown Funk Dueling Pianos
Julian Dossett • blues at Blue Grasshopper Brew PubMore Recommended Events ››
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H2OTEL features a large breakfast room in which business meetings or workshops can be held for up to 35 persons. This is only possible after the breakfast, on weekdays from 11.00 AM and on weekends from 12:00. In case you still prefer to organise your meeting or workshop in the early morning, we can arrange spaces which can be used at a 5-meter distance from H2OTEL.
Due to the fact that there are several rooms positioned behind the large breakfast room, it is possible that guests will walk through this room. Of course, we try to avoid this as much as possible. Our H2OTEL space can be used flexibly. There are possibilities to book a lunch or appetizers/snacks together with your reservation. It features tables and chairs, moreover, the available flip-over is at your disposal. There is also a flat screen TV available on which a laptop can be connected.
For (wedding) parties and social gatherings with appetizers and alcoholic/non-alcoholic drinks the breakfast room and the bar/lounge can be used with a capacity of 100 persons. Click here for a price overview.
If you have any other wishes or require further information, don't hesitate to contact us. For reservations, the same contact information can be used.
Maxime Haak - firstname.lastname@example.com or email@example.com (Sales)
Jan Willem Jansen - firstname.lastname@example.com (Manager and Chef-Cook)
Phone number: 0031 (0)10 444 5690


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'Under occupancy penalty could force people from homes' – Brady
Thursday, May 31st, 2012
Sinn Féin MLA Mickey Brady has said that the Social Development Minister Nelson McCausland must make provision for those people who will be penalised by the Under Occupancy Policy.
Speaking to Newry Times, Brady said,
"It is proposed in the Tory welfare reform bill that people living in under occupied houses could lose 15% housing benefit for one room under occupied and 25% for two rooms empty. This could impact on thousands of tenants when you consider there are over 90,000 Housing Executive houses and over 30,000 owned by housing associations the scale of any reduction in housing benefit could force tens of thousands out of their homes."
He continued, "It is important that people are not penalised for living in a house that has been their home for many years. The Minister Nelson McCausland needs to ensure that people are not forced further into the poverty trap by accruing a penalty on the basis of their home."
"I would call on the Minister to make provision for people who find themselves penalised through no fault of their own by implementing measures to offset the penalty," he added.
Would you like to advertise your business on Newry Times and reach thousands of people every day? Contact the Newry Times office on 028 4062 6520 or email Paul: email@example.com


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Carleton Road
North Yorkshire BD23 2BE
Telephone: (01756) 701220
Website: www.carletoncourtskipton.co.uk
Provider Name: Carleton Court Residential Home Ltd
Care home beds: 24
Care Types: Care Home • Older People
Genuine care, professional staff, a warm and welcoming environment and a place to call 'home'. The Carleton Court residential home for the elderly offers much more than a place to be; we work to ensure your comfort, dignity, enjoyment and security.
Standing in its own spacious grounds with mature gardens and lawns, Carleton Court is an impressive home with beautiful features and comfortable accommodation for up to 24 residents, in tastefully decorated and furnished surroundings.
We serve a varied menu and make fresh fruit available as well as home-baked items with morning coffee and afternoon tea.
In the home itself, we hope you will encourage your family and friends to visit at any time and you will bring your most cherished personal belongings in order to arrange your space, just the way you like it.
OverallRead overall summary
Requires improvement
We carried out this inspection under Section 60 of the Health and Social Care Act 2008 as part of our regulatory functions. This inspection was planned to check whether the provider is meeting the legal requirements and regulations associated with the Health and Social Care Act 2008, to look at the overall quality of the service, and to provide a rating for the service under the Care Act 2014.
The first day of the inspection took place on 29 February 2016 and was unannounced. The inspection team consisted of two adult social care inspectors, who were supported by a specialist professional advisor (SPA). A SPA is a health and social care professional with a background relevant to the service being inspected. The SPA for this inspection was a registered nurse with experience of working with older people. We were also supported by an expert-by-experience. An expert-by-experience is a person who has personal experience of using or caring for someone who uses care services. The expert-by-experience who assisted with this inspection had experience of using health and social care services and caring for people who used these services. We returned to the home on 7 March 2016 to give feedback to the provider and registered manager.
Before the inspection we reviewed the information we held about the service. This included notifications regarding safeguarding (this is where potential abuse may have occurred and a referral for investigation is made to the local authority safeguarding team) and any accidents and changes which the provider had informed us about. A notification is information about important events which the service is required to send us by law. We also looked at previous inspection reports. Before the inspection the provider completed a Provider Information Return (PIR). This is a form that asks the provider to give some key information about the service, what the service does well and improvements they plan to make. We planned the inspection using this information.
We looked at most areas of the home including some bedrooms (with peopleâs permission) and all of the communal areas. During the first day of inspection we looked at records which related to peopleâs individual care. We looked at care planning documentation for seven people and other records associated with running a care service. This included two recruitment records and the staff rota. We also reviewed records required for the management of the service such as audits, statement of purpose, satisfaction surveys and the complaints procedure. During our visit to the service we spoke with the registered manager, a senior care worker and two care staff. On the first day of the inspection we spoke with eight people who lived at the service. We spoke with four relatives of people who lived at Carleton Court. We telephoned the specialist nurse practitioner from the Craven Care Homes Quality Improvement Support service.
We visited the service again on 31 March 2016. This visit was carried out by two inspectors, as we had concerns that people were not always safe because there was a lack of sufficient staff at the service. We spoke with five people living at the service during this visit and observed peopleâs care. We spoke with a visiting district nurse. We telephoned the Advanced Practitioner from the District Nurse Team and spoke with three GPâs who visit the service.
We received information from Healthwatch. They are an independent body who hold key information about the local views and experiences of people receiving care. CQC has a statutory duty to work with Healthwatch to take account of their views and to consider any concerns that may have been raised with them about this service. We also consulted North Yorkshire County Council to see if they had any feedback about the service, and we have incorporated this in our report.
Last updated 12:28:30 25th Apr 2017 - Update Now
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