text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 10, 1992
|Filing date
|Jan 27, 1992
|Priority date
|Dec 4, 1989
|Fee status
|Publication number
|John B. Wilker
|Original Assignee
|Hill-Rom Company
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (17), Non-Patent Citations (19), Referenced by (77), Classifications (15), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of application Ser. No. 07/444,837, filed Dec. 4, 198
The present invention relates to infant care beds and more particularly to infant warmer open care beds for providing temperature regulation of infants in maternity and newborn care facilities.
Neonatal facilities of hospitals require, under current care standards, the provision of infant beds which will automatically maintain the baby's environment within acceptable temperature limits. This necessitates the use of heating elements with controls which will effectively regulate the heat delivered to the unit in response to sensors in the bed which monitor the temperature in the vicinity of the baby and, preferably, the actual temperature of the baby's skin. It is desirable that the controls for such warmers have, in order to reliably regulate the baby's temperature, a stable and accurate control, and one which will also be responsive to abnormal and potentially unsafe conditions which require an alarm or other response.
Two types of controls have been available to regulate the temperature of infant warmers. One is the proportional or analog control by which power to a heater is varied as a function of the difference between the actual sensed temperature and a temperature setpoint. The other is the on/off type control or switching control which alternately energizes the heater, usually at a single power level, and switches off the heater, depending on whether the actual temperature is either below or above a setpoint, or below a lower minimum setpoint or above an upper maximum setpoint.
In proportional control, the temperature is usually controlled by gradually reducing the heater output as the setpoint is approached and/or exceeded, eventually turning off the heater when a maximum temperature is reached. If the temperature range around the setpoint over which the heater output is varied is wide, a very stable temperature control can be achieved, at least where the ambient conditions are stable. This is known as a loose proportional control. However, the amount of heat required to maintain the setpoint is a variable depending on external conditions which affect the rate at which heat energy is lost from the bed or unit. Where ambient conditions vary, loose proportional control may equilibrate at a temperature other than the setpoint. The equilibrium temperature which such a control may produce can, depending on ambient conditions, equal any temperature in the range of temperature over which the heater power is being tapered. The conditions which affect the equilibrium temperature would include such ambient conditions as air movement (wind chill), the proximating of attending or visiting personnel, or the operation of building heating and air conditioning equipment. Thus, although proportional control is desirable for stability, it is undesirable for accuracy.
In ON-OFF type of control, the temperature is regulated by switching the heater to full power until the measured temperature exceeds the setpoint by a specified amount, then switching the heater off until the temperature drops below the setpoint by a specified amount. This type of control continually overshoots and undershoots the setpoint by the amount of hysteresis which is dependent on the heater power level and the heat loss rate of the unit. While this type of control at least brings the temperature completely to the set point, the temperature oscillates about the setpoint so that it is neither smooth nor stable.
Infant warmers of the prior art possess at least one of the disadvantages of the proportional or on/off control systems described above.
Furthermore, although most infant warmers have high and low temperature alarms, incidents of overheating still occur with prior art devices due to the temperature sensing probe being partially dislodged from the skin of the infant or misapplied in such a way that the probe senses a slightly lower temperature than the actual skin temperature. In addition, the probe can be completely off the infant but positioned in such a manner as to be heated by the heating element, which is often a radiant element, to the temperature setpoint when the temperature of the infant is actually above or below the setpoint. All radiant warmers with servo control are subject to this hazard. When this problem occurs, since the temperature sensed may be within an allowable range of values, no alarm would be activated and the heater output may be regulated at too high or too low a temperature. Alarm systems based on temperature rely on the skin probe to sense the correct skin temperature of the infant. If the probe is not installed correctly, the alarms may not respond to the proper alarm condition.
Also, many radiant infant warmers have a manual mode of operation for use in situations where it is impossible or difficult to use the skin probes. This may be the case in a labor-delivery room, for example. When operating in such a manual mode, the temperature display is normally still active and reads whatever temperature the probe may be sensing as it rests in the warmer bed. Some warmer beds have a slide switch to select between servo and manual modes. This presents a possible hazard condition in that the warmer may be in manual mode and displaying a temperature that is within the range of an infant's skin temperature. In fact, the skin probe may be attached to the infant while the nurse may not notice that the switch is in manual mode. Depending on the manual heat setting, the infant may receive too much or too little heat.
In some heater beds, the heater power is controlled by a thyristor semiconductor device commonly known as a triac. A common failure of thyristors is to become shorted or to turn on when they should be off. This may result from electrical disturbances on the power lines. When this occurs, the heater turns on and is uncontrollable. This is of course very hazardous.
Each of the problems described above are problems currently existing in the art. Accordingly, there exists a need in the art to overcome the problems.
It is a primary objective of the present invention to provide for the regulation of the temperature of an infant in an infant warmer bed in a manner which is both accurate and stable.
It is a further objective of the present invention to provide an infant warmer bed control which reliably protects the infant against overheating.
It is an additional objective to adequately protect the infant in an infant warmer bed from improper temperature regulation in the case of use of the warmer in a manual mode.
It is a still further objective of the present invention to provide a control which protects the infant in the case of heater control malfunction.
According to the principles of the present invention there is provided a temperature control having the characteristics of an analog proportional control without the error associated with a conventional proportional control. This is accomplished by employing a circuit that adjusts the heater output up or down over a limited range until the proportional control equilibrates at a predetermined setpoint temperature. The adjustment made in this way compensates for changes in heat loss rate due to drafts and other such factors.
In accordance with the preferred embodiment of the invention, the control is initialized when powered up such that the heater output will be delivered at an intermediate value, for example 50% of maximum power, when the measured temperature is equal to the setpoint temperature. The actual amount of heater power, however, may be offset from between 10 and 90% of maximum controllable power range. Then, at widely spaced time intervals of, for example, two minutes, the temperature offset is incremented either up or down depending on whether the measured temperature is above or below the setpoint.
Also in accordance with principles of the present invention, an alarm is provided to signal excessive heating, to protect the infant. It functions by monitoring the amount of total heat delivered over a specified period of time. If the amount of heat delivered is more than normally expected as, for example, may be predetermined from statistical data for the particular type of warmer, then the system actuates an alarm and the power is reduced to a value predetermined to be at or below a maximum safe value, for example, at half power.
Further, in accordance with principles of the present invention, a control for an infant warmer bed is provided with an automatic reset to a manual mode when the system is first powered up or when a prewarm option is selected by, for example, the pressing of a button. The control, however, immediately switches to a servo or automatic temperature control mode when the skin probe senses a temperature the set-point temperature, preferably a temperature of 31� C. In accordance with the preferred embodiment of the invention, the temperature display is turned off if the unit is in manual. Then, when the system senses warmth on the temperature probe, the system latches into servo mode, turns on the temperature display and activates all safety alarms. Thus, the likelihood of having the system in manual mode and thinking it is in servo mode is substantially reduced.
Still, in accordance with other principles of the present invention a heater current signal proportional to the actual heater current is compared with the heater control signal from the proportional controller. If, at any time the two signals do not agree, a system fault alarm is activated. Preferably, the system fault alarm removes AC power from the heater by means of an electromagnetic relay and sounds an audible alarm and lights all fault indicators.
The present invention provides an infant warmer bed with stable and accurate temperature regulation, and with protection for the infant against overheating, inadvertent manual mode operation and power circuit failure.
These and other objectives and advantages of the present invention will be more readily apparent from the following detailed description of the drawings in which:
FIG. 1 is a perspective view of one preferred embodiment of an infant warmer bed in accordance with the principles of the present invention.
FIG. 2 is a view of the control panel of the embodiment of FIG. 1.
FIG. 3 is a schematic block diagram of a control circuit of the embodiment of FIG. 1.
FIG. 4 is a circuit block diagram of portions of the circuit of FIG. 3.
Referring to FIG. 1, an infant warmer bed 10 according to a preferred embodiment of the present invention is illustrated. The unit 10 includes an upstanding base 11 which has supported thereon a horizontal procedure table or bed 12. Supported at the top of the base or frame 11 is a warmer and lighting module 14 which includes a radiant heating element 15 directed downwardly onto the surface of the bed 12 so as to warm the bed 12 when energized. The bed 12 is enclosed on its sides by upstanding walls 16 with an open top 17. Above the bed 12 on the frame 11 is a panel 18. Connected through a cord to the panel is skin temperature probe 20 attachable to the infant's skin for sensing the baby's skin temperature The panel 18 is illustrated in detail in FIG. 2.
Referring to FIG. 2, the control panel 18 according to the preferred embodiment is illustrated. On the control panel 18 are mounted controls which include a power on-off push button switch 21, a lighting on-off push button switch 22, an Apgar timer on-off push button switch 23, a temperature setting control 24, a servo mode heater power indicator 25, an infant temperature display 26, a heater power control manual mode silence push button switch 29, and alarm indicators including an overheating indicator 30, "hi/lo" temperature indicator 31, over 39� C. indicator 32, and probe fault indicator 33. The controls and the indicators of the control panel 18 are elements of the control circuit illustrated in the circuit block diagram of FIG. 3.
FIG. 3 illustrates the controller operated from the control panel 18 to control the heater element 15. The control includes a control circuit 34 connected between the controls on the panel 18 and a heater power circuit 35 which energizes the heater element 15. The heater element 15 is connected into the circuit 35 across the leads of a supply cord 36 connectable to a source of AC power, typically 120 VAC 60 Hz. The heater element 15 is connected in the circuit 35 in series with a heater power control triac 37. The triac 37 has a control input 38 connected to the output of a triac driver circuit 39. The triac driver circuit 39 has an input connected to the power control output 40 of the control circuit 34. A normally closed cut-off relay 41 is also connected in series with the heater 15 and the triac 37 in the circuit 35. The relay 41 has an actuator 42 which is coupled to operate in conjunction with the system fault alarm 43.
A Hall-effect current sensor 44 is provided for generating a signal at a monitoring input 45 of the control circuit 34. The detector 44 has a sensor input 46 coupled to a current responsive indicator 47 connected in series with the heater circuit 35.
A reset circuit 48 is provided having an input 49 coupled to circuit 35 to provide a power-up reset momentary signal at a reset input 50 of the circuit 34. The reset circuit 48 has a second input from the alarm silence pushbutton 29. Operation of the alarm silence pushbutton 29 also causes a reset signal to be generated on a reset line 50 to the circuit 34.
The control circuit 34 includes four subcircuits which include a self-adjusting proportional servo-control circuit 57, a heater power servo/ manual/cutback selector circuit 59, an automatic mode control circuit 60 and a "hi/lo", 39� C., probe, overheat system fault alarm circuit 61.
The skin temperature probe 20 is connected to the input of a temperature measuring circuit 51 which has an output 52 on which a signal proportional to the measured skin temperature is delivered to a temperature signal inputs of the proportional control circuit 34 and the alarm circuit 61 of the control circuit 34. The temperature setting control 24 is connected to a temperature setpoint input 53 of the proportional control 57 and alarm circuit 61 of the control circuit 34. The manual mode heater power setting control 27 is connected to a manual power level input 56 ,of the control circuit 34.
The self-adjusting proportional control 57 has a pair of inputs connected one to the temperature signal output 52 of the temperature measuring circuit 51 and the other to a setpoint signal line 53 of the servo temperature setpoint control 24, and an output for delivering an analog signal on a line 58 to an input of the heater power selector circuit 59.
The heater power selector 59 is a dual analog switch circuit which selects one of three signals from either of three inputs connected respectively to the proportional control circuit 58, a manual control line 56 from the manual control 27, or a preset default level signal line 30 in response to signals from the output 62 of the automatic mode control circuit 60 or from an output 54 the alarm circuit 61. The output signal on output line 40 of the power selector circuit 59 is delivered to the input of the triac driver circuit 39. The triac driver circuit 39 is an optical coupled triac which operates to deliver a gate signal on the gate input 38 of the heater power control triac 37 to cause it to control the power in the power circuit 35 in accordance with the analog signal output 40 of the control circuit 34.
The automatic mode control circuit 60 has three inputs, one of which is connected to the temperature signal input 52 of the circuit 34, another of which is connected to the reset signal input 50 of the circuit 34, and a digital output signal line 62 connected to the alarm circuit 61 and the heater power selector circuit 59.
The control circuit 34 has as its fourth subcircuit, an alarm circuit which has seven inputs and six outputs.
The inputs to the alarm circuit 61 are reset input from reset line 50, the servo/manual mode signal input from the output 62, a "31� C." signal input 108 from the mode control circuit 60 of control circuit 34, a temperature signal from line 52, a measured temperature-setpoint input 68 from the servo-control circuit 57, the heater drive signal from output line 40 of circuit 34, and an input from the heater current signal input 45 from the hall effect pick-up circuit 44. The outputs from the alarm circuit 61 are a hi/lo temperature alarm signal output 63, a 39� C. alarm signal output 64, a probe fault signal output 65, an overheating alarm signal output 66, a preset power signal output 54 to the heater power selector circuit 59 and a system fail signal output 55 to the system fail indicator 43 and cutoff relay 41. The output signals 63,64,65,66 drive respective alarm indicators 31,32,33,30 (not shown) on the panel 20.
The reset circuit 48 has two inputs, one is the alarm silence, pushbutton 29, the other is a sensor input 49 sensing the presence of line power 49. The circuit 48 has one output 50 connected to the control circuit 34. A power loss alarm circuit 67 is provided for sensing the loss of AC power circuit. The circuit 67 has an input connected to sensor line 49 for sensing the presence of AC line power, and has an audible signaling device contained therein for producing an audible alarm output.
The details of the subcircuits 57, 59, 60 and 61 and of the related circuitry are illustrated in greater detail in the block diagram of FIG. 4.
Referring to FIG. 4, the self adjusting proportional control circuit 57 is illustrated. It includes a differential amplifier 70 having a pair of inputs connected one each to the temperature signal input line 52 and the temperature setpoint signal line 53. The circuit 57 also has an output signal line 71 connected to a summing network 72 and to an input of the alarm subcircuit 61. The circuit 57 further includes an analog comparator circuit 73 which is provided also with a pair of inputs connected, one each to the temperature signal 52 and the setpoint signal 53, and having an output 74 connected to an up/down control input of a 4 bit binary up/down counter 75. The comparator 73 produces a digital signal output 74 indicative of which of the two analog signals connected to the inputs, 52 & 53 is greater in voltage.
The counter 75 has a clock input 76 connected to the output of a long time interval timer circuit 77. This causes the counter 75 to step up or down in accordance with the state of the up/down input 74 at a slow rate, for example every two minutes. The counter also has a preset input 78 which sets the counter to an intermediate value, for example "8" upon power-up of the unit 10. The counter 75 has a parallel 4 line digital output 79 connected to a digital to analog converter circuit 80 which has an analog output connected to the second input of the summing network 72. The summing network adds the two analog signals from the differential amplifier 71 and the D/A converter 80 to produce the servo control signal 58.
The servo heater control output 58 of the summing network 72 is connected to one of three analog inputs of the heater power selector circuit 59. The second of three analog inputs 56 is connected to the output 56 of the manual control 27. The third analog input 30 is a preset level formed by a voltage divider which is the level set during an alarm condition.
The heater power selector subcircuit 59 is controlled by a digital signal 62 from the automatic mode control circuit 60 and a second digital signal 54 from the alarm circuit 61. The circuit 59 includes a pair of analog switches 1-2 and 113. The function of the switches 112 and 113 is to connect one of three analog inputs (servo, manual or preset) to the output 85. The output 85 is connected to the input of a voltage comparator 87 which has a second input 84 connected to a sawtooth wave generator 83. The voltage comparator 87 produces a pulse width modulated square wave output 40 whose ratio of "on" time to "off" time instantaneously varies with respect to the difference between the actual temperature and the setpoint temperature and varies in a slow stepwise manner to the difference between the setpoint and the equilibrium point temperature.
The modulated square wave output 40 of the control circuit 34 is connected via the opto-coupler triac driver circuit 39 to the heater power control triac 37. The analog output 85 is also connected to a bargraph driver circuit 86. The bargraph driver circuit illuminates a series of rectangular LED bars to display the power level. The bargraph driver is connected to two bargraphs, one for servo mode 25 and the other for manual mode 27. Only one of the two bargraphs are on at a given time as determined by the mode control signal 62.
The automatic mode control subcircuit 60 has an input from the temperature signal 52 connected to a comparator circuit 107 designed to produce an output signal 108 when the measured temperature is greater than 31C. The comparator output 108 is connected to the set input of a latch circuit 110 and to the input of a one-minute timer 121 of the alarm circuit 61. The latch circuit output 62 is connected to the heater power selector circuit to switch the control from manual to servo operation and the alarm circuit to enable the hi/lo alarm 31 and the probe dislodged timer. The hi/lo temperature and dislodged probe alarms 31 and 32 are active only in servo mode. The servo mode latch circuit 110 is reset to manual mode by a reset signal 50 which is active whenever the unit is powered up or the alarm silence button is pressed.
The alarm circuit 61 consists of five separate alarms: a hi/lo temperature alarm 31, a 39� C. temperature alarm circuit 32, a probe alarm 33 (open or dislodged), an overheating alarm 30, and a system fault alarm 43. The alarm signals from the first four alarms 30-33 are connected to an OR gate 122 whose output is a power cutback signal generated on signal line 54 which causes the heater power selector circuit 59 to switch to the preset level regardless of the state of the automatic mode circuit. The preset level is set to approximately 25% of full power.
The hi/lo temperature alarm circuit consists of two voltage comparators 97 & 98 which compare the output signal on, line 71 of the differential amplifier 70. This signal corresponds to the difference between the measured temperature and the temperature control setpoint to preset voltage levels equivalent to +0.5� C. and -0.5� C. temperature differential. The outputs of the two comparators are connected to an OR gate 81 so that either output will cause an alarm signal to be produced to one of two inputs of an AND gate 82 if the measured temperature differs from the control setpoint temperature by +/-0.5� C. Another input of the AND gate 82 is connected to the servo/manual signal 62 such that the hi/lo alarm 31 is enabled only in servo mode. The output 63 of the AND gate 82 is connected to the hi/lo alarm indicator 31 and to the enable input of a two minute timer 119. The output of the timer 119 is connected to an input of an OR gate 122. If the hi/lo alarm signal on line 63 is on for two minutes or more, the timer output 119 is activated which causes the OR gate output 54 to activate which sets the heater power circuit 35 to the preset power level.
The 39� C. alarm consists of a voltage comparator circuit 116 with the measured temperature signal 52 as one input and a voltage divider set to a voltage level equivalent to a 39� measured level as the second input. The output 64 of the comparator 116 is connected to the 39� C. alarm indicator 32 and to the OR gate 122. If the measured temperature exceeds 39� C., the 39� C. alarm indicator 32 is activated and the heater power is set to the reduced power mode.
The probe alarm 33 consists of a one minute timer 121 which is enabled by the servo mode signal on line 62 and the inverse of 31� C. temperature signal on line 108. If the unit is in servo mode and the probe temperature drops below 31� C. for 1 minute or longer, a signal from the output of the timer 121 is connected through an OR gate 120 to the probe fault output 65. The output 65 is thereby activated and the heater power is set to the preset level of approximately 25%. The one minute delay allows the probe location to be changed without activating the alarm. If the probe becomes open circuited, for example due to a broken wire, then the probe fault output 65 is immediately activated by the open probe comparator 117, the output of which is connected through the OR gate 120 to the output 65, and to an input of the OR gate 122 by which the heater power is reduced to the preset level. The timer is reset by the alarm silence & power-up reset signal 50.
The overheating alarm includes a square wave circuit 88 having an input connected to the heater current signal 45 from the Hall-Effect current pickup circuit 44. The square wave circuit 88 functions to amplify and hardlimit the AC signal from the Hall-Effect device 44, to produce a rectangular wave signal consisting of bursts of 60 Hz pulses for a duration proportional to the power delivered by circuit 35 to the heater 15. These pulses are connected to the clock input of a 24 bit binary counter 90. A 16 bit parallel digital output 91 of the counter 90 is connected to a programmable decoder 92 which generates an overheating alarm output signal 66 when the count of the counter 90 exceeds a predetermined number indicative of excessive total power to the heater during a predetermined time interval. The time interval is determined by a timer 93 which is preferably a 15 minute timer, connected through an OR gate 113 to the reset input 94 of the counter 90. The other input of OR gate 113 is connected to the reset timer 50. If the counter 90 fails to reach the predetermined count during the duration of the time period, the counter is reset and the cycle repeated. The overheating alarm output 66 is connected to the overheating alarm indicator 30 and to the OR gate 112 which causes the heater power to be set to the preset level if the alarm condition is present.
The system fail alarm circuit monitors the power control circuitry 35 for the heater 15. The signal on line 89, consisting of bursts of 60 Hz square wave pulses, is connected to a 20 millisecond retriggerable multivibrator circuit 95 whose output 96 is a rectangular waveform whose width is equal to the timer period that the heater 15 is actually on. The multivibrator output 96 is connected to one input of a two input exclusive-OR circuit 114, which has its second input connected to the heater control signal line 40 of the control circuit 34. The exclusive-OR circuit produces an output signal on line 99 to the input of an OR gate 123 whenever the power control signal on line 40 and the multivibrator output 96 representing heater current are not concurrent. The output of OR gate 123 is connected to the set input of a system fail latch circuit 100. The other input of OR gate 123 is connected to the shorted-probe voltage comparator output 115, which compares the signal at its input from line 52 with a voltage reference to recognize a shorted probe condition. The system fail latch 100 has an output 55 connected to the system fail circuit 43 which activates the power cut-off relay 41 and illuminates all the fault indicators 30,31,32,33. The latch circuit 100 has its reset input 118 connected to a power up reset signal 50.
In manual operation, the measured temperature by the probe 20 must remain below 31� C. During this time, the heater power is controlled by a voltage level derived directly from the setting of the front panel manual power level control 27. The open or shorted probe alarms, 33, the excessive heating alarm 30, and the system fault alarm 43 are active. If the probe temperature increases above 31� C., such as would be the case if placed on an infant, the automatic mode control switches to servo mode and latches unless reset by the alarm silence button 29 or by powering down the unit and turning back on. If the control is reset to manual with the probe temperature greater than 31� C., it will immediately switch back to servo mode. The manual power bargraph indicator 28 is illuminated only during manual operation and indicates the percentage of full power of the heater 15.
In servo operation, the setpoint temperature and the measured temperature are each converted to an electrical voltage level with equal scale factors and applied at the respective inputs 53 & 52 of the control circuit 34. These two signals are compared by the op-amp voltage comparator 73. The output 74 of the comparator 73 is high or low depending on which of the two voltages is larger. This output signal 74 is communicated to the up/down control input of the 16 count binary counter 75. The counter 75 will have been present to count 8 when powered up and is clocked at a very slow rate of 1 clock every 2 minutes as determined by the timer 77. The binary counter will count up if the setpoint is above the measured temperature, and will, count down if the setpoint is below the measured temperature. Under steady state conditions the up/down switching will alternate at a 2 minute rate. The counter is inhibited from going any further if a count of 0 or 15 is reached. The output signals from the counter 75 are connected to a digital-to-analog converter circuit 80 which converts the count to a voltage 81 with a level proportional to the count of the counter 75. This level is scaled such that each count produces a voltage change equivalent to approximately 0.05� C. This voltage 81 is added as an offset to the signal 71, representing the difference between the measured temperature and setpoint voltages, by the summing network 72 which produces the servo mode heater control signal 58. Thus, the heater output, with the control at equilibrium, will be adjusted slightly up or down depending on whether the setpoint is above or below the measured temperature. This will continue until the control comes to equilibrium precisely at the setpoint. Once this occurs, the proportional control is precisely compensated for the environmental conditions which influence the rate of heat loss from the unit 10, yet will respond immediately to measured temperature variations from the sensor 20.
The heater output is controlled by switching the heater on and off for a number of cycles of the line current as determined by the proportional control. The ratio of ON time to the total time available is related to the percentage of maximum power. By monitoring the 60 Hz heater current signal during a definitive time interval, the average percentage of full heater power is determined. A heater current signal is developed by passing the current through an inductor coil 47 (FIG. 3). The magnetic field set up by the heater current passing through the inductor 47 is detected by a Hall-Effect device 44 which has an electrical output 45 proportional to the magnetic field set up by the heater current in circuit 35. The heater current signal is used by the heat alarm circuits 61 which generates both the excessive heating alarm signal on output 66 and the heater power control monitor which controls the system fail alarm at output 55.
The heater current signal from input 45 is converted to a square wave and used to clock the totalizing counter-decoder 90 that will output a signal at a predetermined count. The counter will count the 60 Hz current signal in bursts equal in duration to the ON time until the count equals the predetermined value or is reset. For example, if the heater is on 50% power for 15 minutes then the count would be:
50/100�60 Hz�60 sec/min�15 min=2700.
The counter 90 is reset at preset time intervals determined by the timer 93. If the counter 90 reaches the preset count total within the preset time interval, then the circuit 61 activates the alarm 30 and reduces power to a safe value by switching to a preset level of 25% for full power. If the counter 90 does not reach the preset count within the time interval, it is reset to start a new monitoring period. For example, if the counter is reset every 15 minutes, and the preset count to alarm is 27000, then if the power level averaged more than 50% it would alarm.
The following are example cases:
At 100% power the alarm will go off in 7.5 min. (100/100�60�60�7.5=27000)
At 60% power the alarm would go off in 12.5 min. (60/100�60�60�12.5=27000)
At 40% power level the alarm would not go off. The counter 90 would be reset to 0 at 15 minutes prior to the count reaching 27000. (40/100�60 Hz�60 sec/min�15 min=21600)
Therefore, the system will alarm if the heater output exceeds a preset amount during a predetermined time interval. The actual values for the percentage of power and time interval are adjustable to allow for variation in heaters,, but should approximately equal to that percentage of heater power needed to produce an irradiance of 20 milliwatts per square centimeter measured 4 inches above the bed 12 for 15 minutes.
The skin temperature is converted to a voltage which is displayed on the digital display 26 using a DVM (digital voltmeter) circuit. This voltage also goes to the alarm board. A series of four voltage comparators 117, 107, 116 and 115 detect the following temperatures: (1) out-of-range low--open probe alarm 117, (2) greater than 31� C.--servo mode active 107, (3) greater than 39� C. --high temp alarm 116, and (4) out-of-range high--shorted probe alarm 115. When the unit is turned on, the servo-manual latch 110 is placed in its manual mode by a reset signal from reset input 50. Whenever a skin probe temperature of 31C or greater is sensed by the sensor 20, the latch 110 sets to servo mode. If the skin probe temperature is above 31� C., then drops below 31� C., the latch 110 will stay in servo mode until the alarm silence button 29 is pressed.
The heater current monitoring is provided by passing the heater current through the inductor coil 47 which is magnetically coupled to a linear Hall-effect device 44. The output of the Hall-effect device is an AC voltage proportional to the heater current. This ,voltage is converted to a square wave in the circuit 88 and is used to trigger the 20 millisecond retriggerable one-shot multivibrator 95. Since the period of the 60 Hz current waveform is 16.6 milliseconds, the output of the multivibrator 95 is a constant high logic level when the heater is on and low when it is off. This level is compared using an `exclusive OR` logic circuit with the heater control signal from the analog output 40. If the two signals differ, the exclusive-OR circuit triggers a latch circuit 100. The latch 100 will also activate if the heater current is off when it should be on. Thus, it immediately latches if the heater, fuse or thermal switch fails open circuited. Thus, a signal is also generated before the infant gets cold or low temperature alarm goes off.
The present invention represents a significant improvement in the safety of infants nursed under radiant warmers.
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|U.S. Classification
|600/22, 119/319, 219/497, 392/418, 119/306, 237/3, 219/494, 236/3
|International Classification
|Cooperative Classification
|European Classification
|Jun 18, 1996
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text:
|Publication number
|Publication type
|Application number
|Publication date
|Sep 29, 2009
|Filing date
|Jul 29, 2005
|Priority date
|Nov 29, 2000
|Fee status
|Also published as
|Publication number
|Klaus Johannes Weber, Andrew William Blakers
|Original Assignee
|Australian National University
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|BiBTeX, EndNote, RefMan
|Patent Citations (100), Non-Patent Citations (23), Referenced by (25), Classifications (32), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of U.S. application Ser. No. 10/432,936, filed May 28, 2003, which is a 371 U.S. National Phase application claiming priority to PCT/AU01/01546, filed Nov. 29, 2001, which is based on Australian provisional application PRI748, filed Nov. 29, 2000.
The present invention relates to semiconductor processing, and in particular to methods for processing a semiconductor wafer to increase the useable planar surface area, to a method for fabricating solar cells and to a process for decreasing the reflectivity of a semiconductor surface.
In most areas of semiconductor processing, the cost of the starting substrate wafer is small compared to the value of the final, processed wafer. However, this is not always the case. For example, the photovoltaic solar cell industry is extremely cost sensitive, and the cost of a starting silicon wafer is typically nearly half of the processed wafer value. Thus, in this industry it is extremely important that the silicon substrates are used as efficiently as possible. These substrates are produced by sawing thin slices from a cylindrical boule of crystalline silicon, typically 6 inches (about 15 cm) in diameter. The thinnest slice that can be cut is determined by the mechanical properties of the silicon, and is typically 300-400 μm for the current generation of 6 inch wafers, but is projected to be 200 μm for the next wafer generation. However, the kerf loss for sawing through a 6 inch wafer is approximately 250 μm, meaning that much of the boule ends up as powder. There is a need, therefore, for a method which increases the useful surface area of semiconductor for a given unit volume of the semiconductor, or at least for a useful alternative to current methods of semiconductor processing.
In accordance with a first embodiment of the present invention, there is provided a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, said method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into said strips at an angle to said substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.
In a second embodiment, the present invention provides a method for processing a semiconductor wafer having a substantially planar surface to increase the useable planar surface area of said wafer, including the steps of:
It will be understood that the faces of the strips which were previously at an angle to the surface of the wafer are the faces of the strips exposed as a result of cutting the wafer and separating the strips from each other.
The semiconductor wafer is typically single crystal silicon or multicrystalline silicon. However, the semiconductor wafer may be a wafer of other semiconductor material capable of being fabricated into a thin, substantially flat wafer.
In a third embodiment, the present invention provides a method for producing silicon solar cells, said method comprising the steps of:
Solar cells can be formed before or after the separation of the strips or as part of the separation process.
In the methods of the first to third embodiments of the invention the strips may be at any angle to the surface of the semiconductor wafer or substrate, such as at an angle of from 5� to 90� to the surface of the wafer or substrate. Typically the strips are at an angle of at least 30�, more typically at least 45�, still more typically at least 60� and even more typically about 90� (that is, substantially perpendicular) to the surface of the wafer or substrate.
Thus, in a preferred form of the method of the first embodiment of the invention, there is provided a method for processing a semiconductor wafer to increase the useable planar surface area, including the steps of selecting a strip thickness for division of the wafer into a series of thin strips generally perpendicular to the wafer surface, selecting a technique for cutting the wafer into said thin strips in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, and dividing the wafer into said thin strips.
In a preferred form of the method of the second embodiment of the invention, there is provided a method for processing a semiconductor wafer to increase the useable planar surface area, including the steps of:
In one form of the methods of the first to third embodiments of the invention, a laser is used to form the slots in the wafer. An area around the periphery of the wafer may be left uncut, forming a frame, so that all the resulting strips are held within the frame. This allows handling of the wafer following formation of the slots, while the strips undergo further processing. The strips may be separated from the frame at any convenient stage of the further processing.
In another form of the methods of the first to third embodiments of the invention, a dicing saw is used to form the slots in the wafer. An area around the periphery of the wafer may be left uncut, forming a frame, so that all the resulting strips are held within the frame. This allows handling of the wafer following formation of the slots, while the strips undergo further processing. The strips may be separated from the frame at any convenient stage of the further processing.
In yet another form of the methods of the first to third embodiments of the invention, wet anisotropic etching of (110) oriented wafers is used to form the slots. An area around the periphery of the wafer may be left unetched, forming a frame, so that all the resulting strips are held within the frame. This allows handling of the wafer following formation of the slots, while the strips undergo further processing. The strips may be separated from the frame at any convenient stage of the further processing.
In still another form of the methods of the first to third embodiments of the invention, photo-electrochemical etching may be used to create an aligned series of perforations through a semiconductor wafer, and chemical etching may then be used to etch through the semiconductor remaining between the perforations and along the lines defined by the perforations, to form a narrow slot through the wafer.
In a further form of the methods of the first to third embodiments of the invention, at least one interconnecting portion is formed in or on the wafer, which connects adjoining strips to each other to maintain a relatively constant gap between the strips. Usually, in this form of the methods of the invention, there are a plurality of interconnecting strips. Conveniently, the interconnecting strips are spaced apart at regular intervals along the length of the strips. The inclusion of such interconnecting portions allows processing steps such as diffusions and oxidations to be carried out in a reliable and repeatable manner, resulting in predictable diffusion profiles and oxide thicknesses down the sides of the slots. The interconnecting portions suitably take the form of one or more strips of the semiconductor material formed at least partly across one or both main surfaces thereof, perpendicular or oblique to, and usually substantially perpendicular to, the strips which are defined by the plurality of slots.
The methods described herein are equally applicable to entire semiconductor wafers and to pieces of wafers. Consequently, the word wafer used in this specification is to be taken to refer to entire wafers or portions thereof.
In the methods of the second and third embodiments of the invention the slots are typically created through the complete thickness of the wafer, though not necessarily. Where the slots are created through the thickness of the wafer, they may be created in one step or more than one step. For example, the plurality of slots may be created partly through the wafer, optionally further processing may be carried out, such as doping of the surfaces of the strips so created, and then the plurality of slots may be completed by cutting or etching through the remainder of the thickness of the wafer. Thus, the step of separating the strips from each other will typically occur when the creation of the slots is completed through the entire thickness of the wafer. Alternatively, if a frame is left uncut around the periphery of the wafer as described above, the step of separating the strips from each other will occur when the strips are cut from the frame. As a further possibility, when interconnecting portions are employed to connect adjoining strips, as described above, the step of separating the strips from each other occurs when the interconnecting portions are removed or broken. As a still further possibility (though less preferred) the strips may be separated from each other by breaking them apart if the slots between the strips are formed only partway though the wafer but the remaining part of the wafer at the bottom of the slots is very thin.
Preferably, most of the processing of the strips into solar cells is carried out while the strips are supported within a frame formed from an uncut area around the periphery of the wafer. Following processing, the strips are cut out of the frame and laid flat side by side. Preferably, separation of the strips from the frame is carried out using a laser or dicing saw.
Advantageously, solar cells made by a process which includes a method in accordance with the present invention may be arranged with gaps between adjacent cells and used with an optical concentrator to increase the effective solar cell area.
Advantageously, said solar cells may be used with optical reflectors in order to utilize the cells fabricated by illumination on both sides of each solar cell strip.
In some forms of the methods of the invention, such as when chemical etching is used to form the slots that separate the strips, the newly-exposed surface of the semiconductor material is a polished surface. Such a surface is typically a reflective surface, and it will be appreciated that a reflective surface is undesirable for a solar cell. Although some techniques exist for texturing a polished semiconductor surface, they are not well adapted to be used in conjunction with the methods of the first to third embodiments of the present invention. Accordingly, there is a need for an improved process for reducing the reflectivity of a semiconductor surface.
The present invention, in another aspect, provides such a process.
Thus, in accordance with a fourth embodiment of the present invention, there is provided a process for decreasing the reflectivity of a surface of a semiconductor material, the process comprising:
In the process of this embodiment, by "substantially unetched" is meant that the etching is carried out under conditions in which the semiconductor material is etched in the vicinity of the apertures in the protective substance, but sufficient of the protective substance remains on the surface of the semiconductor material at the end of the etching to prevent the semiconductor material from being etched in regions other than in the vicinity of the apertures.
In the process of the fourth embodiment, the semiconductor material is typically silicon and the protective substance is silicon nitride and the etchant is a mixture of hydrofluoric acid and nitric acid, such as a 1:50 by volume mixture of 49% by weight aqueous HF and 70% by weight aqueous nitric acid. When the semiconductor material is silicon, it may be single crystal silicon, microcrystalline silicon, multicrystalline silicon or polycrystalline silicon.
The process of the fourth embodiment typically includes the further step of removing the protective substance from the surface after the etching step has proceeded sufficiently to produce a plurality of etch pits on the surface. The protective substance may be removed by applying an etchant that etches the protective substance much more rapidly than the semiconductor material. For example, when the semiconductor material is silicon and the protective substance is silicon nitride, the protective substance may be removed by reactive ion etching or by contact with phosphoric acid at elevated temperature, typically about 180� C.
The layer of protective substance is typically only a few atomic layers thick and may be formed by known techniques such as chemical vapour deposition or low pressure chemical vapour deposition. Other possible techniques for applying the protective substance include spray pyrolysis, evaporation and sputtering. Thus, the layer of protective substance is typically about 2 nm thick, and when formed by low pressure chemical vapour deposition in this thickness is an incomplete layer in that it contains numerous holes though which the semiconductor material beneath the protective layer can be etched. When the semiconductor material is silicon and the layer of protective substance is a layer of silicon nitride about 2 nm thick, the step of etching the semiconductor is achieved by contacting with a 1:50 (v/v) HF/nitric acid mixture as described above for a time of a few minutes, typically 2-3 minutes, at ordinary room temperatures.
Preferred embodiments of the present invention are hereinafter described, by way of example only, with reference to the accompanying drawings, which are briefly described as follows.
In the description of the drawings which follows, like items are referred to by reference to like numerals. It will be appreciated that the drawings are not to scale and are diagrammatic only. For example, for greater clarity, the drawings do not necessarily depict all of the slots, strips, interconnecting portions and the like formed in a semiconductor material by the methods described.
Referring to
Slots 2 can be formed by cutting the wafer with a dicing saw having a narrow blade. Alternatively, slots 2 can be formed by laser ablation. For example, a Resonetics Nd:YLF Q-switched laser operating at the fundamental wavelength of 1046 nm or frequency doubled (523 nm) can be used to cut wafer 3. Other systems can also be used, such as a water-jet guided laser cutting system as described in U.S. Pat. No. 5,773,791. As a further possibility, slots 2 can be formed by using a wet anisotropic etchant, such as potassium hydroxide solution (KOH), as is well known in the art. In this case, it is necessary to use a single-crystal silicon wafer of (110) orientation. First, a suitable etch mask such as silicon dioxide or silicon nitride is deposited or grown on both sides of wafer 3. Photolithography is used to open narrow stripes in the etch mask on one surface of wafer 3, the stripes being typically 0.005 mm wide, at a 0.1 mm pitch and oriented along the [1-1-2] direction. Wafer 3 is now immersed in the etching solution. One suitable solution is an aqueous solution of 44% w/v KOH, with etching done at or above room temperature.
Any of the methods described above can be carried out either from one side of wafer 3 only, or from both sides of wafer 3, allowing thicker wafers to be used. For example, when using a laser capable of ablating 0.5 mm of silicon, a first set of slots is made from the front side of a 1 mm thick wafer. The wafer is then turned around, and a second set of slots, aligned to the first, is made. Alternatively, both sets of slots may be formed simultaneously by having aligned laser beams above and below the sample.
If either a dicing saw or a laser is used to form the slots, it is desirable to have multiple blades or multiple beams cutting slots into the substrate simultaneously in order to speed up the process. For example, if slots are to be formed over a 10�10 cm2 wafer of silicon with a pitch of 0.1 mm, one thousand cuts are required. If twenty laser beams are arranged to hit the sample surface at a pitch of 5 mm, each beam is required to make only fifty cuts.
Silicon wafer 3, provided with an array of macropores 27, is then immersed in a silicon etchant such as a potassium hydroxide solution. This results in an enlargement of macropores 27. As shown in
In yet a further form of the methods of the first to third embodiments, slots through the wafer extend all the way through the wafer over most of their length but at regular intervals along the slots they are less deep so that some substrate remains at the bottom of the groove, forming a series of connecting strips. This is shown in
In a still further form of the methods of the first to third embodiments, shown in
Slots 2 are then formed in wafer 3 from the face opposite to the face of wafer 3 in which trenches 7 are formed, using either a dicing saw or KOH etching, as shown in
A still further form of a method in accordance with the present invention is illustrated in
Yet a further form of the methods of the first to third embodiments of the present invention is illustrated in
Having formed structures as described above, the entire wafer may be processed to form solar cells, as described below. Following processing of the wafer and prior to separation of the silicon strips from the supporting frame, the connecting strips, if present, are removed if required. This can be done, for example, by laser ablation. Removal of the connecting strips may not be required if they are so thin that they will break when the silicon strips are separated from the supporting frame. The silicon strips are then separated from the supporting frame and laid flat by means of an arrangement such as that shown in
Solar cells can be fabricated on the silicon strips 1 by the following process, which is described with reference to
The starting wafer is p-type with a resistivity of around 1 ohm-cm. A heavy phosphorus diffusion 9 (typically 10 ohms per square) is made on one side of the wafer, followed by a heavy boron diffusion 10 (typically 20 ohms per square) into the opposite side. A thin oxide (around 50 nm) is grown on both sides of the wafer, followed by deposition of a thin layer (around 50 nm) of LPCVD silicon nitride resulting in a layer on each side of the wafer. Slots are subsequently formed in the wafer, as described above. If a dicing saw or laser is used, the slots are etched in a suitable solution such as 20% KOH at room temperature, in order to clean the sidewalls of the strips and remove any residual damage. The sidewalls can be textured using a suitable texturing technique. A light phosphorus diffusion 11 of around 200 ohm per square is made with both sides of the wafer exposed to the dopant, so that the sidewalls are entirely n-doped. This is followed by the growth of an oxide 12 of around 200 nm thickness on the exposed sidewalls. Next, the nitride layer is stripped off the front and rear of the wafer using either reactive ion etching or other suitable nitride etch such as hot phosphoric acid at about 180� C. The thin oxide underneath the nitride is then removed in hydrofluoric acid solution. Since oxide 12 covering the light phosphorus diffusion is much thicker than the oxide under the nitride, it is not removed by this etch. Metal 13 is now deposited on both sides of the wafer in such a way as to minimize deposition of the metal down the sidewalls. This can be done, for example, by line of sight vacuum evaporation.
In another process for fabricating solar cells, described with reference to
This cell structure can be realized using just one photolithographic step, as follows. Following deposition of oxide and nitride on the front and rear surfaces, both surfaces are coated with photoresist and aligned stripe patterns are photolithographically defined in both resist layers. This may be achieved in a single exposure step by arranging for simultaneous exposure of two aligned masks, one above the wafer, and the other below the wafer. After developing the photoresist, the wafer is immersed in buffered HF solution, which etches silicon nitride as well as silicon dioxide, albeit more slowly. The wafer is removed from the etching solution when about half the thickness of the nitride layers has been etched, as shown in the schematic illustration of the oxide layers 12A and 12B, and nitride layers 29A and 29B, on front surface 40 and rear surface 50 respectively, in
Once the wafer has been processed and the strips have been separated from each other, the strips are laid flat on a suitable substrate. The cells can be connected in series or in parallel, either with a gap between cells in the case where static concentration of light is used, or without a gap between cells.
The arrangements of
After the individual cells have been fabricated and mounted according to any of the embodiments described above, the cells must be packaged into a suitable form for use.
Because each of the strips is an individual cell, this can be exploited to increase the effective area of each cell by using a light concentrator. In order to increase the amount of light absorbed by each cell, the cells are not placed next to each other but spaced apart by a certain distance. The spacing is between 0 and 3 times the width of each cell. Advantage can also be taken of the fact that the cells are bifacial: that is, they respond equally well to sunlight impinging on either surface.
In order to maximize the efficiency of silicon solar cells, it is important to maximize the amount of light with a wavelength less than 1100 nm absorbed in the silicon. There are two mechanisms which can reduce the amount of light absorbed. Light may be reflected off the silicon surface, or it may enter the silicon and exit the silicon again some time later without having been absorbed. Both these loss mechanisms can be reduced by roughening, or texturing, the silicon surface. This reduces reflection losses by increasing the probability that a light ray will strike the silicon surface multiple times, and it reduces absorption losses by confining the light within the silicon.
A texturing technique which can be used for single crystal silicon of (100) orientation is to etch the silicon in a solution of potassium hydroxide (KOH) and isopropyl alcohol (IPA). This results in a surface covered in square base pyramids. However, this approach cannot be used for the case where the silicon strips are created by KOH etching, as in this case the surfaces of the strips have a (111) crystallographic orientation. Several other texturing techniques are currently under development which do not rely on a particular crystallographic orientation, such as the use of reactive ion etching (RIE). However, these techniques may prove to be expensive or to lead to other disadvantages, such as increased carrier recombination at the silicon surface. Further, these techniques are only suitable for the texturing of flat wafers and cannot be applied to the texturing of silicon strips which are held in a wafer frame, such as strips produced as part of a process of the present invention.
The above texturing technique is particularly advantageous for thin film silicon cells since it only consumes a small amount of silicon in the texturing process (approximately 2-3 microns on each textured surface). The texturing technique can be applied to silicon wafers or films of arbitrary grain size.
The etching of deep grooves with vertical sidewalls into (110) silicon wafers has been reported extensively in the literature. For narrow grooves of several hundred microns depth, it is often found difficult to maintain a uniform groove depth and a reasonable etch rate. Two possible reasons for this are the formation of hydrogen bubbles which adhere to the sidewalls of the grooves and prevent etching in the regions around the bubbles, and the lack of supply of fresh etchant to the bottom of the grooves. Several methods have been discussed in the literature which may improve the etch rate and uniformity of deep grooves, such as the use of ultrasonic agitation and stirring. However, stirring of the solution does not result in a substantial improvement in the etch behaviour of deep grooves, while ultrasonic agitation often leads to the destruction of fine features.
We now describe another technique for the etching of deep narrow grooves. This technique consists of periodically removing the wafer from the solution and then reinserting it. In a typical treatment, etching is done with a 44 wt % solution of KOH at 85� C. for 5 hours. The wafers are placed in an assembly which holds them in place, typically at an angle of about 45� to the horizontal. The assembly lowers the wafer into the solution and leaves it immersed for 5 minutes. Then, the wafers are raised above the solution and left in this position for 5 minutes. Now the cycle is repeated by again lowering the wafers into the solution.
The technique described above was applied to a silicon wafer having grooves whose initial width was 10 microns. A 5 hour etch resulted in approximately 10 microns lateral etching so that the final groove width was 20 microns. Depth variation was found to be less than 40 microns at the end of the 5 hrs etching. The minimum and maximum groove depth was at 340 and 380 μm respectively. An experimental evaluation showed that 60% of grooves etched to a depth range of 350-360 microns, 15% etched to a depth of 340 and the remaining 25% etched to a depth range of 370-380 microns. A 0.5 mm thick piece of silicon was entirely etched through in a time of 6 hours and 30 minutes.
Solar cells have been fabricated as follows. 0.5 Ohm-cm, boron doped float-zoned wafers, 100 mm in diameter and 0.8 mm thick, were used as the starting material. The wafers were etched to remove any surface damage. A phosphorus diffusion was made into one side of the wafer (the top side) to a sheet resistance of approximately 50 ohm/square, followed by a boron diffusion into the rear side to about 50 ohm/square. A 100 nm thick oxide was grown on both surfaces, followed by deposition of 50 nm of silicon nitride. Cuts were made into the wafers from the top side using a dicing saw, with the cuts extending to within approximately 50 microns of the rear surface, to create silicon strips. The wafers were then given an etch in potassium hydroxide solution to remove any damage resulting from the cutting process. A phosphorus diffusion was then made into the grooves to about 100 ohm/square. An oxide was grown on the sidewalls of the strips to a thickness of 200 nm. A second set of cuts was then made on a dicing saw into the rear of the wafer, aligned to the first set of cuts and of sufficient depth to create cuts extending all the way through the wafer. The wafers were again immersed in a potassium hydroxide solution to remove any damage from the cuts. An oxide of 275 nm thickness was then grown on the freshly exposed silicon surfaces, increasing the thickness of the sidewall oxide to 300 nm. The silicon nitride layers on the front and rear of the wafer were now removed using phosphoric acid at 165� C. The wafers were then immersed in a solution of 10% hydrofluoric acid in water until the oxide had been removed from the top and rear surfaces of the wafer. At this stage, an oxide of approximately 180 nm thickness was still present on the sidewalls of the silicon strips. The wafers were now metallised. Silver was then electroplated onto the contacts to a thickness of approximately 4 microns. Finally, the silicon strips were cut out using a dicing saw. Silicon strips having thicknesses ranging from less than 100 microns to 250 microns have been made in this way.
One hundred and fifty silicon strips were connected together in series as follows. The strips were butted against each other and placed into a suitable plating jig. They were shorted together by applying silver paint along one edge of the assembly of strips. The cells were then silver plated. This resulted in a silver deposit creating an electrical and physical connection between adjoining strips. Following plating, the edges of the resulting cell to which silver paint had been applied were cut off with a dicing saw. The resulting cell was mounted on glass using heat activated adhesive. A 53 cm2 cell was manufactured in this way. The cell had an efficiency of 13.4% with an open circuit voltage of 92V, a current of 10.3 mA and a fill factor of 73%.
A silicon nitride layer approximately 2 nm thick was deposited at 750� C. on a polished silicon wafer of (111) orientation, using low pressure chemical vapour deposition. A sample was cut out of the wafer and etched in a solution of 1:50 hydrofluoric acid:nitric acid for 150 seconds at 0� C. The sample was encapsulated behind 1 mm thick low iron glass using silicone and its reflectance was measured using a spectrophotometer with an integrating sphere. The sample had a reflectivity of 11% at 900 nm, while a polished encapsulated silicon reference wafer had a reflectivity of 24% and a sample of (100) oriented silicon textured with inverted pyramids had a reflectivity of 8% at the same wavelength. These results indicate that the texturing process is very effective at reducing reflection from the silicon surface. The results also indicate that the texture is likely to be very effective at confining light within the silicon.
Advantages of the Processes of the Present Invention over Prior Art Industrial Silicon Solar Processing Techniques
The processes of the present invention provide a greater surface area of solar cell per unit length of ingot material, compared to prior art methods. For example, next generation crystalline silicon (c-Si) solar cells will be around 0.2 mm thick. Kerf losses are around 0.25 mm, resulting in a total thickness of about 0.45 mm of ingot consumed per wafer. In accordance with the present invention, if strips are cut at a pitch of 0.1 mm from a 1 mm thick wafer, then this provides an effective surface area which is ten times the area of the original wafer, for a consumption of 1.25 mm of ingot. So the amount of ingot consumed per equivalent wafer area would be 0.125 mm and the gain would be a factor of 3.6 (that is, 0.45/0.125). The inclusion of a silicon frame around the periphery of the wafer would reduce this gain slightly. This area gain can be extended further by concentrating the sunlight directed onto solar cells made from the strips.
In the methods of the present invention, a solar cell fabrication process can be carried out while the strips remain attached to the wafer. For each wafer processed, and using the above example, effectively ten times the area of the wafer is being processed, reducing processing costs. In general, the thickness of the wafer should be greater than the sum of the width of each strip and the width of silicon removed in order to achieve a net gain in planar surface area.
Monolithic interconnection results naturally from the processes of the present invention. This is desirable as it lends itself more easily to automated production than the conventional cell interconnection process. Cells can also be connected in series, giving a high voltage, small current device which is also desirable.
The invention also allows very simple, yet highly effective static concentrator designs to be implemented, which allow concentration of sunlight by a factor of two or more. This means that only about one half or less of the surface of a module must be covered in solar cells. There are two basic reasons why solar cells produced by the processes of the present invention are better suited to static concentrator designs than solar cells of the prior art.
The first reason is that cells produced by the processes of the present invention are bifacial—that is, they respond equally well to sunlight impinging on either surface. Standard solar cells of the prior art are not bifacial and only respond to sunlight impinging on one surface. The most effective static concentrator designs require bifacial cells.
The second reason is that cells produced by the processes of the present invention can be very narrow—of the order of 1 mm is typical. The height of static concentrators is directly proportional to the width of the cell. Standard solar cells of the prior art, made from wafers, are typically 10�10 cm2 or larger, and therefore static concentrator systems made with such cells are large and bulky.
Many modifications of the processes described herein with reference to the accompanying drawings will be apparent to those skilled in the art without departing from the scope of the present invention
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|Apr 20, 2010
Owner name: TRANSFORM SOLAR PTY LTD,AUSTRALIA
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