text:
Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
[0001] This application claims priority from provisional application Ser. No. 60/273,112 filed Mar. 2, 2001.BACKGROUND OF THE INVENTION
[0002] The invention relates to the field of relaxed SiGe platforms for high speed CMOS electronics and high speed analog circuits.
[0003] Si CMOS as a platform for digital integrated circuits has progressed predictably through the industry roadmap. The progress is created through device miniaturization, leading to higher performance, greater reliability, and lower cost. However, new bottlenecks in data flow are appearing as the interconnection hierarchy is expanded. Although digital integrated circuits have progressed at unprecedented rates, analog circuitry has hardly progressed at all. Furthermore, it appears that in the near future, serious economic and technological issues will confront the progress of digital integrated circuits.
[0004] The digital and communication chip markets need an enhancement to Si CMOS and the maturing roadmap. One promising candidate material that improves digital integrated circuit technology and introduces new analog integrated circuit possibilities is relaxed SiGe material on Si substrates. Relaxed SiGe alloys on Si can have thin layers of Si deposited on them, creating tension in the thin Si layers. Tensile Si layers have many advantageous properties for the basic device in integrated circuits, the metal-oxide field effect transistor (MOSFET). First, placing Si in tension increases the mobility of electrons moving parallel to the surface of the wafer, thus increasing the frequency of operation of the MOSFET and the associated circuit. Second, the band offset between the relaxed SiGe and the tensile Si will confine electrons in the Si layer. Therefore, in an electron channel device (n-channel), the channel can be removed from the surface or 'buried'. This ability to spatially separate the charge carriers from scattering centers such as ionized impurities and the 'rough' oxide interface enables the production of low noise, high performance analog devices and circuits.
[0005] A key development in this field was the invention of relaxed SiGe buffers with low threading dislocation densities. The key background inventions in this area are described in U.S. Pat. No. 5,442,205 issued to Brasen et al. and U.S. Pat. No. 6,107,653 issued to Fitzgerald. These patents define the current best methods of fabricating high quality relaxed SiGe.
[0006] Novel device structures in research laboratories have been fabricated on early, primitive versions of the relaxed buffer. For example, strained Si, surface channel nMOSFETs have been created that show enhancements of over 60% in intrinsic gm with electron mobility increases of over 75% (Rim et al, IEDM 98 Tech. Dig. p. 707). Strained Si, buried channel devices demonstrating high transconductance and high mobility have also been fabricated (U. Konig, MRS Symposium Proceedings 533, 3 (1998)). Unfortunately, these devices possess a variety of problems with respect to commercialization. First, the material quality that is generally available is insufficient for practical utilization, since the surface of SiGe on Si becomes very rough as the material is relaxed via dislocation introduction. These dislocations are essential in the growth of relaxed SiGe layers on Si since they compensate for the stress induced by the lattice mismatch between the materials. For more than 10 years, researchers have tried to intrinsically control the surface morphology through epitaxial growth, but since the stress fields from the misfit dislocations affect the growth front, no intrinsic epitaxial solution is possible. The invention describes a method of planarization and regrowth that allows all devices on relaxed SiGe to possess a significantly flatter surface. This reduction in surface roughness increases the yield for fine-line lithography, thus enabling the manufacture of strained Si devices.
[0007] A second problem with the strained Si devices made to date is that researchers have been concentrating on devices optimized for very different applications. The surface channel devices have been explored to enhance conventional MOSFET devices, whereas the buried channel devices have been constructed in ways that mimic the buried channel devices previously available only in III-V materials systems, like AlGaAs/GaAs. Recognizing that the Si manufacturing infrastructure needs a materials platform that is compatible with Si, scalable, and capable of being used in the plethora of Si integrated circuit applications, the disclosed invention provides a platform that allows both the enhancement of circuits based on Si CMOS, as well as the fabrication of analog circuits. Thus, high performance analog or digital systems can be designed with this platform. An additional advantage is that both types of circuits can be fabricated in the CMOS process, and therefore a combined, integrated digital/analog system can be designed as a single-chip solution.
[0008] With these advanced SiGe material platforms, it is now possible to provide a variety of device and circuit topologies that take advantage of this new materials system. Exemplary embodiments of the invention describe structures and methods to fabricate advanced strained-layer Si devices, and structures and methods to create circuits based on a multiplicity of devices, all fabricated from the same starting material platform. Starting from the same material platform is key to minimizing cost as well as to allowing as many circuit topologies to be built on this platform as possible.SUMMARY OF THE INVENTION
[0009] Accordingly, the invention provides a material platform of planarized relaxed SiGe with regrown device layers. The planarization and regrowth strategy allows device layers to have minimal surface roughness as compared to strategies in which device layers are grown without planarization. This planarized and regrown platform is a host for strained Si devices that can possess optimal characteristics for both digital and analog circuits. Structures and processes are described that allow for the fabrication of high performance digital logic or analog circuits, but the same structure can be used to host a combination of digital and analog circuits, forming a single system-on-chip.BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a schematic block diagram of a structure including a relaxed SiGe layer epitaxially grown on a Si substrate;
[0011] FIG. 2 is a schematic block diagram of an exemplary structure showing that the origin of the crosshatch pattern is the stress fields from injected misfit dislocations;
[0012] FIG. 3 is a table showing surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates;
[0013] FIGS. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention;
[0014] FIGS. 5A-5D are schematic diagrams of the corresponding process flow and layer structure for a surface channel FET platform in accordance with the invention;
[0015] FIGS. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention;
[0016] FIGS. 7A-7D are schematic diagrams of a process flow for a surface channel MOSFET in accordance with the invention;
[0017] FIGS. 8A and 8B are schematic block diagrams of surface channel devices with protective layers;
[0018] FIGS. 9A and 9B are schematic block diagrams of surface channel devices with Si layers on Ge-rich layers for use in silicide formation;
[0019] FIG. 10 is schematic diagram of a buried channel MOSFET after device isolation in accordance with the invention;
[0020] FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention;
[0021] FIGS. 12A-12D are schematic diagrams of a process flow in the case of forming the surface channel MOSFET in the top strained Si layer in accordance with the invention;
[0022] FIGS. 13A-13D are schematic diagrams of a process flow in the case of forming the surface channel MOSFET in the buried strained Si layer in accordance with the invention; and
[0023] FIGS. 14A and 14B are schematic diagrams of surface and buried channel devices with Si1-yGey channels on a relaxed Si1-zGez layer.DETAILED DESCRIPTION OF THE INVENTION
[0024] FIG. 1 is a schematic block diagram of a structure 100 including a relaxed SiGe layer epitaxially grown on a Si substrate 102. In this structure, a compositionally graded buffer layer 104 is used to accommodate the lattice mismatch between the uniform SiGe layer 106 and the Si substrate. By spreading the lattice mismatch over a distance, the graded buffer minimizes the number of dislocations reaching the surface and thus provides a method for growing high-quality relaxed SiGe films on Si.
[0025] Any method of growing a high-quality, relaxed SiGe layer on Si will produce roughness on the surface of the SiGe layer in a well-known crosshatch pattern. This crosshatch pattern is typically a few hundred angstroms thickness over distances of microns. Thus, the crosshatch pattern is a mild, undulating surface morphology with respect to the size of the electron or hole. For that reason, it is possible to create individual devices that achieve enhancements over their control Si device counterparts. However, commercialization of these devices requires injection of the material into the Si CMOS process environment to achieve low cost, high performance targets. This processing environment requires that the material and device characteristics have minimal impact on the manufacturing process. The crosshatch pattern on the surface of the wafer is one limiting characteristic of relaxed SiGe on Si that affects the yield and the ease of manufacture. Greater planarity is desired for high yield and ease in lithography.
[0026] The origin of the crosshatch pattern is the stress fields from the injected misfit dislocations. This effect is depicted by the exemplary structure 200 shown in FIG. 2. By definition, the dislocations must be introduced in order to accommodate the lattice-mismatch between the SiGe alloy and the Si substrate. The stress fields originate at the dislocations, and are terminated at the surface of the film. However, the termination at the surface creates crystal lattices that vary from place to place on the surface of the wafer. Since growth rate can be correlated to lattice constant size, different thicknesses of deposition occur at different points on the wafer. One may think that thick layer growth beyond the misfit dislocations will smooth the layer of these thickness differences. Unfortunately, the undulations on the surface have a relatively long wavelength; therefore, surface diffusion is typically not great enough to remove the morphology.
[0027] FIG. 3 is a table that displays surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates. Note that the as-grown crosshatch pattern for relaxed Si0.8Ge0.2 buffers creates a typical roughness of approximately 7.9 nm. This average roughness increases as the Ge content in the relaxed buffer is increased. Thus, for any SiGe layer that is relaxed through dislocation introduction during growth, the surface roughness is unacceptable for state-of-the-art fabrication facilities. After the process in which the relaxed SiGe is planarized, the average roughness is less than 2 nm (typically 0.57 nm), and after device layer deposition, the average roughness is 0.77 nm with a 1.5 &mgr;m regrowth thickness. Therefore, after the complete structure is fabricated, over one order of magnitude of roughness reduction can be achieved.
[0028] The regrowth device layers can be either greater than or less than the critical thickness of the regrowth layer. In general, in any lattice-mismatched epitaxial growth, thin layers can be deposited without fear of dislocation introduction at the interface. At a great enough thickness, any lattice-mismatch between the film and substrate will introduce misfit dislocations into the regrown heterostructure. These new dislocations can cause additional surface roughness. Thus, if the lattice-mismatch between the regrowth device layers and relaxed SiGe buffer is too great, the effort of planarizing the relaxed SiGe may be lost since massive dislocation introduction will roughen the surface.
[0029] There are two distinct possibilities with respect to the regrowth thickness and the quality of surface. If the regrowth layers are very thin, then exact lattice matching of the regrowth layer composition and the relaxed buffer composition is not necessary. In this case, the surface roughness will be very low, approximately equal to the post-planarization flatness. However, in many applications for devices, the regrowth layer thickness will be 1-2 &mgr;m or more. For a 1% difference in Ge concentration between the relaxed SiGe and the regrowth layer, the critical thickness is approximately 0.5 &mgr;m. Thus, if optimal flatness is desired, it is best to keep the regrowth layer below approximately 0.5 &mgr;m unless excellent control of the uniformity of Ge concentration across the wafer is achieved. Although this composition matching is achievable in state-of-the-art tools, FIG. 3 shows that less precise matching, i.e., within 2% Ge, results in misfit dislocation introduction and introduction of a new crosshatch pattern. However, because the lattice mismatch is so small, the average roughness is still very low, approximately 0.77 nm. Thus, either lattice-matching or slight mismatch will result in excellent device layer surfaces for processing.
[0030] It is also noted that the relaxed SiGe alloy with surface roughness may not necessarily be a uniform composition relaxed SiGe layer on a graded composition layer. Although this material layer structure has been shown to be an early example of high quality relaxed SiGe, there are some disadvantages to this structure. For example, SiGe alloys possess a much worse coefficient of thermal conductivity than pure Si. Thus, for electronic devices located at the surface, it may be relatively difficult to guide the heat away from the device areas due to the thick graded composition layer and uniform composition layer.
[0031] Another exemplary embodiment of the invention, shown in FIGS. 4A-4D, solves this problem and creates a platform for high power SiGe devices. FIGS. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention. The structure is produced by first forming a relaxed uniform SiGe alloy 400 via a compositionally graded layer 402 on a Si substrate 404. The SiGe layer 400 is then transferred to a second Si substrate 406 using conventional bonding. For example, the uniform SiGe alloy 400 on the graded layer 402 can be planarized to remove the crosshatch pattern, and that relaxed SiGe alloy can be bonded to the Si wafer. The graded layer 402 and the original substrate 404 can be removed by a variety of conventional processes. For example, one process is to grind the original Si substrate away and selectively etch to the SiGe, either by a controlled dry or wet etch, or by embedding an etch stop layer. The end result is a relaxed SiGe alloy 400 on Si without the thick graded layer. This structure is more suited for high power applications since the heat can be conducted away from the SiGe layer more efficiently.
[0032] The bond and substrate removal technique can also be used to produce SiGe on insulator substrates, or SGOI. An SGOI wafer is produced using the same technique shown in FIGS. 4A-4D; however, the second substrate is coated with a SiO2 layer before bonding. In an alternative embodiment, both wafers can be coated with SiO2 to enable oxide-to-oxide bonding. The resulting structure after substrate removal is a high quality, relaxed SiGe layer on an insulating film. Devices built on this platform can utilize the performance enhancements of both strained Si and the SOI architecture.
[0033] It will be appreciated that in the scenario where the SiGe layer is transferred to another host substrate, one may still need to planarize before regrowing the device layer structure. The SiGe surface can be too rough for state of the art processing due to the substrate removal technique. In this case, the relaxed SiGe is planarized, and the device layers are regrown on top of the high-quality relaxed SiGe surface.
[0034] Planarization of the surface via mechanical or other physical methods is required to flatten the surface and to achieve CMOS-quality devices. However, the field effect transistors (FETs) that allow for enhanced digital and analog circuits are very thin, and thus would be removed by the planarization step. Thus, a first part of the invention is to realize that relaxed SiGe growth and planarization, followed by device layer regrowth, is key to creating a high-performance, high yield enhanced CMOS platform. FIGS. 5 and 6 show the process sequence and regrowth layers required to create embodiments of surface channel and buried channel FETs, respectively.
[0035] FIGS. 5A-5D are schematic diagrams of a process flow and resulting layer structure in accordance with the invention. FIG. 5A shows the surface roughness 500, which is typical of a relaxed SiGe alloy 502 on a substrate 504, as an exaggerated wavy surface. Note that the substrate is labeled in a generic way, since the substrate could itself be Si, a relaxed compositionally graded SiGe layer on Si, or another material in which the relaxed SiGe has been transferred through a wafer bonding and removal technique. The relaxed SiGe alloy 502 is planarized (FIG. 5B) to remove the substantial roughness, and then device regrowth layers 506 are epitaxially deposited (FIG. 5C). It is desirable to lattice-match the composition of the regrowth layer 506 as closely as possible to the relaxed SiGe 502; however, a small amount of mismatch and dislocation introduction at the interface is tolerable since the surface remains substantially planar. For a surface channel device, a strained Si layer 508 of thickness less than 0.1 &mgr;m is then grown on top of the relaxed SiGe 502 with an optional sacrificial layer 510, as shown in FIG. 5D. The strained layer 508 is the layer that will be used as the channel in the final CMOS devices.
[0036] FIGS. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention. In this structure, the regrowth layers 606 include a lattice matched SiGe layer 602, a strained Si channel layer 608 with a thickness of less than 0.05 &mgr;m, a SiGe separation or spacer layer 612, a Si gate oxidation layer 614, and an optional sacrificial layer 610 used to protect the heterostructure during the initial device processing steps.
[0037] Once the device structure has been deposited, the rest of the process flow for device fabrication is very similar to that of bulk Si. A simplified version of the process flow for a surface channel MOSFET in accordance with the invention is shown in FIGS. 7A-7D. This surface channel MOSFET contains a relaxed SiGe layer 700 and a strained Si layer 702. The device isolation oxide 704, depicted in FIG. 7A, is typically formed first. In this step, the SiN layer 706, which is on top of a thin pad oxide layer 708, serves as a hard mask for either local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Both techniques use a thick oxide (relative to device dimensions) to provide a high threshold voltage between devices; however, STI is better suited for sub-quarter-micron technologies. FIG. 7B is a schematic of the device area after the gate oxide 716 growth and the shallow-source drain implant. The implant regions 710 are self-aligned by using a poly-Si gate 712 patterned with photoresist 714 as a masking layer. Subsequently, deep source-drain implants 718 are positioned using conventional spacer 720 formation and the device is electrically contacted through the formation of silicide 722 at the gate and silicide/germanides 724 at the source and drain (FIG. 7C). FIG. 7D is a schematic of the device after the first level of metal interconnects 1726 have been deposited and etched.
[0038] Since there are limited-thickness layers on top of the entire structure, the removal of surface material during processing becomes more critical than with standard Si. For surface channel devices, the structure that is regrown consists primarily of nearly lattice-matched SiGe, and a thin surface layer of strained Si. Many of the processes that are at the beginning of a Si fabrication sequence strip Si from the surface. If the processing is not carefully controlled, the entire strained Si layer can be removed before the gate oxidation. The resulting device will be a relaxed SiGe channel FET and thus the benefits of a strained Si channel will not be realized.
[0039] A logical solution to combat Si removal during initial processing is to make the strained Si layer thick enough to compensate for this removal. However, thick Si layers are not possible for two reasons. First, the enhanced electrical properties originate from the fact that the Si is strained and thick layers experience strain relief through the introduction of misfit dislocations. Second, the misfit dislocations themselves are undesirable in significant quantity, since they can scatter carriers and increase leakage currents in junctions.
[0040] In order to prevent removal of strained Si layers at the surface, the cleaning procedures before gate oxidation must be minimized and/or protective layers must be applied. Protective layers are useful since their removal can be carefully controlled. Some examples of protective layers for surface channel devices are shown in FIGS. 8A and 8B. FIG. 8A shows a strained Si heterostructure of a relaxed SiGe layer 800 and a strained Si channel layer 802 protected by a surface layer 804 of SiGe. The surface SiGe layer 804 should have a Ge concentration similar to that of the relaxed SiGe layer 800 below, so that the thickness is not limited by critical thickness constraints. During the initial cleans, the SiGe sacrificial layer is removed instead of the strained Si channel layer. The thickness of the sacrificial layer can either be tuned to equal the removal thickness, or can be made greater than the removal thickness. In the latter case, the excess SiGe can be selectively removed before the gate oxidation step to reveal a clean, strained Si layer at the as grown thickness. If the particular fabrication facility prefers a Si terminated surface, a sacrificial Si layer may be deposited on top of the SiGe sacrificial cap layer.
[0041] FIG. 8B shows a structure where a layer 806 of SiO2 and a surface layer 808 of either a poly-crystalline or an amorphous material are used as protective layers. In this method, an oxide layer is either grown or deposited after the epitaxial growth of the strained Si layer. Subsequently, a polycrystalline or amorphous layer of Si, SiGe, or Ge is deposited. These semiconductor layers protect the strained-Si layer in the same manner as a SiGe cap during the processing steps before gate oxidation. Prior to gate oxidation, the poly/amorphous and oxide layers are selectively removed. Although the sacrificial layers are shown as protection for a surface channel device, the same techniques can be employed in a buried channel heterostructure.
[0042] Another way in which conventional Si processing is modified is during the source-drain silicide-germanide formation (FIG. 7C). In conventional Si processing, a metal (typically Ti, Co, or Ni) is reacted with the Si and, through standard annealing sequences, low resistivity suicides are formed. However, in this case, the metal reacts with both Si and Ge simultaneously. Since the silicides have much lower free energy than the germanides, there is a tendency to form a silicide while the Ge is expelled. The expelled germanium creates agglomeration and increases the resistance of the contacts. This increase in series resistance offsets the benefits of the extra drive current from the heterostructure, and negates the advantages of the structure.
[0043] Ti and Ni can form phases in which the Ge is not rejected severely, thus allowing the formation of a good contact. Co is much more problematic. However, as discussed above for the problem of Si removal, a protective layer(s) at the device epitaxy stage can be applied instead of optimizing the SiGe-metal reaction. For example, the strained Si that will become the surface channel can be coated with a high-Ge-content SiGe alloy (higher Ge content than the initial relaxed SiGe), followed by strained Si. Two approaches are possible using these surface contact layers. Both methods introduce thick Si at the surface and allow the conventional silicide technology to be practiced without encountering the problems with SiGe-metal reactions.
[0044] The first approach, shown on a surface channel heterostructure 900 in FIG. 9A, uses a Ge-rich layer 906 thin enough that it is substantially strained. The layer 906 is provided on a strained Si channel layer 904 and relaxed SiGe layer 902. In this case, if a subsequent Si layer 908 is beyond the critical thickness, the compressive Ge-rich layer 906 acts as a barrier to dislocations entering the strained Si channel 904. This barrier is beneficial since dislocations do not adversely affect the silicide process; thus, their presence in the subsequent Si layer 908 is of no consequence. However, if the dislocations were to penetrate to the channel, there would be adverse effects on the device.
[0045] A second approach, shown in FIG. 9B, is to allow a Ge-rich layer 910 to intentionally exceed the critical thickness, thereby causing substantial relaxation in the Ge-rich layer. In this scenario, an arbitrarily thick Si layer 912 can be applied on top of the relaxed Ge-rich layer. This layer will contain more defects than the strained channel, but the defects play no role in device operation since this Si is relevant only in the silicide reaction. In both cases, the process is free from the metal-SiGe reaction concerns, since the metal will react with Si-only. Once the silicide contacts have been formed, the rest of the sequence is a standard Si CMOS process flow, except that the thermal budget is carefully monitored since, for example, the silicide-germanicide (if that option is used) typically cannot tolerate as high a temperature as the conventional silicide. A major advantage of using Si/SiGe FET heterostructures to achieve enhanced performance is the compatibility with conventional Si techniques. Many of the processes are identical to Si CMOS processing, and once the front-end of the process, i.e., the processing of the Si/SiGe heterostructure, is complete, the entire back-end process is uninfluenced by the fact that Si/SiGe lies below.
[0046] Even though the starting heterostructure for the buried channel device is different from that of the surface channel device, its process flow is very similar to the surface channel flow shown in FIGS. 7A-7D. FIG. 10 is a schematic block diagram of a buried channel MOSFET structure 1000 after the device isolation oxide 1016 has been formed using a SiN mask 1014. In this case, the strained channel 1002 on a first SiGe layer 1010 is separated from the surface by the growth of another SiGe layer 1004, followed by another Si layer 1006. This Si layer is needed for the gate oxide 1008 since gate-oxide formation on SiGe produces a very high interface state density, thus creating non-ideal MOSFETs. One consequence of this Si layer, is that if it is too thick, a substantial portion of the Si layer will remain after the gate oxidation. Carriers can populate this residual Si layer, creating a surface channel in parallel with the desired buried channel and leading to deleterious device properties. Thus, the surface layer Si must be kept as thin as possible, typically less than 50 Å and ideally in the range of 5-15 Å.
[0047] Another added feature that is necessary for a buried channel device is the supply layer implant. The field experienced in the vertical direction when the device is turned on is strong enough to pull carriers from the buried channel 1002 and force them to populate a Si channel 1006 near the Si/SiO2 interface 1012, thus destroying any advantage of the buried channel. Thus, a supply layer of dopant must be introduced either in the layer 1004 between the buried channel and the top Si layer 1006, or below the buried channel in the underlying SiGe 1010. In this way, the device is forced on with little or no applied voltage, and turned off by applying a voltage (depletion mode device).
[0048] FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention. The main process steps are shown in the boxes, and optional steps or comments are shown in the circles. The first three steps (1100,1102,1104) describe the fabrication of the strained silicon heterostructure. The sequence includes production of relaxed SiGe on Si, planarization of the SiGe, and regrowth of the device layers. Once the strained heterostructure is complete (1106), MOS fabrication begins with device isolation (1112) using either STI (1110) or LOCOS (1108). Before proceeding to the gate oxidation, buried channel devices undergo a supply and threshold implant (1114), and any protective layers applied to either a buried or surface channel heterostructure must be selectively removed (1116). The processing sequence after the gate oxidation (1118) is similar to conventional Si CMOS processing. These steps include gate deposition, doping, and definition (1120), self-aligned shallow source-drain implant (1122), spacer formation (1124), self-aligned deep source-drain implant (1126), salicide formation (1128), and pad isolation via metal deposition and etch (1130). The steps requiring significant alteration have been discussed.
[0049] One particular advantage of the process of FIG. 11 is that it enables the use of surface channel and buried channel devices on the same platform. Consider FIGS. 12A-12D and FIGS. 13A-13D, which show a universal substrate layer configuration and a process that leads to the co-habitation of surface and buried channel MOSFETs on the same chip. The universal substrate is one in which both surface channel and buried channel devices can be fabricated. There are two possibilities in fabricating the surface channel device in this sequence, shown in FIGS. 12 and 13. The process flows for combining surface and buried channel are similar to the previous process described in FIG. 7. Therefore, only the critical steps involved in exposing the proper gate areas are shown in FIGS. 12 and 13.
[0050] FIGS. 12A and 13A depict the same basic heterostructure 1200,1300 for integrating surface channel and buried channel devices. There is a surface strained Si layer 1202,1302, a SiGe spacer layer 1204,1304, a buried strained Si layer 1206,1306, and a relaxed platform of SiGe 1208,1308. Two strained Si layers are necessary because the buried channel MOSFET requires a surface Si layer to form the gate oxide and a buried Si layer to form the device channel. The figures also show a device isolation region 1210 that separates the buried channel device area 1212,1312 from the surface channel device area 1214,1314.
[0051] Unlike the buried channel device, a surface channel MOSFET only requires one strained Si layer. As a result, the surface channel MOSFET can be fabricated either in the top strained Si layer, as shown in FIGS. 12B-12D, or the buried Si layer channel, as shown in FIGS. 13B-13D. FIG. 12B is a schematic diagram of a surface channel gate oxidation 1216 in the top Si layer 1202. In this scenario, a thicker top Si layer is desired, since after oxidation, a residual strained Si layer must be present to form the channel. FIG. 12B also shows a possible position for the buried channel supply implant 1218, which is usually implanted before the buried channel gate oxide is grown. Since the top Si layer is optimized for the surface channel device, it may be necessary to strip some of the top strained Si in the regions 1220 where buried channel devices are being created, as shown in FIG. 12C. This removal is necessary in order to minimize the surface Si thickness after gate oxide 1222 formation (FIG. 12D), and thus avoid the formation of a parallel device channel.
[0052] When a surface channel MOSFET is formed in the buried strained Si layer, the top strained Si layer can be thin, i.e., designed optimally for the buried channel MOSFET. In FIG. 13B, the top strained Si and SiGe layers are removed in the region 1312 where the surface channel MOSFETs are formed. Because Si and SiGe have different properties, a range of selective removal techniques can be used, such as wet or dry chemical etching. Selective oxidation can also be used since SiGe oxidizes at much higher rates than Si, especially under wet oxidation conditions. FIG. 13C shows the gate oxidation 1314 of the surface channel device as well as the supply layer implant 1316 for the buried channel device. Finally, FIG. 13D shows the position of the buried channel gate oxide 1318. No thinning of the top Si layer is required prior to the oxidation since the epitaxial thickness is optimized for the buried channel device. Subsequent to these initial steps, the processing for each device proceeds as previously described.
[0053] Another key step in the process is the use of a localized implant to create the supply layer needed in the buried channel device. In a MOSFET structure, when the channel is turned on, large vertical fields are present that bring carriers to the surface. The band offset between the Si and SiGe that confines the electrons in the buried strained Si layer is not large enough to prevent carriers from being pulled out of the buried channel. Thus, at first, the buried channel MOSFET would appear useless. However, if enough charge were present in the top SiGe layer, the MOSFET would become a depletion-mode device, i.e. normally on and requiring bias to turn off the channel. In the surface/buried channel device platform, a supply layer implant can be created in the regions where the buried channel will be fabricated, thus easing process integration. If for some reason the supply layer implant is not possible, note that the process shown in FIG. 11 in which the surface channel is created on the buried Si layer is an acceptable process, since the dopant can be introduced into the top SiGe layer during epitaxial growth. The supply layer is then removed from the surface channel MOSFET areas when the top SiGe and strained Si layers are selectively etched away.
[0054] In the processes described in FIGS. 10, 12 and 13, it is assumed that the desire is to fabricate a buried channel MOSFET. If the oxide of the buried channel device is removed, one can form a buried channel device with a metal gate (termed a MODFET or HEMT). The advantage of this device is that the transconductance can be much higher since there is a decrease in capacitance due to the missing oxide. However, there are two disadvantages to using this device. First, all thermal processes after gate definition have to be extremely low temperature, otherwise the metal will react with the semiconductor, forming an alloyed gate with a very low, or non-existent, barrier. Related to this issue is the second disadvantage. Due to the low thermal budget, the source and drain formation and contacts are typically done before the gate definition. Inverting these steps prevents the gate from being self-aligned to the source and drain, thus increasing the series resistance between the gate and the source and drain. Therefore, with a carefully designed buried channel MOSFET, the self-aligned nature can be a great advantage in device performance. Another benefit of the MOSFET structure is that the gate leakage is very low.
[0055] The combination of buried n-channel structures with n and p type surface channel MOSFETs has been emphasized heretofore. It is important to also emphasize that in buried n-channel devices as well as in surface channel devices, the channels need not be pure Si. Si1-yGey channels can be used to increase the stability during processing. FIGS. 14A and 14B are schematic diagrams of surface 1400 and buried 1450 channel devices with Si1-yGey channels 1402 on a relaxed Si1-zGez layer 1404. The devices are shown after salicidation and thus contain a poly-Si gate 1410, gate oxide 1408, silicide regions 1412, spacers 1414, and doped regions 1416. In the surface channel device 1400, a thin layer 1406 of Si must be deposited onto the Si1-yGey layer 1402 to form the gate oxide 1408, as previously described for buried channel devices. In the buried Si1-yGey channel device 1450, the device layer sequence is unchanged and consists of a buried strained channel 1402, a SiGe spacer layer 1418, and a surface Si layer 1420 for oxidation.
[0056] To maintain tensile strain in the channel of an nMOS device, the lattice constant of the channel layer must be less than that of the relaxed SiGe layer, i.e., y must be less than z. Since n-channel devices are sensitive to alloy scattering, the highest mobilities result when the Ge concentration in the channel is low. In order to have strain on this channel layer at a reasonable critical thickness, the underlying SiGe should have a Ge concentration in the range of 10-50%.
[0057] Experimental data indicates that p channels are less sensitive to alloy scattering. Thus, surface MOSFETs with alloy channels are also possible. In addition, the buried channel devices can be p-channel devices simply by having the Ge concentration in the channel, y, greater than the Ge concentration in the relaxed SiGe alloy, z, and by switching the supply dopant from n-type to p-type. This configuration can be used to form Ge channel devices when y=1 and 0.5<z<0.9.
[0058] With the ability to mix enhancement mode surface channel devices (n and p channel, through implants as in typical Si CMOS technology) and depletion-mode buried channel MOSFETs and MODFETs, it is possible to create highly integrated digital/analog systems. The enhancement mode devices can be fabricated into high performance CMOS, and the regions of an analog circuit requiring the high performance low-noise depletion mode device can be fabricated in the buried channel regions. Thus, it is possible to construct optimal communication stages, digital processing stages, etc. on a single platform. These different regions are connected electrically in the backend of the Si CMOS chip, just as transistors are connected by the back-end technology today. Thus, the only changes to the CMOS process are some parameters in the processes in the fabrication facility, and the new material, but otherwise, the entire manufacturing process is transparent to the change. Thus, the economics favor such a platform for integrated Si CMOS systems on chip.
[0059] Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
1. A method of fabricating a semiconductor structure comprising:
- providing a relaxed Si1-xGex layer on a substrate;
- providing a Si1-yGey layer on said Si1-xGex layer;
- providing a Si1-wGew layer on said Si1-yGey layer;
- providing a Si layer on said Si1-wGew layer, wherein
- surface channel and buried channel devices are integrated on said semiconductor structure.
2. The method of claim 1, wherein a carrier channel of a surface channel device is provided in either said Si layer or said Si1-yGey layer.
3. The method of claim 1, wherein the semiconductor structure is undoped.
4. The method of claim 1, wherein y<x.
5. The method of claims 2 or 4, wherein y is approximately 0.
6. The method of claim 1 further comprising planarizing at least one surface.
7. The method of claim 1, wherein the substrate comprises Si.
8. The method of claim 1, wherein the substrate comprises Si with a layer of SiO2.
9. The method of claim 1, wherein the substrate comprises a graded composition SiGe layer on Si.
10. The method of claim 9, wherein the substrate further comprises a uniform composition Si1-zGez layer on said graded composition layer.
11. The method of claim 10, wherein z is approximately equal to x.
12. The method of claim 11, wherein the surface of the substrate is planarized.
13. The method of claim 1, wherein the substrate comprises a uniform Si1-zGez layer on Si.
14. The method of claim 13, wherein z is approximately equal to x.
15. The method of claim 14, wherein the surface of the substrate is planarized.
16. The method of claim 13, wherein the Si1-zGez/Si structure is formed through wafer bonding.
17. The method of claim 13 further comprising a SiO2 layer between the uniform Si1-zGez layer and the Si.
18. The method of claim 17, wherein z is approximately equal to x.
19. The method of claim 18, wherein the surface of the substrate is planarized.
20. A method of fabricating a semiconductor structure comprising:
- providing a relaxed Si1-xGex layer;
- planarizing said relaxed Si1-xGex layer; and
- providing regrown device layers on said planarized relaxed Si1-xGex layer, wherein
- surface channel and buried channel devices are integrated on said semiconductor structure.
21. The method of claim 20, wherein the regrown device layers include a Si1-yGey layer of thickness h; a Si1-wGew layer; a Sii-uGeu layer having supply dopants; and a Si layer.
22. The method of claim 21, wherein h is approximately 0.
23. The method of claim 21, wherein w<x and the supply dopants are n-type.
24. The method of claim 20, wherein a carrier channel of a surface channel device is provided in either said Si layer or said Si1-wGew layer.
25. A method of fabricating an integrated circuit comprising:
- integrating at least one surface channel MOSFET and at least one buried channel FET on a relaxed Si1-xGex layer that is provided on a substrate.
26. The method of claim 25, wherein the surface channel MOSFET comprises a Si1-yGey layer with y<x; a Si layer of thickness h; a gate dielectric; and a highly conductive gate layer.
27. The method of claim 26, wherein h and y are approximately 0.
28. The method of claim 27, wherein the buried channel FET comprises a Si1-yGey layer with y<x; a Si1-wGew layer; a Si layer; a gate dielectric; and a highly conductive gate layer.
29. The method of claim 28, wherein y is approximately 0.
30. The method of claim 27, wherein the buried channel FET comprises a Si1-yGey layer with y<x; a Si1-wGew layer; a Si layer; and a highly conductive gate layer.
31. The method of claim 30, wherein y is approximately 0.
32. The method of claim 25, wherein the surface channel MOSFET comprises a Si1-yGey layer with y>x, a Si1-wGew layer; a Si layer; a gate dielectric; and a highly conductive gate layer.
33. The method of claim 32, wherein the buried channel FET comprises a Si1-yGey layer with y>x; a Si1-wGew layer; a Si layer; a gate dielectric; and a highly conductive gate layer.
34. The method of claim 33, wherein y is approximately 1.
35. The method of claim 32, wherein the buried channel FET comprises a Si1-yGey layer with y>x; a Si1-wGew layer; a surface Si layer; a highly conductive gate layer.
36. The method of claim 35, wherein y is approximately 1.
37. The method of claim 25, wherein the relaxed Si1-xGex further comprises at least one planarized surface.
38. A method of fabricating a semiconductor circuit on a heterostructure, said heterostructure including a relaxed Si1-xGex layer on a substrate, a Si1-yGey layer on said relaxed Si1-xGex layer, a Si1-wGew layer on said Si1-yGey layer, and a Si layer on said Si1-wGew layer, said method comprising:
- integrating surface channel and buried channel devices on said heterostructure.
39. The method of claim 38, wherein a carrier channel of a surface channel device is provided in either said Si layer or said Si1-yGey layer.
40. The method of claim 38, wherein the semiconductor structure is undoped.
41. The method of claim 38, wherein y<x.
42. The method of claims 39 or 41, wherein y is approximately 0.
43. The method of claim 38 further comprising planarizing at least one surface.
44. The method of claim 38, wherein the substrate comprises Si.
45. The method of claim 38, wherein the substrate comprises Si with a layer of SiO2.
46. The method of claim 38, wherein the substrate comprises a graded composition SiGe layer on Si.
47. The method of claim 46, wherein the substrate further comprises a uniform composition Si1-zGez layer on said graded composition layer.
48. The method of claim 47, wherein z is approximately equal to x.
49. The method of claim 48, wherein the surface of the substrate is planarized.
50. The method of claim 38, wherein the substrate comprises a uniform Si1-zGez layer on Si.
51. The method of claim 50, wherein z is approximately equal to x.
52. The method of claim 51, wherein the surface of the substrate is planarized.
53. The method of claim 50, wherein the Si1-zGez/Si structure is formed through wafer bonding.
54. The method of claim 50 further comprising a SiO2 layer between the uniform Si1-zGez layer and the Si.
55. The method of claim 54, wherein z is approximately equal to x.
56. The method of claim 55, wherein the surface of the substrate is planarized.
57. A method of fabricating a semiconductor circuit on a heterostructure, said heterostructure including a planarized relaxed Si1-xGex layer on a substrate, and regrown device layers on said planarized relaxed Si1-xGex layer, said method comprising:
- integrating surface channel and buried channel devices on said heterostructure.
58. The method of claim 57, wherein the regrown device layers include a Si1-yGy layer of thickness h; a Si1-wGew layer; a Si1-uGeu layer having supply dopants; and a Si layer.
59. The method of claim 58, wherein h is approximately 0.
60. The method of claim 58, wherein w<x and the supply dopants are n-type.
61. The method of claim 57, wherein a carrier channel of a surface channel device is provided in either said Si layer or said Si1-wGw layer.
Type: Application
Filed: Jul 16, 2001
Publication Date: Sep 5, 2002
Patent Grant number: 6900103
Inventor: Eugene A. Fitzgerald (Windham, NH)
Application Number: 09906533
International Classification: H01L021/8238; H01L021/28; H01L021/44;


text:
Re: "." problems
Hi there,
I've noticed that the behavior of the "." operator in viEmu for VC++ differs significantly from that of both vi and vim, sometimes in ways that seem clearly buggy. In particular, I find that "."ing O and A edits don't seem to add any of the text I've written. Is anyone else experiencing this? Is there a workaround?

subset: commoncrawl


text:
Jessie was very much enjoying the sand, sea & waves.
When you saw the sea, you couldnt wait
and jumped in the water.
Enjoying the waves. You were having
so much fun and amused yourself
quite a long time in the water.
When you finally got out
you did catch the last sunbeams
to dry in the sun,
You are so adorable.
Credits to:
Template: Anna Aspnes Foto Blendz Layered Template No 6
Papers: Lynn Grieveson flitter-kit
Wordart (signs of summer): Ali Edwards June 7 Journaling Challenge
Thanks for looking!


text:
Cases of eye infections due to contact lenses are increasing despite being easily avoidable! Learn more about the risks and take a look at some contact lens care tips.
A recent report of Jessica Greaney, an 18 year old student being admitted to hospital with Acanthamoeba keratitis has spread across the internet warning of this contact lens parasite. Moorfield Eye Hospital, The BBC reports, have highlighted an increase of this particular eye infection
Acanthamoeba are naturally occurring tiny, one-celled animals called amoeba which can attach to the contact lens. If the parasite infects the eye, this results in Acanthamoeba keratitis, which attacks the cornea and is incredibly difficult to treat. It can sometimes require a corneal transplant surgery - Greaney had to remain awake for a week while doctors attempted to treat the infection with eye drops rather than surgery.
Prevention is therefore vital, making good lens care essential.
Acanthamoeba are commonly found in water, from soil & sewage systems to hot tubs and tap water. Most cases (approximately 90%) of Acanthamoeba keratitis involve contact lens wearers- a simple drop of water could be the cause, which is the suspected source of Greaney's infection.
Contact lens wearers generally have a higher risk of eye infections as micro-organisms such as bacteria and fungi can stick to the lens, causing an eye infection. Symptoms of a possible infection include irritation, discharge/tearing, swelling, red eyes, pain, blurring and vision loss, and even photophobia (light sensitivity).
Symptoms of Acanthamoeba keratitis are similar, with the additional signs of pain after the removal of your lenses and the feeling that there's something in your eye. If you experience any of the above, it's important to seek medical advice - the sooner you are treated, the less likely you are to have permanent damage.
Good lens hygiene, application, and eye care can greatly reduce your risks of an infection and discomfort. To help you keep your eyes healthy and infection free, we have put together a quick guide to contact lens best practices:
Cleaning & Solutions
- Use fresh solution for overnight storage and never re-use or top up the solution- it should always be discarded and replaced with fresh solution
- Clean your storage case with solution and air dry after each use – replace the case regularly (atleast once in 3 months)
- Always discard solutions & lenses that have passed their expiry date
- Keep a storage case and small bottle of solution with you for emergency use
- Only use the solutions prescribed/specified by your eye care practitioner, don't switch or mix brands unless advised this is ok
- Don't decant your solution into smaller containers, this could lead to contamination of the solution
- Only use your solution to wet the lens, water and saliva are not safe alternatives and can risk an eye infection
- Never use water to clean your lenses or their case – water can contain bugs that are harmful and can cause dangerous infections (see above)
Lens Application
- Always wash and dry your hands thoroughly with soap and water then rinse and dry them with a clean lint-free towel before handling your lenses
- Insert lens before applying make-up and remove them before taking it off
- Avoid contact with your fingernails, both with the lens and your eye
- Don't mix your left and right lenses – try inserting and removing the same lens first
- Always check the lens is not damaged or inside out before inserting
- Always remove your lenses before sleeping unless instructed otherwise
- Apply hairspray, deodorant or spray cologne/perfume before putting your lenses, make sure the spray has settled before insertion to avoid contaminating the lens
General Good Practice
- Never ignore the warning signs of infection, always seek medical advice
- Avoid contact with water when wearing your lenses, i.e. don't swim or shower with lenses in
- Seek advice from your eye care practitioner before using eye drops (other than the lubricant drops you've been recommended) as they are known to interact with contact lenses
- Avoid wearing your lenses when you have the flu or a cold
- Go for periodic examinations, usually annually, for a check-up and re-evaluation of your lenses
Learn more about the different types of contacts to find which lens is suited to you.


text:
Celebrating the living Roman Way and the legacy of the Roman world. For current discussions, visit us at [societas-via-romana] on Google Groups.
Moderator: Aldus Marius
"In the name of the Urban Prefect I demand that -"
"Aldus Marius!" exclaimed the tribune. "What, by Dis, are you doing here? Who are these people?"
Marius wrote:if you're quite determined to tackle a Tar Baby, we will definitely need to stop by the insula. Castra Vetera, I call it, and for good reason. You see, I rent to other 'old soldiers'. ...if it's 'strength' we want, all we'll need is a contubernium of my tenants."
Marius wrote:He could be any stripling lad, anywhere. Stripling lass, for that matter, you know that! ... You really want us to try to chase him down, one out of so many in this town? We'll probably have all the 'fun' we can handle if we follow Paulus home..."
Formosus wrote:"... Otherwise we all might have spent the night at the Mamertine Hotel, hè ?' ... Reminds me of the old times, when we served together at the Walls in the VI Invictrix....
"Except, of course, sir,' adressing Iohannes, ' we had some real adversaries there. Blue-faced Picts. Craziest people in the world, those Picts. Pretty useless in a regular battle, but fierce fighters man on man. No match of course for our friend Marius here. Once, when on a fouraging party, he was suddenly set upon by three of those brutes in what we thought was an abandoned farmstead. I tell you, before any of us others had the time to come to his rescue, he had sent the three of them to join their forefathers, single-handedly. And not a scratch on him. Not even a sweat. But, surely, you know what kind of man he is, sir, you seem to know him pretty well.'
Formosus to Marius wrote:"You haven't introduced me yet to our mutual friend, properly, Marius -- if I may be so bold as to call you my friend, sir; because, as far as I am concerned, anybody who is a friend of him, is a friend of mine -- "
Formosus, continuing wrote: "... and he has already layed out such a spendid entertainment for us !"
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text:
Size: 330 ml
Kris Boelens family run brewery from Belsele essentially started brewing in 1993 at a time when the mini revival of Belgian beer was in full swing. Towns and villages were tired of standing by and watching the conglomerates like Heineken and InBev pick off their historic family run businesses. The Boelens story though wasn't a particularly new one – Kris Boelens can trace his brewing family tree right back to his great grandfather!
The Boelens brewery actually began its life in Lokeren in the 19th Century, a dozen miles away from the town of Belsele, where the family opened another brewery called De Meester. The owner would eventually pass away leaving his wife with a business she was ill-equipped to run. As she was also the sister of the brewer of the Boelens brewery she sought help from the family. It would be Henri Boelens, (her nephew, and Kris Boelens grandfather) who had trained as a brewer who joined his aunt in Belsele to take the business venture on. Henri eventually decided to rename the Belsele brewery Boelens; and it was in this very building that the current Boelens brewery is still based.
At that time the brewery was providing for seventeen pubs and inns in the town, which considering it only had a population of just under two thousand was pretty impressive, however fortune was to turn sour for the family run business in the shape of the German invasion during World War I. The systematic removal of all copper from Belgian breweries meant that the Boelens family had to choose another means of survival. They gained agreement from the German army to change the nature of their business into the distribution of existing beer, and thus brewing stopped, and wouldn't start again until 1993 where we begun our little tale.
The Santa Bee, or the Kerstbier as it is more often known is unsurprisingly the Boelens Christmas offering. It is a dark tasty brew, very much in the typical Christmas beer genre. It poured a heavy chocolate brown with a thick rich head and reminded me somewhat of the Sainte-Monon Brune (#55). I'm definitely growing to like this little brewery who have yet to disappoint me on my journey. There's also plenty more in the cellar to come.


text:
UH Hilo receives National Science Foundation award to lead Islands of Opportunity Alliance
Partnership will help to increase number of underrepresented students in Hawaii and the Pacific to receive degrees in STEM areasUniversity of Hawaiʻi
Dan Brown, (808) 974-7468
Islands of Opportunity Alliance
HILO, Hawaiʻi —The University of Hawaiʻi at Hilo has been selected to serve as the lead institution for the National Science Foundation's newly awarded Islands of Opportunity Alliance, part of the Louis Stokes Alliance for Minority Participation (LSAMP) program.
UH Hilo will work collaboratively with 19 institutions throughout Hawaiʻi and the Pacific to increase the overall number of underrepresented students receiving bachelor degrees in the areas of science, technology, engineering and math (STEM). Alliance member institutions include UH Hilo, UH Mānoa, UH West Oahu, Chaminade University, the University of Guam, Hawaiʻi Pacific University, the community colleges of the UH system, American Samoa Community College, Guam Community College, College of the Marshall Islands, Northern Marianas College, College of Micronesia and Palau Community College.
The Islands of Opportunity Alliance's key leadership team consists of UH Hilo Chancellor Rose Tseng, who will serve as principal investigator; Dr. Dan Brown serving as program director; and Carmen Perez-Frayne serving as program manager.
"As a university that has always valued diversity and provided education for the underrepresented in society, the University of Hawaiʻi at Hilo is privileged and honored to take the lead in the Islands of Opportunity Alliance," said Tseng. "This program will play a vital role in bringing a culturally relevant education in the STEM disciplines to the people of the Pacific Basin."
Launched in 1991, the main goal of LSAMP is to encourage and facilitate access to careers in STEM fields for underrepresented populations. More specifically, NSF hopes to encourage these students to enroll in and complete baccalaureate programs in STEM fields, as well as to continue on to graduate studies in these fields. The LSAMP Program began with grants to six multi-institution collaborative efforts called Alliances. Today, there are 34 Alliances with more than 450 participating institutions throughout the country, with the Islands of Opportunity Alliance being the newest addition.
The Islands of Opportunity Alliance plans to build upon the successes of past and current LSAMP Programs throughout the country, utilizing practices that have been shown to best accomplish the primary goal of increasing graduation rates of underrepresented students in STEM fields. The Alliance has adapted these best practices to the unique cultural and geographic setting of the Pacific region, utilizing the extensive scholarship on cross-cultural communication and on learning styles of islander peoples, and administrative structures that have succeeded in spanning the vast distances between islands.


text:
Product Summary
Scaffolds and Stages can be used for many applications, including painting, theatrical and entertainment, and building maintenance. The sections allow the user to easily add height to an existing tower.
Quick Links
Learn More - Use the Quick Links on this page to navigate quickly through the manufacturer's website or Contact Us directly .
Product Availability and Pricing
Click here for details.
Similar Products
See all our Ladders & Scaffolding products.


text:
On the subject of Football and Marketing, the Super Bowl is fast approaching us and there'll be no doubt on the big effect social media will have this year.
Check out the article from Mashable about the Super Bowl's Social Media Command Center.
An excerpt from the article: "a fan won't need to tweet, "where can I find parking?" to get help; Raidious operatives will be able to pick up on a general phrase such as "parking sucks" to offer assistance." <–WOW!


text:
Speed and power of the motor at users option nema 17 57bygh hybrid stepper motor
1.How could you help me select an appropriate motor solution for my application?A:The absolute minimum information required to properly select a motor solution is the supply voltage, available continuous and peak current, load torque, speed at load, and desired motor technology (brush or brushless). To be sure, the more application information you can provide, the more accurate and exact motor we can offer or quote to you. 2.How do I calculate the rated speed or the speed at a specific torque for a motor or gearmotor?A:The output speed for a motor or gearmotor is given by the equation below: w = [VS - (I x Rmt)] / (KE x N)Wherew = SpeedVS = Supply VoltageI = Current (Obtained from previous equation)Rmt = Motor Terminal ResistanceKE = Back-EMF ConstantN = Gear Ratio (Equals 1 if there is no gearbox)3.What environmental considerations are there?A:Typical environmental temps for the motor should be in a low humidity environment with an ambient temperature range of –20 C to +50 C. BLDC motors do have IP ratings associated to them and limited customization can be done to increase the IP rating. If severe conditions require IP ratings of IP54 or higher, a customized motor construction is required to accommodate this need. 4.Should I use brushless motor or brush motor in my application?A:It should be important to decide when it comes to determining which motor you will need for whatever application or project you are realizing, and your choice will depend on a variety of factors. Some major issues you will need to consider are target cost, amount of power you will need and how long you need it to last. If you have a project or application where you will only need a motor for short term use or light daily duty, you may prefer a cheaper one that may wear out more quickly. If your job requires a motor that will last as long as possible, you will probably want to consider a BLDC motor, for reasons which will become apparent.5.What is a brushless motor?A:A Brushless DC (BLDC) motor is a rotating electric machine where the stator is a classic three-phase stator like that of an induction motor and the rotor has surface-mounted permanent magnets. BLDC motors often incorporate either internal or external position sensors to sense the actual rotor position or the position can be detected without sensors. The BLDC motor is driven by rectangular voltage strokes coupled with the given rotor position. The generated stator flux interacts with the rotor flux, which is generated by a rotor magnet, defines the torque and thus speeds of the motor. The voltage strokes must be properly applied to the two phases of the three-phase winding system so that the angle between the stator flux and the rotor flux is kept close to 90° to get the maximum generated torque. Due to this fact, the motor requires electronic control for proper operation.6.What is a brush dc motor?A:Brush DC Motor provides precision control of speed, driven by a direct current. Noted for a particularly high ratio of torque to inertia, the Brush DC Motor has the potential to supply three to four times more torque than its rated torque. The Brush DC Motor consists of six different major components: the shaft, armature/rotor, commutator, stator, magnets, and brushes. The Brush DC Motor offers stable and continuous current, using rings to power a magnetic drive that operates the motor's armature. 7.What is the lifetime of brush motor?A:This is a tricky question to answer in a short paragraph. The life of the brushes, bearings, and gearbox (if used) all play an important role in the longevity of a Brush DC Motor. Most commonly, Brush DC Motor life expectancies range from 1,000 to 5,000 hours of operation, although actual service life varies.Brush DC Motor design, operating current, speed, voltage, rotation direction, duty cycle and other conditions are all contributing factors.
2018New high speed torque 2 phase NEMA24 closed loop stepper motor made in China


text:
Placenta previa is a placenta that has grown low in the uterus,
partially or fully over the opening to the birth canal (cervix). Placenta
previa can be dangerous during labor and delivery, when it is most likely to
cause severe placental bleeding that can be life-threatening to the mother or
The amount of the cervix that is covered by the placenta may be
slight (marginal), moderate (partial), or complete (total). Unless a placenta
previa is only marginal, a surgical delivery (cesarean section) is needed to
prevent severe placental bleeding.
A woman's risk for placenta previa increases with each pregnancy,
cesarean section, uterine procedure that scars the uterus, or previous placenta
previa. Smoking, cocaine use, and advancing age also increase placenta previa
Last Revised:
February 3, 2012
Healthwise Staff
Medical Review:
Sarah Marshall, MD - Family Medicine & William Gilbert, MD - Maternal and Fetal Medicine
This information does not replace the advice of a doctor. Healthwise, Incorporated disclaims any warranty or liability for your use of this information. Your use of this information means that you agree to the Terms of Use. How this information was developed to help you make better health decisions.
To learn more visit Healthwise.org
© 1995-2012 Healthwise, Incorporated. Healthwise, Healthwise for every health decision, and the Healthwise logo are trademarks of Healthwise, Incorporated.


text:
What is a Notre Dame man? When I asked a friend and teammate of Toryan's to describe who he is, he pretty much defined exactly that: 'Toryan is as passionate as they come. What you see is what you get. Loyal to those he calls friends and family. He wants to impact those around him and create a positive change in the world. He isn't afraid to "rock the boat." He stands up for what he believes in. He is serious, but doesn't take things too seriously. He enjoys life.'
Toryan Smith, son of Charles Smith, a Georgia Bulldogs football player and assistant high school football coach at Rome High School, decided not to following in his father's footsteps and play at hometown favorite UGA but to instead travel north and don the gold helmet of the Fighting Irish of Notre Dame. During his time at Notre Dame, he not only impacted the Irish defense but the special teams squad as well as a hard-hitting inside linebacker who loved the contact and physical aspect of the game. What is Toryan up to these days? Come with me and walk the journey of Toryan Smith.
Q: After growing up in Rome, Georgia, how did you end up playing football at Notre Dame and not near home at UGA?
A: "When I was making the decision whether or not I was coming out of SEC country, it really came down to the invitation that I received from Notre Dame. I was really sold on Notre Dame and what it had to offer. The biggest selling point? Give us four years and we'll give you 40. The '40 years' pitch was what got me. Not only that, but I also felt so comfortable when I made my visit to South Bend, I knew it was where I wanted to be. I was so excited about going to Notre Dame that I literally could not sleep at night — that's what ND does to you. My host during my visit was Darius Walker, another Georgia boy — he helped to reassure me that the transition from Georgia to South Bend was doable. I received offers from every school in the SEC but my top four schools were Alabama, Florida, Michigan, and Notre Dame."
Q: Do you think starting players as freshmen is a good thing or a bad thing?
A: "I think you can look at starting players as freshmen two ways. First,I definitely think starting players in their first year can be a positive experience. Most of all it depends on whether or not the player is ready. If they are ready to contribute, I see no problem starting them right away. In the long run, as a team, you want to have enough depth that you don't HAVE to start players as freshmen. I think if your team is in the position that you have to start guys as freshmen, especially if they are not quite ready, then that can be a negative experience and you can be doing a disservice to your players and team. Being thrust into such a situation without the adequate preparation can be very damaging.
There are so many expectations that a player is under to perform, to handle the pressure, and to succeed; not only from the coaching staff but also from the fans and the alumni. If they are not ready to handle those expectations,the resulting experience can affect their ability to succeed in the long run. If you look at a team like Alabama, they rarely start freshmen players, but that is because they have developed the depth that they need to not have to start them right away. That is the ideal situation for a team to be in. If they are ready, though, it can be an empowering experience."
Q: What is your best Notre Dame football memory?
A: "My best Notre Dame football memory was playing Michigan State in East Lansing my freshman year (2006).
"My freshman year we played Michigan State on the road and came from 21 points behind to beat MSU. That's when I really felt the magic of Notre Dame. It was a big-time game and we had a quarterback competing for the Heisman; simply put, it was an epic game, an instant classic. I was just getting used to playing football, the hectic schedule, balancing football and class work. That game really solidified to me that I was an integral part of a big-time football program."
Q: What is your best football road trip experience?
A: "My best road trip experience at Notre Dame was playing UCLA at the Rose Bowl. We were having a rough season up to that point and hadn't won a game yet, but traveling to Los Angeles was unbelievable. We stayed at the Beverly Hilton, were living the high life in LA, and we upset UCLA on its home turf. It was the first win of our season, on ABC, and in primetime at the Rose Bowl. It was also my first start of that season. Definitely a road trip that I won't soon forget."
Q: What was it like playing for head coach Charlie Weis? How did Weis change during the time you were there?
A: "It was a great experience playing for Coach Weis. He was a great X's and O's coach. He was an NFL-style coach and was very business-like in his coaching mentality and how he handled the ups and downs throughout the season. I think in Coach Weis' first two years everything really clicked. We had an experienced group of players and went to two BCS games. Then in Coach Weis' third year we had a new quarterback and a young team and went 3-9 and that is when the pressure started. For some reason we just were not able to deal with the ups and downs and the challenges that were put in front of us. Coach Weis did a great job at preparing us for life with his business-like style of coaching. I will always have his back because he gave me the opportunity to go to Notre Dame."
Q: Were you expecting to get drafted to play in the NFL? What was that experience like?
A: "I wasn't expecting to be selected in the NFL draft being that I was predominately a backup player. I was not on the field with enough consistency for people to really see what I could do. I played through three different defensive coordinators and that didn't help either. I tried out at the Pro Day and had a few calls but couldn't get anyone to make an offer. At that point I just wanted to get into the business world and make something of myself. The whole process of trying out for the NFL was amazing. I got to go down and do some serious NFL training, really body-specific training. I learned a great deal about my genetic make-up and learned a lot about my body and how it works/what it can do, and I really enjoyed going through the NFL workouts. I also got to see another side of the NFL: the business side. You have to be able to ride the ups and downs, work through the pain, and maintain your sanity to survive and succeed in the NFL. What I also realized is that this applies to the rest of life as well. The NFL at its core is just another business like anything else!"
Q: What was your biggest challenge as a Notre Dame student-athlete? How did Notre Dame prepare you for life after college?
A: "My biggest challenge was being able to balance the academics and the athletics all at once. The endless hours each week just preparing for football and then on top of that you add the 25-30 hours in the classroom, homework, studying for tests, and being expected to perform at a high level in both arenas. There is such a high standard at Notre Dame in both athletics and academics. Notre Dame would never let you jeopardize your academic goals in order to achieve your athletic ones. It was not a tradeoff, it was not an either/or situation, it was always both. Most of the students at Notre Dame were either valedictorians of their class or big-time athletes. There were no tiny fish in the sea at Notre Dame — it was a very competitive environment all around.
Being able to perform under such high pressure and intense scrutiny really molded me into a person who can handle just about anything. If I can perform in front of 80 thousand people, being instructed by three different coaches, being hit by my opponent, then I can perform anywhere. Being able to handle all of that pressure and still perform prepared me to face just about any work situation placed in front of me. The hardest part of my day these days is waking up. If I can wake up; physically, emotionally, and mentally, I can accomplish anything. Notre Dame shaped me into the person I am today and this helps me take myself to the next level."
Q: Where did life take you after football?
A: "After graduation I moved straight from South Bend to Los Angeles, California. That is where I wanted to go so I took a business management position with a tobacco company, Commonwealth Altadis, and my territory was in Ventura County and stretched from Santa Barbara to Santa Monica. My title was account manager and I was responsible for the entire business segment — I was 100% in control of the business. I was leery about selling tobacco but it was a good business. I negotiated the deals with the chain accounts and worked with the purchasing managers of stores like 7-Eleven, Super K, Wal-Mart, and Albertsons to make sure our products were on their shelves. It was fun. I looked forward to doing it every day. And I loved living on the coast — I almost felt that I was cheating by living somewhere that the weather was so good all of the time."
"In April of 2013 I decided to start a not-for-profit with some of my friends called the Bridges Society of America. It is what I really want to get into and so over the last nine months we've been spreading the word and are getting ready to eventually expand and launch it as a nationwide program."
Bridges Society of America (BSA) is a Kansas City, Missouri, based non-profit organization wholly committed to developing the character of young men in Kansas City's urban center as well as young men across the United States. BSA acknowledges and appreciates the myriad of challenges facing disadvantaged youth and recognizes the pivotal role male mentors play in fostering the development of qualities paramount to a young man's success in 21st century America. BSA's mission statement proudly pledges to "help young men in urban areas across America build professional and social relationships that help them achieve their academic and professional goals." The overarching theme is to employ a vast network of like-minded professionals in an effort to empower young men all over the country in creating their own destinies.
"We are going into urban neighborhoods to connect young men with their communities. We are teaching them how to network in order to connect with their goals both academically and athletically. We're teaching them how to say 'Yes ma'am and no ma'am,' how to pull their pants up, how to dress for an interview, how to place themselves in the best position, and teaching them how to play the game of life. It's all about presentation. You can set yourself apart from the rest by working with a career center and doing a resume. We are showing them how to strategically place themselves in front of other by being prepared. Preparation is the key to success in anything in life, both on and off the field.
I want to focus on the kids because they are our future. If we can turn a kid around, we can make the world a better place for all of us. If we can get the top kids in the community to become role models, and teach them how to lead in their own community, we can reach kids that we might not otherwise. If we can get one kid, we can get five; and if we can get five kids, we can get twenty — the whole thing just snowballs! We're just trying to impact the community any way we can."
Q: I'm curious to learn how you got involved with HuddlePass
A: "One of my teammates was telling me about HuddlePass. He basically gave me the information and introduced me to CJ Bacher, a quarterback out of Northwestern University. Their goal is to have a site where former student-athletes can interact with the fans."
HuddlePass is an interactive community for fans to connect with former student-athletes who wish to share and teach the game. Fans get an insider's perspective and behind-the-scenes access to their favorite teams. Join your favorite team's Huddle and start getting analysis from those who know the program inside and out.
"On most websites you have sportswriters who never gained a ton of playing experience covering the games, but at HuddlePass you are getting articles directly from former athletes and you are able to interact with them and get the story straight from the horse's mouth. My job is to get former Notre Dame student-athletes involved and to contribute to the website."
Q: What advice would you give current student-athletes?
A: "Definitely get to know your classmates. Quite frankly, these are going to be world leaders moving forward. The people we went to school with are people of outstanding talent and character and will change the world. Get involved, use the network; especially the alumni network because it is so vast. Become active in the alumni network even before you graduate. Right now I consult a bit with the alumni association as well as help the monogram club attract younger members. We're doing our best to get young people active in the alumni and monogram clubs sooner rather than later."
I'd like to give a big thank you to Toryan for stopping by the blog. It was an absolute pleasure to walk through his journey with him. Stay tuned for many more great stories in the "Where are they now?" series! If you enjoy this series, you can also read more stories in my new book, "Echoes From the End Zone: The Men We Became." Signed copies of the book are available through my web site, contact me for more information!
Cheers & GO IRISH!
- Breaking Discoveries in CTE Research? - March 12, 2018
- A Football Player's Lucky Charm? - February 22, 2018
- Part II: From Football to Coffee Beans? - January 31, 2018


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Improving the CSS 2.1 strict parser for IE 7
We've already started talking about a few of the CSS changes that are going to be available in IE 7 when we release, but there are a few hanging points that we haven't talked about yet or haven't covered completely. There are 3 specific items I'd like to talk about:
- Using the root node wild card selector for IE only rules (* HTML) [strict mode only fix]
- Multi-class selectors as defined by CSS 2.1 (.floral.pastel) [strict mode only fix]
- Pseudo-element parsing sometimes flags rules as invalid (P:first-letter{ color: red; }) [strict/quirks mode fix]
Root node selection:
To be very clear the root node selector was a bug. This was introduced by Chris Wilson back in IE 4 which is why we don't let him work with the code anymore.
The root node selector has long been used to create rules that only work in IE. The general pattern would be to write rules that would match in all browsers first. Then use the child selector logic ( > ) to create more specific rules that would match only in browsers that supported these selectors. Prior to IE 7 we didn't support these selectors so they were transparent to us. Finally, you would apply rules that would only match in IE by using the * HTML pattern to match the root node. Since no other browser supports or contains a node in the DOM located above the HTML node these patterns wouldn't match.
So what happens when we start to match child selectors in IE 7? Well, it makes a big mess because we now match more rules not meant to be used from within IE and then those are merged with IE only rules. Because of the merge styles that were never meant to be combined end up changing the layout of the page away from what the author originally intended when they designed their cross browser matrix and testing patterns.
The best fix here was to disable the root tag matching logic because it wasn't supposed to work according to the standards. We only do this in strict mode, since the new selectors only match in strict mode, and so we now use the same sets of rules that other CSS 2.1 compliant browsers would use and we ignore the IE only rules resulting in a page that will lay out as designed by the author. There are a few issues with this when we differ in our interpretation of the spec from other browser implementations but most of the time these are minor and have easy workarounds.
An article on peachpit by Molly Holzschlag contains further examples detailing how this works.
Multi-class selectors:
When the class selector support was originally written it was drawn up based on the CSS 1 spec which only supported a single class selector in each simple selector. We wound up keeping this behavior even after implementing portions of later versions of CSS. The end result is that we always threw out the extra classes in the selector and only kept the last one in the list and matched based on that.
Well, some sites use multi-class selectors so when we looked at doing CSS 2.1 selectors work it was pretty easy to upgrade our class selectors to allow more than one class to be applied. When in strict mode we now obey all specified class selectors per simple selector. While you won't often use the feature it can be used for some interesting applications. One of my original test cases would use combinations of red, yellow, and blue classes to paint elements based on their combined color. A selector such as .red.yellow would paint and element orange if it contained both of these classes in a space separated list within the class attribute. Any elements not matching at least both of these wouldn't match and so you can more accurately apply hierarchical styles.
DHTML Kitchen has a great example of multi-class selectors and the current compatibility problems.
Invalid Pseudo-Element selectors:
We applied a very, very strict interpretation of pseudo elements in our parser and this would cause certain constructs to get thrown out. Basically we asserted that any pseudo-element had to be the very last thing in the selector. The spec only really mentions that there can be only one pseudo-element per selector and it must appear in the last simple-selector within the selector. Because of our strict interpretation if we saw any non-whitespace character or token after we just processed a pseudo-element we'd throw an error flag into the rule. This gave us the following behavior:
- Fail - P:first-letter{ color: blue; }
- Fail - P:first-letter:hover { color: blue; }
- Succeed - P:first-letter { color: blue; } /* note the space */
- Succeed - P:hover:first-letter { color: blue; } /* note the ordering */
The parser is much more intelligent about when and how it applies the error flag in IE 7 and the two failures you see will now succeed. Truly invalid rules will still fail and you have to be careful not to apply multiple pseudo-elements or apply pseudo-elements that are in simple selectors that are in the beginning of a complex selector.
For a clear example of this issue you can take a look at an article on MaxGeek.com.
Moving Forward:
These small issues that made writing web pages according to spec a trial-and-error situation have been fixed for IE7. By improving the parsing logic it becomes more obvious how your selectors should be written and existing W3C documentation can be used to quickly come up to speed. It should be easy to introduce interesting layouts and formatting in your web pages without having to specify custom rules for each browser and hopefully IE 7 comes one step closer to making that a reality.
- Justin Rogers