text:
Humans are an instinctively tribal species. And while this trait served us extremely well throughout our long history, we have not only outgrown its usefulness, but are now victim to its destructive influence.I have often stated that religious belief is outdated and irrelevant to our modern world but I don't recall ever expanding on that idea as eloquently as Ted Cadsby does above.
Compared to other animals, humans exhibit extreme "groupishness." We are unusually co-operative with, even altruistic toward, in-group members. And on the flip-side, we are distinctly suspicious of out-group members. We suspect their habits, motives and values, and even question their intelligence. Our apprehension is extreme: while a small number of animal species display occasional viciousness, their aggression is nowhere near the scale of human righteousness, warfare or terrorism.
In explaining the tribal nature of Homo sapiens, evolutionary scientists collectively share the view that within-group co-operation improves the survival rates of its members, who, for example, would be hard-pressed to succeed as independent hunters. In a harsh environment with limited resources, it is highly adaptive to be both pro-social within our tribes and anti-social to outsiders who compete for food and mates. We have been hunter-gatherers for more than 99 percent of our history as a member of the Homo genus, and for 90 percent of our time as the sapiens species of this genus. So what worked for our progenitors has been deeply hardwired into who we are today.But the out-group hostility element of tribalism is no longer adaptive in the modern, complex form of civilization we have created. We are now more interdependent as a species than ever before, by virtue of our interconnected economies, our real-time, Internet-based communication, the power of our weaponry and the environmental influence of our industrial activity. The benefit of out-group hostility has not only expired, but is now severely detrimental to our well-being both as individuals and as a species. We should be working hard to defy our impulse toward out-group hostility. And this is precisely the problem with religion -- it feeds the very instinct that we should be resisting.
While religion promotes the in-group, prosocial side of tribalism, it also fosters the out-group, anti-social side. The out-group feature of religion is uniquely problematic: faith separates people in a deep, fundamental way. Faith-based belief systems are absolutely incommensurable. Different faith-based convictions cannot be reconciled because there is nothing to appeal to in order to understand, challenge or share them. Either you have a certain form of faith or you don't -- there is no rational way to reconcile different views of reality. Religion not only promotes difference, it makes divisions impossible to eliminate, so between-group co-operation is discouraged and out-group hostility is fueled. [Penn] Jillette makes the point that "the only argument against religious terrorism is to try to share the reality of the world." And he points out that faith separates us since it means that "anything goes." Indeed, a shared sense of reality is the only valid starting point for reducing our tribal instincts.
...the more relevant argument is that religion promotes out-group mentality in an age of interdependence when we can't afford to surrender to ancient instincts. Just as we have to resist our ancestral urge to eat sweet, fatty foods -- an instinct that once served our survival but now threatens our well-being in a world where sugar and fat are abundant -- we also have to resist the urge to indulge in the tribalism that religion promotes. Our greatest opportunity as human beings is also our toughest challenge: to defy our maker. Not the faith-based, mystical one, but the natural selection one, which shaped who we are in an environment that was much different than the one in which we now live. (Source)
Humans have not only evolved physically, our social structure has evolved as well. Our most basic drives and instincts were formed at a time when we lived very differently than we do today; hunting and killing our dinner, building and rebuilding our villages as we kept up with the herds of prey or after devastating natural disasters, planting and harvesting our crops by hand. Competition among tribes involved the risk of losing access to prey or the best places to plant crops. Humans had to guard against raids in which food, weapons and even members of the tribe were stolen by neighboring groups. It was a time in our evolution when it made sense to live in small, isolated tribes and to be on guard against those not of our tribe.
Those days are no more. True, humans still compete with each other for limited resources but on a much grander scale. Our tribes have become nations; instead of 10 or 50 people in a tribe we now have millions, in some cases billions, in a nation. Cooperation is often more beneficial than competition on a global level.
The divisive and tribal nature of religion made sense in its time, but that time is past and so are any benefits that religious belief provided us. "The gods" is no longer a necessary postulation for natural occurrences. "Our gods" versus "your gods" is an outdated reason for warfare and contention on a global scale. Religions have not only outlived their usefulness but have become detrimental to our continued survival as a species. Too often warfare is justified by our old tribal instincts. Even in the Middle East or Africa, where it could be argued that the majority still live tribal lifestyles, religious beliefs cause more strife and division than they promote peace and the general welfare.
Religious beliefs, as with other superstitions, have outlived their usefulness, indeed mankind has outgrown their need. For the good of humanity they ought to be relegated to the past where they belong.


text:
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This article is a stub, an article too short to provide more than rudimentary information about a subject. You can help Pro Wrestling Wiki by expanding it.
Kevin Lloyd is a British bodybuilder, martial artist, model and professional wrestler better known by his ring name Sexy Kev. He is easily known for his fitness-inspired gimmick as a wrestling Chippendale, frequently clad in hot-pink ring attire and his highly conditioned physique.
Personal life
Outside of wrestling, Kevin practices martial arts including Ju-Jitsu and Muay Thai. He works as a junior accountant and model.


text:
By MIA FREEDMAN
They're those moments so awkward you don't know whether to speak up and correct someone's mistake or let it slide.
And before you can even decide, it's suddenly too late and the conversation has moved on and you're trapped in a horrible misunderstanding you feel powerless to rectify.
There I was sitting in the doctor's office. He wasn't my usual doctor but my youngest son needed his 4yo immunisations and I'd heard he was an expert injection-giver. Which he was. He'd been doing it for more than 50 years. But that wasn't the problem.
Early on in the consultation, he referred to my son as 'she'. As in, "….and how old is she?"
This threw me. My son's name – Remy – could possibly be seen as unisex. OK. But he looks very much like a boy. Short hair. Dressed like a boy. Not a lot of room for error, visually.
As this all flashed through my mind, the very small window of opportunity for me to correct the lovely elderly doctor passed.
And I was trapped. We were all trapped in this very awkward gender misunderstanding.
It got worse.
"So, is there any family history of breast cancer?"
Um, yes but that's probably not going to be a huge issue FOR MY SON. I thought this but didn't say it because I was so sure the doctor would spontaneously notice that the child I was holding on my lap was, you know, not a girl.
He never did.
And I was then forced to avoid using any personal pronouns myself so as not to draw any attention to the misunderstanding and make it even more awkward.
Because you get to that point where you just can't correct someone any more, can you? When it's just too late.
This happened to me recently except I was the one who needed to be corrected.
Mamamia's Managing Editor, Jamila Rizvi – who I have known for 4 years and worked with for 4 months, had to make a small announcement to the MM editorial team that we had been pronouncing her name wrong.
It's not Jamila-rhymes-with-Camilla.
It's Ja-mee-la.
Which is actually far more beautiful and actually MEANS beautiful in Arabic.
Naturally, we were all mortified that we'd been pronouncing it wrong all this time.
And then she felt bad that we felt bad. And it was all just hilariously awkward.
Selfish of her to bring it up in the first place, I reckon.
Have you had one of these moments? Ever been wrong about someone's name (or had someone be wrong about yours) for years? When does it become too late for a correction?


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GameBoy Player FAQ by cvxfreak
Version: 2.0 | Updated: 04/08/07 | Search Guide | Bookmark Guide
Game Boy Player FAQ
Nintendo GameCube/Game Boy Advance
Written by: cvxfreak
Date: April 08, 2007
Version: 2.0
E-mail: FireEmblemPride[at]gmail[dot]com
This FAQ can be found on GameFAQs and its affiliates, as well as
numerous other websites related to game guide hosting.
Version Updates:
April 08, 2007: Updated the FAQ to cover the North American release
that I oddly never got around to covering. A little bit of Wii, DS and
Game Boy micro information in relation to the Game Boy Player was
included, too.
1. Introduction
2. The Game Boy Player
A. Game Boy Player Installation
B. Boot Disc
C. Region Changes, Etc.
3. Options/Translation of Options
A. Game Swap
B. Time
C. Screen
D. Controller
E. Size
F. Frame
4. Frequently Asked Questions
5. Conclusion
1. Introduction
The first time gamers were able to fully and legally experience GameBoy
titles on the TV was with the Super Game Boy peripheral for the Super
Nintendo. Unfortunately, the flaw to the Super Game Boy peripheral was
that it couldn't connect to the portable version of the GameBoy. A
revision of the Super Game Boy, the Super Game Boy 2, which was only
released in Japan, allowed for link up. But the SNES is also long gone.
When the N64 rolled around, gamers could use Pokemon Stadium and
Pokemon Stadium 2 with the transfer pak and play Pokemon Red, Blue,
Yellow, Gold, Silver and Crystal on a T.V. The flaw to that, too, was
that trading wasn't possible.
In 2003, Nintendo released the Game Boy Player for the GameCube. It
was an accessory that was fitted beneath the GameCube system so it
could play back Game Boy, Game Boy Color and Game Boy Advance games on
a TV screen. The accessory made the GameCube into a perfect cube shape
and allowed for link cable trading.
2. The Game Boy Player
The Game Boy Player is a peripheral for the Nintendo GameCube. In
Japan, it ships in colors of Spice (Orange), Jet (Black), Platinum
(Silver), and Indigo (Purple). Only the Jet Black model is available
in North America. In Japan, it retails for 4,000 Yen, which is close to
$40USD, while the accessory goes for $49.99 in the US.
Any color Game Boy Player is compatible with any color GameCube.
However, due to the Panasonic Q (GameCube + DVD + CD Player from
Panasonic, only available in the Japan) and its support legs, none of
the colored Game Boy Players will be compatible with the Q. Instead,
the Q gets its own Game Boy Player in a unique shape and color that
better matches it. Its a rare item, though, so good luck finding it.
1. Take the Game Boy Player out of its packaging.
2. On the GameCube, look on the bottom of the console.
3. Look for the removable cover that says "HI SPEED PORT" and remove
4. Hook the Game Boy Player beneath it.
5. Using a Stanley screwdriver or a small coin (preferrably a dime),
screw the Game Boy Player so that it is firmly connected to the
GameCube system.
6. Turn the system back over.
The Game Boy Player will not be read by the GameCube unless the Boot
Disc that comes with the package is inside the GameCube. The Boot Disc
is Japanese-encoded (see below). When the Game Boy Player is placed
and connected to the GameCube, put the disc into the GameCube. After
the GameCube logo, a Game Boy or Game Boy Advance logo will appear,
and the inserted Game Boy, Game Boy Color or Game Boy Advance game
will play as if you were using a portable Game Boy system.
The Boot Disc, notably, will also stop spinning, but the Game Boy
Player will still function. Whenever you want to play a GameBoy game
on the TV, use the Boot Disc.
The Game Boy Player, from Japan so far, will play any Game Boy, Game
Boy Color and Game Boy Advance from any region of the world (North
America, Europe, Japan, Australia, etc.). There are a few exceptions,
such as games with a tilt sensor, rumble feature, or accessories like
the GameBoy Camera.
The Boot Disc is NOT region-free. So if you bought a Game Boy Player
from Japan, you can only use the Boot Disc that came with it on a
Japanese GameCube, unless you have a mod switch installed or use a
Datel Freeloader.
Nintendo of America sells replacement Boot Discs on their website,
store.nintendo.com. So if you imported a Game Boy Player from Japan
and want to have the options screen in English, use the replacement
Boot Disc, which works just fine with the Japanese Game Boy Player
hardware and vice versa.
3. Options/Translation of Options
I only have a Japanese Boot Disc, so I cannot tell you how the options
are told in the North American version of the Boot Disc, but this
translation should more or less reflect what it says on the Game Boy
Player menu in English.
During gameplay at anytime, press the Z Button to access the Game Boy
Player menu. It is completely in Japanese. From RIGHT TO LEFT are the
translations of the options:
A. Game Swap
Select this option, and you will be asked if you want to change to a
new Game Boy/Color/Advance game. The left option is YES and the right
option is NO. If you select YES, a screen will pop-up. Swap games.
Then the Game Boy Player will restart (boot disc not needed).
B. Time
Parents can set time limits for their kids. Press A, and the time
limits can be set. Select up to an hour, so far. Please note that the
times that appear in 1-60 are minutes.
C. Screen
Select screen display settings from SOFT (top option), NORMAL (second
option) and SHARP (bottom option).
D. Controller
There are two options. Here are the possible control schemes,
corresponding with the Game Boy/Advance and GameCube controller.
GameCube - Game Boy (Advance): Setting One
GameCube - Game Boy Advance: Setting Two
Personally, I prefer the first set up, but the second one is unique and
effective as well.
E. Size
There are two sizes available: FULL and NORMAL, which is basically it.
FULL will display the game more on the TV; NORMAL will use a little
F. Frame
The Game Boy Player will never display games to the absolute fullest on
a TV, but there are as many as 20 frames to choose from.
4. Frequently Asked Questions
Q. Should I get a Game Boy Advance SP or a Game Boy Player?
A. It depends on whether you play outside or at home more. As of 2007,
the Game Boy Advance SP is now offered in a backlit model, so it would
be fairly competent at home, too. Likewise, with the Wii now Nintendo's
main priority as a game console, you may not want to keep the GameCube
hooked up.
Q. Do the graphics and sound match the SNES/Genesis?
A. Yes and no. The graphics from SNES ports look about as good as their
SNES counterparts, but a lot of the time, they'll look softer and less
colorful (such as Super Mario Advance when compared to Super Mario All-
Stars: Super Mario Bros. 2). Sound-wise, it doesn't match up to the
SNES game. Some audio doesn't translate too well onto the televsion
Q. Where can I find a Game Boy Player?
A. Try www.ncsx.com or www.play-asia.com if you want a Japanese unit,
and your typical American retailers for an American unit, such as
EBGames/GameStop, Target, Walmart, Circuit City and Best Buy.
Q. How much is a Game Boy Player?
A. In Japan, it's about 4000 Yen, while the U.S. price is $49.99.
Q. What colors do they come in?
A. In Japan, it's Silver, Black, Orange and Purple. In the U.S., it is
only available in Jet Black despite the presence of the Indigo and
Platinum colored GameCube systems.
Q. Why isn't Q compatible with the Game Boy Player?
A. The Q has long legs supporting it. The Game Boy Player port won't be
able to reach the extension spot on the Q. Panasonic and Nintendo, in
order to solve this, released a larger Game Boy Player model that
accommodates for the Q's legs.
Q. Can we connect this to the Game Boy, Game Boy Pocket, Game Boy
Color, Game Boy Advance, Game Boy Advance SP and another Game Boy
A. Yes, yes, yes, yes and... yes. The first 5 require their respective
link cables. Linking to another Game Boy Player is possible, if you
have 2 GameCubes and 2 TVs, and 2 Game Boy Players, and the GBA Link
Cable of course.
Q. What about the Game Boy micro?
A: The Game Boy micro was released in 2005 and was a smaller sized
Game Boy Advance unit without the backwards compatibility. However, it
contained a unique port for its link cable, so a converter to connect
with other Game Boy Advance systems including the Game Boy Player is
needed. However, Nintendo has not created a Game Boy micro to GameCube
link cable, so you cannot use the Game Boy micro to control your Game
Boy Player games on the TV. However, some forum uses have made mods to
make this work, so a Google search should help you find what you're
looking for.
Q: And the Nintendo DS/DS Lite?
A: The DS and DS Lite have succeeded the Game Boy Advance line. They
play Game Boy Advance games, but not Game Boy or Game Boy Color games,
nor can the DS use any link up features for GBA games. So it can't
connect to the Game Boy Player in any way.
Q. Can having the Game Boy Player hooked up access GBA-connected
features in some GameCube games?
A. No. A separate screen is necessary, which isn't available. Plus, the
GameBoy Player is inactive when playing GameCube games as both the GB
Player and a GameCube game cannot be booted at once.
Q. The Wii can play GameCube games. What about the Game Boy Player?
A. No, the Wii cannot play back Game Boy Advance games with one minor
exception that has nothing to do with the Game Boy Player. The Game Boy
Player literally cannot fit with the Wii because the Wii does not
possess the serial port needed to do it. It can, however, run the Boot
Disc, but without the hardware, no game can be played.
Pokemon Box: Ruby and Sapphire was able to run copies of Pokemon Ruby
and Sapphire using the GBA-GC link cable, and since the Game Boy
Advance and SP can link up to the Wii, the Wii is able to run those
Q. Can Game Boy Advance movies run on the Game Boy Player?
A. No, Nintendo's specifically locked out movie cartridges from
running on the Game Boy Player. You'll simply end up with a screen
that says "Not Compatible With Game Boy Player." The reason is, the
movies could be recorded and uploaded onto Youtube or any other site.
Not to mention that the movies are in such a low resolution anyway that
no one would want to use the Game Boy Player for it anyway.
5. Conclusion
FAQ is done. Credits go to:
CJayC of GameFAQs
Nintendo for creating all the products mentioned in this FAQ
Friends, family and others
- cvxfreak
FAQ Display Options: Printable Version


text:
Lists of Derbyshire Miners, taken from the Censuses of 1841 to 1871, have been compiled by the society's Recorder, Dave Williams in the course of researching the decline of employment in the Derbyshire lead mining industry and to try and plot the emigration of lead-miners to the Derbyshire coalfield. These lists are by no means complete and the absence of a name should not be taken as the absence of the miner. These lists have been presented by year and in alphabetical order, please select the required year below . Where a name is unreadable an asterisk has been used to cover the missing character. We hope that these are of use to researchers, and would welcome any additional information, corrections or omissions.
Apart from research from microfilms in the Matlock, Chesterfield and Buxton branches of the Derbyshire Library Service, Dave also extracted data using the CDs of census data supplied by Archive CD Books (http://www.rod-neep.co.uk) and the web-site belonging to John Palmer who has an exhaustive collection of data relating to Wirksworth and district on his web-site (http://www.wirksworth.org.uk).


text: Politics 10 August 2013 David Cameron to Stephen Fry: I won't boycott the Winter Olympics The prime minister responds to the suggestion that Russia's anti-gay laws mean Britain should refuse to take part in the Winter Olympics. Sign up for our weekly email * Print HTML David Cameron has refused calls for Britain to boycott the Winter Olympics in Russia because of the country's anti-gay laws. In a series of tweets, he said: 1/2 Thank you for your note @stephenfry. I share your deep concern about the abuse of gay people in Russia... — David Cameron (@David_Cameron) August 10, 2013 2/2 @stephenfry However, I believe we can better challenge prejudice as we attend, rather than boycotting the Winter Olympics. DC — David Cameron (@David_Cameron) August 10, 2013 Fry had earlier written that, in Russia: Beatings, murders and humiliations are ignored by the police. Any defence or sane discussion of homosexuality is against the law. Any statement, for example, that Tchaikovsky was gay and that his art and life reflects this sexuality and are an inspiration to other gay artists would be punishable by imprisonment. It is simply not enough to say that gay Olympians may or may not be safe in their village. The IOC absolutely must take a firm stance on behalf of the shared humanity it is supposed to represent against the barbaric, fascist law that Putin has pushed through the Duma. Several prominent gay athletes and commentators have welcomed Fry's move, but disagreed with the idea of a boycott. The BBC's Clare Balding said that she would attend: "I'm pleased Stephen has raised the argument and I hope that his piece is read and debated at the highest levels. If the venue for the Winter Olympics remains as it is, I will be presenting from Sochi for the BBC. I will do so because I am a sports presenter who happens to be gay. I think the best way of enlightening societies that are not as open-minded as our own is not to be cowed into submission. I intend to stand proud, do my homework and do my job as well as I possibly can - as I would for any other sporting event." Skater Johnny Weir said that it was "not Russia's public's fault that their government is so bigoted" and therefore he would attend the Olympics. The Daily Mail responded to Fry's blog with a feature entitled "What right has this smug luvvie to speak for the civilised world?" In it, Andrew Pierce asked: "Why do he and his luvvie friends think they can try to dictate which countries are appropriate to stage Olympic events and which are not? The problem with actors, of course, is that they think they are as clever as the lines they recite." Fry responded yesterday with a follow-up post: The Mail still can't quite live with the shame that it has always, always been historically wrong about everything - large and small - from Picasso to equal pay for women. › Who will be able to afford to "pay to stay" in social housing? Skater Johnny Weir, whose husband is Russian, will attend the Olympics. Photo: Getty Helen Lewis is deputy editor of the New Statesman. She has presented BBC Radio 4's Week in Westminster and is a regular panellist on BBC1's Sunday Politics. Subscribe from just £1 per issue More Related articles Britain's largest communications union to affiliate to Momentum Scotland's vast deficit remains an obstacle to independence The NHS's sustainability is under threat if more isn't done to look after its staff Subscription offer 12 issues for £12 + FREE book LEARN MORE Close This week's magazine


text:
Recent research into the Global Acetic Acid Market
ACCESS REPORT @ Recent research into the Global Acetic Acid Market
Global Acetic Acid market was valued at 12,124.3 kilo metric tons in 2014 and is expected to reach 16,155.09 kilo metric tons by 2020, showing a compound annual growth rate of 4.9%. Asia-Pacific is the biggest consumer of in the industry, which consumed around 60% of the total global demand in 2014, followed by North America with a considerable demand. China is the biggest consumer, and is also among the fastest growing markets with an estimated CAGR of about 5.6% from 2014 to 2020. The European and North American markets are comparatively mature with a demand growth below the average market growth.
It is a key building block to manufacture various chemicals, such as Vinyl Acetate Monomer (VAM), Purified Terephthalic Acid (PTA), Acetate Esters, and Acetic Anhydride that are further used by a wide range of end-user industries, such as synthetic fibers, textiles, inks, and pesticides.
The application segments covered in the study include vinyl acetate monomer, purified terephthalic acid, acetate esters and acetic anhydride. Vinyl acetate monomer (VAM) was the largest application segment for the market accounting for 32% of global acetic acid consumption in 2014. Consumption of acetic acid in the manufacturing of VAM generated revenue of over USD 2,000 million in 2014 primarily driven by the demand for VAM in the adhesive and sealant industry.
Acetate Esters manufacturing segment is expected to be the strongest growth segment of the market, which is primarily driven by the growing demand from coatings industry.
Among all the acetic acid derivatives, VAM led the market with the highest global consumption of more than 5.0 million tons, followed by ester solvents with total global consumption of around 4.0 million tons in 2014.
In addition, acetic acid has niche applications such as development of photographic films, household descaling agent, lysing of RBC (red blood cells), food preservatives and synthesis of metal acetate. Owing increasing number of applications over the past decades the scope of this market is expected to increase manifold in the coming years.
Companies profiled in the Acetic Acid market report include BP Plc., Celanese Corporation, Eastman Chemical Company, PetroChina, Daicel Corporation, LyondellBasell Industries N.V., Sasol, SABIC, Jiangsu Sopo Co. Ltd., and Kingboard Chemical Holdings Ltd. among others.
Acetic acid is the main feedstock to manufacture vinyl acetate monomer, which was at the forefront in terms of volumetric consumption in 2012. It is mainly driven by the growing demand of polyvinyl acetates and vinyl alcohols, which in turn are accelerating the demand for acetic acid. VAM is a key raw material in the manufacturing of water based adhesive which accounts for close to 54% of the global adhesive and sealants market and the increasing demand from Asia Pacific is expected to boost the demand for acetic acid over the forecast period.
Environmental concerns represent one of the major factors influencing the market for acetic acid. Demand is expected to rise as the chemical replaces solvents in printing inks, coatings and adhesives.
Adoption of innovative and path breaking technologies are providing competitive edge to the companies to enhance their profit margins vis-a-vis competitors. Accordingly, manufacturers of acetic acid are increasingly adopting these technologies over age-old technologies such as low-water technology. Saturation in western economies and mushrooming growth in Eastern economies have spurred globalization of industries. Together with the opportunities to expand presence, globalization brought with it a host of problems that are region-specific and hence, the regional governments' foreign trade and investment policies and formation of free trade areas are of critical importance.
What the report contains
The report elucidates the situation of Acetic Acid around the world and studies its markets by application which include Vinyl Acetate Monomer (VAM), Purified Terephthalic Acid (PTA), Acetate Esters, Acetic Anhydride and Others.
Lastly, the report is divided by geography - North America, Europe, the Asia-Pacific (APAC), South America and Middle-East & Africa (MEA); where-in the market share of each region is analyzed and estimates are provided for the next 5 years.
ENQUIRE FOR DISCOUNT @ Recent research into the Global Acetic Acid Market
15. Company Profiles (Overview, Products & Services, Financials, Recent Developments)
15.1 British Petroleum
15.2 Celanese
15.3 Daicel Corporation
15.4 DuPont
15.5 Eastman Chemical Co.
15.6 Jiangsu Sopo Co. Ltd.
15.7 Kingboard Chemical Holdings Ltd.
15.8 LyondellBasell
15.9 Mitsubishi Chemical Company
15.10 PetroChina
15.12 Sasol
15.13 Shandong Hualu-Hengsheng Chemical Co. Ltd.
15.14 Shanghai Huayi Group
15.15 Sinopec
15.16 Yancon Cathay Chemical
15.17 Yankuang Cathay Coal Chemicals Co. Ltd.
KNOW MORE WITH SAMPLE REPORT @ Recent research into the Global Acetic Acid Market
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text:
HI all,
I need to configure the POP3 mail account on exchnge SERVER 2010 so that all the mail comes in exchange 2010 server and then these mail deliver to the concern user of exchange server. is it possible can we do this.
3 Replies
Sep 17, 2010 at 2:15 UTC
Exchange includes a POP3 connector only in Small Business Server. For a regular Exchange Server, you would need to buy and install a third-party POP3 connector such as for example Mapilab http://www.mapilab.com/exchange/exchange_pop3/
Sep 17, 2010 at 9:19 UTC
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I have always been impressed and passionate about flying machines and the ultimate frontier that space represents. This led me to recently graduate from a Masters in Aerospace Engineering as one of the top students at a leading UK university. Throughout this degree I was offered the opportunity to understand and apply advanced engineering concepts to different design projects.
In my final year, I consequently designed a proof of concept nuclear battery or Radioisotope Thermoelectric Generator (refer to my courses to learn more about these) for nanosatellites which was judged by academics as one of the best projects of my department and presented at the 4th Interplanetary Cubesat Workshop. Similarly, I developed, with a team of colleagues, an unmanned rotorcraft able to fight fires, carry cargo and surveillance missions which eventually won a design competition for Agusta Westland.
I am very excited to be able to share my knowledge with curious individuals, who like me want to know more about the engineering behind the wonderful machines that populate our sky.


text:
|Publication number
|Publication type
|Application number
|Publication date
|May 6, 2003
|Filing date
|Mar 30, 1999
|Priority date
|May 8, 1998
|Fee status
|Publication number
|James Christopher Wilson, Wolf-Dietrich Weber
|Original Assignee
|Fujitsu Limited
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Referenced by (28), Classifications (13), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims the benefit of U.S. Provisional Application No. 60/084,795, filed on May 8, 1998.
This application is related to U.S. patent application Ser. No. 09/041,568, entitled "Cache Coherence Unit for Interconnecting Multiprocessor Nodes Having Pipelined Snoopy Protocol," filed on Mar. 12, 1998; U.S. Pat. No. 6,212,610, entitled "Memory Protection Mechanism for a Distributed Shared Memory Multiprocessor with Integrated Message Passing Support," issued on Apr. 3, 2001; and U.S. Pat. No. 6,209,064, entitled "Cache Coherence Unit with Integrated Message Passing and Memory Protection for a Distributed, Shared Memory Multiprocessor System," issued on Mar. 27, 2001; which are hereby incorporated by reference.
1. Technical Field
This invention relates generally to multiprocessor data processing systems, and more particularly to cache coherence for a plurality of multiprocessors with a multi-bus shared memory system.
2. Discussion of the Background Art
Some computer systems are built with multiple processors that can work in parallel on a program to speed up its execution. The architectures of such multiprocessor systems are classified according to the mechanisms used to communicate between the multiple processors. In shared-memory architectures, all processors access a single large memory and communicate with one another by writing to and reading from this shared memory.
A computer system node may be divided into a processor subsystem and a memory subsystem. The memory subsystem includes the main Dynamic Random Access Memory (DRAM) and provides data from memory in response to requests from any number of connected processors. Normally, the amount of time spent to access data in the memory subsystem is quite long relative to a processor's speed and therefore processors are often built with caches to improve their performance. A cache is a small memory connected between a processor and main memory that stores recently-used data from locations of main memory. The smallest unit of data that can be transferred into and out of a cache is called a "line."
The processor subsystem includes the processors and one or more caches. A cache has a much faster access time than the main memory subsystem, but is usually much smaller. Since a smaller cache cannot hold all of the data that is in the main memory, it must store both the address (called the tag) and the value for any data it currently holds. When a processor requests a particular line, it first attempts to match the address against each of the tags currently in the cache to see whether the line is in the cache. If there is no match, the memory subsystem passes the request to the main memory.
All caching schemes divide main memory into physically consecutive segments. A cache is usually organized as a series of lines totaling the same size as a segment. The tag is used to identify which segment is currently occupying the cache. If the line with a requested address is contained in the cache then the data in that line is delivered to the processor. If the line is not in the cache, then the segment of the main memory containing the line is fetched into the cache and the line is delivered to the processor.
In a direct-mapped cache memory, segments are put into cache lines whose line numbers can easily be calculated from the main memory address.
An associative cache differs from a direct-mapped cache in that a line from any segment may be loaded into any cache line. The cache line needs to store the segment number in addition to the data itself. In order to allow searching the cache, an associative cache includes circuitry to simultaneously check the segment number address against the segment number in every line of the cache. This additional circuitry makes associative caches more expensive.
Set-associative mapping combines architectures of both direct-mapping and associative caches. A set-associative cache is organized as a number of sets, each containing a number of lines. With set-associative mapping, the cache set is determined by the address segment number, but the line within the set is not determined by the address segment number. Typically, set-associative caches are two way, meaning that there are two sets in the cache, which significantly improves the cache hit rate over a direct-mapped cache in providing the requested memory lines.
FIG. 1 shows a flowchart of a typical prior art cache memory access algorithm 100 starting in step 102 with a new request for data in memory. In step 104 the requested data address is compared to the cache tags. Step 106 determines whether the requested data is in a cache. In step 106, if no valid copy of the data is in a cache, then in step 108 the memory subsystem fetches the requested data from main memory into cache memory. Once the requested data is in a cache, in step 110 the memory subsystem delivers the data to the processor that requested it. After the data is delivered to the processor, the memory access algorithm returns to step 102 to await a next memory request.
In a shared-memory multiprocessor system, each processor typically has its own cache, so the system has multiple caches. Since each cache can hold a copy of a given data item, it is important to keep the states of all the caches consistent and up-to-date with the latest copy written by one of the processors. It is the responsibility of the memory subsystem to return from the caches or main memory the correct value as prescribed by the processor's memory model, which is a set of rules governing the operation of the memory subsystem. This is achieved through the use of a cache coherence protocol.
Therefore, in addition to the main memory, the memory subsystem includes a cache coherence directory which contains control information used by the cache coherence protocol to maintain cache coherence in the system. A conventional directory has an entry for each main memory location with state information indicating whether the memory location data may also exist in a cache somewhere in the system. The node where the main memory line resides is called the home node of that line. The node where the directory resides is called the local node and other nodes are called remote nodes. The coherence protocol keeps track of the state of each cache line and guarantees that the most recent copy of data is given to the processor. The protocol also specifies all transitions and transactions to be taken in response to a request. Any action taken on a cache line is reflected in the state stored in the directory. A common scheme uses three permanent states to accomplish this. The "Invalid" state exists when a line is not cached anywhere and main memory has the only copy. The "Shared" state exists when a remote node (group of processors) has a valid copy of the line. This is not to be confused with a "global shared state," i.e., a global cache coherence state which exists when any cache in the local node or at least one remote cache has a valid copy of the line. These valid lines are read-only and are identical to the copy in main memory. The "Dirty" state exists when a line is valid in one cache only at a remote node. The copy may be modified by that processor and the main memory may contain old data.
FIG. 2 shows a flowchart of a memory access algorithm 200 using a cache coherence directory. A new request for data in memory starts the algorithm in step 202. In step 204 the algorithm compares the requested data address to the directory tags in the cache coherence directory.
In step 206 the algorithm determines the state of the requested data from the cache coherence directory. If in step 206 the state is "Invalid" (i.e., there is no valid copy of the data in a cache), then in step 208 the algorithm fetches the requested data from main memory or local cache into cache memory. If in step 206 the state is "Shared" (i.e., the requested data is in a cache in a remote node), then in step 212 the algorithm fetches the data from memory and if the request is a "store," invalidates the cached copies. If in step 206 the state is "Dirty" (i.e., the most recent version of the data is valid in only one cache), then in step 210 the algorithm fetches the requested data from the cache.
Once a valid copy of the data has been fetched, in step 214 the algorithm delivers the data to the processor that requested it. After the data is delivered to the processor, the memory access algorithm returns to step 202 to await a next memory request.
The coherence protocol may use other transient states to indicate that a line is in transition. Given enough time, these transient states revert to one of the three permanent states.
A cache coherence protocol is typically implemented by a finite state machine in which the states determine where the most recent value of the data resides. A state value must be explicitly or implicitly associated with every line in memory. Typically, explicit association is done by adding some state information to the cache tags in each cache. For lines that are not cached, the state value is implicit in there being no tag match anywhere in the system and thus it is known that the most recent value is in the main memory.
On every processor request, the memory subsystem must look at all cache tags in all caches in the system. There are two methods of doing this: In the first method, sometimes called a "snoopy protocol," each cache can "snoop" every request and then signal to the memory subsystem if it has the most recent copy of the data. In the second method, sometimes called a "directory based cache-coherence protocol," the memory subsystem can keep a copy of each cache's tags to find the location of the most recent copy.
In cache coherent non-uniform memory architecture (cc-NUMA) machines, several memory subsystems are linked together, using a cache coherence protocol to enforce the correct memory model between memory subsystems, to form a single shared memory system. As such a machine is enlarged by the addition of memory subsystems, the bandwidth of the communication paths to memory scales up. Similarly, the cache coherence protocol can be made scalable by making it directory-based. As more memory subsystems are added, so grows the number of directories. The directories may be distributed among the nodes in the system. Each directory tracks the states of all cache lines. The directory size is therefore proportional to the total size of caches and the directory may be organized as a set associative cache of directory entries.
Direct mapping always puts segments in the same place, and thereby avoids the question of which line to replace when the cache is full. However, fully associative and set-associative cache mapping schemes require a replacement protocol to determine which segment in the cache will be replaced by a newly requested segment. The most popular protocol is the "Least Recently Used" (LRU) protocol, which replaces the segment which has not been used for the longest time.
FIG. 3 shows a prior art system 300 including multiple CPUs 302, 304, 306, and 308 having respective local caches 310, 312, 314, and 316 connected by a bus 318 to a memory controller 320 for main DRAM memory 322. In this example of a non-sparse directory, main memory 322 has, for each memory line location, space reserved for a directory 324 entry. This wastes memory space because the total number of cached lines, which determines the number of valid directory entries, is usually much smaller than the total number of lines in main memory. This also wastes memory bandwidth because the same memory 322 is used for directory 324 to hold all coherence states, and there is no faster, smaller memory available for a directory dedicated to lines in short-term transient states.
The prior art cache coherence protocols are deficient in that the directory structure does not distinguish between transient and non-transient line states. Normally, there is only a single transition between transient and non-transient states, but there may be multiple transitions between transient states. Thus, multiple state changes occurring when a line is transient requires additional directory bandwidth.
What is needed, therefore, is a cache coherence protocol that provides an optimized directory architecture which can take advantage of the different directory requirements of different coherence states of lines in cache to improve memory subsystem performance.
The present invention includes multiple multiprocessor nodes each having at least one processor connected to a cache storing multiple cache line entries, a coherence controller, and a directory for keeping track of the cache line states in the caches. The directory includes a first part that holds temporary state information about a first subset of lines for the caches, and the second part that holds non-temporary state information about a second subset of lines for the caches.
The invention reduces the amount of external storage required to hold cache coherence states. Because the amount of time that a line is in a transient state is very short and only a small number of lines will be transient at any given time, the invention also reduces the size of a temporary state buffer. Additionally, the invention, through multiple transient states, eliminates accesses to the external directory for transitions and increases the overall throughput of the coherence protocol.
These and other advantages of the invention will be apparent to those skilled in the art from the following detailed description and the accompanying drawings.
FIG. 1 is a flowchart of a prior art cache memory access algorithm;
FIG. 2 is a flowchart of a prior art cache memory access algorithm using a cache coherence directory;
FIG. 3 is a block diagram of a prior art system including multiple CPUs each having its own local cache, connected by a bus to main memory;
FIG. 4 is a block diagram of a ccNUMA system having a number of interconnected nodes each including a number of processors and caches, a coherence controller, an external directory and a temporary state buffer; and
FIG. 5 is a flowchart of a local read operation using the temporary state buffer in the ccNUMA system of FIG. 4.
The present invention uses cache coherence state information in directory-based cache coherence protocols. The invention thus includes external random access memories (RAM) holding permanent states and an internal buffer holding transient states. The invention is therefore advantageous over prior art systems whose buffers, in addition to cache coherence state information, store both the state and data value. These buffers are usually internal fully associative cache extensions for lines that are transitioning in and out of memory.
The invention also allows many of the state transitions to be done entirely within the internal buffer, and thus reduces the required bandwidth of the external directory and increases overall throughput. Prior art split transaction systems must do a read cycle and a write cycle to the external directory RAM for any state update.
FIG. 4 shows an overview of a ccNUMA system 400 comprising a number of connected nodes 402, . . . , 408, and 410. Each node, as shown for node 410, includes some number of processors 412, 414, . . . , and 420 having respective caches 422, 424, . . . , and 430 connected to a single memory subsystem 440. Memory subsystem 440 includes an external directory 460, main memory 490, and a coherence control chip 480 which contains a coherence controller 450 and a temporary state buffer 470. Coherence controller 450 reads and writes state information contained in an external directory 460 and temporary state buffer 470.
External directory 460 is normally implemented using off-the-shelf RAMs. Only a single "read" or "write" can be performed at one time, although reads and writes can be pipelined, and it usually takes multiple system cycles for a read or write operation to finish. It is usually implemented as a set-associative or direct-mapped cache. If set-associative, then each set comprises multiple entries, each contains a tag, state, and other information used by coherence controller 450. Typically there is also a small amount of other information, such as a "Least Recently Used" (LRU) field, to enable coherence controller 450 to allocate and de-allocate entries. Coherence controller 450 manages external directory 460 by performing basic read and write operations to the RAMs. Since these are off-the-shelf RAMs, their operation is well-known and will not be described here.
Temporary state buffer 470 contains a number of entries, each including a tag, a state, and other information used by coherence controller 450. Operations that can be performed on temporary state buffer 470 are: allocate an entry, de-allocate an entry, and update an entry. In addition, temporary state buffer 470 has an output that indicates to coherence controller 450 that all entries are allocated. These operations can also be done simultaneously on temporary state buffer 470.
Allocation includes finding an unused entry. Unused entries can be indicated either by having an explicit bit in each entry or by setting the state of the entry to "invalid." An unused entry can be selected arbitrarily, one simple way being through the use of a priority encoder (not shown). Allocation is performed by writing the state as a "valid" value and writing all the fields in the entry. Temporary state buffer 470 then returns to coherence controller 450 the number of the entry that was allocated.
De-allocation can be done either by entry or by associative lookup. If done by entry, coherence controller 450 provides the number of the entry to be de-allocated. If done by associative lookup, temporary state buffer 470 compares the address with all tags in the temporary state buffer 470 to determine which entry to de-allocate. De-allocation is done either by setting an explicit bit as "invalid" or by setting the state as the "invalid" state.
Coherence controller 450 can update a valid entry in temporary state buffer 470. It first determines which entry to update either by using an explicit entry number or by using associative lookup. Temporary state buffer 470 then writes any fields, including the state field but not the tag field, specified by coherence controller 450.
FIG. 5 is a flowchart of a local read operation 500 using temporary state buffer 470. The algorithm starts in step 502 with processor 412 executing a load instruction with an address that refers to a location in local node 410. In step 504, processor 412 first passes this request to its cache 422, which in step 506 checks whether it has a valid copy of the line. If so, then in step 508 cache 422 provides the line and finishes the load instruction. If not, then in step 510 cache 422 passes the request to memory subsystem 440. In step 512 coherence controller 450 in memory subsystem 440 first compares the address to the entries in both external directory 460 and in temporary state buffer 470 to see if any state information matches the address in these directories. If there is no match, then the most recent value of the data line must be in main memory and accordingly in step 514 memory subsystem 440 fetches the data line from main memory 490 and the load instruction is finished. If in step 512 the algorithm finds a matching address stored in temporary state buffer 470, then in step 516 coherence controller 450 determines that a request is already outstanding for this line. How this is handled depends on the coherence protocol, but one way to handle this situation is shown in step 518, where the algorithm simply instructs processor 412 to retry the request.
If in step 512 the algorithm determines that there is a matching address in external directory 460 indicating that the most recent value exists in some other node, then in step 520 coherence controller 450 sends a message to that node, allocates an entry for this line in temporary state buffer 470 and puts the previously existing line in buffer 470 in a transient state. In step 522 coherence controller 450 completes the current transaction by informing the requesting processor 412 that coherence controller 450 is waiting for the data. Coherence controller 450 is then free to process new requests.
Later, in step 524, the requested data arrives from the remote node and in step 526 coherence controller 450 looks up the line in temporary state buffer 470 to retrieve the transient state. The transient state tells coherence controller 450 where to deliver the data and what the final permanent state should be. In step 528 coherence controller 450 starts a new transaction to send the data to requesting processor 412, de-allocates the temporary state buffer entry, updates external directory 460 to the final permanent state and finishes the load instruction.
The exemplary embodiment described herein is for purposes of illustration and is not intended to be limiting. Therefore, those skilled in the art will recognize that other embodiments could be practiced without departing from the scope and spirit of the claims set forth below.
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|Wolf-Dietrich Weber
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|Jul 20, 2001
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|Silicon Graphics, Inc.
|Memory device storing data and directory information thereon, and method for providing the directory information and the data in the memory device
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|Method and system for exclusive two-level caching in a chip-multiprocessor
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|Microsoft Corporation
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|Intel Corporation
|Method and apparatus for the synchronization of distributed caches
|May 5, 2011
|May 13, 2014
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|Oct 11, 2016
|Broadcom Corporation
|System, method, and computer program product for conditionally sending a request for data to a node based on a determination
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|Method and apparatus for managing data in a distributed buffer system
|Aug 27, 2001
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|George Robert T.
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|Sep 25, 2002
|Mar 25, 2004
|Ashwini Nanda
|Real time emulation of coherence directories using global sparse directories
|Feb 2, 2004
|Dec 23, 2004
|Barroso Luiz Andre
|Method and system for exclusive two-level caching in a chip-multiprocessor
|Mar 31, 2004
|Oct 6, 2005
|Microsoft Corporation
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|Sep 13, 2005
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|Solace Systems, Inc.
|Highly scalable subscription matching for a content routing network
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|U.S. Classification
|711/144, 711/146
|International Classification
|Cooperative Classification
|Jun 2, 1999
Owner name: FUJITSU LIMITED, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WILSON, JAMES CHRISTOPHER;WEBER, WOLF-DIETRICH;REEL/FRAME:009988/0560;SIGNING DATES FROM 19990508 TO 19990516
|Oct 13, 2006
|Fee payment
Year of fee payment: 4
|Oct 6, 2010
|Fee payment
Year of fee payment: 8
|Oct 8, 2014
|Fee payment
Year of fee payment: 12


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UK: New emissions tester established
A new vehicle emissions test company has been established by powertrain engineering consultancy Integral Powertrain and specialist Tickford Powertrain Test.
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Donald Trump shifts his focus to Hillary Clinton's energy policy during a speech to supporters in Virginia. He says Clinton's agenda will destroy the U.S. coal industry and reduce personal income in the long term.
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Rosenheim, Germany, March 2012: Multitest, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, announces that it has expanded its MEMS portfolio to pick-and-place applications with the introduction of its test and calibration cart for the MT9510. Multitest MEMS solutions now are available for strip test and singulated package test –on Multitest InStrip® with optional InCarrier™, the well-established gravity test handlers MT93xx and MT9928, or the MT9510XP tri-temp pick-and-place handler.
This new combination is based on the two well-established platforms: MT MEMS and MT9510. This setup leverages Multitest's long-term MEMS test expertise as well as thorough understanding of the challenges in DUT handling. Thus, the industry-leading positioning accuracy and tri-temp performance of the MT9510 also is now available for MEMS test.
Multitest has developed this even further by leveraging the contact site dimension of the MT9510 x16. The company now is able to offer a quad-site test solution for MEMS on pick-and-place handlers. Based on the same MEMS cart as for the MT9928, this MT9510 x16/MEMS setup uses both Multitest's pick-and-place and MEMS expertise.
For more information, visit www.multitest.com/MEMS or www.multitest.com/MT9510x16 .


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New iPod Touch Has Nike+ Integration!
If you're like me, you use your iPod mostly when you exercise — I can't live without my tunes when I run. I'm also a religious Nike+ Sports Kit user, the device that snaps into my iPod and tells me how fast I'm running, how far I've run, and how many calories I've burned. It's a wonderful motivator that allows me to keep track of my workouts, but you know, it's tough to keep track of the little one-inch receiver! I've lost two already and have to keep re-buying them. Now I don't have to worry because the new iPod touch (unveiled yesterday) has the Nike+ receiver integrated inside (the first generation iPod touch doesn't, and neither does the iPhone). No receiver to plug in means you don't have to worry about losing it. You still have to wear the sensor that fits in or on your shoe, but I can deal with that. You can get an 8GB iPod for $229, 16GB for $299, and 32GB for $399. It's definitely on my wish list.


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Tuxedo Vests are the Latest Trend in Men's Formalwear According to TuxedosOnline.com
Sunday, December 29, 2013 4:12:40 PM America/Los_Angeles
TuxedosOnline.com's CEO, Vrej Grigorian, believes that tuxedo vests have recently become a hot trend in men's formalwear. Over the last month, tuxedo vest sales have spiked, especially the sale of red vests for the holidays.
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