text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 8, 1980
|Filing date
|Apr 22, 1976
|Priority date
|Apr 22, 1976
|Also published as
|Publication number
|Charles L. Devlin, Charles W. Eichelberger
|Original Assignee
|General Electric Company
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (21), Referenced by (84), Classifications (16)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates, in general, to microcomputer systems and, more specifically, to a memory for use in a multiprocessor microcomputer system utilizing a bus interconnection structure.
Microcomputers are becoming increasingly important in a wide ranging variety of applications. As economies involved in the production of microprocessors and microcomputers continue to reduce the cost thereof, they will be utilized in more and more applications. It may often times be desirable to utilize more than one processing unit in conjunction with a single memory or a portion thereof. This may be desirable in order to divide the functions performed by a microcomputer among two or more processors in order to increase the capacity of the microcomputer system. Another advantage of a multiprocessor system is that lower cost may be achieved by enabling the implementation of a complex system with two or more relatively low cost processors as opposed to a single more complicated and consequently higher cost processor. A further advantage which may be obtained is that a system may be designed such that, in the event of failure of a single processor a second processor will assume the functions of the failed processor and thus provide a degree of redundancy not found in single processor systems. A still futher advantage attendant a multiprocessor microcomputer system is that communications may be established between two or more processors through a shared memory directly accessible to any processor. A system of this type has the capacity for sharing not only data but also programming information and has the further advantage of allowing one processor to control the programming of another by modifying the instructions stored in a single memory. Many microprocessors currently in use are organized according to a bus structure for communication between the microprocessor and the other components of the microcomputer system as, for example, memory and input/output devices. A bus interconnection structure allows the ready modification of a microcomputer system by the substitution of components therein without the need for physical modification of the basic system hardware. It is desirable, therefore, that a shared memory for utilization in conjunction with a multiprocessor microcomputer system be compatible with a bus-type interconnection structure.
These and other advantages and improvements in a multiprocessor microcomputer system are achieved in accordance with this invention. Briefly stated, and in accordance with one aspect of this invention, a multiprocessor microcomputer system is provided having two or more substantially independent processors each of which has its own bus-type interconnection structure, and a shared memory accessible by any of the processors without interferring with the proper operation of the other processors. In accordance with another aspect of this invention, a multiprocessor shared memory microcomputer is provided wherein one processor is designated a priority processor and is allowed access to the shared memory on a priority basis without interferring with the proper operation of the other processors. The types of microprocessors used in conjunction with a shared memory of the type with which this invention mainly is concerned often times operate in a mode which actively utilizes an associated memory for only a portion of the time, typically in accordance with a clock waveform wherein actual connection to memory is required during only a certain phase of the clock. A shared memory in accordance with this invention enables two microprocessors to utilize a shared memory in a fashion providing extremely efficient use of a single memory by two or more processors. A feature of certain memories in common use is that they are able to respond to requests for service from a microprocessor faster than the processor is able to utilize the service. For example, data can be written into or read out of a memory faster than certain microprocessors are able to perform the reading or writing operations. Accordingly, there is provided by this invention means for increasing the efficiency of memory utilization by enabling a single shared memory to provide service to two or more processors such that the time during which one processor does not require service is dedicated to the other. In this way a substantial amount of time during which memory was previously inactive and, therefore, wasted is efficiently utilized.
In accordance with still another aspect of this invention, a shared memory is provided which may, if desired, appear to each of the two or more processors sharing it to be a different section of the total memory capability of the processor. For example, assume that each of two processors has the capability to address 64,000 memory addresses. Assume still further that shared memory is provided in accordance with this invention to the extent of 8,000 addresses. In accordance with a feature of this invention, the 8,000 shared addresses might appear as addresses 0 through 7,999 to a first processor and 8,000 to 15,999 to a second processor. Where desired, of course, the shared memory may be the same addresses for two or more processors.
The features of the invention which are believed to be novel are pointed out with particularity in the appended claims. The invention itself, however, both as to its organization and method of operation together with further objects and advantages thereof may best be understood by reference to the following description taken in connection with the accompanying drawings in which:
FIG. 1 is a block diagram of a multiprocessor microcomputer in accordance with this invention wherein memory is shared between two or more processors.
FIG. 2 is a detailed logical schematic diagram of a shared memory for utilization with two processors in accordance with a presently preferred embodiment of this invention.
FIG. 3 is another detailed logical schematic diagram of a shared memory in accordance with this invention.
FIG. 4 is a detailed logical schematic diagram of a shared memory for use with more than two microprocessors in accordance with this invention.
A two processor microcomputer including a shared memory in accordance with this invention is illustrated in block diagram form at FIG. 1. The computer, designated generally at 10, includes first processor 12 and second processor 14. It is to be understood that while this invention will be described in conjunction with FIG. 1 with respect to a multiprocessor microcomputer having two processors, that those skilled in the art will readily appreciate that two, three or more processors may readily be employed with a single shared memory in accordance with the teachings of this invention. Processor 12 has associated therewith a first bus structure generally designated at 16 which includes: an address bus 18, a data-out bus 20, a data-in bus 22, a read/write control bus 24 and a wait bus 26. It will be appreciated by one skilled in the art that while the read/write control bus and wait bus are illustrated as single wires and the address and data buses are illustrated as three wires that the precise configuration of the buses will vary depending upon the type and number of signals required to be transmitted along the buses. For example, it is often times convenient to provide parallel address data inputs and outputs including as many as 16 bits. It will be appreciated that the address bus will contain a sufficient number of distinct electrical connections to supply the requisite number of bits. Similarly, the data-out and data-in buses may contain, for example, 8 bits of parallel format information each and will therefore require 8 conductor buses for each of the data-in and data-out buses. The read/write and wait buses may readily be accomplished utilizing only one electrical conductor referenced to ground or, alternatively, two or more conductors as desired. The specific form taken by the sundry buses depends upon the organization of the processor and related ancillary equipment utilized in accordance with this invention. Although not illustrated, it will be appreciated by those skilled in the art that additional busses may be provided in accordance with particular embodiments of this invention. For example, although not illustrated, power supply buses are understood to be included in the microcomputer system 10 of FIG. 1.
A second set of buses substantially identical to buses 18 through 26 is associated with second processor 14. These buses, 18', 20', 22', 24' and 26' correspond to buses 18 through 26 associated with processor 12. Each of processors 12 and 14 and the associated bus structures thereof is associated with certain peripheral components. Processor 12 is connected via bus structure 16 to input/output device 30 and to local memory 32. Processor 14 and its associated bus structure 16 are connected to input/output device number 34, input/output device 36 and local memory 38. It is to be understood that the connection between the processors and the associated equipment hereinabove described is conventional and will not, therefore, be described at great length herein. Briefly, the address buses 18 and 18' are supplied by the processors 12 and 14, respectively, with address information which is supplied to each device connected to the bus structure. The address present at any given time on the address bus will correspond to a particular address in a particular device and access will be gained to that device and to the particular location in the device to which the address corresponds. For example, a particular 16 bit address may correspond to a certain location in memory. Whenever the particular combination of bits appears on the address line that location in memory will be available to the processor. Buses 20 and 22 along with corresponding buses 20' and 22' are the data input and output buses. These buses provide paths between the devices for data to be transferred from one device to another. The data input and output buses carry the actual data between devices. For example, data may be written into or read from memory by providing a memory address on the address bus and providing data from the processor onto the data-out bus from which it is received by the addressed device. It will be appreciated that it may be required to supply to the memory further signals as exemplified by signals of the type carried by the read/write buses 24 and 24' before data can be entered into or recovered from memory or other device. Wait buses 26 and 26' provide signals from device requesting service when the device from which service is requested is unable to comply with a request. For example, if data is being supplied to an input/output device from a processor, it will often times be the case that the processor is able to supply the data at a speed greater than that at which the input/output device can utilize it. In order to prevent data from being lost, a wait signal is sent to the processor to moderate the rate of data flow from the processor to the input/output device to an extent that the data is supplied at a rate at which the input/output device can accept it. This same relationship may exist between any two devices when the speeds at which they are able to perform various operations are different. In addition to the devices hereinabove described, microcomputer 10 includes shared memory 40. Shared memory 40 is connected to the bus structures associated with both processor 12 and processor 14. In accordance with a presently preferred embodiment of this invention shared memory 40 includes a single memory accessible to both processor 12 and processor 14. It is a feature of this invention that shared memory 40 may appear to each of the processors to be a different portion of the total memory accessible by each processor.
An exemplary shared memory in accordance with a presently preferred embodiment of this invention is illustrated at FIG. 2. A memory 50 which may advantageously be a random access memory is provided having an address port 52, a data-in port 54, a data-out port 56, a read/write control port 58 and a memory enable port 60. As was hereinabove described in conjunction with the discussion of FIG. 1, each of the aforementioned address, data-in, data-out, read/write and memory enable ports may include one or more physical connections. Address port 52 of memory 50 is connected to tri-state buffers 62 and 64. Buffers 62 and 64 provide selective connection between the address port 52 of memory 50 and the appropriate address buses associated with the two processors accessing the memory. In accordance with this invention, the shared memory module of FIG. 2 may readily be employed in conjunction with a microcomputer structure of the type illustrated at FIG. 1 and the discussion hereinafter appearing will assume that the shared memory of FIG. 2 corresponds to shared memory 40 of FIG. 1. Accordingly, tri-state buffers 62 and 64 are connected to address buses 18 and 18' of FIG. 1. It will be appreciated that while tri-state buffers 62 and 64 are illustrated as single blocks, that multiple blocks are employed as required in order to accommodate multiple address connections. Tri-state buffers 62 and 64 are characterized by input terminals 66 and 68 respectively and output terminals 70 and 72. Tri-state buffer 62 is provided with gate input terminal 74 which in this particular embodiment of the invention is an inverting input terminal, that is to say one which activates tri-state buffer 62 when a ground or logical zero signal is applied thereto. Corresponding gate input terminal 76 is provided at tri-state buffer 64. Tri-state buffers 62 and 64 provide selective connection between inputs 66 and 68 and outputs 70 and 72. When a logical zero level signal is applied to gate input terminal 74, for example, a low impedance electrical connection is provided between input 66 and output 70. When gate terminal 74 is provided with a positive voltage, a logical one, no connection is provided between input 66 and output 70 and output 70 is permitted to float, that is is not connected to either a zero or a plus signal but rather is left in a substantially unterminated state. The operation of tri-state buffer 64 is identical. The function of tri-state buffers 62 and 64 may be readily visualized by analogy to an electrical relay of the single pole, single throw type wherein input and output terminals 66 and 70 are the contacts of the relay and gate terminal 74 provides connection to the coil of the relay. It will be appreciated by those skilled in the art that the function of tri-state buffers 62 and 64 might be provided in a variety of fashions and this invention is not intended to be limited to any particular method or apparatus for obtaining the function hereinabove described. For example, tri-state buffers such as the 8216 or 8226 manufactured by Intel Corp., Santa Clara, California may be utilized.
Additional tri-state buffers 78 and 80 provide selective connection to read/write input 58 of memory 50 from read/write inputs 82 and 84 respectively. Tri-state buffers 86 and 88 similarly provide connection to data-in port 54 from inputs 90 and 92 while buffers 94 and 96 provide connection from data-out port 56 of memory 50 to output terminals 98 and 100. It will be understood that as was the case with buffers 62 and 64 that buffers 78, 80, 86, 88, 94 and 96 may provide more than a single electrical connection to the appropriate buses. It will be appreciated that the nature of the buffers permits direct connection to the appropriate buses of the microcomputer systems. For example, buffer 62 is connected to bus 18, buffer 64 to bus 18', buffer 78 to bus 24, buffer 80 to bus 24', buffer 86 to bus 20, buffer 88 to bus 20', buffer 94 to bus 22 and buffer 96 to bus 22'. The shared memory of FIG. 2 further includes AND gates 102 and 104 which are adapted in accordance with this invention to be connected to that portion of buses 18 and 18' which carry the high order address bits. Those skilled in the art will appreciate that the address bus will carry a plurality of address bits in binary form. Visualizing the address data in parallel form, it will be appreciated that in the case wherein memory 50 includes a number of addresses smaller than the total number of addressable addresses by the processor that the higher order address bits will not be required in order to uniquely specify an address in memory 50 alone. They will, however, be necessary to distinguish the block of memory addresses represented by memory 50 from the remaining memory addresses accessible by the processor. Accordingly, the higher order address bits are applied to AND gates 102 and 104 which provide signals at outputs 106 and 108 thereof when memory 50 is addressed. Each of AND gates 102 and 104 includes a plurality of inputs 110 and 112, the precise number of which will differ depending upon the relative size of memory 50 and the addressing capability of the processor. As AND gates 102 and 104 provide outputs when each of the inputs thereof is at a high logic level, it will be appreciated that memory 50 will be accessed when the respective processor addresses the portion of memory having the highest address location. For example, wherein 16 bits are provided by the processor to the address bus and further wherein memory 50 includes, for example, 8000 addresses and further wherein the 8000 addresses are the highest 8000 addresses addressable by the processor, and still further that the 8000 addresses represent one-eighth of the total number of addresses addressable by the processor, then three binary bits are required to uniquely determine which of eight blocks of memory is addressed. Accordingly, in the embodiment of this invention illustrated at FIG. 2, the three highest order address bits are applied to inputs 110 of AND gate 102 and an output is produced at output 106 thereof when each of inputs 110 is high. It will be appreciated that any of the seven other blocks of memory will produce at least one bit at input 110 of AND gate 102 which is zero or low and no output will be produced at output 106. Where it is desired in accordance with this invention to address other than the highest group of memory addresses, inverters may be utilized between the high order portion of the address bus and AND gate 102 in order to provide an input at input 110 thereof which comprises three logical ones. It will be appreciated, therefore, that memory 50 may appear to the processor to be any of a number of blocks of memory locations. Further, gates 102 and 104 may be configured so that memory 50 appears to each of processors 12 and 14 to be a different portion of the memory addressable by the respective processors. For example, assume that three bits of address data are supplied to each of gates 102 and 104 and assume further that each of the bits applied to gate 104 is inverted before being connected to inputs 112 thereof. It will be appreciated that gate 104 will provide an output signal at output terminal 108 thereof whenever each of the high order address bits is zero rather than one and that memory 50 will appear to processor 14 to be the lowest 8000 memory addresses and to processor 12 to be the highest 8000 memory addresses.
NAND gates 116 and 118 provide the final connection to the bus structure of two processors at outputs 120 and 122 thereof, respectively. Output 120 is connected to wait bus 26 and output 122 to wait bus 26'. The shared memory of FIG. 2 may be seen to be connected only to the bus structures of the two portions of the multiprocessor microcomputer of FIG. 1. No additional control is required and no direct connection is made between the two bus structures.
The operation of the shared memory of FIG. 2 requires that a number of conditions be satisfied. Memory 50 may be addressed by either of processors 12 or 14 but may not be simultaneously addressed by both. When only one processor addresses the memory, the shared memory of FIG. 2 gives access to that processor. When both processors simultaneously require access to the memory that processor which most recently utilized the memory is given access. It will be appreciated that a request for service by a processor will be evidenced by a high output at either of outputs 106 or 108 of gates 102 and 104. For purposes of discussion, reference will be made to "high" and "low" signals. It will be understood that these references are to high and low logic level signals and do not necessarily refer to specific relative magnitudes. Those skilled in the art will recognize that high and low respectively refer to logical ones and zeros. Assume first that only output 106 of AND gate 102 is activated to produce a high signal thereat indicating that a processor 12 desires access to the memory. A high signal appears at output 106 of AND gate 102 and simultaneously at input 130 of NOR gate 132, input 138 of NAND gate 140 and input 142 of NAND gate 144. Since no service is being requested by processor 14 output 108 of AND gate 104 is low providing a low signal to: input 146 of inverter 148, input 150 of NAND gate 152 and input 154 of NAND gate 156. Inverter 136 provides a low signal to input 172 of NAND gate 152, output 174 of which will necessarily be high. Output 174 of NAND gate 152 is connected to input 164 of NAND gate 166 and provides a high signal thereto. Since input 146 of inverter 148 is low, output 158 thereof provides a high signal to input 160 of NAND gate 140. Since input 138 of NAND gate 140 is also high, output 162 thereof is low providing a low signal to input 176 of NAND gate 178 which insures that output 182 thereof is high. Output 182 is connected to input 167 of NAND gate 166 and since both inputs 164 and 167 are high, output 168 of NAND gate 166 is low providing a low signal to gate inputs 74 and 184 of tri-state buffers 62 and 78, respectively. Low logic signals are similarly provided to input 190 of tri-state buffer 86 and to input 192 of NAND gate 116 which provides a high signal at output 120 thereof. It will be recalled that NAND gates 116 and 118 are connected to the wait buses associated with processors 12 and 14, respectively. In accordance with this invention, a low signal will cause the processor to wait and a high signal will allow it to proceed. Accordingly, it will be appreciated that tri-state buffer 62 provides connection between input 66 thereof and output 70 thereby connecting address bus 18 to input 52 of memory 50. Similarly, input 82 of tri-state buffer 78 is connected to input 58 of memory 50 and input 90 of tri-state buffer 86 is connected to input 54 of memory 50. Thus, the appropriate address, read/write and data buses are connected to the memory. The selective activation of the memory for either accepting or providing data therefrom will be described hereinbelow.
The operation of the shared memory of FIG. 2 when service is required by processor 14 alone is similar to that hereinabove described and produces a low signal at output 182 of NAND gate 178 thereby activating tri-state buffers 64, 80 and 88 to provide connection to memory 50 of inputs 68, 84 and 92. The operation of the shared memory when service is simultaneously required by both processors 12 and 14 depends upon which processor has most recently had access to the memory. Assume that prior to the simultaneous request for services that a processor 12 has most recently addressed the memory. Output 168 of NAND gate 166 will provide a low signal while output 182 provides a high signal. Assume now that both AND gates 102 and 104 provide log signals indicating that neither processor requires service. A low signal is provided to NAND gate 140 while a high signal is provided to input 164 of NAND gate 166. Since input 167 of NAND gate 166 is connected to output 182 of NAND gate 178 which, it will be recalled, is providing a high signal, NAND gate 166 will remain in its previous state and produce a low signal at output 168 thereof. This low signal is connected to input 180 of NAND gate 178 assuring that a high signal continues to be produced at output 182 thereof. It will be seen that NAND gates 166 and 178 are connected in a flip-flop circuit relationship and will maintain a low and high signal, respectively, at the output thereof in the absence of service requests from either processor. Assume now that both processors require service. Both outputs 106 and 108 will be high thus providing high signals to inverters 136 and 148 which will, therefore, produce low signals at outputs 158 and 170, thereof, respectively, which low signals will insure that high signals are produced at outputs 162 and 174 which are coupled to inputs 176 and 164, respectively. It will be recalled that NAND gate 166 was previously in an "on" state producing a low signal at output 168 thereof and that NAND gate 178 was producing a high signal at output 182 thereof and it will be appreciated that these conditions will continue during the simultaneous request for service by both processors. The inputs to NAND gate 166 remaining high and inputs 180 and 176 of NAND gate 178 being low and high, respectively, thus producing a high output at output 182 of NAND gate 178.
Assume now that request is made only by processor 14 and that therefore output 106 is low and output 108 is high. High signals are applied to inverter 148 and input 150 of NAND gate 152. Low signals are applied to inverter 136 and input 138 of NAND gate 140. NAND gate 140 consequently produces a high signal at output 162 thereof while NAND gate 152 produces a low signal at output 174 thereof. The low signal appearing at output 174 of NAND gate 152 is connected to input 164 of NAND gate 166 which produces a high signal at output 168 thereof which is connected to input 180 of NAND gate 178. Since output 162 of NAND gate 140 is connected to input 176 of NAND gate 178, output 182 thereof changes to a low state and processor 14 is given access to the memory while access is removed from processor 12.
It will be appreciated that in accordance with this invention as hereinabove described access is given to either processor requesting it when requests appear one at a time and to the processor most recently having access when simultaneous requests are received. In this way, neither processor will be interrupted, during a transaction with memory, by a request from the other processor.
It is desirable to provide two modes of access to the memory, a first mode in which data is read into the memory from the processor or another device and the second mode wherein data is read out of the memory to the processor or the other device. The shared memory of FIG. 2 provides the necessary control to provide these two modes of access. It will be appreciated by those skilled in the art that the nature of electrical connection to memory 50 in order to accomplish the read and write operations is somewhat different. Particularly, data-out port 56 provides relatively low impedance signal sources, the logic levels of which determine the data supplied by memory 50. It will be appreciated therefore, that data-out port 56 must be isolated from the bus structure of the appropriate processor except when it is desired to read data from the memory. Data-in port 54 is adapted to receive data from the bus structure and is characterized by a relatively high impedance. It is, therefore, unnecessary during the time when a particular processor has access to the memory, to isolate port 54 while it is not actually in use. The distinction between data-in and data-out ports 54 and 56 may be more readily understood by considering that whenever data appears at port 56, it will essentially clamp the data bus to which it is connected to the data values in the particularly addressed memory location. Data-in bus 54, however, may be allowed to float since data will not be entered into memory except as determined by the signal applied to read/write port 58. Accordingly, data-out port 56 is connected to tri-state buffers 94 and 96 which are controlled by NAND gates 144 and 156, respectively. By way of example, and referring specifically now to NAND gate 144, it will be recalled that when processor 12 alone desires access to the memory, that a high signal is supplied to input 142 of NAND gate 144. It will be further recalled that output 168 of NAND gate 166 is low and it will be seen that this output is connected to input 191 of inverter 193 which provides a high input to input 194 of NAND gate 144. Output 196 of NAND gate 144 is connected to input 198 of tri-state buffer 94 which is energized to connect output terminal 98 to output terminal 56 of memory 50. Memory 50 is connected, therefore, to the output data bus only when an actual request for service is detected by NAND gate 102. It will be seen that tri-state buffers 86 and 88 remain actuated to connect the processor last receiving service to data-in port 54 of memory 50 even when no actual request for service is present. This is due to the flip-flop circuit arrangement of NAND gates 166 and 178. NAND gate 156 cooperates in a similar fashion with tri-state buffer 96 providing a low output signal from output 200 of NAND gate 156 to input 202 of tri-state buffer 96 whenever high signals are provided at inputs 204 and 154 of NAND gate 156. These signals are provided when AND gate 104 is activated by a request for service from processor 14 and further when NAND gate 178 provides a low signal at output 182 thereof which is inverted by inverter 206 to provide a high signal at output 208 thereof. Inputs 204 and 154 of NAND gate 156 both being high, output 200 thereof provides a low signal to activate tri-state buffer 96 and connect data-out port 56 to output 100 of tri-state buffer 96.
Read/write buses 24 and 24' are selectively connected to read/write port 58 of memory 50 by tri-state buffers 78 and 80. Buffers 78 and 80 are energized concurrently with buffers 62 and 64, respectively, and read/write buses 24 and 24' control the memory during those times when the corresponding address buses are connected to port 52 of memory 50.
Memory-enable port 60 is connected to output 210 of NOR gate 132, inputs 130 and 212 of which are connected to outputs 106 and 108 of AND gates 102 and 104, respectively. The memory is enabled by a high signal at output 210 of NOR gate 132 whenever either or both of AND gates 102 and 104 provides an output indicative of a request for service.
While the shared memory of FIG. 2 provides many advantages and will be readily appreciated by those skilled in the art to be quite widely applicable to any of a number of particular combinations of processors and memories commonly utilized, it is often times advantageous in accordance with this invention to provide certain specific additional features which substantially increase the efficiency of the shared memory. FIG. 3 illustrates a shared memory in accordance with this invention providing substantially all of the advnatages of the shared memory of FIG. 2 plus certain additional features. Referring specifically to FIG. 3 in which like reference numerals designate like elements with respect to FIG. 2, it will be seen that inverter 148 of FIG. 2 has been replaced by NAND gate 220 in FIG. 3. NAND gate 220 includes first input 222 which is connected to output 108 of AND gate 104 and second input 224 connected to input terminal 226. Inverter 136 is replaced by second NAND gate 228 which includes first and second terminals 230 and 232. Input 230 is connected to output 106 of AND gate 102 while input 232 is connected to input terminal 234. Input terminals 226 and 234 are adapted to be connected to the status busses of processors 14 and 12, respectively. The operation of the shared memory of FIG. 3 may be most readily understood by considering the nature of status information applied to inputs 226 and 234. It is emphasized that the following is exemplary, and while it applies to a particular microprocessor viz., an 8080 manufactured by Intel, other processors provide similar status information which may differ in form but which may be readily utilized by those skilled in the art by minor changes to the structure illustrated in FIG. 3. Status information indicates which of two states a microprocessor is in at a particular instant. These states are for convenience referred to as status and active states. During a status state, information is supplied at the data output port of a microprocessor indicative of the operation which will be accomplished during the succeeding active state. For example, read, write, input, output and interrupt operations may be indicated during the status period. Status and active microprocessor states occur in alternating fashion with the status state typically being somewhat shorter than the active state although this is not required in accordance with this invention. The signal applied to inputs 226 and 234 is a logic level signal having two conditions, a low condition during the status period and a high condition during the active period.
Three modes of operation are readily achievable by the shared memory structure of FIG. 3. In a first mode, one processor is chosen to have priority over the other. This is accomplished by connecting the input of the appropriate NAND gate 220 or 228 corresponding to the high priority processor permanently to a high logic signal. For example, assume that it is desired to give priority to processor 12. The NAND gate corresponding to processor 12 is NAND gate 228 and consequently input 234 is connected to a high logic level signal while input 226 is connected to the status output of processor 14. Since input 234 is permanently connected to a high logic level signal, whenever input 230 of NAND gate 228 is high, indicating a request for service by processor 12, a low signal will be produced at output 236 of NAND gate 228 and applied to input 172 of NAND gate 152. Input 226 is connected to the status output of processor 14 and since the status signal as hereinabove described changes alternately from a high to a low signal, it will be clear that when a request for service is present as indicated by a high signal at output 106 of AND gate 102, the flip-flop circuit comprising NAND gates 166 and 178 will be triggered during the next status period of processor 14 following a request for service by processor 12. On the other hand, assume that processor 12 has been for some time, and is requesting service. Since the status signal from processor 12 is not connected to NAND gate 228, but rather a permanently high logic signal is connected to input 232, processor 12 will retain connection to memory 50 so long as a service request is present at AND gate 102. A second mode of operation achieves equal priority by connecting both inputs 226 and 234 to a logic high signal. This mode of operation corresponds to the mode of operation of the embodiment of this invention illustrated in FIG. 2. It may be characterized as "lockout until done" operation and provides service to a processor so long as a request therefor is present.
A third and presently preferred system for assigning priority also gives equal priority to both processors but provides substantially increased efficiency of operation. In this mode, status signals are applied to inputs 226 and 234 from the respective processors 14 and 12. Assuming that requests for service are present at both of AND gates 102 and 104 autosynchronous operation is achieved. Service is provided to each processor in turn so long as the status information therefrom indicates an active mode of operation. Service is switched to the other processor at the termination of the active mode and beginning of the status mode. In the particular case when the status and active modes are equal in length, synchronous operation will be achieved with memory service being provided alternately to the two processors during substantially 100% of the time. Where the status and active periods are of different lengths, presumably the status period being shorter, a certain amount of waiting time is necessary. It has been found that a shared memory in accordance with this invention provides nearly ideal memory utilization for processors of the type having alternating status and active periods and allows each processor to utilize the memory during the periods when it is not required by the other, thus eliminating what has heretofore been approximately 50% wasted time with respect to the memory. The shared memory of FIG. 3 includes another feature of this invention which will be useful in conjunction with certain specific embodiments hereof. Memory read inputs 240 and 242 are connected to additional inputs 244 and 246 of NAND gates 144 and 156. Certain microcomputer systems employ identical addresses for specific memory locations and also for input data locations. It is necessary that a memory for utilization in conjunction with a computer of this type provide means for distinguishing between memory addresses and input addresses. Memory read terminals 240 and 242 provide this function. Signals are applied to inputs 240 and 242 from processors 12 and 14, respectively, indicative of whether the address provided by the processor is a memory address or input address. A high logic signal applied to input 240 indicates that the address provided by the processor is a memory address while a low input to input 240 indicates that an input address is being provided. The signal applied to input 242 is identical but is derived from processor 14. It will be seen that the addition of memory read information increases the capability of a microcomputer system in accordance with this invention in that a smaller number of addresses and consequently a smaller number of address bits is required to provide access to both the memory and a large number of input devices. When a high logic level signal is provided at memory read input 240, for example, and further when a request for service is received at AND gate 102 providing a high signal at output 106 thereof which is applied to input 142 of NAND gate 144 and still further when a low signal is provided at output 168 of NAND gate 166 which low signal is inverted by inverter 193 and applied to input 194 of NAND gate 144 tri-state buffer 94 is activated by a low signal applied to input 198 thereof to connect data output 56 to output terminal 98 which is connected to the data-in bus of the microcomputer system. Tri-state buffer 96 is similarly actuated by the conjunctive existence of logical high signals at inputs 246, 204 and 154 of NAND gate 156. It will be seen that whenever either of memory read inputs 240 and 242 is low that tri-state buffers 94 and 96 cannot be actuated and outputs 98 and 100 thereof remain in a high impedance state and thus do not interfere with the acquisition of the data by the processor from the addressed input device.
It will be appreciated by those skilled in the art that either or both of the features of this invention illustrated at FIG. 3, viz. the assignment of priority through utilization of status information, and the increase in addressing capability through the use of memory read information, may be applied in accordance with this invention to a shared memory as illustrated herein. It is further emphasized that neither of these features is required and that neither depends upon the other.
A shared memory in accordance with this invention may readily be configured to provide the capability for sharing memory among three or more processors. FIG. 4 illustrates an embodiment of this invention wherein provision is made for connecting three processors to a single memory while retaining all the features and advantages of the shared memory of FIG. 3. The shared memory of FIG. 4 includes both the utilization of status information and the further utilization of memory read information hereinabove described in conjunction with the shared memory of FIG. 3. In FIG. 4, like reference numerals denote like elements with respect to FIGS. 2 and 3. The operation of the shared memory of FIG. 4 is substantially identical to that of FIG. 3 except for the addition of certain logical elements in order to provide for the simultaneous connection of the shared memory to three processors. Accordingly, FIG. 4 will be described in somewhat less detail than FIG. 3, the principles of operation thereof being equally applicable to FIG. 4. The distinctions between FIGS. 3 and 4 will, however, be clearly described hereinbelow.
The shared memory of FIG. 4 designated generally at 300, includes additional tri-state buffers 302, 304, 306 and 308 which provide selective connection to the address, read/write, data-in and data-out buses, respectively, of a third processor. Tri-state buffers 302, 304, 306 and 308 correspond and are substantially identical to the existing buffers which selectively connect the address, read/write, data-in and data-out buses of the first and second processors to memory 50. Shared memory 300 further includes additional AND gate 310 for connecting the high order address bits of the third processor to the shared memory, NAND gate 312 for connection to the wait bus of the third processor, and NAND gate 314 for connection to the memory read bus of the third processor. NAND gates 320, 322 and 324 are connected to the outputs of AND gates 102, 104 and 310 while OR gates 326, 328 and 330 are connected to NAND gates 116, 118 and 312, respectively, which provide wait signals to the three processors. Status signals are applied to inputs 340, 342 and 344 which are connected to NAND gates 320, 322 and 324, respectively.
The operation of shared memory 300 may be readily understood by considering several exemplary operating conditions. In order to simplify the discussion to follow, the microprocessors which are utilized in conjunction with shared memory 300 will be designated 1, 2 and 3. Microprocessor 1 is connected to tri-state buffers 62, 78, 86, and 94. It is further connected to AND gate 102, NAND gate 116, memory read input 240, and status input 340. Microprocessor number 2 is connected to tri-state buffers 64, 80, 88 and 96. Processor 2 is further connected to memory read-input 242, NAND gate 118, AND gate 104 and status input 342. Processor 3 is connected to tri-state buffers 302, 304, 306 and 308. It is further connected to memory read input 346, AND gate 310, NAND gate 312 and status input 344. Assume now that a request for service is indicated by application of high logic signals to the inputs of AND gate 102. Assume further that processors 2 and 3 do not require service and therefore that gates 104 and 310 provide low logic signals at the outputs thereof. High signals are supplied to NAND gate 320, NAND gate 348 and NAND gate 144. Input 340 will supply a high signal to NAND gate 320 when computer 1 is in the active mode and NAND gate 360 will supply a high signal to the last input of NAND gate 320 whenever processor 1 was the last processor having access to the memory. When all three inputs to NAND gate 320 are high, a low output will be produced thereby which low output is applied to NAND gate 350 and 352 thereby preventing either of flip-flops 362 or 364 from being set. For purposes of convenience, NAND gates 366 and 368 will be collectively referred to as flip-flop 362 while NAND gates 370 and 372 will be referred to as flip-flop 364. Similarly, NAND gates 360 and 374 comprise flip-flop 376. Each of these flip-flops is identical and is SET by applying a logical low signal to a first input of each of the flip-flops which input is input 378 in the case of flip-flop 376, 380 in the case of flip-flop 362 and 382 in the case of flip-flop 364. It will be seen that applying a zero to any of these inputs produces a one at the corresponding outputs of NAND gates 360, 366 and 370 when any of the flip-flops are SET and a low level signal is applied to the appropriate tri-state buffers associated with the corresponding processor. It will be understood that flip-flop 376 corresponds to processor 1, flip-flop 362 to processor 2 and flip-flop 364 to processor 3. It will be further understood that each flip-flop is RESET by the application of a low logic signal to the input of NAND gate 374, 368 or 372. Each of flip-flops 376, 362 and 364 will remain in either the SET or RESET condition indefinitely in the absence of additional signals thereto. AND gates 384, 386 and 388 provide the RESET signal to the flip-flop. Each of these AND gates includes two inputs, one input from each of NAND gates 348, 350 and 352 with which it is not associated. AND gate 384 is associated with NAND gate 348, AND gate 386 with NAND gate 350 and AND gate 388 with NAND gate 352. Therefore, for example, AND gate 384 has a first input from NAND gate 352 and a second input from NAND gate 350. It will be appreciated that whenever either of these inputs is zero, a zero will be produced at the output of AND gate 384 thus preventing flip-flop 376 from being SET. Therefore, whenever either of processors 2 or 3 has access to memory 50, processor 1 cannot gain access and interrupt the SET access. AND gates 386 and 388 are similarly connected. The ability of the shared memory of FIG. 4 to prevent the interruption of a transaction between a processor and memory prevents the premature interruption of a transaction with memory.
Memory 300 includes a system for determining which of two requests for memory will be accommodated. Consider, for example, that requests for service are received from processors 1 and 2 thus producing high logic level signals at the outputs of AND gates 102 and 104, respectively. Assume further that processor 2 last had access to memory 50 and that flip-flop 362 therefore is set producing a low output at the output of NAND gate 368 and a high output at the output of NAND gate 366. Assume further that flip-flops 376 and 364 are RESET producing low signals at the outputs of NAND gates 360 and 370. These low signals are applied to NAND gates 320 and 324, respectively, which provide high signals at the outputs thereof which high signals are connected to NAND gate 350. Since requests for service are received from processors 1 and 2 thus providing high signals at the outputs of AND gates 102 and 104, the outputs of NAND gates 320, 322 and 324 are high, low and high, respectively, assuming that the status signals applied to inputs 340, 342 and 344 are all high. NAND gate 322 provides low signals to NAND gates 348 and 352 thus inhibiting each of flip-flops 376 and 364 from being set and only flip-flop 362 can be SET. As has been described, all of the inputs to NAND gate 350 are high thereby producing a low output thereat which SETS flip-flop 362 and connects processor 2 to memory 50.
Those skilled in the art will appreciate that the status inputs applied to inputs 340, 342 and 344 become important only when simultaneous requests for service are present from two or more processors. When this is the case, access to memory is provided to a processor only so long as its status information indicates an active mode, and access is removed and supplied to the other processor when a status mode is indicated by the first processor.
The operation of NAND gates 144, 156 and 314 corresponds substantially to the corresponding gates in FIGS. 2 and 3. Each of the gates provides a low logic signal at the output thereof during the coincidence of: a memory read signal applied to inputs 240, 242 and 346; a request for service supplied from AND gates 102, 104 and 310 and a SET condition of flip-flops 376, 362 and 364. The operation of a multiprocessor shared memory utilizing a memory read signal was hereinabove described and will not be repeated. NOR gate 390 provides a low logic level memory enable signal whenever any of AND gates 102, 104 or 310 indicates a request for service by the presence of a high logic signal at the output thereof.
OR gates 326, 328 and 330 supply signals to NAND gates 116, 118 and 312, respectively, whenever any of flip-flops 376, 362 and 364 are SET. For example, OR gate 326 provides a high signal to NAND gate 116 whenever either of flip-flops 362 or 364 is SET. Similarly, OR gate 328 provides a high signal to NAND gate 116 whenever either of flip-flops 376 or 364 is SET. Further, OR gate 330 provides a high signal to NAND gate 312 whenever either of flip-flops 376 or 362 is SET. The coincidence of a high signal from one of OR gates 326, 328 and 330 with a request for service as indicated by a high signal from AND gates 102, 104 or 310 provides a wait signal at the output of one or more of NAND gates 116, 118 and 312 indicating to the appropriate processor that although service is requested, one of the other processors is currently utilizing the memory and, therefore, the requesting processor must wait.
Those skilled in the art will appreciate that under certain conditions simultaneous requests for service may be received from two processors neither of which was the last to have access to memory 50. While memory 300 will provide service to one of the requesting processors on a more or less random basis, it may be desirable to provide prioritized access. Accordingly, in accordance with this invention, it may be desirable to provide capacitors connected from the outputs of NAND gates 348, 350 and 352 to ground. These capacitors will provide a certain delay in response of NAND gates 348, 350 and 352 according to the size of the capacitor. In accordance with this invention, the microprocessor associated NAND gate which is desired to have the highest priority is provided with the smallest or no capacitor while the second priority processor associated NAND gate is provided with a somewhat larger capacitor and the final processor associated NAND gate is provided with a largest capacitor.
One skilled in the art will readily discern the nature of the response of shared memory 300 to a variety of requests for service conditions by reference to FIG. 4. It is, therefore, not deemed necessary to describe particular operating conditions in further detail. It will further be appreciated that reference to FIGS. 2-4 and the discussions corresponding thereto will enable one skilled in the art to expand, where desired, a shared memory in accordance with this invention to accommodate a larger number of processors than included in any of the examples herein.
A shared memory has been described in accordance with this invention which provides many advantages over prior art memories. Operation of a shared memory in accordance herewith is possible utilizing only the bus interconnected structures of a number of microcomputers without the need for further interconnections therebetween or control of one by the other. A shared memory in accordance with this invention provides increased efficiency, speed of operation and reliability without the need for modification with any of the microprocessors with which it is associated.
Many of the features hereinabove described in conjunction with the description of this invention provide unique solutions to a number of problems. For example, as has been described a shared memory in accordance with this invention may provide the appearance of different address locations to different processors. Further, means have been outlined to provide, in a simple and straight-forward way, a method for establishing priority between two or more processors. Synchronized operation through the utilization of status information supplied by two or more processors connected to a single shared memory in accordance with this invention is yet another feature provided herein. Applications of shared memories in accordance with this invention are limited only by the needs of the user. For example, in a simple two processor system, a first processor may be utilized to perform arithmetic operations on data while a second processor connected to the same shared memory with the first processor may be utilized to format the data for output in a usable form. This provides the advantage that the first processor may provide substantially real-time output data from a variety of inputs while the second processor accomplishes the formating of the output. Similarly, data may be transferred between processors in a more efficient manner than has been heretofore possible. The processor having the data may transfer to memory as the data is available and need not wait until the other processor is ready to receive it. Similarly, the receiving processor may read the data from memory at any time after it has been transferred and need not interrupt any operations occurring therein due to a need for simultaneous availability of two processors for transfer.
Shared memories in accordance with this invention may be utilized in a variety of ways to provide multi-processor systems. For example, as has been hereinabove described multiple processors may be connected to a single memory or, in the alternative, memories and processors may be connected in a chain-type structure, a single processor being connected to two memories and each memory being connected to two processors, the connections between processors and memories being of the type illustrated in FIG. 1 where, for example, processor 14 is connected to a second shared memory which, in turn, is connected to a yet another processor in the manner shown and described.
While the invention has been particularly shown and described with reference to several preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the true spirit and scope of the invention as defined by the appended claims.
|Cited Patent
|Filing date
|Publication date
|Jul 14, 1967
|May 20, 1969
|Communication arrangement in data processing system
|Dec 2, 1965
|Sep 23, 1969
|Hughes Aircraft Co
|Interlocking means for a multi-processor system
|Feb 28, 1967
|Apr 7, 1970
|Gen Electric
|Data storage access control apparatus for a multicomputer system
|Oct 11, 1967
|Jan 12, 1971
|Burroughs Corp
|Multiprocessor digital computer system with address modification during program execution
|Jun 10, 1969
|Feb 2, 1971
|Arrangement for effecting vector mode operation in multiprocessing systems
|Aug 10, 1970
|Oct 17, 1972
|Control Data Corp
|Adaptive data priority generator
|Jan 6, 1971
|Dec 12, 1972
|Fujitsu Ltd
|Multiprocessor type information processing system with control table usage indicator
|Aug 25, 1971
|May 22, 1973
|High speed buffer operation in a multi-processing system
|May 8, 1972
|Sep 25, 1973
|Philips Corp
|Bus transport system for selection information and data
|Nov 5, 1973
|Oct 29, 1974
|Honeywell Inf Systems
|Cache store clearing operation for multiprocessor mode
|Jun 29, 1973
|May 27, 1975
|Shared data controlled by a plurality of users
|Nov 16, 1973
|Jun 10, 1975
|Sperry Rand Corp
|Common storage controller for dual processor system
|Sep 25, 1973
|Jul 22, 1975
|Texas Instruments Inc
|Synchronous multi-processor system utilizing a single external memory unit
|Oct 12, 1973
|Nov 18, 1975
|Burroughs Corp
|Multirequest grouping computer interface
|Sep 25, 1974
|Jan 6, 1976
|Data General Corporation
|Data processing system
|Nov 5, 1973
|Feb 24, 1976
|Digital Equipment Corporation
|Interconnecting unit for independently operable data processing systems
|Aug 5, 1974
|May 25, 1976
|Gte Automatic Electric Laboratories Incorporated
|Multiprocessing system implemented with microprocessors
|Apr 16, 1974
|Sep 21, 1976
|International Business Machines Corporation
|Prefixing in a multiprocessing system
|Jun 30, 1975
|Dec 28, 1976
|Honeywell Information Systems, Inc.
|Data processing system providing locked operation of shared resources
|Feb 13, 1976
|Oct 25, 1977
|Digital Equipment Corporation
|Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
|Title not available
|Citing Patent
|Filing date
|Publication date
|Jun 16, 1978
|Jun 30, 1981
|Gould Inc. Modicon Division
|Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
|Jun 9, 1980
|Jul 21, 1981
|General Electric Company
|Dedicated microcomputer-based control system for steam turbine-generators
|Aug 21, 1979
|Apr 13, 1982
|International Business Machines Corporation
|Parallel storage access by multiprocessors
|May 19, 1980
|Jun 7, 1983
|Data General Corporation
|Masterless and contentionless computer network
|Dec 17, 1980
|May 1, 1984
|Texas Instruments Incorporated
|Multiple register digital processor system with shared and independent input and output interface
|Oct 5, 1981
|May 15, 1984
|Digital Equipment Corporation
|Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
|May 14, 1981
|May 22, 1984
|Texas Instruments Incorporated
|Multiprocessor with dedicated display
|Sep 30, 1981
|Sep 4, 1984
|British Broadcasting Corporation
|Real-time data sampling with memory sharing by high speed I/O processor and cycle stealing support processor
|Dec 15, 1980
|Jan 1, 1985
|Texas Instruments Incorporated
|Plurality of processors sharing the memory, the arithmetic logic unit and control circuitry all on a single semiconductor chip
|Feb 22, 1982
|Jan 1, 1985
|International Business Machines Corporation
|Data processing system having shared memory
|Jan 17, 1983
|Mar 18, 1986
|Automatix Incorporated
|Vision system
|May 7, 1984
|May 20, 1986
|Burroughs Corporation
|Memory control circuit for subsystem controller
|Mar 23, 1983
|May 27, 1986
|The United States Of America As Represented By The Secretary Of The Air Force
|Plurality of processors where access to the common memory requires only a single clock interval
|May 20, 1983
|Oct 7, 1986
|International Business Machines Corporation
|Communicating random access memory
|Jul 28, 1983
|Jan 6, 1987
|Harris Corporation
|Fault detection and redundancy management system
|May 20, 1982
|May 5, 1987
|Fanuc Ltd.
|Sequence controller
|Nov 9, 1982
|Oct 6, 1987
|Texas Instruments Incorporated
|Multiprocessor interface device
|Sep 4, 1984
|Nov 24, 1987
|Nec Corporation
|Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memory
|Mar 31, 1986
|May 24, 1988
|Halliburton Company
|Data acquisition module and method
|Mar 31, 1986
|Jun 14, 1988
|Halliburton Company
|Local area network data transfer system
|Feb 14, 1986
|Jul 5, 1988
|Prime Computer, Inc.
|Method and apparatus for high bandwidth shared memory
|Jan 17, 1986
|Feb 7, 1989
|Panafacom Limited
|Multiprocessor system having common memory
|Aug 6, 1986
|Mar 7, 1989
|Canon Kabushiki Kaisha
|Control device for control of multi-function control units in an image processing apparatus
|Jan 7, 1988
|Mar 28, 1989
|Thomas Engineering, Inc.
|Pharmaceutical tablet press control mechanism
|Mar 23, 1988
|May 23, 1989
|International Business Machines Corporation
|Logical arrangement for controlling use of different system displays by main processor and co-processor
|Feb 23, 1988
|Jun 27, 1989
|Sony Corp.
|Digital control bus system
|Jan 7, 1988
|Jul 4, 1989
|American Telephone And Telegraph Company, At&T Bell Laboratories
|Feeder monitor arrangement for stored program controlled rectifier plant
|Apr 24, 1987
|Aug 29, 1989
|International Business Machines Corp.
|Architecture for a distributive microprocessing system
|Aug 6, 1986
|Nov 28, 1989
|Voest-Alpine Automotive Gesellschaft Mbh
|Microcomputer system for regulating internal combustion vehicular engines
|Dec 5, 1988
|Jun 12, 1990
|Texas Instruments Incorporated
|Method for assigning priority to read and write requests received closely in time
|May 10, 1988
|Aug 14, 1990
|Battelle Memorial Institute
|Parallel processor-based raster graphics system architecture
|Aug 30, 1989
|Feb 5, 1991
|Encore Computer Corporation
|Real-time data processing system
|Sep 11, 1989
|Oct 22, 1991
|Elettronica San Giorgio-Elsag S.P.A.
|High-capacity memory having extended addressing capacity in a multiprocessing system
|Jan 17, 1991
|Dec 10, 1991
|Encore Computer U.S., Inc.
|Real-time data processing system
|Sep 19, 1988
|Dec 17, 1991
|Fujitsu Limited
|Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles
|Sep 29, 1989
|Dec 24, 1991
|Motorola, Inc.
|Memory access serialization as an MMU page attribute
|Jun 6, 1990
|May 19, 1992
|Ncr Corporation
|Dual port memory system
|Apr 8, 1991
|Aug 25, 1992
|Cray Research, Inc.
|Apparatus for sharing memory in a multiprocessor system
|May 31, 1991
|Nov 3, 1992
|International Business Machines Corporation
|Computer system with input/output cache
|Jun 20, 1988
|Apr 6, 1993
|Hitachi, Ltd.
|Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor
|Sep 12, 1990
|Apr 27, 1993
|Cray Research, Inc.
|Fault tolerant networking architecture
|Apr 27, 1992
|Sep 21, 1993
|International Business Machines Corporation
|Computer system having different communications facilities and data transfer processes between different computers
|Jun 1, 1990
|Sep 21, 1993
|Cray Research, Inc.
|Method and apparatus for sharing memory in a multiprocessor system
|Sep 11, 1991
|Oct 19, 1993
|Encore Computer U.S., Inc.
|Multiprocessor system with reflective memory data transfer device
|Sep 19, 1988
|Jan 4, 1994
|Princeton University
|Oblivious memory computer networking
|Jul 24, 1992
|Mar 8, 1994
|International Business Machines Corporation
|Computer system with input/output cache
|Nov 27, 1989
|Apr 26, 1994
|Nec Corporation
|Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed
|Jun 11, 1993
|Jun 28, 1994
|International Business Machines Corporation
|System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory
|Mar 19, 1993
|Jul 19, 1994
|Pitney Bowes Inc.
|Mail processing system controller
|Dec 14, 1992
|Aug 23, 1994
|Motorola, Inc.
|Device for assigning a shared resource in a data processing system
|Jul 25, 1994
|Jun 27, 1995
|Dow Benelux N.V.
|Secure communication system for re-establishing time limited communication between first and second computers before communication time period expiration using new random number
|Jul 12, 1994
|May 21, 1996
|The Dow Chemical Company
|Intelligent process control communication system and method having capability to time align corresponding data sets
|Sep 28, 1990
|Jun 18, 1996
|Siemens Aktiengesellschaft
|Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory
|Nov 28, 1994
|Sep 10, 1996
|Olympus Optical Co., Ltd.
|Sewing treatment and management system using electronic data processing apparatus
|Feb 21, 1995
|Oct 1, 1996
|The Dow Chemical Company
|System and method for determining whether to transmit command to control computer by checking status of enable indicator associated with variable identified in the command
|Jun 7, 1995
|Oct 22, 1996
|The Dow Chemical Company
|Stealth interface for process control computers
|Oct 13, 1993
|Dec 3, 1996
|Encore Computer, U.S., Inc.
|Multiprocessor system with reflective memory data transfer device
|Mar 24, 1995
|Mar 4, 1997
|Cirrus Logic, Inc.
|Reset based computer bus identification method and circuit resilient to power transience
|Apr 21, 1994
|Mar 10, 1998
|Fanuc Ltd.
|Combined two computer system
|Jul 1, 1996
|Jun 23, 1998
|Advanced Micro Devices, Inc.
|Apparatus having signal processors for providing respective signals to master processor to notify that newly written data can be obtained from one or more memories
|Dec 13, 1995
|Sep 1, 1998
|International Business Machines Corp.
|Status handling for transfer of data blocks between a local side and a host side
|May 22, 1995
|Jun 29, 1999
|Lsi Logic Corporation
|Method and apparatus for transferring data between two devices with reduced microprocessor overhead
|Dec 23, 1997
|Jul 11, 2000
|Deltatrak, Inc.
|Environmental data logging system
|Jan 27, 1998
|Feb 13, 2001
|Sgs-Thomson Microelectronics S.A.
|Circuit for the management of memories in a multiple-user environment with access request and priority
|Jan 19, 1993
|May 8, 2001
|Canon Kabushiki Kaisha
|Container-based method for exchanging information between computer processes
|Apr 28, 2000
|Nov 18, 2003
|Hewlett-Packard Development Company, L.P.
|Method and apparatus for preventing deadlock in a distributed shared memory system
|Feb 27, 2002
|Jul 20, 2004
|Hitachi, Ltd.
|Data processor having an address translation circuit
|Jul 10, 1997
|Apr 11, 2006
|Gerard Chauvel
|Protocol processor intended for the execution of a collection of instructions in a reduced number of operations
|Sep 8, 2003
|Aug 7, 2007
|Nec Electronics Corporation
|Data processing apparatus that shares a single semiconductor memory circuit among multiple data processing units
|Jan 18, 2008
|Oct 28, 2014
|Sick Stegmann Gmbh
|Process and device for the parameterization of measuring device
|Apr 19, 2002
|Oct 31, 2002
|Peltier Michael G.
|Collective memory network for parallel processing and method therefor
|Feb 27, 2002
|Dec 5, 2002
|Makoto Saen
|Data processor having an address translation circuit
|Sep 8, 2003
|Mar 11, 2004
|Masakatsu Uneme
|Data processing apparatus
|Aug 19, 2003
|Jun 3, 2004
|Yoshihiro Nishida
|Computer system and memory control method
|Jan 18, 2008
|Jul 24, 2008
|Josef Siraky
|Process and device for the parameterization of measuring device
|Oct 18, 1982
|Apr 19, 1984
|Licentia Gmbh
|Method and arrangement for controlling the coupling between two digital processor systems which are jointly or separately clocked
|Oct 27, 1981
|Aug 15, 1984
|International Business Machines Corporation
|Electronic document distribution terminal
|Dec 13, 1982
|Jul 18, 1984
|Fraunhofer-Gesellschaft Zur F�rderung Der Angewandten Forschung E.V.
|Coupler for processors
|Dec 2, 1983
|Jul 18, 1984
|Digital Equipment Corporation
|Address conversion unit for multiprocessor system
|Dec 2, 1983
|Jan 14, 1987
|Digital Equipment Corporation
|Address conversion unit for multiprocessor system
|Apr 18, 1984
|Oct 31, 1984
|Cray Research, Inc.
|Computer vector multiprocessing control
|Apr 18, 1984
|Apr 27, 1988
|Cray Research Inc
|Computer vector multiprocessing control
|Sep 22, 1982
|Apr 14, 1983
|Digital Equipment Corp
|Interface mechanism between host processor and peripheral-controlling processor
|Apr 28, 1999
|Nov 2, 2000
|Foreman Richard L
|Environmental data logging system
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification


text:
RENO, Nev. -- A bomb threat made in the early morning in Reno, Nev. delayed the University of Nevada's women's basketball game against UNLV and caused the school's morning commencement ceremonies to be pushed back to 2 p.m.
Staff at the Lawlor Events Center were unable to put in place the basketball court until 7 p.m. because of the delayed graduation ceremony. Team warm-ups will take place once the court is set up, and the game will begin after another half-hour, barring further delays.
No other changes have been planned for the regular sequence of the game.

subset: commoncrawl


text:
|Message view
|« Date » · « Thread »
|« Date » · « Thread »
|"David Jencks (JIRA)" <...@geronimo.apache.org>
|[jira] Created: (GERONIMO-561) Connection obtained in Synchronization.afterCompletion gets associated w/tx context
|Tue, 01 Feb 2005 00:21:19 GMT
Connection obtained in Synchronization.afterCompletion gets associated w/tx context ----------------------------------------------------------------------------------- Key: GERONIMO-561 URL: http://issues.apache.org/jira/browse/GERONIMO-561 Project: Apache Geronimo Type: Bug Components: connector Versions: 1.0-M3 Reporter: David Jencks Assigned to: David Jencks If you have code like this in a Synchronization.afterCompletion: Connection c = ds.getConnection(); //do something c.close(); it gets added to the connection tracking of the transaction context that just ended. c.close() returns it to the pool, properly, but the end-of-tx cleanup returns it to the pool a second time. The connection should not be tracked by the transaction context, the transaction is over. -- This message is automatically generated by JIRA. - If you think it was sent incorrectly contact one of the administrators: http://issues.apache.org/jira/secure/Administrators.jspa - If you want more information on JIRA, or have a bug to report see: http://www.atlassian.com/software/jira
|View raw message


text:
Four-letter racing game news now, with developer Asobo talking up the tech it's concocted for its open-world racer, Fuel. The in-game map, a blend of satellite information and procedurally generated data which stretches across 5,000 virtual square miles, would reportedly be a couch potato's worst nightmare if assembled via traditional means. "In the context of that map, which is one small corner of it, when the guys showed us this technology, if you were to build it in a traditional manner it would fill about four Blu-rays," Fuel producer David Brickley tells VideoGamer.com. "A gargantuan amount of data, just enormous."
That last word is what we'd normally use to describe, say, Burnout's Paradise City, but Brickley seems to imply that we need a change of perspective: "I did a little Power Point internally to do it and it zoomed them [Fuel and Paradise City] in to each other. It's like a little postage stamp because I think it does like four kilometres or something." Well, Criterion, it seems come 2009, you'll be licked in terms of sheer size. But will there be a restart option?


text: Hi, Received the I1 in January -- but have been too busy on other stuff to use it. I seem to remember getting some prop locks in the mail...but can't find them (ugh!)...and I just received the quick release props in teh mail with the one-time use warning. So my questions are: 1. Am I missing any other items? 2. Which is better - prop locks or quick release (I willl want to rebox my I1 after each outing). 3. I presume I have to upgrade my firmware on everything...can I go from stock to current or do I need any intermediate upgrades first? 4. Any significant capability upgrades or user warnings since January? Thanks! s.


text:
How to Sew Little Felt Animals
Sorry, this item is out of stock
Colorful, strong and easy-to-use, felt is the perfect material to make this collection of charming classic woodland animals. Follow the clear step-by-step instructions to create a group of endearing little creatures that you will want to make and keep. Sue Quinn, 128 pages, paperback.


text:
BRASELTON, Ga. - The American Le Mans Series begins a stretch of five races in seven weeks this weekend and strong fields of professional sports car racing teams are expected for all of the events. Thirty-seven cars are on hand at Infineon...
BRASELTON, Ga. - The American Le Mans Series begins a stretch of five races in seven weeks this weekend and strong fields of professional sports car racing teams are expected for all of the events.
Thirty-seven cars are on hand at Infineon Raceway in Sonoma, Calif., for this weekend's running of the Infineon Grand Prix of Sonoma. Testing gets underway on Friday, with official practice and qualifying set for Saturday. The two-hour, 45-minute timed race starts at noon (PDT) on Sunday.
The series will move to Canada for the next two races, with 36 cars entered for the Aug. 1-3 running of Le Grand Prix de Trois-Rivieres at Trois-Rivieres, Quebec, and 37 entered for the Aug. 15-17 Grand Prix of Mosport at Mosport International Raceway near Toronto. The recent Chevy Grand Prix of Atlanta at Road Atlanta started 35 cars only two weeks after many of those teams had competed in the 24 Hours of Le Mans in France, and 55 cars started the Mobil 1 Twelve Hours of Sebring that opened the season in March.
"At a time when many more-established racing series are struggling with low car counts, the American Le Mans Series is enjoying some of the strongest fields ever assembled for professional sports car racing in North America," said Scott Atherton, President and CEO of the ALMS. "It's not just the number of cars, but also the quality of the cars and teams that pleases us. These are truly world-class racing teams.
"In these challenging economic times, the fact that we have formal season-long commitments from more race teams this season than ever before speaks volumes for the health of the American Le Mans Series," he said. "We will continue to steer the course we have chosen for the future."
Following the swing through Canada, the American Le Mans Series will be at Road America in Elkhart Lake, Wis., Aug. 22-24 and then at Mazda Raceway Laguna Seca in Monterey, Calif., Sep. 5-7.
Four classes of American Le Mans Series sports cars will compete in the Infineon Grand Prix of Sonoma, presented by the Napa Valley Marriott Hotel & Spa and Foster's Lager. The field will include the fast and exotic Prototypes of the P900 and P675 classes, as well as the production-based cars of the GTS and GT classes.
The race will be broadcast live by the American Le Mans Series Radio Web online at www.americanlemans.com. NBC Sports will have live television coverage in North America beginning at 4 p.m. (EDT).
Ticket information is available online at www.infineonraceway.com or by calling the Infineon Raceway ticket office at 1-800-870-RACE.


text:
Video Switched Up (REACTION) YICReacts By Nasty C, here is the fans reaction to nasty c switched up single as YICReacts to Nasty C – Switched Up (Official Music Video) reaction!
If you are a music artist, be it upcoming or famous you and you wish to drop your music for fans to access online. You can Send your song to email@example.com for help or Call Peterumimo on 08035685110 or Wale on 08137199036.
More music is now available for download free on 9jamusicbox.com. Download more of latest music free today.You could also enjoy free music promo.
Always visit us for all naija latest music
Video Switched Up (REACTION) YICReacts By Nasty C


text:
Brookdale Edina also offers unparalleled services and amenities. As a resident, you'll have a selection of activities and clubs to share with friends and neighbors. Join one of our shopping trips to local stores and boutiques, take a swim in our indoor, heated swimming pool, or meet friends for Happy Hour on our outdoor patio under the glass atrium of Edinborough Park. At Brookdale Edina, it all comes together with our calendar of social gatherings, activities and outings, just one of the many amenities you'll enjoy as a resident.
Fitness and wellness programs are an important part of our commitment to our residents' experience at Brookdale Mt. Lebanon. Brookdale's Optimum Life is a holistic initiative that balances six key dimensions of wellness – purposeful, emotional, physical, social, spiritual and intellectual — to help you live a lifestyle that promotes health, wholeness and fulfillment.
Meaningful relationships live here every day. Our associates build lasting connections with residents, while providing exceptional service and care. For our associates, this opportunity to serve others is more than a job — it's a passion.
Live the life you choose with the care options you may need. Our community offers your choice of care with Independent Living, Assisted Living, and Memory Care accommodations.
At Brookdale Edina, trade the work and expense of house maintenance for a well-appointed residence that serves you. Let us take care of the chores, while you relax and enjoy a well-deserved retirement. Our Independent Living lifestyle offers refined amenities, attentive service and engaging opportunities so you can live life as you choose.
As a resident you will enjoy the convenience of restaurant-style dining, housekeeping, laundry and transportation services in a desirable location near popular attractions with shopping and restaurants close to campus.
Remember your own days in a college dorm or summer camp, living with people your own age that shared your interests and experiences? You played cards and board games, and talked for hours swapping stories. Here at Brookdale Edina, we recreate that fun experience of living with a family of friends.
With a number of planned activities and award-winning programs, our residents have many appealing and entertaining options. We offer life enriching opportunities to engage our resident's interests, passion and purpose.
Brookdale is committed to evidence-based programs, like our signature B-Fit exercise program as well as Brookdale Celebrates. Brookdale Celebrates combines inspired culinary and educational offerings that come together with themed experiences, special events and group activities spotlighting different cultures and cuisines.
There may come a time when you or your loved may need additional help with daily tasks. At Brookdale Edina, we offer Assisted Living care so you'll be prepared, if or when you need more assistance.
It all begins with a personal service assessment. We take the time to listen to our residents, so we can understand their needs. Then we establish clinical, dining and program support that works for them in a meaningful way.
We partner with our residents, recognizing their individual needs and preferences, and adjust services to meet their changing needs. So whether it's a unique snack, the celebration of a favorite season or a lifelong interest, we value the privilege of knowing our residents and building relationships with them to create a truly personalized living experience.
With our exclusive personal service system, you can live your life the way you want with the right care at the right time, delivered by the right people. Through years of experience serving seniors, we have developed a process that allows us to customize personal care plans for our Assisted Living residents. Your customized care plan means you only pay for the services you need and want, giving you the flexibility to change your plan.
Step inside our community, and you'll smell pies baking in the kitchen, hear grandchildren laughing in the halls, and feel the soft fur of a pet nudging you for love and attention. When you're here, you're home. The residences in our community are a neighborhood, where neighbors become friends and friends become family.
We provide care that balances independence with assistance and delivers service with compassion, understanding and respect. With comfortable accommodations and an impressive line of features and amenities, Brookdale residents enjoy life with the confidence of knowing we are here, partnering with you and your family, to customize solutions that support our residents' needs as they evolve.
We understand your concerns for your loved one's safety and well-being, and we understand the weight of the responsibility of caring for someone with Alzheimer's or other types of dementia. Let us help you and your loved one with our compassionate, specialized care.
Brookdale Edina offer programs and safe environments for those with Alzheimer's disease or other types of dementia. We believe no matter where an individual is on life's journey, each has the right to live in a dignified manner and to enjoy meaningful experiences every day.
Deeply rooted in a person-centered approach, our Alzheimer's and Dementia Care program, also called the Clare Bridge program, focuses on sustaining feelings of belonging, purpose and safety while seeking to preserve a sense of self. The Clare Bridge Daily Path provides residents with a structured routine of activities that help maintain their abilities and encourage the use of their current skills.
Designed by a team of culinary associates, experts in Dementia Care and registered dieticians, our unique dining program promotes a positive and successful dining experience with the following features:
Brookdale is the nation's largest provider of Alzheimer's and Dementia care. Through our unique memory care programs, we offer comfort from the struggles of dementia for you and your loved one with customized care to meet your loved one's specific needs. Our skilled associates provide compassionate and attentive dementia care, and enable residents to experience daily moments of success.
Experience Brookdale's distinctive blend of hospitality, attentive service, and well-appointed amenities. Call today to schedule a tour.


text:
our breathtaking newsletter
Weekly gloriousness sent to your inbox.
Featured Local Event full calendar»
Friday, August 18th - 5:00 PM-12:00 PM
|Cincy Brew Ha-Ha @ Sawyer Point
DERF Happy Hour
Keep checking back here to find out where the next DERF Happy Hour will be!
Snap, Crackle, and Pop admit to running phone sex operation
BATTLE CREEK, MI - Amid the controversy surrounding a sex line phone number on packages of OchocincO's cereal, an investigation into the seedy underworld of cereal has revealed that pitchmen Snap, Crackle and Pop have been running a phone sex operation of their own.
Evidence suggests that in the early 90's, the trio started a phone sex line promising customers a "snap, crackle, popping good time." Callers to their 800 number spent over four dollars a minute listening to adult conversation while the sound of crisped rice marinating in milk played softly in the background. The service was reportedly extremely popular in Japan.
"We would like everyone to know that this venture is separate from our roles as breakfast cereal spokesmen," said an obviously embarrassed and nervous Crackle. "Economic times are tough, and with increased competition from generic brands, we found that it was wise to diversify our talents."
The investigation is ongoing, and focused on possible involvement by other cereal spokesman. "We've found some evidence that this may be widespread," said Kellogg's Vice President Martin Ainesworth. "I don't want to name names, but we've found an advertisement by someone claiming to be a real Tiger, and they promise a Grrrrrreat Time over the phone."
The General Mills cereal corporation may also have a similar problem, ads have been found in gay publications offering up phone sex from a man claiming to have a sexy Irish accent who refers to himself as magically delicious. In addition, there is a phone sex line run by someone named Sonny, who promises that you will go Cuckoo over his chocolate balls.
- Rio Chipotle restaurants try to keep up with city ecoli production
- Lack of fans means foul ball goes unclaimed for six innings at Great American Ballpark
- Reds hope relations with Cuba lead to starting pitching prospects
- Cam Newton storms out of press conference after losing New Hampshire primary
- Johnny Manziel purchases Super Bowl ad time to kickoff job search
- Bengals acquire defense attorney Stan Chesley in first round of NFL draft
- Post-victory couch burning alleviates Lexington bed bug crisis
- Charlie Sheen offers words of hope to Reds and Cincinnati prostitutes
- Bill Belichick admits hiding video cameras inside Tim Tebow's church
- Super athlete Michael Phelps perfects one-handed iron cross on gymnastic rings
- Crosstown Shootout rebranded as less violent Crosstown Hugfest


text:
Red Dead Redemption
How do I solve (us marshal uniform)?
Ok so i went to all 6 gang hideouts in the us with in a few hours and the unlock states a single 24 hour period and it didnt unlock the uniform
Dsamuraigamer6 - 7 years ago
Top Voted Answer
I just did this. ya need to clear 5 hideouts. the fastest route is first gaptooth breach, then tumbleweed, fort mercer, twin rocks and then pikes basin. use horse pills between each hideout. you only have 24 in-game hours but it is very doable :D dont use camp or stagecoach to travel. it costs ya 6 hours, so only ride on your horse.
ShrimpManiac - 7 years ago
You need to go to all 6 hideouts in 24 hours of game time. Not sure if you did that or 24 hours of real time.
Panzervi3576 - 7 years ago
You need to Complete the hideout not just go to them, and its only 5 (Fort Mercer, Twin Rocks, Gaptooth Ridge, Tumbleweed and Pikes Basin), Solomans Folly isn't included as it is only in the PS3 version.
lalilulelo6 - 7 years ago
you also can die at least once and still be able to complete it. I was killed once while trying to complete it in the 24hrs of in game time.
darkelgta3 - 7 years ago
You have to ride a horse to all of them (not sure about solomons folly did it anyway though) not camp/ride the carriage. That's how i did it.
joeblaze - 7 years ago
You can't unlock it until the story is complete.
twyz - 7 years ago
AND you need to complete the story first :B
ShrimpManiac - 7 years ago
Easy enough, thank you shrimp
Jbanks17 - 7 years ago
This question has been successfully answered and closed.
More Questions from This Game
|How do I get the US Marshall uniform to change from "Undiscovered uniform" ?
|Why does the game keep telling me The man in uniform cheat cannot be activated?
|How do I solve this?
|How do I solve the final treasure?
|How do I solve survivalist rank 10?


text:
Eagles Quarterback Carson Wentz Leaves Big Tip in His Home State
Philadelphia Eagles star rookie quarterback, Carson Wentz is also a star when it comes to leaving a tip!
Philadelphia Eagles star rookie quarterback, Carson Wentz is also a star when it comes to leaving a tip!
The quality of food at football stadiums has been getting better and better. So, what's the best thing to eat at our local stadiums?
Eagles fans get a bad rap. But on Monday night in Chicago, they proved that their reputation is not always correct.
(973espn.com) - Asked last week what was the toughest road environment he had faced to date, all Eagles' rookie quarterback Carson Wentz could come up with was Missoula...
On the 15th anniversary of the September 11th bombings of the World Trade Center in New York City, Eagles fans decided to protest a protest of San Francisco 49er Colin Kaepernick.
He tricked his way to the top 10 finalist on 'America's Got Talent,' but Philadelphia Eagles Long Snapper Jon Dorenbos will have to settle with the bronze.
As football season comes into full view, what's the perfect craft beer for your favorite team?
Jon Dorenbos advances to the semifinals on 'America's Got Talent' with his amazing magic show!
Philadelphia Eagles long snapper Jon Dorenbos made a magical second appearance on NBC's America's Got Talent Tuesday night.
This would probably be funny - if it weren't so true. Especially lately.
NBC 10 is reporting that former Eagles running back LeSean McCoy and other NFL players were involved in an altercation at a Philadelphia nightclub Saturday night with an off-duty police officer.
PHILADELPHIA (AP) — Mark Sanchez and Darren Sproles yelled at each other after a pick-6, a fitting end to a frustrating day for the Philadelphia Eagles.


text:
Jump to navigation
Whitehorse General Hospital•Dawson City Community Hospital•Watson Lake Community Hospital
Yukon is well known for its cold climate, and now a local physician and pharmacist from Whitehorse General Hospital are garnering national attention for a new way to more effectively treat frostbite.
The expansion of Whitehorse General Hospital continues to move forward. Read the very latest information as we build a new, state-of-the-art health care facility.


text:
Each month, Rated People connects over 50,000 homeowners with quality tradesmen - simply enter your job details in the form above to get started.
We'll match your job to the relevant tradesmen in your area - those interested will pay to see your contact details and call you to quote.
As each tradesman expresses interest in quoting on your job, we'll send you their profile and ratings to help you choose the right one for you.
After the work is complete, return to the site and rate your tradesman based on their quality of work, reliability and value for money.
Tree Surgeon
Added 18/09/2016
Crown thinning 2 small (25' approx) copper beech
Searching for tradespeople
Tree Surgeon
Added 24/08/2016
3 conifers and 1 maple tree need attention, plus possibly some other work
Searching for tradespeople
Tree Surgeon
Added 11/07/2016
To fell approximately three pine trees at an approximate height of 50 feet each.Landowners...
Searching for tradespeople
Tree Surgeon
Added 12/04/2016
Fairly large branches of neighbour's birch overhang my garden which I would like removed.
Searching for tradespeople
Tree Surgeon
Added 22/09/2015
IMy conifers need thinning or pruning? At the top of the garden - shading the light too mu...
Managing your job is easier with the Rated People Homes App, download it today.


text:
Well it appears that the reach of the knockout game continues to grow as it has hit the upstate NY city of Rochester. This time however, it may not have been so anonymous after the assailants uploaded the video to Facebook posting their names along with it.
As you all probably know, the "knockout game" is an incident where a group targets a single individual at random. The group selects one person to walk up to the victim and knock them out with only one blow.It seems as though the cowards that like to participate in this "game," like to target people who are less able to fight back. This time, an elderly man was attacked outside on the street.
(See also: VIDEO: Horrific Assault on Jewish Man – Knockout Game Victim?)
The morons then took to Facebook to brag about their dastardly encounter with the elderly man. Rochester resident Tiaje Gray ended up sharing the video on Facebook with his family, friends and followers.
Over time, the other assailants in the video chimed in joking over the issue. A man who only went by the alias, "Haze on Homage" eventually ended up revealing the names of himself and the other assailant. Showing the truly disgusting nature of the man, Haze on Homage wrote, "He saw me the whole time getting ready to punch him it's his fault he didn't wanna fight."
After Haze on Homage revealed the names of those involved, one source was said to have determined the attacker's real name.
(See also: "Knockout Game" Spreads To Philadelphia)
This gave police the names of those involved as well as the exact time and date that the incident occurred.
The post was of course taken down after the men had come down off their adrenaline high to realized the stupidity of their actions. Before the video was removed however, a picture was taken via screen cap and posted to Live Leak.
There is no word yet on if Rochester Police have arrested the imbeciles yet.


text:
A spacious, single storey barn conversion, Blacksmiths Cottage on the Welsh, Shropshire and Herefordshire borders sits close to medieval town Ludlow and literary festival centre Hay-on-Wye. Single storey and detached, this luxury retreat for two is within easy reach of amenities in local towns Knighton and Presteigne. Parking is onsite for 2 cars, and extensive grounds with pretty wildlife pools and gazebo surround the cottage. Blacksmiths is the perfect year round romantic retreat, ideal for exploring the beautiful Elan Valley, nearby Snowdonia and the border market towns.
All Ground Floor Accommodation:-
Short breaks, minimum 2 nights, available.


text:
About the Book
Revision #1 of my first book with all the features you come to expect from "Dave's Different Perspective Photography". See you there and Enjoy !!!
Features & Details
- Category Travel
Large Format Landscape, 13×11 in, 33×28 cm
120 Pages
- Publish Date Sep 26, 2010
- Tags Coffee Table, Landscape, Balloons, GPS
About the Creator
Hi There! I'm Dave Grower, Owner of "Dave's Different Perspective Photography". I am here after numerous suggestions from my many friends who believe that my skill with the camera is "special". I firmly believe that my "skill" with the camera comes from the fact that I have been blind in my left eye since birth. The view through the "lens" is the other half of my vision. It is how God compensated for my defect... by giving me a "Different Perspective"! I am a published author of four "blurb" books: "The Landscapes and Balloons of the West" "The Morning and Evening Skies of the West" "The Beautiful Blooms of the West" "The Picturesque Parks of the West". I am a member of the World Photographers Organization and a freelance photographer for "World Images Today Magazine". I also shoot Real Estate sales portfolios for Brokers in the Phoenix/Sedona, Arizona areas. I hope you enjoy my images as much as I enjoyed taking them!
Log in or create an account to post a comment.


text:
Off-duty Garda nabs man robbing Dublin pharmacy with hammer
A man in his late 40s is scheduled to appear before The Criminal Courts of Justice tomorrow morning charged in connection with the robbery of a pharmacy yesterday.
At approximately 10.50am on Saturday morning it is alleged the man entered a pharmacy on Eden Quay armed with a hammer.
It is also alleged that he threatened staff and demanded money.
He escaped with a sum of money and fled the scene.
No one was injured.
An off duty garda observed the suspect and following a foot chase at Custom House Quay the suspect was arrested with the assistance of gardai from Store Street.
The money was also recovered.
The male in his late 40's was detained at Store Street Garda Station under the provisions of Section 4 of the Criminal Justice Act 1984.
He is scheduled to appear before Court No.1, The Criminal Courts of Justice, Parkgate Street at 10.30am Monday morning charged in relation to the incident.


text: PoliticsLiving in fear of evictions Uncertainty descends over Palestinians as Israel continues demolishing homes. 04 Nov 2009 02:33 GMT | Politics, Middle East, Israel The United Nations, the United States and the European Union have all called on Israel to stop the illegal eviction of Palestinians and the demolition of their homes. Ban Ki-moon, the UN secretary-general, urged Israel to end its "provocative actions" in East Jerusalem, while calling for it to freeze all settlement activity in the occupied West Bank. Despite that, the sight of Palestinians in East Jerusalem being forced out of their homes has become an all too familiar scene. Al Jazeera's Jacky Rowland reports from occupied East Jerusalem.Source: Al Jazeera


text:
Border collie kennel Home of Kavany
Welcome to our website.
Here you will find all the information about us and our dogs.
Hope you'll enjoy it en please visit us again!
OneWeb 2012 © Copyright
It all began with our first border collie "Girlfever van 't hof diabolo"
She had such al lovely personality and so much drive to work that whe decided to breed with her.
She gave us some lovely litters with dogs who do well in all types of sports, obedience, agility, ...
Now a few years later whe meanly go on dogshows and so we breed a different type of border collie, "the showtype" but whe still want to breed dogs who do good in sports and have good health and a nice personality.
Our studdog Mirko is a perfect example.