text:
Intel Pentium Pro / Pentium II/III
Performance-Monitoring Events, Commentary and [Review Questions]
(under construction)
Previous example -- pmc_event_set_t Next example -- hardware registers Return to Main Menu Diagram -- events and processor/cache/memory components jpeg format, pdf format (requires Adobe Acrobat Reader) Suggested event pairs, as a rabbit input file Nearly complete coverage Data references related to other events Events vs. cycles for some events User mode vs. System mode References: "quoted text" without a reference is (with minor modifications) from Intel Corp., Intel Architecture Software Developer's Manual, vol. 3: System Programming Guide, 1997, order no. 243192, Appendix A, Performance-Monitoring Events. [1] Dileep Bhandarkar and Jason Ding, "Performance Characterization of the Pentium Pro Processor," Proc. Third Int. Symp. on High-Performance Computer Architecture, Feb. 1-5, 1997, IEEE Computer Society Press, 1997, pp. 288-297. [2] Intel Corp., Intel Architecture Optimization Manual, 1997, order no. 242816-003. [3] Intel Corp., Intel Architecture Optimization Reference Manual, 1999, order no. 245127-001. In the following event descriptions, the event codes are hex (base 16), and the arrows represent movement of information in response to a request. Rabbit command-line options (-this or --that) are used. Terms and Acronyms: L1, L2 = Level 1 cache, Level 2 cache. (Think of the registers as Level 0, the memory as Level 3, and the paging disk as Level 4.) IFU = Instruction Fetch Unit, includes the L1 instruction cache. DCU = Data Cache Unit, includes the L1 data cache. (L2 is a unified cache.) TLB = Translation Lookaside Buffer, a small cache for virtual memory address calculations. BTB = Branch Target Buffer, used for dynamic branch prediction. MMX = MMX. Some people claim this means Multi-Media eXtensions. hit, miss: When the processor needs some information, it is found (a hit) or not (a miss). A miss at Level i causes a request to Level i+1, and then a hit or miss at Level i+1. Since Level i+1 is slower than Level i, there will be a delay (the Level i miss penalty) before data is delivered in response to the request. The miss ratio (misses at Level i / requests to Level i) is also important information. fault: A miss that causes paging activity. cache line: To improve efficiency, based on spatial locality, 32 bytes (a cache line) are moved between Level 1, Level 2 and memory in response to any processor request. cache line management: ... allocate, remove, evict, replace data bus: Connects the L1 and L2 caches; also called the backside cache bus. external bus: Connects the processor to the memory and other devices. Carries data, addresses, and transaction information. A bus agent is any device, usually a processor or memory subsystem, that can initiate a bus transaction. An external bus transaction will occupy the bus for some number of cycles. The counters can be configured to react to any bus agent (rabbit option --bus_agent 1) or only to this processor (--bus_agent 0). processor cycle, bus cycle: ... For example, a 200 MHz Pentium Pro with a 66 MHz system bus will use 3 processor cycles for each bus cycle. active cycle: A processor cycle when the processor is not halted. halt state: The Time Stamp Counter will continue to increment in the halt state (HLT instruction). Cache Line States: S = shared (and not modified) E = exclusive (and not modified) M = modified (and exclusive) I = invalid (Intel prefers the acronym MESI for this protocol.) The cache line state answers these questions related to consistency: How does this copy of the line compare to the one in memory? (the local copy has been modified or has not been modified since it was obtained from memory) Is there another copy of the line in another processor's cache? (if shared then maybe, if exclusive then no) Lines in the Level 1 instruction cache are either shared or invalid. Copying a line from memory to the local cache requires a conversation with the other processors to see if they already hold a copy of the line. When reading a line, an M-state line elsewhere must be written back to memory and changed to S-state, and an E-state line elsewhere must be changed to S-state; S-state lines elsewhere are unaffected. The read from memory can then proceed, with the local line in either S- or E-state. To establish exclusive ownership before writing to a line, an M-state line elsewhere must be written back to memory and invalidated, while all S- or E-state lines elsewhere can simply be invalidated. The line can then be loaded from memory in M-state and modified. This "read for ownership" sequence will occur on single- and multi-processor systems. Some cache lines or virtual memory pages may be non-cacheable. This is usually determined by the operating system, or by the user through a system call. [What is the effect of the C keyword "volatile"?] Pipeline Stalls: The processor pipelines must delay execution of an operation if the required information is not available. These "stalls" are usually caused by a miss at some level of the cache/memory hierarchy, but also by a relatively slow or delayed previous operation, or by a resource conflict in the processor. Pipeline Latency (Pentium Pro): ... 14-stage pipeline in-order front end, 8 stages out-of-order execution, 3 stages, 5 execution units in-order retirement, 3 stages A simple register-to-register integer operation executes in one cycle. operation cycles, cycles/result, latency throughput load (L1 hit) 3 integer multiply 4 1 fl.pt. add 3 1 fl.pt. multiply 5 2 fl.pt. divide 17 single not pipelined 32 double 37 extended Speculative Execution: To compensate for various delays, the processor will attempt to execute an instruction as soon its data is available, even before the previous instructions have all completed. This entails fetching instructions from predicted paths following a conditional branch; when the branch direction is resolved, the instructions on the wrong path are discarded, and those on the right path are accepted (retired). Instructions are retired in the order in which they appear in the program, so there are no semantic difficulties. The ability to predict branch direction based on recent behavior reduces the possibility that speculative work is wasted. Micro-operations: An instruction is decoded into one or more micro-operations, which are then matched with available data and sent to the execution units. The number of micro-operations executed per cycle is a measure of the internal parallelism in the processor. On the Pentium Pro, up to five micro-ops can be in execution in one cycle, and up to three retired per cycle. Register renaming is used to compensate for the relatively small number of architectural registers. Up to three micro-ops can be renamed in one cycle; there are 40 physical registers available. L1 and L2 cache: The L1 d-cache can execute one load and one store operation per cycle. Buffering between the processor and the cache helps to smooth out delays. size (KB) set associativity L1 i L1 d L1 i L1 d L2 Pentium Pro 8 8 4 2 4 Pentium II 16 16 The size of the L2 cache can be determined from the CPUID instruction (try 'rabbit -p'). A larger L2 cache tends to reduce the average number of cycles per instruction, and definitely increases the cost of the processor. Data Bus Transactions: On the L1 side of L2, these events record the action taken by the processor that caused a cache line to be copied. See the next group for the memory side of L2. 2e requests 28 instruction fetch L2 to L1 i-cache 29 data load L2 to L1 d-cache 2a data store L1 d-cache to L2 These event count relations should hold: 2e = 28 + 29 + 2a These are the only events affected by the --mesi option. The data bus is 8 bytes wide, while a cache line is 32 bytes wide. On the Pentium Pro, the transaction timing is 4-1-1-1 at the processor clock rate; that is, 4 cycles for the first 8 bytes, followed by 1 cycle for each of the next 8 bytes. External Bus Transactions: As seen by the event counters, 70 all 6c i/o 6f memory 6e burst 65 burst read 66 read for ownership 67 writeback 68 instruction fetch 6b partial 6a partial write 69 invalidate 6d deferred These event count relations should hold: 6e = 65 + 66 + 67 + 68 6f = 6e + 6b + 69 70 = 6c + 6f + 6d The external bus is 8 bytes wide. With the Pentium Pro, it operates at 60 or 66 MHz; with the Celeron, Pentium II and Pentium II Xeon processors, it operates at 66 or 100 MHz. With the Pentium III, it operates at 100 MHz. On the Pentium Pro, up to 8 outstanding bus transactions are allowed. Event 60 will count some of these transactions. The transaction timing depends on the degree of memory interleaving. On the Pentium Pro, it can be 14-1-1-1, 14-2-2-2, or 14-4-4-4 for 4-, 2- or 1-way interleaving, counted in bus cycles. Subset Relations: The first event is included in the second event: 85 81 46 45 23 22 25 24 27 26 Miss Relations: The first event is a miss directly following the second event: 81 80 L1 instruction cache 45 43 L1 data cache 68 28 L2, instruction fetch Events or cycles. These events may be configured (with --duration) to count events (--d 0) or cycles (--d 1): 04, 14, 22, 23, 48, 60, 61, 62, 63, 64, 79, 7a, 7b, 7e, 86, 87, a2, c6, c7, d2. However, there is usually no difference in the results. Bummer. At each cycle, clocks 79 cpu_clk_unhalted "Number of cycles during which the processor is not halted." The halt state is typically used in the OS idle loop. a2 resource_stalls "Number of cycles during which there are resource-related stalls." Other operations could occur when one operation is stalled. Resources include "register renaming or reorder buffer entries, memory buffer entries, and execution units." [1] d2 partial_rat_stalls "Number of cycles or events for partial stalls." RAT = register alias table, used for renaming; AX is a partial register in EAX. An instruction fetch will induce these events: memory access 80 ifu_ifetch processor <-- L1 i-cache. "Number of instruction fetches, both cacheable and non-cacheable." Includes speculative fetches for instructions decoded but not executed, or decoded and executed but not retired. The processor will attempt one fetch of 16 bytes each active cycle. 81 ifu_ifetch_miss L1 i-cache <-- L2 cache. "Number of instruction fetch misses." Caused by an L1 i-cache miss. 85 itlb_miss L1 i-cache <-- L2 cache. "Number of instruction TLB misses." Caused by an L1 i-cache TLB miss (which would also imply an L1 i-cache miss). 28 l2_ifetch L1 i-cache <-- L2 cache. "Number of L2 instruction fetches." (--mesi) Caused by an L1 i-cache miss. [What is the relation between events 81 and 28?] 68 bus_tran_ifetch L2 cache <-- external bus (memory). "Number of instruction fetch transactions." (--bus_agent) Caused by an L2 cache miss. processor pipelines 86 ifu_mem_stall processor <-- L1 i-cache <-- L2 cache. "Number of cycles that the instruction fetch pipe stage is stalled, including cache misses, ITLB misses, ITLB faults, and victim cache evictions." The victim cache holds recently removed TLB entries. 87 ild_stall "Number of cycles that the instruction length decoder is stalled." This pipe stage is immediately downstream from the fetch pipe stage. [What is the longest legal instruction, in bytes?] instruction decode and retire unit d0 inst_decoder "Number of instructions decoded." Up to three instructions can be decoded in one cycle, generating up to 6 micro-operations in one cycle (one instruction up to 4 uops, and two instructions at 1 uop each). A microcode sequencer is used for complex operations. The decode can stall if its output queue (6 uops) is not drained by the 5 execution units. The number of uops per instruction (except for the complex cases) for the Pentium Pro or Pentium II/III is given in reference [2] or [3], Appendix C. branch unit e0 br_inst_decoded "Number of branch instructions decoded." e2 btb_misses "Number of branches that miss the branch target buffer." The BTB holds information about recently executed branches, and the direction actually taken. It is used for branch prediction and speculative execution; on the Pentium Pro, it has 512 entries. e4 br_bogus "Number of bogus branches." [Is this event bogus?] e6 baclears "Number of times BACLEAR is asserted." (static branch prediction) floating-point execution unit 10 fp_comp_ops_exe "Number of computational floating-point operations executed." (counter 0 only) This includes integer multiply. 11 fp_assist "Number of floating-point exception cases handled by microcode." (counter 1 only) 12 mul "Number of multiplies." (counter 1 only) This includes integer multiply. 13 div "Number of divides." (counter 1 only) 14 cycles_div_busy "Number of cycles during which the divider is busy." (counter 0 only) On the Pentium II, 35 cycles per divide. MMX execution unit (Pentium II only) b0 MMX_instr_exec "Number of MMX instructions executed." b1 MMX_sat_instr_exec "Number of MMX saturating arithmetic instructions executed." b2 MMX_uops_exec "Number of MMX micro-operations executed." (--MMX) On port 0..3, requested by the unit mask, bitwise. b3 MMX_instr_type_exec Number of MMX instructions executed (--MMX). Requested by the unit mask, bitwise: 1 packed multiply 2 packed shift 4 pack operation 8 unpack operation 10 packed logical 20 packed arithmetic cc fp_MMX_trans Number of transitions between FP and MMX states (--MMX). Requested by the unit mask: 0 MMX to FP 1 FP to MMX cd MMX_assist "Number of MMX assists (that is, the number of EMMS instructions executed)." ce MMX_instr_ret "Number of MMX instructions retired." cf PII_0xCF MMX, saturated arithmetic instructions retired (undocumented) Streaming SIMD execution unit (Pentium III only) d8 emon_sse_inst_retired "Number of Streaming SIMD Extensions instructions retired." (--MMX) Requested by the unit mask, bitwise: 0 packed and scalar 1 scalar d9 emon_sse_comp_inst_ret "Number of Streaming SIMD Extensions computational instructions retired." (--MMX) Unit mask as above. instruction decode and retire unit c0 inst_retired "Number of instructions retired." c2 uops_retired "Number of micro-operations retired." Up to 3 per cycle. c1 flops "Number of computational floating-point operations retired." (counter 0 only) This does not include integer multiply (refer to events 10, 12). branch unit c4 br_inst_retired "Number of branch instructions retired." c5 br_miss_pred_retired "Number of mispredicted branches retired." "Mispredicted branches are not recognized for about 10 to 15 cycles." [1] c9 br_taken_retired "Number of taken branches retired." ca br_miss_pred_taken_ret "Number of taken mispredicted branches retired." A data memory access (load or store) will induce these events: memory access 43 data_mem_refs processor <--> L1 d-cache. "All memory references, both cacheable and non-cacheable." Includes speculative loads for instructions executed but not retired. There are no speculative stores, but there may be a speculative load for ownership. The number of bytes referenced is not indicated, and must be deduced by other means. The Pentium Pro load latency on an L1 d-cache hit is 3 cycles. [In C, how many references are caused by the assignments (q = p), (q = *p), (p = *p) or (p = p->next), if p and q are not initially in registers, and the types are reasonable?] 05 misalign_mem_ref "Number of misaligned data memory references." A compiler will usually align static or global data to the appropriate boundary, but local (runtime stack) double precision data is easily misaligned. Misaligned data takes longer to access than aligned data. A data load will further induce these events: memory access 45 dcu_lines_in L1 d-cache <-- L2 cache. "Total lines allocated in the Data Cache Unit." Caused by an L1 d-cache miss (if the reference was a hit, the line would already be allocated). Includes misses on speculative loads for instructions executed but not retired. The cache line state is E (exclusive) or S (shared). The bytes in the cache line are the same as the corresponding bytes in memory, or in another cache. Two successive misses to one cache line will allocate the line only once; the second miss appears to be a hit, but may still suffer an access delay. The L1 d-cache miss ratio, (event 45) / (event 43) can thus be underestimated. A reference that misses the cache but crosses a cache line boundary will allocate two lines, so the miss ratio can thus be overestimated. It is necessary to examine some other event counts and the number of cycles to decide if the miss ratio has been estimated reliably. 48 dcu_miss_outstanding L1 d-cache <-- L2 cache. "Weighted number of cycles while a DCU miss is outstanding." This event has the unit miss-cycles. That is, in each cycle the number of unsatisfied data references is added to the event counter. The aggregate (over all levels of memory) average miss penalty is (event 48) / (event 45) cycles [explanation follows], except that "An access that also misses the L2 is shortchanged by 2 cycles (i.e., if it counts for N cycles, it should be for N+2 cycles). Subsequent loads to the same cache line will not result in any additional counts. Count value not precise, but still useful." "The L1 data cache can accept a new load or store every cycle, and has a latency of three cycles for loads. It can handle as many as four simultaneously outstanding misses." [1] 29 l2_ld L1 d-cache <-- L2 cache. "Number of L2 data loads." (--mesi) Caused by an L1 d-cache miss. [What is the relation between events 45 and 29?] 60 bus_req_outstanding "Number of bus requests outstanding." "Counts only DCU full-line cacheable reads, not RFOs, writes, instruction fetches, or anything else. Counts 'waiting for bus to complete' (last data chunk received)." [Can we use the ratio (event 60) / (event 29) to obtain the L2 miss penalty?] A data store will further induce these events: load for ownership 45 dcu_lines_in (see above) The bytes in the cache line are notionally the same as the corresponding bytes in memory, or in another cache, but this is only a temporary situation until the state is changed to M and the store is executed. 46 dcu_m_lines_in L1 d-cache <-- L2 cache. "Number of M-state lines allocated in the Data Cache Unit." Caused by an L1 d-cache store miss. Included in event 45. The cache line state is M (modified), and thus exclusive. Copies of the same line in another cache are invalidated; the copy in memory is not yet changed. [What is the relation between events 45, 46 and 29? Is it always 45 = 46 + 29 ?] 48 dcu_miss_outstanding (see above) store 03 ld_blocks "Number of (times the) store buffer blocks." 04 sb_drains "Number of store buffer drain cycles." 47 dcu_m_lines_out L1 d-cache --> L2 cache. "Number of M-state lines evicted from the Data Cache Unit. This includes evictions via snoop HITM, intervention, or replacement." That is, caused by normal replacement of a cache line (when the L1 d-cache is full and another line is to be brought in), explicit write-back (for ex., a cache flush), or a snoop hit by another processor claiming the line in modified state. [What is the relation between events 46 and 47?] 2a l2_st L1 d-cache --> L2 cache. "Number of L2 data stores." (--mesi) This should not miss the cache, because of the previous load for ownership. [What is the relation between events 47 and 2a? Is it always 47 = 2a + 69 ?] A generic memory access (fetch, load or store) will induce these events: L2 cache (L1 side) 2e l2_rqsts L1 (d or i)-cache <--> L2 cache. "Number of L2 cache requests." (--mesi) Caused by an L1 cache miss, instruction or data; includes events 28, 29 and 2a. The request refers to a whole cache line. 22 l2_dbus_busy L1 (d or i)-cache <--> L2 cache. "Number of cycles during which the data bus was busy." Caused by an L1 cache miss. Each cache line should take 7 cycles to move, with the 4-1-1-1 timing. [What is the L1 cache-miss penalty?] 23 l2_dbus_busy_rd L1 (d or i)-cache <-- L2 cache. "Number of cycles during which the data bus was busy transferring data from the L2 cache to the processor." Caused by an L1 cache miss. Included in event 22. [Does this include instruction fetches?] L2 cache (memory side) 21 l2_ads "Number of L2 cache address strobes." [By whom?] 24 l2_lines_in L2 cache <-- external bus (memory). "Number of lines allocated in the L2 cache." Caused by an L2 cache miss. cf. events 45, 28, 29. 25 l2_m_lines_inm L2 cache <-- external bus (memory). "Number of modified lines allocated in the L2 cache." Caused by an L2 cache store miss. Included in event 24. cf. event 46. 26 l2_lines_out L2 cache --> external bus (memory). "Number of lines removed from the L2 cache for any reason." [An unmodified cache line could simply be marked invalid, and not be written back to memory. What actually happens?] 27 l2_m_lines_outm L2 cache --> external bus (memory). "Number of modified lines removed from the L2 cache for any reason." Included in event 26. cf. event 47. external bus transaction 65 bus_tran_brd L2 cache <-- external bus (memory). "Number of burst read transactions." (--bus_agent) A burst will move a cache line (32 bytes) in four data transfers (8 bytes each). [What is the relation between events 65 and 24?] 66 bus_tran_rfo L2 cache <-- external bus (memory). "Number of read-for-ownership transactions." (--bus_agent) 67 bus_trans_wb L2 cache --> external bus (memory). "Number of write-back transactions." (--bus_agent) 68 bus_tran_ifetch L2 cache <-- external bus (memory). "Number of instruction fetch transactions." (--bus_agent) 6e bus_tran_burst L2 cache <--> external bus (memory). "Number of burst transactions." (--bus_agent) Includes events 65, 66, 67, 68. 6a bus_tran_pwr L2 cache --> external bus (memory). "Number of partial write transactions." (--bus_agent) Included in event 6b. 6b bus_trans_p L2 cache <--> external bus (memory). "Number of partial transactions." (--bus_agent) A partial transaction moves less than a full cache line. 69 bus_tran_inval "Number of invalidate transactions." (--bus_agent) 6f bus_tran_mem L2 cache <--> external bus (memory). "Number of memory transactions." (--bus_agent) Includes events 6e, 6b, 69. 6c bus_trans_io "Number of I/O transactions." (--bus_agent) 6d bus_tran_def "Number of deferred transactions." (--bus_agent) 70 bus_tran_any "Number of all transactions." (--bus_agent) Includes events 6f, 6c, 6d. An external bus transaction will occupy the bus for some number of cycles: 62 bus_drdy_clocks "Number of clocks during which DRDY (the data ready signal) is asserted." "--bus_agent 0 counts bus clocks when this processor is driving DRDY; --bus_agent 1 counts processor clocks when any agent is driving DRDY." The DRDY signal is asserted by the bus agent driving the data to indicate that the data is valid during the data phase of a transaction. Wait states can be induced by not asserting DRDY during this phase. On a single-processor system, the other bus agents would be memory and i/o devices. 64 bus_data_rcv "Number of bus clock cycles during which this processor is receiving data." [Does this include instruction fetches?] [What does (event 64) / (event 60) represent?] 61 bus_bnr_drv "Number of bus clock cycles during which this processor is driving the BNR pin." (BNR = Block Next Request) 63 bus_lock_clocks "Number of processor clocks during which the LOCK signal is asserted." (--bus_agent) 7a bus_hit_drv "Number of bus clock cycles during which this processor is driving the HIT pin. Includes cycles due to snoop stalls." 7b bus_hitm_drv "Number of bus clock cycles during which this processor is driving the HITM pin. Includes cycles due to snoop stalls." 7e bus_snoop_stall "Number of bus clock cycles during which the bus is snoop stalled." This should only happen on a multiprocessor. An interrupt will induce these events: c8 hw_int_rx "Number of hardware interrupts received." On most personal computers, this will be about 100 per second, from the real-time clock. c6 cycles_int_masked "Number of processor cycles for which interrupts are disabled." c7 cycles_int_pending_and_masked "Number of processor cycles for which interrupts are disabled and interrupts are pending." A memory-management operation will induce these events: segment register 06 segment_reg_loads "Number of segment register loads." d4 seg_rename_stalls "Number of segment register renaming stalls." (--MMX) Pentium II only. Use the unit mask to specify segment registers ES, DS, FS, GS, by or-ing 1, 2, 4, 8. d5 seg_reg_renames "Number of segment register renames." (--MMX) Pentium II, as above. d6 ret_seg_renames "Number of segment register rename events retired." Pentium II only. A prefetch operation will induce these events (Pentium III only): 07 emon_sse_pre_dispatched "Number of prefetch/weakly-ordered instructions dispatched; speculative prefetches are included in counting." (--MMX) Requested by the unit mask, bitwise: 0 prefetch NTA 1 prefetch T0 2 prefetch T1, prefetch T2 3 weakly ordered stores 4b emon_sse_pre_miss "Number of prefetch/weakly-ordered instructions that miss all caches." (--MMX) Unit mask as above. These events report a hazardous condition: 52 PII_0x52 self-modifying code sequences (undocumented) Explanations. The miss penalty for data references. Over a period of N processor cycles, for large N, how many Level 1 data-cache misses will have been outstanding, and for how long on average? Let N = processor cycles = (actual cycles, but we could also use event 79), r = data references / cycle = (event 43) / (event 79), m = L1 d-cache misses per reference = (event 45) / (event 43), p = aggregate average miss penalty (cycles). Some of the L1 d-cache misses will also miss L2 or cause a page fault, so p is not the L1 miss penalty alone. Because p is determined by an experiment with one program or section of code, this estimate might not apply to another program or section of code. Nevertheless, here we go: In N cycles, there will be Nr data references. Among these Nr references, there will be (Nr)m misses. Event 48, over N cycles, will count (Nrm)p miss-cycles. Thus, (event 48) = N * r * m * p = (event 79) * (event 43 / event 79) * (event 45 / event 43) * p, so p = (event 48) / (event 45). [Why was it necessary to assume a measurement over a large number of cycles, when the number of cycles does not appear directly in the final equation? Are there any other tacit assumptions in this analysis?] [The processor can only hold a certain number of outstanding misses in its buffer. How should this number enter into the analysis?] [Suppose a miss is outstanding for t cycles, and there is a limit of b outstanding misses; further misses are delayed in the processor. If n misses occur in rapid succession, the last outstanding miss is cleared after t*n/b + b-1 cycles; for simplicity we assumed n is a multiple of b. Event 48 will count b(b-1)/2 {ramp up over b-1 cycles} + b(t-b+1) {steady state for first b misses} + b*t*(n-b)/b {steady state for n-b misses; clear b in t cycles} + b(b-1)/2 {ramp down over b-1 cycles} = nt miss-cycles. Event 45 will count n misses, and the ratio is correct, subject to the inaccuracies described earler.] Preventing Out-of-order Execution For Precise Measurement: The micro-operations, and thus the instructions, will execute when their data is available. There is a class of serializing instructions that will not execute until all prior instructions have completed, and will prevent subsequent instructions from moving ahead. The CPUID instruction is the only serializing instruction available in user mode. If the rdtsc and rdpmc instructions (to read the cycle and event counters) have been inlined, then serialization is required for precise measurement. Consider the sequence instr 1 # end of measured code rdtsc # read the Time Stamp Counter instr 2 # start of unmeasured code To prevent rdtsc from moving ahead of instr 1, and measuring too little, and to prevent instr 2 from moving ahead of rdtsc, and measuring too much, the code can be written as instr 1 # end of measured code eax = 0 # operand for cpuid cpuid # writes to eax, ebx, ecx, edx rdtsc # writes to eax, edx instr 2 # start of unmeasured code and the overhead for the two additional instructions should be subtracted from the measured time. The overhead should be an estimate of the least possible cycle or event count, to avoid producing a negative result for the measurement. Measurements with rabbit. The program should have consumed a large fraction of the CPU time; if not, the test should be repeated when the system is otherwise idle. Use the '--os 0' option to remove kernel-mode events, but not kernel- mode cycles. Use the '-s 1' option to reduce the sampling overhead when averages are the main interest. Use the '-S 2' option to see the most measurement detail. 1. average cycles per instruction retired average cycles per micro-operation retired micro-operations per instruction rabbit -S 2 --e 0xc0,0xc2 -s 1 --os 0 foo The measurements are reported as 'Events per cycle', so they must be inverted to get 'cycles per instruction'. Further Topics. For which events can there be more than one event per cycle? [rabbit --compare gt0,le0 --e 0xd0 -s 1 foo] [rabbit --compare gt1,le1 --e 0xd0 -s 1 foo] [rabbit --compare gt2,le2 --e 0xd0 -s 1 foo] [rabbit --compare gt3,le3 --e 0xd0 -s 1 foo] [rabbit --compare gt4,le4 --e 0xd0 -s 1 foo] d0 decode up to 3 instructions per cycle c2 retire up to 3 micro-operations per cycle 48 up to 4 outstanding misses (L1 d-cache) in a cycle ...


text:
HP is offering a coupon discount on this HP Personal Media 2TB External Hard Drive which is only $139.99 – $21 Coupon (ACCS73419) + Free Shipping = $118.99!
Grant yourself the ability to take it all with you, and save a ton of money all at the same time. This HP Personal Media drive is designed to handle anything you can throw at it, due to it's massive 2 Terabyte capacity which allows you told hold everything from your High Definition video collection to all sorts of important data and backups. It's lightweight and compact so it will easily fit on your desk and utilizes USB 2.0 connectivity for fast speeds and maximum compatibility at the same time. It's also very easy to keep tabs on the power of the drive due to 2 LEDs for use and power.

subset: commoncrawl


text:
Following these guidelines will help get your music on the air:
Check our program schedule
Get a sense of our music preferences, and if you feel your music would fit CKUA, then please send it our way. (We don't play metal or hard-core rap, for example.)
Send it to our Music Coordinator
CKUA Radio Network
Carol Ann Murray, Music Coordinator
9804 Jasper Avenue
Edmonton, Alberta T5J 0C5
If you feel that your music would suit a particular show, feel free to send an additional copy to that show's announcer.
Send CDs
We prefer to receive new music in CD format, although we can accept digital submissions. And please ensure that your submission meets minimum broadcast production standards.
Label your CDs
Please clearly label your CD with the proper artist/album info, including track times. Bear in mind that slip sleeves and paper envelope CD packaging can easily get lost on the shelves; regular sized jewel cases/ digipaks with a spine label are a big help to the announcers, and to you.
Include a short bio (typed, not handwritten!)
A one-page bio is helpful, but keep it minimal. Include:
- your musical genre
- where you're from
- current tour info
- other artists you might compare yourself to
- your website or contact info
Things to Consider
As a community-supported radio station, we operate very differently than commercial stations and our airplay does not concentrate on singles or focus tracks.
CKUA does not air music that contains obscene lyrics. We are not able to screen the large volume of music that we receive for lyrical content. So we ask please that albums sent that feature questionable language have a clear indication of which songs contain obscenities. Even better, if you can send an album that is a "clean edit" (obscenities removed from the recording) we will be happy to receive it.
Announcers are free to play whatever they wish - they determine which albums receive the most exposure. Because of this, we do not have the resources to produce tracking reports for individual songs. Albums which receive the most airplay will appear on our music charts. Data used to compile these charts is based on the most popular choices of our announcers over a two-week period.
We do our best to support talented artists at all levels, but we receive such a tremendous amount of music from Albertan, Canadian, and International artists, that we are simply unable to guarantee airplay on any music that is submitted to us.
What happens next?
Most music we receive and approve lands in the New Release section, which our announcers regularly review for music that interests them. Due to the sheer size of our music collection we reserve the right to pull music that receives little to no airplay from the library.
Thank you for listening and we hope you hear your own tracks soon!
Punta de Choros (Original Mix)
by Deadbeat
Saturdays at 7pm
Top Spin This Week:
Ryan Adams - Ryan Adams


text:
This design is for females with curves. It includes a representation of a woman's body with curves. Designed in 2 colors. Great design for those who are proud of their curves and also for those who are learning to be proud of them.
This great custom product in kelly green from our department Women and T-Shirt category can be printed just for you in the size and style you like. The design Curvy Girl was created by birdy27 and uploaded to Spreadshirt for you to have printed on a T-Shirt. Next to a host of other great customized designs, you can find this Curvy Girl design in Spreadshirt's Women category. If you are interested in topics like ass or booty, then you'll love Curvy Girl designs by birdy27. Spreadshirt also offers a huge selection of custom t-shirts, hoodies and accessories for the category Women as well as top brick house clothing. birdy27's designs have already impressed many of our customers, so we are sure that we've got right stuff for you! Spreadshirt is your destination for great designs of all kinds – whether it's ass, booty or brick house. We are sure that you will find something nice in our shop, there are many amazing custom Women t-shirts, hoodies, or accessories for you to find!Tags: Design ID: 2720764
birdy27 here! thx for stopping by! got cool stuff in my WHO U BE TEES shop! of course, hundreds of designs in the Spreadshirt marketplace! hundreds of designs sold! for latest b27 designs & info, join my Facebook fan page: www.facebook.com/birdy27designs
acting, writing/songwriting, dancing, inline skating, exercise, weightlifting, fashion, makeup, movies, theater, music (r&b, jazz, hip hop, dance/remixes, latin, reggae), graphic designing, color, snorkeling, travel, vegetarianism, holistic healing/altern
sunglasses_mustache3 Other Designed by surreal197
love to train Designed by skill11
Wicked strong Designed by 3087565
The Official Save the Ta-tas® Logo Other Designed by SAVETHETATAS
A mustache with a gift ribbon Other Designed by namo
Two owls Other Designed by SumuLee
Sloth Love Hug iPhone 4/4S Case Designed by carlhuber
segelschiff_o_3c Bags Designed by Judith-M83
This figure-flattering, slim fit t-shirt is soft, stylish and above all comfortable. This is the one you don't let your girlfriends borrow. It's perfect with jeans, khakis, leggings or pretty much any other bottom and is great for layering.
still to fill


text:
In 1998, President Boris Yeltsin's government defaulted on its domestic debt and Russia experienced a financial meltdown that brought it to the brink of disaster. In No Precedent, No Plan, Martin Gilman offers an insider's view of Russia's financial crisis. As the International Monetary Fund's senior person in Moscow, Gilman was in the eye of the storm. Russia's policy response to the economic collapse stemming from the disintegration of the Soviet Union was chaotic.
This pioneering study reconceptualizes the impact of social organizations, economic conditions, and human agency on human reproduction in preindustrial communities in Europe and Asia. Unlike previous studies, in which Asia is measured by European standards, Prudence and Pressure develops a Eurasian perspective.
Lives of the Laureates offers readers an informal history of modern economic thought as told through autobiographical essays by twenty-three Nobel Prize Laureates in Economics. The essays not only provide unique insights into major economic ideas of our time but also shed light on the processes of intellectual discovery and creativity. This fifth edition adds five recent Nobel laureates to its list of contributors: Vernon L. Smith (2002), Clive W. J. Granger (2003), Edward C. Prescott (2004), Thomas C. Schelling (2005) and Edmund S. Phelps (2006).
In 1931 distinguished economist John Maynard Keynes published a short essay, Economic Possibilities for Our Grandchildren, in his collection Essays in Persuasion. In the essay, he expressed optimism for the economic future despite the doldrums of the post-World War I years and the onset of the Great Depression. Keynes imagined that by 2030 the standard of living would be dramatically higher; people, liberated from want (and without the desire to consume for the sake of consumption), would work no more than fifteen hours a week, devoting the rest of their time to leisure and culture.
Currency boards, more so than other exchange rate regimes, have come in and out of fashion. Defined by a fixed exchange rate with full convertibility, central bank liabilities backed with foreign exchange reserves, and a high cost of exiting the regime, currency boards were common in colonial times—until most were cast off as countries gained independence after World War II.
The innovative approach to economic history known as the New Comparative Economic History represents a distinct change in the way that many economic historians view their role, do their work, and interact with the broader economics profession. The New Comparative Economic History reflects a belief that economic processes can best be understood by systematically comparing experiences across time, regions, and, above all, countries.
Although technological change is vital for economic growth, the interaction of finance and technological innovation is rarely studied. This pioneering volume examines the ways in which innovation is funded in the United States. In case studies and theoretical discussions, leading economists and economic historians analyze how inventors and technologically creative entrepreneurs have raised funds for their projects at different stages of U.S. economic development, beginning with the post-Civil War period of the Second Industrial Revolution.
János Kornai, a distinguished Hungarian economist, began his adult life as an ardent believer in socialism and then became a critic of the communist political and economic system. He lost family members in the Holocaust, contributed to the ideological preparation for the 1956 Hungarian Revolution, and became an influential theorist of the post-Soviet economic transition. He has been a journalist, a researcher prohibited from teaching in his home country, and a tenured professor at Harvard.
This startlingly original (and sure to be controversial) account of the evolution of Christianity shows that the economics of religion has little to do with counting the money in the collection basket and much to do with understanding the background of today's religious and political divisions. Since religion is a set of organized beliefs, and a church is an organized body of worshippers, it's natural to use a science that seeks to explain the behavior of organizations—economics—to understand the development of organized religion.
In Global Imbalances and the Lessons of Bretton Woods, Barry Eichengreen takes issue with the argument that today's international financial system is largely analogous to the Bretton Woods System of the period 1958 to 1973. Then, as now, it has been argued, the United States ran balance of payment deficits, provided international reserves to other countries, and acted as export market of last resort for the rest of the world.
One Rogers Street
Cambridge MA 02142-1209
Suite 2, 1 Duchess Street
London, W1W 6AN, UK
Contact Us


text:
Marilyn Tuxedo Pro Brush
Marilyn Tuxedo Pro Brush is designed to perfectly style fine to medium hair types!
- Better styling in less time. The curved shape achieves full contact of the brush bristles with the hair and the scalp. This contact gives a much wider brushing area than the one obtained with regular brushes.
- More control. The angle in the brush shape prevents hair from sliding out of the brush bristles during styling.
- More volume. With the Marilyn brush a greater number of bristles reach the hair roots, stretching and pulling them up to the heat of the blow-dryer. The final hairdo is then full bodied.
- Better finishing of hair ends. The middle area of the barrel has a smaller diameter than the ends of the barrel, allowing the hair ends to wrap around firmly. With this grip the hair ends are more controlled, offering better results in less time.
- 100% natural boar bristles.
- Beautiful combination alternating black and blond boar bristles.
- Triangular wood handle for a comfortable grip.
- Modern up-to-date black matte handle.
- Available in five sizes: 1.75 in, 2 in, 2.5 in, 3 in, 3.5 in
Folica stands behind the authenticity of everything we sell. Since 1998, Folica has made it our mission to provide you with an outstanding selection of hair and beauty products at highly competitive prices.
Most Helpful Reviews
I switched to using natural bristle brushes to blow my long, curly hair out after reading Ouidads "Curl Talk." (I noticed that synthetic brushes were putting stress on my hair, and it wasnt getting as… Read More
Was this post helpful?
Ask & Answer
Have you used this product to get out of a hairy situation? Leave a note here.
Marilyn Flatter Me Too Round Brush
Marilyn Flatter Me Too Round Brush is perfect for straight styling coarse hair!New Price:
Marilyn Ovali Pro Round Brush
Marilyn Ovali Pro Round Brush is two brushes in one!New Price:
Marilyn Jeli Ceramica Round Brush
Marilyn Jeli Ceramica Round Brush is a ceramic coated round barrel boar bristle brush for all hair types.New Price:
Marilyn Teasing Brush
The Marilyn Teasing Brush features 100% natural boar bristles with an elevated center row for increased texture when styling your hair. Extra long grip ensures comfort while styling.New Price:
Marilyn Hot Flash Brush
Marilyn Hot Flash Brush is the new ceramic coated aluminum barrel brushes — the Hot Flash!
Old Price: $28.00New Price:Discontinued


text:
- Product Highlights
- Great as a Gluten-Free & All-Natural Snack for Both Kids & Adults!
- Contains 2 g of Protein, 21 g of Sugar, 3 g of Fat & 180 Calories Per Serving
- Formulated Without the 8 Most Common Food Allergens Identified by the FDA
- Naturally Sweetened with Real Fruit & Real Fruitrim Juice Concentrates
SKU 016073612224 Quantity 12 Bars (680 g) Serving Size 1 Bar (57 g) Servings Per Container 12 Flavor Apricot Dietary Needs Gluten Free Directions Enjoy! Warnings Does not contain any of the 8 major food allergens identified by the FDA. Good Manufacturing practices used to segregate ingredients in a facility that processes other foods that may contain Soy, Egg, Wheat, Milk, Peanuts and Tree Nuts. Ingredients Apricot Filling (Fruit Juice Concentrate (Pear, Pineapple, Apple, Peach), Apricots, Inulin, Tapioca Starch, Apple Powder, Natural Flavors, Apricot Juice Concentrate, Water, Turmeric and Annatto Extract for color…for product label information including a complete list of ingredients, click all product images above.
- Product Details
Betty Lou's Fruit Bars are a delicious, gluten-free all-natural snack with the taste of homemade baked cobbler! All sugars come from natural fruit and fruit juice. Both kids and adults will love them!
Certified Gluten-Free
Fruit Bars Brand: Betty Lou's5 stars, based on 1 review(s).Rating:Price: $16.47 - In stock
- Why SuperSupplements?
Unbeatable Selection ~ We carry an unbeatable selection of the very best nutritional supplements, sports nutrition and natural personal care products. We continually refresh our selection so you always have access to the newest, most effective products right here in one convenient spot.
Satisfaction Guarantee ~ Your complete satisfaction with any Super Supplements purchase is guaranteed. You may return any item that does not meet your expectations within 30 days of purchase for a full refund of the product price. Guaranteed!
Free Samples ~ We encourage you to try new products - on us! Visit our Free Samples section and select any sample product that looks interesting to you complimentary with any purchase.
Free Shipping ~ Why pay for shipping when you can use those dollars for more great products? Spend $49 and enjoy free, fast shipping to most locations.
Passionate People ~ We love what we do. We work hard to bring you the very best products at the very best overall value every single day. If there is anything we can do to make your experience with Super Supplements a better one, we want to hear from you - with a passion!
Betty Lou's Fruit Bars, Apricot, 12 Bars Reviews Showing 1 out of 1 reviews for Betty Lou's Fruit Bars, Apricot, 12 Bars
This is a Great Product
Fruit Bars review posted by mike finch on 3/27/12
This is a wonderful product
Family Bars Chocolate Blast
15 Bars
NOW Energy Bar
NOW High Protein Bar Peanut & Caramel
12 Bars
Organic Dark Chocolate Bar Mint & Rosema...
2 oz Bar
ISS Research
Oh Yeah! Good Grab Bars Peanut Butter Caramel
12 Bars
Family Bars Really Vanilla
15 Bars
Organic Protein Bars Dark Chocolate Almond
12 Bars
Super Supplements | 750 S Michigan St, Seattle, WA 98108 | (877) 454-3988


text:
GreatSchools Rating
Teacher quality
Principal leadership
Parent involvement
LA ESCUELA ES MUY BUENA! el principal! y los maestros son exelentes he conocido varios de ellos y siempre he tenido exelente respuesta y los felicito por se como son: miss Bird, miss Corbett, missHagman miss Knott, miss Montelli gracias muchas gracias!
My son went to kindergarten here for half of the year & his teacher has taught him so much, he talked about her everyday and really loved Ms. Bird, the principal was extremely involved. Now that we are at this new school, we miss everyone at Gilbert school.
this school is perfect for my child loves it there
The best school ever. It has the best teachers espesially Ms.Knott.
I'm a school dentist and this school has one of the best principal in terms of concern to students, involvement in their activities....All for the betterment of the individual student.
I can't believe that turn around. The school has new playground equipment. My child's principal has created a workroom for parents. Test scores have gone up. My child has been here since Kindergarten and I know the teachers are doing one heck of a great job.
Wow! What a turn around at this school with the new Administration. More parent involvement in all areas from classroom help to fundraising. We even have our own 'parent workroom!' My children seem happier and so do their teachers.
My daughter is in Kindergarten. She can read, add and subtract but for some reason they still keep her in the same class. So far, all they have done is learn the alphabet, color and shape recognition, patterns, among other stuff. I have asked her teacher twice for books but I don't think they have any.
The community and families do their best for the students. Too bad the same can't be said for all of the teachers. Test scores have gone down and no one seems to care.
Community ratings and reviews do not represent the views of GreatSchools nor does GreatSchools check their accuracy or verify the reviewers' identities. Use your discretion when evaluating these reviews.
The Community Rating is the school's average rating from its community members (e.g., parents, students, and school staff). The highest possible rating is five stars; the lowest is one star.
7255 Eighth Street
Buena Park, CA 90621
Phone: (714) 522-7281
To start a new list, click OK. Otherwise click Cancel.
Thank you! You will begin to receive newsletters from us shortly.
Great work! Only one more step. Now we just need you to verify your email address. Please click on the link in the email we just sent you to complete your registration.
Great work! Only one more step. Now we just need you to verify your email address. Please click on the link in the email we just sent you to submit your review.
Please click on the link in the verification email we just sent you to complete your change of email address.
Whoops! It looks like we still need to verify your email. To do so, please click on the link in the email we sent you. Can't find the e-mail? Click the button below and we'll send you a new one.
Thanks for registering. Welcome to GreatSchools, the largest online community committed to improving educational outcomes through parental involvement.
Thanks for verifying your updated email address.
Oops! You haven't verified your email address yet. To do so, please click on the link in the email we sent you. Can't find the email? Click the button below to receive a new one.
Oops! That email verification link has expired. Please click the button below to receive a new one.
Create an account to submit your answers.
Sign in with an existing GreatSchools account or using Facebook:
Your review has been posted to GreatSchools.
Share with friends! Post your opinion of Carl E. Gilbert Elementary School on Facebook.
Welcome to GreatSchools!
For principals and school officials, we offer a special Enhanced School Profile (ESP) which allows you to update and add information about your school, as well as respond to reviews. If you are a school official, click Continue to start.
Please note that it can take up to 48 hours for your comment to be posted to our site. While you're here, we'd like to invite you to fill out a survey on your school's programs, activities, and extracurriculars. It only takes a few minutes and will help parents get a full picture of your school.
Continue to compare the schools you have already selected or Edit schools to change your selection.
Get started now! You have successfully registered and can now start updating your Official School Profile. The information you provide is extremely valuable in helping parents and students learn more about your school, so thanks for taking the time!
Thank you for registering as a school leader. We just need to verify your email address. We've sent you an email - please click on the link in that message to get started editing your school's information!
Thanks! We just sent you an email – please click on the link in the email to post your answers.
Get timely updates for Carl E. Gilbert Elementary School, including performance data and recently posted user reviews.


text:
|We Work with the Best
Our clients are leaders in their fields. From education to real estate and land development, municipalities to corporations, they are forward thinking, passionate and dedicated. They share our desire to create environments that will delight, satisfy, and work for their staff, tenants, clients and users. They choose us for our ability to design excellent places. We choose them for their expectation for great architecture.
Higher Education
Bryn Mawr College
Cornell University
Denison University
Drew University
Haverford College
Hobart and William Smith Colleges
Kean University
Lafayette College
Lawrence University
Montclair State University
New Jersey City University
Princeton University
Rider University
Rowan University
Rutgers University
State University of New York at Cortland
Stevens Institute of Technology
The College of New Jersey
The Richard Stockton College of New Jersey
University of Delaware
University of Medicine and Dentistry of New Jersey
University of Pennsylvania
Ursinus College
Villanova University
Virginia Commonwealth University
West Chester University
Westminster Choir College, The School of Music of Rider University
Widener University
Pre-K - K-12
A. Harry Moore School
Civic Builders
Cranbury School
Eden Institute, Inc.
New Jersey Schools Development Authority
NJCU University Academy Charter School
Real Estate Advisory & Development Services (READS)
TEAM Charter Schools
The Calais School
The Harmony Schools
Uncommon Schools
Interior Design
Aegis Property Group
Altered Image
Blank Rome
BPG Properties Ltd.
Bristol-Myers Squibb
Caxton Corporation
CB Richard Ellis
Cephalon Inc.
Clique Communications
Dechert LLP
Educational Testing Service
Genmab Inc.
Holly Rock Miller
Institute for Advanced Study
Ironbound Capital Management
Mathematica Policy Research
Matrix Development Group
Mercer Bucks Cardiology
Nassau Educators Federal Credit Union
New Jersey Economic Development Authority
Opinion Research Corporation
Princeton Advisory Group
Princeton Longevity Center
Princeton University
Princeton University Press
Reed Smith
Saul Ewing LLP
Spear Street Properties
The Children's Place
The Gale Company
Trammell Crow
Walt Disney World
Washington Group International
Commercial / Corporate
AMB Property Corporation
BBL Construction Services
Bohren's Moving and Storage
Brandywine Realty Trust
C&I Promotions
Cabot Industrial Trust
Carteret 12 Development
Cityside Archives Ltd.
Commercial Realty Corp.
Empire Merchants North Distributors
Forsgate Industrial Partners
Hansor, Inc.
Matrix Development Group
PA Associates
Playmobil, Inc.
ProLogis Trust
RBH Group
Roland Foods
Scozzari Builders
Somfy Systems, Inc.
TEVA Pharmaceuticals
The Coca-Cola Company
The Keating Group
The Punia Company
The Research and Collection Preservation Consortium
Volkswagen of America
W.W. Grainger
WHYY Public Media
Williamstown Business Group
Municipal / Government
Borough of Highland Park
Borough of Milltown
Borough of Pennington
Cranbury Township
Denville Township
Garden Club of Princeton
Higher Education Student Assistance Authority
Mendham Township
Montgomery Township
New Jersey Economic Development Authority
Princeton Township
South Brunswick- Community Center
South Brunswick- Fire/Rescue Substation
South Brunswick- Public Works Department
Township of Fairfield
Township of Franklin
Township of Montville
Township of Readington
U.S. Coast Guard Stations in New Jersey and New York
Wall Township
West Caldwell
Image: KSS Architects LLP


text:
Mon Jul 21, 2014 3:54 pm
Latest Player Updatesclose
Dezmon Briscoe
Tue Jun 17, 2014 6:33 pm Ravens worked out free agent WR Dezmon Briscoe.
Fantasy Source Spin: The 2010 sixth-rounder last appeared in a regular-season game in 2012. He was waived/injured by the Redskins last August. Briscoe would be little more than a camp body in Baltimore. He has no connection to new OC Gary Kubiak.
Source: Aaron Wilson on Twitter
Sat Aug 31, 2013 6:51 pm Redskins waived/injured WR Dezmon Briscoe.
Fantasy Source Spin: Briscoe injured his shoulder in the final exhibition game. He caught four passes for 113 yards in mop-up duty this preseason.
Sat Aug 31, 2013 9:24 am Redskins WR Dezmon Briscoe is out 4-6 weeks with a shoulder injury.
Fantasy Source Spin: Briscoe was tearing up Washington's preseason finale before going down. He'll likely be placed on injured reserve as part of Saturday's final cuts.
Source: Grant Paulsen on Twitter
Sat Jun 22, 2013 3:13 pm CSN Washington doesn't envision Redskins WR Dezmon Briscoe making the final 53-man roster.
Fantasy Source Spin: Briscoe, a 2010 sixth-round pick of the Bengals, was claimed off waivers by the Redskins from the Bucs last July. He ended up making the team and appearing in seven games last season, but he caught just two passes for 22 yards. Briscoe is no higher than seventh on the depth chart, right now.
Source: CSN Washington
Mon Sep 3, 2012 9:57 am The Washington Times believes Dezmon Briscoe could be active over Leonard Hankerson in Week 1.
Fantasy Source Spin:
Source: Washington Times
Sat Jul 28, 2012 11:39 am The Cowboys, Eagles, and Bengals also put in waiver claims on Redskins WR Dezmon Briscoe following his Thursday release from the Bucs.
Fantasy Source Spin: It doesn't appear the league at large shares new Bucs coach Greg Schiano's opinion of the (soon to be) 23-year-old former sixth-round pick. It's also a sign Briscoe would latch on elsewhere if he can't crack the Redskins' crowded receiver corps.
Source: Aaron Wilson on Twitter
Fri Jul 27, 2012 5:08 pm Redskins claimed WR Dezmon Briscoe off waivers from the Buccaneers.
Fantasy Source Spin: The Raheem Morris connection pays off for Briscoe. A talented but unfocused 22-year-old, Briscoe led the 2011 Buccaneers in touchdowns (6) and has some appeal as a red-zone threat. The new regime in Tampa Bay got rid of Briscoe because he skipped offseason workouts and failed his conditioning test to open training camp. Briscoe will battle for a roster spot in Washington.
Source: Adam Caplan on Twitter
Fri Jul 27, 2012 9:23 am Dezmon Briscoe failed his conditioning test prior to being waived by the Bucs.
Fantasy Source Spin: New coach Greg Schiano's conditioning test includes running 16 110-yard dashes in a predetermined amount of time. Briscoe didn't meet the standard for wide receivers, and also failed to show for voluntary offseason workouts this spring. He'll hit the open market with some baggage.
Source: Tampa Bay Times
Thu Jul 26, 2012 4:53 pm Bucs released WR Dezmon Briscoe.
Fantasy Source Spin: The writing was on the wall when Briscoe failed to show for the start of OTAs in May after missing pre-draft workouts. Hard-line head coach Greg Schiano is shipping all holdovers from the Raheem Morris regime if they come with commitment issues. With Vincent Jackson, Mike Williams, Preston Parker and Arrelious Benn in line for the top four spots, Briscoe was a roster long shot regardless.
Source: Adam Schefter on Twitter
Mon Jul 23, 2012 3:10 pm Dezmon Briscoe came on strong late last season as a red-zone target, scoring all six of his touchdowns from late October on. That included two scores in Week 17 with Arrelious Benn sidelined, but he's an afterthought this year with the Bucs' addition of Vincent Jackson.
Fantasy Source Spin: Lacks the opportunity to be draftable.
Source: Fantasy Source
Tue May 22, 2012 9:58 am WR Dezmon Briscoe has reported for the second week of Bucs OTAs.
Fantasy Source Spin: Briscoe missed pre-draft voluntary workouts in addition to the first week of OTAs, but has finally gotten himself to Bucs Park. Perhaps he was spooked by Monday's trade of Kellen Winslow. Briscoe needs a strong offseason and camp to be assured of holding his roster spot.
Source: Pewter Report on Twitter
Tue May 15, 2012 12:37 pm Bucs WR Dezmon Briscoe was a no-show again for the start of OTAs Tuesday.
Fantasy Source Spin: The OTAs are voluntary, but Briscoe isn't assured of a roster spot in Tampa and can't endear himself to the new coaching staff when he's not there. Briscoe also missed pre-draft voluntary workouts due to a personal issue. It's fair to wonder if the third-year receiver's priorities are no longer on football.
Source: Rick Stroud on Twitter
Wed Apr 18, 2012 5:45 pm Dezmon Briscoe has been a no-show for the first two days of Buccaneers voluntary workouts.
Fantasy Source Spin: We don't understand the details because we don't watch "Basketball Wives," but there is a story on the internet about Briscoe that can be easily accessed via a Google search. It appears he's having personal problems. Regardless, the absence and unnecessary notoriety is unlikely to go over well with the Buccaneers' new coaching staff. Briscoe is not a lock to make the Bucs' roster.
Source: Stephen Holder on Twitter
Sun Jan 1, 2012 8:24 pm Dezmon Briscoe caught eight passes for 53 yards with two touchdowns in the Week 17 loss to the Falcons.
Fantasy Source Spin: Briscoe drew the start with Arrelious Benn sidelined. Although the majority of his stats came in garbage time, he continues to produce at a higher rate than Benn when given the opportunity. Briscoe's second season ends with 35 catches for 387 yards and six touchdowns. He'll head into the offseason penciled in as the primary backup to both Mike Williams and Benn.
Sun Dec 18, 2011 12:57 am Dezmon Briscoe caught three passes for 37 yards and one touchdown in Week 15 against the Cowboys.
Fantasy Source Spin: Briscoe made his first career start while filling in for the injured Arrelious Benn (concussion) and managed to score against Sean Lee in man coverage in the latter half of the third quarter. He was shown wide-open downfield on a play in the fourth quarter that was called back on a false start by Donald Penn, but was otherwise unproductive. Continue to leave him on the waiver wire for now.
Fri Dec 16, 2011 5:39 pm With Arrelious Benn (concussion) out for Week 15, Dezmon Briscoe will be the Bucs' starting flanker Saturday night against the Cowboys.
Fantasy Source Spin: Mike Williams is the split end and Preston Parker is the slot receiver. Rotating with Benn all year at flanker, Briscoe has caught 23 passes for 292 yards and three touchdowns. Briscoe has good size (6'2/210) for the red zone and will be an every-down player in a favorable matchup, but Tampa Bay's passing game as a whole has struggled mightily of late. He'd be a low-end WR3.
Source: St. Petersburg Times
Thu Oct 27, 2011 10:14 am Dezmon Briscoe is the Bucs' flanker in three-wide sets.
Fantasy Source Spin: Arrelious Benn explained that the injuries to the Bucs' backfield last week actually lessened his role in the offense. Benn is the flanker in the Bucs' base formations, but they were forced to go three-wide almost exclusively after Earnest Graham's injury. It's strange the Bucs didn't make an exception to get Benn on the field more, but the bottom line is that last week was a little fluky. Most weeks, Benn will get more snaps and targets than Briscoe.
Source: St. Petersburg Times
Sun Oct 23, 2011 5:42 pm Dezmon Briscoe made six catches for 73 yards and a touchdown in Sunday's loss to the Bears.
Fantasy Source Spin: Briscoe drew 10 looks on the afternoon, doubling his targets for the season. He appeared to have the full confidence of quarterback Josh Freeman, and made a number of difficult catches, exhibiting excellent body control. Considering he had just 10 catches for 123 yards on the year coming into this afternoon, he's not yet worth a flier, but he's at least worth monitoring in deeper leagues if you're hurting at receiver.
Sun Sep 18, 2011 6:15 pm Bucs WR Dezmon Briscoe caught four passes for 42 yards in the team's Week 2 win over Minnesota.
Fantasy Source Spin: The efficient, if rotational, receiver hauled in all four of his targets while outproducing both Arrelious Benn and Mike Williams in terms of catches and yards. Early in the season, at least, the Bucs have employed a timeshare with their top three outside wideouts. Williams plays the most. Briscoe has six catches for 56 yards through two games.
Thu Aug 18, 2011 11:03 am Bucs WR Dezmon Briscoe has "taken control" of the starting job opposite Mike Williams, according to the St. Petersburg Times.
Fantasy Source Spin: With Arrelious Benn still working his way back from ACL surgery, Briscoe is starring. He caught four passes for 60 yards in the preseason opener even though he played just one half. And in Week 17 of last season, Briscoe caught four passes for 65 yards with a touchdown. He's not a burner, but clearly has the attention of Josh Freeman. If Benn continues to be sidelined, Briscoe could emerge as a deep league flier.
Source: St. Petersburg Times
Fri Aug 12, 2011 10:13 pm Bucs WR Dezmon Briscoe caught four passes for 60 yards in the team's preseason opener against the Chiefs Friday night.
Fantasy Source Spin: Arrelious Benn (knee) was held out as a precaution, so Briscoe drew the start as the Bucs' flanker receiver. The Kansas alum showed fearlessness over the middle, and Josh Freeman was clearly comfortable throwing to him. Briscoe will be a backup once Benn returns healthy, but the Bucs need to find a way to keep him involved. Using Briscoe and Benn outside with Mike Williams in the slot for three-receiver sets wouldn't be a bad idea.
Mon Jun 27, 2011 10:52 am Dezmon Briscoe has not been attending many of the Bucs' player-organized offseason workouts, according to his teammates.
Fantasy Source Spin: Briscoe already has a reputation for being a bit of a slacker, so this is a concern. He's penciled in as the No. 3 receiver with a chance to start if Arrelious Benn (ACL surgery) isn't ready by Week 1. But entering camp in less than ideal physical condition would be a major setback.
Source: Pewter Report
Wed May 11, 2011 10:45 am Pewter Report's Charlie Campbell suggests WR Dezmon Briscoe will be the one Bucs player most hurt by an extended lockout.
Fantasy Source Spin: On the heels of a fine Week 17 performance, Briscoe could have opened plenty of eyes in OTAs while tightening his connection with Josh Freeman. Starter Arrelious Benn (ACL surgery) has a chance to be ready for training camp, so Briscoe could be pushed back into the third- or fourth-receiver role before the Bucs even take the field this year.
Source: Pewter Report
Mon Apr 18, 2011 9:04 am Dezmon Briscoe could start at wide receiver next season if Arrelious Benn isn't recovered from ACL surgery.
Fantasy Source Spin: According to the Pewter Report, the Bucs are very high on Briscoe and see him as the third receiver. Benn's tear was clean and the rehab is reportedly going well, but predicting returns from reconstructive knee surgeries is an inexact science. Briscoe is a name to store in the back of your mind.
Source: Pewter Report
Sun Jan 2, 2011 11:35 pm Buccaneers WR Dezmon Briscoe caught four balls on five targets for 65 yards and a touchdown in a Week 17 victory over the Saints.
Fantasy Source Spin: Briscoe caught a two-yard touchdown pass from Josh Freeman, and a fourth-quarter 54-yard bomb that put the Bucs in field goal range, enabling them to ice the game. The sixth-round rookie has surely turned heads of Tampa Bay's coaches, and will get a long look this offseason given fellow WR Arrelious Benn will be coming off a torn ACL.
Tue Nov 30, 2010 4:22 pm Bucs promoted WR Dezmon Briscoe from their practice squad.
Fantasy Source Spin: As if the Bucs' draft class wasn't impressive enough, they've also nabbed rookies LeGarrette Blount and Briscoe for peanuts. Briscoe offers nice size, great hands, and an impressive college track record. He has a chance to stick, but he'll start off at the bottom of the depth chart.
Sun Sep 5, 2010 7:48 pm Bucs signed WR Dezmon Briscoe to their practice squad.
Fantasy Source Spin: Tampa pried Briscoe away from signing for the Bengals' practice squad by offering him the rookie minimum ($310,000) rather than the practice squad minimum (about $100,000). Briscoe also has more opportunity in Tampa due to a highly suspect receiver corps. The Kansas alum picked the right agent.
Source: Joe Reedy on Twitter
Fri Jun 25, 2010 12:04 pm Bengals agreed to terms with sixth-round WR Dezmon Briscoe on a multi-year contract.
Fantasy Source Spin: Briscoe offers ideal size and plus leaping ability in addition to elite college production, but his stock slipped due to a slow forty time at the Combine. The Bengals are suddenly deep at receiver, and Briscoe missed the majority of OTAs with a groin injury. He's ticketed for the practice squad unless he opens eyes in preseason action.
Source: Joe Reedy on Twitter


text:
Your email has been sent.
Tikkun Olam in Silicon Valley
Q&A: Tech guru Steve Blank talks about Thailand, secret high-tech, and the Valley's Jewish moment
I'm curious about why you joined the U.S. military at the height of the Vietnam War.
When I was in high school I was thought of as a stupid kid. There were smart kids and stupid kids and my sister said, "You know, you're not stupid. You just learn differently." But I never did a day of homework. My mother was never home. She was a bookkeeper and went out dancing every night; I have no idea what she did. I raised myself, essentially.
My sister ran away from home when she was 16. She was great for me when I needed it though. She said, "No, you aren't dumb. There's an organization called Mensa, just take the test for me." It was at Herald Square, I took the exam and she was pissed because I had a better score than she did. It gave me some confidence. I still remember the last year in high school I got four 65s and one 98. The 98 was in the first computer class they offered in high school. And then they used to give this thing called the Regents scholarship test, so I took the test, and I'm looking for my name in the bottom, I'm there 30 minutes looking for my name until I found it, and I was third in my class. I got a scholarship to SUNY. I didn't want to go to Buffalo, so I chose Michigan State to be a pre-med.
What was a "computer" back then? And why did you leave school?
Punch-cards. It was just a notion of being able to control a device.
As for why I left, I had a girlfriend my first year in Michigan State, and I'm on scholarship and she's working her ass off. Here I'm screwing around, not really interested. She says, "Why are you wasting your time? Some of us are working our asses off. You ought to leave!" And I said, "How far can I go?"
So, I hitchhiked to Miami. The next-to-last ride I got down there was from some guys in a Volkswagen Beetle, and they gave me their phone number and names just in case something didn't work out. I went to visit my friend and he said, "I hope you aren't staying because I just threw out the last guy who was on my floor." So, I called up the guys in the Beetle, and I stayed on their couch—and they turned out to be Buddhists. The next morning I woke up to chanting, and then when they were done they told me there was a job at the airport and asked me if I wanted to come. So, I started working at the Miami International Airport loading racehorses onto cargo planes.
There I got interested in the avionics on the planes. I would take home manuals and ask the guys, "Where do you learn this stuff?" They said they learned it in the air force. I ended up joining the military and went through a year of training in Mississippi. Everybody was getting assigned to Thailand, Vietnam, whatever, so my turn comes up, I get assigned to—Miami. So, I go back to Miami, and I'm placed at the Homestead Airforce Base. I was there a week, and our chief said, "Hey, listen; they're calling for volunteers in Thailand. Any volunteers?" In the military the rule is you don't volunteer for anything. But who the hell wants to be in Miami. I want to go to Thailand!
So, I volunteered to go to Southeast Asia, which turned out to be the best thing I ever did in my life.
How long were you there?
A year and a half. I worked on fighter planes and wild weasel. By the time I left Thailand I was supervising 15 other technicians. I was good at pattern recognition, and fixing things is pattern recognition. After a while you see enough stuff, you have enough data, and you know the odds of fixing something.
Were you strictly military in Thailand?
When I was in the air force I was strictly military. At my first company in Silicon Valley, I went to Korea and another undisclosed location as a civilian.
How did you get spotted into the black world track?
So, you're not going to believe this, but they're all accidents. My accidents happen through volunteering; I show up for a lot more than most people. "80 percent of life is showing up," I think that's a Woody Allen line—but it's absolutely true. So, when I came out to Silicon Valley I was working for a company in Ann Arbor, and they said, "Well, the valley's in San Jose"—and I remember our secretary got us tickets for San Jose, Puerto Rico. Because no one had heard of Silicon Valley.
So, I go out there, and the first night was surrealistic. We get off the plane me and another engineer—a Palestinian from Dearborn. The company we were with was so cheap we had to share a hotel room. We're driving in the rental car and all of a sudden an ad comes on the radio—scientists, engineers, Intel is hiring! So, it's Sunday and I buy this newspaper called The San Jose News, and for some reason it's thicker than the Sunday New York Times. I still remember 48 pages of help wanted ads. Then we turn on the TV and see more help wanted ads.
I take in all this stuff, and it's the blizzard of '78 in Ann Arbor. Why the hell would I go back? So, I interview all week and get a job as a lab technician, and I fly back to quit, drive out to California and get to my new job, and they told me the guy who hired me was fired and he had no authority to give me a job. The entrepreneur in me thank god, said, "Well, are you hiring for any jobs?" And the poor HR woman took pity on me, and she said you could talk to a new manager in the department, they're looking for a new training instructor. I go, "I taught before in the military … not really … but sure, absolutely!" And the guy said, "You're hired!"
New York's New Firebrand Rabbi
For Sharon Kleinbaum—friend of Christine Quinn, partner to Randi Weingarten—the personal is political


text:
Energizer Ultra Plus Aa 12 Pack
Add to basket
Product information
Essential power everyday
Locks in power for up to 10 years* so they're ready when you are
Keep your everyday life going with Energizer® Ultra+ with PowerSeal technology. Energizer's innovative technology locks in power for up to 10 years* so you can rely on your batteries to be ready when you are. By using fewer batteries you'll create less waste.
Locked in Power for:
More hours for your kids to play with their favourite toy
A flashlight that will perform when you need it most
Greater adventures on your walkie talkie
*Shelf Life
Using product information
While every care has been taken to ensure this information is correct, food products are constantly being reformulated and nutrition content may change. We would therefore recommend that you do not rely solely on this information and always check products labels.
Where further dietary information is important to you, for example because you have an allergy or specific dietary requirement, you should contact Tesco Customer Services if the product is Tesco branded or the product manufacturer if the product is not Tesco branded.
Nutritional and guideline daily amounts (GDA) information is based on the typical composition of the product. Guideline daily amounts are those for a typical adult (men and women).
GDA information for non Tesco products is calculated by Tesco based on information provided to Tesco. Tesco has no control over the recipe or nutritional content of such products and information on this site may differ from that given on the product label. We would therefore recommend that you do not rely solely on this information and always check products labels.
Although this information is regularly updated, Tesco are unable to accept liability for any incorrect information.
This does not affect your statutory rights.
This information is supplied for personal use only. It may not be reproduced in any way whatsoever without the prior consent of Tesco Stores Limited nor without due acknowledgement.
Tesco © Copyright 2013


text:
Reader Comments (Page 1 of 1)
I saw most of this event.....what pissed me off is the bloke who went and accomplished this on my server decided to start the 10 hour even in the early morning meaning the majority of players on my server missed it entirely. He did this on purpose too. Ya know what? It was still an awesome event in spite of one douches efforts.


text:
Gleeks & Klaine fans, we're still not over this and we know you aren't either! Catch the performance (above) of "Hopelessly Devoted To You" from last week's Glee and if you haven't yet, click here to pick up your copy of Glease!
Gleeks! Did you guys watch the season four premiere last night? Of course you did! What was your favourite part?
Glee The Music: The Christmas Album Vol. 2 drops next week!
(via gleeks)
Welcome to Sony Music Canada's official home on Tumblr!
Paper Stacks, a collaboration by FiftyThree and ALLDAYEVERYDAY.


text:
Diagnosing the "Russian Disease": Growth and Structure of the Russian Economy Then and Now
AbstractThis paper diagnoses the present Russian situation characterized as the "Russian Disease." First, it shows that a key symptom of the Russian Disease is a strong positive relation between the country's real growth and terms-of-trade-effects, which is different from the symptoms of the "Dutch Disease". This paper also presents three variants (oil prices, terms-of-trade, and trading gains) of the concept of terms-of-trade effects using the SNA framework. Second, it shows a strong positive impact of terms-of-trade effects on the Russian manufacturing, which markedly differs from one of the major symptoms of the Dutch Disease (slower growth of manufacturing through the booming mining sector and real appreciation of exchange rates). This paper also suggests the significance of the manufacturing industry for the Russian economy. Third, this paper shows that the appreciation (depreciation) of real exchange rates of Russia's rubles induced the boost (decline) of its imports. Fourth, this paper proves that the boost of imports, in turn, induced the GDP growth of the trade sector as one of the major sources of the Russian overall growth. We also present the impact of oil prices on two kinds of real exchange rates (CPI-based and GDP-based real exchange rates).
Download InfoIf you experience problems downloading a file, check if you have the proper application to view it first. In case of further problems read the IDEAS help page. Note that these files are not on the IDEAS site. Please be patient as the files may be large.
Bibliographic InfoPaper provided by Russian Research Center, Institute of Economic Research, Hitotsubashi University in its series RRC Working Paper Series with number 28.
Length: 30 p.
Date of creation: Oct 2010
Date of revision:
Handle: RePEc:hit:rrcwps:28
Contact details of provider:
Postal: 2-1 Naka, Kunitachi City, Tokyo 186-8603
Phone: +81-42-580-8382
Fax: +81-42-580-8333
Web page: http://www.ier.hit-u.ac.jp/rrc/
More information through EDIRC
Related researchKeywords: Russian Disease; Dutch Disease; growth; oil price; terms-of-trade; trading gain; manufacturing; imports; real exchange rate; trade;
Find related papers by JEL classification:
- E31 - Macroeconomics and Monetary Economics - - Prices, Business Fluctuations, and Cycles - - - Price Level; Inflation; Deflation
- P24 - Economic Systems - - Socialist Systems and Transition Economies - - - National Income, Product, and Expenditure; Money; Inflation
- P28 - Economic Systems - - Socialist Systems and Transition Economies - - - Natural Resources; Environment
- P59 - Economic Systems - - Comparative Economic Systems - - - Other
This paper has been announced in the following NEP Reports:
- NEP-ALL-2010-12-11 (All new papers)
- NEP-CIS-2010-12-11 (Confederation of Independent States)
- NEP-TRA-2010-12-11 (Transition Economics)
ReferencesNo references listed on IDEAS
You can help add them by filling out this form.
Blog mentionsAs found by EconAcademics.org, the blog aggregator for Economics research:
ListsThis item is not listed on Wikipedia, on a reading list or among the top items on IDEAS.
StatisticsAccess and download statistics
CorrectionsWhen requesting a correction, please mention this item's handle: RePEc:hit:rrcwps:28. See general information about how to correct material in RePEc.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (Digital Resources Section, Hitotsubashi University Library).
If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.
If references are entirely missing, you can add them using this form.
If the full references list an item that is present in RePEc, but the system did not link to it, you can help with this form.
If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your profile, as there may be some citations waiting for confirmation.
Please note that corrections may take a couple of weeks to filter through the various RePEc services.


text:
The ACMs are coming April 6th on CBS...and it's up to YOU (yes, YOU) to decide who will take home the award for "Best New Artist." Voting has already begun and will run through February 4th to dwindle down the field of eight semi-finalists to three, who will then move on to the final round! CLICK HERE TO VOTE! Here are the semi-finalists...
Lee Brice
Brett Eldredge
Tyler Farr
Justin Moore
Kip Moore
Kacey Musgraves
Thomas Rhett


text:
How to be happy for your engaged friends
Text: Denise Ngo
Photos: Getty Images
Not long ago, you could pull up Facebook on New Year's Day knowing exactly what awaited you: photos of your classmates getting hammered at the club, status updates proclaiming hilariously idealistic resolutions, and wall posts written by people who were still recovering from the night before. It was gloriously entertaining. There was nothing quite like starting the year feeling smug. But against all odds, your friends got their act together. Wedding announcements began populating your News Feed. And in an embarrassing reversal of fortunes, while your acquaintances continue getting engaged over the holidays, you're spending New Year's Day guzzling leftover champagne while scrolling past their engagement photos.
You feel guilty for wallowing. You're not the type of person who devotes the first day of the year to stalking, but your ex-colleague put up an album full of engagement photos taken on the Brooklyn Bridge, with participants holding up a rainbow of signs spelling "WILL YOU MARRY ME?", and you are powerless to resist.
No matter how much you insist that singleness is underrated, that you don't need a man, that it's not the right time, or that 2013 will be your year, seeing engagement photos makes you feel like you're missing out on something. It's like gym class all over again, where the team captain picks you last because you're the worst at sports, except this time the arena is marriage and the team captain is the cosmic force in charge of our love lives.
It's not unusual to feel this way, especially if your exes and frenemies beat you to the altar. Even studies done at Cornell and at Stanford have found that Facebook usage contributes to angst because looking at other people's photos makes you believe that they are happier than you are.
And deep inside, you know that the solution to your problems isn't a man-friend. It's the elusive ability to feel happy for other people's good fortune. Why is it so hard? When did you get so petty? Is it possible to take their announcements as signs of what's to come in your own life, rather than evidence of what you're lacking?
From experience, yeah, it is. But first, you have to be forgiving – of yourself, for being vulnerable to self-pity; of your exes, for finding someone before you did; and of time and opportunity for making you wait your turn.
More Sex & Relationship Features
facebook recommendations
- Entertainment
- Asia Celeb News
- Hollywood Buzz
- Korean Buzz
- Celeb Interviews
- Celeb Bios
- Celeb Blogs
- Photo Galleries
- Music Reviews
- Movies
- xinFirst Webisodes
- TV Channels
- Channel 5
- Channel 8
- Channel U
- okto
- Suria
- Vasantham
- Radio
- Class 95FM
- Gold 90.5FM
- Lush 99.5FM
- Symphony 92.4FM
- Capital 95.8FM
- Love 97.2FM
- Ria 89.7FM
- Warna 94.2FM
- Oli 96.8FM
- Lifestyle
- Beauty & Fashion
- Food
- Going Out
- Health
- Relationships
- Travel
- Work Life
- Style
- Style:Men
- Style:Weddings
- Style:Living
- i-Weekly i周刊
- Timepieces
- Mother & Baby
- Elle
- Postbox
- News
- Singapore
- World
- Regional
- Sci-Tech
- Weird
- Business
- News Videos
- Sports
- Local Sports
- World Football
- Formula One
- Video
- Catch-Up TV
- Entertainment
- xinmsn Celebs
- Korean Celebs
- Hollywood Celebs
- Weird & Wonderful
- News
- Lifestyle
- Sports
- xinFirst


text:
GRANDVIEW- Late last night in Grandview, Police responded to a report of a break-in in the 600 block of E 3rd street. Three males reportedly entered the residence and demanded money. After displaying a firearm several shots were reportedly fired. Some items and money were taken from the victims.
Police spotted the suspects as they tried to escape. A high-speed chase up to 100 mph ended in Sunnyside at the intersection of Midvale and Green Valley Roads. One man escaped the vehicle and officers were unable to find him.
A 17 year-old male was arrested, but a 42 year-old male Wapato resident tried to escape. An officer placed in fear for his life shot the suspect. The man was taken to Sunnyside Community Hospital for treatment. The Yakima Police Department's Major Crimes Unit was called in to conduct a complete investigation.
The Juvenile arrested was transported to Yakima Juvenile. Charges have been requested for multiple counts of burglary, assault and robbery. The Grandview Police Department's Detective will conduct the original investigation of the robbery.
Local News Washington News Idaho News National International Connect With Kleck KHQ MD Invest Northwest KHQ Birthdays Sports from SWX Pro Sports College Sports High School Sports
Forecast Discussion HD Doppler 6i Radar 6 Day Forecast School Closures & Delays Road & Pass Conditions Weather Pix Dave Law's Fishing Report
All content © Copyright 2000 - 2014 WorldNow and KHQ. All Rights Reserved. For more information on this site, please read our Privacy Policy and Terms of Service.


text:
Was £44.95
Now £31.46
Now £22.47
50% Off
Save a total of £22.48
Black girls' marley riding boots
Item No.61132_427515BLA
Just like mum's favourite pair, crafted from genuine suede (with a man-made back shaft). The slip-resistant rubber soles stand up to her every step. Inside, a pink lining adds a girly pop.
- Cow suede/man made upper
- Cow suede/man made upper
- Spot clean
Debenhams is happy to exchange or refund your purchase within 28 days providing the goods are in a fully resaleable condition (including tags) and not within the exclusion policy*. This policy does not affect your statutory rights. You can return unwanted items either by visiting your local store (the fastest way to get a refund), by arranging a courier collection or returning by post. Exclusions apply to selected products. For instructions on how to return products and information on Debenhams refund policy visit the returns and refunds section of the website.