text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 6, 2008
|Filing date
|Apr 2, 2007
|Priority date
|Mar 31, 1992
|Also published as
|Publication number
|Sanjiv Garg, Kevin Iadonato, Le Nguyen, Johannes Wang
|Original Assignee
|Transmeta Corporation
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|Referenced by (7), Classifications (17), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of application Ser. No. 11/252,820, filed Oct. 19, 2005, now pending, which is a continuation of application Ser. No. 10/086,197, filed Mar. 1, 2002, now U.S. Pat. No. 7,051,187, which is a continuation of application Ser. No. 09/906,099, filed Jul. 17, 2001, now abandoned, which is a continuation of application Ser. No. 09/329,354, filed Jun. 10, 1999, now U.S. Pat. No. 6,289,433, which is a continuation of application Ser. No. 08/990,414, filed Dec. 15, 1997, now U.S. Pat. No. 5,974,526, which is a continuation of application Ser. No. 08/594,401, filed Jan. 31, 1996, now U.S. Pat. No. 5,737,624, which is a continuation of application Ser. No. 08/219,425, filed Mar. 29, 1994, now U.S. Pat. No. 5,497,499, which is a continuation of application Ser. No. 07/860,719, filed Mar. 31, 1992, now abandoned. The disclosures of each of the above-referenced applications are incorporated herein by reference.
The following are related applications: "Semiconductor Floor Plan and Method for a Register Renaming Circuit," Ser. No. 07/860,718, filed Mar. 31, 1992, now U.S. Pat. No. 5,371,684; "High-Performance, Superscalar-Based Computer System with Out-Of-Order Instruction Execution," Ser. No. 07/817,810, filed Jan. 8, 1992, now U.S. Pat. No. 5,539,911; and "High-Performance, Superscalar-Based Computer System with Out-Of-Order Instruction Execution and Concurrent Results Distribution," Ser. No. 08/397,016, filed Mar. 1, 1995, now U.S. Pat. No. 5,560,032. The disclosures of the above applications are incorporated herein by reference.
1. Field of the Invention
The present invention relates to superscalar reduced instruction set computers (RISC). More particularly, the present invention relates to instruction scheduling including register renaming and instruction issuing for superscalar RISC computers.
2. Related Art
A more detailed description of some of the basic concepts discussed in this application is found in a number of references, including Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1991); John L. Hennessy et al., Computer Architecture—A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990). Johnson's text, particularly Chapters 2, 6 and 7 provide an excellent discussion of the register renaming issues addressed by the present invention.
A major consideration in a superscalar RISC processor is to how to execute multiple instructions in parallel and out-of-order, without incurring data errors due to dependencies inherent in such execution. Data dependency checking, register renaming and instruction scheduling are integral aspects of the solution.
Storage Conflicts and Register Renaming
True dependencies (sometimes called "flow dependencies" or "write-read" dependencies) are often grouped with anti-dependencies (also called "read-write" dependencies) and output dependencies (also called "write-write" dependencies) into a single group of instruction dependencies. The reason for this grouping is that each of these dependencies manifests itself through use of registers or other storage locations. However, it is important to distinguish true dependencies from the other two. True dependencies represent the flow of data and information through a program. Anti- and output dependencies arise because, at different points in time, registers or other storage locations hold different values for different computations.
When instructions are issued in order and complete in order, there is a one-to-one correspondence between registers and values. At any given point in execution, a register identifier precisely identifies the value contained in the corresponding register. When instructions are issued out of order and complete out of order, correspondence between registers and values breaks down, and values conflict for registers. This problem is severe when the goal of register allocation is to keep as many values in as few registers as possible.
Keeping a large number of values in a small number of registers creates a large number of conflicts when the execution order is changed from the order assumed by the register allocator.
Anti- and output dependencies are more properly called "storage conflicts" because reusing storage locations (including registers) causes instructions to interfere with one another even though conflicting instructions are otherwise independent. Storage conflicts constrain instruction issue and reduce performance. But storage conflicts, like other resource conflicts, can be reduced or eliminated by duplicating the troublesome resource.
Dependency Mechanisms
Johnson also discusses in detail various dependency mechanisms, including: software, register renaming, register renaming with a reorder buffer, register renaming with a future buffer, interlocks, the copying of operands in the instruction window to avoid dependencies, and partial renaming.
A conventional hardware implementation relies on software to enforce dependencies between instructions. A compiler or other code generator can arrange the order of instructions so that the hardware cannot possibly see an instruction until it is free of true dependencies and storage conflicts. Unfortunately, this approach runs into several problems. Software does not always know the latency of processor operations, and thus, cannot always know how to arrange instructions to avoid dependencies. There is the question of how the software prevents the hardware from seeing an instruction until it is free of dependencies. In a scalar processor with low operation latencies, software can insert "no-ops" in the code to satisfy data dependencies without too much overhead. If the processor is attempting to fetch several instructions per cycle, or if some operations take several cycles to complete, the number of no-ops required to prevent the processor from seeing dependent instructions rapidly becomes excessive, causing an unacceptable increase in code size. The no-ops use a precious resource, the instruction cache, to encode dependencies between instructions.
When a processor permits out-of-order issue, it is not at all clear what mechanism software should use to enforce dependencies. Software has little control over the behavior of the processor, so it is hard to see how software prevents the processor from decoding dependent instructions The second consideration is that no existing binary code for any scalar processor enforces the dependencies in a superscalar processor, because the mode of execution is very different in the superscalar processor. Relying on software to enforce dependencies requires that the code be regenerated for the superscalar processor. Finally, the dependencies in the code are directly determined by the latencies in the hardware, so that the best code for each version of a superscalar processor depends on the implementation of that version.
On the other hand, there is some motivation against hardware dependency techniques, because they are inherently complex. Assuming instructions with two input operands and one output value, as holds for typical RISC instructions, then there are five possible dependencies between any two instructions: two true dependencies, two anti-dependencies, and one output dependency. Furthermore, the number of dependencies between a group of instructions, such as a group of instructions in a window, varies with the square of the number of instructions in the group, because each instruction must be considered against every other instruction.
Complexity is further multiplied by the number of instructions that the processor attempts to decode, issue, and complete in a single cycle. These actions introduce dependencies. The only aid in reducing complexity is that the dependencies can be determined incrementally, over many cycles to help reduce the scope and complexity of the dependency hardware.
One technique for removing storage conflicts is by providing additional registers that are used to reestablish the correspondence between registers and values. The additional registers are conventionally allocated dynamically by hardware, and the registers are associated with values needed by the program using "register renaming." To implement register renaming, processors typically allocate a new register for every new value produced (i.e., for every instruction that writes a register). An instruction identifying the original register, for the purpose of reading its value, obtains instead the value in the newly allocated register. Thus, hardware renames the original register identifier in the instruction to identify the new register and correct value. The same register identifier in several different instructions may access different hardware registers, depending on the locations of register references with respect to register assignments.
Consider the following code sequence where "op" is an operation, "Rn" represents a numbered register, and ":=" represents assignment:
R3b:=R3a op R5a (1)
R4b:=R3b+1 (2)
R3c:=R5a+1 (3)
R7b:=R3c op R4b (4)
Each assignment to a register creates a new "instance" of the register, denoted by an alphabetic subscript. The creation of a new instance for R3 in the third instruction avoids the anti- and output dependencies on the second and first instructions, respectively, and yet does not interfere with correctly supplying an operand to the fourth instruction. The assignment to R3 in the third instruction supersedes the assignment to R3 in the first instruction, causing R3 c to become the new R3 seen by subsequent instructions until another instruction assigns a value to R3.
Hardware that performs renaming creates each new register instance and destroys the instance when its value is superseded and there are no outstanding references to the value. This removes anti- and output dependencies and allows more instruction parallelism. Registers are still reused, but reuse is in line with the requirements of parallel execution. This is particularly helpful with out-of-order issue, because storage conflicts introduce instruction issue constraints that are not really necessary to produce correct results. For example, in the preceding instruction sequence, renaming allows the third instruction to be issued immediately, whereas, without renaming, the instruction must be delayed until the first instruction is complete and the second instruction is issued.
Another technique for reducing dependencies is to associate a single bit (called a "scoreboard bit") with each register. The scoreboard bit is used to indicate that a register has a pending update. When an instruction is decoded that will write a register, the processor sets the associated scoreboard bit. The scoreboard bit is reset when the write actually occurs. Because there is only one scoreboard bit indicating whether or not there is a pending update, there can be only one such update for each register. The scoreboard stalls instruction decoding if a decoded instruction will update a register that already has a pending update (indicated by the scoreboard bit being set). This avoids output dependencies by allowing only one pending update to a register at any given time.
Register renaming, in contrast, uses multiple-bit tags to identify the various uncomputed values, some of which values may be destined for the same processor register (that is, the same program-visible register). Conventional renaming requires hardware to allocate tags from a pool of available tags that are not currently associated with any value and requires hardware to free the tags to the pool once the values have been computed. Furthermore, since scoreboarding allows only one pending update to a given register, the processor is not concerned about which update is the most recent.
A further technique for reducing dependencies is using register renaming with a "reorder buffer" which uses associative lookup. The associative lookup maps the register identifier to the reorder buffer entry as soon as the entry is allocated, and, to avoid output dependencies, the lookup is prioritized so that only the value for the most recent assignment is obtained if the register is assigned more than once. A tag is obtained if the result is not yet available. There can be as many instances of a given register as there are reorder buffer entries, so there are no storage conflicts between instructions. The values for the different instances are written from the reorder buffer to the register file in sequential order. When the value for the final instance is written to the register file, the reorder buffer no longer maps the register; the register file contains the only instance of the register, and this is the most recent instance.
However, renaming with a reorder buffer relies on the associative lookup in the reorder buffer to map register identifiers to values. In the reorder buffer, the associative lookup is prioritized so that the reorder buffer always provides the most recent value in the register of interest (or a tag). The reorder buffer also writes values to the register file in order, so that, if the value is not in the reorder buffer, the register file must contain the most recent value
In a still further technique for reducing dependencies, associative lookup can be eliminated using a "future file." The future file does not have the properties of the reorder buffer discussed in the preceding paragraph. A value presented to the future file to be written may not be the most recent value destined for the corresponding register, and the value cannot be treated as the most recent value unless it actually is. The future file therefore keeps track of the most recent update and checks that each write corresponds to the most recent update before it actually performs the write.
When an instruction is decoded, it accesses tags in the future file along with the operand values. If the register has one or more pending updates, the tag identifies the update value required by the decoded instruction. Once an instruction is decoded, other instructions may overwrite this instruction's source operands without being constrained by anti-dependencies, because the operands are copied into the instruction window. Output dependencies are handled by preventing the writing as a result into the future file if the result does not have a tag for the most recent value. Both anti- and output dependencies are handled without stalling instruction issue.
If dependencies are not removed through renaming, "interlocks" must be used to enforce dependencies. An interlock simply delays the execution of an instruction until the instruction is free of dependencies. There are two ways to prevent an instruction from being executed: one way is to prevent the instruction from being decoded, and the other is to prevent the instruction from being issued.
To improve performance over scoreboarding, interlocks are moved from the decoder to the instruction window using a "dispatch stack." The dispatch stack is an instruction window that augments each instruction in the window with dependency counts. There is a dependency count associated with the source register of each instruction in the window, giving the number of pending prior updates to the source register and thus the number of updates that must be completed before all possible true dependencies are removed. There are two similar dependency counts associated with the destination register of each instruction in the window, giving both the number of pending prior uses of the register (which is the number of anti-dependencies) and the number of pending prior updates to the register (which is the number of output dependencies).
When an instruction is decoded and loaded into the dispatch stack, the dependency counts are set by comparing the instruction's register identifiers with the register identifiers of all instructions already in the dispatch stack. As instructions complete, the dependency counts of instructions that are still in the window are decremented based on the source and destination register identifiers of completing instructions (the counts are decremented by a variable amount, depending on the number of instructions completed). An instruction is independent when all of its counts are zero. The use of counts avoids having to compare all instructions in the dispatch stack to all other instructions on every cycle.
Anti-dependencies can be avoided altogether by copying operands to the instruction window (for example, to the reservation stations) during instruction decode. In this manner, the operands cannot be overwritten by subsequent register updates. Operands can be copied to eliminate anti-dependencies in any approach, independent of register renaming. The alternative to copying operands is to interlock anti-dependencies, but the comparators and/or counters required for these interlocks are costly, considering the number of combinations of source and result registers to be compared.
A tag can be supplied for the operand rather than the operand itself. This tag is simply a means for the hardware to identify which value the instruction requires, so that, when the operand value is produced, it can be matched to the instruction. If there can be only one pending update to a register, the register identifier can serve as a tag (as with scoreboarding). If there can be more than one pending update to a register (as with renaming), there must be a mechanism for allocating result tags and insuring uniqueness.
An alternative to scoreboarding interlocking is to allow multiple pending updates of registers to avoid stalling the decoder for output dependencies, but to handle anti-dependencies by copying operands (or tags) during decode. An instruction in the window is not issued until it is free of output dependencies, so the updates to each register are performed in the same order in which they would be performed with in-order completion, except that updates for different registers are out of order with respect to each other. The alternative has almost all of the capabilities of register renaming, lacking only the capability to issue instructions so that updates to the same register occur out of order.
There appears to be no better alternative to renaming other than with a reorder buffer. Underlying the discussion of dependencies has been the assumption that the processor performs out-of-order issue and already has a reorder buffer for recovering from mispredicted branches. Out-of-order issue makes it unacceptable to stall the decoder for dependencies. If the processor has an instruction window, it is inconsistent to limit the look ahead capability of the processor by interlocking the decoder. There are then only two alternatives: implement anti- and output dependency interlocks in the window or remove these altogether with renaming.
The present invention is directed to instruction scheduling including register renaming and instruction issuing for superscalar RISC computers. A Register Rename Circuit (RRC), which is part of the scheduling logic allows a computer's Instruction Execution Unit (IEU) to execute several instructions at the same time while avoiding dependencies. In contrast to conventional register renaming, the present invention does not actually rename register addresses. The RRC of the present invention temporarily buffers the instruction results, and the results of out-of-order instruction execution are not transferred to the register file until all previous instructions are done. The RRC also performs result forwarding to provide temporarily buffered operands (results) to dependant instructions. The RRC contains three subsections: a Data Dependency Checker (DDC), Tag Assign Logic (TAL) and Register file Port MUXes (RPM).
The function of the DDC is to locate the dependencies between the instructions for a group of instructions. The DDC does this by comparing the addresses of the source registers of each instruction to the addresses of the destination registers of each previous instruction in the group. For example, if instruction A reads a value from a register that is written to by instruction B, then instruction A is dependent upon instruction B and instruction A cannot start until instruction B has finished. The DDC outputs indicate these dependencies.
The outputs of the DDC go to the TAL. Because it is possible for an instruction to be dependent on more than one previous instruction, the TAL must determine which of those previous instructions will be the last one to be executed. The present invention automatically maps each instruction to a predetermined temporary buffer location; hence, the present invention does not need prioritized associative look-up as used by conventional reorder buffers, thereby saving chip area/cost and execution speed.
Out-of-order results for several instructions being executed at the same time are stored in a set of temporary buffers, rather than the file register designated by the instruction. If the DDC determines, for example, that a register that instruction 6's source is written to by instructions 2, 3 and 5, then the TAL will indicate that instruction 6 must wait for instruction 5 by outputting the "tag" of instruction 5 for instruction 6. The tag of instruction 5 shows the temporary buffer location where instruction 5's result is stored. It also contains a one bit signal (called a "done flag") that indicates if instruction 5 is finished or not. The TAL will output three tags for each instruction, because each instruction can have three source registers. If an instruction is not dependent on any previous instruction, the TAL will output the register file address of the instruction's input, rather than a temporary buffer's address.
The last part of the RRC are the RPMs or Register file Port MUXes. The inputs of the RPMs are the outputs of the TAL, and the select lines for the RPMs come from another part of the IEU called the Instruction Scheduler or Issuer. The Instruction Scheduler chooses which instruction to execute (this decision is based partly on the done flags) and then uses the RPMs to select the tags of that instruction. These tags go to the read address ports of the computer's register files. In the previous example, once instruction 5 has finished, the Instruction Scheduler will start instruction 6. It will select the RPM so that the address of instruction 5's result (its tag) is sent to the register file, and the register file will make the result of instruction 5 available to instruction 6.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
The invention will be better understood if reference is made to the accompanying drawings.
Instructions are sent to IEU 100 from an Instruction Fetch Unit (IFU, not shown) through an instruction FIFO (first-in-first-out register stack storage device) 101 in groups of four called "buckets." IEU 100 can decode and schedule up to two buckets of instructions at one time. FIFO 101 stores 16 total instructions in four buckets labeled 0-3. IEU 100 looks at an instruction window 102. In one embodiment of the present invention, window 102 comprises eight instructions (buckets 0 and 1). Every cycle IEU 100 tries to issue a maximum number of instructions from window 102. Window 102 functions as an instruction buffer register. Once the instructions in a bucket are executed and their results stored in the processor's register file (see block 117), the bucket is flushed out a bottom 104 and a new bucket is dropped in at atop 106.
In order to execute instructions in parallel or out of order, care must be taken so that the data that each instruction needs is available when the instruction needs it and also so that the result of each instruction is available for any future instructions that might need it. A Register Rename Circuit (RRC), which is part of the scheduling logic of the computer's IEU performs this function by locating dependencies between current instructions and then renaming the sources (inputs) of the instruction.
As noted above, there are three types of dependencies: input dependencies, output dependencies and anti-dependencies. Input dependencies occur when an instruction, call it A, performs an operation on the result of a previous instruction, call it B. Output dependencies occur when the outputs of A and B are to be stored in the same place. Anti-dependencies occur when instruction A comes before B in the instruction stream and B's result will be stored in the same place as one of A's inputs.
Input dependencies are handled by not executing instructions until their inputs are available. RRC 112 is used to locate the input dependencies between current instructions and then to signal an Instruction Scheduler or Issuer 118 when all inputs for a particular instruction are ready. In order to locate these dependencies, RRC 112 compares the register file addresses of each instruction's inputs with the addresses of each previous instruction's output using a data dependency circuit (DDC) 108. If one instruction's input comes from a register where a previous instruction's output will be stored, then the latter instruction must wait for the former to finish.
This implementation of RRC 112 can check eight instructions at the same time, so a current instruction is defined as any one of those eight from window 102. It should become evident to those skilled in the art that the present invention can easily be adapted to check more or less instructions.
In one embodiment of the present invention, instructions can have from 0 to 3 inputs and 0 or 1 outputs. Most instructions' inputs and outputs come from, or are stored in, one of several register files. Each register file 117 (e.g., separate integer, floating and boolean register files) has 32 real entries plus the group of 8 temporary buffers 116. When an instruction completes (the term "complete" means that the operation is complete and the operand is ready to be written to its destination register), its result is stored in its preassigned location in the temporary buffers 116. Its result is later moved to the appropriate place in register file 117 after all previous instructions' results have been moved to their places in the register file. This movement of results from temporary buffers 116 to register file 117 is called "retirement" and is controlled by termination logic, as should become evident to those skilled in the art. More than one instruction may be retired at a time. Retirement comprises updating the "official state" of the machine, including the computer's Program Counter, as will become evident to those skilled in the art. For example, if instruction I0 happens to complete directly before instruction I1, both results can be stored directly into register file 117. But if instruction I3 then completes, its result must be stored in temporary buffer 116 until instruction I2 completes. By having IEU 100 store each instruction's result in its preassigned place in the temporary buffers 116, IEU 100 can execute instructions out of program order and still avoid the problems caused by output and anti-dependencies.
RRC 112 sends a bit map to an Instruction Scheduler 118 via a bus 120 indicating which instructions in window 102 are ready for issuing. Instruction decode logic (not shown) indicates to Issuer 118 the resource requirements for each instruction over a bus 123. For each resource in IEU 100 (e.g., each functional unit being an adder, multiplier, shifter, or the like), Issuer 118 scans this information and selects the first and subsequent instructions for issuing by sending issue signals over bus 121. The issue signals select a group of Register File Port MUXes (RPMs) 124 inside RRC 112 whose inputs are the addresses of each instruction's inputs.
Because the results may stay in temporary buffer 116 several cycles before going to register file 117, a mechanism is provided to get results from temporary buffer 116 before they go to register file 117, so the information can be used as operands for other instructions. This mechanism is called "result forwarding," and without it, Issuer 118 would not be able to issue instructions out of order. This result forwarding is done in register file 117 and is controlled by RRC 112. The control signals necessary for performing the result forwarding will become evident to those skilled in the art, as should the random logic used for generating such control signals.
If an instruction is not dependent on any of the current instructions, result forwarding is not necessary since the instruction's inputs are already in register file 117. When Issuer 118 decides to execute that instruction, RRC 112 tells register file 117 to output its data.
RRC 112 contains three subsections: a Data Dependency Checker (DDC) 108, Tag Assign Logic (TAL) 122 and Register File Port MUXes (RPM) 124. DDC 108 determines where the input dependencies are between the current instructions. TAL 122 monitors the dependencies for Issuer 118 and controls result forwarding. RPM 124 is controlled by Issuer 118 and directs the outputs of TAL 122 to the appropriate register file address ports 119. Instructions are passed to DDC 108 via bus 110. All source registers are compared with all previous destination registers for each instruction in window 102.
Each instruction has only one destination, which may be a double register in one embodiment. An instruction can only depend on a previous instruction and may have up to three source registers. There are various register file source and destination addresses that need to be checked against each other for any dependencies. As noted above, the eight bottom instructions corresponding to the lower two buckets are checked by DDC 108. All source register addresses are compared with all previous destination register addresses for the instructions in window 102.
For example, let's say a program has the following instruction sequence:
add R0, R1, R2 (0)
add R0, R2, R3 (1)
add R4, R5, R2 (2)
add R2, R3, R4 (3)
The first two registers in each instruction 0-3 are the source registers, and the last listed register in each instruction is the destination register. For example, R0 and R1 are the source registers for instruction 0 and R2 is the destination register. Instruction 0 adds the contents of registers 0 and 1 and stores the result in R2. For instructions 1-3 in this example, the following are the comparisons needed to evaluate all of the dependencies:
I1S1,I1S2 vs. I0D
I2S1, I2S2 vs. I1D, I0D
I3S1, I3S2 vs. I2D, I1D, I0D
The key to the above is as follows: IXRS1 is the address of source (input) number 1 of instruction X; IXRS2 is the address of source (input) number 2 of instruction X; and IXD is the address of the destination (output) of instruction X.
Note also that RRC 112 can ignore the fact that instruction 2 is output dependent on instruction 0, because the processor has a temporary buffer where instruction 2's result can be stored without interfering with instruction 0's result. As discussed before, instruction 2's result will not be moved from temporary buffers 116 to register file 117 until instructions 0 and 1's results are moved to register file 117.
The number of instructions that can be checked by RRC 112 is easily scaleable. In order to check eight instructions at a time instead of four, the following additional comparisons would also need to be made:
I4S1, I4S2 vs I3D, I2D, I1D, I0D
I5S1, I5S2 vs I4D, I3D, I2D, I1D, I0D
I6S1, I6S2 vs I5D, I4D, I3D, I2D, I1D, I0D
I7S1, I7S2 vs I6D, I5D, I4D, I3D, I2D, I1D, I0D
There are several special cases that RRC 112 must handle in order to do the dependency check. First, there are some instructions that use the same register as an input and an output. Thus, RRC 112 must compare this source/destination register address with the destination register addresses of all previous instructions. So for instruction 7, the following comparisons would be necessary:
I7S1, I7S2, I7S/D vs. I6D, I5D, I4D, I3D, I2D, I1D, I0D.
Another special case occurs when a program contains instructions that generate 64 bit outputs (called long-word operations). These instructions need two registers in which to store their results. In this embodiment, these registers must be sequential. Thus if RRC 112 is checking instruction 4's dependencies and instruction 1 is a long-word operation, then it must do the following comparisons:
I4S1, I4S2 vs. I3D, I2D, I1D, I1D+1, I0D
Sometimes, instructions do not have destination registers. Thus RRC 112 must ignore any dependencies between instructions without destination registers and any future instructions. Also, instructions may have only one valid source register, so RRC 112 must ignore any dependencies between the unused source register (usually S2) and any previous instructions.
RRC 112 is also capable of dealing with multiple register files. When using multiple register files, dependencies only occur when one instruction's source register has the same address and is in the same register file as some other instruction's destination register. RRC 112 treats the information regarding which register file a particular address is from as part of the address. For example, in an implementation using four 32 bit register files, RRC 112 would do 7 bit compares instead of 5 bit compares (5 for the address and 2 for the register file).
Signals indicating which instructions are long-word operations or have invalid source or destination registers are sent to RRC 112 from Instruction Decode Logic (IDL; not shown). IDL also tells RRC 112 which register file each instruction's sources and destinations will come from or go to.
A block diagram of DDC 108 is shown in
DDC 208 comprises 28 data dependency blocks 204. Each block 204 is described in a KEY 206. Each block 204 receives 3 inputs, IXS1, IXS2 and IXS/D. IXS1 is the address of source (input) number 1 of instruction X, IXS2 is the address of source (input) number 2 of instruction X and IXS/D is the address of the source/destination (input) of instruction X. Each block 204 also receives input IYS/D, which is the destination register address for some previous instruction Y. A top row 208, for example, receives I0S/D, which is the destination register address for instruction 0. Each block 204 outputs the data dependency results to one of a corresponding bus line 114. For example, the address of I2S/D must be checked with operand addresses S1, S2 and S/D of instructions 7, 6, 5, 4, and 3.
Each block 204 performs the three comparisons. To illustrate these comparisons, consider a generic block 700 shown in
These comparisons are represented by three comparator blocks 702, 704 and 706, respectively. One set of inputs to comparator blocks 702, 704 and 706 are the bits of the IYS/D field, which is represented by number 708. Comparator block 702 has as its second set of inputs the bits of the IXS1. Similarly, comparator block 704 has as its second set of inputs the bits of the IXS2, and comparator block 706 has as its second set of inputs the bits of the IXS/D.
In a preferred embodiment, the comparisons performed by blocks 702, 704 and 706 can be performed by random logic. An example of random logic for comparator block 706 is shown in
The random logic for comparator blocks 702 and 704 will be identical to that shown in
As will further become evident to those skilled in the art, various implementation-specific special cases can arise which require additional random logic to perform data dependency checking. An illustrative special data dependency checking case is for long word handling.
As mentioned before, if a long word operation writes to register X, the first 32 bits are written to register X and the second 32 bits are written to register X+1. The data dependency checker therefore needs to check both registers when doing a comparison. In a preferred embodiment, register X is an even register, X+1 is an odd register and thus they only differ by the LSB. The easiest way to check both registers at the same time is to simply ignore the LSB. In the case of a store long (STLG) or load long (LDLG) operation, if X and Y only differ by the LSB bit [0], the logic in
A data dependency check flowchart for IXS1 and TYS/D is shown in
A more detailed discussion of data dependency checking is found in commonly owned, copending application Ser. No. 07/860,718, the disclosure of which is incorporated herein by reference.
Because it is possible that an instruction might get one of its inputs from a register that was written to by several other instructions, the present invention must choose which one is the real dependency. For example, if instructions 2 and 5 write to register 4 and instruction 7 reads register 4, then instruction 7 has two possible dependencies. In this case, it is assumed that since instruction 5 came after instruction 2 in the program, the programmer intended instruction 7 to use instruction 5's result and not instruction 2's. So, if an instruction can be dependent on several previous instructions, RRC 112 will consider it to be dependent on the highest numbered previous instruction.
Once TAL 122 has determined where the real dependencies are, it must locate the inputs for each instruction. In a preferred embodiment of the present invention, the inputs can come from the actual register file or an array of temporary buffers 116. RRC 112 assumes that if an instruction has no dependencies, its inputs are all in the register file. In this case, RRC 112 passes the IXS1, IXS2 and IXS/D addresses that came from IFIFO 102 to the register file. If an instruction has a dependency, then RRC 112 assumes that the data is in temporary buffers 116. Since RRC 112 knows which previous instruction each instruction depends on, and since each instruction always writes to the same place in temporary buffers 116, RRC 112 can determine where in temporary buffers 116 an instruction's inputs are stored. It sends these addresses to register file read ports 119 and register file 117 outputs the data from temporary buffers 116 so that the instruction can use it.
The following is an example of tag assignments:
0: add r0, r2, r2
1: add r0, r2, r3
2: add r4, r5, r2
3: add r2, r3, r4
The following are the dependencies for the above operations (dependencies are represented by the symbol "#"):
First, look at I0; since it has no dependencies, its tags are equal to its original source register addresses:
I0S1 TAG=I0S1=r0
I0S2 TAG=I0S2=r1
I0S/D TAG=I0S/D=r2
I1 has one dependency, and its tags are as follows:
I1S1 TAG=I1S1=r0
I1S2 TAG=I0S/D=t0
I2 is also independent
I2S1 TAG=I2S1=r4
I2S2 TAG=I2S2=r5
I2S/D TAG=I2S/D=r2
I3S1 has two possible dependencies, IOS/D and 12SD. Because TAL 122 must pick the last one (highest numbered one), I2S/D is chosen.
I3S1 TAG=I2S/D=t2
I3S2 TAG=I1S/D=t1
I3S/D TAG=I3S/D=r4
These tags are then sent to RPM 124 via bus 126 to be selected by Issuer 118. At the same time TAL 122 is preparing the tags, it is also monitoring the outputs of DCL 130 and passing them on to Issuer 118 using bus 120. TAL 122 chooses the proper outputs of DCL's 130 to pass to Issuer 118 by the same method that it chooses the tags that it sends to RPM 124.
Continuing the example, TAL 122 sends the following ready signals to Issuer 118:
(The DONE signals come from DCL 130 via a bus 132. In connection with the present invention, the term "done" means the result of the instruction is in a temporary buffer or otherwise available at the output of a functional unit. Contrastingly, the term "terminate" means the result of the instruction is in the register file.)
Turning now to
Each block 302 of
An illustrative PE is shown in
As stated before, if an instruction depends on several previous instructions, PE 902 will select and output only the most previous instruction (in program order) on which there is a dependency. This is accomplished by connecting the signal showing if there is a dependency on the most previous instruction to the highest priority input of the PE 902 and the signal showing if there is a dependency on the second most previous instruction to the input of PE 902 with the second highest priority and so on for all previous instructions. The input of the PE 902 with the lowest priority is always tied high so that at least one of PE 902's outputs will be asserted.
Outputs 906 are used as select lines for a MUX 910. MUX 910 has eight inputs 912 to which the tags for each instruction are applied.
To illustrate this, assume that I7 depends on I6 and I5; then, since I6 has a higher priority than I5, the bit corresponding to I6 at outputs 906 of PE 902 will be high. At the corresponding input 912 of MUX 910 will be I6's tag for S1 (recall PE 902 is for I7S1). Because I7 is dependent on I6, the location of I6's result must be output from MUX 910 so that it can be used by I7. I6's tag will therefore be selected and output on an output line 914. I6's done flag, DONE[6] must also be output from MUX 910 so that Issuer 118 will know when I7's input is ready. This data is passed to Issuer 118 via bus 120. Since an instruction can have up to three sources, TAL 122 monitors up to three dependencies for each instruction and sends three vectors for each instruction (totaling 24 vectors) to Issuer 118. If an instruction is independent, TAL 122 signals to Issuer 118 that the instruction can begin immediately. 100961 The MSB of the tag outputs which are sent to RPMs 124 is used to indicate if the address is a register file address or a temporary buffer address. If an instruction is independent, then the five LSB outputs indicate the source register address. For instructions that have dependencies: the second MSB indicates that the address is for a 64 bit value; the third through fifth MSB outputs specify the temporary buffer address; and the LSB output indicates which bucket is the current bucket, which is equal to the BKT signal in TAL 122.
Like DDC 108, TAL 122 has numerous implementation dependent, (i.e., special cases) that it handles. First, in an embodiment of the present invention, register number 0 of the register file is always equal to 0. Therefore, even if one instruction writes to register 0 and another reads from register 0, there will be no dependency between them. TAL 122 receives three signals from Instruction Decode Logic (IDL; not shown) for each instruction to indicate if one of that instruction's sources is register 0. If any of those is asserted, TAL 122 will ignore any dependencies for that particular input of that instruction.
Another special case occurs because under some circumstances, an instruction in bucket 0 will be guaranteed to not have any of the instructions in bucket 1 dependent on it. A four bit signal called BKT1_NODEP_ is sent to RRC 112 from the IEU control logic (not shown) and if BKT1_NODEP[X]=1 then RRC 112 knows to ignore any dependencies between instructions 4,5,6 or 7 and instruction X.
An example for TAG assignment of instruction 7's source 1 (I7S1) is shown in a flowchart in
1 As evident by inspection of the remaining sections of
A representative block diagram of Issuer 118 is shown in
In the case of multiple register files (integer, floating and/or boolean), Issuer 118 is capable of issuing instructions having operands stored in different register files. For example, an ADD instruction may have a first operand from the floating point register file and a second operand from the integer register file. Instructions with operands from different register files are typically given higher issue priority (i.e., they are issued first). This issuing technique conserves processor execution time and functional unit resources.
In a further embodiment in which IEU 100 may include two ALU's, ALU scanning becomes a bit more complicated. For speed reasons, one ALU scanner block scans from I0 to I7, while the other scanner block scans from I7 to I0. This is how two ALU requests are selected. With this scheme it is possible that an ALU instruction in bucket 1 will get issued before an ALU instruction in bucket 0, while increasing scanning efficiency.
Scanner outputs 1003 are selected by MUXing logic 1004. A set of SELect inputs 1006 for MUX 1004 receive three 8-bit vectors (one for each operand) from TAL 122 via bus 120. The vectors indicate which of the eight instructions have no dependencies and are ready to be issued. Issuer 118 must wait for this information before it can start to issue any instructions. Issuer 118 monitors these vectors and when all three go high for a particular instruction, Issuer 118 knows that the inputs for that instruction are ready. Once the necessary functional unit is ready, the issuer can issue that instruction and send select signals to the register file port MUXes to pass the corresponding instructions outputs to register file 117.
In a preferred embodiment of the present invention, after Issuer 118 is done it provides two 8-bit vectors per register file back to RRC 112 via MUXOUTputs 1008 to bus 121. These vectors indicate which instructions are issued this cycle, are used a select lines for RPMs 124.
The maximum number of instructions that can be issued simultaneously for each register file is restricted by the number of register file read ports available. A data dependency with a previous uncompleted instruction may prevent an instruction from being issued. In addition, an instruction may be prevented from being issued if the necessary functional unit is allocated to another instruction.
Several instructions, such as load immediate instructions, Boolean operations and relative conditional branches, may be issued independently, because they may not require resources other than register file read ports or they may potentially have no dependencies.
The last section of RRC 112 is the register file port MUX (RPM) section 124. The function of RPMs 124 is to provide a way for Issuer 118 to get data out of register files 117 for each instruction to use. RPMs 124 receive tag information via bus 126, and the select lines for RPMs 124 come from Issuer 118 via a bus 121 and also from the computer's IEU control logic. The selected TAGs comprise read addresses that are sent to a predetermined set of ports 119 of register file 117 using bus 128.
The number and design of RPMs 124 depend on the number of register files and the number of ports on each register file. One embodiment of RPMs 124 is shown in
RRC 112 and Issuer 118 allow the processor to execute instructions simultaneously and out of program order. An IEU for use with the present invention is disclosed in commonly owned, co-pending application Ser. No. 07/817,810 the disclosure of which is incorporated herein by reference.
While Various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. Thus the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
|Citing Patent
|Filing date
|Publication date
|Jan 9, 2007
|Mar 23, 2010
|Sanjiv Garg
|RISC microprocessor architecture implementing multiple typed register sets
|Dec 21, 2006
|Jun 15, 2010
|Seiko Epson Corporation
|High-performance, superscalar-based computer system with out-of-order instruction execution
|Sep 17, 2008
|Apr 26, 2011
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|Dec 31, 2009
|May 10, 2011
|Intellectual Venture Funding Llc
|RISC microprocessor architecture implementing multiple typed register sets
|Feb 26, 2009
|Jun 7, 2011
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|Jun 10, 2005
|Oct 13, 2005
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|May 30, 2013
|Dec 19, 2013
|Apple Inc.
|Zero cycle load
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|May 23, 2007
Owner name: S MOS SYSTEMS, INC., CALIFORNIA
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Owner name: S MOS SYSTEMS, INC., CALIFORNIA
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|Mar 4, 2009
Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;REEL/FRAME:022343/0219
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subset: commoncrawl


text:
- Jimmy Strobl
- Falkenberg
- Sweden
This conversation is closed.
Did you know this about TED?
This Conversation is meant as a Conversation where we share all the things we've learned about TED that may be of interest for the TED community.
It's for all the small (and big) things about TED that we've found out that we can't really share anywhere else.
Like who made the first TED account ( http://www.ted.com/profiles/1 )
Or that there are about 200000 protected profiles on TED
Or that...?
You know, the silly things that some of us like so much.
Jun 18 2013: People don't know this, but you can actually write FUCK in a TED comment, if it's justified.
Frank Barry
Jun 18 2013: Gerald,
- +2
A sad example of your treasury of freedom of speech.
But, in today's moral fever, it was to be expected.
Jun 19 2013: swear words are not for the prissy but they are a legitimate part of the language and hold a legitimate place in everybody's vocabulary. often, they express how a person feels more accurately than attempting to eggshell-tiptoe around other peoples' sensitivity.
Frank Barry
Jun 19 2013: Scott,
- +3
Nothing wrong with not owning a value system.
And, a lack of vocabulary is more easily hidden with swear word or two.
As I age, I watch my children and grandchildren spew vile words in
everyday conversations.
I am so glad I was raised differently.Jun 19 2013: say rather "not owning a value system that is the same as yours".
curbing a person's vocabulary out of some traditional sense of appropriateness is akin to censorship.
if you don't like swear words then don't use them but don't get all "high-road" with others that choose to.
you may have missed the humour present in Gerald's post by focusing on the naughty word.Jun 19 2013: It got me thinking about the evolution of language, differences in generations and variety in value systems.
It was worth not censoring.
Frank Barry
Jun 20 2013: Gerald,
- +1
Still, I have a problem with lack of good manners.
A Victorian attitude to be sure. But one I am proud to use.
What you print on the internet is read by adults and children
with some parents that want to protect their children from such
you shared. It is a easy thing to dismiss. Obviously you did.
Intellect comes in many forms and colors.
Yours, a bit darker than mine.
I am so glad I was raised differently.
Amos Schrum
Jun 21 2013: I find it astonishing, that you, sir, who are openly against aggression in language has to underline and undermine your statements with subtle, but noticeable aggressions and insults such as " Obviously you did" or "Intellect comes in many forms and colors. Yours, a bit darker than mine. " or "I am so glad I was raised differently." or " Nothing wrong with not owning a value system." or " And, a lack of vocabulary is more easily hidden with swear word or two. " or "A sad example of your treasury of freedom of speech.
- +1
But, in today's moral fever, it was to be expected.". I thank you sir. For showing little children how to poison an serious and objective discussion and how to insult without swear words.Jul 1 2013: ...and you've just proven you can as it is STILL here! The comment, I mean :)
Frank Barry
Jun 19 2013: Scott,
- +2
You can and will speak using any language you choose. That is a given.
I am so glad I was raised differently.
A bit more "high-road" for your pleasure.
And, yes Scott, I did miss the humour in Gerald's post.
I see you've not used a naughty word, although you could have.
I appreciate that. Thank you.Jul 1 2013: I recently went back to a conversation area that I was involved in and soon discovered that my whole comment had been deleted, along with about 5 other posts from other TED members!
I was a bit surprised that mine had been removed as I always am mindful of what I say and post and so feel that a degree of cencorship had been applied in an uncaring manner.
By this I mean that, I had put a lot of thought into what I had put up and was very fair in what I had to say and used no profanities or racial/religious slurrs etc, yet, my comment was wiped!
Now I feel somewhat uneasy as I do not know whether my posts will be mysteriously deleted....no explanation...no idea as to what was said on the back of what I had said from others.
It seems now like we can only perhaps view a sanitised version of TED comments, censored for what purpose?
If freedom of speech is a right, then what has become of this right in the context as I have described above?
If the ethos for TED is about spreading ideas, then how can there be this if there is such a thing as a wrong idea which culminates in cencorship/deletion.I had always thought that there was no such thing as a bad idea and if something was, then conversation and clarity would sort it out...... : D
Jul 1 2013: Time Traveller,
I think I know the conversation you refer to, and my comments were removed as well. Unfortunately, that conversation evolved into personal comments that were off topic and disrespectful. Your comments in that conversation were very helpful and appropriate in my perception.
The TED terms of use allows TED moderators to remove disrespectful, off topic comments, and often, the whole off topic thread is removed, rather than leaving some comments that are no longer relevant to the topic conversation.....make sense?
Usually, TED sends a notice to you which says something like.....sorry your comment was removed because it was a reply to another comment that was removed.....or something like that.
Your comments seem very thoughtful, respectful and on topic, so don't give up.....ok?Jul 1 2013: What Colleen writes here is correct. If something you wrote in Conversations is itself considered inappropriate, you will always get an email from the moderators about it. Sometimes there is a part of a thread in which someone is being sufficiently disrespectful of others to be in violation of terms of use, and in that case, the perfectly valid comments in response might be eliminated along with the comments in violation, because they would just be hanging there without anyone's being able to understand them out of context.
The standards for deleting comments from the actual talks area, are, I believe, different from the criteria here.
Jimmy Strobl
Jun 27 2013: A Docs sheet of (almost) all TED Talks https://docs.google.com/spreadsheet/ccc?key=0AsKzpC8gYBmTcGpHbFlILThBSzhmZkRhNm8yYllsWGc&hl=en#gid=0
- +1
Jun 23 2013: I am going to share this here, I have shared it before in other conversations.
- +1
Did you know that AFTER a conversation CLOSES, the TED member that posted the thread can still access it, and post CLOSING REMARKS.
These closing remarks appear in a gray box at the top of the thread.
Doing this allows a future reader to have a good idea of the major points of the conversation.
Still, today, after being a TED member for a while, I rarely see anyone enter closing remarks.
I think it is a nice thing to do, I think it is good TED ediquette.
It is never too late to go back to your old conversations and enter closing remarks.
There is no time limit.
Just click over there at the left side of the screen where SEARCH CONVERSATIONS appears.
Change the Search: criteria to "Conversations by" then type YOUR name, and all the conversations you have ever started will display.
You can then choose to enter your closing remarks......you get to have the last word. :)
I hope more TEDsters use this feature in the conversations.
Jun 24 2013: Have you ever compared the closing remarks to the way you might have summarized the discussion in the thread?
Jun 24 2013: Are they not one and the same?
- 0
Fritzie -
Jun 24 2013: Sometimes people open a conversation with a particular view and report essentially that that view was vindicated. In an active conversation, it can be challenging to represent the range of central ideas in a way that captures the debate or discussion.
- +1
The summary is interesting for what the host of the thread took away from it, which may be quite different than what others in the conversation or a silent reader might.
Jun 24 2013: It can be a challenge to represent the range of central ideas in a way that captures the debate, but we can still give it a go. I have seen conversations with 16 comments, and still no closing statement.
- +1
I think that, besides showing good manners, putting something of a closing statement at the end of a conversation shows that the originator of the post took an active role in the conversation, and walked away with something........and if they lack words, they could at least thank the participants.
I think it shows respect for others, but of course this is my personal way of living, I cannot expect everyone to be the same.
I kind of see it this way........how often do you call someone up with a question, listen to them ramble on with their reply, then hang up the phone without so much as a good-bye?
I, personally, like to click on conversations that have ended, in a hopes to get some sort of closure. Even if I did not post a comment in the conversation, I am hoping to get a summary or an idea about what went on.
And, if TED provides you with this feature, why not take advantage of it?
But, I have been sadly disappointed in the lack of closing statements which are posted.Jun 18 2013: Hmmm, or rather things that make you go hmmm. I am relatively new to this whole TED experience, while at 50 + TEDCRED Jimmy you are somewhat more experienced!
I like your thinking, in so far as you create circumstances that initiate future/big picture ideals! From memory, I think there are some 200,000 TED members. I had mentioned in one of my posts somewhere here that only approximately (I think it is statistically) that only 5% of that membership will put up posts, the rest are readers.... so what is that then, 10,000.... from what I've seen it is nooooowhere near that amount! My reckoning 1000 tops, which would then be what, half a percent of 200,000!
What can we conclude, from this, I don't exactly know but it does profer the question, of an online membership such as this, how many real members are there? That is to say, posters can be counted, however readers are unqualified, tho dare I say when they sign in there would be the potential to track membership traffic!
Furthermore, I have noticed that you only put a short 1week time frame for your post, (as I now know) with the knowledge that if there is a lot of interest in it, you can extend it for a month. In my newbie ignorance I posted an idea with a 1 month time frame and pretty much seem to be the main contributor to it now after only some 10 posts and 28 odd days to run!
I have also noticed that there is a particular topic that (apart from my TED Prize one) people avoid. It has to do with a religious belief that from my observation, people are SCARED to discuss for fear of being potentially subject to consequences that they would rather not potentially subject themselves to. As clearly am I, which is like Voldemort (of Harry Potter fame) Iwon't mention.
Also, consider, what becomes of all our TED words posted here? Who owns them? Where do they go? What becomes of them and what is the TED big picture ideal and when will the TED Community be informed of it? What does TED stand for? Who made it up!:D
Jun 18 2013: If you click on the link above that reads TED Community, you will see there are a bit over 189,000 members with photos and something over 1.74 million without photos.
Jun 18 2013: Fritzie,
I haven't learned how to take my picture yet, not how to upload.
Of course, I just don't care to try. lol
TED is a great way to waste a couple of hours fighting over niggly points.Jun 20 2013: Thanks for the update Fritzie, re TED member numbers! Wow it is 10 X larger than what I thought ! This then makes my speculation on the number of members who end up posting on the TED medium even significantly smaller again, proportionality.
Still curious to know some of the answers in terms of the bigger picture as I posed in my earlier post ! : D
Fritzie -
Jun 20 2013: Here is what I can tell you. TED stands for Technology Entertainment Design. The mission is to spread ideas, which the non-profit does in a continuously evolving way by gathering the most interesting and creative speakers across fields and bringing communities together to listen to and interact about them. Some of this is live via conferences, where talks can trigger collaborations among those in attendance. The TED Prize winners are some that can become a focus for collaboration, but any speaker's project might, as those in attendance interact with them during breaks.
- +1
Another component is online, where anyone in the world can listen to and comment on the talks for free, engaging also in discussions about other ideas, as we do here
There is no mystery to me in people's being members yet not participating in online discourse. One needs to sign in to have an alert of talks delivered to the email box, and the number of people interested in hearing the talks would, of course, be vastly greater than those who might want to converse here. There is little overlap, for example, between the TED speakers people want to hear and people posting online.
There are groups of people who listen to TED Talks together or listen and then get together. So the ideas in the talks travel through word of mouth and discussions take place in lots of private venues among people who want to discuss the ideas together. The TEDx events are kind of like this, except that those are independently curated by the hosts of those.
I expect TED would love to see ideas presented here and people connected by and inspired by them to take actions that solve problems and improve the quality of life on the planet.
I do not notice general avoidance of religious topics here. People who do not participate in those likely have a range of reasons other than the one you mention. Some people are not interested in religion. Some are private about faith. Some notice and expect to read mainly hardened views.Jun 18 2013: Well, as Firitzie says there are 1.74 million accounts that show up when you do a worldwide search more members with or without photos http://www.ted.com/profiles/browse?name=&company=&country=&sort=date&hasphoto=0
And I managed to find out that there's been at least 1.92 million accounts created. You do this by adding the numbers 1920000 after http://www.ted.com/profiles/
If you check the ratio of the first twenty profiles you will see that many are private profiles and some seem to have been deleted (Chris Anderson has profile number nine http://www.ted.com/profiles/9 ) .
Maybe the Wiki can lead you somewhere on the history of TED http://en.wikipedia.org/wiki/TED_(conference)
Frank Barry
Jun 18 2013: JImmy,
- +1
I am positive your research will find eager readership.
Do you have anything to do in life?
Jimmy Strobl
Jun 19 2013: Not right now... Don't you ever play around with useless information?Jun 26 2013: Did you know that there's a thesis paper on "TED Conversations as a community". I just found out now (Googled my name and 4 pages in there it was).
- +1
It's 15 pages long and was written in 2012. Sadly for many of you it's in Danish BUT you could always translate it if you're really curious.
Here's the pdf http://isabelaagaard.dk/wp-content/uploads/2012/05/Ted-Conversation-som-Community.pdfJun 19 2013: 189,726 members of the TED Community have a profile with photosJun 18 2013: What's wrong with having a protected file. I'm of the old guard, I value or like a small group around me rather than an open book, which is perfectly fine for everyone who likes it or prefers it. I don't have much to contribute other than the dribble that formulates behind my eyes. Why is there such an interest in protected profiles ( not that it is a global issue) but it seems to crop up a lot.
Jun 18 2013: I didn't say that it was wrong, it was simply an example of info about TED that i thought few knew... Nothing more.
Jun 18 2013: Of course, i just used it as a launching rant Jim. There is a group of humans out there that believe a blanket one mind one thought society is our future where all is divulged and nothing is sacred yet we have had this communication medium for only 20 years and already the group mindset is skewed. Without knowing it people have become vampires of others details. quite a neurotic post, conspiracist mania? He heh! Good to see you on Jim.Jun 18 2013: Ken and Jimmy,
You guys can make a lot of something out of nothing.
And, I'm just as bad. I am here writing this.
Arrruggh !!!!!


text:
Rainbow Cookies {Slice and Bake}
Sometimes, in the middle of cold and flu season, I wonder if the feds are going to come and knock down my front door. They will take me away and interrogate me for my extra large purchases of Sudafed and search my house in hopes of finding my meth lab.
You know, the one I keep in my basement?
Just kidding, I don't have a basement.
Ever since they started carding for the little red miracle pills, I feel a little like a druggie every time I go to the pharmacy.
"Can I have the generic Sudafed please? A 96?" I ask.
"We're out of 96," replies the pharmacist.
"Okay, then two 48's?" I inquire, discreetly sliding my driver's license across the counter like I'm expecting to be slipped a little white packet or something.
I think I've bought Sudafed at least four or five times just this school year so far. And, with the way things are going, I anticipate needing to buy it a few more times before summer. (You all remember how I pop the little red pills at the first hint of stuffiness, to ward of ear infections, right? That I'm really not an addict?)
The problem is that they only let you buy two packages. Only one if it's the 96-pack. You can buy two 48-packs. But the thing I don't understand? They won't let you buy four 24-packs. Um, what's the difference between if I buy one 96 or four 24's? Oh well, no one ever said our government had common sense.
How does that relate to these cookies? It doesn't. It's just that I'm kinda in the middle of a Sudafed-fever-induced fog and couldn't thing of anything glittery and rainbowey with a side of unicorns to write about.
Have I mentioned my kid is a horrible sharer? Unless it's germs. Then she gives them away freely.
I made these cookies for Jordan's birthday party, but they would be perfect for St. Patrick's Day. Now, they take a little work but the overall product is totally worth it.
I swear, I think these are the best tasting (flavor and texture) sugar cookies I've ever eaten. The dough is a bitch to work with, it's very sticky and kinda gets everywhere, but you'll thank me, I promise. They are that good.
The secret is to freeze the dough before slicing. And then you freeze them again before baking, to reduce spreading.
I made clouds for some of my cookies. I dyed the batter white and rolled up little balls to place at the ends of the rainbow.
I also bent the rainbows a little to go with the clouds. They looked better that way.
Bake them, and try not to eat the whole batch. These are some seriously addictive cookies.
Kind of like Sudafed.
Rainbow Cookies {Slice and Bake}
Get the cookie recipe at Good Life Eats or use refrigerated dough, or your favorite recipe.
Gel food colorings: red, orange, yellow, green, blue, purple, and white (if you do not wish to have clouds, you can skip the white)
Make cookie dough. (Or use your favorite dough.)
If you want clouds, separate ¼ of the dough into a separate bowl and color it white. Then equally divide the rest of the batter into six separate piles. (If you are not making clouds, just divide it into six portions from the beginning.)
Color each of the six portions of dough a different color, one for each color of the rainbow. I did this by using a hand mixer and rinsing the beaters and the bowl in between each color. Wrap each color individually in plastic wrap and chill for about a half an hour.
Working with one dough at a time, place each color between two sheets of wax paper and roll into a large rectangle. (The dough will still be pretty sticky at this point.) Once you have 6 flat rectangles of dough (each between two sheets of wax paper), chill them until they are firm, at least an hour.
Remove from refrigerator. Place the purple layer on a new sheet of waxed paper. Layer the colors: purple, blue, green, yellow, orange, red. Cover with plastic wrap and freeze until very firm.
If you are making clouds: roll the white portion into small balls and chill.
When you are ready to bake, heat the oven to 350°. Remove dough from freezer and slice strips across the shorter side about ¼ inch thick and then cut each strip in half (or desired size). Place cookies on a parchment lined cookie sheet and freeze again to minimize spreading while baking. (This dough softens up very quickly.)
If you want clouds, place a white ball at each end of the rainbow (I "bent" my rainbows a little before attaching the clouds) and press to resemble clouds. I didn't have enough clouds for the entire batch, but that was fine. I ended up with about 24 cloud rainbows and the rest were plain.
Bake for 6-10 minutes. Cool on cookie sheet for a few minutes before transferring to a cooling rack. Serve with smiles and green milk for St. Patrick's Day!
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21 Responses to "Rainbow Cookies {Slice and Bake}"
You're such a whizz! Thanks for linking up at Thriving on Thursdays. The linky party starts in just over 12 hours. Would love to see what you've been up to this week.
Anne @ Domesblissity
These are GORGEOUS!! So cute and love the method of freezing the dough. Thanks so much for stopping by Mop It Up Mondays!
They are so beautiful…& thanks for the idea of freezing the dough!!
I would like if you link with my event for decorations….
Oh my!!!!!! They look SOOOO YUMMY!!!!!!!!! I want some PLEASE!!!!
I would love it if you shared this over at The DIY Dreamer!
These are so fun! And have fun with that Sudafed!
Those are such fun cookies!!! I am loving all things rainbow right now too:-)
Those totally remind me of the 80s! How fun!
Pure cuteness!
Awesome cookies! You are so smart!! Sharing these little beauties, for sure!
Take care,
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Is nobody else going to bring up the fact that these look like penises or all we are trying to ignore it? still cute though
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I know its early but I am trying to plan a mini vacation with my family to South Florida. I want to attend training camp and I know there are certain dates they are open to the public. I didnt see anything on the website so I will have to call the office for that information.
Anway, can anyone give me some information or tips on where to stay, what to bring, what there is to do when they are not practicing, etc.


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Looking Back at the Last Year in HIV Science, Activism and Policy
For each year that passes since 1981, when the human immunodeficiency virus infection/acquired immunodeficiency syndrome (HIV/AIDS) was first clinically observed in the U.S., there have been new advances in science, policy, activism and hope. In this capacity, 2012 has been particularly bright. From the repeal of DADT, to the end of preexisting conditions with Obamacare and scientific advances, there is more hope than ever for the roughly 34.2 million people that were living with HIV in 2011. Some highlights from this incredibly exciting year follow:
One amazing stride forward in the treatment of HIV was the FDA approval of Stribild and Truvada, both HIV-1 Infection Drugs. They are single-dose medications approved for the treatment of HIV, and may significantly simplify the treatment protocol for sufferers of HIV, especially those who are "treatment-naïve," or who have never received treatment before. Over the past decade, co-formulated HIV medicines have simplified therapy for many patients and have become standard of care. The approval of Stribild and Truvada will provide physicians and their patients an effective new single tablet treatment option for individuals starting HIV therapy for the first time.
In July of this year, Timothy Brown, a.k.a. The Berlin patient, became the first person to be considered medically cured of HIV. In 2007, Brown was given a stem cell transplant as part of his treatment for acute myeloid leukemia (AML). After 20 months without antiretroviral drug treatment, it was reported that HIV levels in Brown's blood, bone marrow and bowel were below the limit of detection. The virus remained undetectable over three years after the first transplant. These findings, while still under scrutiny by medical researchers, have given hope to millions.
Earvin "Magic" Johnson shocked the world in 1991 when he announced he had HIV and abruptly retired from a hall of fame basketball career. Now, 21 years later, Magic Johnson is extremely active in HIV/AIDS education campaigns through the Magic Johnson Foundation and has sought to show that the risk of infection was not limited to traditionally high-risk groups like IV drug users, and using his life as an example of the fact that an HIV diagnosis is not a death sentence. At age 53, Johnson is an activist, entrepreneur and the new owner of the Los Angeles Dodgers.


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An amazing day for Sooner Nation! On New Year's Day 2003, College Football's most historic Bowl game, the Rose Bowl, belonged to Oklahoma from the opening kickoff, and by the time the picture for this poster was taken in the second quarter, the crimson-and-cream party had already started. With a 17-0 lead and Washington State's offense pinned back in its own red zone...SNAP! The moment is preserved for all-time, and is now available for your wall!
This incredible panoramic poster features the grand old New Year's game in all its glory, and as you pan across the image you feel like you are actually there! You can read the scoreboards, see the players on the sideline and the action on the field, the cheerleaders, the marching bands, and the massive sea of red-and-white-clad Cougars and Sooners fans that packed the stadium. With the stunning San Gabriel Mountains rising up beyond the grandstand, and the mature trees all around, football glory and natural beauty collide here like nowhere else in America! For fans of the Rose Bowl and the Oklahoma Sooners, this piece is a must-have addition to your wall, forever invoking memories of Bob Stoops, Nate Hybl, Quentin Griffin, Antwone Savage, Curtis Fagan, Trent Smith, Teddy Lehman, Derrick Strait, Jonathan Jackson and the rest of the boys from that unforgettable afternoon. Worthy of a nice frame and a central location on your sports wall-of-fame!
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Charles C Harrington
Professional Background
Educational Background
Ph.D., Harvard University
Scholarly Interests
Human development in social and cultural contexts. The study of Pathmakers: resiliency, resistance, invulnerability and success in at-risk populations. Psychological anthropology and education. Psychoanalytic anthropology.
Selected Publications
Paths to Success: Beating the Odds in American Society (Harvard University Press).
Educational Policy in an Era of Conservative Reform (AMS Press).
Race, Sex, and National Origin: Public Attitudes of Desegregation (AMS Press).
Psychological Anthropology and Education (AMS Press).
ALERTA: A Multicultural, Bilingual Approach to Teaching Young Children. (Addison-Wesley)
A Psychological Anthropology of Depression. in progress.
principal publications
1997. "Jackson's Meadows: A Retrospective Foreword" Introduction to Communal Organization and Social Transition. New York: Peter Lang Publishing.
1993. "Making Culture and Making People." Contemporary Psychoanalysis 29(4): 251-271. Discussion by Mary Lionells.
1990. "Review of Effective Education: A Minority Policy Perspective by C.V. Willie." Teachers College Record 92(1): 150-151.
1990. "Review of Central American Refugees & U.S. High Schools: A Psychosocial Study of Motivation & Achievements by Marcelo M. Suarez-Orozco." American Anthropologist 92(3): 768-769.
1987. (With S.K. Boardman and S.V. Horowitz) "Successful Women" in Larwood, L. & Gutek, B. (eds) Women's Career Development. Newbury Park, CA: Sage Publications. Pp 66-85.
1986. (With M.R. Barnett and P.V. White) "Education Policy in an Era of Conservative Reform" in Barnett, M.R. & Harrington, C. C. (eds) Educational Policy in an Era of Conservative Reform. New York: AMS Press. Pp vii-xvi.
1985. (With M. R. Barnett) "Perspectives on Desegregation in Public Education" in Barnett, M. R. & Harrington, C. C. (eds) Race, Sex and National Origin: Public Attitudes of Desegregation. New York: AMS Press. Pp ix-xv
1984. (With M. R. Barnett) "Interdisciplinary Perspectives on Equal Education" in Barnett, M. R. and Harrington, C. C. (eds) Readings on Equal Education: 7. New York: AMS Press. Pp ix-xvi.
1982. "Issues from the Issues." Anthropology and Education Quarterly 13(4): 323-346.
1981. "Bilingual Education: A View from 1980." Urban Diversity Series #68, ERIC-CUE. New York: Teachers College, Columbia University.
1980. "Textbooks and Political Socialization" Teaching Political Science 7(4): 481-500.
1978. "Bilingual Education, Social Stratification and Cultural Pluralism." Equal Opportunity Review. Summer: pp 1-14.
1977. "From the Editor" Anthropology and Education 8(3): 192.
1977. "Methods and Issues in Cross-Cultural Research" in Adler, L. (ed) Annals of the New York Academy of Sciences: Issues in Cross-Cultural Research. 285: 89-93.
1976. "Textbooks and Political Socialization: A Multivariate Analysis" I.U.M.E. Report Series #4. Institute for Urban and Minority Education, Teachers College, Columbia University, New York City.
1976. "Schools & Peers in the Political Socialization of the Urban Poor." Equal Opportunity Review, August: 1-8.
1976. "Psychological Anthropology and Educational Practice." Teachers College Record 78(1): 69-76.
1976. "Behavioral Scientists Comment." Medical Tribune. January 21: 13, 20.
1975. "A Psychological Anthropologist's View of Ethnicity and Schooling." IRCD Bulletin 10(4).
1975. "Review of The Next Generation by J. Ogbu." Teachers College Record 77(1): 136-138.
1973. "Pupils, Peers and Politics" in Burnett, J. and Kimball, S. (eds) Learning and Culture. University of Washington. Pp 131-159.
1973. "Review of Cross-Cultural Studies of Behavior by I. Al-Issa and W. Dennis" American Anthropologist 75(2): 389-390.
1972. (With P. Gumpert) "Intellect and Cultural Deprivation." Teachers College Record 74(2): 261-273.
1972. "Review of Ghetto School by Gerald Levy." American Anthropologist 74(4): 991-992.
1972. (With J.W.M. Whiting) "Socialization Process and Personality" in Hsu, F.L.K. (ed) Psychological Anthropology (2nd Edition). Schenkman. Pp 469-507.
1971. "Review of Soulside by Ulf Hannerz." Teachers College Record 72(3): 471-473.
1971. (With M.W. Adler & N. Adler) "Toward the Learning of Participatory Citizenship." Impact on Instructional Improvements 6(3): 20-23.
1968. "Sexual Differentiation, Socialization, and Some Male Genital Mutilations." American Anthropologist 70(5): 951-956.
1968. "The Myths of Ethnomusicology." American Record Guide, May: 865-868.
1966. (With M.L. Wilkins) "Treating the Social Symptoms of Mental Illness." Hospital and Community Psychiatry 17(3): 136-139.
1963. (with E. Cummings) "Clergyman as Counselor." American Journal of Sociology LXIX(3): 234-243.
ITSF 4012: Cross-cultural studies of learning
Analyses of basic anthropological concepts, with particular reference to the influence of cultures and subcultures on the learning process, to education in multicultural classrooms, and to the relevance of psychological anthropology to educational issues. Four-point enrollment requires attendance at film showings before or after class and additional discussion sessions held at hours to be arranged.
ORLJ 4901: Research and independent study in social-organizational psychology
ITSF 4902: Research Independent Study:International Transcultural
Research Independent Study:International Transcultural
ITSF 5000: Methods of inquiry: Ethnography and participant observation
This course examines the methods of the social sciences as they relate to ethnography and participant observation. The course emphasizes the role of theory, characteristics of various research techniques, and the importance of integrated research design. The course provides opportunities to practice ethnographic research techniques, including developing a research question, designing a study, interviewing, conducting observations, and analyzing data.
ITSF 5013: Psychological anthropology
The concepts, theories, and methods of psychological anthropology. Cross-cultural studies of learning processes. Emphasis on recent work in the field, prob lems of cross-cultural methodology, and the study of socialization.
ITSF 6511: Seminar in psychological anthropology
Permission required. Prerequisite: ITSF 5013. A research seminar focusing on current issues in psychological anthropology.
ORLJ 6901: Advanced research and independent study in social-organizational psychology
ITSF 6910: Studies in anthropology and education
Advanced students may register for intensive individual study of some aspect of their concentration. Registration is only by permission of the instructor under whose guidance the work will be undertaken. Times for individual conferences will be arranged. Enrollment may be for 1 or more points each term, and registration is not limited to one or two terms.
ITSF 6911: Workgroup in psychological anthropology
This workgroup meets every other week to discuss current issues in psychological anthropology. It also discusses and reviews current research and proposals for research of workgroup members, including faculty, alumni, and doctoral students concentrating in psychological anthropology.
Documents & Papers
Download: Behavioral Scientists Comment [PDF]
1978. Equal Opportunity Review. Summer. pp 1-14
Download: Bilingual Education, Social Stratification and Cultural Pluralism [PDF]
Download: Bilingual Education 1980 [PDF]
Download: Clergyman as Counselor [PDF]
Download: From the Editor [PDF]
Download: Intellect and Cultural Deprivation [PDF]
Download: Perspectives on Desegregation [PDF]
Download: Education Policy [PDF]
Download: Interdisciplinary Perspectives on Equal Education [PDF]
Download: Issues from the Issues [PDF]
Download: Jackson's Meadows [PDF]
Download: Discussion: Making Culture [PDF]
Download: Making Culture and Making People [PDF]
Download: Methods and Issues [PDF]
Download: Towards the Learning of Participatory Citizenship [PDF]
Download: Psychological Anthropologist & Ed Practice [PDF]
Download: A Psychological Anthropologist's View [PDF]
Download: Pupils, Peers and Politics [PDF]
Download: Review of Suares Orozco [PDF]
Download: Review: Al-Issa and Dennis [PDF]
Download: Review of Effective Education [PDF]
Download: Review: Levy [PDF]
Download: Review: Hannerz [PDF]
Download: Review: Ogbu [PDF]
Download: Schools & Peers [PDF]
Download: Sexual Differentiation, Socialization and Some Male Genital Mutilation [PDF]
Download: Socialization Process and Personality [PDF]
Download: Treating the Social Symptoms of Mental Illness [PDF]
Download: Successful Women [PDF]
Download: Textbooks and Pol Socialization: Analysis [PDF]
Download: Textbooks and Political Socialization [PDF]


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Garden Rocker Gardening Kneeler Bench
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Albuquerque's City Hall is located at 400 Marquette NW, Albuquerque, NM 87102.
Many City departments are based out of City Hall. View the department listing to find department addresses and other contact information.


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I ask this question more to satisfy my curiosity than to tend to a pressing need. But looking at the carpet in my condo (two bedroom) I don't notice any cuts in it. Was it installed as one continuous piece?
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Home Improvement Stack Exchange is a question and answer site for contractors and serious DIYers. It's 100% free, no registration required.
Carpet is generally sold in 12' wide rolls.
Good carpet installers use a combination of seam tape and a good stiff comb to make seams vanish.
What they do is lay down the "tape" which is actually a 4" wide strip of cloth mesh coated in wax.
They then butt the seams of the carpet up together nice and tight, and run a hot iron under the carpet between the seams (see the label on the pic above) and while the wax is still melted, press the carpet into it. Then they just comb the carpet together to hide what seam may still show.
Sounds easy but having tried it once - NEVER AGAIN. I will hire a carpet installer any day of the week.


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The surf life is the good life and you're all about making life good. Take your energy to a tropical level with this Lost in Hawaii towel tank from Lost. The printed island graphics and the terry-knit fabric are ready for some seaside action with you!
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25 November 2011
Posted in DinoDigs
Have you ever heard of Dr. Linda Webster? We hadn't either, but it turns out, she's the newest addition to the DinoDigs team. Dr. Webster is actually a fictional character who is adding a new take on the exhibit signs in DinoDigs. Recently, each sign panel was taken out and replaced by Dr. Webster's field journals, notes and memos.
The signs give guests a new way of looking at the exhibits and include interesting facts about each dinosaurs such as where they lived and what they ate. More importantly, they provide an opportunity for critical thinking, asking guests questions that require them to use the knowledge they gained to form their own hypotheses.
According to Kim Hunter, Senior Director of Exhibit Development here at the Science Center, the new signs help play an important role in the visitor experience. "The new interpretations in DinoDigs allow guests to pretend they are an actual paleontologist," Kim noted. "Along with some interesting information about each dinosaur, you can see what the field of paleontology is like and the processes these professionals use through the eyes of a fictitious scientist."
So, the next time you're in DinoDigs, make sure you meet Dr. Webster. You'll be glad you did!


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Penn Takes Two From Baseball on Saturday
March 22, 2014
PHILADELPHIA - The Lafayette baseball team dropped the first two games of its home-and-home series with Penn on Saturday afternoon at Meiklejohn Stadium. The Quakers took the first game by a final of 3-0, before winning the nightcap 8-3.
Lafayette Athletics, as a partner in the mission of the College, provides an incredibly effective learning experience for student-athletes through competitive NCAA Division I athletics. Lafayette sponsors 23 varsity sports with more than 600 student-athletes.Mission Statement | Leopard Tradition | Staff Directory | Feedback
The Lafayette Sports Network (LSN) handles all multimedia elements and advertising sales for athletics at Lafayette College. LSN is the Patriot League leader in delivering high-quality programming worldwide via television, radio, streaming video and satellite.Advertising and Sponsorships | Digital Media | LSN TV


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In Biblical Hebrew, what is the "internal passive with characteristic u vowel"?
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Mi Yodeya is a question and answer site for those who base their lives on Jewish law and tradition and anyone interested in learning more. It's 100% free, no registration required.
It sounds like you are referring to the adjectival form "qatul", in which the u vowel is inserted between the second and third letters of the root. It denotes the passive of a pa'al verb, usually functioning to modify a noun. For example, etz shatul (Psalms 1).
It refers to forms like
And also to the extinct qal internal passive, found only rarely and in altered form in Hebrew, e.g. yullad ילד ) יולד), Ruth 4:17.