text:
I have noted some comments regarding the size of the books. Can you please confirm the actual dimensions.
great for collecting, not as easy to read because they are heavy but they will last....
The Lord of the Rings: Return of the King/Two Towers/Fellowship of the Ring (Hardcover)
One Ring to rule them all, One Ring to find them, One Ring to bring them all and in the darkness bind them
In ancient times the Rings of Power were crafted by the Elven-smiths, and Sauron, The Dark Lord, forged the One Ring, filling it with his own power so that he could rule all others. But the One Ring was taken from him, and though he sought it throughout Middle-earth still it remained lost to him. After many ages it fell, by chance, into the hands of the hobbit, Bilbo Baggins.
From his fastness in the Dark Tower of Mordor, Sauron's power spread far and wide. He gathered all the Great Rings to him, but ever he searched far and wide for the One Ring that would complete his dominion.
On his eleventy-first birthday, Bilbo dissapeared bequeathing to his young cousin, Frodo, the Ruling Ring, and a perilous quest: to journey across Middle-earth, deep into the shadow of the Dark Lord and destroy the Ring by casting it into the Cracks of Doom.
The Lord of the Rings tells of the great quest undertaken by Frodo and the Fellowship of the Ring: Gandalf the wizard, the hobbits Merry, Pippin and Sam, Gimli the Dwarf, Legolas the Elf, Boromir of Gondor, and a tall, mysterious stranger called Strider.
|FICTION / Fantasy / Epic
|Publisher Date
|2002-11-01 00:00:00.0
|Houghton Mifflin Harcourt
|10.25 in
|8.0 in
|4.5 in
|Unit weight
|10.5 lb
|Return of the King/Two Towers/Fellowship of the Ring
|Volume Number
|Tolkien, J. R. R.
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collector edition
great for collecting, not as easy to read because they are heavy but they will last.Read More
Great set for fans!
Love the books, love the films! Great set to have for fans and collectors. I took the dust covers off. The books are red with gold lettering. Arrived fast and in great condition.Read More
Great Keepsake
Excellent quality in a good, box-cover. Large size. Excellent for people who love books and want some to hold in hand, rather than electronicRead More
The Lord of the Rings box set by J?R.R Tolken ( Ha
I perchance this as a gift. The first seat arrived damaged. Called overstock they sent out new set arrived in time for Christmas. I was very happy with Customer service they where great help. My sister was very happy with this set. Thank you Overstock for every thing.Read More
Awesome Boxed Set
I looked for a nice Lord of the Rings boxed set for my husband for quite a while before I came accross this set. The price was good so I bought it for him. It looked very nice in the pictures but I was a little hesitant that the quality would not be that good. I sure was surprised! The quality is excellent! The pages of the book are very smooth and kind of shiny like you would find in an encyclopedia. The books are a little taller than I expected and very substantial. If you are just looking for a set for reading quickly, this is not the set for you. This is a set to read, cherish and display!Read More
Bigger than I anticipated
Classis story, worth owning on hardback! Nook and Kindle is one thing, but I will always have this book! We had a slight complication with shipping. We received the books the first time and it looked as though the carrier had just thrown the box around and damaged the product! We contact O and they sent another set, no questions asked, given that we returned the damaged! Everything worked out great!Read More
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The product dimensions are 7.90 inches wide by 10.25 inches high by 4.30 inches deep.
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text:
Black Taffy (2 lb. Bag)
Black Taffy, an Old-Time Treat for the Licorice Lover in You
Black Taffy (2 lb. Bag)
Black Taffy, an Old-Time Treat for the Licorice Lover in You
What Our Customers Are Saying about Our Black Taffy (2 lb. Bag) …
"Dear Mr. Orton, I was so thrilled to receive your catalogue and find you had Black Jack Taffy. This was my favorite as a kid and I have looked for this candy for many, many years. Thank you!" - Patty Moran, Staunton, VA
"My sisters and I have searched for this "blackjack taffy" every time we go to different places on vacation or anywhere. We loved this as kids and more as adults! Haven't been able to find it for years! I will be a big hit when I give them this!!" - sue, broken bow, NE
"Oh my gosh, i finally found my true love of candy. I remember buying this at my childhood store, in Johnson City, NY. I have talked about this candy for many years. Than you. I will be ordering this." - Judy Matthews, Binghamton, NY

subset: commoncrawl


text:
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You have chosen to receive our #NAMED_LISTS# newsletters at #EMAIL_ADDRESS#. You will receive an e-mail shortly confirming your subscription. So excited to have you!
Refinery 29
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We know Miami girls aren't afraid of a burst of color — in fact, we're pretty sure the city has never met a neon it didn't like. So when it comes to bold statement jewelry… well, suffice to say that Miami just isn't for the sartorially shy, which is why designer Sara Lowery Ng of Noble House Designs has gleaned so much inspiration from the 305. In her latest collection of bold, look-at-me necklaces, she's dedicated her strands to her favorite places across the world… which just happen to include West Palm Beach and the Magic City itself. So, we've gone ahead and rounded up the best bright, shiny, and big necklaces Noble House has to offer (which are plenty), and each is perfect for jazzing up everything from a simple black tank to your favorite dress. And even though some of them are inspired by other cities, their exuberance shows that they're all Miami at heart. Click through to scope 'em out, and consider your spring accessories game officially on point.
Photo: Courtesy of Noble House Designs


text:
When: Tuesday, December 20, 7:00 p.m.
Opponent: @ New Jersey (18-13-1)
UPDATE: Jeff Woywitka participated in the morning skate but John Tortorella isn't sure if he'll be able to play tonight. Otherwise, the lineup will be the same and Henrik Lundqvist will start in net for New York. (11:56 a.m.)
UPDATE: It looks like the Rangers will catch a break as Devils' leading scorer Patrik Elias won't play tonight. Neither will defenseman Henrik Tallinder. Martin Brodeur will start in net for New Jersey. (10:57 a.m.)
EARLIER: The good news for the Rangers is that No. 1 defenseman Marc
Staal might be cleared for contact by the end of the week. The bad news is that for the foreseeable
future New York will have to go into battle with a woefully thin defense.
Steve Eminger separated his shoulder on Saturday night
against Phoenix and will be out eight-to-10 weeks, joining Staal and Mike Sauer on the shelf with injuries. Making
matters even worse, Jeff Woywitka left Monday's practice with a foot injury and
is questionable for Tuesday's match against New Jersey.
To replace their wounded the Rangers recalled physical
blueliner Stu Bickel, a late-blooming 25-year-old that leads the CT Whale in
penalty minutes, and top prospect Tim Erixon, who will play Tuesday in the
event that Woywitka cannot.
If it sounds like the Rangers are about to dress a group of
no-names, it should. Of the seven defenders
that could possibly skate against the Devils, only two – Dan Girardi and Ryan
McDonagh – were assured of top-six spots entering training camp.
Michael Del Zotto won a job out of camp and has had a
tremendous season. He'll be counted on
like never before in the coming weeks.
The members of the hodgepodge group of Erixon, Bickel,
Woywitka and Anton Stralman, though, will have to prove that they're not in
over their head.
Girardi, McDonagh and Del Zotto could all approach nearly 30
minutes of ice-time against the Devils, but how Tortorella chooses to deploy
the rest of his rearguard remains to be seen.
Stralman has become a key player after sitting out for weeks
and has played over 20 minutes in each of his last two games. He figures to be a critical piece for the
Rangers going forward after failing to earn a contract from the Devils out of
Woywitka has remained in the lineup despite playing just a
handful of minutes per game, but Tortorella has been adamant about bringing
Erixon along slowly even though he proved earlier this season that he can
handle NHL competition. The organization
would be thrilled to keep Erixon in the press box tomorrow if at all possible.
That leaves Bickel, an afterthought entering the season that
impressed the coaching staff with his snarl.
Bickel was snatched from Anaheim in a deal for forgotten prospect Nigel
Williams, but there had been next to no buzz about him entering the fall or
since camp broke. However, with four
straight rivalry games ahead Bickel could become a very visible player on the
The shabby state of the defense can't be helped, but the
Rangers now need their offense more than ever.
The team had been rolling on the power play and had several
periods with multi-goal outbursts in recent weeks, but has slowed over the last
3-3-1 stretch.
New York has gotten by without much from Brandon Dubinsky and Brian Boyle, but the spotlight on those players is growing brighter by the
day as the team searches for a boost.
This isn't an ideal time to be running into the Devils,
either. New Jersey has won four straight
and six of seven and has generated 26 goals during that stretch. Zach Parise has caught fire after a slow
start to the season and center Travis Zajac returned to the Devils' lineup last
New Jersey, which many had left for dead, now trails the
Rangers by just three points, making Tuesday's tilt in New Jersey a critical
here for our full 2011-2012 Season Archive >
Follow us on Twitter (@NYRBlueBulletin and @kevinbaumer) and on Facebook.


text:
Beloved (Les bien-aimes)
Drama, Romance
In the '60s, Madeleine leaves Paris to re-join her Czech husband Jaromil in Prague, but his infidelities and the arrival of Russian tanks in the city lead her back to France. Thirty years later we follow the romance of Madeleine's daughter, Vera, who falls in love with a musician in London who is incapable of devoting himself to her. Meanwhile in Paris, a re-married Madeleine has rekindled her love affair with Jaromil.
Cast: Catherine Deneuve, Ludivine Sagnier, Christophe Honoré
Produced by:
Directed by: Christophe Honoré
Written by:
Running time: 2hr 25min
Opens: Aug 17, 2012 NY
|Theaters for Today
Pick a day
on this day.


text:
Guys, looking for some advice.
I have the need for attaching 3/16" and 1/4" diameter sst rod in a grid pattern. Looking for a fast and reliable means to do this. With my limited knowledge of welding, it seems like if I could rig up the tips of a spot welder to have good contact on these rounds, and I could get good force to these tips, I could spot weld these joints.
Any thoughts or am I way off base with this idea?
Results 1 to 7 of 7
Thread: Woodworker needs some help
09-28-2012, 06:16 PM #1Junior Member
- Join Date
- Sep 2012
- Posts
- 2
Woodworker needs some help
Don't know what size spot welder you have but you may be under powered....BobBob Wright, Grandson of Tee Nee Boat Trailer Founder
Metal Master Fab Salem, Oh 44460
Birthplace of the Silver & Deming Drill
1999 MM185 w/185 Spoolgun,1986 Thunderbolt AC/DC
Spool Gun conversion. How To Do It. Below.
09-29-2012, 12:51 PM #3Junior Member
- Join Date
- Sep 2012
- Posts
- 2
Thanks Bob for the reply, but I don't have a spot welder yet. I'm just trying to get input on if a spot welder could do the job, what size I need and if two steel rods at 90 degrees have enough contact area for a spot welder to work....?
09-29-2012, 01:03 PM #4Senior Member
- Join Date
- Sep 2005
- Location
- WY...armpit of U.S.A.
- Posts
- 659
Your typical spot welder, even the 220v variety, isn't going to give you the penetration necessary for your job. About the best you could hope for would be a bond similar to that a tube of JB Weld.
I believe that if you click on the link below you'll see that the maximum capacity of a Miller 220v spot welder is 3/16". That is 3/16" TOTAL thickness for both parts added together.
If you wish to go cheap...stick welder, easy...MIG welder and precision (but far from inexpensive)...TIG welder.
http://www.millerwelds.com/products/spotwelders/Miller 251...sold the spoolgun to DiverBill.
Miller DialArc 250
Lincoln PrecisionTig 275
Hypertherm 900 plasma cutter
Bridgeport "J" head mill...tooled up
Jet 14 X 40 lathe...ditto
South Bend 9" lathe...yeah, got the change gears too
Logan 7" shaper
Ellis 3000 band saw
Hossfeld bender w/shopbuilt hyd.
Victor Journeyman torch and gauges
3 Gerstner boxes of mostly Starrett tools
Lots of dust bunnies
Too small of a shop at 40 X 59.
10-09-2012, 03:35 PM #5Senior Member
- Join Date
- Dec 2007
- Location
- Posts
- 378
Did a real quick and dirty test with my Miller LMSW-52 on 1/4" diam stainless rod.
Pieces are about 3" long.
Tried to get good close up photos but the depth of field suffers the closer I got.
Anyway, one spot weld like this is easy. Took about 1 second.
Drawback is that you get burn marks on the outside surfaces.
I was sloppy so it may be better with practice.
Trade-off is that a cleaner looking short dwell time spot weld may not be as strong as a longer one.
My LMSW-52 has 12" tongs which reduces the amperage at the tips but I had more than enough power.
If I had held the switch down longer, I would have melted both rods.
Stainless has higher electrical resistance than carbon steel so this may make a slight difference.
I think the hardest part may to align your pieces and to hold them securely between the spot welder tips.
May require machining a special set so they won't slip.
Anyway, hope this helps.
http://www.millerwelds.com/products/...__air-cooled_/Thermal Arc GTSW400, Airco Heliwelder II, Miller Dynasty 350, Hypertherm 1000, oxy-fuel setup, metal cutting bandsaw, air compressor, drill press, etc.:
Call me the "Clouseau" of welding !
maybe you can find something that will work for you
http://www.twpinc.com/wire-mesh/TWPCAT_5Ed Conley
Passport Plus w/Spool Gun
Miller 125c Plasma 120v
O/A set
SO 2020 Bender
You can call me Bacchus
10-09-2012, 08:43 PM #7Junior Member
- Join Date
- Sep 2011
- Posts
- 12


text:
|Publication number
|Publication type
|Application number
|Publication date
|Feb 9, 2012
|Priority date
|Dec 23, 1994
|Also published as
|Publication number
|Todd A. Merritt, Troy A. Manning
|Original Assignee
|Round Rock Research, Llc
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (12), Referenced by (2), Classifications (26), Legal Events (1)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a divisional of U.S. patent application Ser. No. 12/642,414 which was filed on Dec. 18, 2009, which is a divisional of U.S. patent application Ser. No. 12/144,446, which was filed on Jun. 23, 2008, which is a divisional of U.S. patent application Ser. No. 11/419,166, which was filed on May 18, 2006, which issued as U.S. Pat. No. 7,397,711, which is a divisional of U.S. patent application Ser. No. 10/946,772, filed Sep. 22, 2004, which issued as U.S. Pat. No. 7,088,625, which is a divisional of U.S. patent application Ser. No. 10/232,978, which was filed on Aug. 29, 2002, which issued as U.S. Pat. No. 7,075,857, which is a divisional of U.S. patent application Ser. No. 09/361,795, which was filed on Jul. 27, 1999, which issued as U.S. Pat. No. 6,525,971, which is a continuation of U.S. patent application Ser. No. 09/031,325, which was filed on Feb. 26, 1998, which issued as U.S. Pat. No. 6,381,180, which is a divisional of U.S. patent application Ser. No. 08/785,867, which was filed on Jan. 21, 1997, which issued as U.S. Pat. No. 5,757,703, which is a continuation of U.S. patent application Ser. No. 08/497,354, which was filed on Jun. 30, 1995, which issued as U.S. Pat. No. 5,598,376, which is a continuation-in-part of U.S. patent application Ser. No. 08/386,894, which was filed on Feb. 10, 1995, which issued as U.S. Pat No. 5,610,864, which is a continuation-in-part of U.S. patent application Ser. No. 08/370,761, which was filed on Dec. 23, 1994, which issued as U.S. Pat. No. 5,526,320, all of which are incorporated herein by reference.
This invention relates to memory device architectures designed to provide high density data storage with high speed read and write access cycles. This is invention relates more specifically to circuits and methods for controlling memory write cycles.
There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers.
Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM) for example has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.
It is desirable to design and manufacture a memory device having a standard DRAM pinout and a burst mode of operation where multiple data values can be sequentially written to or read from the device in response to a single address location and multiple access strobes. It is also desirable that this new memory device operate at higher frequencies than standard DRAMs.
There is a problem in performing write cycles at high frequencies. In standard Fast Page Mode and EDO mode DRAM devices, write cycles are performed in response to both /CAS and /WE being low after /RAS is low. If an address change occurs at approximately the same time that /CAS falls, then an additional delay is required to equilibrate input/output lines and to fire a new column prior to beginning the write cycle. Data to be written is latched, and the write cycle begins when the latter of /CAS and /WE goes low provided that the equilibrate is complete. Generally, the write time can be considered to be the period of time that /WE and /CAS are simultaneously low. However, in order to allow for maximum page mode operating frequencies, the write cycle is often timed out so that it can continue for a short period of time after /CAS or /WE goes high especially for "late write" cycles. Maintaining the write cycle throughout the time-out period eases the timing specifications for /CAS and /WE that the device user must meet, and reduces susceptibility to glitches on the control lines during a write cycle. The write cycle is terminated after the time out period, and if /WE is high a read access begins based on the address present on the address input lines. The read access will typically begin prior to the next /CAS falling edge so that the column address to data valid specification can be met (tAA). In order to begin the read cycle as soon as possible, it is desirable to minimize the write cycle time while guaranteeing completion of the write cycle. Minimizing the write cycle duration in turn minimizes the margin to some device operating parameters despite the speed at which the device is actually used. Circuits to model the time required to complete the write cycle typically provide an estimate of the time required to write an average memory cell. While it is desirable to minimize the write cycle time, it is also necessary to guarantee that enough time is allowed for the write to complete, so extra delay is added making the write cycle slightly longer than required.
Another aspect of controlling the write cycle timing includes delaying the write enable or write enables to guarantee that the write data drivers are not enabled prior to the completion of the equilibrate function. Equalization of internal data I/O lines is performed in response to column address transitions in preparation for reading or writing data from another memory cell, and also in response to receipt of a write command to reduce the maximum signal transition on the data lines once the write drivers are enabled. If the data lines are each equalized to one half of Vcc for example, then the write data drivers will only need to drive one line from half Vcc to ground, and the other from half Vcc to Vcc. Otherwise, if the write data is not equal to the data previously on the I/O lines, the write data drivers will need to drive both true and compliment I/O lines a full Vcc swing for each data bit being written. Equalization of the data I/O lines reduces the maximum write cycle time by eliminating the worst case signal swing conditions. A simple method of equilibrating the I/O lines is to: disable I/O line drivers; isolate the I/O lines from the digit lines; and couple complimentary I/O lines together. When a true I/O line is coupled to a complimentary I/O line, a logic high will be coupled to a logic low and each line will equalize to a potential approximately half way between a high and a low. It is important to disable the I/O line drivers during equilibration to prevent a true logic driver from being coupled to a complimentary logic driver which will draw excessive current from the logic high source to the logic low source.
Whether /CAS goes low last (early write) or /WE goes low last (late write), the column address will be valid at or before the write command is received. Hence, a delay from receipt of the write command which is greater than the equilibrate time will guarantee that an equilibrate due to a column address change is complete prior to the enabling the write drivers. If an equilibrate of internal data I/O lines is performed in response to receipt of each write command, a simple delay of the write enables will allow for the equilibrate to complete prior to enabling the write drivers. The delay value for the write cycle to write driver enable delay must account for the worst case signal delays from the equilibrate and write driver enable signal sources to the furthest data I/O line equilibrate devices and write data drivers. Since the equilibrate and write driver enable signal sources are located in a main logic area, a considerable signal propagation delay will result from the transmission of these signals across the chip to the furthest I/O line pair. Timing delays due to routing differences in the two signal paths can be very difficult to accurately model and predict. To overcome these difficulties, extra delay is added for timing margin. Unfortunately, this prevents the write drivers from being enabled as soon as the equilibrate function is complete.
Throughout the memory device product lifetime, manufacturing process advances and circuit enhancements often allow for increases in device operating frequencies. The write cycle timing circuits may need to be adjusted to shorten the is minimum write cycle times to match these performance improvements. Adjustments may include shortening the equilibrate time, shortening the write cycle to write driver enable time and shortening the write cycle hold time. Fine tuning of these timing circuits is time consuming and costly. If the write cycles are too short, the device may fail under some or all operating conditions. If the write cycles are too long, the device may not be able to achieve the higher operating frequencies that are more profitable for the device manufacturers. Finally, if the equilibrate is not complete prior to enabling the write drivers, then excessive current may flow through the write drivers from Vcc to ground.
With the increased operating frequencies of burst access memory devices a new method of generating the write cycle timing is desired which will allow for maximum write cycle times despite the operating frequency of the device.
The features of the invention as well as objects and advantages are best understood by reference to the appended claims, detailed description of particular embodiments and accompanying drawings where:
In a burst read cycle, data within the memory array located at the row and column address selected by the row and column address decoders is read out of the memory array and sent along data path 32 to output latches 34. Data 10 driven from the burst EDO DRAM may be latched external to the device in synchronization with /CAS after a predetermined number of /CAS cycle delays (latency). For a two cycle is latency design, the first /CAS falling edge is used to latch the initial address for the burst access. The first burst data from the memory is driven from the memory after the second /CAS falling edge, and remains valid through the third /CAS falling edge. Once the memory device begins to output data in a burst read cycle, the output drivers 34 continue to drive the data lines without tri-stating the data outputs during /CAS high intervals dependent on the state of the output enable and write enable (/OE and /WE) control lines, thus allowing additional time for the system to latch the output data. Once a row and a column address are selected, additional transitions of the /CAS signal are used to advance the column address within the column address counter in a predetermined sequence. The time at which data becomes valid at the outputs of the burst EDO DRAM is dependent only on the timing of the /CAS signal provided that /OE is maintained low, and /WE remains high. The output data signal levels may be driven in accordance with, but are not limited to, CMOS, TTL, LVTTL, GTL, or HSTL output level specifications.
The address may be advanced linearly, or in an interleaved fashion for maximum compatibility with the overall system requirements. The column address may be advanced with each /CAS transition, each pulse, or multiple of /CAS pulses in the event that more than one data word is read from the array with each column address. When the address is advanced with each transition of the /CAS signal, data is also driven from the part after each transition following the device latency which is then referenced to each edge of the /CAS signal. This allows for a burst access cycle where the highest switching control line (/CAS) toggles only once (high to low or low to high) for each memory cycle. This is in contrast to standard DRAMs which require /CAS to go low and then high for each cycle, and synchronous DRAMs which require a full clock cycle (high and low transitions) for each memory cycle. For maximum compatibility with existing EDO DRAM devices, the invention will be further described in reference to a device designed to initiate access cycles on falling edges of the /CAS signal. For designs where falling edges of the /CAS signal initiate an access cycle, the falling edge may be said to be the active transition of the /CAS signal.
It may be desirable to latch and increment the column address after the first /CAS falling edge in order to apply both the latched and incremented addresses to the array at the earliest opportunity in an access cycle. For example, a device may be designed to access two data words per cycle (prefetch architecture). The memory array for a prefetch architecture device may be split into odd and even array halves. The column address least significant bit is used to select between odd and even halves while the other column address bits select a column within each of the array halves. In an interleaved access mode with column address 1, data from columns 0 and 1 are read and the data from column 1 is output followed by the data from column 0 in accordance with standard interleaved addressing as described in SDRAM specifications. In a linear access mode column address 1 is applied to the odd array half, and incremented to address 2 for accessing the even array half to fulfill the two word access. One method of implementing this type of device architecture is to provide a column address incrementing circuit between the column address counter and the even array half. The incrementing circuit increments the column address only if the initial column address in a burst access cycle is odd, and the address mode is linear. Otherwise the incrementing circuit passes the column address unaltered. For a design using a prefetch of two data accesses per cycle, the column address is advanced once for every two active edges of the /CAS signal. In a write cycle, multiple data words may be temporarily stored as they are input to the device. The actual write of data to the memory cells occurs after the last input data is latched, and may extend slightly into the next memory cycle as long as it ends prior to the next column being activated. Prefetch architectures where more than two data words are accessed are also possible.
Other memory architectures applicable to the current invention include a pipelined architecture where memory accesses are performed sequentially, but each access requires more than a single cycle to complete. In a pipelined architecture the overall throughput of the memory approaches one access per cycle, but the data out of the memory is offset by a number of cycles equal to the pipeline length and/or the desired latency from /CAS.
In the burst access memory device, each new column address from the column address counter is decoded and is used to access additional data within the memory array without the requirement of additional column addresses being specified on the address inputs 16. This burst sequence of data continues for each /CAS falling edge until a predetermined number of data accesses equal to the burst length occurs. A /CAS falling edge received after the last burst address has been generated latches another column address from the address inputs 16 and a new burst sequence begins. Read data is latched and output with each falling edge of /CAS after the first /CAS latency.
For a burst write cycle, data 10 is latched in input data latches 34. Data targeted at the first address specified by the row and column addresses is latched with the /CAS signal when the first column address is latched (write cycle data latency is zero). Other write cycle data latency values are possible; however, for today's memory systems, zero is preferred. Additional input data words for storage at incremented column address locations are latched by /CAS on successive /CAS active transitions. Input data from the input latches 34 is passed along data path 32 to the memory array where it is stored at the location selected by the row and column address decoders. As in the burst read cycle previously described, a predetermined number of burst access writes are performed without the requirement of additional column addresses being provided on the address lines 16. After the predetermined number of burst writes occur, a subsequent /CAS pulse latches a new beginning column address, and another burst read or write access begins.
The memory device of
The write enable signal is used in burst access cycles to select read or write burst accesses when the initial column address for a burst cycle is latched by /CAS. /WE low at the column address latch time selects a burst write access. /WE high at the column address latch time selects a burst read access. The level of the /WE signal must remain high for read and low for write burst accesses throughout the burst access. A low to high transition within a burst write access terminates the is burst access, preventing further writes from occurring. A high to low transition on /WE within a burst read access likewise terminates the burst read access and places the data output 10 in a high impedance state. Transitions of the /WE signal may be locked out during critical timing periods within an access cycle in order to reduce the possibility of triggering a false write cycle, and/or to guarantee the completion of a write cycle once it has begun. After the critical timing period the state of /WE determines whether a burst access continues, is initiated, or is terminated. Termination of a burst access places the DRAM in a state to receive another burst access command. Both /RAS and /CAS going high during a burst access also terminates the burst access cycle placing the data drivers in a high impedance output state. Read data may remain valid at the device outputs if /RAS alone goes high while /CAS is active for compatibility with hidden refresh cycles, otherwise /RAS high alone may be used to terminate a burst access. A minimum write enable pulse width is only required when it is desired to terminate a burst read and then begin another burst read, or terminate a burst write prior to performing another burst write with a minimum delay between burst accesses. In the case of burst reads, /WE transitions from high to low to terminate a first burst read, and then /WE transitions back high prior to the next falling edge of /CAS in order to specify a new burst read cycle. For burst writes, /WE transitions high to terminate a current burst write access, then back low prior to the next falling edge of /CAS to initiate another burst write access. A minimum /WE pulse width may be specified to guarantee recognition of the /WE pulse despite /WE lockout periods. If no /WE lockout circuit is used, termination of a burst access may be edge sensitive to the /WE signal.
A basic implementation of the device of
Programmability of the burst length, /CAS latency and address sequences may be accomplished through the use of a mode register 40 which latches the state of one or more of the address input signals 16 or data signals 10 upon receipt of a write-/CAS-before-/RAS (WCBR) programming cycle. In such a device, outputs 44 from the mode register control the required circuits on the DRAM. Burst length options of 2, 4, 8 and full page as well as /CAS latencies of 1, 2 and 3 may be provided. Other burst length and latency options may be provided as the operating speeds of the device increase, and computer architectures evolve. The device of
A preferred embodiment of a sixteen bit wide burst EDO mode DRAM designed in accordance with the teachings of this invention has two column address strobe input pins /CASH and /CASL. For read cycles only one /CAS signal needs to toggle. The second /CAS may remain high or toggle with the other /CAS. During burst read cycles, all sixteen data bits will be driven out of part during a read cycle even if one /CAS remains inactive. In a typical system application, a microprocessor reads all data bits on a data bus in each read cycle, but may only write certain bytes of data in a write cycle. Allowing one of the /CAS control signals to remain static during read cycles helps to reduce overall power consumption and noise within the system. For burst write access cycles, each of the /CAS signals (CASH and /CASL) acts as a write enable for an eight bit width of the data. The two /CAS's are combined in an AND function to provide a single internal /CAS which will go low when the first external /CAS falls, and returns high after the last external /CAS goes high. All sixteen data inputs are latched when the first of the /CAS signals transitions low. If only one /CAS signal transitions low, then the eight bits of data associated with the /CAS that remained high are not stored in the memory.
The present invention has been described with reference to several preferred embodiments. Just as fast page mode DRAMs and EDO DRAMs are available in numerous configurations including x1, x4, x8 and x16 data widths, and 1 Megabit, 4 Megabit, 16 Megabit and 64 Megabit densities; the memory device of the present invention may take the form of many different memory organizations. It is believed that one who is skilled in the art of integrated circuit memory design can, with the aide of this specification design a variety of memory devices which do not depart from the spirit of this invention. It is therefore believed that detailed descriptions of the various memory device organizations applicable to this invention are not necessary.
It should be noted that the pinout for this new burst EDO memory device may be identical to the pinout for a standard EDO DRAM. The common pinout allows this new device to be used in existing memory designs with minimum design changes. The common pinout also allows for ease of new designs by those of skill in the art who are familiar with the standard EDO DRAM pinout. Variations of the described invention which maintain the standard EDO DRAM pinout include driving the /CAS pin with a system clock signal to synchronize data access of the memory device with the system clock. For this embodiment, it may be desirable to use the first /CAS active edge after /RAS falls to latch the row address, a later edge may be used to latch the first column address of a burst access cycle. After row and column addresses are latched within the device, the address may be incremented internally to provide burst access cycles in synchronization with the system clock. Other pin function alternatives include driving the burst address incrementing signal on the /OE pin since the part does not require a data output disable function on this pin. Other alternate uses of the /OE pin also allow the device to maintain the standard EDO pinout, but provide increased functionality such as burst mode access. The /OE pin may be used to signal the presence of a valid column starting address, or to terminate a burst access. Each of these embodiments provides for a high speed burst access memory device which may be used in current memory systems with a minimum amount of redesign.
It should be noted from
Array regions 54 are broken into 16 subarray regions 64 each of which has an associated data sense amplifier 66 located along one edge of the array. Write enable signal 68 and I/O line equilibrate signal 70 are routed to each data sense amplifier.
Read data follows the same path from the memory cell to the global sense amp where it is then driven on complimentary data read lines 122 to complimentary data lines 126 under control of data path control logic 124 and timing circuits 59. Complimentary data 126 is driven to an I/O pad 100 through output circuit 128.
This specific embodiment is not intended to provide an exhaustive is description of all forms of the, present invention. For example, I/O line multiplexer 104 would not be necessary if there is a global sense amp 67 for each pair of array I/O lines. Alternatively, additional array I/O lines could be multiplexed through the multiplexer 104 to allow for even fewer global sense amplifiers. Another variation is to allow read and write data to share a common path between the global sense amplifiers and the I/O pad. Also, separate input and output data pins can be provided. Numerous additional variations are possible and will be recognized by one of skill in the art.
Address inputs 170 are coupled to an address counter 172 and/or column address latch 174 which provide a burst column address 175 to the memory array. The column address and a version of the write command 176 are used to generate an equilibrate signal 182 in the address transition detection circuit 180. For burst accesses, the address transition circuit may generate the equilibrate signal synchronously with an access cycle strobe signal rather than waiting for an actual address transition to be detected, especially if the address is advanced on rising /CAS edges in preparation for the next active falling edge. Equilibration control signal 182 passes through distributed resistance 184, and is loaded by distributed capacitance 186. A delayed version of the equilibrate signal 188 is coupled to the sense amp 66.
The time delay of the write and equilibrate signals 164 and 188 at sense amp 66 will be dependent on which sense amp is being driven, as the distributed resistance and capacitances will vary for each sense amp location. Write command 164 and equilibrate signal 188 are combined at the global sense amp 66 in circuit 200. In circuit 200, the write command is gated with a decoded row address signal 204 in circuits 202 and 208. Gated write command 210 is then combined with the equilibrate signal in logic gate 212 to form a write driver enable signal 214. Equilibrate signal 188 provides an active low enable signal to data I/O line equilibration device 232. When the equilibrate signal on line 188 is low, device 232 couples the two data I/O lines 106 together to equalize their potentials. A low on line 188 also disable logic device 212 preventing the write driver enable 214 from going active. When the equilibrate control signal 188 transitions high, the equilibration device 232 is deactivated, and the write driver enable gate 212 is enabled. For write cycles it is beneficial to provide the write command on line 164 before the equilibrate signal 188 goes high, then as soon as the equilibrate signal 188 goes high, the write command will be passed through gate 212 placing the write enable signal 214 in an active low condition without the requirement for an equilibration to write enable delay. Signal 214 is inverted in inverter 216 to provide an active high write enable 218. The active low write enable goes to two NOR gates 242 and 246. Active high write enable 218 is coupled to NAND gates 240 and 244. The NOR and NAND gates pass write data to the I/O lines through devices 250-256 when enabled by the write driver enable signals 214 and 218. For writing a logic "one" for example, the write data on line 103 may be high. A high on signal 103 in combination with a high write driver enable on signal line 218 will provide a low output from NAND gate 240 which will turn on device 250 to drive a logic one on the true I/O line. the high signal on data line 103 will disable NOR gate 242 to eliminate a current path to ground while NAND 250 is turned on. Data line 103 is inverted at inverter 258 to provide compliment data 260. When data line 103 is high, complimentary data line 260 will be low which will enable NOR gate 246 and disable NAND gate 244. Enabled NOR gate 246 combined with the active write driver enable signal 214 will provide a high output from NOR 246 to turn on device 256 and drive the complimentary I/O line low. For a maximized data write cycle time, the write command 164 can remain active throughout a burst write access. In this case, the write drivers are enabled and disabled by the equilibrate signal which will occur at the beginning of each access cycle. Multiple write command signals 158 may be utilized in devices with multiple /CAS or multiple /WE inputs to control writes to one of multiple data bytes for example. The decoded row address input prevents the write drivers from driving data on I/O lines in nonselected sections of the array. Multiplexer 104 of
It is important to note that devices 250 and 256 will generally be enabled simultaneously, as will devices 252 and 254. If the enable gate 212 were not locally present, then the write enable signal would need to be delayed from the equilibrate disable time to guarantee that a current path through devices 250, 232 and 256 or devices 252 , 232 and 254 does not exist.
At the end of a burst write access, the write enable may be deactivated in response to /RAS high and /CAS high, /RAS high alone, or after a time-out period following /CAS high. As stated above, the write command may be held active throughout a burst write access. Alternatively, it may be cleared at the beginning of each access cycle, and then relatched provided that /WE is low on the following /CAS high to low transition. If cleared, the period of time that the write command is inactivated within a burst write access is preferably shorter than the equilibrate time so that the write cycle can be maximized which in turn allows for a minimum cycle time. When a read command is detected (/WE high at /CAS falling), a current burst write access will be terminated and a burst read access will begin. It may be desirable to gate the equilibrate signal with the read command and the write control signal to ensure that the equilibrate signal does not end prior to the write control signal becoming invalid. This would be done to prevent the write drivers from becoming enabled for a fraction of the first read cycle in a burst read access sequence.
By gating the write command and equilibrate signals at the sense amplifiers, numerous advantages are obtained over the simple write command delay. One advantage is a maximized write time since the write cycle can begin as soon as the equilibrate is complete for all device types, and can last until the next cycle begins in burst access devices. A second advantage is elimination of write driver enable delay circuitry which can have a variable delay dependent on the operating conditions of the memory device (supply voltage, temperature, etc.). Each driver will be fired when the equilibrate signal is locally deactivated, eliminating the possibility of crossing current through complimentary write drivers while complimentary data lines are coupled together for equilibration.
A memory device may be designed with multiple /CAS inputs as described above. For a memory device with two /CAS inputs where each /CAS controls eight bits of a sixteen bit wide data port, a write cycle where only one /CAS is low must not write all data bits from the data input to the memory. A portion of the write data path associated with an inactive /CAS may be interrupted in a number of ways. Each of the two /CAS signals may enable half of the column address decoders such that no column will be selected in half of the memory associated with a high /CAS in a write cycle. In this case the write data drivers can be enabled, but the data I/O lines associated with a disabled column decoder will not be coupled to any memory cells. Alternately, the write control signals may be gated with the appropriate /CAS signal to prevent some of the write data drivers from being enabled. In this case, read data may be coupled from some memory cells to data I/O lines.
In a burst write operation, the processor 112 provides an initial address and a write command to the memory controller. The memory controller provides a row address to the memory with a row address strobe. The memory controller then provides a write command, a column address and a column address strobe to the memory. The memory will equilibrate internal data I/O lines in response to receipt of the write command and column address. During the equilibrate operation, write data and write command signals are passed to global sense amplifiers within the burst access memory device. At the end of the equilibrate operation, write data drivers are enabled, and write data is stored in the memory array. In a preferred embodiment, positive (low to high) transitions of /CAS will cause an internal address counter of the memory device to advance to the next burst address. Negative (high to low) transitions of /CAS will then end the previous write cycle and equilibrate the I/O lines. The negative transition of /CAS will also allow the burst address from the counter to be applied to the array. Once the equilibration is complete, the next write will be performed at the burst address from the counter. In an alternate embodiment, a clock signal is input to a burst access device to control generation of a burst address from the counter (SDRAMs for example have a clock input pin).
In another embodiment, memory 124 operates in a page mode such as Fast Page Mode or EDO mode. Write commands at memory sense amps are enabled by the equilibrate signal becoming inactive at the sense amp. Using the equilibrate signal at the sense amp to gate the write signal to enable the write drivers eliminates wasted time associated with delaying the write driver enable signal to prevent excessive currents from flowing through the write drivers during the equilibration operation.
For the purposes of this specification a node may be, but is not limited to, an intersection of conductors, a circuit input or output, or any point along a signal path. For example, the write command may be said to enter the global sense amp at node 164 and device 250 of
An integrated circuit memory device with a standard DRAM pinout is designed for high speed data access and for compatibility with existing memory systems. A high speed burst mode of operation is provided where multiple sequential accesses occur following a single column address, and read data is output relative to the /CAS control signal. In the burst mode of operation the address is incremented internal to the device eliminating the need for external address lines to switch at high frequencies. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at high speeds. Only one control line per memory chip (/CAS) must toggle at the operating frequency in order to clock the internal address counter and the data input/output latches. The load on each /CAS is typically less than the load on the other control signals (/RAS, /WE and /OE) since each /CAS typically controls only a byte width of the data bus.
A new write cycle timing method and circuit allow for maximized write cycle timing at all operating frequencies to provide maximum write cycle timing margins. Write control is maintained throughout a write cycle such that the write operation time approaches the write cycle time. The write function is only halted between write cycles for a period of time required to select a new column of the array and to equilibrate I/O lines in the array. To maximize write cycle times, a logic device is located near the sense amplifiers of the device to control the write function directly with the use of the I/O line equilibrate signal. It is important to disable the write drivers during the equilibrate time to prevent current flow through the true and compliment data drivers while the I/O lines are coupled together. The local write enable circuit allows the write cycle time to be essentially equal to the access cycle time minus the I/O line equilibrate time in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next cycle.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
|Cited Patent
|Filing date
|Publication date
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|Jan 28, 1997
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
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|Mar 17, 1998
|Micron Technology, Inc.
|Address transition detection on a synchronous design
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|May 26, 1998
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Apr 24, 1998
|Jan 9, 2001
|Micron Technology, Inc.
|Synchronous dynamic random access memory device
|Aug 22, 1997
|Nov 6, 2001
|Micron Technology Inc
|256 Meg dynamic random access memory
|Feb 26, 1998
|Apr 30, 2002
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Jul 27, 1999
|Feb 25, 2003
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Aug 29, 2002
|Apr 27, 2004
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Aug 29, 2002
|Jul 5, 2005
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Aug 29, 2002
|Jul 11, 2006
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Sep 22, 2004
|Aug 8, 2006
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|May 18, 2006
|Jul 8, 2008
|Micron Technology, Inc.
|Distributed write data drivers for burst access memories
|Citing Patent
|Filing date
|Publication date
|Apr 9, 2012
|Oct 2, 2012
|Round Rock Research, Llc
|Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
|Apr 9, 2012
|Aug 2, 2012
|Round Rock Research, Llc
|Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Feb 6, 2012
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:027676/0168
Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK
Effective date: 20091230


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text:
Unfortunately, the weather report for 36 hours is very poor. In Albany, 40 miles north, the clouds are closing in now (2:00 pm) and the chance of rain through Sunday morning is very high.
Unfortunately, the weather report for 36 hours is very poor. In Albany, 40 miles north, the clouds are closing in now (2:00 pm) and the chance of rain through Sunday morning is very high.
Ditto here in Vermont. I was going to go to a function at the NY, CT border but the weather looks "damp"
I guess we gonna have to wear the wetsuit.
Im new to this whole BMW thing but aint it called adventure riding?
2006 Honda Big Ruckus
Heading up in my 'Stich on Sunday!.
70 degrees and beautiful!
I really don't mind riding in the rain. But, living on Long Island and driving in traffic during a rain storm is an adventure of it's own kind. Just not fun!
For those of you who didn't come up today you missed just about perfect weather.
Partly to mostly sunny highs around 70. Forecast for tomorrow looks good.
The weather looked bad...but was great even on top of the mountian, never got rained on 68 and peeks of sun.
J C Hughes
"When you play, play hard, when you work don't play at all".
Colonel Theodore Roosevelt
i hit one drop on Saturday at around 11am in Kingston but never saw any more rain the whole time, thank you weather gods for taking care of us this weekend.
2006 Honda Big Ruckus
You need to ignore the weather forecast, The weather men are wrong more than thay are right. I left Ct on Friday afternoon, arrived by 8:30 PM and the only rain we had was Friday night until Saturday about 6:00 AM . We had clouds and threats of rain but it was a wonderful weekend.
Glad to see all my good friends.
Craig Cleasby
South Windsor, CT
Yankee Beemers
I had it with this wacky and unpredictable weather. I was in rain or shine.
My bike and I stayed dry Friday night, flipped a coin on Sat and luckily heads (head west) won, so I stayed dry, and only hit a few sprinkles southbound on Rt 10 Sun morning. A great weekend.
My Smugmug
850 miles for the weekend not one mile in the rain. Rained Fri night from about 10pm-6am. Great ride Sat.


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ST. MARYS – St. Marys City Police report arresting 44-year-old Michael J. Stephanic following the death of 48-year-old June Talmadge, also known as June Andrus.
Stephanic, of St. Marys, has reportedly been arraigned on charges of criminal homicide and aggravated assault, and has been remanded to the Elk County Prison.
The incident reportedly took place early Tuesday morning at 2:40 a.m. at Eastern Sintered Alloys at 126 Access Rd.
The investigation is continuing.
[1] mailto:firstname.lastname@example.com
[2] http://www.kanerepublican.com/sites/default/files/breaking news_0.png


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Radio and television host Joe Franklin died Saturday of prostate cancer,
It's safe to say that Birdman is officially the frontrunner to win Best Picture at the Oscars next...
Blake Shelton pulled double duty on
With the 10-megawatt Dover Sun Park and the 15-megawatt Milford Solar Park, Kent County produces 27.7 megawatts of solar energy, according to the Delaware Department of Natural Resources and Environmental Control.
Markell's 50-minute State of the Stat speech was mostly a look back at accomplishments over the past six years.
A plan to make Dover a safer place for those who like to get around the city by biking or walking cleared another hurdle Tuesday night.
Karen Gill worked her window treatments business – Royal Treatments – out of her home until the opportunity to open a storefront rent-free for three months became available through the Delaware Economic Development...
Early-morning walkers head to the Dover Mall between 7 a.m. and 9:30 a.m. Mondays through Saturdays.
- Events Calendar


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what is on your mine?
what is on your mine?
what is on your mine?
I'm sorry I forgot your at that age where you can't do that anymore. I'm talking about sex.Originally posted by dolfan06
ROFLMAO! That's Naaaasssshhhhhhhtttttyyyyyyyy!!!!!!
does sex have anything to do with mines? I've heard of explosive, but that's ridiculous.
all of his dates with momma thumb and her 4 daughters, kinda gives a person a one track mind!
...or someone elses shaft?
***Unleash the Killer DOLPHINS***
really not making comments on these threads!


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From Intelligent Design to BioLogos
In this paper, Venema tells the story of his transition from support of Intelligent Design to the view that God uses evolution as a creative mechanism.
The Resource Finder has powerful filtering features — check out the tutorial to learn more.
In this paper, Venema tells the story of his transition from support of Intelligent Design to the view that God uses evolution as a creative mechanism.
In this essay, Hastings looks at "front edge" areas for promoting healthy dialogue in the field of science and Christian theology, areas which are specifically theological in nature.
This article is a comprehensive study of the views of Christian author and apologist C. S. Lewis on the theory of evolution and the argument from intelligent design. It explains how he would distinguish expressly philosophical arguments for a Transcendent Mind from the current claims of the intelligent design (ID) movement to provide scientific evidence for such a reality.
In this paper, adapted from an article from Science & Christian Belief, Dr. Oliver R. Barclay compares and contrasts the biblical view of design in nature with modern design arguments.
In this paper, Venema explores several examples in biology where random mutation and natural selection have indeed led to substantial increases in biological information. The question of how new specified information arises in DNA, far from being an "enigma", is one of great interest to biologists.
Hastings provides a biblical and theological basis for healthy and fruitful dialogue on the theology and science of origins.
Mathematics professor James Bradley looks at the design argument presented in William Dembski's book The Design Inference and offers his criticisms on the accuracy of the model.
In this article, Venema offers his review of Stephen Meyer's book Signature in the Cell.
Can science provide substantive insight into the question of God's existence? Isaac's paper examines three schools of thought regarding the possibility of detecting God's existence through science: Evolutionism, Creationism, and Intelligent Design.
In this paper, Baylor philosophy professor Francis Beckwith distinguishes between Intelligent Design (ID) and Thomistic Design (TD).
Falk's paper asks evangelical Christians to explore whether they are propping up a bubble that they, not God, have created, thereby isolating themselves from the world of academics. The essay describes five layers that may play a role in unnecessarily blocking entry, or reentry, of agnostic scientists into the realm of evangelicalism.
Mark Noll, historian and author of The Scandal of the Evangelical Mind, enumerates 15 attitudes, assumptions, and convictions he considers to be most influential in inciting anti-intellectual sentiment among evangelical Christians.


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PESTO AUTENTICO is an Italian eatery and bar concept from Carnival Establishment. At Pesto Autentico, the focus is about great, elaborate and yet simple dining experience.
Our interior takes its cue from the historical Bowery area in New York City. Our dark nostalgic colorful style is a reflection of an old industrial era mixed with modern touches.
Master Chef Mikko and Executive Chef Danny collaborated in creating an extensive Italian fare. Come for our varieties of pasta, Neapolitan pizza and main courses. We are the purveyor of great Italian cuisine.
Una Festa Magnifica – A magnificent feast is waiting for you at PESTO AUTENTICO.


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New Desktop
I decided to try a new window manager [1], just because I hadn't wasted enough time on just fiddling with Conky [2]. I'm not really into a tiling window managers, even though I have plenty of display space (2 1920×1080 monitors). I had been reading in the Arch forums about GOOMWWM [3] (Get Out Of My Way Window Manager) and looking at the goomwwm web page for it[4] made me think that despite its newness, it looked relatively complete, especially with Xinerama [5] support for my dual monitor setup. So I decided to give it a try.
Trying a new window manager isn't really that big a deal, especially if you are like me and are
lazy hardcore enough to not bother to install a login manager like SLiM and just log in to a text terminal and type startx to bring up X. You just change the window manager that gets exec'd at the end of your .xinitc script to be the one you want. So I changed
exec ck-launch-session dbus-launch openbox-session
to be
exec ck-launch-session dbus-launch `which goomwwm`
and off I went! To be honest, I'm not really sure (a) what the "ck-launch-session dbus-launch" part of the command does or (b) if I really need it (as I just copied it from the openbox Arch wiki page), but I left it in there for safety's sake.
But with nothing set up, it merely brings you to a blank, black screen. And, as I didn't have 'dmenu' [6] installed (it should be, I think, at least an optional dependency, as it is prominently featured in the GOOMWWM tutorial [7]), I couldn't really do anything!
So I went back to the command line and installed dmenu and followed the tutorial, and lo, it was good. Window control is a little more painful with the mouse as you have to hold down the Mod key (left Windows key by default) but is a snap with the keyboard, so that's okay. The concept of tags for windows that correspond to desktops in other window managers again takes some getting used to but works very well in practice. It's especially nice to be able to bring up a window on another "desktop" by merely clicking on it.
So then I spent way too much time getting things somewhat customized. I still like blue for a desktop color, so I went over to The Paper Wall to find a few interesting wallpapers and settled on a blue forest [8] as my left desktop and a nice waterfront view of Boston [9] as my right desktop.
Then I went a Conky customizing, which is an endless time sink if there ever was one. Luckily, I discovered this great Conky customizing script called 'conky-colors' [10]. Basically, you pass in a few (or more!) parameters and it creates a stock Conky config file with support scripts and everything. I eventually settled on this for a conky-colors command line:
$ conky-colors –cputemp –theme=human –arch –cpu=4 –proc=5 –clementine=vinyl –calendar –nvidia –hd=default –weather=USMA0245 –photord –network –unit=F –clock=modern –side=left
And then I modified away, mostly to just get the right colors (more blue!). That's the panel on the left side of the right hand screen. It shows system info, a calendar and clock, a random picture from a folder, what my media player (Clementine) is currently playing, and some more system stats.
The I finally found a script that generated a good Conky weather forecast pane in conkywx[11]. There were a few bumps in the road, but I got them ironed out with the help of the author in the Arch forums and now I have a nice weather panel in the lower right.
So now I just need to get used to goomwwm. I like being able to quickly and easily use the keyboard to move and resize the windows, and even fill the blank space. It can behave a little like a tiling window manager, with commands for windows to swap position, share a position, etc, which I haven't played with much.
It also has a unique idea about "desktops". You can tag any window with a number between 1 and 9 and then hit Alt-F[1-9] to bring all those windows with that tag number to the front. The others are still there but just behind. So it is easy to assign windows to different tags and swap between them, but you can also use very easily use windows with other tags by just clicking on them. And goomwwm tells other tools (like Conky) that the tag selected is the "desktop". Works pretty well.
[1] http://xwinman.org/intro.php
[2] http://conky.sourceforge.net/
[3] https://bbs.archlinux.org/viewtopic.php?id=144038
[4] http://aerosuidae.net/goomwwm/
[5] http://en.wikipedia.org/wiki/Xinerama
[6] http://www.archlinux.org/packages/community/x86_64/dmenu/
[7] http://aerosuidae.net/goomwwm/tutorial
[8] http://thepaperwall.com/wallpaper.php?view=5cddb00435b4ffd1a4d7a08d351723dcee9a3f7d&fol=nature
[9] http://thepaperwall.com/wallpaper.php?view=3b66596749f5d2b44356207bc05a9be32eaa9219&fol=cityscape
[10] https://github.com/helmuthdu/conky_colors
[11] https://bitbucket.org/plikhari/conkywx_pub/overview
My October screenshots. Click to embiggen.


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Men's Shoes: Training
Looking for shoes that will help you train for faster? You're in the right place. PUMA has the cross training shoes you've been looking for – and they have the perfect blend of style and performance.
The Pulse XT is a lightweight training shoe that's fast, flexible, and infused with a bold, dynamic design. So easy to toss in your gym bag. The Carson Runner, in a number of different upper designs, offers another lightweight option that works just as well as a weekend kick-around sneaker. Or there's the Cell Surin, with a durable upper and extra cushioning at the heel.
Our men's training shoes will help you take your workout to the next level. (And you'll look darn good in the process.)


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A DESTINATION WHERE ANYTHING IS POSSIBLEIntroducing Chicago's permier event spaceWhatever the event, The Venue offers you no end of ways to create just the right setting. Our experienced staff can plan and coordinate everything from beginning to end. Every detail is handles with ease. Food, flowers, linens, and entertainment. We do it all. The state-of-the-art kitchen facilities and catering team will provide an unforgettable dining experience. And the space itsself is designed to accommodate the widest variety of occasions possible. In short, The Venue is the hottest event destination in Chicago.
The Venue at Horseshoe Casino
777 Casino Center Drive
Hammond, IN 46320
219-473-5930 Phone
219-473-6025 Fax


text: Front as worn Back Back, with pocket in use Front, straight-on interior compartment interior compartment, with accessories (not included) interior compartment, with camera and accessories (not included) shown with Canon high-zoom camera (not included) Shown with Fujifilm high-zoom camera (not included) shown with Sony NEX-Series camera (not included) View larger Lowepro Adventura Ultra Zoom 100 Shoulder bag for high-zoom and hybrid interchangeable-lens cameras Item #: 766LP36214 2 Reviews This item is no longer available. Original Price: $17.99 Shop all Camera Bags Need help? 1.888.955.6000 Email Chat Ask an expert advisor No pressure, no commission — just lots of good advice from our highly trained staff. Overview Reviews Details Articles & Videos by Woody Sherman The Adventura Ultra Zoom 100 camera bag is the perfect on-the-go companion for your high-zoom or "hybrid" interchangeable lens camera. With its low-profile front cutaway, one quick zip and the camera will be in your hands, ready for action. The soft interior lining protects your LCD display, and convenient interior pockets house your extra memory cards and batteries. The shoulder strap is both adjustable and removable, and the back of the case features a slash pocket suitable for maps or guidebooks. Product Highlights:built for high-zoom and "hybrid" interchangeable lens camerascompact, easy-access designpadded, removable divider adjusts to fit many cameras with accessoriesfront cutaway rides low, allowing quick retrieval of camera for fast reaction to shot opportunitiesbrushed tricot interior lining protects LCD display from scratchesdedicated interior pockets for batteries and memory cardsadjustable/removable shoulder strapquick-grab carrying handleinternal dimensions: 3-3/4"W x 5-5/16"H x 3-5/16"Dweight: 4.8 oz.warranty: limited lifetimeOur 60-day money-back guarantee Lowepro Adventura Ultra Zoom 100 Reviews Average Customer Review: 2 reviews Review this product Submit a review and then enter to win a $350 rewards card Filter by rating: 5 Star: (0) 4 Star: (0) 3 Star: (0) 2 Star: (0) 1 Star: (0) Review this product: Thanks for taking the time to share your experiences about this product. Please be sure to focus your comments on the product itself. Read our Review Guidelines for more information. Review title * Email Your email won't be visible. Please use the email address that is associated with your order. Display name (e.g., JohnD) Your review will be signed using the display name and location * Your location (e.g., Charlottesville, VA) * Your rating Click on a star to rate the overall product on a scale of 1-5 1500 characters left * Your review Attach a YouTube Review Crutchfield Video Review Guidelines Only submit videos that you made or are authorized to use. Do not submit videos that contain music, video or visuals that are copyrighted and belong to someone else. Please see our Review Guidelines for more information. Enter the URL of your YouTube™ video review or product demonstration. e.g., "http://www.youtube.com/v/o79TWHh598U" 500 characters left Pros 500 characters left Cons * Agree to Terms By checking this box you agree your review becomes the property of Crutchfield, that you are over 18 years of age, that you own or have owned this product, and that you are located within the United States or its territories. Please see our Review Guidelines for more information. We reserve the right (but are not obligated to) review all submissions and edit or remove any review in any manner which we deem necessary. Your review should be posted within seven days. Nice case for my nikon Written By videoluvr, calif on Wednesday, March 05, 2014 Crutchfield Customer Review (What's this?) Nice case for my camera Pros: plenty of room and inside is the same color as my camera. Also room for my charger,memory cards and batteries Cons: none Was this review helpful? Yes No Gets the job done! Written By Rich, Philly on Friday, June 01, 2012 Crutchfield Customer Review (What's this?) Great fit for the Canon G1X. Nice looking and compact bag. Adjustable divider is nice, but I have it pretty much all the way expanded to fit the protruding lens, so there's not really any extra room for the charger. An extra battery would squeeze into the internal side pocket, and there are slots for 2 extra SD cards. Besides the back pocket for a small map or guide there are no external pockets but I'm fine with that. I am pretty lean with my accessories as it is and prefer the smaller bag. Pros: Size, accessibility, style, good fit for a G1X or ultra zoom. Cons: No room to safely stash a charger 4 out of 4 people found this helpful Was this review helpful? Yes No Hands-on research What's in the box? | In-depth notes What's in the box? Black camera bag for ultra-zoom cameras Adjustable shoulder strap Product Research Features Overview: The Lowepro Adventura Ultra Zoom 100 is designed for ultra-zoom cameras, and compact Micro Four Thirds cameras. Construction: Materials: Black nylon exterior; Orange tricot interior Pockets: For 2 memory cards, 4 AA batteries, personal items Divider: padded, removable (1) Portability: Quick-grab handle, adjustable/removable shoulder strap Closure: Dual zippers Internal Dimensions: The case has the following internal dimensions: Width: 3.7" Height: 5.3" Depth: 3.3" Our Product Research Team At Crutchfield, you'll get detailed, accurate information that's hard to find elsewhere. That's because we have our own in-house Product Research team. They verify what's in the box, check the owner's manual, and record dimensions, features and specs. We stay on top of new products and technologies to help people make informed choices. Sorry, the Lowepro Adventura Ultra Zoom 100 is no longer available. Looking for a similar item? Shop all Camera Bags Or, you can still... Write a review Search the website Go


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i need help
This advice has been deemed a little to racy for the RomanceClass site. It has been moved to FlirtingClass, our sister site. If you are under age 16, please ask for and receive parental permission before visiting FlirtingClass.
Read i need help Advice at FlirtingClass.com
-- from George
One of Your Friendly Advisors at RomanceClass.com


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Church Stacking Chair, Set of 2
by Gus Modern
At A Glance:
A versatile stacking chair that can be used pretty much anywhere for anything, the Church Chair is a charming, simple blend of plywood and powder-coated metal. Frame is available in a slate or white powder coat. Wood finish is available in oak or walnut veneer. Sold as a set of 2.
What's To Like:
- A stacking chair with gorgeous wood veneer, that looks like it's intended as a permanent fixture of the dining room? Sounds like a winner.
- Equally at home in a modern space as it is in a more eclectic home, the Church Chair is adaptable to your decor, whatever the style.
- Powder-coated steel frame will stand up to all the abuse you'll be (unintentionally) subjecting this chair to.
What's Not to Like:
For some, the metal frame's juxtaposition of angular and curved lines may be a stylistic miss. For others, that same mixture may be a hit. You know what they say about the eye of the beholder.
The Bottom Line:
The Church Chair is just the kind of stacking chair we like to see. Modern, simple, quality materials, easy storage ... Gus Modern has designed a great utilitarian chair.
- Overall dimensions: 31" h x 19" w x 20" d
- Seat height: 18"
- Plywood construction that reveals the many layers used to construct seat and back
- Available in natural oak and walnut veneers
- Frame available in white or slate powder-coated finish
- Plastic bumpers on legs to prevent floor damage
- Stackable design
Also In This Collection
Materials & MeasurementsMaterials:
Overall: 31" h x 19" w x 20" d
Seat height: 18"
Weight: approx. 14lb (each)
Your FurnitureGenius Recommendations
Environmental InformationThe Church Chair contains FSC-Certified Wood harvested from a sustainably harvested forest.
About The ManufacturerWith a focus on simple forms and honest materials, Gus Design Group's vision is to bring comfortable sofas, modern tables, and striking accent pieces to modern interiors everywhere. Their sofas, lounge chairs, and ottomans are an excellent choice for anyone with a fondness for mid-century design, from which Gus Modern draws much of its inspiration. Gus Modern is based in Toronto, Canada.
Related Categories
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Shipping & Delivery
The Gus Modern Church Chair ships Free for destinations within the contiguous United States.
Gus Modern products generally arrive within 4-8 days from the date of purchase.
For additional information, please see our shipping and delivery policies page.


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It was, in that well-worn sporting cliché, a season of two halves: that is, if you call one half Sebastian and the other half Vettel.
In a 19-race season (shortened by one when the political unrest in the Middle East led to the cancellation of Bahrain's Grand Prix), the 24-year-old German won 11 times and became the youngest driver ever to claim back-to-back World Championship titles.
Unlike his first title, stolen by a short head with a late dash to the line, the second was won in a canter. Mounted on another thoroughbred from the seemingly inexhaustible stable of Red Bull Racing design wizard Adrian Newey, Vettel made all the early running – five victories in the first seven races – and added five more in another withering six-race burst between Belgium and India in the second half of the season to seal victory. He was World Champion with four races remaining.
Vettel was poised if not to break, then at least to equal, Michael Schumacher's all-time record of 13 wins in a single season, but a rare failure to finish in Abu Dhabi – a tyre blew as he led the field away on the first lap – and a gearbox gremlin that saw him finish 'only' second in the last round in Brazil meant he had to content himself with another outright record instead.
That was for the number of pole positions claimed in a single F1 season, which stood at 14, a mark set by Nigel Mansell in his all-conquering year with Williams Renault back in 1992. Pole position for the Brazilian race was Vettel's 15th of the year.
That apart, it was another year of outright domination by F1's 'Big Five': Vettel and his Red Bull teammate Mark Webber, McLaren Mercedes duo Lewis Hamilton and Jenson Button, and Ferrari flag-bearer Fernando Alonso.
Among them they claimed all 19 race victories, all 19 poles and all but two fastest laps – the usurper there was Felipe Massa in the sister Ferrari with two of his own in an otherwise forgettable season for the Brazilian, the first Maranello driver to fail to score a podium since Ivan Capelli, also way back in `92.
Speaking of podiums, the Big Five almost monopolised those as well. Of the 57 podium places on offer, just two went to other men: Vitaly Petrov, third for Renault in Melbourne's season-opening race, and Nick Heidfeld, also for Renault, at the very next race in Malaysia. Renault, though, went backwards, and now they have turned to the returning former World Champion Kimi Raikkonen for 2012 in a bid to restore fortunes severely dented by the loss of Robert Kubica to long-term injury.
Behind Vettel the unwanted 'best-of-the-rest' accolade must go to Button. At 31 the 2009 World Champion finds himself in a mature, well-ordered and confident place – so much so that he became the first teammate ever to beat Lewis Hamilton. Both men scored three race wins, but Button's consistency earned him second place overall and a prolonged contract at McLaren.
For Australian fans the good news is that Mark Webber finally won a 2011 race at the final round in Brazil – the first time the popular Aussie had won more than once at any World Championship venue.
Arguably, too, it was Webber who provided the most memorable moments of the year, mainly, it seemed, in his duels with Alonso – two men at the height of their powers with unfailing trust in each other to do the right thing. Who could forget Webber's steely resolve as he passed the Ferrari flat-out through the awe-inspiring Eau Rouge corner at Spa-Francorchamps? Seven fastest race laps also suggest Webber still has the pace to go with a commitment that burns as fiercely as ever as he enters his 11th season at the pinnacle of world motor sport.


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Swarovski boutique
11-19 Great George Street Fashion Walk Causeway Bay
Hong Kong
Telephone: +852 2972 2198
Opening hours:
Monday to Sunday
10:00 - 22:00
Hong Kong: where East meets West
The metropolis of Hong Kong is constantly in motion. Here, in the Land of Smiles, the borders between East and West become blurred. And when the city lights turn on at night, traditional culture is buried like treasure amidst the magnificent buildings that reach up to the sky. But in the Fashion Walk Swarovski Boutique, it is easy to find real jewels, where elegant crystal collections capture light and transform it into a myriad of colors. The thousand reflections in the brilliant Crystal Forest design also make borders disappear without a trace.


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- 2
- people in the U.S. have this name View Melanie Hoffmeister on Whitepages
Meaning & Origins
From an Old French form of Latin Melania, a derivative of the feminine form, melaina, of the Greek adjective melas 'black, dark'. This was the name of two Roman saints of the 5th century, a grandmother and granddaughter. St Melania the Younger was a member of a rich patrician family. She led an austere and devout Christian life and, on inheriting her father's wealth, she emancipated her slaves, sold her property, and gave the proceeds to the poor. She also established several contemplative houses, including one on the Mount of Olives, to which she eventually retired. The name Melanie was introduced to England from France in the Middle Ages, but died out again. It was reintroduced and became popular in the late 20th century.
|275th in the U.S.
German: variant spelling of Hofmeister.
|16,871st in the U.S.
Nicknames & variations
Melani, Melany, Melania, Melanee, Melaney, Melana, Melane, Melaine, Melanio, Melannie
Hoffman, Hoff, Hoffmann, Hoffer, Hoffner, Hoffpauir, Hoffert, Hoffmeyer, Hoffmaster, Hoffart


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To get started, call us today at (516) 570-4010Forbes Music has talented piano teachers near you in these locations and others: Glen Cove, Locust Valley, Lattingtown, Matinecock, Mill Neck, Sea Cliff
Forbes Music sets the highest standard for music education, whether at home in private lessons, in the classroom, or on the stage in our student rock and jazz bands.
Study with one of our accomplished piano teachers today. Forbes Music teachers are graduates of prestigious institutions and have earned outstanding recognition for their accomplishments both in the classroom and on stage.