text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 30, 2006
|Filing date
|Sep 21, 2005
|Priority date
|Aug 31, 1999
|Also published as
|Publication number
|William Wheeler, Bradley Burres, Matthew Adiletta, Gilbert Wolrich
|Original Assignee
|Intel Corporation, A Delaware Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Referenced by (5), Classifications (7), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of, and claims priority to, U.S. patent application Ser. No. 09/387,109 filed on Aug. 31, 1999, entitled "SDRAM CONTROLLER FOR PARALLEL PROCESSOR ARCHITECTURE," the contents of which are hereby incorporated by reference.
This invention relates to memory controllers particularly for use in parallel processing systems.
Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs in a computer, in contrast to sequential processing. In the context of a parallel processor, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed sequentially at a single station or a pipelined machine where tasks are performed at specialized stations, with parallel processing, a plurality of stations are provided with each capable of performing all tasks. That is, in general all or a plurality of the stations work simultaneously and independently on the same or common elements of a problem. Certain problems are suitable for solution by applying parallel processing.
Memory systems used in parallel processing tasks can be inefficient.
According to an aspect of the present invention, a memory controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The memory controller also includes a first read/write queue that holds memory reference from a computer bus and a second read/write queue that holds memory references from a core processor. The memory controller also includes control logic including an arbiter that detects the fullness of each of the queues and a status of outstanding memory reference to select a memory reference from one of the queues.
According to an additional aspect of the invention, the controller has control logic that is responsive to a chaining bit that when set allows for special handling of contiguous memory references. The chaining bit controls the arbiter to have the arbiter select the functional unit which previously requested a bus. Assertion of the chaining bit will control the arbiter when the optimized memory bit is also set to maintain the memory references from a current queue.
One or more of the following advantages may be provided by one or more aspects of the invention.
The controller uses memory reference sorting when an optimized memory bit is set. The memory reference sorting is based on bank accesses that allows hiding of pre-charges from one bank to another bank. Specifically, if a memory system is organized into an odd bank and an even bank, while the memory controller is operating on the odd bank, the memory controller can start precharging the even bank. Precharging is possible if memory references alternate between odd and even banks.
Additionally, other optimizations can be used. For example, merging optimizations where operations that can be merged, are merged prior to memory access, open page optimizations where by examining addresses an opened page of memory is not reopened, chaining, and refreshing mechanisms, can be employed.
Another feature of the controller is that when a memory reference is stored in the queues, in addition to the optimized memory bit that can be set, the controller also uses a "chaining bit". The chaining bit when set allows for special handling of contiguous memory references. Assertion of the chaining bit will control the arbiter to have the arbiter select the functional unit which previously requested a memory bus.
Referring to
The hardware-based multithreaded processor 12 also includes a central controller 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, extra support for packet processing where the microengines pass the packets off for more detailed processing such as in boundary conditions. In one embodiment, the processor 20 is a Strong Arm� (Arm is a trademark of ARM Limited, United Kingdom) based architecture. The general purpose microprocessor 20 has an operating system. Through the operating system the processor 20 can call functions to operate on microengines 22 a-22 f. The processor 20 can use any supported operating system preferably a real time operating system. For the core processor implemented as a Strong Arm architecture, operating systems such as, MicrosoftNT real-time, VXWorks and μCUS, a freeware operating system available over the Internet, can be used.
The hardware-based multithreaded processor 12 also includes a plurality of function microengines 22 a-22 f. Functional microengines (microengines) 22 a-22 f each maintain a plurality of program counters in hardware and states associated with the program counters. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22 a-22 f while only one is actually operating at any one time.
In one embodiment, there are six microengines 22 a-22 f as shown. Each microengines 22 a-22 f has capabilities for processing four hardware threads. The six microengines 22 a-22 f operate with shared resources including memory system 16 and bus interfaces 24 and 28. The memory system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26 a and a Static Random Access Memory (SRAM) controller 26 b. SDRAM memory 16 a and SDRAM controller 26 a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. The SRAM controller 26 b and SRAM memory 16 b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
The six microengines 22 a-22 f access either the SDRAM 16 a or SRAM 16 b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from SDRAM. The microengines 22 a-22 f can execute memory reference instructions to either the SDRAM controller 26 a or SRAM controller 16 b.
Advantages of hardware multithreading can be explained by SRAM or SDRAM memory accesses. As an example, an SRAM access requested by a Thread_0, from a microengine will cause the SRAM controller 26 b to initiate an access to the SRAM memory 16 b. The SRAM controller controls arbitration for the SRAM bus, accesses the SRAM 16 b, fetches the data from the SRAM 16 b, and returns data to a requesting microengine 22 a-22 b. During an SRAM access, if the microengine e.g., 22 a had only a single thread that could operate, that microengine would be dormant until data was returned from the SRAM. By employing hardware context swapping within each of the microengines 22 a-22 f, the hardware context swapping enables other contexts with unique program counters to execute in that same microengine. Thus, another thread e.g., Thread_1 can function while the first thread, e.g., Thread_0, is awaiting the read data to return. During execution, Thread_1 may access the SDRAM memory 16 a. While Thread_1 operates on the SDRAM unit, and Thread_0 is operating on the SRAM unit, a new thread, e.g., Thread_2 can now operate in the microengine 22 a. Thread_2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the processor 12 can have a bus operation, SRAM operation and SDRAM operation all being completed or operated upon by one microengine 22 a and have one more thread available to process more work in the data path.
The hardware context swapping also synchronizes completion of tasks. For example, two threads could hit the same shared resource e.g., SRAM. Each one of these separate functional units, e.g., the FBUS interface 28, the SRAM controller 26 a, and the SDRAM controller 26 b, when they complete a requested task from one of the microengine thread contexts reports back a flag signaling completion of an operation. When the flag is received by the microengine, the microengine can determine which thread to turn on.
One example of an application for the hardware-based multithreaded processor 12 is as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a media access controller device e.g., a 10/100BaseT Octal MAC 13 a or a Gigabit Ethernet device 13 b. In general, as a network processor, the hardware-based multithreaded processor 12 can interface to any type of communication device or interface that receives/sends large amounts of data. Communication system 10 functioning in a networking application could receive a plurality of network packets from the devices 13 a, 13 b and process those packets in a parallel manner. With the hardware-based multithreaded processor 12, each network packet can be independently processed.
Another example for use of processor 12 is a print engine for a postscript processor or as a processor for a storage subsystem, i.e., RAID disk storage. A further use is as a matching engine. In the securities industry for example, the advent of electronic trading requires the use of electronic matching engines to match orders between buyers and sellers. These and other parallel types of tasks can be accomplished on the system 10.
The processor 12 includes a bus interface 28 that couples the processor to the second bus 18. Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO bus). The FBUS interface 28 is responsible for controlling and interfacing the processor 12 to the FBUS 18. The FBUS 18 is a 64-bit wide FIFO bus, used to interface to Media Access Controller (MAC) devices.
The processor 12 includes a second interface e.g., a PCI bus interface 24 that couples other system components that reside on the PCI 14 bus to the processor 12. The PCI bus interface 24, provides a high speed data path 24 a to memory 16 e.g., the SDRAM memory 16 a. Through that path data can be moved quickly from the SDRAM 16 a through the PCI bus 14, via direct memory access (DMA) transfers. The hardware based multithreaded processor 12 supports image transfers. The hardware based multithreaded processor 12 can employ a plurality of DMA channels so if one target of a DMA transfer is busy, another one of the DMA channels can take over the PCI bus to deliver information to another target to maintain high processor 12 efficiency. Additionally, the PCI bus interface 24 supports target and master operations. Target operations are operations where slave devices on bus 14 access SDRAMs through reads and writes that are serviced as a slave to target operation. In master operations, the processor core 20 sends data directly to or receives data directly from the PCI interface 24.
Each of the functional units are coupled to one or more internal buses. As described below, the internal buses are dual, 32 bit buses (i.e., one bus for read and one for write). The hardware-based multithreaded processor 12 also is constructed such that the sum of the bandwidths of the internal buses in the processor 12 exceed the bandwidth of external buses coupled to the processor 12. The processor 12 includes an internal core processor bus 32, e.g., an ASB bus (Advanced System Bus) that couples the processor core 20 to the memory controller 26 a, 26 c and to an ASB translator 30 described below. The ASB bus is a subset of the so called AMBA bus that is used with the Strong Arm processor core. The processor 12 also includes a private bus 34 that couples the microengine units to SRAM controller 26 b, ASB translator 30 and FBUS interface 28. A memory bus 38 couples the memory controller 26 a, 26 b to the bus interfaces 24 and 28 and memory system 16 including flashrom 16 c used for boot operations and so forth.
Referring to
If the memory subsystem 16 is flooded with memory requests that are independent in nature, the processor 12 can perform memory reference sorting. Memory reference sorting improves achievable memory bandwidth. Memory reference sorting, as described below, reduces dead time or a bubble that occurs with accesses to SRAM. With memory references to SRAM, switching current direction on signal lines between reads and writes produces a bubble or a dead time waiting for current to settle on conductors coupling the SRAM 16 b to the SRAM controller 26 b.
That is, the drivers that drive current on the bus need to settle out prior to changing states. Thus, repetitive cycles of a read followed by a write can degrade peak bandwidth. Memory reference sorting allows the processor 12 to organize references to memory such that long strings of reads can be followed by long strings of writes. This can be used to minimize dead time in the pipeline to effectively achieve closer to maximum available bandwidth. Reference sorting helps maintain parallel hardware context threads. On the SDRAM, reference sorting allows hiding of pre-charges from one bank to another bank. Specifically, if the memory system 16 b is organized into an odd bank and an even bank, while the processor is operating on the odd bank, the memory controller can start precharging the even bank. Precharging is possible if memory references alternate between odd and even banks. By ordering memory references to alternate accesses to opposite banks, the processor 12 improves SDRAM bandwidth. Additionally, other optimizations can be used. For example, merging optimizations where operations that can be merged, are merged prior to memory access, open page optimizations where by examining addresses an opened page of memory is not reopened, chaining, as will be described below, and refreshing mechanisms, can be employed.
The FBUS interface 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted. The FBUS interface 28 also includes a controller 28 a that performs header processing of incoming packets from the FBUS 18. The controller 28 a extracts the packet headers and performs a microprogrammable source/destination/protocol hashed lookup (used for address smoothing) in SRAM. If the hash does not successfully resolve, the packet header is sent to the processor core 20 for additional processing. The FBUS interface 28 supports the following internal data transactions:
FBUS unit (Shared bus SRAM) to/from microengine. FBUS unit (via private bus) writes from SDRAM Unit. FBUS unit (via Mbus) Reads to SDRAM.
The FBUS 18 is a standard industry bus and includes a data bus, e.g., 64 bits wide and sideband control for address and read/write control. The FBUS interface 28 provides the ability to input large amounts of data using a series of input and output FIFO's 29 a-29 b. From the FIFOs 29 a-29 b, the microengines 22 a-22 f fetch data from or command the SDRAM controller 26 a to move data from a receive FIFO in which data has come from a device on bus 18, into the FBUS interface 28. The data can be sent through memory controller 26 a to SDRAM memory 16 a, via a direct memory access. Similarly, the microengines can move data from the SDRAM 26 a to interface 28, out to FBUS 18, via the FBUS interface 28.
Data functions are distributed amongst the microengines. Connectivity to the SRAM 26 a, SDRAM 26 b and FBUS 28 is via command requests. A command request can be a memory request or a FBUS request. For example, a command request can move data from a register located in a microengine 22 a to a shared resource, e.g., an SDRAM location, SRAM location, flash memory or some MAC address. The commands are sent out to each of the functional units and the shared resources. However, the shared resources do not need to maintain local buffering of the data. Rather, the shared resources access distributed data located inside of the microengines. This enables microengines 22 a-22 f, to have local access to data rather than arbitrating for access on a bus and risk contention for the bus. With this feature, there is a 0 cycle stall for waiting for data internal to the microengines 22 a-22 f.
The data buses, e.g., ASB bus 30, SRAM bus 34 and SDRAM bus 38 coupling these shared resources, e.g., memory controllers 26 a and 26 b are of sufficient bandwidth such that there are no internal bottlenecks. Thus, in order to avoid bottlenecks, the processor 12 has an bandwidth requirement where each of the functional units is provided with at least twice the maximum bandwidth of the internal buses. As an example, the SDRAM can run a 64 bit wide bus at 83 MHz. The SRAM data bus could have separate read and write buses, e.g., could be a read bus of 32 bits wide running at 166 MHz and a write bus of 32 bits wide at 166 MHz. That is, in essence, 64 bits running at 166 MHz which is effectively twice the bandwidth of the SDRAM.
The core processor 20 also can access the shared resources. The core processor 20 has a direct communication to the SDRAM controller 26 a to the bus interface 24 and to SRAM controller 26 b via bus 32. However, to access the microengines 22 a-22 f and transfer registers located at any of the microengines 22 a-22 f, the core processor 20 access the microengines 22 a-22 f via the ASB Translator 30 over bus 34. The ASB translator 30 can physically reside in the FBUS interface 28, but logically is distinct. The ASB Translator 30 performs an address translation between FBUS microengine transfer register locations and core processor addresses (i.e., ASB bus) so that the core processor 20 can access registers belonging to the microengines 22 a-22 c.
Although microengines 22 can use the register set to exchange data as described below, a scratchpad memory 27 is also provided to permit microengines to write data out to the memory for other microengines to read. The scratchpad 27 is coupled to bus 34.
The processor core 20 includes a RISC core 50 implemented in a five stage pipeline performing a single cycle shift of one operand or two operands in a single cycle, provides multiplication support and 32 bit barrel shift support. This RISC core 50 is a standard Strong Arm� architecture but it is implemented with a five stage pipeline for performance reasons. The processor core 20 also includes a 16 kilobyte instruction cache 52, an 8 kilobyte data cache 54 and a prefetch stream buffer 56. The core processor 20 performs arithmetic operations in parallel with memory writes and instruction fetches. The core processor 20 interfaces with other functional units via the ARM defined ASB bus. The ASB bus is a 32-bit bi-directional bus 32.
Referring to
In addition to event signals that are local to an executing thread, the microengines 22 employ signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all microengines 22. Receive Request Available signal, Any and all threads in the microengines can branch on these signaling states. These signaling states can be used to determine availability of a resource or whether a resource is due for servicing.
The context event logic 74 has arbitration for the four (4) threads. In one embodiment, the arbitration is a round robin mechanism. Other techniques could be used including priority queuing or weighted fair queuing. The microengine 22 f also includes an execution box (EBOX) data path 76 that includes an arithmetic logic unit 76 a and general purpose register set 76 b. The arithmetic logic unit 76 a performs arithmetic and logical functions as well as shift functions. The registers set 76 b has a relatively large number of general purpose registers. As will be described in
The microengine 22 f also includes a write transfer register stack 78 and a read transfer stack 80. These registers are also windowed so that they are relatively and absolutely addressable. Write transfer register stack 78 is where write data to a resource is located. Similarly, read register stack 80 is for return data from a shared resource. Subsequent to or concurrent with data arrival, an event signal from the respective shared resource e.g., the SRAM controller 26 a, SDRAM controller 26 b or core processor 20 will be provided to context event arbiter 74 which will then alert the thread that the data is available or has been sent. Both transfer register banks 78 and 80 are connected to the execution box (EBOX) 76 through a data path. In one implementation, the read transfer register has 64 registers and the write transfer register has 64 registers.
As shown in
The SDRAM interface 26 a provides a signal back to the requesting microengine on reads that indicates whether a parity error occurred on the read request. The microengine microcode is responsible for checking the SDRAM read Parity flag when the microengine uses any return data. Upon checking the flag, if it was set, the act of branching on it clears it. The Parity flag is only sent when the SDRAM is enabled for checking, and the SDRAM is parity protected. The microengines and the PCI Unit are the only requesters notified of parity errors. Therefore, if the processor core 20 or FIFO requires parity protection, a microengine assists in the request. The microengines 22 a-22 f support conditional branches. The worst case conditional branch latency (not including jumps) occurs when the branch decision is a result of condition codes being set by the previous microcontrol instruction. The latency is shown below in Table 1:
1 2 3 4 5 6 7 8 microstore lookup n1 cb n2 XX b1 b2 b3 b4 reg addr gen n1 cb XX XX b1 b2 b3 reg file lookup n1 cb XX XX b1 b2 ALU/shifter/cc n1 cb XX XX b1 write back m2 n1 cb XX XX
where nx is pre-branch microword (n1 sets cc's)
cb is conditional branch
bx is post-branch microword
XX is aborted microword
As shown in Table 1, it is not until cycle 4 that the condition codes of n1 are set, and the branch decision can be made (which in this case causes the branch path to be looked up in cycle 5). The microengine incurs a 2-cycle branch latency penalty because it must abort operations n2 and n3 (the 2 microwords directly after the branch) in the pipe, before the branch path begins to fill the pipe with operation b1. If the branch is not taken, no microwords are aborted and execution continues normally. The microengines have several mechanisms to reduce or eliminate the effective branch latency.
The microengines support deferred branches. Deferring branches are when a microengine allows 1 or 2 microwords after the branch to occur before the branch takes effect (i.e. the effect of the branch is "deferred" in time). Thus, if useful work can be found to fill the wasted cycles after the branch microword, then the branch latency can be hidden. A 1-cycle deferred branch is shown below where n2 is allowed to execute after cb, but before b1:
1 2 3 4 5 6 7 8 microstore lookup n1 cb n2 XX b1 b2 b3 b4 reg addr gen n1 cb n2 XX b1 b2 b3 reg file lookup n1 cb n2 XX b1 b2 ALU/shifter/cc n1 cb n2 XX b1 write back n1 cb n2 XX
A 2-cycle deferred branch is shown below, where n2 and n3 are both allowed to complete before the branch to b1 occurs. Note that a 2-cycle branch deferment is only allowed when the condition codes are set on the microword preceding the branch.
1 2 3 4 5 6 7 8 9 microstore lookup n1 cb n2 n3 b1 b2 b3 b4 b5 reg addr gen n1 cb n2 n3 b1 b2 b3 b4 reg file lookup n1 cb n2 n3 b1 b2 b3 ALU/shftr/cc n1 cb n2 n3 b1 b2 write back n1 cb n2 n3 b1
The microengines also support condition code evaluation. If the condition codes upon which a branch decision are made are set 2 or more microwords before the branch, then 1 cycle of branch latency can be eliminated because the branch decision can be made 1 cycle earlier:
1 2 3 4 5 6 7 8 microstore lookup n1 n2 cb XX b1 b2 b3 b4 reg addr gen n1 n2 cb XX b1 b2 b3 reg file lookup n1 n2 cb XX b1 b2 ALU/shifter/cc n1 n2 cb XX b1 write back n1 n2 cb XX
In this example, n1 sets the condition codes and n2 does not set the conditions codes. Therefore, the branch decision can be made at cycle 4 (rather than 5), to eliminate 1 cycle of branch latency. In the example below, the 1-cycle branch deferment and early setting of condition codes are combined to completely hide the branch latency:
Condition codes (cc's) set 2 cycles before a 1-cycle deferred branch:
1 2 3 4 5 6 7 8 microstore lookup n1 n2 cb n3 b1 b2 b3 b4 reg addr gen n1 n2 cb n3 b1 b2 b3 reg file lookup n1 n2 cb n3 b1 b2 ALU/shifter/cc n1 n2 cb n3 b1 write back n1 n2 cb b3
In the case where the condition codes cannot be set early (i.e. they are set in the microword preceding the branch), the microengine supports branch guessing which attempts to reduce the 1 cycle of exposed branch latency that remains. By "guessing" the branch path or the sequential path, the microsequencer pre-fetches the guessed path 1 cycle before it definitely knows what path to execute. If it guessed correctly, 1 cycle of branch latency is eliminated as shown below:
guess branch taken/branch is taken 1 2 3 4 5 6 7 8 microstore lookup n1 cb n1 b1 b2 b3 b4 b5 reg addr gen n1 cb XX b1 b2 b3 b4 reg file lookup n1 cb XX b1 b2 b3 ALU/shifter/cc n1 cb XX b1 b2 write back n1 cb XX b1
If the microcode guessed a branch taken incorrectly, the microengine still only wastes 1 cycle:
guess branch taken/branch is NOT taken 1 2 3 4 5 6 7 8 microstore lookup n1 cb n1 XX n2 n3 n4 n5 reg addr gen n1 cb n1 XX n2 n3 n4 reg file lookup n1 cb n1 XX n2 n3 ALU/shifter/cc n1 cb n1 XX n2 write back n1 cb n1 XX
However, the latency penalty is distributed differently when microcode guesses a branch is not taken:
For guess branch NOT taken/branch is NOT taken there are no wasted cycles as set out below.
1 2 3 4 5 6 7 8 microstore lookup n1 cb n1 XX b1 b2 b3 b4 reg addr gen n1 cb XX XX b1 b2 b3 reg file lookup n1 cb XX XX b1 b2 ALU/shifter/cc n1 cb XX XX b1 write back n1 cb XX XX
However for guess branch NOT taken/branch is taken there are 2 wasted cycles.
1 2 3 4 5 6 7 8 microstore lookup n1 cb n2 b1 b2 b3 b4 b5 reg addr gen n1 cb n2 b1 b2 b3 b4 reg file lookup n1 cb n2 b1 b2 b3 ALU/shifter/cc n1 cb n2 b1 b2 write back n1 cb n2 b1
The microengine can combine branch guessing with 1-cycle branch deferment to improve the result further. For guess branch taken with 1-cycle deferred branch/branch is taken is:
1 2 3 4 5 6 7 8 9 microstore lookup n1 cb n2 XX n3 n4 n5 n6 n7 reg addr gen n1 cb n2 XX n3 n4 n5 n6 reg file lkup n1 cb n2 XX n3 n4 n5 ALU/shftr/cc n1 cb n2 XX n3 n4 write back n1 cb n2 XX n3
In the case above, the 2 cycles of branch latency are hidden by the execution of n2, and by correctly guessing the branch direction. If microcode guesses incorrectly, 1 cycle of branch latency remains exposed as shown below:
guess branch taken with 1-cycle deferred branch/branch is NOT taken
1 2 3 4 5 6 7 8 9 microstore lookup n1 cb n2 XX b1 b2 b3 b4 b5 reg addr gen n1 cb n2 XX b1 b2 b3 b4 reg file lkup n1 cb n2 XX b1 b2 b3 ALU/shftr/cc n1 cb n2 XX b1 b2 write back n1 cb n2 XX b1
If microcode correctly guesses a branch NOT taken, then the pipeline flows sequentially in the normal unperturbed case. If microcode incorrectly guesses branch NOT taken, the microengine again exposes 1 cycle of unproductive execution as shown below:
guess branch NOT taken/branch is taken 1 2 3 4 5 6 7 8 9 microstore lookup n1 jp XX XX XX j1 j2 j3 j4 reg addr gen n1 jp XX XX XX j1 j2 j3 reg file lkup n1 jp XX XX XX j1 j2 ALU/shftr/cc n1 jp XX XX XX j1 write back n1 jp XX XX XX
where nx is pre-branch microword (n1 sets cc's)
cb is conditional branch
bx is post-branch microword
XX is aborted microword
In the case of a jump instruction, 3 extra cycles of latency are incurred because the branch address is not known until the end of the cycle in which the jump is in the ALU stage:
1 2 3 4 5 6 7 8 9 microstore lookup o1 ca br n1 n2 n3 n4 n5 n6 reg addr gen o1 ca XX n1 n2 n3 n4 n5 reg file lkup o1 ca XX n1 n2 n3 n4 ALU/shftr/cc o1 ca XX n1 n2 n3 write back o1 ca XX n1 n2
Context Switch:
Referring to
1 2 3 4 5 6 7 8 9 microstore lookup o1 ca br n1 n2 n3 n4 n5 n6 reg addr gen o1 ca XX n1 n2 n3 n4 n5 reg file lkup o1 ca XX n1 n2 n3 n4 ALU/shftr/cc o1 ca XX n1 n2 n3 write back o1 ca XX n1 n2
where ox is old context flow
br is branch microword in old context
ca is context rearbitration (causes context switch)
nx is new context flow
XX is aborted microword
In a context switch the "br" microword is aborted to avoid control and timing complexities that could be caused by saving the correct old context PC.
Conditional branches that operate on ALU condition codes which are set on the microword before the branch can select 0, 1 or 2-cycle branch deferment modes. Condition codes set 2 or more microwords before the conditional branch that operates on them can select 0 or 1-cycle branch deferment modes. All other branches (including context rearbitrations) can select either 0 or 1-cycle branch deferment modes. The architecture could be designed to make a context arbitration microword within a branch deferment window of a preceding branch, jump or context arbitration microword, an illegal option. That is, in some embodiments, a context switch would not be allowed to occur during a branch transition in the pipeline because as mentioned, it could unduly complicate saving of the old context PC. The architecture could also be designed to make branching within the branch deferment window of a preceding branch, jump or context arbitration microword illegal to avoid complicated and possible unpredictable branch behaviors.
Each microengine 22 a-22 f supports multi-threaded execution of four contexts. One reason for this is to allow one thread to start executing just after another thread issues a memory reference and must wait until that reference completes before doing more work. This behavior is critical to maintaining efficient hardware execution of the microengines because memory latency is significant. Stated differently, if only a single thread execution was supported, the microengines would sit idle for a significant number of cycles waiting for references to return and thereby reduce overall computational throughput. Multi-threaded execution allows an microengines to hide memory latency by performing useful independent work across several threads. Two synchronization mechanisms are supplied in order to allow a thread to issue an SRAM or SDRAM reference, and then subsequently synchronize to the point in time when that reference completes.
One mechanism is Immediate Synchronization. In immediate synchronization, the microengine issues the reference and immediately swap out that context. The context will be signaled when the corresponding reference completes. Once signaled, the context will be swapped back in for execution when a context-swap event occurs and it is its turn to run. Thus, from the point of view of a single context's instruction stream, the microword after issuing the mem reference does not get executed until the reference completes.
A second mechanism is Delayed Synchronization. In delayed synchronization, the microengine issues the reference, and then continues to execute some other useful work independent of the reference. Some time later it could become necessary to synchronize the thread's execution stream to the completion of the issued reference before further work is performed. At this point a synchronizing microword is executed that will either swap out the current thread, and swap it back in sometime later when the reference has completed, or continue executing the current thread because the reference has already completed. Delayed synchronization is implemented using two different signaling schemes:
If the memory reference is associated with a transfer register, the signal from which the thread is triggered is generated when the corresponding transfer register valid bit is set or cleared. For example, an SRAM read which deposits data into transfer register A would be signaled when the valid bit for A is set. If the memory reference is associated with the transfer FIFO or the receive FIFO, instead of a transfer register, then the signal is generated when the reference completes in the SDRAM controller 26 a. Only one signal state per context is held in the microengines scheduler, thus only one outstanding signal can exist in this scheme.
There are at least two general operational paradigms from which microcontroller micro-programs could be designed. One would be that overall microcontroller compute throughput and overall memory bandwidth are optimized at the expense of single thread execution latency. This paradigm would make sense when the system has multiple microengines executing multiple threads per microengine on unrelated data packets.
A second one is that microengine execution latency should be optimized at the expense of overall microengine compute throughput and overall memory bandwidth. This paradigm could involve execution of a thread with a real-time constraint, that is, a constraint which dictates that some work must absolutely be done by some specified time. Such a constraint requires that optimization of the single thread execution be given priority over other considerations such as memory bandwidth or overall computational throughput. A real-time thread would imply a single microengine that executes only one thread. Multiple threads would not be handled because the goal is to allow the single real-time thread to execute as soon as possible—execution of multiple threads would hinder this ability.
The coding style of these two paradigms could be significantly different with regard to issuing memory references and context switching. In the real time case, the goal is to issue as many memory references as soon as possible in order to minimize the memory latency incurred by those references. Having issued as many references as early as possible the goal would be to perform as many computations as the microengines as possible in parallel with the references. A computation flow that corresponds to real-time optimization is:
o) issue mem ref 1
o) issue mem ref 2
o) issue mem ref 3
o) perform work independent of mem refs 1, 2 and 3
o) synch to completion of mem ref 1
o) perform work dependent on mem ref 1 and independent of mem ref 2 and 3
o) issue any new mem refs based on preceding work.
o) synch to completion of mem ref 2
o) perform work dependent on mem ref 1 and 2 independent of mem ref 3
o) issue any new mem refs based on preceding work.
o) synch to completion of mem ref 3
o) perform work dependent on the completion of all 3 refs
o) issue any new mem refs based on preceding work.
In contrast, optimization for throughput and bandwidth would take a different approach. With optimization for microengine computational throughput and overall memory bandwidth less consideration is given to single thread execution latency. To accomplish this, the goal would be to equally space memory references across the microprogram for each thread. This would provide a uniform stream of memory references to the SRAM and SDRAM controllers and would maximize the probability that 1 thread is always available to hide the memory latency incurred when another thread is swapped out.
Register File Address Types:
Referring to
Across banks A and B, the register set 76 b is also organized into four windows 76 b 0-76 b 3 of 32 registers that are relatively addressable per thread. Thus, thread_0 will find its register 0 at 77 a (register 0), the thread_1 will find its register_0 at 77 b (register 32), thread_2 will find its register_0 at 77 c (register 64), and thread_3 at 77 d (register 96). Relative addressing is supported so that multiple threads can use the exact same control store and locations but access different windows of register and perform different functions. The uses of register window addressing and bank addressing provide the requisite read bandwidth using only dual ported RAMS in the microengine 22 f.
These windowed registers do not have to save data from context switch to context switch so that the normal push and pop of a context swap file or stack is eliminated. Context switching here has a 0 cycle overhead for changing from one context to another. Relative register addressing divides the register banks into windows across the address width of the general purpose register set. Relative addressing allows access any of the windows relative to the starting point of the window. Absolute addressing is also supported in this architecture where any one of the absolute registers may be accessed by any of the threads by providing the exact address of the register.
Addressing of general purpose registers 78 can occur in 2 modes depending on the microword format. The two modes are absolute and relative. In absolute mode, addressing of a register address is directly specified in 7-bit source field (a6-a0 or b6-b0):
7 6 5 4 3 2 1 0 A GPR: a6 0 a5 a4 a3 a2 a1 a0 a6 = 0 B GPR: b6 1 b5 b4 b3 b2 b1 b0 b6 = 0 SRAM/ASB: a6 a5 a4 0 a3 a2 a1 a0 a6 = 1, a5 = 0, a4 = 0 SDRAM: a6 a5 a4 0 a3 a2 a1 a0 a6 = 1, a5 = 0, a4 = 1
register address directly specified in 8-bit dest field (d7-d0):
7 6 5 4 3 2 1 0 A GPR: d7 d6 d5 d4 d3 d2 d1 d0 d7 = 0, d6 = 0 B GPR: d7 d6 d5 d4 d3 d2 d1 d0 d7 = 0, d6 = 1 SRAM/ASB: d7 d6 d5 d4 d3 d2 d1 d0 d7 = 1, d6 = 0, d5 = 0 SDRAM: d7 d6 d5 d4 d3 d2 d1 d0 d7 = 1, d6 = 0, d5 = 1
If <a6:a5>=1,1, <b6:b5>=1,1, or <d7:d6>=1,1 then the lower bits are interpreted as a context-relative address field (described below). When a non-relative A or B source address is specified in the A, B absolute field, only the lower half of the SRAM/ASB and SDRAM address spaces can be addressed. Effectively, reading absolute SRAM/SDRAM devices has the effective address space; however, since this restriction does not apply to the dest field, writing the SRAM/SDRAM still uses the full address space.
In relative mode, addresses a specified address is offset within context space as defined by a 5-bit source field (a4-a0 or b4-b0):
7 6 5 4 3 2 1 0 A GPR: a4 0 context a3 a2 a1 a0 a4 = 0 B GPR: b4 1 context b3 b2 b1 b0 b4 = 0 SRAM/ASB: ab4 0 ab3 context b2 b1 ab0 ab4 = 1, ab3 = 0 SDRAM: ab4 0 ab3 context b2 b1 ab0 ab4 = 1, ab3 = 1
or as defined by the 6-bit dest field (d5-d0):
7 6 5 4 3 2 1 0 A GPR: d5 d4 context d3 d2 d1 d0 d5 = 0, d4 = 0 B GPR: d5 d4 context d3 d2 d1 d0 d5 = 0, d4 = 1 SRAM/ASB: d5 d4 d3 context d2 d1 d0 d5 = 1, d4 = 0, d3 = 0 SDRAM: d5 d4 d3 context d2 d1 d0 d5 = 1, d4 = 0, d3 = 1
If <d5:d4>=1,1, then the destination address does not address a valid register, thus, no dest operand is written back.
The following registers are globally accessible from the microengines and the memory controllers:
The microengines are not interrupt driven. Each microflow executes until completion and then a new flow is chosen based on state signaled by other devices in the processor 12.
Referring to
The order queue 90 c maintains the order of reference requests from the microengines. With a series of odd and even banks references it may be required that a signal is returned only upon completion of a sequence of memory references to both the odd and even banks. If the microengine 22 f sorts the memory references into odd bank and even bank references and one of the banks, e.g., the even bank is drained of memory references before the odd bank but the signal is asserted on the last even reference, the memory controller 26 a could conceivably signal back to a microengine that the memory request had completed, even though the odd bank reference had not been serviced. This occurrence could cause a coherency problem. The situation is avoided by providing the order queue 90 c allowing a microengine to have multiple memory references outstanding of which only its last memory reference needs to signal a completion.
The SDRAM controller 26 a also includes a high priority queue 90 d. In the high priority queue 90 d, an incoming memory reference from one of the microengines goes directly to the high priority queue and is operated upon at a higher priority than other memory references in the other queues. All of these queues, the even bank queue 90 a, the odd bank queue 90 b, the order queue 90 c and the high priority queue, are implemented in a single RAM structure that is logically segmented into four different windows, each window having its own head and tail pointer. Since filling and draining operations are only a single input and a single output, they can be placed into the same RAM structure to increase density of RAM structures.
The SDRAM controller 26 a also includes core bus interface logic i.e., ASB bus 92. The ASB bus interface logic 92 interfaces the core processor 20 to the SDRAM controller 26 a. The ASB bus is a bus that includes a 32 bit data path and a 28 bit address path. The data is accessed to and from memory through MEM ASB data device 98, e.g., a buffer. MEM ASB data device 98 is a queue for write data. If there is incoming data from the core processor 20 via ASB interface 92, the data can be stored into the MEM ASB device 98 and subsequently removed from MEM ASB device 98 through the SDRAM interface 110 to SDRAM memory 16 a. Although not shown, the same queue structure can be provided for the reads. The SDRAM controller 26 a also includes an engine 97 to pull data from the microengines and PCI bus.
Additional queues include the PCI address queue 94 and ASB read/write queue 96 that maintain a number of requests. The memory requests are sent to SDRAM interface 110 via multiplexer 106. The multiplexer 106 is controlled by the SDRAM arbiter 91 which detects the fullness of each of the queues and the status of the requests and from that decides priority based on a programmable value stored in a priority service control register 100.
Once control to the multiplexer 106 selects a memory reference request, the memory reference request, is sent to a decoder 108 where it is decoded and an address is generated. The decoded address is sent to the SDRAM interface 110 where it is decomposed into row and column address strobes to access the SDRAM 16 a and write or read data over data lines 16 a sending data to bus 112. In one implementation, bus 112 is actually two separate buses instead of a single bus. The separate buses would include a read bus coupling the distributed microengines 22 a-22 f and a write bus coupling the distributed microengines 22 a-22 f.
A feature of the SDRAM controller 26 a is that when a memory reference is stored in the queues 90, in addition to the optimized MEM bit that can be set, there is a "chaining bit". The chaining bit when set allows for special handling of contiguous memory references. As previously mentioned, the arbiter 12 controls which microengine will be selected to provide memory reference requests over the commander bus to queue 90 (
Contiguous memory references will be received in queue 90 when the chaining bit is set. Those contiguous references will typically be stored in the order queue 90 c because the contiguous memory references are multiple memory references from a single thread. In order to provide synchronization, the memory controller 26 a need only signal at the end of the chained memory references when done. However, in an optimized memory chaining, (e.g., when optimized MEM bit and chaining bit are set) the memory references could go into different banks and potentially complete on one of the banks issuing the signal "done" before the other bank was fully drained, thus destroying coherency. Therefore, the chain bit is used by the controller 110 to maintain the memory references from the current queue.
Referring to
As shown in
Referring to
The SRAM controller 26 b also includes core bus interface logic i.e., ASB bus 122. The ASB bus interface logic 122 interfaces the core processor 20 to the SRAM controller 26 b. The ASB bus is a bus that includes a 32 bit data path and a 28 bit address path. The data is accessed to and from memory through MEM ASB data device 128, e.g., a buffer. MEM ASB data device 128 is a queue for write data. If there is incoming data from the core processor 20 via ASB interface 122, the data can be stored into the MEM ASB device 128 and subsequently removed from MEM ASB device 128 through SRAM interface 140 to SRAM memory 16 b. Although not shown, the same queue structure can be provided for reads. The SRAM controller 26 b also includes an engine 127 to pull data from the microengines and PCI bus.
The memory requests are sent to SRAM interface 140 via multiplexer 126. The multiplexer 126 is controlled by the SRAM arbiter 131 which detects the fullness of each of the queues and the status of the requests and from that decides priority based on a programmable value stored in a priority service control register 130. Once control to the multiplexer 126 selects a memory reference request, the memory reference request, is sent to a decoder 138 where it is decoded and an address is generated.
The SRAM Unit maintains control of the Memory Mapped off-chip SRAM and Expansion ROM. The SRAM controller 26 b can address, e.g., 16 MBytes, with, e.g., 8 MBytes mapped for SRAM 16 b, and 8 MBytes reserved for special functions including: Boot space via flashrom 16 c; and Console port access for MAC devices 13 a, 13 b and access to associated (RMON) counters. The SRAM is used for local look-up tables and queue management functions.
The SRAM controller 26 b supports the following transactions:
Microengine requests (via private bus) to/from SRAM. Core Processor (via ASB bus) to/from SRAM.
The SRAM controller 26 b performs memory reference sorting to minimize delays (bubbles) in the pipeline from the SRAM interface 140 to memory 16 b. The SRAM controller 26 b does memory reference sorting based on the read function. A bubble can either be 1 or 2 cycles depending on the type of memory device employed.
The SRAM controller 26 b includes a lock lookup device 142 which is an eight (8 entry address content addressable memory for look-ups of read locks. Each position includes a valid bit that is examined by subsequent read-lock requests. The address and command queue 120 also includes a Read Lock Fail Queue 120 d. The Read Lock Fail Queue 120 d is used to hold read memory reference requests that fail because of a lock existing on a portion of memory. That is, one of the microengines issues a memory request that has a read lock request that is processed in address and control queue 120. The memory request will operate on either the order queue 120 c or the read queue 120 b and will recognize it as a read lock request. The controller 26 b will access lock lookup device 142 to determine whether this memory location is already locked. If this memory location is locked from any prior read lock request, then this memory lock request will fail and will be stored in the read lock fail queue 120 d. If it is unlocked or if 142 shows no lock on that address, then the address of that memory reference will be used by the SRAM interface 140 to perform a traditional SRAM address read/write request to memory 16 b. The command controller and address generator 138 will also enter the lock into the lock look up device 142 so that subsequent read lock requests will find the memory location locked. A memory location is unlocked by operation of a microcontrol instruction in a program after the need for the lock has ended. The location is unlocked by clearing the valid bit in the CAM. After an unlock, the read lock fail queue 120 d becomes the highest priority queue giving all queued read lock misses, a chance to issue a memory lock request.
As shown in
Referring to
The FBI 28 contains a Transmit FIFO 182, a Receive FIFO 183, a HASH unit 188 and FBI control and status registers 189. These four units communicate with the microengines 22, via a time-multiplexed access to the SRAM bus 38 which is connected to the transfer registers 78, 80 in the microengines. That is, all communications to and from the microengines are via the transfer registers 78, 80. The FBUS interface 28 includes a push state machine 200 for pushing data into the transfer registers during the time cycles which the SRAM is NOT using the SRAM data bus (part of bus 38) and a pull state machine 202 for fetching data from the transfer registers in the respective microengine.
The Hashing unit includes a pair of FIFO's 188 a, 188 b. The hash unit determines that the FBI 28 received an FBI_hash request. The hash unit 188 fetches hash keys from the calling microengine 22. After the keys are fetched and hashed, the indices are delivered back to the calling microengine 22. Up to three hashes are performed under a single FBI_hash request. The busses 34 and 38 are each unidirectional: SDRAM_push/pull_data, and Sbus_push/pull_data. Each of these busses require control signals which will provide read/write controls to the appropriate microengine 22 Transfer registers.
Generally, transfer registers require protection from the context controlling them to guarantee read correctness. In particular, if a write transfer register is being used by a thread_1 to provide data to the SDRAM 16 a, thread_1 must not overwrite this register until the signal back from SDRAM controller 26 a indicates that this register has been promoted and may now be re-used. Every write does not require a signal back from the destination indicating that the function has been completed, because if the thread writes to the same command queue at that destination with multiple requests, the order of the completion is guaranteed within that command queue, thus only the last command requires the signaling back to the thread. However, if the thread uses multiple command queues (order and read), then these command requests must be broken into separate context tasks, so that ordering is maintained via context swapping. The exception case indicated at the beginning of this paragraph is relative to a certain class of operations using an unsolicited PUSH to transfer registers from the FBI for FBUS status information. In order to protect read/write determinism on the transfer registers, the FBI provides a special Push_protect signal when these special FBI push operations are set up.
Any microengine 22 that uses the FBI unsolicited push technique must test the protection flag prior to accessing the FBUS interface/microengine agreed upon transfer registers. If the flag is not asserted, then the transfer registers may be accessed by the microengine. If the flag is Asserted then the context should wait N cycles prior to accessing the registers. A priori this count is determined by the number of transfer registers being pushed, plus a frontend protection window. The basic idea is that the Microengine must test this flag then quickly move the data which it wishes to read from the read transfer registers to GPR's in contiguous cycles, so the push engine does not collide with the Microengine read.
It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.
|Citing Patent
|Filing date
|Publication date
|Jun 7, 2006
|Mar 10, 2009
|Stmicroelectronics Pvt. Ltd.
|System and method for maintaining the integrity of data transfers in shared memory configurations
|Oct 10, 2003
|Jul 6, 2010
|Intel Corporation
|Method and apparatus for gigabit packet assignment for multithreaded packet processing
|Oct 10, 2003
|Apr 15, 2004
|Intel Corporation, A Delaware Corporation
|Method and apparatus for gigabit packet assignment for multithreaded packet processing
|Nov 5, 2002
|May 6, 2004
|Hooper Donald F.
|Flow control in a network environment
|Feb 17, 2004
|Sep 23, 2004
|Intel Corporation, A California Corporation
|Memory mapping in a multi-engine processor
|U.S. Classification
|711/151, 711/104, 711/150
|International Classification
|Cooperative Classification
|European Classification
|Dec 17, 2007
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WHEELER, WILLIAM R.;BURRES, BRADLEY;ADILETTA, MATTHEW;AND OTHERS;REEL/FRAME:020256/0037
Effective date: 20011204
|Sep 22, 2011
|Fee payment
Year of fee payment: 4


text: (Photo by Mike Ehrmann/Getty Images) [ Finally, Some Madness By Andy Lee March 17, 2012 CBS analyst Greg Anthony stars in a commercial where he rhetorically asks the audience, "Is it March monotony?" He quickly answers his own question by saying, 'no, it's March Madness.' The funny thing is day one of the NCAA Tournament was rather monotonous Read More|Comment Category: Basketball, March Madness, NCAA, Sports, SportsTalk Tags: duke blue devils, lehigh mountain hawks, March Madness, missouri tigers, ncaa tournament, norfolk state spartans, notre dame fighting irish, rick majerus, st. louis billikens, xavier musketeers Send to a friend! Share on Facebook Share on Twitter Pin it! Reddit This! Share on Tumblr!

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text:
Best in Beauty: September's Hottest Hair, Makeup and Skincare Tips
Get the inside scoop on the latest hair and makeup trends the red carpet regulars sported this month, and learn how you can try them yourself!Be the first to know about the latest beauty trends; sign up for the FREE Beauty Tips of the Week newsletter and you'll get a cool new beauty tip delivered straight to your inbox EVERY DAY! SEE MORE
OMG! A Celeb Hairstyle Scoop That Might Shock You
Here's a U.S. Open scoop you won't find in the sports section: ever wonder how top tennis stars like Venus Williams manage to look gorgeous both on and off the courts? Well, turns out that they have their very own hair and makeup salon, right at the U.S. Open's Arthur Ashe stadium! Tennis greats hit up the salon before and after their matches, because, as the pro in charge, celebrity hair and makeup stylist Julien Farel, told me, "These days the tennis court has become a catwalk, so not only do players need to perform at their best, they need to look great!" Crazy right? Well, it gets even more wild: this season, Farel is using a new technique called hair threading, where hair—instead of being secured with the sometimes-slippery bobby pins—is actually "stitched up" with thin elastic string! Easily blended into your hair, the string helps make chignon or ponytail totally budge-proof. Still not convinced? Watch this video to see how it's done and then do a DIY experiment with some stretchy cord from a fabric store and a thick, blunt-end needle (the kind kindergartners use on their arts and crafts projects). It's a look to love-love, if I do say so myself.
The Two Products That Make Taylor Swift Look Even Prettier
I just love the gorgeous ethereal makeup look Taylor Swift wore at one of her recent concerts. While her glowy makeup look is perfect for the stage, her makeup artist, Lorrie Turk tapped into a few fall makeup trends that are totally swipe-able for a fun night out with the girls (or guys!). First, there's Swift's stained red mouth that Turk created using Stila Lip Rouge in Pucker. Not only is this sweet lip look is totally kissable, it's also easy to pull-off: Lip Rouge is shaped like a felt-tip pen, so it's pretty much smudge-free. Plus, the color stays put forever. On Swift's eyes, Turk applied two golden hues—Makeup Forever Star Powder in 902 (a pearl gold) and 922 (a golden copper)— to the lids with a damp brush, which really intensified the shimmery effect. But what makes Swift's peepers really pop is the hint of intense blue shadow (Nars Duo Eyeshadow South Pacific) on the bottom lashline. Test drive the look this weekend; it'll be sure to catch that certain someone's eye.
How to Make Blush Look Fresh This Fall
You may have heard that everything '80s is back this fall. The one old-school trend that isn't ready for a comeback? Thick too-bright blush. If you're still doing the sweep the blush up to your temples thing, here's a quick 3.0 blush lesson. The new way to wear blush is more of a soft flush that starts at the apples, sweeps down across the lower part of your cheeks and is subtly blended so that it looks like your own rosy hue. To get the kind of natural-looking glow Beverly Hills 90210 star Shenae Grimes always seems to have, I find it easiest to use a cream blush, applying it right on top of your cheeks with your fingers and blending down and out to the side. (Try Nars Cream Blush Cheek Color in Penny Lane, a celeb makeup artist favorite.) Next. dab a little on your temples and then dab some more onto your eyelids—from the inside of the crease to just above the crease—to pull the blush color into the rest of your makeup look. It's like a quickie makeover, with just one product!
The Secret to Hollywood's Sexiest Brunettes (Plus, A Fab New Shine Product!)
Despite the blonding trend amongst some of Hollywood's most head-turning brunettes—both Angelina Jolie and Kim Kardashian have recently lightened up their locks—one look at these two raven-haired beauties, Lindsay Price and Jenna Dewan, and it's clear you don't have to go blond to be a certified bombshell. Maybe that's because there's a new way to make brunette hair look extra gorgeous. Brad Johns, color director for the Red Door Spas at Elizabeth Arden NYC, calls it "invisible highlighting," a salon process in which three shades of complementary browns—coffee, chocolate, dark chocolate—are all woven through the hair to give the color life and dimension. (That's salon-speak for total awesomeness.) You don't necessarily notice the different shades immediately, but the way the scene-stealing hair catches the light can't be missed. The other bonus: On natural brunettes, these invisible highlights only need to be touched-up once or twice a year for maintenance, so it's pretty wallet-friendly. Steering clear of any dye or highlights this season? Whatever your color, Johns recommends silicone drops like Davines Defining Drops to make hair as smooth as glass after a good blow-dry.
Why Fab Brows Might Be Your New Favorite Beauty Trick
If you're glued to the red carpet scene like I am, you'll notice that eyebrows are getting bolder and more defined this season. Makeup artist Brett Freedman recently explained why this new look is catching on so quickly: "For a while, stars were going for the lash extension look, where lashes were enhanced with mascara or faux lashes to really stand out as the most attention-stealing feature on your face. Now we're moving to brows as the stronger focal point," she says. So why is this good news? Because it's super esasy to take your look from day to night with just a brow update. To get the before-five version of the look, Freedman recommends filling in brows with a shade slightly lighter than your brow-hair color, so you see the hairs, not the makeup—it'll look more natural. At night, go for a color that's slightly darker than your natural hue to create a standout look. The only exception to this bold brow rule? Gals with dirty-blond hair. Freedman says they should always stick with a taupe-y shade, no matter what time of day you're working the look. To help you find your perfect brow-enhancing color, check out Vanitymark's 8 different brow powder shades.
Got a Hot Date? Try This Supermodel Hair How-To
While I can't tell you how she gets her Victoria's Secret curves, I've got the 411 on Miranda Kerr's bodacious curls. All you need is a few styling products and a curling iron, but the trick is to create curls just on the end of your lengths—not all over. Miranda's mane man, David Keough told me that he started with John Frieda Luxurious Volume Bountiful Body Mousse. "Then, using a big round brush, I gave her a blow-dry to give the hair some 'guts.' After I dried it, I went back in and sprayed the roots with John Frieda Luxurious Volume Lavish Lift Root Booster, which adds some lift," he said. "Then I used a curling iron from the ends up, going up the hair about 3 inches—I just wanted the bend at the bottom." After letting each curl cook, he tousled hair gently and spritzed with a light hairspray to keep the curls together and in place. Pretty easy, right?
How to Get Fall's Newest Lip Look (Without Buying a Thing!)
Mischa Barton has been popping up at New York Fashion Week, looking better than ever! She hit a Dior party wearing one of the hottest lip looks for fall: a wine-color lipstick that has a soft velvet finish. If you're loving it as much as I am, try these tips from celebrity makeup artist Toby Fleischman: "I'm obsessed with Nars Velvet Matte Pencils for a quick and easy application of spectacular color. Or you could simply blot some translucent powder over your regular color to matte-ify and modernize your normal shade. Just apply lipstick, press a single sheet of tissue over your mouth, then dust right over the tissue with the powder." Fleischman also reminded me that when playing up your lips, you want to keep the rest of your look understated. "Just use a few coats of mascara," she says. Gotta love a trend that can be created by reusing stuff you have in your makeup bag already.
Sneaky Ways to Make the Purrfect Cat Eye
Sometimes cat-eye makeup can look a little too old-school and contrived, but somehow Ginnifer Goodwin makes it look modern and sexy. So what's the secret? The sharpness and length of the liner. See how it thins out to a precise, pointed line at the end? It stretches to the very end of her eyebrows—the perfect stopping point when you're lining your own eyes. A sharply pointed liquid liner makes it easy to get a straight and narrow line. Try one of the new liquid liners pens, like Revlon ColorStay Liquid Eye Pen. They look (and work!) just like a fine-tip Magic Marker. To make the liner look even sharper, use a lining brush to apply a highlighting cream or even foundation to trace the top edge of the liner—it'll make it stand out even more and camouflage any unsteady edges.
Don't You Just Love This Red Lip Look? Good. Because You Don't Need a New Lipstick to Get It.
Sometimes when I wake up in the morning, red lipstick seems like too much trouble. I don't always have time to apply it perfectly, to find the right liner shade and to update the color throughout the day. But this fall, there's a new and totally effortless red lip look that's catching on. Instead of intense, color-saturated lips, it's all about gently stained color. And the best part? You can use lipstick you already have. Just use your fingers to smudge on your favorite shade instead of swiping it on with the applicator. Pair your muted red with bold brows, a few coats of mascara and a tiny bit of blush to create a makeup look that feels totally fresh and polished.
Lusting After Kim Kardashian's Sexy Hair? Us Too. Here's How to DIY Her 'Do.
Before I get into all the hairstyle tippage, I just have to geek out for a second: When I spotted Kim Kardashian backstage at the Catherine Malandrino show at New York Fashion Week, she pretty much stopped me in my tracks. Kim's skin and makeup looked totally flawless, and her hair was so shiny that I almost needed my sunglasses. The Bumble and Bumble hair team is responsible for her sexy 'do, so I immediately asked them for all the scoop. "I wanted to give Kim a glamorous, pretty, old-Hollywood style that played up her classically beautiful features," Bumble and Bumble stylist Rolando Beauchamp told me. "To start, I applied Bumble and Bumble Thickening Hairspray to Kim's damp hair and created a very deep, very straight side part with a fine-toothed comb. I then used a large round brush to blow out her hair in sections, making sure each section of hair was exactly the same width as the round brush. That's the key to achieving the smooth, glassy finish." Easy, right? I want to run home right now and try Rolando's tip myself, but before I do, here's one last hairstyle tip for my fellow Kardashian fans: Rolando used velvet-coated hot rollers called Remington Protect & Shine Rollers to create Kim's bodacious curls. After removing curlers from Kim's hair, he gently brushed the curls into soft waves and then finished the look with Bumble and Bumble Does It All Hairspray.
The Skin-Softening Product That Supermodels Swear By
One of my favorite people to run into backstage at New York Fashion Week is the adorable Chanel Iman. She really puts the "super" in supermodel: She's super friendly, super funny and super generous—when I saw her backstage at the Jason Wu show, she shared everything, from her salmon croquette recipe to one of her fave beauty products—Olio Lusso by Rodin. "It's an oil I apply after taking a hot bath—it smells so good and makes your skin so soft and is so soothing, it makes me sleep like a baby! I also put it on when I wear a bikini; it makes your skin look flawless!" Created by Linda Rodin—a former model and longtime fashion stylist—the product has a cult following: Celebrity makeup artist Diane Kendal was among the many beauty pros who raved about it to me during New York Fashion Week. While it's not exactly cheap ($135 for one ounce!), it's nice to know the folks who have used and experimented with the beauty products in the world give it two big thumbs-up. Although, if you're in the market for a more wallet-friendly oil, I can also give Neutrogena Bath Oil ($10) the stamp of skin-softening approval.
The New Way to Wear Your Nail Dark Polish
I love how Kerry Washington managed to coordinate her dress and makeup without looking too prissy or matchy-matchy. Instead of the usual match-your-dress-to-your-lipstick thing, her makeup artist, Autumn Moultrie, went for a muted lip look and opted to echo Kerry's dress color in her cheeks by just applying a hint of sheer coral blush right to her apples. I also love how Kerry's bright, glowy cheeks contrast with her dark, vampy nails. Her whole look is a little ladylike and a little edgy, which is the freshest way to go, according to celeb manicurist Deborah Lippmann. Last year, we saw a lot of celebs go a little Goth with their makeup by pairing black nails with dark lipstick, but Lippmann says things are lightening up this season—choose one edgy feature in your makeup look and keep the rest pretty and sweet—just like you! To test out Kerry's nail look, try Lippmann's Dark Side of the Moon, a deep gray-green polish.
A Step-by-Step Guide to Creating Mischa Barton's Too-Dewy-to-Be-True Makeup Look
Want to know the secret behind Mischa Barton's gorgeous new look? Me too. That's why I asked Anetta Klemens, genius celebrity makeup pro/the beauty guru behind Mischa Barton's new beauty look, to spill the details. She tells me it is the lack of dark and smudgy eye makeup—something that used to be one of Barton's signature styles—that makes all the difference. "I was convinced it was time for Mischa to refresh her look to reflect her healthier state of mind by using more color and less heavy eye makeup," Klemens told me. To start, she prepped Barton's skin with Aveeno Positively Radiant Daily Moisturizer SPF 30 to brighten and even her skin tone, then applied a foundation mixture of Makeup For Ever HD Invisible Coverage Foundation and Clinique Up-lighting Liquid Illuminator in Natural. "I used a fluffy brush to apply light brown eyeshadow from Bobbi Brown's Nude Eye Palette on the crease, then I patted the gold shade in the palette on top of the brown, using my finger. This made her eyes look extra big!" said Klemens. And instead of a heavy liner, she used a thin black pencil to apply a light layer of color to the lids, starting at the center of the eyelid and drawing a line outward—always staying very close to the lashes. She slanted the line upward a little at the end and then blended the line in a little to soften the overall look. "On the bottom, I used a softer pencil to keep the line delicate, again starting at the middle and moving outward. This way opens up the eye instead of closing it up, like the typical smoky eye makeup Mischa used to wear," added Klemens. Finally, after applying concealer, Makeup For Ever Invisible Coverage HD Concealor, to make her eyes look even brighter and healthier, Klemens finished the look by using CoverGirl Outlast Lipstain in Berry Smooch to add a subtle hint of color to Barton's lips. It's a look worth testing out, don't you think? Especially since that beautiful CoverGirl lip stain is only $8!
An Emmy-Worthy Updo That You Can Do Yourself
Heidi Klum's Emmy Awards appearance totally took my breath away—not just because she has that especially gorgeous pregnancy glow but also because her chignon was so, well, chic! To get a sculptural bun like Heidi's, hairstylist Michel Aleman says to start by center-parting the hair. Next, apply Frédéric Coiff Bouffant Lifting & Texturizing Spray Gel before blowing it dry, then make two same-size ponytails just above the nape, one about an inch away from the other. Take one ponytail and coil into a bun, wrapping hair around both ponies. Secure with pins, then take the other ponytail and coil that around the existing bun. This will give the final chignon a little more structure and make hair look extra thick and voluminous. Finish it all off with Frédéric Fekkai's Advanced Brilliant Glossing Sheer Shine Mist and you'll be ready to take on the evening's activities—whether it includes hitting an awards show or watching a good Hollywood flick.
A Fab New Solution to the "Should My Mani-Pedi Match?" Dilemma
Backstage during spring 2010 New York Fashion Week, there were a lot of discussions about matchy-matchy nails and toes. Some nail pros said they liked it best when both polishes matched perfectly, while others liked more of a tone-on-tone match (meaning either hands or feet had a slightly brighter version of the same tone). While the debate still rages on, it looks like Freida Pinto found her own solution: She matched her fingernail polish to her clothes and her pedicure polish to her shoes! The star was recently photographed wearing a buttercream-color dress and a sweet off-white manicure with a deep burgundy pedicure peeking out of her dark strappy shoes. Even if a sexy little dress and high-heeled sandals like Freida has on here isn't something you wear every day, it'd be easy to match your nails to, say, a favorite fall jacket and do your tootsies in a color that pairs well with your favorite jeans, right? If you're into that idea, you'd love Barielle's Slate of Affairs and Falling Star, two blue nail lacquers that would both look great with denim!
If You Buy Only One New Beauty Product This Fall, Make It This One
Yes, I know that seems like a dramatic declaration, but really, who doesn't love a gorgeous pink lipstick? It's one of the most universally flattering makeup looks out there, and like its cousin red lipstick, it can glam up an outfit in seconds. Celebs are already in on this beauty secret: I've seen more fuchsia lip looks at fashion shows and awards shows this fall than ever before. So why the hot pink? Makeup artist Anetta Klemens tells me that the new lip trend is all about "brightening up and looking more alive"—a grin-and-bear-it response to this tough and wacky year. The trick to pulling off a sexy pink lipstick like Mischa Barton's (who, by the way, is wearing Nars Lipstick in Funny Face semi-matte fuchsia in this snap) is to go easy on the eye makeup. Just stick to a neutral shadow and add a few coats of mascara. Another good trick? Try bronzer instead of blush. When you restrict the pink hue to your pretty smile, it'll make your bold lip look stand out even more. If the straight-from-the-tube color seems too bright for you, try blotting it down gently to create more of a stain, then finish with clear lip gloss.
Get Kim Kardashian's Gorgeous Eye Makeup Look (for Just $10!)
Oh, Kim Kardashian—the girl can do no wrong makeupwise! To get the amazing silverized eye makeup Kim wore to the Emmy Awards, all you need is a soft metallic pencil like L'Oréal's HIP Color Chrome Eye Liner in Silver Lightening. A makeup artist pal recently turned me on to this amazing drugstore find, and I have to say, the $10 product is pretty much perfect: Not too creamy and not too stiff, it works for creating a finely lined look or a smudgy, more full-coverage effect. (It even comes in gold!) To get Kim's look, apply the metallic liner on the inside rim of the eye to make eyes pop. Continue to sweep the color across the whole lid, way up into the crease. Blend well to "smoke it out" and create an even color, then add a little line under the lower lashes to pull the whole look together.
Good News for Ponytail Addicts: Your Favorite 'Do Is Fall's Hottest Hairstyle
If you watched the Emmys, you probably noticed that a ton of A-listers sported big, beautiful ponytails instead of a fussy updo. While I thought all of them looked amazing—including Kristin Chenoweth's tight 'n' sleek style and Debra Messing's fluffy, curled version—I loved actress Emily Blunt's best, especially since I know her 'do would work well in real life. That's why I asked Blunt's stylist, Jeffrey Paul, to give me some DIY ponytail tips. Paul's first suggestion was all about what to wear with a pony: He suggests pairing a looser ponytail with tighter clothes for a cool contrast. Next, he suggested experimenting with your pony before you head out the door: Find the spot where your ponytail will sit most comfortably—usually it's above or below your occipital bone at the back of your head, not directly on it. Paul also encouraged using a "hair bungie"—a thin elastic cord with a hook on each end—to secure hair without crushing or kinking it. And finally, if you're really feeling daring, channel your inner screen siren and add in some faux extensions—drugstore versions will totally do the trick—to pouf up or lengthen your pony, just like all the Hollywood stars do.
The Face-Slimming Makeup Trick Celebs Swear By
You probably wear just one color of foundation, right? Well, celebs usually have two—and that's the secret to their sleek, sculpted makeup looks! A lot of celeb makeup artists, including Brett Freedman—who works with all the glam Melrose Place stars—use one skin-tone-matching foundation color to create an even base and another shade that's a teensy bit lighter or darker, to contour the face. Freedman says that when applied to the center of the forehead, nose, cheeks and chin, the lighter hue acts as a "spotlight" to brighten the face. Meanwhile, the darker shade can be used along the jawline to make your cheekbones look higher and slim the face. If all that color mixing and matching seems like something best left to the pros like Freedman, try this easy tip: After applying your regular foundation, use a slightly darker foundation shade and add a little bit just under your cheekbones as you would a bronzer. This'll make your cheekbones more pronounced, and since the hue isn't bronze or pink, you can wear it with any kind of eye-makeup color. One last foundation tip: If buying more than one shade seems daunting, try L'Oréal's True Match Liquid Makeup. I've seen the color-matching product in multiple celeb makeup artists' kits—and it's only $11. It doesn't get much better than that!


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Ryan's so consistent that sometimes it seems the hardest part for him is deciding which tricks to do. Here's a nice trio.
Ryan has that rare "problem" where he stacks such a firestorm of utterly insane clips that even a skate rat's brain has a hard time comprehending it all. You just have to watch this.
Yeah, he's got that crazy natural talent and consistency but, trust us, Ryan pushed himself hardcore for this part. Get ready. Full part premieres here on Friday.
Paul has an aggressive, possessed approach to skating where he just crushes spots. Here's basically two full parts with a ripping Friends section in the middle. Ryan Decenzo introduces a classic Globe part from 2007.
Remember Me


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Former Bredesen officials go to work for special interests
By Brad Schrade | Published July 28, 2009
Several high-ranking Bredesen officials went to work after leaving office for clients seeking to influence state government, according to Channel 4 investigative reporter Jeremy Finley. One of them, Paula Flowers, is now running for Congress. Others mentioned in the investigation include former Deputy Governor Dave Cooley, legislative director Robert Gowan and communications chief Bob Corney. […]
Posted in Politics | Tagged Bob Corney, Dave Cooley, investigative reporting, Jeremy Finley, Lobbying, Paula Flowers, Phil Bredesen, Robert Gowan, special interests | Comments Off
AboutThe Tennessean's political staff keeps tabs on the latest from Legislative Plaza and beyond. Contributors include Chas Sisk, Michael Cass and Bill Theobald.
Tags4th congressional district 6th congressional district 2014 election Barack Obama Bart Gordon beth harwell Bill Haslam Bill Ketron Bob Corker Chip Forrester diane black Douglas Henry education Glen Casada Governor's race guns health care reform House jeff yarbro Jim Cooper Jim Gotto jim kyle Jim Tracy Joe Carr Karl Dean Kent Williams Lamar Alexander lou ann zelenik Marsha Blackburn Metro Council MIKE MCWHERTER mike turner mitt romney Music City Center Phil Bredesen Rich Riebeling ron ramsey Roy Herron scott desjarlais Senate Stacey Campfield tea party Tennessee Democratic Party Tennessee State Fairgrounds Zach Wamp


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Well-known as a primary antioxidant, Vitamin C is also important for healthy immune functions.* Daily use may help to maintain and improve overall health. Vitamin C can be used daily for supporting natural immune responses and defending the body.
For immune support and environmental protection, use ChildLife Vitamin C daily as a vital antioxidant.* When needed, use with ChildLife First Defense and ChildLife Echinacea.
Directions for Use: For infants 6 months to 1 yr: 1/4 teaspoon daily. For children 1-4 yrs: 1/2-1 teaspoon daily. For children 5-12 yrs: 1-2 teaspoons daily.Shake well before use. Store in a cool dry place. Can be mixed with juice or your child's favorite drink.
* Daily value not establishedThese statements have not been evaluated by the FDA. These products are not intended to diagnose, treat, cure, or prevent any disease.
Other IngredientsPurified Water, Fructose, Glycerine, Potassium Bicarbonate, Grapefruit Seed Extract, Potassium Sorbate, Xanthan, Natural Orange Flavor. Gluten free casein free, alcohol free. Contains no milk, eggs, soy, wheat, yeast or corn. No artificial colorings, flavorings or sweeteners.
Pharmaca Integrative Pharmacy is your source for natural health products. Browse our online selection of products from all of the best natural brands, or visit one of our pharmacy locations and talk with one of our licensed practitioners. From natural beauty products and cosmetics to vitamins, herbs and supplements, we offer high-quality natural wellness products for the whole family! Start exploring—shop by brand or by condition to find the perfect natural health products for your body, skin, home and more.
The products and claims made about specific products on this site have not been evaluated by Pharmaca.com or the United States Food and Drug Administration and are not approved to diagnose, treat, cure or prevent disease. The information on this site is for educational purposes only and is not intended as a substitute for advice from your physician or other health care professional or any information contained on or in any product label or packaging. You should not use the information on this site for diagnosis or treatment of any health problem or for prescription of any medication or other treatment. You should consult with a healthcare professional before starting any diet, exercise or supplementation program, before taking any medication, or if you have or suspect you might have a health problem. Pharmaca Integrative Pharmacy will not assume liability for any cross-contamination of ingredients, misprints, or adverse reactions to any ingredients in the products we carry. The products sold here may contain lead and other substances that are known to the state of California to cause cancer and birth defects and other reproductive harm. Prices and promotions are subject to change without notice. All content on this web site is copyrighted by Pharmaca Integrative Pharmacy unless otherwise stated. All online offers and prices are valid for online purchases only, and may be different from those in our retail stores. Free shipping offer may not apply to all orders and all states; see shipping policy for full details. Copyright © 2009 – 2015 by Pharmaca Integrative Pharmacy. All rights reserved.


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Max, a former champion living in Arizona, was healthy and happy before his owner was forced to give him up.
As the deadly snow storms that have already hit the Great Plains illustrate, winter is coming. It won't be long before much of the country is buried under a blanket of white.
This is the time of year equine rescues, sanctuaries, and community hay banks serving needy horse owners stock up on hay for the entire winter. The ASPCA assists these groups through grants made possible by our members' compassion and generosity, ensuring that horses don't suffer and starve.
One such group is the Arizona Coalition for Equines (ACE), which received a $3,000 grant from the ASPCA in November 2012. These are just a few of the lives ACE was able to touch with that funding:
- Slammed by foreclosure on her home and forced to move after the death of her mother, a woman living on disability ran out of money to feed her two horses. She turned to ACE for a helping hand, saying she would rather feed her horses than herself. ACE responded with a month's worth of hay and settled her unpaid feed bill, giving her time to get back on her feet. Her horses remain in excellent condition.
- A disabled veteran on a fixed income asked ACE for help when his horse became unable to walk. Sometimes feeding his horses before himself, he was desperate to get veterinary care but unable to pay the upfront costs. With ACE assistance, a veterinarian did a complete examination and diagnosed thrush, a front hoof abscess and a possible pelvic injury. Treatment provided immediate relief.
The greatest success story belongs to Max, a 30-year-old former champion show horse (pictured) who had been owner-released to a commercial stable due to financial hardship. His former owner was devastated when he went to visit Max months later and found him close to death—he had been left to starve. The man reached out to ACE, which rescued Max and covered the cost of his foster care until a new forever home was found.
As you budget your holiday spending and pick out the perfect gifts for everyone on your list, please remember the horses—as well as the cats and dogs—who are out in the cold this winter. If you haven't done so lately, please consider making a gift to the ASPCA today. You'll assist animals like Max who are bracing for winter and waiting for our help.
When ACE rescued Max from a commercial stable, he was emaciated and starving from severe neglect.


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We're delighted to announce that I Love Blue Sea has joined Vital Choice. We share the same passion for health and vitality, and we offer you easy access to an even wider variety of premium seafood that is among the purest and most nutritious available. Please accept our offer of a 10% discount on your first order. Simply use code ILOVEVC at checkout. Welcome to the Vital Choice family.
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There's a lot on the line when you fire up the grill for the family or any gathering. The last thing you need is worry about charring or drying the fish at the center of your feast!
Our pure, untreated Alder Grilling Planks offer the perfect solution!
Native Americans in the Pacific Northwest pioneered the art of roasting fish and game on wood planks, which preserves moisture and imparts wonderfully subtle wood notes to grilled food.
Each plank is 12" long x 5 1/2" wide, about 3/8" thick. They can accommodate two to four portions of fish, and are normally good for just one use.
(Planks may be used twice if they are not seriously charred.)
Cedar Plank Salmon; Johns Fish Marinade
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Grilling planks are normally good for just one use, but may be reusable if they're not charred too seriously.
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Soak the planks first, or they will burn on the grill. Immerse them in clean water for at least two hours, or overnight. If you have less than two hours for soaking, immerse the planks in hot water to speed absorption.
Place the planks in a clean baking dish or kitchen sink, add enough water to cover, and weight the planks down with a heavy object to keep them completely submerged.
If you have time to soak the planks for several hours, you can add white wine, beer, apple cider, fruit juice or fresh herbs to the water to impart added flavor to your cooked fish or shellfish.
Dry the soaked planks well using a clean dish towel, and then brush or spray the top surface lightly with olive or macadamia nut oil. You can also choose to rub herbs, garlic or flavored oil onto the planks.
Place the fish or shellfish on the prepared plank, skin-side down for skin-on fillets. As desired, rub seasonings on the top of the fish, but go easy lest you overpower the flavor imparted by the plank. (Vital Choice Salmon Marinade mix works well for this purpose.) Fruit slices or vegetables sprinkled around the fish will help retain moisture and enhance the flavor as well.
Place plank with the fish or shellfish on the preheated medium-hot grill (i.e., between 350 F and 450 F.) Close the lid. At this temperature, the grilling plank should give off light to medium smoke within a few minutes.
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When the fish is done, bring the plank to the table the sizzling, smoking seafood makes quite an impression!
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Submission + - IBM-Texas settle contentious data center consolidation spat->
coondoggie writes: "Looking to avoid what would have been a costly and likely lengthy court battle IBM and the state of Texas's Department of Information Services have apparently agreed to disagree over a failed $863 million data center consolidation pact. Published reports indicate that under an agreement, IBM will transfer $20 million worth of equipment already installed to the state and forgo $26 million worth of billing for work it has already done. For its part, Texas will pay in total about $35 million owed to IBM for the cost of services and equipment. As of February, Texas had paid IBM almost $758 million and assessed the Big Blue $10 million in penalties for failing to meet certain contract requirements."
Link to Original Source
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February 10
Sunday, 2:00 pm
Afternoon Lecture
Deciphering the Lod Mosaic
Highway construction in Lod, Israel in 1996 accidently unearthed a large and well-preserved Roman mosaic that probably once decorated a large audience room. The mosaic dates to circa 300 CE and features a kind of arena of ferocious animals, including a lion and lioness, an elephant, a giraffe, a rhinoceros, a tiger, and a wild bull. In this lecture, Dr. C. Brian Rose, Curator-in-Charge, Mediterranean Section, explores why decorative motifs of this kind were held in such high esteem during the Roman Empire. That exploration leads us into the world of gladiatorial games, the wild animal export industry, and mythological charades in ancient Rome. Free with Museum admission. For more information, call 215.898.2680.
Image © Israel Antiquities Authority
3260 South Street
Philadelphia, PA 19104
(215) 898-4000
Tuesday-Sunday: 10:00am - 5:00pm
First Wednesdays: 10:00am - 8:00pm
Monday: CLOSED


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Lori Popkewitz Alper is the founder and editor-in-chief of Groovy Green Livin, a site dedicated to sharing simple green living tips and current information on sustainable living. Lori uses Groovy Green Livin as a platform to create awareness, dialog and debate surrounding advocacy for healthy environments without harmful chemicals.
A contributing writer for multiple blogs and websites, Lori speaks, writes and advises on a variety of issues related to creating a greener lifestyle. Lori is a green living educator, social media consultant, freelancer, blogger and recovering attorney. She lives in the Greater Boston area with her three sons, chocolate lab and groovy husband.
In her free time Lori can be found practicing yoga, pitching a baseball, running, cycling, skiing, reading, cooking, or eating Stonyfield Vanilla Fudge Swirl Nonfat Frozen Yogurt.
Connect with Lori and Groovy Green Livinon Facebook, Twitter, Pinterest, Google+ and LinkedIn.