text:
|Publication number
|Publication type
|Application number
|Publication date
|Jun 22, 2004
|Filing date
|Mar 9, 2001
|Priority date
|Mar 9, 2000
|Fee status
|Publication number
|Bryan H. Hoyer, Michael C. Fairman
|Original Assignee
|Altera Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (42), Non-Patent Citations (16), Referenced by (39), Classifications (6), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims priority of U.S. provisional patent application No. 60/188,348, filed Mar. 9, 2000 entitled "Method of Gaining Access to Internal Nodes in a PLD," which is hereby incorporated by reference.
This application is related to U.S. patent application Ser. No. 08/958,435, filed Oct. 27, 1997, entitled "Embedded Logic Analyzer For A Programmable Logic Device, " now U.S. Pat. No. 6,182,247 to U.S. patent application Ser. No. 09/186,607 filed Nov. 6, 1998, entitled "Enhanced Embedded Logic Analyzer," now U.S. Pat. No. 6,286,114 and to U.S. patent application Ser. No. 09/186,608 filed Nov. 6, 1998, entitled "Enhanced Embedded Logic Analyzer:," now U.S. Pat. No. 6,247,147.
The present invention relates generally to analysis of a hardware device in connection with a computer system. More specifically, the present invention relates to analysis of internal registers within a programmable semiconductor device for purposes of debugging.
In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design. However, once the PLD has been programmed and is operating within a working system, it is also important to be able to debug the PLD in this real-world environment.
And although a simulation may be used to debug many aspects of a PLD, it is nearly impossible to generate a simulation that will accurately exercise all of the features of the PLD on an actual circuit board operating in a complex system. For example, a simulation may not be able to provide timing characteristics that are similar to those that will actually be experienced by the PLD in a running system; e.g., simulation timing signals may be closer or farther apart than what a PLD will actually experience in a real system.
In addition to the difficulties in generating a comprehensive simulation, other circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a PLD that are only evident when the PLD is operating within a working system. Still further, it can be difficult to generate sufficiently varied test vectors to stress the PLD design to the point where most bugs are likely to be observed. For example, a PLD malfunction can result when the PLD is presented with stimuli that the designer did not expect, and therefore did not take into account during the design and simulation of the PLD. Such malfunctions are difficult to anticipate and must be debugged in the context of the complete system. Thus, simulation of an electronic design is useful, but usually cannot debug a PLD completely.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. (For example, the HP1670A Series Logic Analyzer from Hewlett-Packard Company.) Typically, a number of probe wires are connected manually from the logic analyzer to pins of interest on the hardware device in order to monitor signals on those pins. The logic analyzer captures and stores these signals. However, the use of an external logic analyzer to monitor pins of a hardware device has certain limitations when it comes to debugging such a device. For example, such an external logic analyzer can only connect to and monitor the external pins of the hardware device. Thus, there is no way to connect to and monitor signals that are internal to the hardware device. Unfortunately, when programming a hardware device such as a PLD, it would be useful to be able to monitor some of these internal signals in order to debug the PLD.
Although some custom hardware devices may come ready-made with some internal debugging hardware, this debugging hardware is typically hardwired to route specific internal signals and cannot be readily changed by an engineer who wishes to look at other signals. Also, with such built-in debugging it is not possible to choose any signal to monitor that the engineer desires. Further, creating an electronic design for a PLD is an iterative process that requires creative debugging by an engineer who may wish to view almost any internal signal, and who may change his mind fairly frequently in the course of debugging a PLD within a system.
As explained above, debugging discrete components on a circuit board used to be simpler in that one could look at most any input or output. Now that components are inside an integrated circuit, the ability to look at intermediate nodes and signals is inhibited. In other words, while the inputs and resultant outputs of a chip are visible, the intermediate points inside the chip are not. The overall problem then is the visibility of nodes and signals inside a chip.
Various prior art techniques have been used to solve different aspects of this problem, i.e., techniques for looking at internal signals. Actel Corporation of Sunnyvale, Calif. provides a product named SILICON EXPLORER which is an external logic analyzer with JTAG capability. This tool, however, is only able to route two internal signal lines to the outside of a chip for analysis. All internal registers are not visible. These signals are specified by the user and may not be flexibly reassigned to other signals. Furthermore, the signals are referenced via the netlists and are not identified in the original source code.
Prior art techniques that allow identification of signals by reference to a netlist can be useful; however, identifying a signal in a netlist is always a complicated and time-consuming technique. It would be far easier for a design engineer to be able to identify registers of interest in the source code directly while the engineer is creating that source code.
In the realm of processors, various tools exist for halting and dumping the contents of a processor but there is no capability for the easy identification of internal registers for analysis. With ASICs, it is known to create a built in JTAG scan chain with which to scan out information. This scan chain, though, is only for use while the device is in a test fixture and is being tested for functionality. The JTAG scan chain is not used while the device is operational in a system.
Intel Corporation of Santa Clara, Calif. uses a JTAG port to control access to specified debug registers for help in debugging a central processing unit (CPU). Because a CPU is a known design, it is known beforehand exactly how many debug registers will be needed and control is simpler. With a PLD, however, each user-implemented design will be custom; it is unknown ahead of time what that design will be and how many debug registers might be needed. Different designs will require different debug registers. Thus the straightforward technique used by Intel with a known design of a CPU would not be appropriate with a PLD.
U.S. patent application Ser. No. 08/958,435, now U.S. Pat. No. 6,182,247 referenced above discloses an advantageous apparatus and technique that allow an embedded logic analyzer to flexibly analyze internal signals of interest in an electronic design, such as within a programmable logic device (PLD). The other two above-referenced patent applications disclose a technique for embedding a separate logic analyzer in a PLD for later analysis of internal signals. These techniques, however, all impact the design in that the separate logic analyzer takes up resources in the design and may not always be the optimal solution. Thus there is room for improvement in the analysis of internal signals of a PLD for debugging purposes.
As described above, in the course of working with blocks of programmable logic it is often necessary to reveal the contents of internal registers or nodes. When programming an ASIC this can be accomplished via a scan chain connected to the JTAG port. Registers of interests are inserted in the manufacturing test scan chain and then test software can be written to reveal their contents. In programmable logic, though, the manufacturing scan chains verify the electronic design prior to the download of the end user's design. In other words, scan chains are inserted to test the electronic design but are not part of the end user's design, therefore end users do not have the option of inserting scan chains. An end user could of course rebuild the test logic in the programmable part of the chip but this is undesirable as it consumes both engineering development time and programmable resources. It is possible to insert an embedded logic analyzer into a programmable device (as mentioned above), but this solution is not always desirable as it performs capture into a memory buffer that uses chip resources.
What is desirable then is a technique for identifying internal registers in the source code and for automatically making these registers visible during testing or later use without significantly impacting an electronic design.
To achieve the foregoing, and in accordance with the purpose of the present invention, a debugging device and technique are disclosed that allow internal registers of a PLD to be exposed for debugging.
The present invention provides a means for a user of a programmable logic device to identify registers or nodes of interest at the source code level and then have these registers automatically inserted in a scan chain where they can be accessed by test software provided by the device manufacturer. Initially, the EDA software tool provides a means of choosing a node or register of interest from the electronic design. Next, the EDA tool connects the selected node to the JTAG scan chain and passes information to the control/post processing software about the location of the node in the scan chain. The EDA tool provides for scanning of the chain under automatic or manual control. The selected nodes are extracted from the chain and displayed in a user-specified format.
In a second embodiment of the invention, registers in encrypted blocks can be exposed. Before a particular encrypted block is sold to a user, the vendor of the block decides which registers are of importance or would be interesting to view for an engineer who is attempting to debug an electronic design. The vendor may select these registers on their own, or may select registers based upon input from its various customers. Once these registers are selected, the vendor creates a "debugging" file which is delivered to the customer along with the encrypted block. The "debugging" file contains the names of the registers (unencrypted) in the source code to which a user will have access. The user may then convey these names to the EDA tool so that they are exposed during debugging.
This embodiment of the present invention provides numerous advantages for the vendor of an encrypted block intended for an electronic design. Although a vendor wishes to allow an engineer to debug a system of which their block is a part, they do not wish to reveal their source code or go to extra efforts. Making use of this embodiment, a vendor need not change their source code to allow debugging to occur, and need not reveal their source code to the engineer user. The vendor simply creates a simple "debugging file" with names of registers to be viewed and their symbolic values.
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram of a programmable logic development system according to one embodiment of the present invention.
FIG. 2 is a flowchart of a design methodology used to design a programmable logic device according to one embodiment of the present invention.
FIG. 3 is a block diagram illustrating a programmable logic device under test.
FIG. 4 is a flow chart describing a technique for exposing a register in a PLD.
FIG. 5 illustrates an apparatus for implementing step 214 of FIG. 4.
FIG. 6 is a sense cell which may be used to implement the shift register of FIG. 5.
FIG. 7 is a flow chart describing a technique for exposing a register in an encrypted block.
FIGS. 8A and 8B illustrate a computer system suitable for implementing any of the computers of FIG. 1 or 3, and for hosting an EDA tool.
In order to develop a design for programming an electronic design such as a programmable logic device (PLD), a programmable logic development system is used. As used herein, "electronic design" refers to circuit boards and systems including multiple electronic devices and multi-chip modules, as well as integrated circuits. For convenience, the following discussion will generally refer to "integrated circuits",or to "PLDs", although the invention is not so limited.
FIG. 1 is a block diagram of an embodiment of a programmable logic development system 10 that includes a computer network 12, a programming unit 14 and a programmable logic device 16 that is to be programmed. Computer network 12 includes any number of computers connected in a network such as computer system A 18, computer system B 20, computer system C 22 and computer system file server 23 all connected together through a network connection 24. Computer network 12 is connected via a cable 26 to programming unit 14, which in turn is connected via a programming cable 28 to the PLD 16. Alternatively, only one computer system could be directly connected to programming unit 14. Furthermore, computer network 12 need not be connected to programming unit 14 at all times, such as when a design is being developed, but could be connected only when PLD 16 is to be programmed.
Programming unit 14 may be any suitable hardware programming unit that accepts program instructions from computer network 12 in order to program PLD 16. By way of example, programming unit 14 may include an add-on logic programmer card for a computer, and a master programming unit, such as are available from Altera Corporation of San Jose, Calif. PLD 16 may be present in a system or in a programming station. In operation, any number of engineers use computer network 12 in order to develop programming instructions using an electronic design automation software tool. Once a design has been developed and entered by the engineers, the design is compiled and verified before being downloaded to the programming unit. The programming unit 14 is then able to use the downloaded design in order to program PLD 16.
For the purposes of debugging a PLD according to an embodiment of the present invention, any of the computers shown or others may be used by an engineer to compile a design. Furthermore, programming cable 28 may be used to receive data from the PLD, or a separate debugging cable may be used to directly connect a computer with device 16. Such a programmable logic development system is used to create an electronic design. A user creates a design by specifying and implementing functional blocks, as will now be described in the context of an exemplary design methodology.
FIG. 2 shows a design methodology 50 for using a system design specification in order to develop a design with which to program a PLD. It should be appreciated that the present invention may be practiced in the context of a wide variety of design methodologies. By way of example, the work group computing techniques and system of the present invention work well with an electronic design automation (EDA) software tool within the framework of the methodology of FIG. 2.
In step 52 a system specification for the PLD to be programmed is obtained. This specification is an external document or file that describes, for example, the device pin names, the functionality of each of the pins, the desired system functionality, timing and resource budgets, and the like.
Once the system specification is obtained, creation of a design using functional block diagrams is begun. In step 54 a top-level block diagram is created in which connections between lower-level designs blocks are specified. In this block, the target device, speed grade, and key timing requirements may be specified. Those skilled in the art will recognize that this top-level block may also include blocks that have already been developed or implemented or that have been obtained from a third party provider. This top-level block may also be converted into an HDL file, or the like, for use in other related design tools, such as an external simulator.
Step 56 includes generating design file templates with the EDA tool for all blocks present in the top-level block diagram of step 54. After the designer has created a block which has not yet been implemented, the system may generate a design file template. Such templates may display a block in a window format including, for example, a title, a date, etc. around the boundaries. It may also include some details of the functional content depicted within the window. The design file templates may be in any specified design format including VHDL, AHDL, Verilog, block diagram, schematic, or other like format. In the case of a VHDL block the template may also include much of the formatting and necessary syntax for any VHDL block. The user need only take the template and add the small portion of VHDL syntax required to implement his function. For example, the user may need only add syntax defining a particular AND gate operation. Normal design, such as VHDL or other IEEE standard, requires large amounts of text to adequately set up the design block.
Those skilled in the art will recognize that design file templates such as these can be used as starting points for the design of the structural or functional entities needed by the design. Thus, a design file template may serve as a reusable object for different instances of a block in one or more designs. More importantly, design file templates will be employed to reduce the amount of labor that the designer must expend to generate the logic in the blocks. In one embodiment, the generation of the design file templates is done in such a way that the templates can be updated later if the top-level block diagram changes.
Next, in step 58, each of the blocks of the top-level block is implemented using the EDA tool. It is noted that for more complicated designs, there may be additional levels of block diagrams (i.e., blocks within blocks). If changes are required at the top-level then the top-level block diagram is updated and the sub-designs are preferably automatically updated as well.
Furthermore, a block may be compiled through to a fitting stage for a particular integrated circuit die to provide information about resource utilization, timing performance, etc., as required for a given design. As such, it is envisioned that some timing optimization may be performed during step 58. This sequence illustrates a style of design in which an engineer first designs, then compiles and simulates, and then returns to design again if the simulation results are not satisfactory. In another style, an engineer may iterate through a number of design followed by simulation loops before finally compiling the complete design.
Concerning block implementation order, one or more of the following factors can be used to determine implementation order: (1) the complexity of a block; (2) the uncertainty or risk associated with a block; and/or (3) how far upstream and/or downstream in a given data-path the block resides. Each of steps 60, 62, 64, 68 and 70 may also lead back to this block implementation step for additional implementation necessitated by later changes in the design.
In step 60 a block is simulated functionally at the source level using a behavioral simulator and vectors generated by using a VHDL or Verilog test bench, for example. The simulation results can then be displayed or otherwise presented/recorded as waveforms, text or annotated onto the source files. The designer may also return to step 58 to implement a block again. Also, at this point a block may be compiled or a timing analysis performed.
Once the designer is satisfied with the simulation results, in step 62 the block is combined with other blocks and the resulting group is simulated together. In some cases, it may be useful to complete a full compilation to provide critical resource and timing information. Also, output simulation vectors from one block may become the input simulation vectors to the next block. The designer may also return to step 54 to modify the top-level block or to step 58 to implement a block again.
Next, in step 64, the entire design is simulated functionally at the source level using a behavioral simulator. Preferably, the top-level block diagram is fully specified before simulation and shows complete design connectivity. Vectors can be generated using a VHDL or Verilog test bench. Again, the simulation results can be displayed either as waveforms or annotated onto the source files. The designer may also return to step 54 to modify the top-level block or to step 58 to implement a block again. In step 66 the entire design is compiled through to a file containing the information needed to program a PLD to implement the user's design, such as to a "programming output file".
A wide variety of compile techniques may be used depending upon the type of design being created. By way of example, a few examples of compilation are presented below. For a PLD, compilation includes the steps of synthesis, place and route, generation of programming files and simulation. For a traditional integrated circuit design with a custom layout, compilation includes a layout version schematic, a design rule checker and simulations. For integrated circuit design using a high level design tool, compilation includes synthesis from a language such as VHDL or Verilog, automatic place and route and simulations. For printed circuit boards, compilation includes automatic routing, design rule checking, lumped parameter extraction and simulation. Of course, other types of compilation and variations on the above are possible. Within the context of the present invention, any of the above compile techniques may be modified in order to take into account the source level registers to be exposed.
Following compilation in step 66, in step 68 the timing checker inside the compiler is used to determine if the performance goals for the design have been met. Also, timing simulations are used to check performance details. In addition, other analysis tools such as a design profiler and/or layout editor can be used to further optimize the performance of the design. Preferably, optimization is not performed prior to step 68 because full compilation is usually required to establish the location of one or more critical paths within the design. The designer may also return to step 54 to modify the top-level block or to step 58 to implement a block again.
Next, in step 70 the device is programmed/configured using programming unit 14 and tested in the system. Again, the designer may also return to step 54 to modify the top-level block or to step 58 to implement a block again. While methodology 50 presents a top-down design process, it may also be used to support a bottom-up type methodology. Now that a general design methodology has been described by which an engineer may develop a design for a PLD, a technique for exposing internal registers of a PLD will now be discussed.
FIG. 3 is a block diagram illustrating a programmable logic device under test. Device under test 102 is any suitable programmable device as described above. Host computer 104 includes an improved EDA software tool for creating and compiling an electronic design, along with other associated software. In one specific embodiment, the EDA tool is the QUARTUS development software available from Altera Corporation of San Jose, Calif.
JTAG controller 106 is used for communication between the computer and device under test using JTAG port 108. The device also includes a test access port (TAP) controller 110 and user log blocks 112 and 114. JTAG (Joint Test Action Group) port 108 is implemented under the IEEE 1149.1 standard and is known to those of skill in the art. Using host computer 104 an engineer creates an electronic design, identifies registers of interest, complies and loads the design onto device 102. During debugging the scanned results of registers of interest are scanned out of the device via JTAG port 108 back up to the host computer for viewing by the engineer.
FIG. 4 is a flow chart describing a technique for exposing a register in a PLD. In this embodiment of the present invention, an automated "source-to-source" debugging tool is described. The tool not only allows identification of registers in the source code, but also provides results in a source code format. Contrasted with a logic analyzer which might provide results in 1's and 0's (a logic level device) the present invention is able to provide symbolic output that greatly assists an engineer in debugging a design.
Briefly, the improved EDA tool provides a design engineer with an "expose" command which allows the engineer to identify registers of interest in the source code. After recompilation, these registers (which are normally hidden inside a chip) are displayed in a symbolic format to assist with debugging. In step 202 an engineer creates an electronic design for a PLD using design steps as described above with reference to FIG. 2 (for example). Typically, an engineer has written HDL source code and is using behavior simulation to program a PLD and to run a system. As part of that effort, in step 206 the engineer tests the design and discovers some problem that is best debugged by access to an internal node or register of the PLD. By the nature of the problem, and based upon his experience, the engineer will realize which register or registers are of interest.
In step 210, the engineer indicates in any suitable fashion which registers in the source code that he is interested in having displayed. The engineer can identify these registers and convey their identification to the novel EDA tool in a variety of manners. By way of example, the engineer preferably identifies these registers by their symbolic, text based names in the source code. The engineer conveys which registers are of interest to the EDA tool by manually typing their symbolic names into a separate pop-up window in the screen, by selecting a command that queries the engineer for the names of the registers, or by highlighting and "double clicking" on the symbolic names in the source code itself. At this point, the EDA tool is aware of which registers the engineer wishes to expose and of the possible values for the register.
In step 214, the EDA tool automatically builds a scan chain for each register of interest. Preferably, separate HDL code is produced to represent the scan chain which is then linked to the engineer's existing HDL code. One technique for building a scan chain for output over a JTAG port is illustrated in FIG. 5. Preferably, the HDL code representing the scan chain uses the register names identified by the engineer, thus when the new HDL code is connected to the engineer's existing code it will be compatible.
In steps 218-226 the engineer then uses the EDA tool to recompile his design, reconfigure the PLD and run the system again for testing purposes. The steps may be performed as described above with reference to FIG. 2, or in other manners as will be known to those of skill in the art. After the new electronic design (including the additional debugging scan chains) has been downloaded to the PLD and the system run, in step 230 the EDA tool automatically scans the register to be exposed and outputs the result through the JTAG port.
The EDA tool receives the output value of the exposed register and displays a result to the engineer in step 234. The result may be displayed in many different fashions. By way of example, a simply binary result as received from the JTAG port may be displayed. Preferably, as the EDA tool is aware of the symbolic name of the register from the source code, and its data type, the EDA tool may choose to display the value in a symbolic format. This symbolic format could be a decimal representation of the register value, a hexadecimal representation, the simple name of the register, its Boolean value, a symbolic name from a case statement (if the register has been used in the source code as the switch for a case statement), a particular named state of a state machine, etc.
As the EDA tool original received the identified register from the engineer in the context of the source code, the EDA tool is aware of that context and can display a symbolic result to the engineer that is more meaningful then simply a binary value such as might be displayed from a typical logic analyzer.
At this point in time, the engineer is also provided with the option of giving a "loop" command such that step 230 is executed again and the register is scanned one more time and its result displayed again. This looping is useful if the register contents may change while the design executes. Alternatively, the engineer may insert breakpoints within the source code such that when a break point is reached, the EDA tool automatically, scans any register to be exposed and outputs its value over the JTAG port. If the engineer directs that execution begin after a breakpoint, then the register in question may be exposed again when another breakpoint is reached and the value downloaded and again displayed.
FIG. 5 illustrates an apparatus 300 for implementing step 214 of FIG. 4. In this embodiment PLD 302 to be programmed includes a JTAG port 304 and register 306 which an engineer desires to view. Step 214 implements a scan chain by inserting an additional shift register 308 into the electronic design for each register that is to be viewed. Register 306 is connected to the shift register in parallel such that the contents of register 306 may be loaded to the shift register at the same time. Once loaded, the contents of the shift register are shifted out bit-by-bit over the TDO (data out) line of the JTAG port. Of course, other similar techniques for shifting out the contents of a register through a JTAG port will be known to those of skill in the art upon the reading of this disclosure.
FIG. 6 is a sense cell which may be used to implement the shift register of FIG. 5. Sense cell 805 receives scan in data over line 834 and sends out data over scan out line 836. Data is scanned in through the cell into latch 832 and scanned out on the next clock signal when no data is being loaded. When data is being loaded, for example from a bit location in register 306, a load signal passes the bit through multiplexer 830 into latch 832 from where it may be scanned out subsequently. Upon review of this disclosure, one of skill in the art would find it straightforward to implement a series of these sense cells that would load bits from register 306 in parallel and then scan out the bits to a JTAG port. Other modifications on this scanning technique may also be used.
FIG. 7 is a flow chart describing a technique for exposing a register in an encrypted block. In the course of creating an electronic design for an integrated circuit, it is common to use a block of predefined circuitry (typically called a "core") from a vendor. These blocks are also called "intellectual property blocks" are simply "IP" blocks. These cores have a predefined functionality and are useful for incorporating into a design to create a working system more efficiently. To protect their technology, most vendors will encrypt these cores so that the user may not discover their internal workings. Thus, the user receives encrypted source code which is straightforward to incorporate into an electronic design. Any of a variety of known software tools will then decrypt this encrypted core during compilation. Unfortunately, because the internal design of the encrypted block is not visible, and because the source code is also encrypted, an engineer cannot view the contents of internal registers in order to debug the overall system. This embodiment of the present invention provides a solution to this problem.
Before a particular encrypted block is sold to a user, the vendor of the block decides (step 400) which registers are of importance or would be interesting to view for an engineer who is attempting to debug an electronic design. The vendor may select these registers on their own, or may select registers based upon input from its various customers. Once these registers are selected, the vendor creates a "debugging" file which is delivered to the customer along with the encrypted block. The "debugging" file contains the names of the registers (unencrypted) in the source code to which a user will have access. Associated with each register name is the corresponding syntax for that register, i.e., the symbolic values for the register which will aid an engineer in debugging. The prior art is deficient in this respect. For example, a prior art debugging command might result in the cryptic output:
This output indicates that a particularly important register in the design has a value of "1", but it is not immediately clear which register. After a certain amount of effort, the engineer would discover that this register is the STATUS register and the value of the numeral "1" means that the status is "wait for packet." Cryptic outputs like these in the prior art make it more difficult for an engineer to debug a design.
By contrast, this embodiment of the present invention provides more meaningful results. The debugging file from the vendor contains the source code symbolic name of the register, its data type and its various values so that the EDA tool can provide the engineer with more meaningful results. For example, considering the case of the status register, and entry in the debugging file may occur thus:
An entry in the debugging file is created for each register and of course may be more complicated. By way of example, each register may have any number of values depending upon its size. The data type may be binary, decimal, hexadecimal, Boolean, may represent a switch value in a case statement, etc. The simple creation of this debugging file creates advantages for the block vendor because the vendor does not have to change their source code, does not have to reveal their source code, and can simply identify register names and values which are to be used by the EDA tool.
Once the user receives the encrypted block and the debugging file from the vendor, the user then loads this debugging file into the EDA tool in step 401. Thus, the source code name of the register and its actual and symbolic values are incorporated into the EDA tool so that it may display meaningful debugging results to the engineer. These register names and their symbolic values may of course be loaded into the EDA tool in other manners (such as described in step 210 above) but it is preferred to use a debugging file from the vendor.
In step 402 the engineer creates an electronic design using not only their own user design, but also the encrypted block received from the vendor. One of skill in the art is well able to create their own electronic design using an encrypted block from a third party. In step 406 the engineer tests the design and discovers some problem that is best debugged by access to an internal node or register of the encrypted block of the PLD. By the nature of the problem, and based upon his experience, the engineer will realize which register or registers are of interest in the encrypted block.
In step 410, the engineer indicates in any suitable fashion which registers in the source code that he is interested in having displayed. The engineer can identify these registers and convey their identification to the novel EDA tool in a variety of manners. By way of example, the engineer preferably identifies these registers by their symbolic, text based names in the source code. The engineer conveys which registers are of interest to the EDA tool by manually typing their symbolic names into a separate pop-up window in the screen, by selecting a command that queries the engineer for the names of the registers, or by highlighting and "double clicking" on the symbolic names in the source code itself. The EDA tool may also display on screen the limited number of registers available for viewing in the encrypted block. At this point, the EDA tool is aware of which registers the engineer wishes to expose and of the possible values for the register.
In step 414, the EDA tool automatically builds a scan chain for each register of interest in the encrypted block. Preferably, separate HDL code is produced to represent the scan chain which is then linked to the engineer's existing HDL code. One technique for building a scan chain for output over a JTAG port is illustrated in FIG. 5.
In steps 418-426 the engineer then uses the EDA tool to recompile his design, reconfigure the PLD and run the system again for testing purposes. The steps may be performed as described above with reference to FIG. 2, or in other manners as will be known to those of skill in the art.
After the new electronic design (including the additional debugging scan chains) has been downloaded to the PLD and the system run, in step 430 the EDA tool automatically scans the register to be exposed and outputs the result through the JTAG port.
The EDA tool receives the output value of the exposed register and displays a result to the engineer in step 434. The result may be displayed in many different fashions. By way of example, a simply binary result as received from the JTAG port may be displayed. Preferably, as the EDA tool is aware of the symbolic name of the register from the source code, and its data type, the EDA tool may choose to display the value in a symbolic format. This symbolic format could be a decimal representation of the register value, a hexadecimal representation, the simple name of the register, its Boolean value, a symbolic name from a case statement (if the register has been used in the source code as the switch for a case statement), a particular named state of a state machine, etc.
FIGS. 8A and 8B illustrate a computer system 900 suitable for implementing any of the computers of FIGS. 1 or 3, and for hosting an EDA tool. FIG. 8A shows one possible physical form of the computer system. Of course, the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board and a small handheld device up to a huge super computer. Computer system 900 includes a monitor 902, a display 904, a housing 906, a disk drive 908, a keyboard 910 and a mouse 912. Disk 914 is a computer-readable medium used to transfer data to and from computer system 900.
FIG. 8B is an example of a block diagram for computer system 900. Attached to system bus 920 are a wide variety of subsystems. Processor(s) 922 (also referred to as central processing units, or CPUs) are coupled to storage devices including memory 924. Memory 924 includes random access memory (RAM) and read-only memory (ROM). As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPU and RAM is used typically to transfer data and instructions in a bi-directional manner. Both of these types of memories may include any suitable of the computer-readable media described below. A fixed disk 926 is also coupled bi-directionally to CPU 922; it provides additional data storage capacity and may also include any of the computer-readable media described below. Fixed disk 926 may be used to store programs, data and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 926, may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 924. Removable disk 914 may take the form of any of the computer-readable media described below.
CPU 922 is also coupled to a variety of input/output devices such as display 904, keyboard 910, mouse 912 and speakers 930. In general, an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers. CPU 922 optionally may be coupled to another computer or telecommunications network using network interface 940. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon CPU 922 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Therefore, the described embodiments should be taken as illustrative and not restrictive, and the invention should not be limited to the details given herein but should be defined by the following claims and their full scope of equivalents.
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|U.S. Classification
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|Jul 2, 2001
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOYER, BRYAN H.;FAIRMAN, MICHAEL C.;REEL/FRAME:011942/0703;SIGNING DATES FROM 20010525 TO 20010625
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|Fee payment
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text:
- Location : Bulgaria - Sofia
- Date : 20.05.2012
- Type : Show
- Pilots acro : Veso Ovcharov, Horacio Llorens
- Special thanks: ART SPACE, Sol araglders, XCOSports, PAMIFID SA.
- Music / Manu Chao - Rainin In Paradize
These days Art Space is one of the most active and positive organisations in Bulgaria - they organise various culture events in center of Sofia - the capital of Bulgaria.
The goal of the Company is to share people's experiences in different art areas (music, sports etc.) and to present it to the society and media.
Veso Ovcharov and his friend Horacio Llorens (3 x time Acro PG World Champion) made the first ever in the history of Bulgaria Acro show in the center of Sofia - over the National Palace of Culture - NDK.
They jumped together from a para trike and performed different tricks, incl. the most attractive and extreme one - Infinite Tumbling.
After the demo Veso & Horacio presented their film Infinity Himalaya.
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Jerry Jones: It's hard to beat Drew Brees with 'limited' Brandon Weeden
One week Dallas Cowboys owner Jerry Jones is trying to convince the media that his backup quarterback is the best in the business, and the next he uses him as an example of why the team was unable to win a tight game. After Drew Brees connected with C.J. Spiller for an 80-yard game-winning touchdown…Read More


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Menorahs for Hanukkah 2012
Hanukkah starts at sunset on Dec. 8, and for eight nights, your menorah will be the central focus of your family's evening celebrations. Choosing a style that best suits your taste is important, but that task is made easier with the wide variety of options available. This year's offerings run the gamut from classic and chic to elaborately artistic, and all are available at local retailers. Here are some picks for the season. -- By Lara Ewen
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20 crazy-cute pet costumes 11 Halloween events for dogs Pumpkin specialties to fall for Haunted attractions near Long Island and NYC Peek inside Long Island's most lavish homes Brian Wilson concert, more NYC weekend picks 15 new theme park rides, attractions in 2015 29 chains Long Island wants now 20 best places to see fall foliage in the Northeast 12 secrets of North Shore Animal League 23 vegetarian recipes 23 vegetarian recipes


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BackHome » Small Hotels / Inns UK Search » UK Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning » England Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning » Northern England Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning » North Yorkshire Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning » Malton Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning
Small Hotels & Inns with Flying, Hang Gliding, Paragliding, Hot Air Ballooning Alford
Small hotels & inns with flying, hang gliding, paragliding, hot air ballooning in Alford, such as Burythorpe House, are featured underneath. Experienced in flying pursuits, or brave enough to give them a try? Hang gliding, paragliding and ballooning can be enjoyed whilst staying at any of these small hotels and inns.
Burythorpe House
Burythorpe, Malton 69.2 miles away
Burythorpe House, a former gentleman's residence built around 1750, is both family owned and managed and stands in a beautiful rural location with wonderful views over the surrounding countryside. All the rooms in the house have ample bathrooms and... more
The Cavendish Hotel
Church Lane, Baslow 74.5 miles away
Gliding fom Hucklow
The Cavendish Hotel exudes a quiet elegance and is decorated with an extensive collection of original artwork, antiques and charming furnishings. Its a calm tranquil place and all the bedrooms overlook Chatsworth Estate in the Peak District and are... more
Samuel Fox Country Inn
Stretfield Road, Bradwell, Hope Valley 79.6 miles away
Round off a blow-out meal at the Samuel Fox at Bradwell in Derbyshire, a restaurant serving contemporary local dishes, by taking a few steps and retreating to one of their four chic and comfortable rooms. Unpack your bags surrounded by pretty... more
Dial House Hotel
High Street, Bourton-on-the-Water 124.5 miles away
Hot air ballooning
A brilliant blend of old and modern, The Dial House Hotel offers an archetypal country hotel experience. Set in idyllic surroundings and built from golden Cotswold Stone it dates back to 1698 and is the very essence of English style. The bedrooms are... more
The Crab and Boar
Wantage Road (B4494), Chieveley, Newbury 139.5 miles away
Hot air ballooning
Set in the heart of Berkshire countryside, The Crab & Boar is a lovely country pub with rooms offering British cuisine, free Wi-Fi and a large car park. The 14 bedrooms feature antique furnishing, luxury throws, Egyptian cotton linen, flat screen... more
The Bear Hotel
41 Charnham Street, Hungerford 145.5 miles away
The Bear Hotel is one of England's oldest coaching inns and has been the focus of hospitality since 1464 in the quintessentially English market town of Hungerford, in the Royal County of Berkshire. We are situated in the Heart of the North Wessex... more
Wilton Court Restaurant with Rooms
Wilton Lane, Wilton, Ross-on-Wye 148.0 miles away
Wilton Court Restaurant with rooms has been carefully refurbished reflecting its 16th century origins and features many objects d'art, rugs and various collectables from the Middle and Far East creating an oasis of comfort and tranquility. In an... more
Latest Special Offers & Deals for Wilton Court Restaurant with Rooms
The White Horse
1 High Street, Chilgrove, Chichester 166.7 miles away
Flying at Goodwood
Perched at the foot of the stunning South Downs, The White Horse in Chilgrove is the perfect place to enjoy the peace and tranquillity of the English countryside. The lovely inn won the 'Best Pub' of the year at the GG Food & Drink awards and... more
Latest Special Offers & Deals for The White Horse
- Spoil Yourself Sundays
- To view the full details of all (1) Special Offers & Deals for The White Horse, click here
The Royal Oak
Pook Lane, East Lavant, Chichester 170.1 miles away
Flying, Hang Gliding, Paragliding & Hot Air Ballooning available at Goodwood please enquire
Opt for the 200-year-old Royal Oak, two miles from historic Chichester in West Sussex, and you're in glorious Goodwood country. The hotel has just eight beautifully-decorated rooms, featuring plump down duvets, Egyptian cotton sheets, fireplaces,... more
The Lamb Inn
Hindon 177.7 miles away
Hot air ballooning
Located in the centre of beautiful village of Hindon which can be found in the West Wiltshire Downs, an area of Outstanding Natural Beauty, and is also close to one of the wonders of the Ancient world Stonehenge. The Lamb would have been trading... more
Compton House
Townsend, Axbridge 184.6 miles away
Paragliding, hot air ballooning
A showcase of Georgian splendour, Compton House wouldn't look out of place in a lavish period drama. Boasting mullioned windows, flag stones and original fireplaces, this Grade II listed country house, near the medieval town of Axbridge in Somerset,... more
The King John Inn
Tollard Royal, Salisbury 184.8 miles away
Flying at Compton Abbas Airfield, Virgin Balloon flight
The King John Inn is a beautiful country inn situated in the scenic village of Tollard Royal in rural Wiltshire. The eight en-suite bedrooms combine modern comfort with rustic elegance and feature luxurious linen, espresso machines, flat-screen... more
Travel Ideas containing The King John Inn
The Museum Inn
Farnham, Blandford Forum 185.6 miles away
Virgin Hot Air Ballooning, Flying at Compton Abbas Airfield
The Museum Inn is a superb 17th Century country inn situated in the delightful village of Farnham, Dorset, on the glorious Cranborne Chase, an Area of Outstanding Natural Beauty and a renowned countryside pursuit's destination. The pub has eight... more
Loch Kinord Hotel
Ballater Road, Dinnet, Royal Deeside 292.6 miles away
Calling nature lovers and leisure seekers. Head to the unspoilt Royal Deeside and stay at Lord Kinord Hotel, with the Cairngorm Mountains looming in the background and green glens carpeting the surrounding land – it's a dream for the outdoorsy. The... more
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Nearby Towns to Alford with Small Hotel / Inn listings: Alford | Anderby Creek | Sutton-on-Sea | Spilsby | Skegness | Louth | Horncastle | Binbrook | Tetney | Woodhall Spa
'Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning' by County : England: Southern England: Berkshire | Central England: Derbyshire | Southern England: Dorset | Central England: Gloucestershire | Herefordshire | Northern England: North Yorkshire | South West England: Somerset | South East England: West Sussex | Southern England: Wiltshire | Scotland: Central, East & North East Scotland: Aberdeenshire UK Small Hotels & Inns with Flying, Hang gliding, Paragliding, Hot Air Ballooning
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text:
Oven-Roasted Meatballs with Spaghetti
Weeknight-fast and diet-friendly, these extra-light turkey meatballs can even be made and frozen up to one month ahead.
Total Time:
Level: Moderate
Serves: 6
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- 2 slice firm white bread
- 1 small zucchini
- 1 large egg white
- ⅓ c. Romano or Parmesan cheese
- 1 clove garlic
- 1 tsp. salt
- ¼ tsp. ground black pepper
- 1 lb. lean ground turkey breast
- 1 package whole-wheat spaghetti
- 1 jar pasta sauce
- Chopped parsley
- Preheat oven to 450 degrees F. In large bowl, with hand, mix bread, zucchini, egg white, Romano, garlic, salt, and pepper until evenly moistened. Add ground turkey and mix just until evenly combined.
- With wet hands, shape turkey mixture into twelve 2-inch meatballs. Place meatballs in 15 1/2-inch by 10 1/2-inch jelly-roll pan and bake 18 to 20 minutes or until cooked through and lightly browned.
- Meanwhile, heat large saucepot of salted water to boiling over high heat; add spaghetti and cook as label directs.
- While spaghetti is cooking, in 2-quart saucepan, heat sauce over medium-low heat until simmering, stirring occasionally.
- Drain spaghetti. Serve spaghetti with sauce and meatballs. Sprinkle with parsley if you like.
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CBT preview made in the shade
High on Bearden Hill historic Knollwood, an antebellum mansion, was a dramatic setting for the Clarence Brown Theatre Society's Champagne Preview event on a Friday evening past.
More than 100 members of the Society and their guests had a sneak preview of vignettes and songs from productions scheduled for the 2008-09 season. There were champagne toasts and appreciative applause for the teaser taste of what is to be.
Knollwood is now the executive headquarters for The Schaad Companies, host sponsor for the evening and for all CBT productions during the coming season. Schaad Companies CEO Jennifer Banner expressed her pleasure at the opportunity to serve for the season.
Townes Lavidge Osborn and Sheena McCall planned the event for the theater aficionados.
Knollwood has enjoyed a rich domestic heritage but now serves a commercial purpose. Rooms long designated for family living are handsomely appointed offices and conference rooms, but in their renovation are still charming reminders of a day past. James Schaad, Patrick and Lisa Schaad, and Michael Schaad enjoyed showing guests around Knollwood.
Attending with her mother, Lydia Pulsifer, was Allison Pulsifer whose great-great-great-grandfather Edington was born and reared at Knollwood.
Its once unfettered pinnacle view has been compromised by "progress." Businesses now dot the hillside of the once-vast acreage, but Knollwood retains its dignity and remains a special place.
Tall trees shaded the patio where CBT Society members and guests were seated at tables for dining from Sunspot and By the Tracks Bistro provided by Randy Burleson; the champagne was from Bob and Karen Gilbertson and roses from Judi Starliper.
Providing the theatrics staged on Knollwood's side porch were Tracey Copeland-Halter singing from the Fats Waller musical revue "Ain't Misbehavin," the season's opener, accompanied on the piano by CBT veteran Jimmy Brimer; Jessica Ripten and Jen Ballard performing a scene from a romantic comedy, "The Triumph of Love"; and Jed Diamond as Scrooge in a sketch from "A Christmas Carol," a role he played to sold-out audiences last season that will be repeated this year; and Clarence Brown's Artistic Director Calvin MacLean on guitar with vocalist Quentin Cason performing "Pinball Wizard" from "Tommy" - all to be mounted on the Clarence Brown stage.
The season will also include CBT productions to be seen in the round on the Carousel Theater stage: "The Marriage of Bette and Boo," "Love's Labour's Lost," "Copenhagen," "Flyin' West," and "The Secret Rapture."
It was announced that MacLean, there with his wife Rebecca, will be leading the Society's annual New York City theater trip March 13-15.
Attending the event were UT's Dean of Arts and Sciences Bruce Bursten, Carol Mayo Jenkins and Tom Cervone, Allen and Lisa Carroll, Bob and Margie Parrott, Robyn and Joe Ben Turner, Peggy, Ron, Rachel and Clare Turner, Bob and Diana Samples, Dave and Alice Torbett, Barbara Apking, Channing and Whitney Dawson, John and Donna Dempster, Judith Foltz, Brian Salesky, Jackie Wilson, Suzanne Carriere, Tom and Melanie Wood and Georgiana Vines.
Also, Peter Acly and Ellen Robinson, John and Patty Purvis, William and Sherry Pender, Stephanie and Steve Hess, John Neely and Mary Stewart, Shirley Nash-Pitts, Georgia and Lynn Blake, Alan Solomon and Andrea Cartwight, Kay Stout, Kay Johnson, Henrietta Grant, Myron and Jayne Ely, Joe and Carol Pelliccia, Allen and Lisa Carroll, Finley and Kim Hudgens, and William and Julie Hoppe.
n On that same evening Jim Ogle was host for the 10th annual "Picnic at Pittman for the Park" at his Everts Cove home. He was joined by co-hosts Phillip and Vicky Fulmer in welcoming guests to this annual event that benefits The Friends of the Smokies.
Following barbecue and a silent auction, everyone moved to the back porch of Jim's home for a spirited live auction conducted by auctioneer Marty Loveday. Marty was assisted by UT assistant football coaches Dan Brooks and Steve Caldwell, who encouraged the crowd to dig deep in their pockets to support the Great Smoky Mountains National Park.
There were some big spenders for popular items on the block. Winning bids and bidders with hefty price tags were Harry and Sam Valentine, who purchased a Robert Tino watercolor, "By the Light of the Moon"; Jim and Carol Muszik, winning bidders for a UT-UCLA weekend package with airfare, game tickets and lodging at the historic chateau Marmont on Sunset Boulevard; Linda Ogle, who bought a UT-Georgia game weekend package with game tickets, lodging at the Four Seasons in Atlanta and a limousine to and from the game in Athens. She also was high bidder for an orange and white golf cart.
Sid and Jo Blalock purchased a dinner for six at Blackberry Farm.
This year's auction raised more than $100,000 for the Smokies, and in the past 10 years has raised more than $750,000.
Among the attendees were Park Superintendent Dale Ditmanson and wife Suzanne, Steve and Donna Casey, Cheryl Houston, Tom and Bev Brosch, Missy Kane and husband Jim Bemiller, Jack and Catherine Burgin, Robert and Mary John Tino, Joe and Tonya Keener, Paul and Judith Moody, Sally Cleveland and Susan Krisle, John Waters, Geoff and Pat Wolpert, Jack Williams, Jody and Sam Curtis, Mark and Jennifer Haub, Kevin and Carolyn Kirkland, Morton and Becky Massey, and Jim Hart, president of Friends of the Smokies.
n Before spring turned into our recent summer, The Friends of the Smokies had one of its major fund-raising events at the Swag Country Inn near Waynesville, N.C. The Swag is owned by board members Deener and Dan Matthews.
The couple left Knoxville, where Dan served as rector of St. John's Episcopal Church (now Cathedral), to go to New York where he was rector of Trinity-St. Paul's Chapel Church on Wall Street, serving for 17 years there before retiring in 2004.
In the 12 years since its inception, the Swag weekend, underwritten by the Matthews and other loyal park supporters, has raised more than $600,000 to provide support for park needs. For attendees the weekend is always a time to enjoy the beauty of the national park and to share fellowship of others who appreciate its grandeur.
Welcoming the guests were Mark and Kristin Williams, Gary and Sandy Wade, Dale and Suzanne Ditmanson, and Kevin and Cyn Fitzgerald.
Among the first to arrive were Jim and Natalie Haslam, Jim and Kay Clayton, Jack Williams, Jean Ogle of Gatlinburg, Bill and Donna Cobble of Friendville, John and Joan Dickson of Asheville, N.C., and Melle Dalton of Columbia, S.C.
Following a delicious Swag dinner, the guests were entertained by singer-songwriter-attorney Doug Peters, Mark Williams, a master banjo picker, and Jack Williams.
The next day brought a visit to Thistlecroft, the beautiful home of Hal and Marji Roberts on nearby Utah Mountain.
After a tour of the house and extensive grounds, they returned for an entomology exercise conducted by park ranger scientist Keith Langdon. Jim and Kati Blalock and Jeff and Pat Wolpert had success in capturing specimens via "bug-sucking" method, and there was a falconry lesson by Black Mountain falconer Charles McKenzie.
A fundraising auction followed dinner at the Swag. Robert and Mary John Tino arrived bearing items for the auction. Bill and Kay Stokely, Jim Sams, and Doug and Kathy Peters brought auction treasures as well. Entertainment that evening was by 12-year-old bluegrass singer Logan Murrell of Knoxville who got rave reviews.
U.S. Rep. Heath Shuler of North Carolina, former UT football star, came on Sunday with his wife Nikol, and gave an inspiring talk at the Rev. Matthews' morning service. Following the service there was a presentation of black and white photography by John Dickson.
Among others attending were Swag weekend were Cathy Ackerman and Tommy Walker, Julie and Bob Murrell, Robin and DeAnn Turner, Earl and Margit Worsham, Lauren Gass, and Sarah Weeks. Elaine Stewart represented the Friends' Waynesville, N.C., office.
Barbara Aston-Wash may be reached at firstname.lastname@example.com or 865-523-7991.


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New product releases. Special Promotions and Giveaways. Event info. Athlete Updates.
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By Gladys Edmunds, Special to USA TODAY
Dear Gladys,
I am in my own business and I love it. I would like some ideas on how to keep my expenses in check. My friend says that thinking in terms of cutting costs and saving money is to emphasize what you lack or need. He says that focusing on the idea of wealth is a better path to success. I don't want to compromise my business. So how can I run my business on a budget while maintaining thoughts and feelings of wealth?
Anthony P.
When I was a child I took the monthly magazines and cut out pictures of expensive things that I hoped to own one day and put them into a shoe box. My grandmother called it having a champagne mentality on a beer budget.
In that box I had created a vision for my future. I believe that your friend is suggesting that you create a mental vision for your future business success.
One of the most important things to consider is to do something each day that adds value to your company. One way to do this is to determine exactly how much you need to earn in the course of a day to break even and make a point to exceed that amount daily. Any business can do this. If you find that you are just $5 over your break-even point, you are making progress. To achieve this you will need to take a hard look at how to increase your sales.
As for expenses, you usually get what you pay for. When you need something, make quality purchases. I know a couple who owns a landscaping business. Instead of buying top-rate equipment they insist on buying cheaper, second-hand lawn mowers. It seems that year after year the equipment breaks down at the height of the cutting season and they are forced to rent equipment at a steep price. They would do better to buy top quality mowers that are built to last.
Don't get caught up in the credit card system for business purchases. I frequently talk to a man who owns a floral shop and he has a habit of putting supplies on a high-interest credit card. The last time I spoke with him the credit card company was charging 21% and he owes more than $10,000. It was not hard for this to happen. He also used the credit card to pay for attending conventions and workshops. Although it was for a good purpose it's hard to think in terms of wealth and success when a large percentage of your payment is going toward high interest rates.
If you need money for educational purposes or supplies, talk to a lender about a low-interest loan.
If you want to think wealth and success while you operate on a budget, then do as the wealthy do and don't waste either your time or your money. Watch how you spend both. Invest in things that bring real value to your company.
Also do the things that make you feel successful and rich, no matter how simple it might be. Whatever it is, indulge in it. I love those gold paper clips. They usually come to me holding papers together from someone who is sending a large bill, like my CPA, lawyer or broker. I notice that they sit in a nice little gold dish on my banker's desk. They seem to pop up in places where large sums of monies are transacted. Stop by Office Depot and get yourself a couple of boxes for your desk.
Search yourself to see what makes you feel like you are already successful and wealthy and do that. However, don't overlook that what it takes to really reach success and riches in a business is the desire to succeed coupled with action.
Gladys Edmunds' Entrepreneurial Tightrope column appears Wednesdays. Click here for an index of her columns. As a single, teen-age mom, Gladys made money doing laundry, cooking dinners for taxi drivers and selling fire extinguishers and Bibles door-to-door. Today, Edmunds is founder of Edmunds Travel Consultants in Pittsburgh and author of There's No Business Like Your Own Business, a six-step guide to success published by Viking. Her website is www.gladysedmunds.com. You can e-mail her at firstname.lastname@example.com.
Conversation guidelines: USA TODAY welcomes your thoughts, stories and information related to this article. Please stay on topic and be respectful of others. Keep the conversation appropriate for interested readers across the map.


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Company Overview of Meditech Pharmaceuticals Inc.
Company Overview
As of March 31, 2005, Meditech Pharmaceuticals Inc. was acquired by Bazhou Deli Solar Energy Heating Co. Ltd. Meditech Pharmaceuticals, Inc., a development stage company, operates as a drug development company. It focuses on the areas of research, development, and marketing in the biomedical industry, with an emphasis on anti-infective drugs. The company is developing two patented compounds, including MTCH-24 and Viraplex, which showed positive test results for treatment of various enveloped viruses. Meditech is also developing anti-infective drugs for human, veterinary, and agricultural applications. The company was founded in 1982 and is based in Scottsdale, Arizona.
2591 Dallas Parkway
Suite 102
Frisco, TX 75034
United States
Founded in 1982
3 Employees
Key Executives for Meditech Pharmaceuticals Inc.
Meditech Pharmaceuticals Inc. does not have any Key Executives recorded.
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To contact Meditech Pharmaceuticals Inc., please visit www.mdch.net. Company data is provided by Capital IQ. Please use this form to report any data issues.
Our data partners will research the update request and update the information on this page if necessary. Research and follow-up could take several weeks. If you have questions, you can contact them at firstname.lastname@example.com.


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David Bowie
"Sometimes I'm so glad, so glad"
Released this day (August 20th) in 1965 was the Davy Jones 45, You've Got A Habit Of Leaving.
Baby Loves That Way was on the flip and both songs were composed by the young Jones before he Bowied-up for his next release the following year.
Produced by Shel Talmy (who was producing The Who and The Kinks at the time), and backed by The Lower Third, the influence of Townshend and his gang is more than apparent on both sides of this disc.
The 18-year-old mod is pictured here around the time of the release, shadowed by his older brother Ziggy who copped the same
"And he was alright, the band was altogether"
Following on from last week's focus on the Ziggy Stardust album, this week we're looking at, and listening to, the live album that sprang from the first American tour in the autumn/fall of 1972 in support of Ziggy Stardust.
October 20 1972 was the first of two dates at the Civic Auditorium, in Santa Monica, Los Angeles, California. The show was broadcast live by local station KMET-FM, and quickly became the first and one of the most popular live Bowie bootlegs of all time.
Santa Monica was released officially by EMI thirty six years later in
"Nothing's gonna touch you in these golden years"
Golden Years will be the last of the 40th anniversary 7" picture discs for 2015. Originally released on November 21 1975, the single had a lot to live up to.
As we said in our previous item, 1975 was a good year for Bowie chart action. Fame had given Bowie his first #1 Stateside and the Space Oddity rerelease became Bowie's first UK #1.
The UK press advert for Golden Years reflected this success while making the following bold prediction:
October No. 1...Fame...USA
November No. 1...Space Oddity...UK
December No.
October No. 1...Fame...USA
November No. 1...Space Oddity...UK
December No.
"Commencing countdown, engines on"
No prizes for guessing the next limited David Bowie 7" picture disc will be the 40th anniversary edition of Space Oddity.
Of course, we're not talking about the anniversary of the original 1969 issue on Philips, which gave Bowie his first Top 5 hit on the UK singles chart, or even the 1973 US release which reached #15 on the Billboard Hot 100 in 1973. No, we're celebrating the 1975 RCA re-issue which furnished Bowie with his first ever UK #1 single.
Originally issued in the UK on Friday September 26th 1975, the single followed hot on the heels of Bowie's
"There's a sailor who sings"
A limited edition pressing of David Bowie's Man Of Words/Man Of Music album is to be issued on blue vinyl, alongside classic versions of Amsterdam and My Death as a limited edition orange vinyl 7" single.
The records are being released via Parlophone to celebrate the opening of the V&A's David Bowie is at the Groninger Museum, Groningen in the Netherlands, on December 11th, 2015. The records are exclusive to the exhibition. (http://smarturl.it/DavidBowieGoingDutch)
Man Of Words/Man Of Music was the US version of the 1969 David Bowie album on Mercury, aka Space


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Relive the championship win . .
Saturday 29 August
SCW Grand Final Game 2
Ringwood Vs Hume City @ 6:00pm
Sunday 30 August
SCW Grand Final Game 3
Ringwood Vs Hume City @ 2:00pm
If you have ever played Representative Basketball in Victoria, you will know all about the October try-outs where kids flock to elite Clubs and battle for a spot ...
The Ringwood Hawks are inviting enquiries from all interested athletes for the 2016 Ringwood Hawks BigV Youth Women's and Youth Men's Championship Teams.


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You'd love to root, root, root for the home team, but cost-prohibitive tickets keep you root, root, rooting in couch cushions for extra change. Swap the sofa for stadium seating with today's deal from ScoreBig.com-- as seen in The Wall Street Journal, Forbes, and TechCrunch. Pay $10 for $40 to spend on live event tickets at serious discounts. This site offers thousands of great, unsold seats -- from front row to the rafters -- to some of the best shows the Pittsburgh area has to offer. Be close to the Buccos action at PNC Park or watch the Pens march their way to the playoffs at CONSOL Energy Center -- heck, you can even head to the Petersen Events Center for a show. Once you choose your event and seating area, pick your price, and ScoreBig will let you know instantly if your offer is accepted. If it is accepted, your ticket is 100% guaranteed and is yours without any fees or shipping charges; and if it's not accepted, simply offer again. Before you know it, you'll be singing Take Me Out to the Ball Game -- because if you don't get out of the house, it's a shame.
Want more? Check out ScoreBig.com on Facebook.
PAID VALUE EXPIRES ON October 9, 2020
PROMOTIONAL VALUE EXPIRES ON September 30, 2012
$40 to Spend on Sports, Concert, and Theater Tickets
- from $10


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Join us at the Western Addition Branch Library as Office of Small Business Administration representative Martha Yanez gives a talk on how to be in compliance with the City and County of San Francisco if you want to start a food truck! Food trucks have become a mainstay in San Francisco and throughout the Bay Area. Learn the basics you will need to have all your business permits in place!
All Things Business: An interactive series for the practical entrepreneur.
Upcoming Events
- Will Writing Workshop
- Wednesday, October 7, 2015, 6:00 pmMain Library, Learning Studio
- All Things Business
- Thursday, October 8, 2015, 10:00 amMain Library, Computer Training Ctr. 5th Floor
- Small Business Ownership and You!
- Thursday, October 8, 2015, 6:00 pmMain Library, Learning Studio
Upcoming Classes
- Finances for Small Business Owners
- Tuesday, October 13, 2015, 6:30 pmNorth Beach, North Beach Meeting Room
Current Exhibits
- Internal Reflections
- Through Sunday, November 15, 2015Main Library, African American Center
*Funded by Friends of the San Francisco Public Library.


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Book your room at The Soco Hotel - All Inclusive
Please enter your travel dates.
Get an overview of this hotel4-star beach resort with a full-service spa
Located in Hastings, this beachfront resort is on the boardwalk and within a 15-minute walk of Surf in Barbados Surf School and Accra Beach. Barbados Museum and Historical Society and Lanterns Mall are also within 1 mi (2 km).
Resort Features
Spend the day relaxing on the beach or pampering yourself at The Soco Hotel - All Inclusive's full-service spa.
Room Amenities
All 24 rooms feature comforts like pillowtop beds and premium bedding, while conveniences include sofa beds and refrigerators. Free WiFi and balconies are standard, as are flat-screen TVs with cable channels.Information missing or incorrect? Tell us!
Hotel Amenities
All-Inclusive Details
This resort is all-inclusive. Onsite food and beverages are included in the room price (some restrictions may apply).
Gratuities and taxes
Taxes are included.
Food and beverages
- All meals, snacks, and beverages included
- Room service during certain hours
Not included
- Golf green fees
- Use of golf cart
- Use of golf equipment
- Miniature golf
- Motorized water sports
- Sailboats
- Scuba-diving certification
- Scuba-diving excursions
- Scuba-diving lessons
- Snorkeling excursions
- Snorkeling gear
- Tennis lessons
- Tennis racquets
- Windsurfing equipment
- Premium food items
- Premium and/or non-domestic beverages
- Bottled wine
- Bottled liquor
- Minibar
- Room service
- Airport transfers
- Childcare
- Laundry/dry cleaning services
- Spa/beauty facilities and services
- Activities and services offered by independent operators
- Offsite tours
- Transportation to offsite activities
Hotel Amenities
The Soco Hotel - All Inclusive is an all-inclusive resort. Room rates include meals and beverages at onsite restaurants and bars. Other items and amenities, including taxes and gratuities, and access to recreational activities and entertainment may also be included. Additional charges may apply for meals at some restaurants, special dinners and dishes, certain beverages, and other amenities.
The Soco Hotel - All Inclusive features a full-service spa and an outdoor pool. The resort offers a restaurant. A bar/lounge is on site where guests can unwind with a drink. A complimentary breakfast is offered. High-speed wireless Internet access is complimentary.
This 4-star property offers access to a business center. This Art Deco resort also offers a rooftop terrace, spa services, and tour/ticket assistance. For a surcharge, a roundtrip airport shuttle (available 24 hours) is offered to guests. Onsite self parking and valet parking are complimentary. A total renovation of this property was completed in April 2013.
The Soco Hotel - All Inclusive has designated areas for smoking.
- 24-hour front desk
- Airport transportation (surcharge)
- Babysitting or childcare (surcharge)
- Bar/lounge
- Beach sun loungers
- Beach towels
- Business center
- Designated smoking areas
- Dry cleaning/laundry service
- Express check-in
- Express check-out
- Free breakfast
- Free parking nearby
- Free self parking
- Free valet parking
- Free WiFi
- Full-service spa
- Number of buildings/towers - 1
- Number of floors - 4
- Outdoor pool
- Porter/bellhop
- Restaurant
- Rooftop terrace
- Free shopping center shuttle
- Spa services on site
- Spa treatment room(s)
- Total number of rooms - 24
- Tours/ticket assistance
- Wedding services
- Year Built 2013
Family Friendly Amenities
- Babysitting or childcare (surcharge)
- DVD player
- Free Wi-Fi
- Outdoor pool
- Refrigerator
- Sofa bed
Room Amenities
- Air conditioning
- Balcony
- Bathrobes
- Blackout drapes/curtains
- Cable TV service
- Climate control
- Coffee/tea maker
- Free toiletries
- Connecting/adjoining rooms available
- Cribs/infant beds available
- Daily housekeeping
- Desk
- DVD player
- Flat-panel TV
- Free local calls
- Free WiFi
- Hair dryer
- In-room massage available
- In-room safe (laptop compatible)
- iPod docking station
- Iron/ironing board
- Phone
- Pillowtop mattress
- Premium bedding
- Private bathroom
- Refrigerator
- Room service (limited hours)
- Shower/tub combination
- Sofa bed
- Turndown service
Where to Eat
Guests are offered a complimentary continental breakfast.
Restaurant at SoCo - This beachfront restaurant specializes in Caribbean cuisine and serves breakfast, lunch, and dinner. Guests can enjoy alfresco dining (weather permitting).
Bar at SoCo - This bar is located on the beach.
Room service (during limited hours) is available.
Nearby Things to Do
The recreational activities listed below are available either on site or nearby; fees may apply.
Spa Services
The Spa at Soco has massage/treatment rooms, couples treatment room(s), and outdoor treatment areas. Massages are available on the beach and in the spa; other services include deep-tissue massages, hot stone massages, and sports massages. A variety of treatment therapies are provided, including aromatherapy, Ayurvedic, and hydrotherapy.
The spa is open daily.
Hotel Policies
Check-in time starts at 3 PM
Check-out time is noon
Payment types
Children and extra beds
- Children are welcome.
- Cribs (infant beds) are available.
You need to know
Extra-person charges may apply and vary depending on hotel policy.
Government-issued photo identification and a credit card or cash deposit are required at check-in for incidental charges.
Special requests are subject to availability upon check-in and may incur additional charges. Special requests cannot be guaranteed.
No elevators
No pets or service animals allowed
Noise-free rooms not guaranteed
We should mention
This property offers transfers from the airport (surcharges may apply). Guests must contact the property with arrival details 24 hours prior to arrival, using the contact information on the booking confirmation. Reservations are required for massage services and spa treatments. Reservations can be made by contacting the resort prior to arrival, using the contact information on the booking confirmation. Only registered guests are allowed in the guestrooms. The property has connecting/adjoining rooms, which are subject to availability and can be requested by contacting the property using the number on the booking confirmation. No pets and no service animals are allowed at this property.


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Christ walked on water, and Moses parted the Red Sea. Impressive as those feats were, they have to retreat when compared with an achievement pulled off by Newsweek columnist Jonathan Alter on MSNBC's "Rachel Maddow Show" on Tuesday.
Ms. Maddow asked Mr. Alter a question, to which Mr. Alter replied he had not heard her because he was not getting any audio. He said, however, that he would answer the question anyway. He went on to give an approximately three-minute answer to a question he said he had not heard.
I wonder how often Mr. Alter also reports news he has not actually heard?
Springfield, Va.


text:
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Surya Kingston KGT2002 Area Rug
|Ships Within
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|Collection: Surya Kingston
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|Country of Origin: China
|Color(s): White >> Secondary Color(s):Beige,Black,Mocha,Black,Tan,Mocha,Gray,Tan,Mocha,Chocolate,Beige,Burgundy,Taupe - Pantone Colors: 19-0000,12-0605,14-1116,16-1333,16-1310,18-1018,19-0815,19-1314,18-1048,17-1224,19-1320,19-1331,15-4706.
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|The Surya Kingston KGT2002 by Surya is sometimes listed with the following brand codes: KGT2002-3656, KGT2002-268, KGT2002-58. Also, the following UPC codes: 764262679335, 764262679519, 764262679397
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- Surya Kingston KGT2003
- Surya Kingston KGT2005
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