text:
Juventus FC v AC Milan - TIM Cup
Urby Emanuelson of AC Milan is tackled by Leonardo Bonucci of... News PhotoA.C. Milan,Club Soccer,Coppa Italia,Horizontal,Italy,Juventus F.C.,Juventus Stadium,Leonardo Bonucci,Match - Sport,Motion,Soccer,Soccer League,Soccer Player,Sport,Tackling,Turin,Urby EmanuelsonPhotographer Valerio PennicinoCollection: Getty Images Sport 2013 Valerio PennicinoTURIN, ITALY - JANUARY 09: Urby Emanuelson (L) of AC Milan is tackled by Leonardo Bonucci of Juventus FC during the TIM cup match between Juventus FC and AC Milan at Juventus Arena on January 9, 2013 in Turin, Italy. (Photo by Valerio Pennicino/Getty Images)


text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 8, 2011
|Priority date
|Apr 7, 2006
|Fee status
|Also published as
|Publication number
|Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
|Original Assignee
|Micron Technology, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (205), Non-Patent Citations (35), Referenced by (5), Classifications (12), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to, and incorporates by reference the entire disclosure of the following: U.S. patent application Ser. No. 11/214,544 (filed 29 Aug. 2005; U.S. patent application Ser. No. 11/219,067 (filed 1 Sep. 2005); U.S. patent application Ser. No. 11/366,212 (filed 2 Mar. 2006); and U.S. patent application Ser. No. 11/367,020 (filed 2 Mar. 2006).
The present invention relates generally to integrated circuit fabrication, and more specifically to simplified processes for forming pitch doubled integrated circuit features.
Integrated circuits are continuously being made smaller as demand for portability, computing power, memory capacity and energy efficiency in modern electronics grows. Therefore, the size of the integrated circuit constituent features, such as electrical devices and interconnect line widths, is also decreasing continuously. The trend of decreasing feature size is evident in memory circuits or devices such as dynamic random access memory ("DRAM"), flash memory, nonvolatile memory, static random access memory ("SRAM"), ferroelectric ("FE") memory, logic gate arrays and so forth.
For example, DRAM typically comprises millions of identical circuit elements, known as memory cells. A typical memory cell consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one binary digit ("bit") of data. A bit can be written to a memory cell through the transistor and read by sensing charge on the reference electrode of the storage capacitor. By decreasing the sizes of these constituent electrical devices and the conducting lines that interconnect them, the sizes of the memory devices incorporating memory cells can likewise be decreased. In similar fashion, the storage capacities of these devices can be increased by fitting more memory cells into the memory devices.
As another example, flash memory (for example, electrically erasable programmable read only memory or "EEPROM") is a type of memory that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. The memory cells include a floating gate field effect transistor capable of holding a charge. The data in a memory cell is determined by the presence or absence of charge on the floating gate. The cells are usually grouped into sections called "erase blocks." The memory cells of a flash memory array are typically arranged into a "NOR" architecture (in which each memory cell is directly coupled to a bit line) or a "NAND" architecture (in which memory cells are coupled into "strings" of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access). The memory cells within an erase block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
As is evident from the examples provided here, memory devices typically include large patterns or arrays of electrical devices and conductors that are used to interconnect the electrical devices. The "pitch" of such a pattern is defined as the distance between an identical point in two neighboring features in the pattern. These features are typically defined by openings in, and are spaced apart from each other by, a material such as an insulator or conductor. Thus, pitch can be understood as the sum of the width of a feature and the width of the space separating that feature from a neighboring feature.
In one embodiment of the present invention, a method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
In another embodiment of the present invention, a method of forming a memory device comprises forming a plurality of mandrels over a substrate in an array region of the memory device. The mandrels optionally comprise a photoresist material. The mandrels are separated by exposed portions the substrate. The method further comprises depositing a spacer material over the mandrels, over the exposed portions of the substrate, and over a peripheral region of the memory device. The method further comprises depositing a peripheral mask over the spacer material in the peripheral region of the memory device. The method further comprises anisotropically etching the spacer material from exposed horizontal surfaces. Spacer material is left remaining (a) on vertical sidewalls of the mandrels in the array region, and (b) between the substrate and the peripheral mask in the peripheral region.
In another embodiment of the present invention, a method of forming an integrated circuit comprises forming a plurality of mandrels on a hard mask layer in an array region. The mandrels comprise a photoresist material. The method further comprises depositing an oxide material over the array region and over a peripheral region that surrounds the array region. The oxide material covers the plurality of mandrels. The method further comprises forming a pattern of photoresist material over the oxide material in the peripheral region. The method further comprises anisotropically etching the oxide material from horizontal surfaces in the array region. The method further comprises removing exposed photoresist material from the array region and the peripheral region after anisotropically etching the oxide material.
In another embodiment of the present invention, a method of integrated circuit fabrication comprises using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer in an integrated circuit array region. The mandrels comprise a photoresist material. The method further comprises forming a pattern of spacers around the plurality of elongate mandrels. The pattern of spacers have a pitch that is smaller than a minimum resolvable pitch of the lithographic technique. The spacers are formed from an oxide material that is deposited at a temperature less than about 100� C.
In another embodiment of the present invention, a partially formed integrated circuit comprises a substrate. The partially formed integrated circuit further comprises a hard mask layer positioned over the substrate. The partially formed integrated circuit further comprises a plurality of spacer loops that are formed directly over the hard mask layer, and that are at least partially positioned in an array region of the partially formed integrated circuit. The partially formed integrated circuit further comprises a mask at least partially defined in a peripheral region of the partially formed integrated circuit, wherein the mask is also directly formed over the hard mask layer.
Exemplary embodiments of the integrated circuits and integrated circuit fabrication techniques disclosed herein are illustrated in the accompanying drawings, which are for illustrative purposes only, and which are not necessarily drawn to scale. The drawings comprise the following figures, in which like numerals indicate like parts.
As the size of the electrical devices and the conductors that comprise a memory device are made smaller and smaller, ever greater demands are placed on the techniques used to form these features. For example, photolithography is commonly used to pattern device features, such as conductive lines, on a substrate. The concept of pitch can be used to describe the size of these features. Due to optical factors such as light or radiation wavelength, however, photolithography techniques have a minimum pitch below which features cannot be formed reliably. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
One technique proposed for extending the capabilities of photolithographic techniques beyond their minimum pitch is the "pitch doubling" technique. This technique is illustrated in
While pitch is actually reduced using these techniques, this reduction in pitch is conventionally referred to as "pitch doubling", or more generally, "pitch multiplication". This is because these techniques allow the number of features in a given region of the substrate to be doubled, or more generally, multiplied. Thus, using the conventional terminology, "multiplication" of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein. By forming multiple layers of spacers upon each other, the definable feature size can be made even smaller. Thus, the terms "pitch multiplication" and "pitch doubling" refer to the process generally, regardless of the number of times the spacer formation process is employed.
Some proposed methods for forming patterns in the periphery and in the array of a memory device involve use of two separate carbon layers. For example, in one such method, the mandrels used to define spacer loops are formed in an upper carbon layer. After pitch doubling and periphery patterning processes are performed, the array pattern is transferred to a lower carbon layer. While this process does allow features of different sizes to be formed in the array and periphery regions, use of a low temperature oxide material to define the spacer loops allows mandrels to be formed from the existing photoresist layer. This advantageously allows the top carbon layer to be omitted, thereby simplifying production.
In accordance with the foregoing, simplified and improved techniques have been developed for forming arrays of features in different regions of a memory device.
In certain embodiments, the feature pattern to be transferred to a substrate has a pitch below the minimum pitch of the photolithographic technique used for processing the substrate. Additionally, certain embodiments can be used to form arrays of features, including logic or gate arrays and volatile and non-volatile memory devices such as DRAM, phase change memory ("PCM"), programmable conductor random access memory ("PCRAM"), read only memory ("ROM"), flash memory. In such devices, pitch multiplication is usable to form, for example, transistor gate electrodes and conductive lines in the array region of the devices. Optionally, conventional photolithography is usable to form larger features, such as local interconnects and complementary metal oxide semiconductor ("CMOS") circuits, in the peripheral region of the devices. For example, the logic array can be a field programmable gate array ("FPGA") having a core array similar to a memory array and a periphery with supporting logic circuits. Exemplary masking steps in the course of fabricating a memory device are illustrated in the figures and are described herein.
On the other hand, the peripheral region 104 optionally includes features larger than those in the array region 102. Conventional photolithography, rather than pitch multiplication, is typically used to pattern these larger features, examples of which include various types of logic circuitry. The geometric complexity of the logic circuits located in the peripheral region 104 makes using pitch multiplication difficult in this region of the integrated circuit 100. In contrast, the regular grid typical of array patterns is conducive to pitch multiplication. Additionally, some devices in the peripheral region 104 may require larger geometries due to electrical constraints, thereby making pitch multiplication less advantageous than conventional photolithography for such devices. In addition to possible differences in relative scale, the relative positions, and the number of peripheral regions 104 and array regions 102 in the integrated circuit 100 can vary in other embodiments. In embodiments wherein different processing techniques are separately used to form features in the array region 102 and the peripheral region 104, the peripheral region 104 can be masked during processing of the array region.
An optional second hard mask layer 110 is formed over the first hard mask layer 108. The second hard mask layer 110 preferably comprises an inorganic material. Example materials for the second hard mask layer 110 include silicon nitride, polycrystalline silicon, or a dielectric antireflective coating ("DARC"), such as silicon-rich silicon oxynitride. Preferably, the material comprising the second hard mask layer 110 can be selectively etched with respect to subsequently-deposited spacer materials. Use of a DARC for the second hard mask layer 110 can be particularly advantageous for forming patterns having pitches near the resolution limits of a photolithographic technique. In particular, a DARC can enhance resolution by reducing light reflections, thus increasing the precision with which photolithography can define the edges of a pattern. The second hard mask layer 110 is omitted in embodiments wherein the first hard mask layer 108 can be etched selectively with respect to subsequently deposited spacer materials. In still other embodiments, the second hard mask layer 110 is replaced with an organic spin on antireflective coating ("ARC") positioned between the first hard mask layer 108 and the subsequently described overlying array photoresist layer.
An array photoresist layer 111, also referred to herein as a mandrel layer, is formed over the second hard mask layer 110. The array photoresist layer 111 preferably comprises a photoresist material that is compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems such as 13.7 nm wavelength systems, or electron beam lithographic systems. Examples of preferred photoresist materials include argon fluoride sensitive photoresist (that is, photoresist suitable for use with an argon fluoride light source) and krypton fluoride sensitive photoresist (that is, photoresist suitable for use with a krypton fluoride light source). Argon fluoride photoresists are preferably used with shorter wavelength photolithography systems, such as 193 nm wavelength systems. Krypton fluoride photoresists are preferably used with longer wavelength photolithography systems, such as 248 nm wavelength systems. In a modified embodiment, the array photoresist layer 111 comprises a photoresist material that can be patterned by nano-imprint lithography, such as by using a mold or a mechanical force to pattern the photoresist material.
In general, the materials for the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are chosen based on the chemistry and the process conditions for the various pattern forming and transfer steps disclosed herein. For instance, in an example embodiment, the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can each be selectively etched with respect to each other. As used herein, a material is considered "selectively etched" (or "preferentially etched") when the etch rate for that material is at least about 2 times greater, preferably at least about 10 times greater, more preferably at least about 20 times greater, and most preferably at least about 40 times greater than that for a neighboring material. In modified embodiments other layers are added if suitable other materials, chemistries and/or processes conditions are used.
The first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can be formed using deposition processes such as spin-on coating, sputtering, chemical vapor deposition ("CVD"), or atomic layer deposition. For example, a low temperature CVD process (preferably less than about 550� C., more preferably less than about 450� C., and most preferably less than about 400� C.) advantageously reduces chemical and/or physical disruption of an amorphous carbon layer, and thus is useful for deposition of materials over an existing amorphous carbon layer, such as the first hard mask layer 108. Additional information regarding the formation of amorphous carbon layers, including doped amorphous carbon layers, is provided in U.S. Pat. No. 6,573,030 (issued 3 Jun. 2003) and U.S. Patent Application Publication 2005/0042879 (published 24 Feb. 2005). The entire disclosure of this patent and patent application publication is hereby incorporated by reference herein.
The thicknesses of the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are also chosen depending upon compatibility with the etch chemistries and process conditions disclosed herein. For example, when etching a material through a mask of another material, such as when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Thus, the upper layer is preferably sufficiently thick such that it is not completely worn away over the course of the pattern transfer. In an example embodiment, the second hard mask layer 110 is preferably between about 10 nm and about 40 nm thick, and is more preferably between about 15 nm and about 30 nm thick.
The thickness of the array photoresist layer 111 depends on the wavelength of light used to pattern the array photoresist layer 111. In an example embodiment wherein 248 nm light is used to perform photolithography, the array photoresist layer 111 is preferably between about 50 nm and about 300 nm thick, and is more preferably between about 200 nm and 250 nm thick. This height can vary depending upon the wavelength of light used to pattern the photoresist layer. Because lines are subsequently formed in the array photoresist layer 111, in certain embodiments the height of the array photoresist layer 111 is limited by the structural integrity and the aspect ratio of the lines to be formed, since tall spacer lines may collapse or otherwise deform.
As illustrated in
The pitch of the resulting lines 124 is equal to the sum of the width of a line 124 and the width of a neighboring trench 122. To reduce the dimensions of features formed using this pattern of lines 124 and trenches 122, the pitch can be at or near the limits of the photolithographic technique used to pattern the array photoresist layer 111. For example, for photolithography using 248 nm light, the pitch of the lines 124 is preferably between about 80 nm and about 150 nm, and is more preferably between about 90 nm and about 120 nm. Thus, in an example embodiment the pitch is the minimum pitch of the photolithographic technique and the subsequently-formed pitch multiplied spacer pattern advantageously has a pitch below the minimum pitch of the photolithographic technique. In alternative embodiments, because the margin of error for position and feature size typically increases as the limits of a photolithographic technique are approached, the lines 124 are formed having larger feature sizes, such as 200 nm, to reduce errors in the positions and sizes of the lines 124.
As illustrated in
As illustrated in
In an example embodiment, the low temperature spacer material 126 is deposited in an ALD process using Si2Cl6, H2O and C5H5N precursors. In such embodiments the spacer material 126 is deposited to a thickness that is preferably between about 20 nm and about 65 nm, more preferably between about 25 nm and about 60 nm, and most preferably between about 30 nm and about 55 nm. In one embodiment, the spacer material thickness is between about 30 nm and about 40 nm, and in another embodiment, the spacer material thickness is between about 43 nm and about 55 nm. The spacer material deposition rate is preferably between about 1 Å per cycle and about 4 Å per cycle, and more preferably about 2 Å per cycle.
As illustrated in
In modified embodiments, the periphery photoresist layer 128 is deposited in the same deposition step in which the array photoresist layer 111 is deposited. In such embodiments, the mask used to pattern the array photoresist layer 111 is configured so as to leave a photoresist pattern or blanket layer in the peripheral region 104. This process results in photoresist being deposited directly on the second hard mask layer 110 in the peripheral region 104, without the intervening spacer material 126.
As illustrated in
As illustrated in
After the freestanding spacers 130 are formed, subsequent processing steps can be conducted, such as a dry develop step and an in situ etch step. The subsequent processing steps can be used to transfer the pattern of spacers 130 and periphery features to the underlying first hard mask layer 108 and/or the second hard mask layer 110, as illustrated in
Certain of the techniques disclosed herein advantageously enable the formation of a pitch doubled pattern of spacers to be formed in the array region without the use of additional layers to define the array features, such as a top carbon layer and an amorphous silicon layer. Specifically, by forming low temperature oxide spacers directly on the array photoresist layer 111 as disclosed herein, the photoresist material itself can be used to define mandrels which are used in a subsequent pitch multiplication technique. This advantageously eliminates the need to pattern additional masking layers to define mandrels. Such techniques advantageously allow process steps associated with such additional masking layers to be eliminated, such as additional dry develop steps and hard mask etch steps. Furthermore, such techniques also advantageously allow the periphery photoresist layer 128 to be defined using the same low temperature spacer material that is used to form the spacers in the array region. Certain of the embodiments disclosed herein also advantageously allow a hard mask material—as compared to a more vulnerable photoresist material—to be used to block and define features in the peripheral region 104 without requiring the use of a separate hard mask layer.
While the foregoing detailed description discloses several embodiments of the present invention, it should be understood that this disclosure is illustrative only and is not limiting of the present invention. It should be appreciated that the specific configurations and operations disclosed can differ from those described above, and that the methods described herein can be used in contexts other than integrated circuit fabrication.
|Cited Patent
|Filing date
|Publication date
|Nov 3, 1978
|Nov 18, 1980
|International Business Machines Corporation
|Method for forming an insulator between layers of conductive material
|Feb 9, 1979
|Jan 27, 1981
|Kawai Musical Instrument Mfg. Co. Ltd.
|Data transfer apparatus for digital polyphonic tone synthesizer
|Dec 30, 1981
|Dec 13, 1983
|International Business Machines Corporation
|Fabrication process of sub-micrometer channel length MOSFETs
|Dec 7, 1981
|Feb 21, 1984
|Bell Telephone Laboratories, Incorporated
|Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
|Mar 26, 1982
|Jun 5, 1984
|Device for registering the rear edges of the sheets in sheet delivery mechanisms for printing machines
|Oct 28, 1983
|Mar 5, 1985
|International Business Machines Corporation
|Method of making structures with dimensions in the sub-micrometer range
|Mar 30, 1981
|Apr 2, 1985
|International Business Machines Corporation
|Lateral device structures using self-aligned fabrication techniques
|Dec 12, 1984
|Feb 18, 1986
|Kabushiki Kaisha Toshiba
|Manufacturing a field oxide region for a semiconductor device
|Oct 30, 1985
|Mar 10, 1987
|International Business Machines Corporation
|Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
|Feb 28, 1985
|Dec 15, 1987
|Westinghouse Electric Corp.
|Non-volatile memory device for a programmable controller
|Nov 28, 1984
|Dec 29, 1987
|Nec Corporation
|Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
|Aug 12, 1986
|Jun 14, 1988
|Abrams William R
|Method for sonic analysis of an anomaly in a seafloor topographic representation
|Oct 30, 1987
|Oct 11, 1988
|International Business Machines Corporation
|Formation of variable-width sidewall structures
|Jun 20, 1988
|Jun 13, 1989
|International Business Machines Corporation
|Process for defining organic sidewall structures
|Jul 18, 1990
|May 7, 1991
|Micron Technology, Inc.
|Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
|Sep 26, 1990
|Sep 10, 1991
|Micron Technology, Inc.
|Method of forming a narrow self-aligned, annular opening in a masking layer
|Jul 19, 1990
|Oct 1, 1991
|Micron Technology, Inc.
|Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
|Oct 16, 1991
|May 26, 1992
|Huls Aktiengesellschaft
|Process for the preparation of organosilanes containing methacryloyloxy or acryloyloxy groups
|Nov 25, 1992
|Jul 12, 1994
|Micron Technology, Inc.
|Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
|Jul 16, 1992
|Jul 19, 1994
|Micron Technology, Inc.
|Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
|Jan 7, 1993
|Nov 28, 1995
|International Business Machines Corporation
|Diamond-like carbon films from a hydrocarbon helium plasma
|Mar 15, 1994
|Mar 26, 1996
|Kabushiki Kaisha Toshiba
|Dynamic random access memory (DRAM) semiconductor device
|Jan 13, 1995
|May 7, 1996
|Myrick; James J.
|SOI methods and apparatus
|Jul 12, 1995
|Jan 14, 1997
|Hyundai Electronics Industries Co. Ltd.
|Method for forming submicroscopic patterns
|Sep 20, 1996
|Sep 23, 1997
|Micron Technology, Inc.
|Thin film transistors
|Jun 20, 1996
|May 19, 1998
|Hyundai Electronics Industries Co., Ltd.
|Method for fabricating metal oxide field effect transistors
|Apr 23, 1996
|Aug 4, 1998
|International Business Machines Corporation
|Plating of noble metal electrodes for DRAM and FRAM
|Jul 26, 1996
|Aug 18, 1998
|International Business Machines Corporation
|Reducing pitch with continuously adjustable line and space dimensions
|Jan 9, 1997
|Nov 3, 1998
|International Business Machines Corporation
|Sputter deposition of hydrogenated amorphous carbon film and applications thereof
|Aug 29, 1996
|May 4, 1999
|Sony Corporation
|Method of forming pattern
|Feb 26, 1998
|May 18, 1999
|Advanced Micro Devices, Inc.
|Ultra short trench transistors and process for making same
|Nov 1, 1996
|Dec 7, 1999
|Micron Technology, Inc.
|Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
|Jan 20, 1998
|Dec 21, 1999
|Advanced Micro Devices, Inc.
|Core array and periphery isolation technique
|Sep 17, 1997
|Mar 28, 2000
|The University Of New Mexico
|Method and apparatus for extending spatial frequencies in photolithography images
|May 17, 1999
|May 2, 2000
|Vanguard International Semiconductor Corporation
|Design for high density memory with relaxed metal pitch
|Sep 29, 1997
|May 16, 2000
|Intel Corporation
|Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
|Nov 10, 1998
|Jun 6, 2000
|Vanguard International Semiconductor Corporation
|Method for simultaneously fabricating a DRAM capacitor and metal interconnections
|Apr 28, 1999
|Aug 29, 2000
|Worldwide Semiconductor Manufacturing Corp.
|Method for forming a hard mask of half critical dimension
|Dec 12, 1997
|Nov 7, 2000
|Applied Materials Inc
|Method for high temperature etching of patterned layers using an organic mask stack
|Dec 10, 1998
|Mar 27, 2001
|Samsung Electronics Co., Ltd.
|Semiconductor device and method for fabricating the same
|Apr 12, 1999
|Apr 3, 2001
|Advanced Micro Devices
|Process for fabricating a semiconductor device component using a selective silicidation reaction
|Sep 29, 1999
|Aug 28, 2001
|International Business Machines Corporation
|Four F-squared gapless dual layer bitline DRAM array architecture
|Jun 23, 2000
|Sep 11, 2001
|Lsi Logic Corporation
|Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
|Dec 19, 1997
|Sep 18, 2001
|Applied Materials, Inc.
|Etch stop layer for dual damascene process
|Mar 10, 2000
|Oct 2, 2001
|United Microelectronics Corp.
|Dual damascene interconnect structure with reduced parasitic capacitance
|Sep 29, 2000
|Jan 1, 2002
|Vanguard International Semiconductor Corporation
|Method of making pillar-type structure on semiconductor substrate
|Aug 25, 2000
|Feb 19, 2002
|Micron Technology, Inc.
|Use of dilute steam ambient for improvement of flash devices
|Sep 6, 2000
|May 7, 2002
|Sony Corporation
|Process for fabricating a semiconductor device
|Aug 30, 2000
|May 28, 2002
|Micron Technology, Inc.
|Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
|May 18, 1999
|Jun 11, 2002
|Mitsubishi Denki Kabushiki Kaisha
|Semiconductor integrated circuit
|Mar 21, 2000
|Jul 23, 2002
|Micron Technology, Inc.
|Use of DARC and BARC in flash memory processing
|Aug 14, 2000
|Sep 24, 2002
|Micron Technology, Inc.
|Nucleation for improved flash erase characteristics
|Apr 2, 2001
|Nov 5, 2002
|Advanced Micro Devices, Inc.
|Method of forming integrated circuit features by oxidation of titanium hard mask
|Jun 28, 2002
|Dec 31, 2002
|Advanced Micro Devices, Inc.
|Method of forming sub-lithographic spaces between polysilicon lines
|May 13, 1998
|Feb 4, 2003
|Semiconductor Process Laboratory Co., Ltd.
|Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same
|Aug 2, 2001
|Feb 18, 2003
|Micron Technology, Inc.
|Programming methods for multi-level flash EEPROMs
|Oct 23, 2001
|Mar 18, 2003
|Advanced Micro Devices, Inc.
|Chemical feature doubling process
|Jun 5, 2001
|Apr 15, 2003
|Applied Materials, Inc.
|Method of producing an interconnect structure for an integrated circuit
|Jun 13, 2002
|May 6, 2003
|Advanced Micro Devices, Inc.
|Method of using amorphous carbon as spacer material in a disposable spacer process
|Aug 26, 2002
|May 20, 2003
|Intel Corporation
|Forming polymer features on a substrate
|Jun 8, 2000
|Jun 3, 2003
|Applied Materials, Inc.
|Method for depositing an amorphous carbon layer
|May 13, 2002
|Aug 5, 2003
|Taiwan Semiconductor Manufacturing Co., Ltd
|Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
|Oct 23, 2002
|Sep 30, 2003
|Micron Technology, Inc.
|Method of forming minimally spaced word lines
|Jul 19, 2000
|Oct 14, 2003
|International Business Machines Corporation
|Self-trimming method on looped patterns
|Jan 7, 2002
|Oct 28, 2003
|Macronix International Co., Ltd.
|Method for pitch reduction
|Oct 12, 2000
|Dec 23, 2003
|Vram Technologies, Llc
|Method and apparatus for patterning fine dimensions
|Jan 2, 2003
|Jan 6, 2004
|Advanced Micro Devices, Inc.
|Use of diamond as a hard mask material
|Dec 20, 2002
|Feb 3, 2004
|Motorola, Inc.
|Vertical MOSFET with asymmetric gate structure
|Jun 28, 2002
|Feb 10, 2004
|Taiwan Semiconductor Manufacturing Company
|Multi-purpose composite mask for dual damascene patterning
|Jul 12, 2002
|Mar 16, 2004
|Masayoshi Sasaki
|Semiconductor memory having longitudinal cell structure
|Oct 9, 2002
|Mar 23, 2004
|Axcelis Technologies, Inc.
|Process for reducing edge roughness in patterned photoresist
|Jul 22, 2002
|May 11, 2004
|Infineon Technologies Ag
|Non-volatile memory cell and fabrication method
|Jun 12, 2002
|May 11, 2004
|Macronix International Co., Ltd.
|Pitch reduction in semiconductor fabrication
|Aug 24, 2001
|Jun 1, 2004
|Micron Technology Inc.
|Floating gate transistor with horizontal gate layers stacked next to vertical body
|May 2, 2003
|Jul 27, 2004
|Texas Instruments Incorporated
|Semiconductor device array having dense memory cell array and hierarchical bit line scheme
|May 20, 2003
|Aug 10, 2004
|Advanced Micro Devices, Inc.
|Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
|Jun 14, 2002
|Aug 17, 2004
|Ingentix Gmbh & Co. Kg
|NROM memory circuit with recessed bitline
|Aug 29, 2002
|Sep 21, 2004
|Micron Technology Inc
|Annular gate and technique for fabricating an annular gate
|Jul 31, 2002
|Oct 5, 2004
|Micron Technology, Inc.
|Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
|Jul 14, 2003
|Dec 28, 2004
|Advanced Micro Devices, Inc.
|Partially de-coupled core and periphery gate module process
|Nov 10, 2003
|Mar 15, 2005
|Macronix International Co., Ltd.
|Fabrication method of sub-resolution pitch for integrated circuits
|Jan 20, 2004
|Apr 5, 2005
|International Business Machines Corporation
|Method for forming quadruple density sidewall image transfer (SIT) structures
|Jun 16, 2003
|Aug 2, 2005
|Applied Materials, Inc.
|Method for fabricating a gate structure of a field effect transistor
|Nov 30, 2004
|Aug 30, 2005
|Micron Technology, Inc.
|Method of forming field effect transistors
|May 27, 2004
|Oct 18, 2005
|Macronix International Co., Ltd.
|Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
|Dec 10, 2003
|Nov 8, 2005
|Microntechnology, Inc.
|Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof
|Apr 28, 2003
|Mar 21, 2006
|Advanced Micro Devices, Inc.
|Use of amorphous carbon for gate patterning
|Feb 28, 2005
|Jul 11, 2006
|Hynix Semiconductor Inc.
|Capacitor of semiconductor device and method for forming the same
|Feb 19, 2004
|Aug 1, 2006
|Samsung Electronics, Co., Ltd.
|Method for forming silicon dioxide film using siloxane
|May 26, 2004
|Aug 29, 2006
|Micron Technology, Inc.
|Methods for forming semiconductor structures
|Sep 2, 2004
|Oct 3, 2006
|Micron Technology, Inc.
|Method for integrated circuit fabrication using pitch multiplication
|Jun 8, 2004
|Feb 27, 2007
|Macronix International Co., Ltd.
|Method of pitch dimension shrinkage
|Dec 13, 2004
|Feb 27, 2007
|Intel Corporation
|Quantum wire gate device and method of making same
|Nov 29, 2004
|Apr 24, 2007
|Texas Instruments Incorporated
|Pitch multiplication process
|Feb 3, 2005
|Sep 18, 2007
|Lam Research Corporation
|Reduction of feature critical dimensions using multiple masks
|May 9, 2005
|Oct 30, 2007
|International Business Machines Corporation
|Double gated transistor and method of fabrication
|Aug 1, 2005
|Nov 6, 2007
|Infineon Technologies Ag
|Method of production pitch fractionizations in semiconductor technology
|Dec 14, 2000
|Jun 28, 2001
|Jin-Won Kim
|Method for manufacturing an electrode of a capacitor
|Sep 20, 2001
|Apr 11, 2002
|Bjarni Bjarnason
|Method in etching of a substrate
|Dec 12, 2001
|Apr 18, 2002
|Werner Juengling
|Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
|Nov 30, 2000
|May 30, 2002
|Cantell Marc W.
|Etching of hard masks
|Dec 4, 2000
|Jun 6, 2002
|Jiunn-Ren Hwang
|Method of forming opening in wafer layer
|Dec 21, 2001
|Jul 18, 2002
|Semiconductor Leading Edge Technologies, Inc.
|Method of forming fine patterns
|Jul 18, 2001
|Sep 12, 2002
|Nippon Steel Corporation
|Semiconductor device and a method of manufacturing the same
|May 8, 2002
|Sep 12, 2002
|Fujitsu Limited
|Semiconductor device and method for fabricating the same
|Mar 16, 2001
|Sep 19, 2002
|Tran Luan C.
|6F2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6F2 dram array and a method of isolating a single row of memory cells in a 6F2 dram array
|Mar 14, 2001
|Sep 19, 2002
|Micron Technology, Inc.
|CMOS gate array with vertical transistors
|Mar 23, 2001
|Sep 26, 2002
|Er-Xuan Ping
|Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
|Oct 10, 2001
|Oct 31, 2002
|Hitachi, Ltd.
|Nonvolatile semiconductor memory device and a method of manufacturing the same
|Mar 1, 2000
|Jan 9, 2003
|Brian Doyle
|Quantum wire gate device and method of making same
|Aug 28, 2002
|Jan 9, 2003
|Micron Technology, Inc.
|Flash memory with ultra thin vertical body transistors
|Oct 21, 2002
|Feb 27, 2003
|Micron Technology, Inc.
|Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines
|Sep 6, 1996
|Mar 6, 2003
|Shigeto Maegawa
|Semiconductor device having a thin film transistor and manufacturing method thereof
|Aug 8, 2002
|Mar 6, 2003
|Yi-Yu Hsu
|Process for improving critical dimension uniformity
|Aug 13, 2001
|Apr 17, 2003
|Reynolds James H.
|Color photothermographic element comprising a dye-forming system for forming a novel infrared dye
|Oct 24, 2002
|Jun 12, 2003
|Hiroshi Kujirai
|Method of manufacturing semiconductor device and semiconductor device
|Jul 16, 2002
|Jun 26, 2003
|Applied Materials, Inc.
|Method of forming a dual damascene structure
|Jan 7, 2002
|Jul 10, 2003
|Macronix International Co., Ltd.
|Method for pitch reduction
|Feb 20, 2003
|Aug 21, 2003
|Dirk Manger
|Method for forming a hard mask in a layer on a planar device
|May 3, 2002
|Nov 6, 2003
|Weimin Li
|Method of fabricating a semiconductor multilevel interconnect structure
|May 1, 2002
|Nov 6, 2003
|Swaminathan Sivakumar
|Patterning tighter and looser pitch geometries
|Mar 24, 2003
|Nov 20, 2003
|Jon Maimon
|Method for making tapered opening for programmable resistance memory element
|May 17, 2002
|Nov 20, 2003
|International Business Machines Corporation
|Method of forming active devices of different gatelengths using lithographic printed gate images of same length
|Dec 11, 2002
|Nov 27, 2003
|Micron Technology, Inc.
|Open bit line DRAM with ultra-thin body transistors
|May 19, 2003
|Dec 18, 2003
|Dong-Seok Nam
|Method of forming fine patterns of semiconductor device
|Jun 28, 2002
|Jan 1, 2004
|Infineon Technologies North America Corp.
|Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
|Jul 23, 2002
|Jan 29, 2004
|So Daniel W.
|Fabricating sub-resolution structures in planar lightwave devices
|Jul 21, 2003
|Jan 29, 2004
|Wei Liu
|Method for fabricating a notch gate structure of a field effect transistor
|Dec 30, 2002
|Feb 5, 2004
|Advanced Micro Devices, Inc.
|Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
|Aug 2, 2002
|Feb 5, 2004
|Applied Materials Inc.
|Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
|Aug 26, 2002
|Feb 26, 2004
|International Business Machines Corporation
|DRAM cell with enhanced SER immunity
|Aug 11, 2003
|Mar 4, 2004
|Voshell Thomas W.
|Random access memory device utilizing a vertically oriented select transistor
|Jun 16, 2003
|Mar 4, 2004
|Wei Liu
|Method for fabricating a gate structure of a field effect transistor
|Sep 18, 2002
|Mar 18, 2004
|Gian Sharma
|Method for forming a sublithographic opening in a semiconductor process
|Oct 28, 2002
|Apr 29, 2004
|Sandisk Corporation
|Flash memory cell arrays having dual control gates per memory cell charge storage element
|Nov 25, 2003
|Jun 3, 2004
|Matsushita Electric Industrial Co., Ltd.
|Method for fabricating semiconductor device
|Dec 13, 2002
|Jun 17, 2004
|Taiwan Semiconductor Manufacturing Company
|Method of fabricating a mosfet device with metal containing gate structures
|Jan 14, 2004
|Aug 12, 2004
|Ted Johansson
|Selective base etching
|Mar 11, 2004
|Sep 30, 2004
|Semiconductor Leading Edge Technologies, Inc.
|Method for manufacturing semiconductor device
|Dec 9, 2003
|Nov 25, 2004
|Renesas Technology Corp.
|Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film
|Aug 22, 2003
|Feb 24, 2005
|Zhiping Yin
|Masking methods
|Oct 1, 2004
|Apr 7, 2005
|Dongbu Electronics Co., Ltd.
|Semiconductor device and a method for fabricating the semiconductor device
|Nov 1, 2004
|May 26, 2005
|Kabushiki Kaisha Toshiba
|Light-emitting device and method for manufacturing the same
|Dec 22, 2004
|Jun 30, 2005
|Samsung Electronics Co., Ltd.
|Method of forming a pattern in a semiconductor device and method of forming a gate using the same
|Jan 8, 2004
|Jul 14, 2005
|Toshiharu Furukawa
|Method of independent P and N gate length control of FET device made by sidewall image transfer technique
|Jan 27, 2004
|Jul 28, 2005
|Micron Technology, Inc.
|Selective epitaxy vertical integrated circuit components and methods
|Jan 30, 2004
|Aug 4, 2005
|Wei Liu
|Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
|Apr 20, 2005
|Aug 25, 2005
|Jackson Timothy L.
|Semiconductor dice having backside redistribution layer accessed using through-silicon vias, methods
|Jun 8, 2004
|Dec 8, 2005
|Macronix International Co., Ltd.
|Method of pitch dimension shrinkage
|May 26, 2004
|Dec 15, 2005
|Werner Juengling
|Methods for forming semiconductor structures
|Jul 1, 2004
|Jan 5, 2006
|Lane Richard H
|Method for forming controlled geometry hardmasks including subresolution elements and resulting structures
|Jul 28, 2004
|Feb 2, 2006
|International Business Machines Corporation
|Borderless contact structures
|Jun 10, 2005
|Feb 2, 2006
|Hynix Semiconductor, Inc.
|Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask
|Oct 7, 2005
|Feb 9, 2006
|Micron Technology, Inc.
|6F2 3-Transistor DRAM gain cell
|Aug 31, 2004
|Mar 2, 2006
|Zhiping Yin
|Prevention of photoresist scumming
|Sep 1, 2004
|Mar 2, 2006
|Abatchev Mirzafer K
|Mask material conversion
|Sep 2, 2004
|Mar 2, 2006
|Sandhu Gurtej S
|Method to align mask patterns
|Sep 1, 2004
|Mar 2, 2006
|Werner Juengling
|DRAM cells with vertical transistors
|Aug 31, 2004
|Mar 2, 2006
|Micron Technology, Inc.
|Methods for increasing photo alignment margins
|Sep 2, 2004
|Mar 2, 2006
|Abatchev Mirzafer K
|Method for integrated circuit fabrication using pitch multiplication
|Oct 7, 2005
|Apr 20, 2006
|Ho-Chul Kim
|Apparatus for exposing a substrate, photomask and modified illuminating system of the apparatus, and method of forming a pattern on a substrate using the apparatus
|Apr 5, 2004
|Jun 22, 2006
|Fujitsu Limited
|Method for fabricating semiconductor device
|Feb 3, 2005
|Aug 3, 2006
|Jeffrey Marks
|Reduction of feature critical dimensions using multiple masks
|Dec 7, 2005
|Aug 24, 2006
|Hynix Semiconductor Inc.
|Composition for an organic hard mask and method for forming a pattern on a semiconductor device using the same
|Aug 29, 2005
|Sep 21, 2006
|Luan Tran
|Pitch reduced patterns relative to photolithography features
|Mar 24, 2005
|Sep 28, 2006
|Couto Fernando J R
|TNFalpha-neutralizing antibodies
|Aug 31, 2005
|Sep 28, 2006
|Tran Luan C
|Integrated circuit fabrication
|Mar 6, 2006
|Oct 19, 2006
|Ji-Young Lee
|Semiconductor device having fine contacts and method of fabricating the same
|Mar 30, 2006
|Oct 19, 2006
|Rodger Fehlhaber
|Hard mask arrangement
|May 23, 2005
|Nov 23, 2006
|Mirzafer Abatchev
|Methods for forming arrays of a small, closely spaced features
|May 26, 2005
|Nov 30, 2006
|Micron Technology, Inc.
|Multi-state memory cell
|Jun 2, 2005
|Dec 7, 2006
|Micron Technology, Inc., A Corporation
|Multiple spacer steps for pitch multiplication
|Dec 6, 2005
|Dec 7, 2006
|Hynix Semiconductor Inc.
|Method for fabricating semiconductor device
|Jun 14, 2005
|Dec 14, 2006
|Eppich Anton P
|Relaxed-pitch method of aligning active area to digit line
|Jun 9, 2005
|Dec 14, 2006
|Wells David H
|Method and apparatus for adjusting feature size and position
|Nov 3, 2005
|Jan 25, 2007
|Bing-Huan Lee
|Nanoimprint lithograph for fabricating nanoadhesive
|Jul 29, 2005
|Feb 1, 2007
|Micron Technology, Inc.
|Pitch doubled circuit layout
|Aug 18, 2005
|Feb 22, 2007
|Micron Technology, Inc.
|Method of etching a substrate and method of forming a feature on a substrate
|Sep 1, 2005
|Mar 1, 2007
|Haller Gordon A
|Memory cell layout and process flow
|Sep 1, 2005
|Mar 1, 2007
|Wells David H
|Methods for forming arrays of small, closely spaced features
|Sep 1, 2005
|Mar 1, 2007
|Micron Technology, Inc., A Corporation
|Method of forming isolated features using pitch multiplication
|Sep 1, 2005
|Mar 1, 2007
|Sandhu Gurtej S
|Pitch multiplication spacers and methods of forming the same
|Sep 1, 2005
|Mar 1, 2007
|Mirzafer Abatchev
|Protective coating for planarization
|Aug 31, 2005
|Mar 1, 2007
|Tran Luan C
|Method of forming pitch multipled contacts
|Aug 25, 2005
|Mar 1, 2007
|Micron Technology, Inc., A Corporation
|Multiple deposition for integration of spacers in pitch multiplication process
|Aug 30, 2005
|Mar 1, 2007
|Micron Technology, Inc., A Corporation
|Method and algorithm for random half pitched interconnect layout with constant spacing
|Dec 28, 2005
|Jun 28, 2007
|Fei Wang
|DRAM cell design with folded digitline sense amplifier
|Mar 7, 2006
|Sep 13, 2007
|Dirk Caspary
|Memory device and an array of conductive lines and methods of making the same
|Mar 17, 2006
|Sep 20, 2007
|Toshiharu Furukawa
|Layout and process to contact sub-lithographic structures
|Oct 14, 2004
|Sep 20, 2007
|The Regents Of The University Of California
|Methods for Fabrication of Positional and Compositionally Controlled Nanostructures on Substrate
|May 24, 2006
|Nov 29, 2007
|Synopsys, Inc.
|Patterning A Single Integrated Circuit Layer Using Multiple Masks And Multiple Masking Layers
|Sep 6, 2006
|Mar 6, 2008
|International Business Machines Corporation
|Vertical field effect transistor arrays and methods for fabrication thereof
|Oct 29, 1992
|May 5, 1994
|Siemens Ag
|Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
|Mar 15, 1994
|Sep 22, 1994
|Toshiba Kawasaki Kk
|Semiconductor arrangement
|Jun 23, 1999
|Jul 6, 2000
|Siemens Ag
|DRAM cell array has deep word line trenches for increasing transistor channel length and has no fixed potential word lines separating adjacent memory cells
|Nov 20, 1986
|Nov 29, 1989
|Plessey Overseas Limited
|Method of manufacturing semiconductor devices having side-wall isolation
|Nov 7, 1991
|Jun 24, 1992
|Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno
|Process for making planarized sub-micrometric trenches in integrated circuits
|Apr 17, 2003
|Jun 23, 2004
|Hewlett-Packard Company
|Method of fabricating sub-lithographic sized line and space patterns
|Apr 13, 2000
|Jan 4, 2001
|Hofmann Franz
|Dram cell arrangement and method for the production thereof
|Apr 29, 2002
|Dec 12, 2002
|Infineon Technologies Corp
|Method for removing polysilane from a semiconductor without stripping
|Jun 18, 2003
|Dec 31, 2003
|Applied Materials Inc
|Method for fabricating a gate structure of a field effect transistor
|Feb 13, 2004
|Aug 26, 2004
|Dimitri A Antoniadis
|Finfet device and method to make same
|Sep 30, 2004
|Apr 14, 2005
|Fehlhaber Rodger
|Method for the production of a hard mask and hard mask arrangement
|Aug 26, 2005
|Mar 9, 2006
|Micron Technology Inc
|Method for integrated circuit fabrication using pitch multiplication
|May 22, 2006
|Nov 30, 2006
|Micron Technology Inc
|Methods for forming arrays of small, closely spaced features
|"Ex parte Cantell, unpublished decision of the Board of Patent Appeals and Interferences, Mar. 4, 2005".
|"U.S. Appl. No. 11/543,515, filed Oct. 24, 2006, MICRON Ref. No. 2005-1173.00/US".
|Bergeron, et al., "Resolution Enhancement Techniques for the 90nm Technology Node and Beyond", Future Fab International, Issue 15, Jul. 11, 2003, 4 pages.
|Bhave et al., "Developer-soluble Gap fill materials for patterning metal trenches in Via-first Dual Damascene process", preprint of Proceedings of SPIE: Advances in Resist Technology and Processing XXI, vol. 5376, John L. Sturtevant, editor, 2004, 8 pages.
|Bruek, S.R.J., "Optical and interferometric lithography-Nanotechnology enablers," Proceedings of the IEEE, vol. 93, No. 10, Oct. 2005, pp. 1704-1721.
|Bruek, S.R.J., "Optical and interferometric lithography—Nanotechnology enablers," Proceedings of the IEEE, vol. 93, No. 10, Oct. 2005, pp. 1704-1721.
|Choi et al, "Sublithographic nanofabrication technology for nanocatalysts and DNA chips," J.Vac. Sci. Technol., Nov./Dec. 2003; pp. 2951-2955.
|Chung et al., "Nanoscale Multi-Line Patterning Using Sidewall Structure", Jpn., J.App.. Phys. vol. 41 (2002) Pt. 1, No. 6B,pp. 4410-4414, 2002.
|Chung et al., "Pattern multiplication method and the uniformity of nanoscale multiple lines*", J. Vac.Sci. Technol. B21(4), Jul./Aug. 2003, pp. 1491-95, Jul./Aug. 2003.
|International Preliminary Report on Patentability of Oct. 16, 2008 for International Application No. PCT/US2007/011525, filed May 14, 2007.
|Joubert et al., "Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas", Microelectronic Engineering 69 (2003), pp. 350-357.
|Lim et al., "Atomic layer deposition of transition metals", Nature Materials, vol. 2, Nov. 2003, pp. 749-754, 6 pages.
|Oehrlein et al., "Pattern transfer into low dielectic materials by high-density plasma etching", Solid State Tech., May 2000, 8 pages.
|Office Action of Mar. 25, 2009 in U.S. Appl. No. 11/744,074, filed May 3, 2009.
|Park et al., "Mass-productive ultra-low temperature ALD SiO2 process promising for sub-90nm memory and logic devices", Electron Devices Meeting, IEDM '02 Digest. International pp. 229-232 (2002).
|Sakao et al., "A Straight-Line-Trench Isolation and Trench-Gate Transistor (SLIT) Cell for Giga-bit DRAMs", Proceedings of IEEE VLSI Technology Symposium May 17-19, 1993 Kyoto, Japan, May 17, 1993, pp. 19-20.
|Schloesser et al., "Highly Scalable Sub-50nm Vertical Double Gate Trench DRAM Cell", Memory Development Center, Infineon Tech., 2004, 4 pages.
|Search Report and Written Opinion dated Mar. 15, 2010 in corresponding Singapore Patent Application No. 200807334-8.
|Sheats et al., "Microlithography: Science and Technology," Marcel Dekkar, Inc., pp. 104-105 (1998).
|U.S. Appl. No. 11/192,828, filed Jul. 29, 2005.
|U.S. Appl. No. 11/213,486, filed Aug. 25, 2005.
|U.S. Appl. No. 11/215,982, filed Aug. 31, 2005.
|U.S. Appl. No. 11/216,613, filed Aug. 30, 2005.
|U.S. Appl. No. 11/217,270, filed Sep. 1, 2005.
|U.S. Appl. No. 11/219,067, filed Sep. 1, 2005.
|U.S. Appl. No. 11/219,346, filed Sep. 1, 2005.
|U.S. Appl. No. 11/219,349, filed Sep. 1, 2005.
|U.S. Appl. No. 11/219,604, filed Sep. 1, 2005.
|U.S. Appl. No. 11/329,755, filed Jan. 11, 2006.
|U.S. Appl. No. 11/366,212, filed Mar. 2, 2006.
|U.S. Appl. No. 11/367,020, filed Mar. 2, 2006.
|U.S. Office Action issued Jul. 11, 2008 in U.S. Appl. No. 11/367,020, filed Mar. 2, 2006.
|U.S. Office Action issued Jun. 2, 2008 in U.S. Appl. No. 11/219,067, filed Sep. 1, 2005.
|U.S. Office Action issued Jun. 5, 2008 in U.S. Appl. No. 11/514,117, filed Aug. 30, 2006.
|Yan et al., "Scaling the Si MOSFET: From Bulk to SOI to Bulk", IEEE Transactions on Electron Devices USA; vol. 39, No. 7, Jul. 1992, pp. 1704-1710.
|Citing Patent
|Filing date
|Publication date
|Nov 18, 2011
|Apr 16, 2013
|Kabushiki Kaisha Toshiba
|Concave-convex pattern forming method and magnetic tunnel junction element forming method
|Feb 1, 2012
|Apr 29, 2014
|Powerchip Technology Corporation
|Method for forming contact hole
|Apr 17, 2009
|Dec 10, 2009
|Mitsuhiro Omura
|Method for fabricating semiconductor device
|May 30, 2013
|Powerchip Technology Corporation
|Method for forming contact hole
|Dec 4, 2013
|Jun 4, 2015
|Taiwan Semiconductor Manufacturing Company, Ltd.
|Lithography Using High Selectivity Spacers for Pitch Reduction
|U.S. Classification
|438/702, 438/699, 438/703, 438/695, 438/694
|International Classification
|Cooperative Classification
|European Classification
|Apr 7, 2006
Owner name: MICRON TECHNOLOGY, IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NIROOMAND, ARDAVAN;ZHOU, BAOSUO;ALAPATI, RAMAKANTH;REEL/FRAME:017775/0513;SIGNING DATES FROM 20060322 TO 20060405
Owner name: MICRON TECHNOLOGY, IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NIROOMAND, ARDAVAN;ZHOU, BAOSUO;ALAPATI, RAMAKANTH;SIGNING DATES FROM 20060322 TO 20060405;REEL/FRAME:017775/0513
|Aug 13, 2014
|Fee payment
Year of fee payment: 4

subset: commoncrawl


text:
#562 of 809
Duncan, OK
Comment, Like, Favorite
Expert Printing and Assembly
Shipping Within 2 - 3 Business Days
Millions of Satisfied Customers
Toni Hopper
Photograph - Photograph
One in a series of Florida black and white images, mostly off the beaten path.
September 14th, 2011
Viewed 1,969 Times - Last Visitor from New York, NY on 10/05/2015 at 9:20 PM
Sales Sheet
More from Toni Hopper
Duncan, OK - United States
Thank you to everyone who has commented! I'm a bit behind in replies!
Titusville, FL - United States
Congratulations on being featured in the Fine Art America Group "Images That Excite You!"
Lyndhurst, NJ - United States
Auburn, CA - United States
Congratulations on your sale!
Pride Of The Prairie - United States
Congratulations on your Fine Sale!
Croydon, Su - United Kingdom
Congrats on your sale!
Razgrad, Ra - Bulgaria
Congrats on your sale!
Duncan, OK - United States
Thank you very much to the buyer in Walpole, ME. I hope you enjoy this and I'd love to see a snapshot of it in your home on the wall!
East Hampton, NY - United States
La Plata, Bu - Argentina
Thanks Lazaro!
Keene , On - Canada
Love this image! It's especially striking in black and white! Congrats and continued success!
Thank you Margaret!
Duncan, OK - United States
Thank you to the buyer from San Diego! I appreciate you and am tickled this image has made its way to the West Coast!!
Poitiers, B2 - France
Very beautiful!!
Philadelphia, PA - United States
Congratulations on your sale!!
Normal, IL - United States
Nicely concise and uncomplicated. Alllows ones imagination free rein. Congratulation on the sale.
East Tilbury, Es - United Kingdom
Fine work..Congratulations on your sale..well done!
Haddam, CT - United States
Congratulations, Toni!
Duncan, OK - United States
Thanks so much everyone! I also love getting the comments because then I can go visit your sites and am inspired each time!
Silverthorne, CO - United States
Niagara Falls, NY - United States
Congrats !
Halifax, WY - United Kingdom
Congratulations on your sale! :-D
Mesa, AZ - United States
Congratulations on your sale
Budapest, H - Hungary
Congratulations on your sale.
Duncan, OK - United States
Thank you again to another wonderful buyer in New York! I appreciate you! Enjoy the print and if you ever want to post a photo of it in its new home on display, feel free to on my facebook page!
Duncan, OK - United States
Thanks again for another wonderful sale of this image!! Thanks to all the congratulation comments too for noticing!
Loveland, CO - United States
'Like!; Congratulations on your $ale! (v)
Philadelphia, PA - United States
Congratulations on your sale!!!!
GTA, ON - Canada
Saw it a million time...never in such an amazing way. Great job!
Budapest, H - Hungary
Congratulations on your sale......................Odon.
Loveland, CO - United States
'Like!' Congratulations on your $ale!
Omaha, NE - United States
Love this, congratulations.
Budapest, H - Hungary
Congratulations on your sale............Odon.
Voorhees, NJ - United States
Congrats on your sale!!! -Kim
Duncan, OK - United States
Thanks everyone! Thank you to the buyer! I love this print, hope you enjoy it too!
Boyertown, PA - United States
Sweet shot, Toni! Congrats on your sale!
Thanks Trish!!
Las Vegas, NV - United States
Not sure what you mean Scott?
Phoenix, AZ - United States
Beautiful with a perfect title Toni, Congrats on your sale :)
Thank you Chrisann!
St. Johns, NL - Canada
Congratulations on your sale!
B.S., MO - United States
Congrats on your sale! :)
Richfield, OH - United States
Congrats, Toni! Nice composition!
Alexandria, VA - United States
Very nice Toni, congrats...
Thanks JC!
Orange, CA - United States
nice, congrats on your sale
Thank you very much Carl!
Please Wait...
Beverly Hills, CA (United States)
Sign up for our newsletter for exclusive deals, discount codes, and more:
Unsubscribe at any time.
Server Status OK
Copyright © 2015 FineArtAmerica.com - All Rights Reserved


text: Authentic loft living at its finest and most luxurious! Custom designed three-level unit at 66 Bell captures all of the historic building's original texture and character. Enjoy unobstructed views of Elliott Bay and the city skyline from your own large private terrace. Inside the loft has exotic hardwood floors, an amazing gourmet kitchen with recycled glass counters, huge master suite with opulent, spa-like bath and fine finish work that contrasts elegantly with exposed structure and brick.


text:
John Amos Jones
Position: P
Height: 6-2 Weight: 197 lbs.
Born: July 9, 1947 in Louisville, GA
High School: Louisville Academy
College: Georgia (school history)
Drafted by the Houston Oilers in the 4th round (92nd overall) of the 1970 NFL Draft.
Weighted Career AV (100-95-...): 11 (6742nd overall since 1950)
Promote your website or business by sponsoring this page for $5 on Pro-Football-Reference.com. Your message will replace this ad.
The research for this page was done by Scott Kacsmar.
Read his extensive three-part article (Part I - Part II -
Part III) for full details.
View complete leaderboards for game-winning drives and comebacks.


text:
The Spanish War and San Pedro
Published on July 12th, 2013 | by Zamná Ávila
One hundred and fifteen years is enough. It was 115 years ago that the United States launched it's first overseas, some say, imperial war, the Spanish-American War. Besides giving the U.S. military control over the Philippines and [&hellip... Read More →


text:
Notre Dame Stadium
Purpose: Competition
Capacity: 80,795
Attendance Record: Sold out for 206 consecutive games
Sq. Ft. : 370, 371 gross
Year Opened: 1930
Architect: Osborn engineering company
Year Added: 1997
Architect: Ellerbe Becket, Inc., of Kansas City, Mo.
Surface Type: Natural Grass
Stadium History
Stadium Seating Chart
Ticket Information
ADA Information
For all the legendary players and memorable moments it has hosted on its bluegrass turf over the past 437 games, Notre Dame Stadium has unquestionably developed a lore of its own. The stadium, which celebrated its 80th anniversary in 2010, continues to be one of the most recognizable and revered structures in the world of sport.
It was the success of Knute Rockne's football teams that prompted the addition of the original Notre Dame Stadium to the University's athletics plant back in 1930. The spirit that was imbued by that Rockne era - and has been sustained by seven Heisman Trophy winners and dozens more All-Americans who have competed on that turf - has changed little in eight decades of football at Notre Dame Stadium.
Originally designed by Osborn Engineering Company - the same firm that designed Comiskey Park in Chicago and New York's Yankee Stadium and Polo Grounds - the total cost of construction exceeded $750,000 and it was patterned on a smaller scale after the University of Michigan's stadium. The 1996 season was the final one played with the customary 59,075 fans at Notre Dame Stadium. A $50-million expansion adding over 21,000 seats was completed before the 1997 kickoff, bringing capacity to its present-day 80,795.
The Stadium measures a half-mile in circumference, stands 45 feet high and features a glass-enclosed press box rising 60 feet above ground level and originally accommodating 264 writers plus facilities for photographers and radio and television broadcasters. There are more than 2,000,000 bricks in the edifice, 400 tons of steel and 15,000 cubic yards of concrete. The total cost of construction exceeded $750,000.
Though Rockne had a chance to coach in the new facility only in its initial season of use, he took a personal hand in its design. The sod from Cartier Field was transplanted into the new Stadium, but Rockne insisted on its use for football only. He kept the area between the field and the stands small to keep sideline guests, as he called them, to a minimum - and he personally supervised the parking and traffic system that basically is the same one in use today.
Notre Dame Stadium, maybe the most renowned college football facility in the nation, now qualifies as one of the most up to date as well, thanks to a major addition and renovations that boosted its capacity to more than 80,000 beginning with the 1997 campaign. The 1996 season was the final one played with the customary 59,075 fans at Notre Dame Stadium. A $50-million expansion adding over 21,000 seats was completed before the 1997 season kickoff. To upgrade on the 1997 renovation, two new scoreboards were installed in both end zones before the 2009 season that utilize the latest in LED-screen technologies.
Elements of the construction included:
Casteel Construction Corp. of South Bend was the general contractor for the project. Ellerbe Becket, Inc., of Kansas City, Mo., was the architect. The project was financed primarily by the November 1994 issuance of $53 million in tax-exempt, fixed-rate bonds. The bonds were sold in 26 states and the District of Columbia, with more than 20 percent sold to retail buyers and almost 80 percent to institutional buyers.
The incremental revenues from the expansion will exceed the debt service on the bonds by $47 million over the next 30 years, allowing the project not only to pay for itself, but also to generate $47 million for academic and student life needs.
Entering 2014, the Irish have played before a sellout crowd at Notre Dame Stadium in 237 consecutive games and 285 of the last 286 home contests have been played before a capacity crowd. Every home game since 1966 has been a sellout except one - a 1973 Thanksgiving Day matchup with Air Force. Notre Dame has played 437 games inside Notre Dame Stadium and compiled a 325-107-5 record (.749).
- About ND Athletics
- Academic All-Americans
- Academics News
- Aerial Lift Safety
- Annual Report
- Atlantic Coast Conference
- Blog
- Business Office
- EADA Report
- Facilities
- General News
- Hockey East Conference
- Irish Extra
- Media Relations
- Monogram Club
- Recent News
- RecSports
- Safety Protocol
- Staff Directory
- Student Welfare and Development
- Sports Performance
- Equipment
- Fan Center
- Football Game Week Central
- Summer Camps
- Kids Club
- Traditions
- Play Like a Champion Today
- Donation Requests
- Alumni Association
- Game Day
- Promotions
- Composite Schedule
- Fighting Irish Toolbar
- Wallpapers
- ND Browser Theme
- Sync Schedules


text:
editor's review
2 comments
PureOS is an open-source operating system derived from the highly acclaimed Debian GNU/Linux distribution and designed with the new Linux user in mind. It features two editions, one with the GNOME desktop environment, and another one with the Openbox window manager.
It is available only for USB devices
The OS is available only for USB devices, as it is distributed as zip archives that contain the directory structure of the distribution, ready for deployment on a USB thumb drive of 1GB or higher capacity.
Detailed installation instructions about how to create a bootable USB device are provided by the developer on the readme.txt file distributed along with the USB directory structure.
Choose between GNOME or Openbox as the default desktop environment
The user can choose between GNOME or Openbox as the default desktop environment for PureOS, simply by downloading the respective zip archive from the downloads section on Softpedia.
Default applications on the GNOME edition
The GNOME edition comes with the Chromium web browser, Gedit text editor, Evince document viewer, Eye of GNOME image viewer, File-Roller archive manager, Nautilus file manager, GNOME MPlayer video player, GNOME Tweak Tool and Synaptic Package Manager. It also includes support for reading and writing from/to NTFS partitions.
Default applications on the Openbox edition
The Openbox edition includes the Chromium web browser, Leafpad text editor, GNU sed stream editor, Squeeze archive manager, Thunar file manager, as well as Synaptic Package Manager. This flavor also includes support for reading from and writing to the NTFS partitions of a Microsoft Windows operating system.
Bottom line
Summing up, PureOS is indeed a pure operating system, a one of a kind distribution of Linux that provides users with the choice of two graphical desktop environments, it is low on resources and includes just the right amount of applications.


text:
Nice to meet you here at Audiko.net, where you can easily find the best ringtones for your smartphone. Today we have a ringtone of "Because You Live" by Jesse McCartney as well as 827 other ringtones by Jesse McCartney. "Because You Live" is a hit from the "Beautiful Soul" album that was composed by Jesse McCartney at their label together with other 16 tracks. You can listen to all 8 Jesse McCartney – "Because You Live" ringtone variations available here and download it for free right to your smart phone. You can also find other 6 albums produced by Jesse McCartney for all time. "Because You Live" is referred to Pop, and we bring you a huge amount of Pop compilations absolutely for free. And finally, we have collected lyrics for this track and you can view it here as well. So feel free to browse, listen, download ringtones at Audiko.net. Make your phone sound cool!
Jesse McCartney Because You Live Ringtone
Similar Ringtones
Browse Genres
American Pop Pop Rock R&B Rock Teen Pop
Because You Live 3:30
Jesse McCartney
Albums by Jesse McCartney
Jesse McCartney
30 Jun 2003
Top ringtones by Jesse McCartney
- Jesse McCartney - Beautiful Soul
- Jesse McCartney - License
- Jesse McCartney - Just So You Know
- Jesse McCartney - She's No You
- Jesse McCartney - Body Language (feat. TPain)
- Jesse McCartney - Up (OST Step Up 3D)
- Jesse McCartney - Leavin'
- Jesse McCartney - The best day of my life
- Jesse McCartney - Right Where You Want Me
New ringtones
- Unknown - 100_kila_feat_dj_diamondz_-_аз_съм_6_official_hd_video_
- BANUS - lynyrd-skynyrd-free-bird372484
- Hacienda - Quizás quieres saber
- Breaking Bad - Lydia
- ring - New Ringtone 1
- tragedie - Tragedie - OH
- Nico & Vinz - Am I Wrong
- Sam Feldt - Show Me Love [feat. Kimberly Anne]
- tragedie - OH
- Zanon SHK - Ale Valencia


text:
Chemical weapons concernsSeptember 06,2013
Chemical weapons concerns
All arguments in favor of aerial spraying against mosquitoes again this year are based on two unfounded assertions. One, that the chemicals used (sumithrin, piperonyl butoxide, and naptha) are safe at the levels being applied; and two, that the pesticide is effective at reducing the targeted mosquito population.
No studies have been done to prove the pesticide is safe. Sumithrin belongs to a class of neurotoxins called pyrethroids that are known to have a long list of negative health affects including nerve, kidney and liver damage, and which function as endocrine disruptors playing havoc with the bodys hormones. Small children and pregnant women are especially vulnerable.
Piperonyl Butoxide is classed as a possible human carcinogen by the EPA and is toxic to bees and fish even at concentrations of one part per million.
Naptha (aka white gas or Coleman fuel) is also classified as a possible human carcinogen, with its own long list of health impacts.
For some, yearly exposure to these chemicals would be an acceptable price to pay if they could at least rest assured that the threat from EEE would be reduced. Unfortunately, there is little evidence for the effectiveness of the pesticide at reducing human infection rates, and at least one study showing that application of this pesticide actually resulted in an increase in the targeted mosquito population.
Once again, I face the option of feeding my growing toddler seriously contaminated food from our gardens and orchards. or tossing the entire harvest and buying less healthy, more expensive food from the supermarket.
I find it unconscionable that in the year 2013 in the United States of America, people find it acceptable to douse unwilling participants with toxins based on such flimsy evidence of a greater good and such obvious evidence of potential harm.
Dan Brett
WhitingMORE IN Letters
Recent testimony to Congress by economics professor Laurence Kotlikoff indicated America is... Full Story
The green movement in Vermont is guided by fear and greed. Full Story
I am writing to call attention to a couple of groups of awesome professionals in our community. Full Story
- Most Popular
- Most Emailed


text:
Royal Baby: Kate Middleton Gives Birth to Boy
UPDATED: After going into labor early Monday, the Duchess of Cambridge and Prince William have welcomed their first child.
LONDON – Kate Middleton has given birth to an 8-pound, 6-ounce boy, the British royals announced late Monday.
The Duke of Cambridge was present for the birth, which occurred at 4:24 p.m.
PHOTOS: London's Royal Baby Frenzy
The Queen, The Duke of Edinburgh, The Prince of Wales, The Duchess of Cornwall, Prince Harry and members of both families have been informed and are delighted with the news.
Her Royal Highness and her child are doing well and will remain in the hospital overnight.
"We could not be happier," Prince William said in a brief statement issued late Monday night. And TV networks quoted a Buckingham Palace spokesman as saying: "The Queen and Duke of Edinburgh (Prince Philip) are delighted at the news."
The BBC interrupted its programming on BBC One during Panorama. Commercial network ITV did not interrupt its regular soap opera Coronation Street with the announcement.
In the U.S., ABC and NBC broke into programming to announce the news, while Fox and CBS did not.
In line with royal tradition, the announcement was not made until after Queen Elizabeth II had been informed about the baby's birth.
Kensington Palace issued a news release containing the details about the royal baby shortly before the formal bulletin left the hospital to be displayed on an easel outside of Buckingham Palace, ITV News reported.
ITV reported that the baby's name would be announced "in due course." No further details were provided.
The palace had announced early Monday that Middleton had gone into the early stages of labor. She arrived at St. Mary's Hospital in Paddington, London, with Prince William around 6 a.m.
PHOTOS: The World's Most Notable Princes and Princesses
Details of Prince William's own birth 31 years ago had been shared with the world the same way.
U.K. TV commentators on Monday had discussed the process, acknowledging that it may seem old-fashioned in the age of Twitter.
Never miss a story. Stay up-to-date with THR's Daily Headlines.
Must Reads
A Widow's Threats, High-Powered Spats and the Sony Hack: The Strange Saga of 'Steve Jobs'
Rick Moranis Reveals Why He Turned Down 'Ghostbusters' Reboot: "It Makes No Sense to Me"
Hollywood's 100 Favorite TV Shows
Dan Rather Reflects on His Dramatic CBS Exit That Inspired 'Truth': "I Have a Lot of Wounds"
'The Martian's' Matt Damon Talks 'Bourne' Return, Politics and PC Flubs: "Oh My God, I Look Like an Asshole"
The Insane Battle Over Sam Simon's Will — Should the Simpson's Co-Creator's Trust Pay $140,000 Per Year For One Dog's Care?
'Empire's' "Batshit Crazy" Behind-the-Scenes Drama: On the Set of TV's Hottest Show
Hollywood's Notable Deaths of 2015


text:
The second of four epic live-action adventure series on Netflix, Jessica Jones also stars David Tennant, Mike Colter, Rachael Taylor, Carrie-Anne Moss, Eka Darville, and Erin Moriarty.
The Internet loves a man who is comfortable showing every side of himself.
The actor talks about building chemistry with his on-screen lover, Miguel Ángel Silvestre.
Co-stars Jennifer Hudson and newcomer Cynthia Erivo will also make their Broadway debut.
The prequel series to the 2001 cult film premieres July 31 on Netflix
Wet Hot American Summer: First Day Of Camp, the prequel that will fill your summer with squeals
In a frank, unvarnished conversation with Out, the two iconic women of the screen swap stories of their years in the trenches of Hollywood, from skinny-dipping with Greta Garbo and the secret origins of Jane Fonda's workout to Lily Tomlin's beautiful breasts and the pleasures of working together on their new Netflix series, Grace and Frankie.
Jane Fonda and Lily Tomlin reunite to star in the new Netflix series Grace and Frankie.
The Netflix comedy stars Jane Fonda and Lily Tomlin as two women whose husbands reveal they are gay
...And five other things you should know today.


text:
Sure the original was something fresh, new, and somewhat original. But the sequels have been anything but. Yeah i know it's high octane fun, but you can say the same thing about Michael Bay films. Am i saying that these sequels are as bad as Michael Bay films? No, but each one offers nothing new, well, unless you count drifting, and that isn't saying a lot. Hopefull this new installment can bring something fresh to the table.
I never thought i would say this, but i actually enjoyed this movie. I went in with low expectations, and came out pretty damn satisfied. Sure the movie had a lot of the same moving parts, but what really made this one stand out is how it actually changed the pace of how they normally do things.
First, they didn't have a damn drag race every 10 minutes. In fact, they barely had any. Which really is a genius idea, because when the time did come to have an awesome driving sequence, you were begging for it. Finally, someone with brains stepped into this movie and said let's save all of our bullets and unleash them in the end.
So with a series that relies heavily on their driving sequences and less on their script, how do you keep your audience entertained? Well, the first step is to incorporate another major actor, enter The Rock. Next, you really need to buff up your script. Okay, here is where it gets both good and bad. It's good because the movie takes a ton of it's credit from the "Ocean 11" films. Yeah, it's stealing an idea, but it injecting more action into it, which is pretty cool. But the reason why i say it's also bad, is because it's still packed with bad cheesy one-liners, poor acting, and some really tarnished plot outlines. But does that take anything away from the fun.......not really.
Bottom Line, okay people, here is your first action movie worth seeing this year. No, i am not one of those people who hold these 'Fast and Furious' films on a high pedestal. Not since the first one have i given anything over a decent review. But i can say with confidence that this one is actually worth your hard earned dollar. Sure it's slightly cheesy, packed with impossible action, and sure it steals some plot outlines from other films, but i like i said earlier, it's still fun to watch. So with that being said, the question remains.....is this the best one in the series? I still say no, but this movie comes damn close. Closer that any of the other ones, thats for damn sure. On a time line, this should have followed up the original
Fast Five
Action / Crime
Fast Five
Action / Crime
Former cop Brian O'Conner partners with ex-con Dom Toretto on the opposite side of the law. Since Brian and Mia Toretto broke Dom out of custody, they've blown across many borders to elude authorities. Now backed into a corner in Rio de Janeiro, they must pull one last job in order to gain their freedom. As they assemble their elite team of top racers, the unlikely allies know their only shot of getting out for good means confronting the corrupt businessman who wants them dead. But he's not the only one on their tail. Hard-nosed federal agent Luke Hobbs never misses his target. When he is assigned to track down Dom and Brian, he and his strike team launch an all-out assault to capture them. But as his men tear through Brazil, Hobbs learns he can't separate the good guys from the bad. Now, he must rely on his instincts to corner his prey... before someone else runs them down first.
Uploaded By: Bokutox
Downloaded 367,902 times
June 9, 2012 at 12:32 pm
Tech specs720p 1080p
Movie Reviews
The first sequel in the series that's actually worth your dollar
Sure the original was something fresh, new, and somewhat original. But the sequels have been anything but. Yeah i know it's high octane fun, but you can say the same thing about Michael Bay films. Am i saying that these sequels are as bad as Michael Bay films? No, but each one offers nothing new, well, unless you count drifting, and that isn't saying a lot. Hopefull this new installment can bring something fresh to the table.
Not a hint of realism...
Now, this movie had its strengths... and its weaknesses... First off, great acting. All actors were superb. Good action scenes, nice action shots and cinematography. The script was a bit shabby.. But I need to vent about my main issue with this title... It doesn't have any realism in the movie at all. None.
First example: A car drives in front of a bus, they were going fairly fast but it should not have had THIS outcome.. The bus hits the back of car. The bus is then propelled 20-30 feet into the air, lands, and is ripped to shreds. No fatalities either, and somehow they snuck an inmate out from the scene of the crime without a soul knowing about it. The bus flying through the air from a minor collision like that is what really angered me.
Second example: An all-terrain vehicle speeds along next to a train. Not only does it stay with the train for a good 10 minutes in the exact same spot without any trouble adjusting to the trains speed, but it is clamped on with enough stability that a team of 2 can use plasma cutters to cut a wall large enough to smuggle a car out of. I liked the idea, but it wasn't put together properly. To make things worse, after a few cars are smuggled out, a final car, with about 2 feet of room to gain momentum with, had enough speed to make an enormous leap off of the train and land perfectly with smooth sailing the rest of the way. This is followed by two men in the car flying off of a cliff large enough to kill anybody landing in the water below. In the real world, limbs would have been lost. They land like it was nothing.
Third example (this takes the cake): An armored vehicle plows through the walls of a police station.. I'm okay with this. Two Chargers pull up, chain themselves to this 10 ton vault, and have enough traction and friction to pull the entire vault off of the wall and out of the building. In a real world situation, the cars would make no progress and spin out, or the chains would break... and they take off! Speeding through Rio with a 10 ton vault, wrecking down buildings, smashing cars, dodging people, and smashing everything else in sight. This really irritated me. It even went through a large concrete building, the chain being strong enough to tear the building apart. I have no clue how this is even plausible. The vault then flies around smashing everything in its path again, still being pulled by these two wimpy cars. Eventually, the police catch up. The drivers suddenly have the dexterity to move the vault and fling it to their will. They smash some more cop cars, cause more collateral damage, and then decide they are going to split up. One Charger takes the vault on its own, and another takes off in the opposite direction. This solo driver suddenly has even more dexterity, and flings the vault around some more, taking out cop cars left and right, killing people exactly how he "planned it". Like I said earlier, if you are pulling a vault the size of a building around in a solitary car, the tires would not have enough traction to continue, and the car wouldn't have enough horsepower to drag that monstrosity around.
It goes on and on, I wish I could actually watch this movie without those three examples. It would be great. I loved the rest of it. But, save all this junk for a sci-fi movie... I can stand small amounts of movies being non-realistic, there are exceptions.. But not taking realism into consideration at all is a bit of a downer. Apparently physics don't apply to anybody living in Rio De Janeiro.
I wasn't expecting much from this...but WOW.
I enjoyed the movie so much, that I came onto IMDb and registered myself just so that I can post a review.
The movie was packed with jaw dropping, eye popping action from beginning to end. The drama had a mix of sadness, comedy and seriousness which were all mixed in together so beautifully to give a consistency to keep the viewer starring at the screen and being involved in the movie rather than daydreaming about other things.
In my honest opinion I would say that it is the best Fast & Furious movie to date.
I want to go see it again!
(by the way, I realise that this isn't the best review in the world or might even be an awful review, the point is that I enjoyed the movie thoroughly and felt I should contribute to it's high average ratings).


text:
The Alaskan Lodge
No prices found through our partners. Please contact the business directly or check some of our recommended alternatives.
Travelers also recommend:
TripAdvisor Reviews The Alaskan Lodge Kenai
Travel Blogs from Kenai
~~Windy, wet, cold and very COOL!~~
... by sound.
Mt. Redoubt, an ACTIVE volcano, overlooks Kenai and boasts an elevation of over 10,000 feet. It has erupted four times since first being observed: 1901, 1966, 1989 and 2009.
Kenai River Estuary serves as a protective area for over 150 species of birds and mammals.
And then there is the elusive caribou...if you are lucky.
Mountains, and salmon, and bears, oh my!
Moved from Ninilchik to Nikiski-Captain Cook S R A to get away from the crazies-locals and tourists all trying to get to the Kenai River to catch salmon any way the law will allow.Dip netting, flossing, snagging-dynamite is still illegal in Alaska. The Swanson River and Bishop River in Captain Cook SRA were peaceful and full of trout the only draw back was there were reports of bear activity, so Sid found a buddy (campground host) with a shot gun. ...
Cold, wet, and looking for something to do
... Lake, a free National Park campground with 4 sites at the dead end of a gravel road. One site was open, it had a wonderful lake, mountain view. It looked like a good lake to fish but 25 MPH winds and rain discourage me from trying to fish it.
Next morning we got an early start for Soldotna. It is the height of salmon season so campsites are at a premium. We decided we would park the RV at Fred Myers and then explore what camping was ...
Exploring in the Kenai
... out the availability as it was going to be rather late when I came back through the town. There were several rooms available so I raced off to try to beat the darkness. 16 miles up the road I passed through Nikiski where many oil companies explore & produce crude oil & natural gas from both on & off shore facilities. I stopped just long enough to take a couple of photos. I knew I'd reached the end of the road when I saw a sign saying "End" but I couldn't see ...
Quit Your Bitchin - We've Got Beaches
... birds with their shore lunch, a moose crossed the river right in front of us. My thought: moose meat for lunch. I did a long cast to try to hook the moose, but he must have been talking to the salmon, because he didn't bite either. Oh well, could have been a blog about fishing for salmon and hooking a moose for lunch. Moose fishing, another new experience for Judy and Roger. So, I'm both a moose mover and moose fisherman ... only in Alaska.


text:
A software publisher's guide to protecting software products against the top 8 piracy threats
This white paper covers how organizations can seize business opportunities presented by Bring Your Own Device while eliminating the associated risks.
In this step-by-step guide, you'll learn how to deploy a unified and efficient data protection platform that can be leveraged to secure all data types residing in or moving between your physical, virtual, cloud and hybrid environments.
We live in a world of sharing, and sometimes we share a
little more than we should. Of course, we're not only referring to social media
posts here; this also includes what is happening with your corporate data
assets too.
With your organization's sensitive data being stored, sliced
and diced, and shared more than ever before, you must have a way to keep it
safe, especially in cloud and multi-tenant environments. Approved users and
processes need to be able to leverage the data that's available, while you
ensure any high-value, sensitive information, such as intellectual property,
personally identifiable information, and company financials, remains on lock
down wherever it resides.
We call this unsharing your data, and in our free ebook, we
outline the steps enterprises need to follow to unshare and protect your
sensitive data. Read it today to learn the must-follow enterprise encryption
best practices!
In all, 888 data breaches occurred in the first half of 2015, compromising 245.9 million records worldwide, according to the latest findings of the Breach Level Index. The number of breaches was relatively flat compared with the last six months of 2014 (892) but was up by 10% compared to the 803 data breaches in first half of 2014.
The report shows large, headline-grabbing data breaches continue to expose massive amounts of records. The biggest breach in the first half of this year, which scored a 10 on the Breach Level Index magnitude scale, was an identity theft attack on Anthem Insurance that exposed 78.8 million records. Read the report to learn more about the top breaches, the industries impacted most, the most prevalent types of breaches in the half, and much more.
This document presents how Gemalto addresses key security issues and the measures taken to ensure the security and robustness of SafeNet Authentication Service (SAS) as a cloud service offering.
This paper presents findings from testing of up to 10 Gemalto SafeNet HSMs with an F5 BIG-IP 7200 appliance running TMOS version 11.6, and recommendations based on the results.


text:
NYCC: Vin Diesel, Wood & More Make "The Last Witch Hunter" the Stuff of Legend
Showing results 1-11 of 11
Director Duncan Jones discusses the unique challenges of crafting a film around a war game that has no clear good or bad guys.
Director Duncan Jones and the orcs and humans of "Warcraft" discussed Legendary's film adaptation of the massively popular video game in San Diego.
Travis Fimmel's human Durotan and Toby Kebbell's orc Lothar are revealed in new posters from the forthcoming video game adaptation.
Legendary will screen footage from its upcoming films at this year's Comic-Con International, plus a Q&A featuring cast members from each film.
The voice of Orgrim Doomhammer says the movie "will more than satisfy" its gamer-based audience.
"True Blood" alum Robert Kazinsky portrays Orgrim Doomhammer in director Duncan Jones' adaptation of the popular video game series.
Character details and posters were unveiled for "Warcraft" at BlizzCon Friday, teasing the March 2016 release of the MMORPG adaptation.
Gal Gadot is "Batman/Superman's" Wonder Woman; "Amazing Spider-Man 2" trailer teases future villains & more.
Take a tour of the "Agents of S.H.I.E.L.D.'s" airborne Bus! Is a "Gotham Central" series in the offing? Oni's "Ghost Projekt" to become a NBC series. Also, a new glimpse of "X-Men: Days of Future Past" and more.
James Spader cast in "Avengers: Age of Ultron!" Vin Diesel discusses Groot in "Guardians of the Galaxy!" Will Amanda Waller show up in "Arrow?" Plus, Transformers 4 & more!
Archives: All | Comic Books | TV/Film | Video Games | Web Comics


text:
Smoke Grey Slouch Beanie
(approx. $6.01 or €5.45)
- In Stock
- Usually Ships in 1-2 Days
- UK & Worldwide Delivery
- Product Type: Beanie
- Product Code: 47290
- Size: One size Fits All
Keep your head warm in style with this cool accessory! Smoke grey and ribbed, this slouch beanie is a great way of accessorising your favourite outfit this winter.


text:
Men's Carolina® 6" Lytning Waterproof EH Work Boots, Brown
Item # WX2-422001
- Google+
- Details & Specs
Carolina® 6" Lytning WATERPROOF EH Work Boots are lightweight, flexible and protective for MUCH LESS!
These Lytning Boots are not only built to work, they're built to protect you while you work. They're loaded with features to keep you safe and comfortable on the jobsite... and they weigh in at a super-light 19 ozs. for easy moving! The waterproof SCUBALINER® keeps moisture out, for bone-dry, comfortable feet all day. These Work Boots also boast a slip-resisting outsole and electrical hazard protection to keep you out of harm's way.Clock in:
- Oiled nubuck leather uppers
- Waterproof SCUBALINER
- Breathable mesh lining
- Removable blown-EVA footbed
- Electrical hazard rated
- Non-metallic shank
- External injection-molded arch support
- Cement construction
- Slip-resistant rubber outsole for top traction
- Pull-on loop at back.
- Each approx. 6 1/2"h., 19 ozs.
State Width: medium or wide; and Size, as available in the Shopping Cart. For Boots you can depend on, order ONLINE today!
- Reviews
Men's Carolina 6 Lytning Waterproof EH Work Boots, Brown is rated out of 5 by 5.Rated 5 out of 5 by TERRI from My son actually ordered the boots. he said they are lightweight and comfortable. Hope they hold up for him, he is very hard on boots.Date published: 2014-04-27Rated 4 out of 5 by JEFFREY from I am very happy with the boots. they are comfortable and lightweight.Date published: 2014-04-17Rated 5 out of 5 by JAMES R from Great boots, and truly are waterproofDate published: 2014-03-29Rated 1 out of 5 by MARK from size runs small had to return and order next size up.Date published: 2014-03-29Rated 5 out of 5 by REGINA from We were looking for something that was light weight but tough and they seem to be bothDate published: 2014-01-04
<!--BVSEO|dz:Main_Site-en_US|sdk:v184.108.40.206-n|msg:Error: Request errored out - The remote server returned an error: (403) Forbidden. -->
- Articles & Tips
Don't Forget
Thorogood Shock Zone InsoleNon-Member $13.99 Buyer's Club $12.59
Peet Boot / Shoe DryerNon-Member $49.99 Buyer's Club $44.99
Softsole Trim-to-fit Boot Laces, Brown / WaxyNon-Member $3.99 Buyer's Club $3.59
You May Also Like
Men's Irish Setter® 6" EH Work Hikers, Mocha Crazy HorseNon-Member $104.99
Guide Gear Men's 8" Soft Toe Leather Hammer Boots, WaterproofNon-Member $89.99 Buyer's Club $80.99
Men's Wolverine Marquette 6" Non-steel Toe Work Boots, BrownNon-Member $79.99 Buyer's Club $71.99


text:
A pair of SBCC football players from opposite ends of the Earth announced their commitments to four-year schools on Friday in a press conference at La … [Read more...]
SBCC's Pettit, Wishnowsky sign with D-1 programs
King, Wishnowsky named All-State from SBCC
Elijah King and Mitch Wishnowsky of SBCC have been named to the All-State Region IV team by the California Community College Football Coaches … [Read more...]
SBCC's Arnell headed to North Dakota
SBCC safety Zach Arnell has signed to play football for the University of North Dakota and will leave in early January to enroll in school and attend … [Read more...]
Five Vaqueros make all-conference teams
Ivan Malinarich-Campos, Elijah King and Mitch Wishnowsky received first-team All-American Pacific League honors in football. Campos, a 6-4, … [Read more...]
Late score by Cerritos beats SBCC in Golden State Bowl
SBCC rose to the occasion and led Cerritos for most of the way in the Golden State Bowl football game on Saturday night in Cerritos. But the … [Read more...]
Vaqueros receive postseason Golden State Bowl invitation
SBCC received an invitation to the CCCAA football bowl party on Sunday and the Vaqueros will play Cerritos in the Golden State Bowl. Kickoff is set … [Read more...]
Glendale jumps on SBCC early, wins battle of Vaqueros
Glendale came out strong on Saturday afternoon, scoring touchdowns on its first three possessions, and built a 30-7 halftime lead on the way to a … [Read more...]
Press Luncheon: This 'Big Game' had everything
Ivan Reyes received the Gary Blades Memorial MVP Trophy, SBCC head coach Craig Moropoulos marveled at the sell-out crowd, and San Marcos … [Read more...]
SBCC gets sloppy, stumbles at Santa Monica
Santa Barbara City College turned the ball over five times on Saturday and Santa Monica took advantage to post a 37-21 football victory in a … [Read more...]
Team of the Month: SBCC getting it done with 'Every Man' approach
Texas A&M football has a tradition called the 12th Man, which started when a former player was called from the stands during a game against the … [Read more...]


text:
Letter: ATK's future: Company needs to have a solution that is good enough to compete
SpaceX, Associated Press
ATK is crying because three other companies won big contracts from NASA. As usual, ATK and its Rep. Rob Bishop are claiming that the others won by unfair lobbying. Talk about the pot calling the kettle black!
ATK has a long history of wining and dining (and sometimes whining) its way into government contracts. In the 1970s, ATK's predecessor won the shuttle contract largely because Utah Sen. Frank Moss chaired the relevant committee. NASA's technical people favored another solution, but Moss brought home the bacon for Utah. Bishop is continuing in the same corrupt history.
ATK and Bishop can't conceive of anyone winning a government contract fairly on the technical merits because ATK's biggest win didn't happen that way.
Now, in truth, Boeing will likely not succeed for NASA. But the other two winners are innovative and may actually work out. Sierra Nevada Corp. makes the unique hybrid engines used by SpaceShipOne, the first private spacecraft, and its successor SpaceShipTwo which will begin private flights for paying customers soon. SpaceX builds the Dragon, the first privately developed craft to dock with the International Space Station, and the well-regarded Falcon launchers.
The future belongs to the nimble and innovative. Companies like Sierra Nevada, SpaceX, Virgin Galactic, XCOR, Armadillo Aerospace and LaserMotive are the future of space flight. If ATK's solution is really so great, they should be able to compete commercially even without NASA pork.
Steve Setzer
- My view: Misinterpretation of Second...
- My view: Utah should not raise minimum wage
- Letter: Greater security
- In our opinion: Suspended Alaskan oil drilling
- Letter: Our French Revolution
- Lois M. Collins: The 'death' of faith may be...
- John Florez: Lawmakers neglect their moral duty
- Jay Evensen: Here's why we should fear...


text:
The Best Gourmet Vegetarian Food, Period.Posted on 08 / 14 / 2014
The Tomlin's philosophy of vegetarian food is that it doesn't have to be boring- vegetarians want and deserve interesting, creative food. Their produce is from their garden or locally sourced, as is the cheese (vegetable rennet) and wine.
But back to the food- dinner is simply AMAZING, and a very good deal. The B&B is tucked in a tiny village in the countryside of mid-Atlantic France, but it absolutely worth the trip (a 3 hour train ride from Paris). Go there just to eat, or they offer vegetarian cooking classes as well. Go.
Cons: Far from where I live (North America)


text:
About Samsára
'Re-awakening to Life'
'Samsára' in Sanskrit literally means 'continuous flow'. It is the repeating and re-awakening to the cycle of life (rebirth).
Samsára Beauty & Holistic Therapy located within Eden Fitness Centre for Women, encourages the perfect synergy of harmony and energy between the mind and body and re-awakening of life. After enjoying a therapeutic or holistic treatment at Samsára, you too can experience the physical & psychological benefits of holistic therapy.
Incorporating massage techniques and stretches learnt from international training in Bristol, London, China and Thailand, experience has been gained over nearly ten years working in spas and managing salons in Greece (Neilson Holidays), New Zealand (Formé Spa), locally (Weston-super-Mare) and on cruise ships (Celebrity Solstice). Every treatment is adapted to meet your needs and expectations and help to improve your overall health and wellbeing. Ask about vegan-friendly products.
Evening & Weekend appointments available. Appointments for men Saturdays only after 2pm