text:
|Project Name
|Price (USD)
|Project Name
|Price (USD)
|Vietnam Stock Exchange Real Time data feed
|...looking for the hanoi and ho chi minh stock exchange real time data feed. We need level 2 data. If you
|C Programming, .NET
|Mar 21, 2010
|Mar 21, 2010Ended
|Financial real-time feed
|*** Develop real-time feeds to our application using our API. *** The task is to integrate Interactive...only the feed which consists of: -Real-time quotes of all instruments -Historical data -Time &...preferably has experience in financial software and real-time programming in previous tasks. We supply you
|C Programming, Data Processing
|Oct 17, 2005
|Oct 17, 2005Ended
|XML feed - Cron Job, and Real Time Inventory
|...The first smaller task is to fix/create our Google Feed that is standard for Zen Cart. We need the automated...to hook up to the inventory and run a real-time inventory xml feeds to populate our Zen Cart and keep
|Jan 5, 2010
|Jan 5, 2010Ended
|Real-time stock charts in Excel
|I am using DDE links from IQ Feed into Excel. I am looking for a program that can chart the highlighted...highlighted number below in real-time. The cells dynamically update from IQ Feed and I don't have a way to chart...chart this number in real-time. Currently I have a macro that records that cell every 15 sec and then
|PHP, Engineering, Software Architecture, Software Testing, Embedded Software, MySQL
|Nov 28, 2007
|Nov 28, 2007Ended
|Integrate Real time Pricing Feed
|...process to 1. read stock prices from a real time pricing feed 2. compare the real time prices with prices...The real time pricing feed is the AmeriTrade API so the familiarity with this API or other stock pricing
|Java, Python, Linux, Software Architecture
|Sep 22, 2013
|Sep 22, 2013Ended
|CS CART XML FEED -XML Real-Time Distributor Integration
|...upgrading to CS CART 3 We have suppliers who has XML FEEDs which consists of new products, sometimes on...We need a XML FEED script written/created for our online shop so it can have real-time XML connectivity
|PHP, XML, eCommerce, Anything Goes, CS-Cart
|Oct 19, 2012
|Oct 19, 2012Ended
|...shopping cart and require someone to put in XML / RSS stock feeds from our supplier to auto add products
|PHP, Engineering, Software Architecture, Software Testing, MySQL
|Oct 27, 2007
|Oct 27, 2007Ended
|XML Feed for Stock
|...via a drop shipper. Supplier can supply stock list via RSS Feed or downloadable CSV. I am after a script...set a cron job to run once a day to update the stock listing.
|eCommerce, OSCommerce
|May 3, 2010
|May 3, 2010Ended
|real time stock prices to excel speadsheet
|...need my excel to update in real time as the stock price changes. The supply feed will come from a java applet...applet that I subscribe to. Stock exchange is canadian tsx.
|Oct 9, 2008
|Oct 9, 2008Ended
|Data Feed via XML into ZenCart
|...to work properly. Currently it does not "Real-Time" update quantities and this needs to be fixed...======================================= Data Feed CWR Electronics provides data feeds to our customers...databases with fresh data from our back-end server. The feed is located at /feeds/productdownload.php and when
|PHP, XML, Zen Cart
|Jan 9, 2010
|Jan 9, 2010Ended
|CSV file import - xml real time stock update
|We are currently working with 3 suppliers (3 csv files) and we need to add a 4th supplier to our shop. Please ask details before bidding Thanks
|PHP, XML, MySQL
|Feb 8, 2010
|Feb 8, 2010Ended
|Real time data forex and Stock data in excel
|I need to have a Stock quote from the Norwegian Stock exchange and a stock quote from NYSE and the USD/NOK...USD/NOK spot rate real time feed in excel. Someone that can help me with that? If this is something you
|C Programming, Java, Excel, C++ Programming
|Dec 10, 2010
|Dec 10, 2010Ended
|sports odds feed xml
|I need odds feed xml from bwin,bet365 by real time update. soccer,baseball, vallyball and basketball...basketball. 1*2,o/u,handicap odds feed. and live score data.
|PHP, Website Design, Graphic Design, HTML
|Sep 22, 2013
|Sep 22, 2013Ended
|need module to be built to import real time xml feed simple
|...easy to use module to be built to import real time xml feed simple api into a shopping cart in joomla...send queries real time as an http post and display information into shopping cart The XML Data Stream...Internet-based interface that uses XML structured queries to obtain information. XML Data Stream is a full-featured
|PHP, XML, Joomla
|Jun 28, 2011
|Jun 28, 2011Ended
|Stock Exchange feed display Program
|Design and test a real time data feed (simple) in real time, which shows data automatically and regularly...The live feed I am going to create will use coding generated in java Language and the live feed output...system that automatically checks the stock market exchange on a stock market exchange website and create
|Java, HTML
|Apr 19, 2013
|Apr 19, 2013Ended
|XML Silver Feed Upgrade
|...upgrade our bronze xml feed(which you coded for us about a month ago) to a silver feed, and we were wondering...information feed and the stock feed. The stock feed will not change. The Product information feed will have...displayed on the product description page: - DVD Run Time - Year Made - Actors - Languages - Audio - Su...
|PHP, OSCommerce,
|Oct 26, 2011
|Oct 26, 2011Ended
|xml feed integartion
|...looking to integrate my xml feed to sale website (e-bay etc.). I can provide the xml feed which contains all...product details to either update the website in real time or manually update once a day. I have access to...me a software which can at least convert this xml feed in press of a button and upload it bulk sale template
|XML, Visual Basic, MySQL
|Mar 25, 2013
|Mar 25, 2013Ended
|xml feed to mysql
|I have a big XML file (about 90 MB) with the dates of a affiliate apartments rent system. I need a...estructure of de XML, the script read the structure. The script will be executed 1 time per week by cron...will be very quickly system The winner give me a real solution to make this actualization very quickly
|PHP, XML, AJAX, MySQL
|Sep 8, 2012
|Sep 8, 2012Ended
|Prepare a XML feed
|...WordPress real estate theme (you can see it here: http://tipscasa.it ) that needs an XML feed implemented...com/your-ads-on-trovit/us/feed-us-homes/ http://feed.immobiliare.it/import/docs/xml-specification-legacy... Thank you very much for your consideration and time.
|PHP, XML, Wordpress, CSS, Real Estate
|Mar 20, 2015
|Mar 20, 2015Ended
|Real Time Data Feed - Server + Client Architecture
|(1) We need to develop a real time data feed architecture from server till client for based client, desk...metaquotes.net/metatrader/ for us for the National Stock Exchange of India (NSE) markets. Please go through...NSE (National Stock Exchange ) of India and then expanding as we move ahead. This data feed is already landing
|C Programming, Java, Data Processing, AJAX, SQL
|Aug 13, 2009
|Aug 13, 2009Ended


text:
updated 06/22/2011 AT 6:00 PM ET
•originally published 06/23/2011 AT 11:00 AM ET
In a revealing new ad for the upcoming season of Project Runway, Heidi Klum leaves little to the imagination.
"This is definitely sexier than past campaigns we've done," she tells PEOPLE. "I guess you could say 'Hans and Franz' are celebrating season 9."
Good thing 20 fresh designers are eager to make the superstar some clothes!
The new season, which premieres July 28 (9 p.m. ET) on Lifetime, features Klum and her trusty co-judges Michael Kors and Nina Garcia, plus mentor Tim Gunn and a bevy of celebrity judges, including Kim Kardashian, Christina Ricci, Zoe Saldana and Malin Akerman.

subset: commoncrawl


text:
|Publication number
|Publication type
|Application number
|Publication date
|5 Dec 2002
|Filing date
|3 May 2002
|Priority date
|4 May 2001
|Also published as
|Publication number
|Johannes Mulkens, Marco Moers
|Original Assignee
|Mulkens Johannes Catharinus Hubertus, Moers Marco Hugo Petrus
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Referenced by (7), Classifications (11), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
[0001] This application claims priority from EP 01304075.3 filed May 4, 2001, herein incorporated by reference.
[0002] The present invention relates generally to lithographic apparatus and more particularly to double exposure.
[0003] In general, a lithographic projection apparatus comprises a radiation system to supply a projection beam of radiation, a support structure to support patterning structure, the patterning structure serves to pattern the projection beam according to a desired pattern, a substrate table to hold a substrate, and a projection system to project the patterned beam onto a target portion of the substrate.
[0004] The term "patterning structure" as here employed should be broadly interpreted as referring to structure or means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term "light valve" can also be used in this context. Generally, the said pattern will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit or other device (see below). Examples of such patterning structure include:
[0005] A mask. The concept of a mask is well known in lithography, and it includes mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. Placement of such a mask in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the mask, according to the pattern on the mask. In the case of a mask, the support structure will generally be a mask table, which ensures that the mask can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired.
[0006] A programmable mirror array. One example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. An alternative embodiment of a programmable mirror array employs a matrix arrangement of tiny mirrors, each of which can be individually tilted about an axis by applying a suitable localized electric field, or by employing piezoelectric actuation means. Once again, the mirrors are matrix-addressable, such that addressed mirrors will reflect an incoming radiation beam in a different direction to unaddressed mirrors; in this manner, the reflected beam is patterned according to the addressing pattern of the matrix-addressable mirrors. The required matrix addressing can be performed using suitable electronic means. In both of the situations described hereabove, the patterning structure can comprise one or more programmable mirror arrays. More information on mirror arrays as here referred to can be gleaned, for example, from U.S. Pat. No. 5,296,891 and U.S. Pat. No. 5,523,193, and PCT patent applications WO 98/38597 and WO 98/33096, which are incorporated herein by reference. In the case of a programmable mirror array, the said support structure may be embodied as a frame or table, for example, which may be fixed or movable as required.
[0007] A programmable LCD array. An example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference. As above, the support structure in this case may be embodied as a frame or table, for example, which may be fixed or movable as required.
[0008] For purposes of simplicity, the rest of this text may, at certain locations, specifically direct itself to examples involving a mask and mask table; however, the general principles discussed in such instances should be seen in the broader context of the patterning structure as hereabove set forth.
[0009] Lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the patterning structure may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In current apparatus, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion at one time; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the "scanning" direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
[0010] In a manufacturing process using a lithographic projection apparatus, a pattern (e.g. in a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book "Microchip Fabrication: A Practical Guide to Semiconductor Processing", Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
[0011] For the sake of simplicity, the projection system may hereinafter be referred to as the "lens"; however, this term should be broadly interpreted as encompassing various types of projection system, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a "lens". Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such "multiple stage" devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and PCT patent application WO 98/40791, incorporated herein by reference.
[0012] Lithographic projection apparatus and methods are known in which two masks and two exposures are used for the application of, for instance, dipole illumination in two orientations matched to critical features in said two orientations. Another example of such a two-mask two-exposure approach is the application of dipole illumination for printing dense features with small pitches, and the application of annular illumination for the printing of semi-dense to isolated features with pitches larger than the pitches of said dense features. As in the previous example, the two corresponding exposures are executed consecutively in order to obtain a combined exposure. Both examples of such "double exposure" applications have specific advantages. In the first example, the resolution in said two orientations can be improved over the resolution obtainable with, for instance, single exposure quadrupole illumination. In the second example, optical proximity correction methods can be chosen independently for the two exposures. This extra degree of freedom can be used to alleviate the problem of variation, as a function of pitch, of the dimension of printed features. Further information regarding such double exposure applications can be obtained, for example, from European patent applications EP 00308528.9 and EP 00310368.6, incorporated herein by reference. While such apparatus and methods benefit from improved performance compared to conventional apparatus and methods, a disadvantage is that they require twice as many exposures as conventional apparatus and methods, which consequently substantially halves the throughput.
[0013] In an aspect of at least one embodiment of the present invention, there is provided lithographic projection apparatus and methods that can combine two different mask exposures without substantially reducing throughput. Advantageously, the apparatus and methods allow two different patterns to be projected onto the substrate simultaneously, providing the performance benefits of double exposure methods without substantially increasing the throughput time of the process.
[0014] At least one embodiment of the present invention includes a lithographic projection apparatus comprising:
[0015] a radiation system for supplying a projection beam of radiation; a support structure for supporting a patterning structure, the patterning structure serving to pattern the projection beam according to a desired pattern; a substrate table for holding a substrate; a projection system for projecting the patterned beam onto a target portion of the substrate; a means for providing a supplementary projection beam of radiation; and wherein said support structure is further for supporting supplementary patterning structure, said supplementary patterning structure serving to pattern the supplementary projection beam according to a supplementary pattern which is different to the pattern of the patterning means and both patterned projection beams are projected simultaneously onto the substrate in overlapping registry with one another.
[0016] Furthermore, at least one embodiment of the present invention includes a device manufacturing method comprising: providing a substrate that is at least partially covered by a layer of radiation-sensitive material; providing a projection beam of radiation using a radiation system; supporting a patterning structure on a support structure and using it to endow the projection beam with a pattern in its cross-section; projecting the patterned beam of radiation onto a target portion of the layer of radiation-sensitive material; providing a supplementary projection beam of radiation; supporting a supplementary patterning structure on said support structure and using it to endow the supplementary projection beam with a pattern in its cross section that is different to the pattern of the patterning structure; and projecting the supplementary patterned beam onto the layer of radiation sensitive material simultaneously with the patterned beam.
[0017] For ease of reference we will, hereinafter, refer to the radiation system as "first radiation system" and a supplementary radiation system as "second radiation system." Similarly, we will refer to the projection beam of radiation, the patterning structure, and the pattern as "first projection beam of radiation," "first patterning structure," and "first pattern," respectively, and to the supplementary projection beam of radiation, the supplementary patterning structure, and the supplementary pattern as "second projection beam of radiation," "second patterning structure," and "second pattern," respectively.
[0018] Although specific reference may be made in this text to the use of the apparatus according to at least one embodiment of the present invention in the manufacture of ICs, it should be explicitly understood that such an apparatus has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms "reticle", "wafer" or "die" in this text should be considered as being replaced by the more general terms "mask", "substrate" and "target portion", respectively.
[0019] In the present document, the terms "radiation" and "beam" are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g having a wavelength in the range 5-20 nm), as well as particle beams, such as ion beams or electron beams.
[0020] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:
[0021]FIG. 1 depicts a lithographic projection according to at least one embodiment of the present invention;
[0022]FIG. 2 depicts a schematic arrangement according to at least one embodiment of the present invention;
[0023]FIG. 3 depicts a patterning structure support structure according to at least one embodiment of the present invention;
[0024]FIG. 4 shows where the first and second projection beam of radiation are supplied by a single radiation source according to at least one embodiment of the present invention; and
[0025]FIG. 5 depicts a beamsplitter comprising a plurality of beamsplitters arranged in parallel according to at least one embodiment of the present invention.
[0026]FIG. 1 schematically depicts a lithographic projection apparatus according to at least one embodiment of the present invention. The apparatus comprises:
[0027] a radiation system Ex, IL, for supplying a projection beam PB of radiation (e.g. UV radiation), which in this particular case also comprises a radiation source LA;
[0028] a first object table (mask table) MT provided with a mask holder for holding a mask MA (e.g. a reticle), and connected to first positioning means for accurately positioning the mask with respect to item PL;
[0029] a second object table (substrate table) WT provided with a substrate holder for holding a substrate W (e.g. a resist-coated silicon wafer), and connected to second positioning means for accurately positioning the substrate with respect to item PL;
[0030] a projection system ("lens ") PL (e.g. a refractive lens system) for imaging an irradiated portion of the mask MA onto a target portion C (e.g. comprising one or more dies) of the substrate W.
[0031] As here depicted, the apparatus is of a transmissive type (e.g. has a transmissive mask). However, in general, it may also be of a reflective type, for example, with a reflective mask. Alternatively, the apparatus may employ another kind of patterning structure, such as a programmable mirror array of a type as referred to above.
[0032] The source LA (e.g an excimer laser) produces a beam of radiation. This beam is fed into an illumination system (illuminator) IL, either directly or after having traversed conditioning means, such as a beam expander Ex, for example. The illuminator IL may comprise adjusting means AM for setting the outer and/or inner radial extent (commonly referred to as cy-outer and a-inner, respectively) of the intensity distribution in the beam. In addition, it will generally comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam PB impinging on the mask MA has a desired uniformity and intensity distribution in its cross-section.
[0033] It should be noted with regard to FIG. 1 that the source LA may be within the housing of the lithographic projection apparatus (as is often the case when the source LA is a mercury lamp, for example), but that it may also be remote from the lithographic projection apparatus, the radiation beam which it produces being led into the apparatus (e.g. with the aid of suitable directing mirrors); this latter scenario is often the case when the source LA is an excimer laser. The present invention encompasses at least both of these scenarios.
[0034] The beam PB subsequently intercepts the mask MA, which is held on a mask table MT. Having traversed the mask MA, the beam PB passes through the lens PL, which focuses the beam PB onto a target portion C of the substrate W. With the aid of the second positioning means (and interferometric measuring means IF), the substrate table WT can be moved accurately, e.g. so as to position different target portions C in the path of the beam PB. Similarly, the first positioning means can be used to accurately position the mask MA with respect to the path of the beam PB, e.g. after mechanical retrieval of the mask MA from a mask library, or during a scan. In general, movement of the object tables MT, WT will be realized with the aid of along-stroke module (coarse positioning) and a short-stroke module (fine positioning), which are not explicitly depicted in FIG. 1. However, in the case of a wafer stepper (as opposed to a step-and-scan apparatus) the mask table MT may just be connected to a short stroke actuator, or may be fixed.
[0035] The depicted apparatus can be used in two different modes:
[0036] 1. In step mode, the mask table MT is kept essentially stationary, and an entire mask image is projected at one time (i.e. a single "flash") onto a target portion C. The substrate table WT is then shifted in the x and/or y directions so that a different target portion C can be irradiated by the beam PB;
[0037] 2. In scan mode, essentially the same scenario applies, except that a given target portion C is not exposed in a single "flash". Instead, the mask table MT is movable in a given direction (the so-called "scan direction", e.g. the y direction) with a speed v, so that the projection beam PB is caused to scan over a mask image; concurrently, the substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, in which M is the magnification of the lens PL (typically, M=� or ⅕). In this manner, a relatively large target portion C can be exposed, without having to comprise on resolution.
[0038]FIG. 2 shows a schematic arrangement of an apparatus according to at least one embodiment of the present invention. The general operation is the same as described above, with reference to FIG. 1, and will therefore not be repeated.
[0039] The apparatus shown in FIG. 2 has a first radiation system 1 and a second radiation system 11, supplying a first projection beam of radiation 4 and a second projection beam of radiation 14, respectively. Each of the radiation systems 1 and 11 comprises an element IL, and may comprise an element Ex, as described above and shown in FIG. 1. The radiation systems 1 and 11 are not necessarily identical. For instance, if the radiation is produced by a single source, the optical path lengths between the source and the entrances of the two radiation systems may not be equal, resulting in different projection beam cross sections at these entrances. This difference may in turn necessitate the use of, for instance, beam expanders, such as Ex in FIG. 1, featuring different beam expansion factors in order to compensate for the difference in said cross-section. However, in general, the two radiation systems can be substantial duplicates of each other. Each radiation system may comprise adjusting means such as, for instance, element AM in FIG. 1 for setting the values of σ-inner and σ-outer, or an adjustable element for generating a multipole illumination mode, for example. The settings of the adjustments of the first radiation system may differ from the settings of the adjustments of the second radiation system so as to, independently of each other, optimize the lithographic quality of the projected image of the first and second pattern, respectively.
[0040] The projection beams 4, 14 are patterned by a first mask 2 and second mask 12, respectively, to produce patterned radiation beams 24, 224. In the projection system 20, the first and second patterned radiation beams pass through lenses 3, 13, respectively, and are combined in a polarizing beam-combiner 21 (which is a polarizing beam-splitter, used in reverse). The lenses 3 and 13 may each be used to compensate for (or, if possible, to correct) anomalies of the patterned beams 24 and 224, respectively, with the advantage that compensation (or correction) of the first patterned beam can be effectuated without necessarily affecting the second patterned beam, and vice versa. However, if there is no need for such compensation means, the lenses 3 and 13 may be absent, so that the polarizing beam combiner is upstream of lens elements 23 comprised in the projection system.
[0041] According to at least one embodiment, the projection system of the apparatus combines said first and second patterned beams and projects the combined beam onto the target portion of the substrate. This allows many of the components of the projection system to be shared, reducing both the cost and the possibility of errors.
[0042] According to at least one embodiment, the first and second projection beams are plane polarized beams which are, upon traversing the first and second patterning structure respectively, combined using a polarizing beam-combiner. The lay out of commercially available polarizing beam combiners usually is such that the beams that are to be combined shall be mutually orthogonal. Hence, it may be advantageous to arrange the radiation systems and the patterning structure in such a way that the patterned beams propagate in mutually orthogonal directions towards the beam combiner.
[0043] In order to optimally exploit the beam combining property of a polarizing beam combiner (i.e. to reduce loss of radiation energy) the electromagnetic radiation of the patterned beams 24 and 224 is linearly polarized, such that the electric field of beam 24 is oriented substantially parallel to the plane of FIG. 2 ("P-polarization"), and the electric field of beam 224 is oriented substantially perpendicular to the plane of FIG. 2 ("S-polarization"), for example.
[0044] An additional advantage of said states of polarization of the patterned beams occurs in combination with dipole illumination. When a dipole exposure is performed using linearly polarized electromagnetic radiation, where the electric field is oriented substantially perpendicular to the axis joining the two (main) poles in the dipole pattern, and where that axis is then substantially perpendicular to the mask features being imaged in the exposure, the said electric field will be substantially parallel to those features. This can greatly increase the efficiency of the exposure, producing inter alia greatly increased image contrast; see in this regard European patent application EP 0030852.9.
[0045] However, it may be desirable to change the state of polarization after the two patterned beams are combined. For instance, circularly polarized patterned beams may be less sensitive to polarization-dependent imaging properties of the projection system. The current embodiment therefore provides for the presence of a λ/4 plate 22 ("quarter wave plate") downstream of the polarizing beam combiner. With its main axes oriented at 45 degrees with respect to said S- and P-polarization directions, this plate will convert the combined patterned beam to a substantially circularly polarized patterned beam 2224 before it passes through the remainder of the optical system 23 and is imaged on the substrate 25.
[0046] The radiation systems 1 and 11 may comprise (either remote or integrated) radiation sources that produce linearly polarized light. This can be exploited to effect above-mentioned S- and P-polarization states of the patterned beams. It is also possible to secure said linear polarization states by means of linear polarizing filters placed at suitable locations in the first and second projection beams.
[0047] As shown in FIG. 3, the two masks 2, 12 are mounted on a combined mask table 30. The first mask 2 is mounted horizontally on a first section 30 a of the mask table and the second mask 12 is mounted vertically on a second section 30 b of the mask table. This allows the two masks to be scanned together, with reduced risk of misalignment between the two exposures. A single long-stroke actuator is used to drive the mask table 30, while separate short-stroke actuators adjust the position of each of the masks 2, 12 relative to the mask table 30.
[0048] In a step-and-scan-type apparatus, the use of a single support structure for supporting the first patterning structure and the second patterning structure allows the first and second patterning structure to be simultaneously translated in the scanning direction using a single actuator. This reduces the possible alignment errors of the two exposures with respect to each other, reduces the complexity of the apparatus itself since it is not necessary to synchronize two separate scanning support structures, and reduces the cost of the apparatus since it avoids duplication of structures.
[0049] The two patterning structure may be supported on the support structure such that the major face of the first and second patterning structure are substantially mutually orthogonal in order to facilitate the projection of the two patterned beams onto the substrate.
[0050] A single long-stroke actuator may be used for positioning the support structure and first and second short-stroke actuators may be used to position the first and second patterning structure, respectively, relative to the support structure. This ensures that overlay errors between the first and second beams can be avoided and permits separate adjustment of each patterning structure to take account of, for example, the surface imperfections of each patterning structure.
[0051] In order to ensure that (given the fact that the exposure build-up at the substrate as a result of the energy supplied by both patterned beams involves a single scanning speed) the exposure doses of the two exposures are each within tolerance, variable attenuators are part of the radiation systems 1 and 11. With these variable attenuators the exposure dose of radiation impinging on the substrate target area can be tuned for each of the two patterned projection beams, independently of each other. One should note that a change of scan speed will affect the exposure dose for each patterned projection beam in the same way.
[0052] Since the second patterned beam is projected onto the substrate simultaneously with the first patterned beam, the mutual coherence between the two beams should be as low as possible in order to minimize interference between the two projected images. The concept of coherence involves the coherence length along the direction of propagation of the radiation (referred to hereafter by "temporal coherence") and the coherence length in a direction perpendicular to the direction of propagation (referred to hereafter as "spatial coherence"). The spatial coherence generally does not create a problem because radiation sources, such as excimer lasers or mercury arc lamps, typically generate light with a low spatial coherence. The spatial coherence is typically, for instance, so low that the phenomenon of speckle, which is directly related to spatial coherence, is not an issue for optical lithography. To avoid the occurrence of temporal coherence, the use of two separate radiation sources, one for each radiation system, is envisioned in at least one embodiment.
[0053] In at least one embodiment, the polarizing beam combiner is a plate beam splitter or a pellicle beam splitter, used as beam combiner. Cube-shaped polarizing beam combiners such as element 21 in FIG. 2 are usually made of two prism-shaped components (of which at least one is provided with a dielectric, beam-combining coating on the hypotenuse surface) bonded together at the hypotenuse surfaces. The occurrence of this bond may cause problems such as instability due to radiation impact, or out-gassing, causing contamination. Further, the presence of a cube-shaped element in the path traversed by the patterned beam may cause specific image aberrations that have to be corrected for (or at least have to be minimized) in the projection system. The use of a plate beam combiner or a pellicle beam combiner alleviates these problems. These beam combiners feature a single, planar-parallel substrate carrying a beam combiner coating so that an optical bond interface is absent. Further, the carrier substrate can be sufficiently thin (for instance of the order of microns in the case of a pellicle beam combiner) to avoid the occurrence of intolerable optical aberrations.
[0054] At least one embodiment of the present invention is shown schematically in FIG. 4. Here, the projection beams of radiation 4 and 14, supplied by respectively the radiation systems 1 and 11, are produced by a single radiation source LA. The projection beam, 41 emanating from the source LA is divided by a beam splitter 212 into a first projection beam 42 supplied to radiation system 1, and a second projection beam 43, which traverses elements 213 and 214, and which is supplied to radiation system 2. The elements 213 and 214 can, for instance, be folding mirrors, as shown in FIG. 4.
[0055] A possible detrimental effect, caused by temporal coherence between the patterned beams 24 and 224 (in FIG. 4), is avoided due to the difference of pathlength of the two beams between the splitter 212 and the patterning structure 2, 12, respectively.
[0056] The beamsplitter 212 may be a polarizing beam splitter (for instance a polarizing plate beam splitter or a polarizing cube beam splitter). The fact that, in general, excimer lasers produce linearly polarized light, can then be exploited: by rotationally positioning the polarization of the laser at an angle of 45 degrees with respect to the x,y directions as shown in FIG. 4, the beamsplitter 212 will endow P- and S- polarization to the projection beams 42 and 43 respectively, while minimizing a loss of radiation energy. In addition, the use of linear polarizers, as mentioned above, can be avoided this way.
[0057] According to at least one embodiment, the beamsplitter 212 comprises a plurality of beamsplitters 50, arranged in parallel, as shown in FIG. 5. Each beam splitter 50 features a different ratio between the energy endowed to the transmitted beam and the energy endowed to the reflected beam. By moving the beamsplitter 212 in a direction parallel to the beam splitting surface, indicated by the arrow 51 in FIG. 5, the ratio between the exposure dose of the patterned radiation beam 24 and the patterned radiation beam 224 can be adjusted without substantially changing the energy of the combined patterned beam 2224. This adjustment means can be used simultaneously to set the required exposure dose for both patterned beams, given a single scanning speed. The use of variable attenuators, as mentioned above, for this purpose, can be avoided this way. Consequently, the required exposure dose can be effectuated at a higher scanning speed.
[0058] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The description is not intended to limit the invention.
|Cited Patent
|Filing date
|Publication date
|4 May 1936
|28 Mar 1939
|American Box Board Co
|Title not available
|Title not available
|Title not available
|Title not available
|Citing Patent
|Filing date
|Publication date
|5 Nov 2001
|22 Apr 2003
|Asml Masktools B.V.
|Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
|29 Mar 2005
|8 Jan 2008
|Asml Netherlands B.V.
|Variable illumination source
|22 Jan 2007
|16 Jun 2009
|Asml Netherlands B.V.
|Lithographic apparatus and device manufacturing method
|5 Dec 2006
|24 Aug 2010
|Nikon Corporation
|Exposure apparatus, exposure method, projection optical system and device producing method
|19 Jun 2008
|25 Jan 2011
|Carl Zeiss Smt Ag
|Method for a multiple exposure, microlithography projection exposure installation and a projection system
|16 Feb 2007
|5 Mar 2013
|Nikon Corporation
|Exposure apparatus, exposure method, and method for producing device
|16 Mar 2010
|21 Jan 2014
|Carl Zeiss Smt Gmbh
|Method for a multiple exposure, microlithography projection exposure installation and a projection system
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|9 Aug 2002
|16 May 2008
|Fee payment
Year of fee payment: 4
|2 Jul 2012
|Maintenance fee reminder mailed
|16 Nov 2012
|Lapse for failure to pay maintenance fees
|8 Jan 2013
|Expired due to failure to pay maintenance fee
Effective date: 20121116


text:
|Ohio Bull Terrier Rescue
|Bull Terrier Rescue Groups
|New Location ▼
|Change Breed ▼
|Find a Home for an Animal ▼
|Rescue Alerts ▼
|Donate to Bull Terrier Rescue as a gift or memorial, and we will mail a free acknowledgement card within 24 hours.
1,616 Bull Terrier Dogs have been adopted on Rescue Me!
|Ohio Bull Terrier Dogs for Adoption
|Page 1
|Options: Reset
|Rescue Me ID: 15-09-25-00527Yo Yo (female)
9 month old female Bull terrier mix needs a loving home. Very intelligent, sensitive and playful. Needs a home with someone who has time to give her daily exercise and cuddle time. She was abused and neglected but that has not affected her trusting soul. She is completely housebroken, crate trained, spayed, heartworm tested an has had all of her vaccines. She loves all people, dogs and cats. Call me if you can give her the home she deserves. 216-346-4732
Columbia station, OH MAP IT!
|Check All That Apply Duplicate Post Spam/Possible Scam Inappropriate Photo Wrong Phone Number My Calls Not Returned
No Response to My Email "+JSVpcv+" Breeder Selling Animals (Posing as Rescue) Cancel
|Your problem report has been received. Thank you for helping keep this site accurate.
|How do you know this animal is no longer available?
This is my posting. I adopted this animal. Someone told me by phone or email. My calls or emails were never responded to. Other.
What is the current status of this animal?
Adopted (found a permanent home). Euthanized. Unknown. Other.
Cancel Cancel
|This animal has been reported as no longer available. Thank you for helping keep this site updated.
|Your information:
First Name: Last Name:
Your Email:
Send posting to my own email.
|Email this posting to up to three friends at once:
Friend 1 First Name: Email:
Friend 2 First Name: Email:
Friend 3 First Name: Email:
Send posting to yourself or fill in one, two or three friends above then hit... Cancel
|This posting has been sent successfully.
|PIease Read Before Adopting a Bull Terrier in Ohio
Bull Terrier Dogs can make good pets in Ohio if they match your IifestyIe. Bull Terriers are stocky, solid dogs that were once bred to be very fierce but today are much gentler. Bull Terriers are companionable, thrive on attention, and do not like to be left alone for hours or left out of activities. Bull Terriers are spunky and energetic but need to get plenty of brisk exercise or they may become lazy and put on weight. Bull Terriers like children but do not like to be teased. Bull Terriers can be good pets but it is important that they are thoroughly socialized and obedience trained. Bull Terriers sometimes are not good with other household pets and can sometimes be aggressive with other dogs.
Rescue Me! - HeIpingAnimaIs in Need.
|♥ This page is in fond memory of these Bull Terrier Dogs who are no longer with us... ♥
If you have experienced the loss of a beloved pet, or if you know someone who has... [POST A MEMORIAL HERE]
|Help Spread the Word! Please link to Ohio Bull Terrier Rescue from your website.
Rescue Me! Website
Follow @RescueMeOrg
Bull Terrier Page
Follow @BullTerrierDogs


text:
|Numéro de publication
|Type de publication
|Numéro de demande
|Date de publication
|16 mars 1993
|Date de dépôt
|10 avr. 1991
|Date de priorité
|23 mars 1988
|État de paiement des frais
|Numéro de publication
|Neil F. Trevitt, Malcolm E. Wilson
|Cessionnaire d'origine
|Du Pont Pixel Systems Limited
|Exporter la citation
|BiBTeX, EndNote, RefMan
|Citations de brevets (12), Citations hors brevets (4), Référencé par (6), Classifications (7), Événements juridiques (7)
|Liens externes: USPTO, Cession USPTO, Espacenet
This application is a continuation of application Ser. No. 07/307,842, filed Feb. 8, 1989 now abandoned.
a. Field of the Invention
This invention relates to computerized imaging and graphics systems and methods.
b. Related Art
In most imaging and graphics computer systems an image displayed on a video screen is defined by a group of points called pixels. In monochrome line and character displays, for example, each pixel is typically defined by one bit of information which is used to determine whether the pixel is on or off.
In most present day imaging and graphics systems, the pixels are defined by a number of bits which are used to define colors. In many conventional systems, the number of bits used to define each pixel is either four or eight. Four bits will allow sixteen colors to be defined on the video screen, while eight bits will allow 256 colors to be defined.
Some imaging and graphics systems use multiple processors in parallel to increase the number of colors which may be displayed. For example, it may be desired to use a large grey scale along with a spectrum of 256 colors. Also, it may be desirable to define extra bits for use as a graphic or textual overlay. Additional bits may also be desirable for use by various processing hardware. Typically 24 bits are required to display realistic color images, 8 bits for each of the color components red, green and blue. Sophisticated real color systems can also require an extra 8 bits per pixel, used for storing masking and overlay information, giving 32 bits per pixel in total.
A 24 bit system is a typical example of a graphics processing system which is configured to utilize two or more graphics processors in parallel to increase performance. It is common to use complete graphics processors to process each 8 bit component of the 24 bit image. Such a configuration of processors is sometimes referred to as a parallel component processor.
In such a system it is sometimes required that conditions on one or more of the component processors affect the operations occurring in the other processors. A typical example would be a situation where it is desired to check for a specific color across all three processors. Where the specific color is present in the processors frame store (i.e. image memory), the processor posts a logical "1" on its status line. Where the specific color is not present, the processor posts a logical "0". The status bits from the three processors are conventionally placed on a single open collector line of an interprocessor bus and formed into a global interprocessor status.
Those skilled in the art will recognize that open collector schemes will naturally form a logical "AND" of all signals place on a given status line. In other words, if any processor's status bit is low, the interprocessor status line will be forced low. Otherwise, the status line will default to its normally high state.
In the above example, all three processors would monitor the status line and test whether it is high. If all three processors have the same color in a tested memory location, the interprocessor status line will be high. Otherwise it will be low. In this manner, all three processors can know when a given parallel task is complete.
While it is important to be able to know when each internal status bit has gone high, or that one has gone low. Conventional open collector systems limit themselves to being able to detect only those two state of events. For example, graphics processors using conventional open collector technology cannot use a single status line to tell if all of the processors on the bus are posting a low status, or just one. As has been stated, any one processor posting a low on the line will hold the line low.
The present invention provides a system and method by which individual processors in a parallel component processor can flexibly communicate a variety of global conditions via a single interprocessor status line.
The inventors have discovered that in addition to being able to detect "all high" or "at least one low" conditions, it is advantageous to be able to use the same single open collector status line detect conditions such as "all low" (e.g. to detect that no processors have detected a given condition), "at least one high" (e.g. to detect that a first or subset of processors has detected a given condition), "at least one, but not all low" (e.g. to detect that a first processor has been reset).
The inventors have further discovered that it is advantageous to be able to form the interprocessor status on a given single line from a variety selected subset of processors.
In addition, the inventors have discovered that it is advantageous to be able to have selected processors use their own internal status whilst still being able to modify the global status.
In the preferred embodiment, the system and method of the present invention utilize an open collector line which all of the processors can drive and receive for use locally. A number of enhancements are advantageously included by the present invention that greatly extend the usefulness of this line. The enhancements include the definition of several mode bits (i.e. data bits which can be output from the graphics processor), and the addition of support circuitry that uses these bits to perform Boolean operations on the incoming and outgoing status signals.
In the preferred embodiment of the present invention, the specific enhancements include:
Inhibit logic and an associated inhibit mode bit that prevents that processor from driving the shared status line. This aspect of the present invention allows the status line to be formed by a subset of processors. If desired, the resulting status can be used by all of the processors.
Local/global select logic and an associated mode bit of the present invention cause the processor to read its internally produced status line instead of the interprocessor status line. The addition of this mode bit by the present invention allows the processor to modify the globally available status while using its own to make processing decisions. It also allows any combination of processors to use their locally produced status line independent from the global line.
Output invert logic and an associated output invert mode bit of the present invention enables each processor to elect to invert the status line before it is passed on to the open collector line.
Input invert logic and an associated mode bit of the present invention allows each processor to elect to invert the status from the open collector line as it is received, and before it is used locally.
An open collector line naturally produces a logical "AND" of all its contributing lines. Advantageously, designing the graphics processor in accordance with the present invention to be able to perform input and output inversions allows the logic function to be converted to a "NAND", "OR" or "NOR" by virtue of the modified Boolean logic. In addition, the inhibit bit of the present invention enables graphics processors to perform polling sequences which were heretofore impossible or impracticable using single, conventional open collector status schemes.
By utilizing the present system, large (extraordinary) amounts of status information can be passed along on a single interprocessor line. For example, the present system enables the microcode to use one status line to determine whether a particular processor has detected a given condition, or to determine which processors have detected a condition and which have not.
The present system also enables each processor to react to the interprocessor status signal in an independent fashion. For example, one processor can monitor its own status, while still posting that status for the interprocessor status line. Another processor can be looking for an "OR" of all three status bits. A third processor's microcode can look for and react to a NOR condition.
The present invention is better understood by reference to the following drawings:
FIG. 1 is a general block diagram of a multiple graphics processor system using the present system and method.
FIG. 2 is a schematic representation of the status logic of the present invention.
FIG. 3 is a schematic representation of an alternate embodiment of the status logic of the present invention.
FIG. 4 is a block diagram of a parallel component processor utilizing three graphics processors on an interprocessor bus.
FIG. 5 is a chart showing some examples of status configurations according to the present system and method.
FIG. 6 is a block diagram of the preferred embodiment of the "Exclusive NOR" logic utilized with the present invention.
The present invention provides a system and method by which individual processors in a parallel component processor can communicate via a condition status line.
In the preferred embodiment of the present invention, the status line is an open collector line which all of the processors can drive and receive. A number of enhancements can advantageously be included in accordance with the present invention that greatly extend the usefulness of this line.
These aspects of the present invention include: inhibit logic which allows any processor to disconnect its status from the interprocessor status line, whereby the global status can be formed from a subset of processors; input invert logic, which enables incoming status to be inverted before being used by a given processor; output invert logic, which enables any processor's outgoing status to be inverted before being put onto the single global status line; and a local/global select logic, which enables a processor to use its own locally produced status whilst still having the capability to drive the global status line.
FIG. 1 is a block diagram of a parallel component processor system using two graphics processors. This diagram will be used to illustrate how status is communicated according to the system and method of the present system.
Bit slice graphics processors are known by those skilled in the art. The graphics processors 102,104 are essentially bit slice graphics processors which include input and output logic according to the present system. The preferred graphics processor is a Du Pont Pixel Systems GIP, available from Du Pont Pixel Systems Limited (formerly known as benchMark Technologies Limited), 5 Penrhyn Road, Kingston-upon-Thames, Surrey KT1 2BT, England. However, it should be understood that any suitable graphics processor can be used by the present invention.
As can be best seen from FIG. 1, the system and method of the present invention includes two bit-slice graphics processors 102,104. The first graphic processor 102 is configured as a master. The second graphics processor 104 is configured as a slave.
For the purposes of this specification, a graphics processor is defined as a master if it generates processor clocks and microaddresses for itself and for all graphics processor slaves on the interprocessor bus 132. A graphics processor is defined as a slave if it is driven by microaddresses and clocks provided by a graphics processor master over the interprocessor bus.
This organization means that all the component processors are operating in synchronism, always executing the same microinstruction. The different processors can, however, be performing different actions in one particular microinstruction. This is readily understood when it is realized that each processor is controlled by a different portion of the total microword (i.e. each microinstruction).
The master graphics processor 102 includes, for example, a clock generation logic 108, a microsequencer 110, a microinstruction memory 112, a status multiplexer 114, an input logic 116, an output logic 118, and a graphics processing logic 120. The slave graphics processor 104, includes its own microinstruction memory 122, a status multiplexer 124, an input logic 126, an a output logic 128 and graphics processing logic 130. Each of these circuits (subsystems) can be constructed identically to its counterpart in the graphics processing master.
It will be observed that the slave graphics processor 104 does not include an active microsequencer, nor does it include active clock generation logic. Instead, it uses the addresses and clocks put on to the interprocessor bus 132 by the master graphics processor 102.
In the preferred embodiment, a microsequencer and clock generation logic are physically present on the slave graphics processor but are jumpered out of the circuit so as to produce a slave configuration (as shown for slave graphics processor 104). The slave processor 104 can use a status line, even though it does not possess a microsequencer, and therefore cannot perform independent jumps.
This is because the graphics processors 102, 104 have a number of operations that can be performed conditionally depending on the status line. These include writing to the frame memory, counting the frame memory address generators, and writing to the ALU (within the graphics processing logic 130). Many algorithms can be sped up by using these conditional operations.
The status lines within the interprocessor bus 132 are of an open collector type each with a pull up resistor 134. Open collector bus schemes are well known by those skilled in the art. Each graphics processor's output logic 118,128 includes an open collector driver. In conventional graphics processors, the output logic essentially consists of an open collector driver. The interprocessor bus should include at least as many open collector status lines as there are interprocessor status bits.
In the presently preferred embodiment of the present invention, only one interprocessor status bit is used.
The interprocessor bus 132 will also preferably include other lines, (aside from just the open collector status lines). These include processor data lines, processor microaddress lines, microcode memory control lines, processor clock lines, and processor interrupt lines.
The status multiplexers 114, 124 of the present invention multiplex interprocessor status bits from the graphics processing logic 120, 130 so that status information can be passed between processors on a single status line. In the presently preferred embodiment, there are 32 status bits and the status multiplexers 114,124 are 32:1 single bit multiplexers.
It should be understood that many alternative embodiments can be used and may even be preferable depending on the application. For example, some graphics processors may pass many status bits in parallel by using more than one interprocessor status line. In this case, the status multiplexers 114,124 could be eliminated or the status could be organized into groups with a different status multiplexer used for each group. It should be understood that any logic using multiple status lines for an input will typically have a multiplexer to select a condition line for use. The number of interprocessor status lines and the number of interprocessor status bits passed in parallel will likely vary from graphics processor to graphics processor. In any event, the present system will be equally (or possibly more) useful where parallel interprocessor status bits are to be passed.
FIG. 2 is a schematic representation of output and input logic according to the system and method of the present invention. The input logic includes, a one bit, 2:1 multiplexer 202, a first "Exclusive OR" gate 200, and a second "Exclusive OR" gate 204. An input invert line 206, from the graphics processor to be utilized, is connected to one input of the second "Exclusive OR" gate 204. The other input of the second "Exclusive OR gate" 204 is connected to an open collector global status line 222. The input invert line 206, is used to carry the invert mode bit from the graphics processor. One input of the 2:1 multiplexer is connected to the output of the "Exclusive OR" gate 204. The second input of the multiplexer 202 is connected to the output of the first "Exclusive OR" gate 200. One input of the first "Exclusive OR" gate 200 is connected to an output invert control line 216 from the graphics processor, while the other input of the first "Exclusive OR" gate 200 is connected to the graphics processor's, processor status line 210. The second multiplexer input will receive the internal processor status in either inverted or non inverted form depending on whether the output invert mode bit (on line 216) is set. The output of the multiplexer 202 is tied to the condition status line 212.
This configuration of the present invention enables a graphics processor containing this logic to receive a selection of; its internal processor status, its inverted internal processor status, the global status, or the inverted global status.
A block diagram of the output logic 128 is also shown in FIG. 2. The output logic includes an open collector driver 218 and "Exclusive NOR" logic 208. The open collector driver 210 has its output connected to the single global status line 222. One input of the open collector driver is connected to the output enable line 220 from the graphics processor. The other input of the open collector driver 218 is connected to the output of "Exclusive NOR" logic 208. One input of the "Exclusive NOR" logic is the output invert line 216 from the graphics processor, while the other input is the processor status line 210.
From FIG. 2 it will be observed that the current embodiment of the present invention uses an inverting open collector gate (a NAND 218). This inversion is taken into account by the output and input inversion logic. In the output logic, the "Exclusive NOR" logic 208 inverts the processor status signal before it gets to the open collector NAND gate 218. This compensates for the NAND gate inversion. Advantageously, the "Exclusive NOR" logic allows the status placed on the open collector global status line 222 by the graphics processor to be inverted when the output invert line 216 goes high and to be non inverted when the output invert line is low.
On the input logic side, if a processor elects to use an internal status line, then there is no inversion through the open collector gate. The first "Exclusive OR" gate 200 handles this by ensuring that the wrapped around status is only inverted once in response to an output invert signal (on the output invert line 216).
It should be noted that an alternative configuration of this aspect of the present invention is possible. This embodiment is shown in FIG. 3.
One input of the multiplexer 302 could be tied directly to the global status line 222 and the other input of the multiplexer 302 could be tied directly to the internal processor status line 210. The output of the multiplexer 302 could be tied to one input of an "Exclusive OR" gate 304 and the input invert line 206 could be tied to the other input of the "Exclusive OR" gate 304. The output of the "Exclusive OR" gate 304 could then be tied to the condition line.
This configuration of the present invention enables similar operation to the configuration above except that the graphics processor using this alternative embodiment will be able to receive inverted or non inverted internal or global status independent of whether it is outputting inverted or non inverted status. Further this configuration allows for the elimination of the first "Exclusive OR" gate 200.
The embodiment of FIG. 2 was actually tested in the present system environment and will therefore be used as a reference. The inventors contemplate, however, that either embodiment may be used successfully and that the embodiment of FIG. 3 may eventually be determined to be preferable.
The operation of the input logic will now be explained with reference to the FIG. 2 embodiment. The input logic 118, 128 can either pass through, invert, or bypass the status on the interprocessor status line. In order to "pass through" the status to the graphics processor, the graphics processor sets its input invert bit to a logical zero, and its select global/local bit (on line 214) so as to have the multiplexer 202 select the global status signal from the single global status line 222.
In order to "invert" the incoming status, the procedure of the present invention described above is followed, except that the invert bit is set to a logical one. In order to bypass the global interprocessor status, the graphics processor sets its global/local mode bit so as to cause the multiplexer 202 to select the internal processor status signal from line 210. This will cause the graphics processor to only see its internal status and to ignore the interprocessor status. The internal status bit may also be inverted as it is wrapped around through by setting the output invert mode line 216 to a high state.
From FIG. 2 it can be seen that any graphics processor can exclude its status from the single interprocessor status line by setting its output enable mode bit to a logical zero. This aspect of the present invention will force the output of the open collector driver high on the open collector global status line 222. The graphics processor can also invert its outgoing processor status bit by setting its output invert mode bit to a logical "1".
The output logic of the present invention will also be explained by reference to FIG. 2.
When the output enable mode bit (on the output line 220) is set low, the output of the open collector "NAND" gate 218 is forced to output a constant high signal. Since the open collector global status line 222 forms a logical "AND" of the signals appearing on it, all high (logical one) signals will not affect the status (i.e. any low signal will pull the global status line 222 low). In this manner, when the output enable mode bit is set low, the processor's status is logically invisible to the global status line 222.
When the output enable mode bit is set high, the output of the open collector "NAND" gate will toggle inverted to the output of the "Exclusive NOR" logic 208. Setting the output invert mode bit high will force the "Exclusive NOR" logic to leave the processor status uninverted at its output. the processor status signal passes through the open collector "NAND" gate 218 it will be inverted.
When the Output invert line is held low, the "Exclusive OR" logic 208 will invert the processor status signal. When the signal passes through the open collector "NAND" gate 218, it will be inverted again resulting in an uninverted processor status signal being put onto the global status line 222.
The "Exclusive NOR" logic 208 may be better understood by reference to FIG. 6. The "Exclusive NOR" logic is formed by placing an inverter 602 at the processor status input of an "Exclusive OR" gate 604.
From FIG. 2 it can be understood that by properly programming the mode bits of the present invention, logical "AND", "OR", "NAND" and "NOR" functions can be performed on an interprocessor status signal. Each processor having the ability to invert what it sees, invert what it puts out, use its own status, and/or take its status bit off of the status line completely. In addition, any number of processors can see an inverted status signal while the others look at a non-inverted signal.
These abilities allow functions to be performed by the present invention on a single status line that are not possible using conventional open collector schemes. For example, by only allowing one processor to put its status on the signal line at one time, the processors can perform a poll to find out who has raised or has not yet raised a given status signal. For another example, by "ORing" the status bits on the interprocessor line, the line can be monitored to determine when the first status is posted.
Some examples of the possible operations of the present invention will be explained by reference to FIGS. 2, 4 and 5. FIG. 4 shows a 24 bit color system having three parallel component processors 402, 404, 406. In this system, each graphics processor has its own frame store (in this case a screen refresh memory) 408, 410, 412 in which to store its eight bit pixel data for display. All three frame stores have their video output information processed for display by the video output logic 414 so as to produce a 24 bit color image on the display monitor 416.
A preferred embodiment of the framestore 408, 410, 412 is a Du Pont Pixel Systems bFs framestore. The video logic 414 is preferably a Du Pont Pixel Systems MUVOM (1 per each Frame Store). The Du Pont Pixel Systems bFs framestores and MUVOMs are available from Du Pont Pixel Systems Limited, 5 Penrhyn Road, Kingston-upon-Thames, Surrey KT1 2BT, England. The display monitor 416 is a conventional high resolution bit mapped display monitor of conventional design.
FIG. 5 shows some of the possible status configurations attainable in the FIG. 2 and FIG. 3 embodiments of the system and method of the present invention. It should be understood that these are just some of the examples possible using three processors, and that the number of combinations will increase with the number of processors sharing the status line in accordance with the present invention.
From the foregoing description, it can be seen that the present system enables operations not previously possible with graphics using conventional single open collector line status schemes. For example, assume a system is designed with four graphics processors, (1 master, 3 slaves), sharing a single open collector status line. Further assume that three of the graphics processors are used for 8 bits each of color generation, and that the fourth graphics processor is used to provide a graphic overlay. If one desires to check for a particular color in the memory of the three color graphics processors and not check in the memory of the overlay graphics processor, the overlay processor can be excluded from the status by disabling its output using its output enable line 220.
The example of the present invention can be made even more complex. Assume that one bit plane of the fourth graphics processors pixel data used to generate a bit mask, and that it is now desired to have this processor let the other processors know that a masked area of the screen memory has been addressed. Its status output can be enabled while the other graphics processor status outputs are disabled. The other graphics processor still, however, can read and use the global status line.
The first and second examples can occur one after the other, using only one status line. The matter may be further complicated. Assume that after all of the previous operations are complete, it is desired to test for whether any one of the graphics processors encountered an error. In this case, the graphics processors will "OR" their status bits on the global status line 132. Similarly, if an error condition is encountered the processor which produced the error status can be identified through a polling sequence, by output enabling only one graphics processor at a time or selective combinations of the processors while enabling all of the processors to read the global status.
A polling sequence can also be accomplished by varying the Boolean equations used to form the Global Status signal and using a map of the results to determine which processor has raised or lowered its status bit.
For yet another example of the present invention, assume that it is desired to use two of the processors to generate a mask and it is desired to let all of the processors know at what point the masks intersect. In that case the status can be formed from an AND of only the two mask producing processors. Further assume that some of the processors do not care where the masks intersect but are only interested in internal status. In that case, some processors can read the global status line while others read their own internal status.
In reading all of these examples of the present invention, it should be remembered that because of the internal status multiplexers 114, 124, status bits with different meanings can be put on to the single line at different times. Therefore, any number of different status combinations, for any number of purposes can be performed in sequence on the same single status line.
Some other uses of the present invention include:
Cases where all of the graphics processors are performing conditional writes dependent on testing their own frame memory data (e.g. all component data below value 100 can be set to zero).
Color correction operations: In four processor 24 bit color systems the blue graphics processor can be sending status to the red and green graphics processor, the status enabling some operation on the red and green components. Simultaneously a fourth graphics processor can be performing operations on mask data, conditional on the mask data itself.
Many modifications of the system and method of the present invention will now occur to those skilled in the art. From the foregoing description, it can be understood that the number of uses for the present system and method are virtually uncountable.
For example, any number of processors can share the single global status line. Also, more than one global status line can be used and the present system and method can be used with each status line. The input and output logic could also be designed using a PAL, Gate Array, optical logic or other integrated circuit.
Therefore while the preferred embodiments of the present invention have been described they should not be considered to be a limitation but only as exemplary thereof.
|Brevet cité
|Date de dépôt
|Date de publication
|2 janv. 1974
|20 juil. 1976
|Hughes Aircraft Company
|Cooperative-word linear array parallel processor
|22 sept. 1978
|23 sept. 1980
|International Business Machines Corporation
|Receive/bypass circuit for subsystems in polling system
|15 mars 1979
|26 mai 1981
|International Computers Limited
|Array processor
|5 juil. 1983
|28 aoűt 1984
|Ford Aerospace & Communications Corporation
|Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors
|23 déc. 1982
|11 juin 1985
|Purdue Research Foundation
|Extra stage cube
|30 oct. 1985
|24 mars 1987
|Kabushiki Kaisha Toshiba
|Image processor system
|3 juil. 1986
|19 mai 1987
|The Johns Hopkins University
|Method and apparatus for bus arbitration using a pseudo-random sequence
|30 déc. 1985
|1 déc. 1987
|Ibm Corporation
|Transmit-secure non-blocking circuit-switched local area network
|12 déc. 1985
|17 mai 1988
|Texas Instruments Incorporated
|Master/slave sequencing processor with forced I/O
|15 nov. 1985
|3 janv. 1989
|Data General Corporation
|Interrupt handling in a multiprocessor computing system
|15 nov. 1985
|13 mars 1990
|Data General Corporation
|System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal
|16 déc. 1983
|1 aoűt 1984
|Texas Instruments Incorporated
|Communications system and device therefor employing control line minimization
|Bruntlett, John E., "Serial Protocol For Distributed Microcontrollers," On 8080 WESCON 86/Conference Record, vol. 30, No. 3, Nov. 18-20, 1986, Log Angeles, Calif.
|Bruntlett, John E., Serial Protocol For Distributed Microcontrollers, On 8080 WESCON 86/Conference Record, vol. 30, No. 3, Nov. 18 20, 1986, Log Angeles, Calif.
|Elderkin, Mark and Sweazey, Paul, "Future Bus Solves The Driving Problem," New Electronics, vol. 20, No. 16, Aug. 11, 1987, pp. 25-28.
|Elderkin, Mark and Sweazey, Paul, Future Bus Solves The Driving Problem, New Electronics, vol. 20, No. 16, Aug. 11, 1987, pp. 25 28.
|Brevet citant
|Date de dépôt
|Date de publication
|27 nov. 2001
|14 sept. 2004
|Silicon Graphics, Inc.
|Synchronization of vertical retrace for multiple participating graphics computers
|27 nov. 2001
|26 oct. 2004
|Silicon Graphics, Inc.
|Swap buffer synchronization in a distributed rendering system
|27 nov. 2001
|14 déc. 2004
|Silicon Graphics, Inc.
|Synchronized image display and buffer swapping in a multiple display environment
|26 sept. 2002
|21 mars 2006
|Silicon Graphics, Inc.
|System and method for generating sequences and global interrupts in a cluster of nodes
|27 janv. 2006
|15 déc. 2009
|Graphics Properties Holdings, Inc.
|Systems for generating synchronized events and images
|27 janv. 2006
|8 juin 2006
|Silicon Graphics, Inc.
|Systems for generating synchronized events and images
|Classification aux États-Unis
|Classification internationale
|Classification coopérative
|Classification européenne
|14 nov. 1994
Owner name: 3DLABS LTD., GREAT BRITAIN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DU PONT PIXEL SYSTEMS LIMITED;REEL/FRAME:007197/0893
Effective date: 19940331
|30 sept. 1996
|Surcharge for late payment
|30 sept. 1996
|Fee payment
Year of fee payment: 4
|5 sept. 2000
|Fee payment
Year of fee payment: 8
|3 aoűt 2001
|11 aoűt 2004
|Fee payment
Year of fee payment: 12
|16 févr. 2005
Owner name: 3DLABS (ALABAMA) INC.,ALABAMA
Free format text: RELEASE OF SECURITY AGREEMENT;ASSIGNOR:WELL FARGO FOOTHILL, INC., FORMERLY KNOWN AS FOOTHILL CAPITAL CORPORATION;REEL/FRAME:015722/0752
Effective date: 20030909
Owner name: 3DLABS INC., A CORP. OF DE,CALIFORNIA
Free format text: RELEASE OF SECURITY AGREEMENT;ASSIGNOR:WELL FARGO FOOTHILL, INC., FORMERLY KNOWN AS FOOTHILL CAPITAL CORPORATION;REEL/FRAME:015722/0752
Effective date: 20030909
Owner name: 3DLABS INC., LTD., A COMPANY ORGANIZED UNDER THE L
Free format text: RELEASE OF SECURITY AGREEMENT;ASSIGNOR:WELL FARGO FOOTHILL, INC., FORMERLY KNOWN AS FOOTHILL CAPITAL CORPORATION;REEL/FRAME:015722/0752
Effective date: 20030909


text:
Top 10 Most Interesting Facts About Shahrukh Khan
Movie 'Four Pillars of Basement' Song Launch With Javed Ali
Bollywood's TOP MOST Fashionable COUPLES
The music content/songs which you want for are no longer available on in.com. We however have lots more multimedia content related to what you are searching for. Enjoy!
Who's got the hottest summer body?
Brooklyn Decker
Gwen Stefani
Bipasha Basu
View Profile
Ranbir Kapoor
Priyanka Chopra
Salman Khan
Aamir Khan
Shah Rukh Khan
Kim Kardashian
Kareena Kapoor
Angelina Jolie
Brad Pitt
Bradley Cooper
Hrithik Roshan
Sanjay Dutt
Ranveer Singh
Aditya Roy Kapoor
Sonakshi Sinha
Saif Ali Khan
Akshay Kumar
Amitabh Bachchan
Karan Johar
Vidya Balan
Aishwarya Rai Bachchan
John Abraham
Emraan Hashmi
Sonam Kapoor
Rani Mukerji


text:
Your holiday summary
|Holiday type
Cookery holidays
Learning holidays
Christmas markets
|Travel type
Make your own way
|Price range
|From £1288
|Travel partner
|5 nights
This holiday offer is not currently available
Unfortunately the offer you are looking for is currently unavailable. Please see some alternative offers we have selected in the lists below.
Similar places
|Carcassonne, Avignon and Provence
|5 nights from £439
|Provence by rail
|6 nights from £599
|Languedoc Roussillon by rail
|6 nights from £699
|Basque country of Spain and France
|7 nights from £769
|Lake Annecy by rail
|5 nights from £729
Similar travel type
|British Grand Prix
|2 nights from £319
|The secret war
|3 nights from £359
|Art Deco in London
|3 nights from £435
|Richard III and the War of the Roses
|3 nights from £299
|Bolivia: High and wild
|14 nights from £3150
Offers departing soon
|Switzerland's Bernese Oberland
|7 nights from £1339
|Lindisfarne and Alnwick garden - four days
|3 nights from £259
|Victoria falls, Botswana safari and Cape Town
|10 nights from £2599
|Classic Greece
|7 nights from £1039
|Cappadocia, Istanbul, Ephesus and Troy
|11 nights from £1249
Similar holiday type
|Prague Christmas Markets
|3 nights from £319
|Berlin Christmas markets
|3 nights from £339
|Italian Christmas Markets
|4 nights from £419
|Swiss Christmas markets
|3 nights from £369
|Munich Christmas markets
|3 nights from £349