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Jan. 1, 2013 12:00 am - Dec. 31, 2015 11:30 pm
Description :This seven-session class includes a state-of-the-art curriculum with training provided by an experienced, certified Parent to Parent teacher. Each of the two-hour sessions covers an area of information absolutely essential to the successful management of ADHD. And best of all, the training is from a parent's perspective, brought to you by experts who have faced the same struggles, questions, and challenges you face.
Nov. 15, 2015 8:00 am - Nov. 15, 2015 5:00 pm
Description :November 15, 2015
8:00 am-5:00 pm
Hyatt Regency New Orleans
601 Loyola Avenue
New Orleans, LA 70113
Imperial 5 A&B
This day-long workshop for mainstream classroom teachers identifies common ADHD-related learning and behavioral problems, the latest research about ADHD and executive function deficits, plus practical classroom techniques, helpful educational technology and academic and behavioral interventions to increase school success for students with ADHD.
The Training Will Provide:
• Information about the basic symptoms of ADHD.
• Classroom interventions that will help increase the academic success of students with ADHD.
• Organizational strategies to address typical behavioral problems
• Ways to change your classroom environment to be more supportive for students with ADHD.
• Each attendee will also receive the CHADD Educator's Manual on ADHD: An In-Depth Look from an Educational Perspective.
Seating is limited to the first 80 registrants. Register by September 21 to secure your spot!
Speakers:Chris A. Zeigler Dendy, a popular author, former educator, school psychologist, children's mental health professional with 45+ years' experience, is the mother of three grown children and five grandchildren with ADHD. She and her late husband have provided training nationally and internationally. She has authored four popular books and two DVDs on ADHD. Her first book, Teenagers with ADD & ADHD has sold over 100,000 copies. Her latest book, Teaching Teens with ADD, ADHD, & Executive Function Deficits, 2nd ed, was released in 2011. In November of 2014, she received CHADD's Lifetime Achievement Award; this is only the second time the award has been given. In 2006 she was inducted into CHADD's Hall of Fame. As a volunteer, she was the lead author for the CHADD Educator's Manual and is a co-founder of CHADD's Teacher-to-Teacher program.
Anne Ellison is a past-president of the Board of Directors of CHADD, and former Chair of the Professional Advisory Board. She has authored and presented hundreds of papers, articles and books, including Interventions for ADHD: Treatment in developmental context (Guilford Press), and Clinical neuropsychological assessment and interventions for children (2nd edition) (Springer Science) with Margaret Semrud-Clikeman. In addition, Dr. Ellison was a co-editor of the CHADD Educator's Manual on Attention Deficit/Hyperactivity Disorder: An in-depth look from an educational perspective with Chris Dendy and Mary Durheim; and, a co-author of Teacher to Teacher (T2T): ADHD Goes to School with Chris Dendy and Joan Helbing. Dr. Ellison is a Professor Emerita at the University of Wisconsin-Milwaukee, and is currently teaching at the University of South Carolina, Aiken. She was inducted into CHADD's Hall of Fame in 2010.
Registration Cancellation by Participant
The deadline to receive a refund for your registration is 30 days before the event (10/15.) Registration cancellations received prior to the deadline may be eligible to receive a refund less a $25 service fee. Cancellations received after the stated deadline will not be eligible for a refund. Refunds will not be available for registrants who choose not to attend an event. Cancellations will be accepted in writing only and must be received by the stated cancellation deadline. All refund requests must be made by the attendee or credit card holder.Refund requests must include the name of the attendee and/or transaction number. Refunds will be credited back to the original credit card.
Questions or to register by phone:
(240) 487-2321


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News Archive
A level results 2015 - 13th August 2015
of Heysham High School students returned a pass rate at A level this summer
with 97% gaining at least two A levels and once again almost half of its
students gaining at least one A*-B grade ...
Read more »
New building work - 12th August 2015
The new atrium being built between the English and Computing classrooms is under construction and on track for September. It will create a light, modern, contemporary space which we will be able...
Read more »
Charity hair cut - 11th May 2015
Well done to Zoe Miller in year 8, who raised over £700 for cancer charities by donating her hair to be made into a wig to help children suffering from cancer. Her new, short haircut...
Read more »
Carnival 2015 - 11th May 2015
Our "Alice in Wonderland" float in this year's carnival looked bright and colourful, even if the sun didn't shine. Well done everyone for flying the Heysham High flag. ...
Read more »
British Champions - 30th April 2015
Huge congratulations to Georgia and Shea Hannam, who continued their quest for excellence last weekend at the British Triathlon Championships for modern pentathlon.
Saturday was the pellet ...
Read more »
Pride Award winners - 27th March 2015
Congratulations to all our Heysham Pride Award winners for 2015 - you are remarkable people and we are indeed very proud of you!...
Read more »
French trip, 2015 - 27th March 2015
A good time was certainly had by all on the French trip last week. The students were a credit to themselves and the school and gained valuable experience of the language and culture of France, a...
Read more »
Engineering workshop - 25th March 2015
Our budding engineers reaped the benefits yesterday of a workshop by GEN2 apprentices, showcasing their latest projects....
Read more »
Young Achiever of the Year - 3rd February 2015
Congratulations to Georgia Hannam, who has won the Lancashire Sports Awards Young Achiever of the Year 2014. This award is for some of the most talented performers across the County, who show ...
Read more »
Rock show's "Royal" boost - 14th December 2014
The cast, musicians and crew of Heysham High's brilliant performance of
"We Will Rock You", the story of legendary rock stars, Queen, received a huge
boost before their performance last week, in t...
Read more »
Year 13 Achievers Awards - 1st December 2014
Congratulations to all our award winners whose academic achievements were celebrated at the "Achievers Awards" evening on Thursday 27th November. It was an excellent, uplifting evening and a ple...
Read more »
Cabin Crew - doors to manual - 19th November 2014
Thanks go to Tom from Thomas Cook travel agents who came into school yesterday to talk to our Cabin Crew students about working in the travel industry and his role as a travel agent. The student...
Read more »
Scholars Awards - 3rd November 2014
We celebrated the academic achievements of our KS3 and KS4 students in October, with two brilliant Scholars Awards evenings. Winners received beautiful glass trophies and the efforts of all the nomine...
Read more »
Reception launched! - 17th October 2014
The eagerly awaited new reception and community facilities building at
Heysham High is now officially open to the public. Regular visitors to the school's website have
been watching the buil...
Read more »
Primary STEM activities - 16th October 2014
Our primary school STEM (Science, Technology, Engineering and Mathematics) days are proving very popular with our local primary pupils. Activities have included CSI investigations, making r...
Read more »
Copyright Heysham High School © 2015. All rights reserved. Outlook
Website Design and CMS by Fat Media

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Manufacturer's Description
Quick is its middle namePicking up and going has never been easier available now in 5 different colors.Even though other laptop stands are designed to support mobile products they are generally not designed to travel. The AViiQ Portable Quick Stand folds flat to fit easily into a laptop bag and is less than 1/4 thick. Unlike other laptop stands which are big bulky and stationary the AViiQ portable quick stand is design to fit the mobile lifestyle. Take it on the go and enjoy the benefits of a laptop stand anywhere. Our unique patented folding design allows you to quickly fold and unfold the laptop stand in seconds not minutes.Technical Specs:Size & Weight. Folded Height: 10.98 inches (279 mm) . Folded Width: 3.22 inches (81.75 mm) . Folded Depth: 0.35 inches (8.77 mm) . Unfolded Height: 2.29 inches (58.11 mm) . Unfolded Width: 10.98 inches (279 mm) . Unfolded Depth: 2.06 inches (52.22 mm). Weight: 3.4 oz (96.4 g)Includes:. 1 AViiQ Portable Quick Stand. 1 Instruction Guide. Format: COMPUTER ACCESSORIES. Genre: STANDS. Age: 778656054288. UPC: 778656054288. Manufacturer No: AVQS12MSGR
The Specs
|Additional Specifications
|Parent Retsku
|Quick Glance
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A table was set with four place-settings representing the four branches of the military to honor those no longer with us, as part of the V.F.W. Ladies' Auxiliary POW/MIA ceremony. Many local veterans also attended an assembly at Barone Middle School after lunch.
In honor of our veterans
Letter to the Editor: Thank you for hosting ceremony
Dear Editor: The Meeker VFW Post 5843 and the Meeker Ladies' Auxiliary 5843 would like to thank the Meeker Chamber of Commerce for hosting the Veterans Day luncheon at Mountain Valley Bank immediately following the Veterans Day ceremonies on the courthouse lawn.
BMS hosts Veterans Day Assembly
MEEKER | Barone Middle is hosting the annual Veterans Day Assembly on Friday, Nov. 11, at 2:30 p.m., in the gym.


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Celebrating the announcement of the wedding of Prince William to Kate Middleton, this lavishly illustrated book tells the story of a modern royal romance. Beginning with their childhoods and showing how the two were brought up in two vastly different backgrounds, the book moves forward to explain how the young couple met at university and began a romance that William, aware of all the interest surrounding his mother's entry to the royal family, was determined to keep away from the glare of publicity. Filled with anecdotes of the couple's life together, Invitation to a Royal Wedding follows their courtship up to the day of the engagement and looks at all the plans for this long-awaited royal wedding. Written by Ian Lloyd,the book enables readers to find out everything regarding how the wedding will be conducted, the venue of Westminster Abbey and what can be expected on the great day itself. Invitation to a Royal Wedding is the ultimate souvenir of the wedding of the century.
Ian Lloyd is a freelance writer and photographer. He is the author of Crown Jewel: A Year in the Life of the Queen Mother and William - The People's Prince. He lives in Oxford.
More books by Ian Lloyd
Delivery Options
All delivery times quoted are the average, and cannot be guaranteed. These should be added to the availability message time, to determine when the goods will arrive. During checkout we will give you a cumulative estimated date for delivery.
* Available free for orders over £10
** Includes Austria, Belgium, Denmark, France, Germany, Greece, Iceland, Irish Republic, Italy, Luxembourg, Netherlands, Portugal, Spain, Sweden and Switzerland.
Delivery Help & FAQs
Returns Information
If you are not completely satisfied with your purchase*, you may return it to us in its original condition with in 30 days of receiving your delivery or collection notification email for a refund. Except for damaged items or delivery issues the cost of return postage is borne by the buyer. Your statutory rights are not affected.
* For Exclusions and terms on damaged or delivery issues see Returns Help & FAQs
The Emergency Poet, Deborah Alma, explains how poetry, with its millennia of history, has long been recognised as the perfect way to soothe trouble minds.
Novelist Jo Bloom interviews Monty Goldman the Jewish East End anti-fascist campaigner who inspired her new novel, Ridley Road.
The author of The Breast Cancer Awareness Cookbook explains why diet and lifestyle are suich important factors in prevention and cure and presents one of the recipes from the book.


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|List your club - Login
We are very pleased to invite you to be a part of a Herbalife Nutrition Club near you and find out the benefits that Herbalife Nutrition Clubs offer:
Herbalife Nutrition Clubs | Privacy Policy | Terms of Use | Contact Us
Copyright 2008-
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Impact of Transplanted hESC-derived Cardiomyocytes on Cardiac Structure and Function
To assess the impact of injected cells on cardiac structure and function, all animals received echocardiography at baseline (two days after infarction but two days prior to cell injection) and at four weeks post cardiomyocyte implantation. All animals exhibited significant cardiac dysfunction two days post infarct. On average, left-ventricular end diastolic and systolic diameters increased by 10% and 42%, respectively, and fractional shortening decreased by 40% compared to uninfarcted controls.
Four days after infarction, animals were injected with 10 million hESC-derived cardiomyocytes suspended in the survival cocktail. Animals injected with either the survival cocktail alone, serum-free media without cells, or equivalent numbers of non-cardiac hESC-derived cells suspended in the survival cocktail served as control groups.
Echocardiography performed four weeks after cell implantation showed attenuation of left-ventricular end-diastolic and end-systolic diameters in animals receiving cardiomyocytes versus all three control groups. In addition, fractional shortening was significantly improved (0.01) in animals that received cardiomyocytes compared to all three control groups. MRI analysis showed improved left-ventricular ejection fraction (p=0.05) in the cardiomyocyte-treated rats compared to controls, as well as a 2.5-fold increase in systolic wall thickening in the infarct zone relative to controls (0.01).
This study is the first to document the potential clinical utility of regenerating damaged heart muscle by injecting hESC-derived cardiomyocytes directly into the infarct zone of the heart. The survival cocktail administered with the cells enables their long-term surviva
|Contact: Sion Rogers
Russo Partners, LLC


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Partner Program
For nearly 20 years, FreedomVoice has been helping partners succeed.
We are committed to offering the utmost in partner support, including our "white glove" deployment-assistance program,
extensive marketing materials, and dedicated account manager assistance. We don't sell direct, so we will never compete with you.
Our success depends on our partners' success.
Don't take the risk of partnering with a relative newcomer, FreedomVoice has been succeeding in the business phone market since 1996.
We have the proven experience necessary to help you succeed with high-margin, recurring revenue!
When we say partner, we stand by it.
We provide everything our partners need to be successful. That begins with a comprehensive onboarding program that gets your team up to speed on business phone technology, market opportunities, and the FreedomVoice portfolio. Next, our free, online technical training program, FreedomVoice University, provides unlimited, on-demand access for self-paced training.
To ensure continued success, FreedomVoice provides each partner with a dedicated account manager, who provides weekly updates about new products, promotions and more. Every quarter, your account manager will meet with you to analyze your recent successes, challenges and future opportunities, and help you plan out your next 90 days of sales and marketing activity.
In an HTG member survey, FreedomVoice was rated #1 of 34 vendors for explaining how partners can make money selling the service, and #1 of all participating voice providers.
The FREE Money Program generates more recurring revenue.
FreedomVoice's FREE Money program pays your sales team to bring us existing or prospective customers, so we can identify ways for you to sell/upsell them.
On average, partners who join the FREE Money Program
close their first deal within 18.4 days.
Collect phone bills from your existing customers/prospects. We review the bills and identify which customers can benefit from FreedomVoice services. Your sales team gets the qualified targets.
FreedomVoice created the FREE Leads program to make it easier for our partners to find/qualify leads.
Just provide FreedomVoice with a list of prospects and we will send them our monthly email marketing campaigns. All qualified leads are forwarded to you! (We will never pursue or share your leads.)
We support what we sell 100%. Our product is easy to market, sell, and install.
FreedomVoice is 100% channel focused, so we will never compete with our partners.
We offer a pricing model that is unique in the industry, designed from the ground up to
give partners maximum control over the pricing and margins on service.
Ready to join the FreedomVoice family?
Let us know a little about yourself and we will schedule a time
to discuss the benefits of our Partner Program.
Have a quick question? Email email@example.com or call us at 888-262-1771.


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Book your room at TownePlace Suites by Marriott Houston Intercontinental Arpt
Please enter your travel dates.
Get an overview of this hotelFamily-friendly hotel with free breakfast and free airport shuttle
This family-friendly Houston hotel is located near the airport, 2.5 mi (4.1 km) from Houston Grand Prix, and within 6 mi (10 km) of Greenspoint Mall and Redstone Golf Club. Mercer Arboretum and Botanic Gardens and Humble Oil Patch Golf Center are also within 9 mi (15 km).
Hotel Features
An outdoor pool, a 24-hour fitness center, and a 24-hour business center are available at this smoke-free hotel. Free buffet breakfast is provided, as well as free WiFi in public areas, free self parking, and a free airport shuttle. Additionally, laundry facilities, a 24-hour front desk, and express check-in are onsite.
Room Amenities
All 134 rooms feature kitchens with refrigerators, stovetops, microwaves, and dishwashers. Other amenities available to guests include free WiFi, free wired Internet, and cable TV.Information missing or incorrect? Tell us!
Hotel Amenities
Hotel Amenities
TownePlace Suites by Marriott Houston Intercontinental Arpt features an outdoor pool and a 24-hour fitness center. High-speed wired and wireless Internet access is complimentary. A 24-hour business center is on site at this 3-star property. A complimentary breakfast is offered. A roundtrip airport shuttle at scheduled times and an area shuttle are complimentary for guests. This family-friendly hotel also offers barbecue grills, laundry facilities, and express check-in. Complimentary self parking is available on site.
TownePlace Suites by Marriott Houston Intercontinental Arpt is a smoke-free property.
- 24-hour business center
- 24-hour fitness facilities
- 24-hour front desk
- Free airport transportation
- Free area shuttle
- Barbecue grill(s)
- Elevator/lift
- Express check-in
- Free breakfast
- Free self parking
- Free WiFi
- Free wired high-speed Internet
- Laundry facilities
- Number of buildings/towers - 1
- Number of floors - 4
- Outdoor pool
- Smoke-free property
- Total number of rooms - 134
Family Friendly Amenities
- Area shuttle (complimentary)
- Cribs/infant beds (complimentary)
- Free Wi-Fi
- Full-sized refrigerator/freezer
- Kitchen
- Laundry facilities
- Microwave
- Outdoor pool
- Rollaway/extra beds available
Available in all rooms: Free WiFi , Free wired high-speed Internet
Available in some public areas: Free WiFi , Free wired high-speed Internet
Free self parking
Room Amenities
- Air conditioning
- Cable TV service
- Climate control
- Coffee/tea maker
- Free newspaper
- Free toiletries
- Cookware, dishware, and utensils
- Free cribs/infant beds
- Dishwasher
- Free WiFi
- Free wired high-speed Internet
- Full-sized refrigerator/freezer
- In-room safe
- Iron/ironing board
- Kitchen
- Microwave
- Private bathroom
- Rollaway/extra beds available
- Shower/tub combination
- Stovetop
Where to Eat
Guests are offered a complimentary hot/cold buffet breakfast.
Nearby Things to Do
Recreational amenities at the hotel include an outdoor pool and a 24-hour fitness center.
To make requests for specific accessibility needs, complete the "Special or Accessibility Requests" section of "Trip Preferences" when you book your hotel.
- Accessible bathroom
- Accessible parking
- In-room accessibility
Hotel Policies
Check-in time starts at 3 PM
Check-out time is noon
Payment types
Children and extra beds
- Children are welcome.
- Rollaway/extra beds are available.
- Free cribs (infant beds)!
Pets allowed
You need to know
Extra-person charges may apply and vary depending on hotel policy.
Government-issued photo identification and a credit card or cash deposit are required at check-in for incidental charges.
Special requests are subject to availability upon check-in and may incur additional charges. Special requests cannot be guaranteed.
Optional extras
- Pet fee: USD 100 per pet, per stay


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Photo Flash: First Look at Victoria Jaiani, Miguel Angel Blanco and More in Joffrey's AMERICAN LEGENDS
The "American Legends" features includes Jerome Robbins' 1945 work Interplay, an energetic, light-hearted and brightly colored ballet with music by Morton Gould that conveys the wonderful playfulness and unfettered curiosity of youth. This is one of Robbins' truly American works, with movement in the same style as his later Broadway choreography for West Side Story. Interplay hasn't been performed by the Joffrey since its Company Premiere in 1972.
The "American Legends" program also includes the Chicago Premiere of Son of Chamber Symphony, a new work choreographed by Stanton Welch, Artistic Director of the Houston Ballet, that had its World Premiere by The Joffrey at the Jacob's Pillow Festival in August, 2012. With shapes reminiscent of such classical ballets as Swan Lake, but placed within a distinctly contemporary perspective and set to a score by John Adams, Son of Chamber Symphony mixes classicism, virtuosity and exuberant theatricality.Single tickets, which range from $31 to $152, are available for purchase at The Joffrey Ballet's official Box Office located in the lobby of Joffrey Tower, 10 E. Randolph Street, as well as the Auditorium Theatre of Roosevelt University Box Office, all Ticketmaster Ticket Centers, by telephone at (800) 982-2787, or online at www.ticketmaster.com.
Victoria Jaiani & Miguel Angel Blanco
Victoria Jaiani & Miguel Angel Blanco
Derrick Agnoletti
Christine Rocas & Joanna Wozniak
Shane Urton & Jaime Hickey
Elizabeth Hansen & Michael Smith
Dara Holmes & John Mark Giragosian
Caitlin Meighan & Jack Thorpe-Baker
About Author
- SAG-AFTRA Convention Continues, George Heller Memorial Awards Presented
- Hugh Jackman, Lady Gaga, and More to Appear on THE TONIGHT SHOW STARRING JIMMY FALLON
- David Leitch to Direct THE COLDEST CITY
- SAG-AFTRA Announces Gabrielle Carteris Re-Elected Executive Vice President at National Convention
- VH1's Primetime Ratings For Third Quarter Surge Ahead +34% Over Prior Quarter Among Adults 18-49
- Sara Bareilles, Idris Elba, Adam Lambert, and More to Visit LATE NIGHT WITH SETH MEYERS
- KEVIN HART PRESENTS PLASTIC CUP BOYZ to be Released on Comedy Dynamics 10/13
- The First Lady Joins Public Media Effort, American Graduate Day 2015
- Review Roundup: Matt Damon Stars in Action Adventure THE MARTIAN
- Original Motion Picture Score from Acclaimed Film THE MARTIAN Out Today
- Kaley Cuoco & More Attend Opening Day of MASTERS OF LA
- Mika Kaurismaki's THE GIRL KING Available 12/8
- Sony Classical Releases THE WALK Original Motion Picture Soundtrack Today
- Documentary PINK & BLUE: COLORS OF HEREDITARY CANCER Set for Worldwide Theatrical Premiere Tonight
- Warner Bros. Celebrates Release of PAN by Asking Audiences to 'Discover Your Neverland'
- THE DAILY SHOW's Trevor Noah to Participate In Politicon
- As World Preps or Release of SPECTRE, Gillette Celebrates 'Bond Moments' in Every Man's Life
- Innovid and Netflix Win 2015 IAB MIXX Gold Award
- Director Ridley Scott Incorporates GoPro into the Making of THE MARTIAN
- Special Screening of Documentary SIR IVAN: I AM PEACEMAN to Kick Off Transgender Awareness Campaign


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Smith Hemline Sunglasses - Women'sView Larger Image
The Smith Hemline Sunglasses offer bold temples and an oversized shape that's 100% fabulous. Low-pro Megol nose pads become grippy when wet for a secure fit in all conditions.
- Carbonic TLT (Tapered Lens Technology) lenses eliminate distortion for crystal-clear optics
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Request a Deal
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People make it happen. Spread the word to request a deal!
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From Our Editors
Bordoloi's Asian Fusion's cooks amalgamate their menu from recipes from all over Asia, including India, China, and Thailand. They whet appetites with crispy lotus wheels, a Chinese specialty, in a sweet honey sauce. For the main course, they dish portions of duck curry, garlic-stuffed red snapper, or buttery lobster stir-fries. To satisfy sweet teeth, they make a lightly fried banana with vanilla ice cream for dessert. They also happily lend their culinary expertise to catered events, such as corporate lunches, private parties, or public apologies for your tenure as mayor.
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GamersGate is the leading digital distribution platform for PC and Mac games creating easily accessible gaming experiences for gamers worldwide anytime, anywhere.
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Apple Event - iPad Pro
Apple has unveiled new products for 2015. The latest iPhones, the new iPad Pro that's even bigger and the new Apple TV.
Apple Announcement
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99.84% positive ratings
Cape Town
10 Oct 2006
Classic Cassette Tape TPU Case for iPhone 4/iPhone 4S(Red)
Turn heads when walking in public with this retro inspired case. Change the color and look of your phone anytime with this removable skin.Custom tailored for ease of use all buttons, earbud jack/headphones port speakers, and camera. You must pull the case edge down to charge the device, but it's very easy and will never stretch damage the case. You do not need to remove the case entirely.


text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 24, 2002
|Filing date
|Dec 28, 2000
|Priority date
|Dec 28, 2000
|Publication number
|Thierry Besson
|Original Assignee
|Besson Thierry D.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Referenced by (17), Classifications (6), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
[0001] Appendices A-G which are a part of the present disclosure, and which are incorporated by reference herein in their entirety, are attached herewith in paper form to be submitted as a microfiche consisting of a total of XXX sheets that contain a total of YYY frames.
[0002] Appendices A-E contain source code of computer programs and related data of an illustrative embodiment of the present invention, for use in a Personal Computer, such as a PC available from Dell Corporation and running the Microsoft NT Operating System, or an Ultra 2 workstation available from Sun Microsystems, Inc, running Unix or Solaris operating system also available from Sun.
[0003] Appendix B includes a file "gnlmap.h" which defines types and data-structures to store a Generic NetList (GNL). This file also defines special generic objects like generic flip-flop, latches, tristates. This file also includes a data-structure (referenced below) named "GNL_MAP_NODE_INFO" which attaches information to a node of the netlist. A node of a netlist is of type GNL_NODE (cf. 'gnl.h') and represents a Boolean functionality.
[0004] Appendix B also includes another file "gnlmap.c" which defines the routines (referenced below) to perform a general mapping (according the optimization criterion: area, speed, power, . . . ) of the input GNL netlist and maps it into cells of a specified target library. The main function called is "GnlMap" at the end of the file. The main function mapping Boolean equations is "GnlMapGnl". For instance for the area criterion, it will call "GnlBestAreaMapNode" which performs the mapping (explained below) on a gnl node 'Node'.
[0005] Appendix B further includes the file "gnllib.c" which analyzes a target library of cells and for each of them creates the set of BDD representants (described below). For each BDD constructed a pointer points back to the corresponding cell. This global work space which has been created (Cells info+ BDDs) are used when invoking the technology mapping (cf 'gnlmap.c') of any Boolean node of the current GNL netlist.
[0006] The software in Appendices A-E can be compiled with a C compiler, e.g. available from Microsoft or Sun. Appendix F contains documentation for the computer programs and data of Appendices A-E. Appendix G contains further documentation for the computer program, and theoretical basis thereof.
[0007] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
[0008] Generally, the design of integrated circuits (ICs) is a complicated process that involves the balancing of several competing design criteria including: minimization of substrate surface area occupied by the IC, maximization of operational speed of the IC, minimization of power consumption of the IC, etc. Today's ICs are growing in size which, in turn, increases the design complexity thereof. Today's ICs have become so complicated that their design often requires the use of automated design tools to assist a designer to, for example, balance the competing design criteria noted above.
[0009] Typically, the integrated circuit design is initially created by a designer in the form of Boolean equations or an HDL description in a language such as Verilog or VHDL (Very High Speed Integrated Circuits Hardware Description Language). The design is then converted to a network consisting of vertices or nodes representing gates and edges representing the nets connecting gate outputs to gate inputs. The gates in the network (also called "technology-independent network") are generally primitive gates such as AND, OR, or NAND gates, and at this stage are independent of the technology to be used in fabrication of ICs.
[0010] One goal of automated design tools is to map a technology-independent network, into a network of cells (also called "CMDS logic cells") that are specific to fabrication. Generally, automated design tools map portions of the technology-independent network to cells of a library (also called "technology-dependent library") where each cell represents descriptions of layers of semiconductor material required to implement a gate (such as an AND gate or an OR gate) or circuit (such as a multiplexer, a latch or a flip-flop). The gates in the technology-dependent library may include primitive gates and gates with complex combinational functions. The result of mapping may be called a technology-mapped or technology-dependent network. The technology-dependent library used in automated design tools depends on the manufacturer of the IC and/or the technology used to manufacture the IC.
[0011] The technology-independent network is mapped using mapping software. Typically, some restructuring is performed by a designer to meet specified design criteria. The restructuring may involve a repetitive optimizing process in which changes are made to the network of cells with recalculations of various parameters after each change. The parameters may include propagation delay (signal speed) which is related to the time required for a change in one of the input signals to travel through the network, or portion thereof, to produce a corresponding change in an output signal. Another parameter is substrate surface area which relates to the number of transistors required to implement a given design, or a portion thereof. Still another parameter is signal drive strength which is related to the amount of current needed to drive an output of a gate to a desired signal level.
[0012] Many CAD tools in the area of circuit design use Binary Decision Diagrams (BDDs) as the underlying data structure to build models of the technology-independent network and the technology-dependent library, and thereafter compare the two types of models. A BDD is a directed acyclic graph (DAG) representation of a boolean function. The DAG has two terminal nodes labeled 0 and 1, representing the boolean values true and false. Each non-terminal node represents a boolean function. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Transactions on Computers, C-35, No. 8, pp. 667-691, 1986 (incorporated by reference herein in its entirety) introduced a reduced order BDD (abbreviated as ROBDD) data structure which is a canonical form, i.e. two boolean functions are equivalent if and only if they have the same ROBDD (assuming the same variable ordering). Bryant provided algorithms to transform a formula into a BDD and moreover he proved that logically equivalent formulae have identical ROBDD representants. ROBDDs are also described in S. Minato, N. Ishiura, S. Yajima, "Shared Binary Decision Diagrams with Attributed Edges for Efficient Boolean Function Manipulation," Proceedings of 27th Design Automation Conference, 1990, which is incorporated herein by reference in its entirety.
[0013] A website www.ics.ele.tue.nl/es/research/fv/research/research_bdd.html provides source code of a software package called "bdd" in which ROBDDs are used. The bdd package reads formulas in BDD syntax, builds a BDD graph and echoes it in sum-of-cubes representation to stdout. The bdd package is based on the article of Karl S. Brace et al, "Efficient Implementation of the BDD Package"in Proceedings of 27th ACM/IEEE Design Automation Conference, pp. 4045, June 1990 (incorporated by reference herein in its entirety). The bdd package uses a hash table to maintain a strong canonical form for the ROBDD and to improve memory usage. By using dynamic variable ordering (see: Exploiting Structural Similarities in a BDD-based Verification Method (TPCD-94, Germany)) the influence of variable ordering on the size of the BDD representation is reduced.
[0014] As stated at the above-described website, the bdd package can be used to check if a function contains another function. In this case the implication is build as a ROBDD. The resulting graph can have: depth 0 and "1" as output: the implication is true (a tautology); depth 0 and "0" as output: the implication is unsatisfiable; depth >0: the implication is satisfiable. The bdd package can also be used to compare two designs. If you write two designs in the BDD-syntax you can compare the designs with each other by stating that the outputs are equivalent. The bdd package then builds one (canonical) graph which contains both descriptions. As output it uses a function (f) which is "0" when the output behaviour of the two designs differ and is "1" if the output behaviour is the same. If the descriptions have the same output-behaviour, the BDD graph will be of depth 0 and have the value "1" (for all input vectors, the outputs of both descriptions are the same).
[0015] Other examples of software for building BDDs are available from a number of sources over the Internet, including, for example the following:
[0016] Eindhoven BDD package:
[0017] http://www.cs.cmu.edu/afs/cs/usr/bwolen/Web/fmcad98/packages/ehv.html
[0018] Berkeley BDD package:
[0019] http://www-cad.eecs.berkeley.edu/Respep/Researchlbdd/call_bdd/
[0020] Boulder Bdd package:
[0021] http://www.elen.utah.edu/˜jiunbin/cudd/
[0022] CMU Bdd package:
[0023] http://www.cs.cmu.edu/afs/cs.cmu.edu/user/bwolen/www/software/ppbf/README
[0024] More information on BDDs and ROBDDs is available on the Internet at the website www.ee.pdx.edu/˜alanmi/research/bdds.htm.
[0025] The present invention relates to mapping portions of an electrical circuit (in the form of a technology-independent network) to cells to be used in fabrication, by use of common names (also called variables) for (1) signals in the electrical circuit and (2) signals input to the cells. In one embodiment, common names are used to build a model (also called "circuit model" , such as a BDD or ROBDD) of at least a portion of the electrical circuit, and also to build models of cells. During construction of a model of one type (e.g. the circuit model), use of common names causes a portion of a previously-constructed model of the other type (e.g. a cell model) to be identified, thereby eliminating the prior art need to explicitly compare models of the two types, after both types of models are constructed. In the just-described example, a previously-constructed cell model may be identified as forming the circuit model (or a portion thereof) if a corresponding cell exists in the library.
[0026] In one implementation of such an example, constructing models of the library cells includes reading from the library data (also called "first data") that includes names of signals being input to a cell. Thereafter, the names are replaced with new names (such as a set of predetermined names that are also used (or to be used) for signals in the electrical circuit), thereby to yield data containing the new names (also called "first renamed data"). Next, a model of the cell is constructed using the first renamed data.
[0027] Depending on the embodiment, construction of the cell model may include generating binary decision diagram (BDD) or reduced order binary decision diagram (ROBDD) data from the first renamed data. The BDD (or ROBDD) data may be generated using a BDD (or ROBDD) builder, which may be of a type well known in the prior art. A relation between the BDD (or ROBDD) data and the cell is established and stored in memory for future reference, in one implementation. In one example of the relation, an identifier of a cell (such as the cell's memory address in the library) is stored in a location adjacent to the BDD (or ROBDD) data (which requires expanding a prior art data structure used to hold the BDD or ROBDD data in the builder, to accommodate the identifier). In another example of the relation, a hash table external to a prior art BDD package is used, to relate BDDs and identifiers of cells that generated the BDDs. After a circuit model has been built, a cell related to the electrical circuit portion being modeled is identified by simply looking up the identifier. Note that a number of cells may be related be related to the same model, e.g. if the cells differ only in the value of a physical parameter, such as propagation delay, power and surface area.
[0028] Modeling all (or substantially all) cells in the library before modeling the electrical circuit enables circuitry to be automatically and implicitly mapped to cells in the library, in accordance with one embodiment. In this embodiment, models of portions of the circuitry are created using some or all of the new names used in creating models of the library cells. For example, data (also called "second data") representing a portion of circuitry may be read from memory. This second data includes names of signals that are input to the circuitry. If these names are different from the above-described new names, these names are replaced with the new names (described above), to obtain second renamed data. Thereafter, models of the circuitry, such as BDD (or ROBDD) data, are generated from the second renamed data, e.g. by using the above-described BDD (or ROBDD) builder. If a cell, corresponding to the circuitry portion being modeled, exists in the library, a corresponding model, e.g. BDD (or ROBDD) data would have already been generated from the first renamed data. So a BDD (or ROBDD) builder returns the previously generated BDD (or ROBDD) data, and the above-described relation between the data and the cell is used to identify the corresponding library cell(s). If no match is found, the BDD (or ROBDD) data may be saved for later use.
[0029] In case of asymmetric cells, a number of cell models are built in one embodiment using different orders of names, to ensure that at least one of these cell models matches a circuit model (as the order of names of signals input to a circuit model depend on remaining portions of the electrical circuit). Therefore, a single asymmetric cell is related (as described above) to a number of models that differ only in the order of the input signals and/or inversion of one or more input signals. Use of multiple cell models for a single cell allows matching to occur implicitly when modeling portions of the circuitry, regardless of the order in which the names occur in the original cell and in the original circuitry.
[0030]FIG. 1 is a block diagram illustrating a computer system implementing the present invention;
[0031]FIG. 2 illustrates canonical representant set of exemplary functions built by the system of FIG. 1;
[0032]FIG. 3 illustrates data used to perform implicit matching of electrical circuitry (e.g. in the form of Boolean functions) to library cells by the system of FIG. 1;
[0033]FIG. 4 shows a more detailed example of CRS 306 of FIG. 3;
[0034]FIG. 5 illustrates a more detailed example of implicit matching in accordance with one embodiment of the present invention.
[0035]FIG. 6 is a flow chart illustrating one embodiment of constructing models of cells in accordance with the present invention;
[0036]FIG. 7 is a flow chart illustrating operational aspects of mapping candidate clusters to library cells in accordance with one embodiment of the present invention.
[0037] Technology mapping in accordance with invention can be divided into at least two acts. In a first act, at each node of a technology-independent network, a set of nodes and edges having the node as the root may be selected. This set of nodes and edges represents a portion of the technology independent circuit design and may be referred to herein as a candidate cluster or simply "cluster". In a second act, a check is performed to determine whether each cluster is realizable, i.e., if the cluster can be implemented by one or more cells from a library (which may or may not be a technology-dependent library). A cluster may be considered realizable if the cluster's function can be implemented by the function of a cell in the library, either directly, or by inverting the inputs, permuting the inputs, or inverting the outputs (i.e., if the cluster's function is NPN equivalent to a cell in the library). In the second act, the realizable clusters are used to completely cover the technology-independent network.
[0038] In one embodiment, boolean functions of clusters in the technology-independent network and cells in the technology-dependent library are not created separately and compared explicitly to determine equivalence. Instead, common names are used for signals input to cells and to a cluster so that an implicit matching is performed, e.g. while building a model, such as a BDD (or ROBDD).
[0039] Therefore, this embodiment eliminates the use of, e.g. Boolean function matching techniques described in J. R. Burch, D. E. Lond, "Efficient Boolean Function Matching," Proceedings of the International Conference-Aided Design, 1992; and S. Ercolani, G. De Micheli, "Technology Mapping for Electrically Programmable Gate Arrays," Proceedings of Design Automation Conference, 1991 and/or tree coverings as shown in K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," Proceedings of Design Automation Conference, 1987, and/or use of defined signatures or keys for each cell as shown in U. Schlichtmann, F. Brglez, M. Hermann, "Characterization of Boolean Functions for Rapid Matching in EFPA Technology Mapping," Proceedings of Design Automation Conference, 1992, and/or canonical keys as shown in U. Hinsberger, R. Kolla, "Boolean Matching for Large Libraries," Proceedings of Design Automation Conference, 1998, all of which are incorporated herein by reference in their entirety.
[0040] Use of common names (also called "variables") as described herein, in comparison with signature or key hashing based methods of the prior art, avoids hashing collision and also avoids Boolean functional comparisons (which are computationally expensive).
[0041]FIG. 1 is a block diagram illustrating a computer system 100 of one embodiment that is used for building models of library cells and for implicitly mapping candidate clusters to cells of the library, by using the cell models during modeling of candidate cluster. Computer system 100 can be a Personal Computer, such as a PC available from Dell Corporation and running the Microsoft NT Operating System, or an Ultra 2 workstation available from Sun Microsystems, Inc, running Unix or Solaris operating system also available from Sun.
[0042] Computer system 100 includes a microprocessor 102, a data memory 104 and an instruction memory 106. Data memory 104 may include a memory 104 a for storing data relating to a technology-independent network representing a to-be-fabricated electrical circuit, a memory 104 b for storing data relating to the cells of a technology-dependent library, and a memory 104 d for storing models of the cells. Data memory 104 may optionally include an additional memory 104 c for storing models of clusters which do not have a corresponding cell model in memory 104 d. Instruction memory 106 stores microprocessor executable instructions for building the models (of the cells and the clusters), and/or other microprocessor executable instructions for processing the network in memory 104 or the models in memories 104 d and 104 c.
[0043] Microprocessor 102 responds to and processes instructions contained in instruction memory 104. Memories 104 and 106 or portions thereof can be, e.g., a CD ROM, or floppy disks; a volatile computer system memory such as DRAM, SRAM, rambus RAM, etc.; or a non volatile memory such as optical storage or magnetic medium, e.g., a hard drive. The term "memory" is used interchangeably with "memory medium" herein. Memories 104 and/or 106 can include other types of memory or combinations thereof. Memories 104 and/or 106 may be located in a system 100 (FIG. 1) in which the instructions are executed, or may be located in a second system that connects to system 100 over a network. In this later instance, the second system provides the instructions to system 100 for execution.
[0044] System 100 may take various forms. In general, system 100 can encompass any device having a processor 102 that executes instructions from a memory medium 106. Instructions for implementing a system as described herein can be received by the system via a carrier medium. The carrier medium may include the memory media or storage media of the type described above in addition to a communication medium such as a network and/or wireless link which carries instructions as signals such as electrical or electromagnetic signals.
[0045] A Boolean function that models a cluster of the technology-independent network is referred to herein as a target function f. A Boolean function modeling a library cell ci is referred to herein as a pattern function fi. Both target functions and pattern function fi can be represented by data stored in the data memory 104 (FIG. 1). In one example, both target and pattern functions have a single output although multi-output functions can be used in other examples It is to be noted that none, one, or more than one cell may map to a given cluster.
[0046] In one embodiment of the present invention, binary decision diagrams (BDDs) are employed, directly or indirectly, in building models of the library cells and/or the candidate clusters. In one example of such an embodiment, reduced ordered BDDs (ROBDDs) are employed directly or indirectly, in building models of the library cells and/or the candidate clusters. The following description refers to ROBDDs, it being understood that the present invention should not be limited thereto.
[0047] A variable assignment Ak, as the term is used herein, from a Boolean vector X={x1, x2, . . . xn} to a Boolean vector Y={y1, y2, . . . yn} is a bijection between X and Y where for each index i and j, yj=Ak(xi) and xi=Ak −1(yj). Each bijection may be enumerated as follows: A1, A2, . . . Ak, and the index "k" corresponds to the enumeration index. So the notation (Ak )k means that it is a list of elements Ak with a variable "k" , e.g. (A1, A2, . . . Ak, . . . ). Since it is a bijection from a vector of n elements to a vector of n elements, there will be n! bijections, from A1 to An!. Y=Ak(X) is referred to herein as the assignment from X to Y. Lamda(X,Y) is the set of all possible variable assignments (Ak )from X to Y.
[0048] Letƒ be a Boolean target function and let vector Xbe the input variables ofƒ (i.e., f=f(X). The ROBDD built on the function f(Y=Ak(X)) with the ordering (y1< . . . <yi . . . <yn) is referred to herein as a canonical representant ofƒ upon vector Y for variable assignment Ak and is designated RY=Ak(X)(f). The canonical representant set ofƒ upon a set of variables Y=(y1, , . . yn) is designated CRSXY(f) for each Ak which is an element of lamda(X,Y).
[0049]FIG. 2 illustrates a set 200 of ROBDD representants (ROBDDRs) for an example target functionfhaving three input variables, f=x1�x2+x3 where "�" represents a logical AND and "+" represents a logical OR, and x 1, x2 and x3 represent original variable names. ROBDDR 201 for the example target Boolean function corresponds to replacement of original names x1, x2 and x3, with the new names y1, y2 and y3 as follows: (y1=A 1(x1), y2=A 1(x2), y3=A1(x3)) and (y1=A2(x2), y2=A2(x1), y3=A2(x3)). Note that variable assignments A1 and A2 differ only in the order of the first two variable names, while the third variable name is unchanged. For this reason, a single ROBDDR 201 represents both variable name assignments A1 and A2. Similarly, ROBDDR 202 corresponds to variable assignments (y1=A3(x1), y2=A3(x2) y3=A3(x3)) and (y1=A4(x2), y2=A4(x3), y3=A4(x1)). Finally, ROBDDR 203 corresponds to variable assignments (y1=A5(x3), y2=A5(x1), y3=A5(x2)) and (y1=A6(x3), y2=A6(x2), y3=A6(x1)). It is noted that the ROBDDR set 200 for f=x1�.x2+x3 has three members ROBDDRs 201, 202 and 203 rather than six since the first two input variables x1 and x2 are symmetric to the example target function (i.e., x1�.x2=x2�x1).
[0050] If a variable assignment Ai exists from X to X' which makes a function f' (X') finctionally equivalent to a flunction f(X), then for all variable assignments Ak which are elements of Lamda(X', Y), the ROBDDRY=Ak(x')(f') ε belongs to CRSxy(f). The converse is also true. It is also true that the canonical representant set of f' andƒ are identical. This proposition is based on the principle that if two ROBDDs are functionally equivalent then they have the same unique ROBDD representant.
[0051] If a variable assignment Ak. exists for which RY=Ak(X′)(f') ε CRSXY(f), then there exists a variable assignment A1 such that ROBBDRY=Ak(X′)(f')=ROBBDRY=A1(X)(f). Consequently the ordering (y1<. . . <yi< . . . <yn) with assignments Y=Ak(X′) or Y=A1(X) produces the same ROBDDR. This means that there exists a relation between X′ and X which verifies:
[0052] As a result of the above, if the ROBDDR of a function f' with a variable assignment Ak is an element of set CRSXY(f), then f' andƒ are functionally equivalent with the assignment Ai defined by equation (2) above. This means that the functional equivalence between a target function ƒ' and a pattern functionƒ can be determined by using a single ROBDDR of f' with a variable assignment Y=Ak(X'). This also means that if f' andƒ are two equivalent functions, then they have exactly the same canonical representants set according to equation (2). Thus a single ROBDDR of a target functionf is used as described herein to determine whether the target ƒ' is functionally equivalent to a set of pattern functions fi each having the same canonical representants set. Such use of the single ROBDDR eliminates the prior art need to check equivalents (at the end) between ROBDDs (e.g. through isomorphism, unification, truth table equivalence and string comparisons).
[0053] The canonical representant set of a cells library L upon a vector Y is designated CRSY(L). A Boolean function ƒ'(X′) has matches in the library cells if for any variable assignment Ak the ROBDDRY=Ak(X′)(f′) belongs to CRSY(L). Matching cells corresponding to the set Cells(ƒ'(X′)) is defined by:
Cells (ƒ'(X′))={c iεL/∀Ak, RY=Ak(X′)(f′)εCRSXiY(fci)} (3)
[0054]FIG. 3 illustrates implicit matching of electrical circuitry (e.g. in the form of Boolean functions) to library cells in accordance with one embodiment of the present invention. More particularly, FIG. 3 shows a cells library 302 (held in memory 104 b of FIG. 1), a given Boolean function 304 (held in memory 104 a of FIG. 1) corresponding to a candidate cluster to be mapped or matched to one or more cells of library 302, a CRS 306 (held in memory 104 d), and new names y1-yn which are used to replace the original names prior to the construction of representants of the cells of library 302 and candidate clusters. The representants of CRS 306 (FIG. 3) are built by a ROBDD builder (held in memory 106 of FIG. 1) from functions representing cells in library 302 with inputs renamed to y1-yn. Pointers (e.g. pointer 310) are used to identify a relation between representants of CRS 306 and cells of library 302.
[0055] Input names x1-x3 of the Boolean function 304 (that are to be mapped to library 302) are renamed to y1-y3, which are the same variable names used in CRS 306. Boolean function 304 with renamed input variables is illustrated as function 304R in FIG. 3, and this function 304R is provided to the ROBDD builder (not shown in FIG. 3). Before the ROBDD builder builds a representant from Boolean function 304R, the ROBDD builder checks CRS 306 first to determine whether a previously built representant exists that corresponds to the Boolean function 304R. Such checking is an integral part of most prior art ROBDD builders, and is normally performed to screen out duplicate ROBDDs. In FIG. 3, at least one previously built representant 203 is determined to exist for the Boolean function 304R. Pointer 310 links this previously built representant 203 to at least one corresponding cell 311 in library 302. This one cell 311 is therefore mapped to the Boolean function 304.
[0056]FIG. 4 shows a more detailed example of CRS 306 with pointers to cells. In FIG. 4, for each representant root node 402 a- 402 g, there is a list of cells 302 a-302 g of library 302 whose functions correspond to this representant. For each pointed cell function cs there is an assignment or ordering Ai between the original input names X of gci and the new names Y. For instance the root node 402 a points to cells 302 a-302 c. Root node 402 ƒ points to cells 302 e and 302 f. Since this information is accessible at the BDD node level, the BDD node structure is extended in this embodiment in order to save pointer 310.
[0057]FIG. 5 illustrates a more detailed example of implicit matching in accordance with one embodiment of the present invention. Given a compatible assignment or ordering Ak and a function ƒ'=!(a.b+c) corresponding to node 502d of FIG. 5, a compatible assignment can be (y1=A1(a)�y2 =A1(b),y3 =A1(c)) or Y=A1(X′) where X'={a,b,c}. Then the representant of f' with its input names replaced may have a root node which is node 402 ƒ of FIG. 4 or 502 g or FIG. 5. Moreover, from this root node one or more cells which can realize function ƒ' may be identified since the one or more cells can be accessed from BDD nodes 402 ƒ or 502 g. To know the variable assignment betweenf and a gate ci, A1 may need to be composed (as defined in equation 2) with the variable assignment Ai pointing on ci.
[0058] To implement the process, ROBDD representants or models of the library cells are first formed using a ROBDD builder. FIG. 6 illustrates, in flow chart, one embodiment for building library models. More particularly, microprocessor 102 (FIG. 1) begins, in act 610, with the selection of one of the cells of the technology-dependent library stored in memory 104. In act 612, the number of different variable assignments Ak of substitute input variables Y for the selected cell is determined, if the selected cell is asymmetric. If the selected cell is not asymmetric, there is only one variable assignment. Input variables Y, or a subset thereof, may be the original input variables of the selected cell (e.g. if the original names are unique relative to one another), in which case nothing is done in act 612 for symmetric cells. It is noted that input variables Y, or subsets thereof, will be commonly used in this embodiment in generating models of a majority or all of the cells of the library (as discussed below in reference to act 620). Additionally, it is noted that input variables Y. or subsets thereof, will be used in this embodiment in constructing models of circuitry (as described below in reference to FIG. 7).
[0059] In act 614, the input variables of the pattern function fci representing the selected cell, are replaced with the input variables according to the first of the variable assignments determined in act 612. By replacing the input variables with the input variables Y, a renamed pattern function is created. Thereafter in act 616, a decision is made as to whether the renamed function matches a previously generated ROBDDR. If no previously generated ROBBDR exists which matches the function, then ROBDDR is generated for this function in act 620 and then in act 624 the selected cell is related to the ROBDDR. This relationship may be stored in memory 104 for future reference. It is noted that different pattern functions may produce identical ROBDDRs. If the renamed function matches previously generated data (e.g. if two cells are isomorphic to one another), then in act 622, an identification (e.g., memory address) of the selected cell is related to the previously generated ROBDDR. Again, this relationship may be stored in memory 104 for future reference.
[0060] In one example, the BDD data structure is extended over the prior art structure to hold the memory address of a cell, and the cell data structure is also extended to hold the memory address of an isomorphic cell. In other examples, other kinds of data structures (such as another linked list that maps a BDD pointer to a cell pointer) can be used, e.g. if source code of the ROBDD builder is not available to allow expansion of the BDD data structure.
[0061] In act 626, a determination is made as to whether a ROBDDR has been generated for each pattern function modified according to the variable assignments determined in act 612. If it is determined that a ROBDDR has not been generated for each variable assignments determined in act 612, then in act 628 the input variables of the pattern function representing the selected cell, are again replaced with the input variables Y according to the next variable assignment, thereby generating a next renamed function. Thereafter, acts 616-626 are repeated for the next renamed function. However, if it is determined that a ROBDDR has been generated from each modified pattern function, then in act 630 a determination is made as to whether a complete ROBDDR and/or corresponding ROBDDR memory address set has been generated for each of the cells of the library. If not, the next cell in the library of cells is selected in act 632. Thereafter, acts 612-630 are repeated. However, if all or substantially all of the ROBDDRs have been generated, the process of modeling the cell library ends.
[0062] Note that several of the acts illustrated in FIG. 6 can be performed by a ROBDD builder (also called "BDD package") in a manner well known in the art (e.g. acts 610, 620 and 616). Next, all matches of a given Boolean target functionƒ to one or more cells may be found using a single ROBDDR construction of f, where the construction of the single ROBDDR and/or memory thereof is performed by the ROBDD builder using the target function ƒ with its input variables replaced by the same input variables Y, or a subset thereof, used in generating the models of the library cells set forth above (presuming the original input variables of the target function are not Y. or a subset thereof).
[0063] The complexity of mapping a given Boolean function depends mainly on the method of representing the Canonical Representant Sets, and the sets can be large for cells or representative pattern functions having many variable inputs. The size of the Canonical Representant Set can be reduced if the number of possible assignments of variable names is reduced. By considering canonical signatures on each original input variable name of the library cells, some possible assignments are eliminated in some examples.
[0064] Let S(x1) be an integer which is a canonical signature of input variable xi in function ƒ(X). Then CRSxy(ƒ) is restricted to representants ROBBDRy=Ak(X)(ƒ) such that Ak verifies:
∀m, n ( y m<y n)
[0065] Ak is said compatible with respect to signature S if equation (4) above is verified. Ak will be referred to herein as a compatible assignment.
[0066] The signature S(xi) used here corresponds to the number of mintems of the function fxi, e.g. the cofactor of ƒ with respect to input variable xi. This signature is computed on a ROBDDR of ƒ and is linear in terms of the number of ROBDD nodes. In the example illustrated in FIG. 2, the following signatures are extracted: S(x1)=3, S(x2)=3, S(x3)=4. The set of possible assignments for ƒ are then (y1=A1(x1), y2=A1(x2), y3=A1(x3)), and (y1=A2 (X2), y2=A2(x1), y3=A2(x3)) and the other assignments are eliminated because there are not compatible with signature S. Then CRSxy(ƒ) has one single element which is the ROBDD 201 of FIG. 2.
[0067] The ROBDD construction of a target functions with a compatible assignment Ak also belongs to CRS(L), if L is the target library. Therefore, considering only compatible assignments when constructing ROBDDs for both pattern functions and target functions has reduced the number of representants being processed.
[0068] Given a compatible assignment Ak and a functionf corresponding to the node 201 in FIG. 2, then ƒ =!(a b +c), a compatible assignment can be (y1=A 1(a),y2=A1(b),y3=A1(c) or Y-A1(X) where X′={a,b,c}. Thenthe ROBDDRY=A1(X′)(ƒ) has a root node which is exactly the root node 402 a of FIG. 4. Moreover, from this root node the method inherits directly and implicitly all of the cells which can realize the functions ƒ′ since it can access all the cells from bdd node 202. Note that the cells found can realize the function or its complement because of the Types ROBDD representation. Generally speaking, NPN function solutions are treated in this way: Output Inversion with typed ROBDD structure, Input permutation with Canonical Representant Set, Input inversions with double-inverters insertions. Finally, to know the variable assignment betweenf and a gate cs, the method composes (as defined in equation (4)) A1with the variable assignment Ak pointing on ci.
[0069] In terms of complexity, the implicitpattern matching for a function ƒ against a library cells L needs only to identify a compatible assignment variable Ak (e.g. computing signature for each variable xi of the support of ƒ which can be done by computing a Bdd of ƒ) plus the construction of ROBDDRY=Ak(X′)(ƒ′). In the worst case, two ROBDDs constructions are necessary to find all the cells ci which match ƒ but one ROBDD construction can be enough because signatures can be also computed on RY=A1(X′)(ƒ′) itself where for each i, yi=AI(xi). If by "chance" AI is compatible with S, then one construction is enough. Practically, this is the case when function has a lot of symmetric variables (ex: Nand2, Nand3, ... needs only 1 ROBDD construction). If the max fan in of the library L is n, then the two ROBDDs can have a maximum size of 2n/n bdd nodes.
[0070]FIG. 7 is a flow chart illustrating one embodiment of the present invention for a computer to automatically map candidate clusters (represented by target function ƒ)to cells in a library L. More particularly, in act 710, a candidate cluster of a network is selected by microprocessor 102 (FIG. 1). Thereafter in act 712, the original input variables of the target finctionfrepresenting the selected candidate cluster are replaced with the input variables Y to generate a renamed function. Note that Y is identical to the Y used for modeling the cell library.
[0071] In act 714, a determination is made as to whether the ROBDDR that was previously generated matches the renamed function. If no such ROBDDR exists, microprocessor 102 generates ROBDD data from the renamed function in act 716 and saves the generated data (e.g. in memory 104 c of FIG. 1) for future use in act 717. However, if such previously generated ROBDDR exists, identifiers of all cells related to the previously generated ROBDDR are read from memory 104. In act 718, a determination is made as to whether more than one cell identification is related to the matching ROBDD data. If only one identifier is read from memory, then the cell identified by the identifier is mapped to the candidate cluster selected in act 710, as shown in act 720. However, more than one cell identifier relating to the previously generated ROBDDR may exist. In this case, as shown in act 722, one of the library cells previously related to the ROBDDR is selected according to a cost function, such as the area occupied by the cell if implemented on silicon, the speed at which the cell operates, the power consumption of the cell, etc. The acts 710-720 set forth in FIG. 7 are repeated (see act 730) for several of the candidate clusters in the Boolean logic network. Thereafter, the method ends.
[0072] The implicit pattern matching has been implemented in a tool illustrated in Appendices A-E which does quick and efficient synthesis. This tool, including the implicit pattern matching engine and the BDD package, has been written in the C language. Experimental tests have been performed on HP 735/126. These results give the optimum solution in terms of Area when mapping MCNC benchmarks with library lib2. lib. For each node, all the matching cells are identified by the implicit pattern matching procedure and then a recursive dynamic programming approach is used to get the optimum. Two options are run. A first option starts from an original netlist where single local variables are collapsed and where the general Boolean tree is transformed into a classical 2-AND/INV tree. A second option starts almost from the same 2-AND/INV Boolean tree except that for each edge between two nodes a double inverter INV is inserted. This insertion is useful to capture input polarities. This second option is better than first option because the starting Boolean tree description has been refined.
[0073] Experiments for some samples show the number of ROBDD constructions is about 1.9 times the numbers of target functions which is in practice the general cost to perform all the matches. Moreover the number of target functions increased a lot between first option and second option but then the number of cells found is much more important which leads to a larger exploration space. In experiments on other samples, the first option clearly shows an important speed-up in terms of CPU time and area improvement compared to TEMPLATE and SIS 1.3. The speed-up is about 38 times faster (resp. 114 times) than SIS 1.3 (resp. TEMPLATE) and the gain in terms of Area is about 11.1% (resp. 3%).
[0074] Regarding the second option, the CPU time is the same as SIS 1.3, and 3 times faster than TEMPLATE. The area gain in about 19.2# better than SIS 1.2 and 11.1% better than TEMPLATE. Note that sometimes the second option can drastically improve results compared to the first option. The results given by the second option are 'a priori' the optimum but it is not the case for circuit pair since TEMPLATE is better. This must come from the fact that the original Boolean networks are probably not the same. In one experiment, both original gates and following configured gates are used in second option. In the configured case, results are not much improved because with this library most of the configured cells can be built with original library cells with less cost. Note that the increase of the number of considered cells between the two cases has almost no impact on the CPU time. Only the time to build the library is a little bit longer (1 s. vs. 12 s.).
[0075] Any BDD package of the prior art can be used in the manner described herein, with the addition of an external table that relates a BDD node to a library cell. Such an external table can be implemented using a hash function, and is used to look up a cell from the signature of a BDD. For example, a hash table can store a couple of the form (bdd_node, attach_info) where the 'bddnode' is the BDD node and the attachinfo the lib.cell with the permutation info. Each couple is stored in the hash table according to the signature of the BDD node 'bdd_node'. When it is necessary to know if a BDD node 'x' is linked to a library cell microprocessor 102 looks in the hash table (instead of having directly the link through the BDD structure field) to retrieve the library cell. In using the hash table case, microprocessor 102 incurs an overhead compared to a direct attachment of a cell to the BDD node (as described next) because it will take some time to insert a couple and to retrieve it.
[0076] If source code for a BDD package is available, there is no need to use an external table. Instead, a data structure of the BDD package that defines ROBDD nodes is enlarged, by one field 310 (called "hook field"), to hold a pointer to a cell in the library, which cell is the one that was used to generate the ROBDD as illustrated in FIG. 4. One example of hook field 310 is illustrated in file 'bbdd.h' of the attached Appendix B, in the structure BDD (typedef struct BDD_STRUCT {. . . ). The hook field is used through the macro function (see file bbdd.h):
#define GetBddPtrHook(BddPtr) ((BddPtr)−>Hook) #define SetBddPtrHook(BddPtr, H) ((BddPtr)−>Hook = H)
[0077] The structure stored on the 'hook' field is of type: LIB_BDD_INFO and is used in file gnllib.c (described above):
[0078] —LibBddlnfoCreate
[0079] —GnlResetBddHook
[0080] —GnlComputeBddMinterms
[0081] —GnlVarHasSymmetricVar
[0082] —GnlGenerateDerivedCellRec
[0083] —GnlGetlnverters
[0084] —GnlGetSizeOffasicEquivalentGate and in gnlmap.c: (the technology mapping itself):
[0085] —GnlGetBestAreaCellOnNode/* use in techology mapping AREA */
[0086] —GnlGetBestPowerCellOnNode/* use in technology mapping POWER */
[0087] —GnlGetBestNLDelayCellOnNode/* use in technology mapping DELAY */
[0088] —GnlGetBestDepthCellOnNode/* mapping but not used */
[0089] —GnlGetBestNetCellOnNode/* mapping but not used */
[0090] Therefore, any bdd package can be used as described herein, regardless of whether or not it provides the capability to attach a cell to a BDD node. Although the present invention has been described in connection with several examples and embodiments, the invention is not intended to be limited to the specific forms set forth herein. For example, instead of building cell models with all permutations of names for an asymmetric cell, another embodiment uses just a single order of names and models the cluster being mapped with each of a number of permutations of names, until a matching model is found. As another example, variable names of input signals to both clusters and cells need not be replaced if input signal names of cells are used as the common names (so that only the names in clusters are replaced). Furthermore, as yet another example, no replacement need be done at all if variable names of input signals to both clusters and cells are common ab initio, for example if a CAD tool used to design the circuit formed by the clusters is programmed to use the names being used in the cells. Also, several of the acts described herein can be performed automatically one after another in the normal manner of a computer program, or one or more acts may be performed after receiving certain manual inputs (or instructions). Numerous such variants will be apparent to the skilled artisan in view of the disclosure.
[0091] Numerous alternatives, modifications, and equivalents of the embodiments and implementations described herein are encompassed by the appended claims.
|Cited Patent
|Filing date
|Publication date
|May 4, 1936
|Mar 28, 1939
|American Box Board Co
|Title not available
|Title not available
|Title not available
|Title not available
|Citing Patent
|Filing date
|Publication date
|Jan 31, 2002
|Jan 25, 2005
|Cadence Design Systems, Inc.
|Method and apparatus for performing technology mapping
|Jan 31, 2002
|Feb 8, 2005
|Cadence Design Systems, Inc.
|Method and apparatus for performing technology mapping
|Jan 31, 2002
|Feb 8, 2005
|Cadence Design Systems, Inc.
|Method and apparatus for performing technology mapping
|Jan 31, 2002
|Feb 15, 2005
|Cadence Design Systems, Inc.
|Method and apparatus for producing a circuit description of a design
|Jan 31, 2002
|Oct 11, 2005
|Cadence Design Systems, Inc.
|Method and apparatus for producing a circuit description of a design
|Jan 31, 2002
|Jan 24, 2006
|Cadence Design Systems, Inc.
|Method and apparatus for performing technology mapping
|Jan 31, 2002
|Apr 4, 2006
|Cadence Design Systems, Inc.
|Method and apparatus for specifying encoded sub-networks
|Jan 31, 2002
|Jul 11, 2006
|Cadence Design Systems, Inc.
|Method and apparatus for specifying encoded sub-networks
|Jan 31, 2002
|Aug 29, 2006
|Cadence Design Systems, Inc.
|Method and apparatus for pre-tabulating sub-networks
|Oct 7, 1999
|Nov 28, 2006
|Cadence Design Systems, Inc.
|Method and system for generic inference of sequential elements
|Jan 31, 2002
|Jun 3, 2008
|Cadence Design Systems, Inc
|Structure for storing a plurality of sub-networks
|May 17, 2006
|Jul 8, 2008
|International Business Machines Corporation
|Trace equivalence identification through structural isomorphism detection with on the fly logic writing
|Jan 31, 2002
|Jul 8, 2008
|Cadence Design Systems, Inc
|Method and apparatus for pre-tabulating sub-networks
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|Cadence Design Systems, Inc.
|Method and apparatus replacing sub-networks within an IC design
|Oct 25, 2008
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|Cadence Design Systems
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|Atrenta, Inc.
|System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
|Jan 31, 2002
|Aug 19, 2004
|Steven Teig
|Method and apparatus for pre-tabulating sub-networks
|U.S. Classification
|716/102, 716/104, 716/103
|International Classification
|Cooperative Classification
|European Classification
|Jan 24, 2002
Owner name: AVANT! CORPORATION, CALIFORNIA
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVANT! CORPORATION LLC;REEL/FRAME:013738/0467
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Creating convincing product visualizations can sometimes be a daunting task, due to the high level of detail and fidelity the artist must achieve in order to make it believable. In this multi-part, intermediate to advanced level tutorial, you will learn the many techniques needed to model a Microsoft Zune HD. Setting up your workspace for your reference images and using them as a guide, modeling complex shapes from boxes, and polygon pushing will all be covered, and can be adapted to virtually any 3D package.
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The nine remaining contestants on 'Dancing With the Stars' shook their respective wild things to movie themes this week. Carson Kressley was called "butch," the judges told Nancy Grace she was kind of a wuss, and Rob Kardashian was almost sexy. It was madness!


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Authorities say the bomb was discovered Sunday when a man moving into the house discovered a suspicious package in the garage.
The bomb exploded when bomb squad technicians tried to disarm it, but no one was injured and no damage was reported.
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In a directing career that's stretched over more than four decades, Steven Spielberg has delivered his fair share of movies about heroes, some of them in stories based on fact, others coming from the imaginations of creative writers. For every real protagonist in a Spielberg film, say Oskar Schindler or Abe Lincoln, there's a fictional one in another. Indiana Jones and Tintin come to mind. Spielberg's newest film, Opening Friday, "Bridge of Spies," is a...
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Schools left behindAugust 19,2014
It was with gratitude and appreciation that I read the top headline on the Aug. 9 newspaper, Vt. ed chief roasts No Child policy. Many thanks to our Education Secretary Rebecca Holcombe.
Having taught French, grades six through 12, I was appalled when No Child Left Behind became federal policy in 2001, appalled at the limits and consequences to be suffered by children, schools, communities, educators and education itself.
Not only can a schools standing be shattered by a single childs inability to meet strict and narrow standards, for whatever reason, but good teachers and principals can be lost and education itself can be left behind.
In a way, I suppose its an honor that nearly every school in our state is low performing: We have not caved in to a bizarre federal policy that can subject some children to discrimination and rob all children of the rich and well-rounded experience that education can and should be.
Judy Larson DiMario
FaystonMORE IN LettersOn Wednesday a team pulled into a cold, rainy Vermont town with just the hint of fall foliage in... Full StoryYou can feel it: The days are getting shorter, the cold weather is creeping in. Full StoryI just read Paul Hellers article about the Pavilion and found it very interesting. Full Story
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... Immodium, asked me to remain in my cabin for the rest of the day and said that she would send up some forms for me to complete. We also got a visit (two actually – a few hours apart) from the housekeeping staff who sprayed all the main touch areas of the cabin. I was given a form to order light meals from room service – which was delivered with the staff wearing a mask and I had to call them to collect the ...
Frites and Waffles in Belgium
... she could do about the weather and she would attempt to find shelter as often as she could. We set off in the rain through a park to the cobbled streets of the old town. There was even some thunder and lightning! Hilde led us through the narrow streets, stopping at sheltered spots to tell us about the sites. Brugges is considered to be one of the best preserved medieval cities in Northern Europe and the city center is a UNESCO World Heritage ...