text:
|Publication number
|Publication type
|Application number
|Publication date
|21 Oct 2003
|Filing date
|28 Nov 2000
|Priority date
|23 Aug 2000
|Fee status
|Publication number
|Mark M. Leather, Farhad Fouladi
|Original Assignee
|Nintendo Co., Ltd.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (445), Non-Patent Citations (192), Referenced by (143), Classifications (14), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims the benefit of U.S. Provisional Application No. 60/226,890, filed Aug. 23, 2000, the entire content of which is hereby incorporated by reference in this application.
The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly this invention relates to reconfiguring a 3D graphics pipeline to move hidden surface removal to different locations within the pipeline depending on rendering mode (e.g., alpha thresholding).
Many of us have seen films containing remarkably realistic dinosaurs, aliens, animated toys and other fanciful creatures. Such animations are made possible by computer graphics. Using such techniques, a computer graphics artist can specify how each object should look and how it should change in appearance over time, and a computer then models the objects and displays them on a display such as your television or a computer screen. The computer takes care of performing the many tasks required to make sure that each part of the displayed image is colored and shaped just right based on the position and orientation of each object in a scene, the direction in which light seems to strike each object, the surface texture of each object, and other factors.
Because computer graphics generation is complex, computer-generated three-dimensional graphics just a few years ago were mostly limited to expensive specialized flight simulators, high-end graphics workstations and supercomputers. The public saw some of the images generated by these computer systems in movies and expensive television advertisements, but most of us couldn't actually interact with the computers doing the graphics generation. All this has changed with the availability of relatively inexpensive 3D graphics platforms such as, for example, the Nintendo 64� and various 3D graphics cards now available for personal computers. It is now possible to interact with exciting 3D animations and simulations on relatively inexpensive computer graphics systems in your home or office.
A problem graphics system designers are constantly confronting is how to speed up the graphics processing. Reduced image processing time is especially important in real time graphics systems such as interactive home video games and personal computers. Real time systems generally are required to produce thirty new image frames each second.
To achieve higher speed, typical modern 3D graphics systems use a graphics pipeline to render the image. Information specifying an image goes into one end of the pipeline, and the rendered image comes out at the other end of the pipeline. The pipeline includes a number of different processing stages performing the various steps involved in rendering the image (e.g., transformation to different coordinate systems, rasterization, texturing, etc.) all at the same time. Just as you can save time laundering clothes by folding one load of laundry while another load is in the washing machine and still another load is in the dryer, a graphics pipeline saves overall processing time by simultaneously performing different stages of processing as pixels move down the pipeline.
The amount of time it takes for information to get from one end of the pipeline to the other depends on the "length" of the pipeline—that is the number of processing steps the pipeline performs to generate screen pixels for display. Shorter pipelines can process information faster, but image complexity is limited by the reduced number of image processing stages. The additional image processing stages of a longer pipeline can be used to produce more complicated and interesting images at the expense of increased processing time.
A common technique in use in many modern graphics systems today to increase speed performance allows the application programmer (e.g., video game designer) to change the length of the pipeline by turning off graphics pipeline features and processing stages that are not currently being used. For example, the application programmer can selectively turn on and off optional processing operations (e.g., texturing, texture filtering, z buffering, etc.) that take a lot of time to perform. Permitting the application programmer to choose from a menu of processing operations provides great flexibility. If the application programmer is interested in the fastest possible rendering, he or she can select cheaper (in terms of processing time) pipeline processing operations and forego the increased image complexity that would be obtainable by more expensive options. An application programmer interested in more complex images can activate, on an a la carte basis, more complex and expensive functions on an as-needed basis at the cost of increased processing time.
Hidden surface removal is an expensive but important operation performed by nearly all modern 3D graphics pipelines. To create the illusion of realism, it is important for the graphics pipeline to hide surfaces that would be hidden behind other, non-see-through surfaces. Letting the viewer see through solid opaque objects would not create a very realistic image. But in the real world, not every surface behind another surface is hidden from view. For example, you can see objects through transparent objects such as window panes. To provide realism, a 3D graphics pipeline should be able to model transparent objects as well as solid (opaque) objects, and perform hidden surface removal based upon whether or not an object in front of another object is transparent. Modern graphics systems model transparency using an additional channel called the "alpha channel" and perform "alpha thresholding" and alpha blending to achieve transparency and other effects.
One common way to perform hidden surface removal is to use something called a depth buffer. The depth buffer is also called the "z buffer" because the z axis is the depth axis. The z buffer typically provides at least one storage location for each pixel (picture element) of the image. When the graphics pipeline writes a pixel on a surface into a color frame buffer that stores the image, it also writes the depth of the surface at that pixel location into a corresponding location in the z buffer. Later, when the graphics pipeline is asked to render another surface at the same image location, it compares the depth of what it has already rendered with the depth of the new surface, relative to the viewpoint. If the new surface is in front of the already rendered surface, the graphics pipeline can discard the new surface information—since the new surface will be hidden from view. If the depth of the newly presented surface is closer to the viewer, then the graphics pipeline can replace the previously rendered pixel with a new pixel for the new surface because the new surface will hide the previously rendered surface. If the new surface is transparent, then the graphics pipeline may blend the newly presented and previously-rendered surfaces together to achieve a transparency effect.
Since hidden surface removal tends to be a rather expensive operation in terms of speed performance, it is often possible to turn off hidden surface removal at certain times (e.g., while redrawing a background image or drawing certain kinds of geometry that do not require such processing). However, altogether eliminating hidden surface removal is usually not desirable because many or most 3D images require hidden surface removal to provide realism.
The texturing stage is another processing stage found in typical modern graphics pipelines. To provide an increase in image complexity without a corresponding increase in the number of polygons that the graphics pipeline must render, graphics system designers often include the ability to apply two-dimensional textures to polygon surfaces within an image. For example, when creating an image including a tree, it is possible to draw a rectangle or triangle and place a two-dimensional picture or other image of a tree onto that surface. Texturing avoids the need to model each leaf and branch of the tree with one or more polygons, and can therefore substantially save the amount of processing time required to generate images. Another example is rendering a complicated architectural surface such as a brick wall or a wood-grained tabletop. Instead of defining each grain within the tabletop or each brick within the wall, one can image a geometric primitive defining the outlines of the wall or tabletop, and insert an appropriate texture onto that surface to provide a high degree of realism without paying a corresponding speed performance penalty for modeling each brick or each wood grain.
While texture mapping saves processing resources, the texture mapping process is not "free" by any means. Rather, texture mapping can require some relatively time consuming processing (especially when texture filtering is activated), and also requires an additional memory lookup to access the texture information. However, because texturing adds a substantial degree of realism and complexity to an image at relatively low cost, oftentimes the applications programmer wants to take advantage of it—even at the expense of increased processing time.
As can be understood from the above discussion, while various techniques are known for reducing the length of a graphics pipeline, such techniques often require the graphics system designer and/or application programmer to choose between increased image complexity and increased speed performance. Accordingly, further improvements are possible and desirable.
The present invention provides a solution to this problem by providing techniques and arrangements that move the position of z (depth) buffering in a graphics pipeline depending upon rendering mode.
Performing hidden surface removal early in a rasterizing pipeline can shorten the pipeline length for certain image information. Pixels rejected by a depth comparison operation often do not need to be processed by expensive additional processing steps such as texturing because they will be discarded anyway due to the depth comparison. By placing hidden surface removal before additional operations such as texturing, we can discard pixels based on the depth comparison operation and avoid having the pipeline waste valuable time performing expensive operations on those pixels.
On the other hand, some rendering modes require expensive operations such as texturing to be performed before the hidden surface removal operations. For example, if the application programmer has chosen to activate the alpha channel for alpha thresholding (e.g., to model transparency, or provide texture alpha mapping or other alpha-based effects), then hidden surface removal should be delayed until after the alpha operations have been performed. Otherwise, the hidden surface removal operation will not properly take the results of alpha thresholding into account.
In accordance with an aspect of our invention, we provide a reconfigurable graphics pipeline with a hidden surface removal phase that may be placed at different locations within the pipeline depending on pipeline rendering mode. When the pipeline operates in certain rendering modes, the hidden surface removal operation can be performed early in the pipeline—allowing the pipeline to discard obstructed pixels early and avoid wasting its time performing expensive operations on image portions that are obstructed by other portions of the image. For other (e.g., alpha-thresholding-based) rendering modes, the hidden surface removal operation is performed near the end of the pipeline—when the pipeline has developed sufficient additional information to resolve depth comparisons based on such rendering mode.
In accordance with one aspect provided by the invention a graphics pipeline has first and second alternate rendering modes and includes a texturing stage having an input and an output. A reconfiguration arrangement selectively places a hidden surface removal stage alternately at the input or at the output of the texturing stage depending upon the graphics pipeline rendering mode.
In accordance with another aspect of the invention, a method of dynamically reconfiguring a graphics pipeline comprises selectively activating alpha thresholding. If alpha thresholding is not activated, hidden surface removal is performed before texturing. If alpha thresholding is activated, hidden surface removal is performed after texturing.
In accordance with another aspect provided by the invention, a graphics pipeline comprises at least one processing stage including selectively activatable alpha thresholding. This processing stage includes an input and an output. A hidden surface removal stage is selectively coupled to the processing stage input or the processing stage output depending at least in part on whether alpha thresholding is activated.
Another aspect of the invention provides a pixel engine including a first input coupled to a z and edge rasterizer, and a second input coupled to a texture environment unit. A z unit is selectively, alternately coupled to the first input or the second input.
Yet another aspect of the invention provides a method of synchronizing a graphics pipeline reconfiguration comprising:
receiving a command;
stalling a graphics pipeline in response to the received command,
inserting a synchronization token into the graphics pipeline that chases pixels within the graphics pipeline while the pipeline is stalled,
detecting when the synchronization token has reached a predetermined point in the graphics pipeline to confirm that the graphics pipeline has been flushed,
reconfiguring a graphics pipeline in response to such detection to reposition a hidden surface removal stage within the pipeline, and
releasing the stall.
An advantage provided by our invention is that it maintains compatibility with expected image processing protocols and APIs while realizing increased speed performance under certain circumstances. For example, the OpenGL graphics standard requires depth buffering to be performed in response to information developed by an alpha channel. As an example, one way to render translucent objects using OpenGL is to enable depth-buffering (e.g., on a read only basis) while drawing translucent objects. Under that standard, you can draw all of the opaque objects in a scene using depth buffering in normal read/write/update operation, and then preserve those depth values by making the depth buffer read-only. When the translucent objects are drawn, their depth values are still compared to the values established by the opaque objects, so they aren't drawn if they are behind the opaque ones. However, if they are closer to the viewpoint, they don't eliminate the opaque objects since the depth-buffer values don't change. Instead, they are blended with the opaque objects. The present invention accommodates the glDepthiMask type commands implementable under OpenGL still providing the flexibility of moving depth buffering to an earlier stage in the pipeline when translucency or other alpha-based effects are not activated.
These and other features and advantages provided by the invention will be better and more completely understood by referring to the following detailed description of presently preferred embodiments in conjunction with the drawings, of which:
FIG. 1 is an overall view of an example interactive computer graphics system;
FIG. 2 is a block diagram of the FIG. 1 example computer graphics system;
FIG. 3 is a block diagram of the example graphics and audio processor shown in FIG. 2;
FIG. 4 is a block diagram of the example 3D graphics processor shown in FIG. 3;
FIG. 5 is an example logical flow diagram of the FIG. 4 graphics and audio processor;
FIG. 5A is a more detailed block diagram of an example rasterizing pipeline;
FIG. 6 is an example flowchart showing how to reconfigure a graphics pipeline;
FIGS. 7A-7F are simplified illustrations of the FIG. 6 graphics pipeline reconfiguration process;
FIG. 8 is a flowchart of an example process for dynamically reconfiguring a graphics pipeline while it is rendering a scene;
FIG. 9 shows an example reconfigurable z unit;
FIG. 10 shows an example control register format;
FIG. 11 shows example graphics pipeline balancing; and
FIGS. 12A and 12B show example alternative compatible implementations.
FIG. 1 shows an example interactive 3D computer graphics system 50. System 50 can be used to play interactive 3D video games with interesting stereo sound. It can also be used for a variety of other applications.
In this example, system 50 is capable of processing, interactively in real time, a digital representation or model of a three-dimensional world. System 50 can display some or all of the world from any arbitrary viewpoint. For example, system 50 can interactively change the viewpoint in response to real time inputs from handheld controllers 52 a, 52 b or other input devices. This allows the game player to see the world through the eyes of someone within or outside of the world. System 50 can be used for applications that do not require real time 3D interactive display (e.g., 2D display generation and/or non-interactive display), but the capability of displaying quality 3D images very quickly can be used to create very realistic and exciting game play or other graphical interactions.
To play a video game or other application using system 50, the user first connects a main unit 54 to his or her color television set 56 or other display device by connecting a cable 58 between the two. Main unit 54 produces both video signals and audio signals for controlling color television set 56. The video signals are what controls the images displayed on the television screen 59, and the audio signals are played back as sound through television stereo loudspeakers 61L, 61R.
The user also needs to connect main unit 54 to a power source. This power source may be a conventional AC adapter (not shown) that plugs into a standard home electrical wall socket and converts the house current into a lower DC voltage signal suitable for powering the main unit 54. Batteries could be used in other implementations.
The user may use hand controllers 52 a, 52 b to control main unit 54. Controls 60 can be used, for example, to specify the direction (up or down, left or right, closer or further away) that a character displayed on television 56 should move within a 3D world. Controls 60 also provide input for other applications (e.g., menu selection, pointer/cursor control, etc.). Controllers 52 can take a variety of forms. In this example, controllers 52 shown each include controls 60 such as joysticks, push buttons and/or directional switches. Controllers 52 may be connected to main unit 54 by cables or wirelessly via electromagnetic (e.g., radio or infrared) waves.
To play an application such as a game, the user selects an appropriate storage medium 62 storing the video game or other application he or she wants to play, and inserts that storage medium into a slot 64 in main unit 54. Storage medium 62 may, for example, be a specially encoded and/or encrypted optical and/or magnetic disk. The user may operate a power switch 66 to turn on main unit 54 and cause the main unit to begin running the video game or other application based on the software stored in the storage medium 62. The user may operate controllers 52 to provide inputs to main unit 54. For example, operating a control 60 may cause the game or other application to start. Moving other controls 60 can cause animated characters to move in different directions or change the user's point of view in a 3D world. Depending upon the particular software stored within the storage medium 62, the various controls 60 on the controller 52 can perform different functions at different times.
FIG. 2 shows a block diagram of example components of system 50. The primary components include:
a main processor (CPU) 110,
a main memory 112, and
a graphics and audio processor 114.
In this example, main processor 110 (e.g., an enhanced IBM Power PC 750) receives inputs from handheld controllers 108 (and/or other input devices) via graphics and audio processor 114. Main processor 110 interactively responds to user inputs, and executes a video game or other program supplied, for example, by external storage media 62 via a mass storage access device 106 such as an optical disk drive. As one example, in the context of video game play, main processor 10 can perform collision detection and animation processing in addition to a variety of interactive and control functions.
In this example, main processor 110 generates 3D graphics and audio commands and sends them to graphics and audio processor 114. The graphics and audio processor 114 processes these commands to generate interesting visual images on display 59 and interesting stereo sound on stereo loudspeakers 61R, 61L or other suitable sound-generating devices.
Example system 50 includes a video encoder 120 that receives image signals from graphics and audio processor 114 and converts the image signals into analog and/or digital video signals suitable for display on a standard display device such as a computer monitor or home color television set 56. System 50 also includes an audio codec (compressor/decompressor) 122 that compresses and decompresses digitized audio signals and may also convert between digital and analog audio signaling formats as needed. Audio codec 122 can receive audio inputs via a buffer 124 and provide them to graphics and audio processor 114 for processing (e.g., mixing with other audio signals the processor generates and/or receives via a streaming audio output of mass storage access device 106). Graphics and audio processor 114 in this example can store audio related information in an audio memory 126 that is available for audio tasks. Graphics and audio processor 114 provides the resulting audio output signals to audio codec 122 for decompression and conversion to analog signals (e.g., via buffer amplifiers 128L, 128R) so they can be reproduced by loudspeakers 61L, 61R.
Graphics and audio processor 114 has the ability to communicate with various additional devices that may be present within system 50. For example, a parallel digital bus 130 may be used to communicate with mass storage access device 106 and/or other components. A serial peripheral bus 132 may communicate with a variety of peripheral or other devices including, for example:
a programmable read-only memory and/or real time clock 134,
a modem 136 or other networking interface (which may in turn connect system 50 to a telecommunications network 138 such as the Internet or other digital network from/to which program instructions and/or data can be downloaded or uploaded), and
flash memory 140.
A further external serial bus 142 may be used to communicate with additional expansion memory 144 (e.g., a memory card) or other devices. Connectors may be used to connect various devices to busses 130, 132, 142.
FIG. 3 is a block diagram of an example graphics and audio processor 114. Graphics and audio processor 114 in one example may be a single-chip ASIC (application specific integrated circuit). In this example, graphics and audio processor 114 includes:
a processor interface 150,
a memory interface/controller 152,
a 3D graphics processor 154,
an audio digital signal processor (DSP) 156,
an audio memory interface 158,
an audio interface and mixer 160,
a peripheral controller 162, and
a display controller 164.
3D graphics processor 154 performs graphics processing tasks. Audio digital signal processor 156 performs audio processing tasks. Display controller 164 accesses image information from main memory 112 and provides it to video encoder 120 for display on display device 56. Audio interface and mixer 160 interfaces with audio codec 122, and can also mix audio from different sources (e.g., streaming audio from mass storage access device 106, the output of audio DSP 156, and external audio input received via audio codec 122). Processor interface 150 provides a data and control interface between main processor 110 and graphics and audio processor 114.
Memory interface 152 provides a data and control interface between graphics and audio processor 114 and memory 112. In this example, main processor 110 accesses main memory 112 via processor interface 150 and memory interface 152 that are part of graphics and audio processor 114. Peripheral controller 162 provides a data and control interface between graphics and audio processor 114 and the various peripherals mentioned above. Audio memory interface 158 provides an interface with audio memory 126.
FIG. 4 shows a more detailed view of an example 3D graphics processor 154. 3D graphics processor 154 includes, among other things, a command processor 200 and a 3D graphics pipeline 180. Main processor 110 communicates streams of data (e.g., graphics command streams and display lists) to command processor 200. Main processor 110 has a two-level cache 115 to minimize memory latency, and also has a write-gathering buffer 111 for uncached data streams targeted for the graphics and audio processor 114. The write-gathering buffer 111 collects partial cache lines into full cache lines and sends the data out to the graphics and audio processor 114 one cache line at a time for maximum bus usage.
Command processor 200 receives display commands from main processor 110 and parses them—obtaining any additional data necessary to process them from shared memory 112. The command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and/or 3D processing and rendering. Graphics pipeline 180 generates images based on these commands. The resulting image information may be transferred to main memory 112 for access by display controller/video interface unit 164—which displays the frame buffer output of pipeline 180 on display 56.
FIG. 5 is a logical flow diagram of graphics processor 154. Main processor 110 may store graphics command streams 210, display lists 212 and vertex arrays 214 in main memory 112, and pass pointers to command processor 200 via bus interface 150. The main processor 110 stores graphics commands in one or more graphics first-in-first-out (FIFO) buffers 210 it allocates in main memory 110. The command processor 200 fetches:
command streams from main memory 112 via an on-chip FIFO memory buffer 216 that receives and buffers the graphics commands for synchronization/flow control and load balancing,
display lists 212 from main memory 112 via an on-chip call FIFO memory buffer 218, and
vertex attributes from the command stream and/or from vertex arrays 214 in main memory 112 via a vertex cache 220.
Command processor 200 performs command processing operations 200 a that convert attribute types to floating point format, and pass the resulting complete vertex polygon data to graphics pipeline 180 for rendering/rasterization. A programmable memory arbitration circuitry 130 (see FIG. 4) arbitrates access to shared main memory 112 between graphics pipeline 180, command processor 200 and display controller/video interface unit 164.
FIG. 4 shows that graphics pipeline 180 may include:
a transform unit 300,
a setup/rasterizer 400,
a texture unit 500,
a texture environment unit 600, and
a pixel engine 700.
Transform unit 300 performs a variety of 2D and 3D transform and other operations 300 a (see FIG. 5). Transform unit 300 may include one or more matrix memories 300 b for storing matrices used in transformation processing 300 a. Transform unit 300 transforms incoming geometry per vertex from object space to screen space; and transforms incoming texture coordinates and computes projective texture coordinates (300 c). Transform unit 300 may also perform polygon clipping/culling 300 d. Lighting processing 300 e also performed by transform unit 300 b provides per vertex lighting computations for up to eight independent lights in one example embodiment. Transform unit 300 can also perform texture coordinate generation (300 c) for embossed type bump mapping effects, as well as polygon clipping/culling operations (300 d).
Setup/rasterizer 400 includes a setup unit which receives vertex data from transform unit 300 and sends triangle setup information to one or more rasterizer units (400 b) performing edge rasterization, texture coordinate rasterization and color rasterization.
Texture unit 500 (which may include an on-chip texture memory (TMEM) 502) performs various tasks related to texturing including for example:
retrieving textures 504 from main memory 112,
texture processing (500 a) including, for example, multi-texture handling, post-cache texture decompression, texture filtering, embossing, shadows and lighting through the use of projective textures, and BLIT with alpha transparency and depth,
bump map processing for computing texture coordinate displacements for bump mapping, pseudo texture and texture tiling effects (500 b), and
indirect texture processing (500 c).
Texture unit 500 outputs filtered texture values to the texture environment unit 600 for texture environment processing (600 a). Texture environment unit 600 blends polygon and texture color/alpha/depth, and can also perform texture fog processing (600 b) to achieve inverse range based fog effects. Texture environment unit 600 can provide multiple stages to perform a variety of other interesting environment-related functions based for example on color/alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending.
Pixel engine 700 performs depth (z) compare (700 a) and pixel blending (700 b). In this example, pixel engine 700 stores data into an embedded (on-chip) frame buffer memory 702. Graphics pipeline 180 may include one or more embedded DRAM memories 702 to store frame buffer and/or texture information locally. Z compares 700 a′ can also be performed at an earlier stage in the graphics pipeline 180 depending on the rendering mode currently in effect (e.g., z compares can be performed earlier if alpha thresholding is not required).
The pixel engine 700 includes a copy operation 700 c that periodically writes on-chip frame buffer 702 to main memory 112 for access by display/video interface unit 164. This copy operation 700 c can also be used to copy embedded frame buffer 702 contents to textures in the main memory 112 for dynamic texture synthesis effects. Anti-aliasing and other filtering can be performed during the copy-out operation. The frame buffer output of graphics pipeline 180 (which is ultimately stored in main memory 112) is read each frame by display/video interface unit 164. Display controller/video interface 164 provides digital RGB pixel values for display on display 102.
FIG. 5A is a more detailed block diagram of an example pipeline 118 including hidden surface removal that can be performed alternatively near the top or near the bottom of the pipeline. In this example, rasterize block 400 b (see FIG. 5) comprises an edge and depth (z) rasterizer that produces, for each pixel being processed by the pipeline 118, x,y and z information along with a coverage mask indicating whether that particular pixel is covered by a primitive being rendered. In the specific embodiment shown, edge and z rasterizer 400 b processes pixels four at a time, and provides the depth information in the form of the parameters specifying the plane equation for the surface. This is sufficient information to perform a depth comparison so long as the alpha channel is not activated. Accordingly, in such circumstances, the application programmer may command pixel engine 700 to perform hidden surface removal at the output of the edge and z rasterizer 400 b before any texturing. This "top" depth comparison 700 a ′ determines whether each pixel is hidden by a previously rendered surface, based on the contents of a z buffer 702 z. In the example embodiment, the top z comparison 700 a stores its results in a z buffer 702 z within embedded frame buffer DRAM 702.
When the application programmer has commanded pixel engine 700 to provide a "top" depth comparison 700 a′, the pixel engine encodes the results of the depth comparison in the form of a modified coverage mask. The output of edge and z rasterizer 400 b in this example provides a coverage mask that specifies whether the pixel is within or outside of the primitive. The "top" z compare 700 a′ can modify this coverage mask so it also indicates whether the pixel is obstructed by a previously rendered surface. "Top" z compare block 700 a′ provides this modified coverage mask to texture coordinate rasterizer 400 r 1 in this example. The texture coordinate rasterizer 400 r 1 examines the modified coverage mask and can discard the pixel based on the state of the coverage mask. In this particular example, the coverage mask is a simple single-bit flag (or, if supersampling for purposes of anti-aliasing is activated, the coverage mask may provide a single bit flag for each of a plurality of supersamples within the pixel).
When the top z compare block 700 a′ is activated, texture unit 500 need not waste its time generating a texture value at pixel locations that will be hidden from view. This can provide significant advantages in term of speed performance—especially in the case where texture unit 500 is a multi-cycle, recirculating texture unit providing such interesting and advantageous effects such as texture tiling and/or multi-texturing. Such texturing effects can add significant complexity and interest to an image, but they also can take a substantial amount of time to generate. The ability to discard pixels hidden from view before those pixels are processed by texture unit 500 can result in significant savings in terms of processing cycles. The saved processing cycles can be put to better use in generating additional scene complexity, or the image can be produced more rapidly.
Not all rendering modes supported by example pipeline 118 permit hidden surface removal to be performed prior to texturing a pixel. In particular, pipeline 118 can support an alpha channel in addition to the color (R, G, B) channels. As is well known, an alpha channel is very useful in providing a wide range of effects including, for example, transparency, cutouts and decaling. In the preferred embodiment, texture unit 500 supports textures having alpha values, e.g., to make cutout shapes (like billboard trees). When the alpha channel is activated, however, the fact that a surface at a particular pixel location is in front of a previously rendered surface at that same pixel location from the selected viewpoint is not enough information to resolve the hidden surface removal question. In particular, since the alpha channel permits modeling of surfaces and textures that are fully or partially transparent, a surface in front of another surface does not necessarily hide that other surface. Accordingly, when the alpha channel is turned on, it is not possible to discard pixels at an early stage based on whether or not the surface being rendered is in front of or behind a previously rendered surface relative to the current viewpoint. Therefore, in the example embodiment, the depth/hidden surface removal process is delayed in such rendering modes until after texturing, color blending and shading. The application programmer may command pixel engine 700 to perform the depth comparison at the bottom of the graphics pipeline (block 700 a)—after the pixel has been fully processed by texture unit 500, color rasterizer 400 r 2 and texture environment unit 600.
In the example embodiment, the default location for hidden surface removal is at the bottom of graphics pipeline 118 (block 700 a). However, the application programmer is encouraged to command pixel engine 700 to perform hidden surface removal near the top of the graphics pipeline 118 (activate top z compare block 700 a′) whenever possible to achieve better speed performance. However, when the texture environment unit 600 a is performing alpha thresholding functions, the application programmer should command pixel engine 700 to perform the z comparison at the bottom of the graphics pipeline 118 (block 700 a). When z compare occurs after texturing, the color and z are written to frame buffer 702 if both the z test and the alpha test pass. Application programmers should configure graphics pipeline 118 to perform z buffering after texturing to, for example, make cutout shapes (like billboard trees) that need to be correctly z buffered.
In one preferred implementation, pixel engine contains only one z unit that is alternately switched between the top and bottom of graphics pipeline 118 based on the state of a control register 701. Such an implementation saves chip real estate in a hardware implementation. Of course, duplicate or plural different z units could be provided in hardware or software logic, with one unit being activated while the other unit is set to provide a pass-through.
FIG. 6 is a flowchart of an example process to reconfigure graphics pipeline 118 by moving the hidden surface removal operation within the pipeline. FIGS. 7A-7F provide a simplified, illustrative explanation of the example FIG. 6 reconfiguration operation. FIGS. 6 and 7A-7F illustrate, among other things, that there is a penalty to paid in terms of lost processing cycles each time graphics pipeline 118 is reconfigured in this manner. FIG. 8 shows a strategy for minimizing the penalty.
FIG. 7A is a simplified view of a graphics pipeline 118. In this simplified illustration, graphics pipeline 118 is illustrated as being an actual physical pipe carrying pixels P through the various processing stages of the pipeline. Of course, this is for purposes of illustration only; in an actual implementation, graphics pipeline 118 would be implemented by electronic circuitry and/or software code.
Referring to FIGS. 6 and 7A, assume that graphics pipeline 118 has been configured to perform the depth comparison and z buffering 700 a′ near the top of the graphics pipeline. Assume further that the applications programmer writes to pixel engine control engine 701 (see FIG. 6A) commanding the pixel engine to move the depth comparison operation to the bottom of the graphics pipeline 118 (block 700 a in FIG. 5A) (e.g., to enable a rendering mode that uses alpha thresholding) (FIG. 6, block 750). In response to receipt of this command, pixel engine 700 stalls the graphics pipeline (FIG. 6, block 752). FIG. 7B illustrates this stall operation in a simplified form by showing a railroad crossing gate being lowered to prevent further pixels from passing down the graphics pipeline 118 while the pipeline reconfiguration is being dynamically performed.
In the example embodiment, pixel engine 700 inserts a token T into the pipeline (block 754). This synchronization token T chases the remaining pixels down the graphics pipeline as shown in FIG. 7B. Graphics pipeline 118 then processes all pixels remaining in the pipeline and updates the frame buffer based on the prior rendering mode (block 756). Pixel engine 700 c an tell when all of the pixels in pipeline 118 have been processed and that the pipeline has been successfully flushed by looking for the synchronization token T at the end of the graphics pipeline (FIG. 6, block 758). When token T appears at the end of the graphics pipeline 118, pixel engine 700 generates a signal (see FIG. 7C) indicating that the token has arrived and hence that the pipeline has been completely flushed (FIG. 6, 760).
Once the pipeline has been flushed, pixel engine 700 reconfigures the graphics pipeline to move the depth comparison/depth buffering operation stage from the top of the pipeline (i.e., before texture processing) to the bottom of the pipeline (FIG. 6, block 762;see FIGS. 7D, 7E). Once the pipeline has been successfully reconfigured, pixel engine 700 can release the stall (FIG. 6, block 764). This is illustrated by raising the railroad crossing gate in the FIG. 7F illustration. Pixels P can now flow through the reconfigured pipeline where hidden surface removal can now be based on alpha thresholding as well as depth comparison.
The same process in FIG. 6 can be used to reconfigure graphics pipeline 118 to move the z comparison from the bottom of the graphics pipeline to the top.
As you can see from the discussion above, there is a penalty to be paid when you dynamically reconfigure the graphics pipeline 118 in this way. In particular, the graphics pipeline 118 must be stalled and flushed before it is reconfigured, or else pixels in the pipeline will be lost and unexpected image results may occur. FIG. 8 shows one example process to dynamically reconfigure graphics pipeline 118 during rendering of a scene while minimizing the penalty. In this particular example, a scene is rendered by first setting the z compare to the top of the pipeline 118 (block 766) and then rendering all primitives that do not require alpha thresholding (block 768). When all such primitives are finished, one may then reconfigure graphics pipeline 118 to move the z compare to the bottom of the pipeline (block 770); and then, render the remaining primitives (i.e., ones with alpha) and update the frame buffer 702 based on both the results of an alpha test and a z test (block 772). The final scene may then be displayed.
Of course, blocks 766, 768 could be exchanged with blocks 770, 772 so that the primitive requiring alpha test could be rendered first and the primitives that do not require alpha test could be rendered thereafter. While it is possible to reconfigure the graphics pipeline 118 on a primitive-by-primitive basis, the penalty of doing so makes this an unattractive option and it is therefore better to sort the primitives based on whether or not they require alpha if one is dynamically change rendering modes in the middle of rendering a scene.
FIG. 9 shows an example implementation of blocks 700 a, 700 a′. The FIG. 9 example provides a series of multiplexers 776 that switch alternatively between the output of the edge and z rasterizer 700 b and the output of texture environment unit 600 a. The multiplexers 776 are controlled by the state of a "z TOP" control bit within an example pixel engine control register 701 shown in FIG. 10. Multiplexers 776 select the output of edge and z rasterizer 400 b when depth comparison/buffering is to be performed at the top of the pipeline, and select the output of texture environment unit 600 when the depth comparison/buffering is to be performed at the bottom of the pipeline.
The example z unit logic shown in FIG. 9 further includes six evaluators 778 and six z comparators 780. In this example implementation, the z evaluators 778 solve the plane equation for a pixel quad to reduce the number of wires. In particular, a single 28-bit quad Z with the format of 27.1 and Zx and Zy with the format s26.5 are sent to z unit 700 a, 700 a′. The quad Z is the value of pixel z at the center of the pixel quad. The z evaluation units 778 use 28 bit adders to perform the following equation:
where the x and the y are based on the pixel number and sample location. In the particular example, the upper three bits of the adder are for overflow/underflow clamping. Clamping is done based on the following:
000 no overflow/underflow
01x overflow, clamp to 0xffffff
0x1overflow, clamp to 0xffffff
1xx underflow, clamp to 0x000000
In the particular example shown, the Z comparison logic blocks 780 compare the output of z evaluators 778 with values read from z buffer 702 z. These values read from z buffer are depicted in this example as "Zdst." In this particular example implementation, the values from z buffer 702 z are 96-bit values. In one particular example, these stored values can be compressed and decompressed to achieve different levels of precision based on near-to-far ratio.
As shown in FIG. 9, the main CPU 110 also has access to the FIG. 9 z unit via a line "CPU z". A set of multiplexers 782 can be used to select between the output of the z evaluation blocks 778 and a z value supplied by CPU 110 for purposes of making a z comparison 780.
The FIG. 10 example control register 701 provides a "z top" control bit that may be set to 0 when z buffering is performed at the end of the graphics pipeline 118 and may be set to 1 for z buffering before texture mapping. Control register 701 also provides the ability to select between different z compression modes (e.g., linear z compression, 14 e 2 z compression, 13 e 3 z compression, 12 e 4 z compression, or inverted versions of these). Control registers for register 701 also may allow the programmer to select between different pixel types for storage into color frame buffer 702 c.
In the example embodiment, writing to control register 701 causes the pipeline stages between the edge and z rasterizer 400 b and the end of the pipeline to be flushed as described above in connection with FIGS. 6 and 7A-7F. This flushing operation can take a minimum of 90 cycles in one example embodiment. This same flushing operation can also be used as a way to synchronize texture copy operations with rendering a primitive that uses the texture being copies (e.g., in order to ensure that the entire texture being copied has been written to the frame buffer before texture unit 500 attempts to use it as a texture).
It may be necessary to balance the graphics pipeline when the FIG. 9 z unit is switched to the "bottom" z compare position. FIG. 11 shows an example pipeline balancing technique that uses a first-in-first-out buffer 790 to buffer color information while some or all of the hidden surface removal operation is performed.
The following are example API (applications programmer interface) commands that may be used in graphics system 50 to dynamically move the location of hidden surface removal within the pipeline:
This function sets whether Z buffering happens before or after texturing. Normally, Z buffering should happen before texturing, as this enables better performance by not texturing pixels that are not visible. However, when alpha compare is used, Z buffering should be done after texturing (see GXSetAphaCompare).
Enables Z-buffering before texturing when set to
GX_TRUE. Otherwise, Z-buffering takes place after
Example Usage:
void GXSetZCompLoc ( GXBool before_tex);
This function sets the Z-buffer compare mode. The result of the Z compare is used to conditionally write color values to the Embedded Frame Buffer (EFB).
When compare_enable is set to GX_DISABLE, Z buffering is disabled and the Z buffer is not updated.
The func parameter determines the comparison that is performed. In the comparison function, the newly rasterized Z value is on the left while the Z value from the Z buffer is on the right. If the result of the comparison is false, the newly rasterized pixel is discarded.
The parameter update_enable determines whether or not the Z buffer is updated with the new Z value after a comparison is performed. This parameter also affects whether the Z buffer is cleared during copy operations, see GXCopyDisp and GXCopyTex.
Enables comparisons with source and destination Z values if
GX_TRUE. Disables compares otherwise.
Z compare function. Accepted values are: GX_NEVER, GX_LESS,
Enables Z-buffer updates when GX_TRUE. Otherwise, Z-buffer
updates are disabled, but compares may still be enabled.
Example Usage:
void GXSetZMode (
update_enable );
This function sets the parameters for the alpha compare function which uses the alpha output from the last active Texture Environment (TEV) stage. The number of active TEV stages are specified using GXSetTevStages.
The output alpha can be used in the blending equation (see GXSetBlendMode) to control how source and destination (frame buffer) pixels are combined.
The alpha compare operation is:
where alpha_src is the alpha from the last active TEV stage. As an example, you can implement these equations:
The Z compare can occur either before or after texturing, see GXSetZCompLoc. In the case where Z compare occurs before texturing, the Z is written based only on the Z test. The color is written if both the Z test and alpha test pass.
When Z compare occurs after texturing, the color and Z are written if both the Z test and alpha test pass. When using texture to make cutout shapes (like billboard trees) that need to be correctly Z buffered, you should configure the pipeline to Z buffer after texturing.
comp0 Comparison subfunction 0.
ref0 Reference value for subfunction 0, 8-bit.
op Operation for combining subfunction0 and subfunction1. Accepted values are: GX_AOP_AND, GX_AOP_OR, GX_AOP_XOR, GX_AOP_XNOR.
comp1 Comparison subfunction 1.
ref1 Reference value for subfunction 1, 8-bit
Example Usage:
void GXSetAlphaCompare (
ref1 );
This function determines how the source image, generated by the graphics processor, is blended with the Embedded Frame Buffer (EFB). Color updates should be enabled by calling GXSetColorUpdate. When type is set to GX_BM_NONE, the source data is written directly to the EFB. When type is set to GX_BM_BLEND, the source color and EFB pixels are blended using the following equation:
The GX_BL_DSTALPHA/GX_BL_INVDSTALPHA can be used when the EFB has GX_PF_RGBA6_Z24 as the pixel format (see GXSetPixelFmt). If the pixel format is GX_PF_RGBA6_Z24 then the src_factor and dst_factor are also applied to the alpha channel. To write the alpha channel to the EFB you may call GXSetAlphaUpdate.
When type is set to GX_BM_LOGIC, the source and EFB pixels are blended using logical bit-wise operations.
Blending mode. Accepted values are: GX_BM_NONE,
Source factor. The pixel color produced by the graphics
processor is multiplied by this factor. Accepted values
are shown in the following table:
Factor Description
frame buffer color
1.0 - (frame buffer color)
source alpha
1.0 - (source alpha)
frame buffer alpha
1.0 - (frame buffer alpha)
Destination factor. The current frame buffer pixel color is
multiplied by this factor. Accepted values are shown
in the following table:
Factor Description
source color
1.0 - (source color)
source alpha
1.0 - (source alpha)
frame buffer alpha
1.0 - (frame buffer alpha)
Blend operation. Accepted values, and the logic operation is
shown in the table:
C-language equivalent bit-wise
dst = 0
dst = 1
dst = src
dst = ˜src
dst = dst
dst = ˜dst
dst = src & dst
dst = ˜(src & dst)
dst = src | dst
dst = ˜(src | dst)
dst = src {circumflex over ( )} dst
dst = ˜(src {circumflex over ( )} dst)
dst = src & ˜dst
dst = ˜src & dst
dst = src | ˜dst
dst = ˜src | dest
Example Usage:
void GXSetBlendMode (
op );
Certain of the above-described system components 50 could be implemented as other than the home video game console configuration described above. For example, one could run graphics application or other software written for system 50 on a platform with a different configuration that emulates system 50 or is otherwise compatible with it. If the other platform can successfully emulate, simulate and/or provide some or all of the hardware and software resources of system 50, then the other platform will be able to successfully execute the software.
As one example, an emulator may provide a hardware and/or software configuration (platform) that is different from the hardware and/or software configuration (platform) of system 50. The emulator system might include software and/or hardware components that emulate or simulate some or all of hardware and/or software components of the system for which the application software was written. For example, the emulator system could comprise a general purpose digital computer such as a personal computer, which executes a software emulator program that simulates the hardware and/or firmware of system 50.
Some general purpose digital computers (e.g., IBM or MacIntosh personal computers, and compatibles) are now equipped with 3D graphics cards that provide 3D graphics pipelines compliant with DirectX or other standard 3D graphics command APIs. They may also be equipped with stereophonic sound cards that provide high quality stereophonic sound based on a standard set of sound commands. Such multimedia-hardware-equipped personal computers running emulator software may have sufficient performance to approximate the graphics and sound performance of system 50. Emulator software controls the hardware resources on the personal computer platform to simulate the processing, 3D graphics, sound, peripheral and other capabilities of the home video game console platform for which the game programmer wrote the game software.
FIG. 12A illustrates an example overall emulation process using a host platform 1201, an emulator component 1303, and a game software executable binary image provided on a storage medium 62. Host 1201 may be a general or special purpose digital computing device such as, for example, a personal computer, a video game console, or any other platform with sufficient computing power. Emulator 1303 may be software and/or hardware that runs on host platform 1201, and provides a real-time conversion of commands, data and other information from storage medium 62 into a form that can be processed by host 1201. For example, emulator 1303 fetches "source" binary-image program instructions intended for execution by system 50 from storage medium 62 and converts these program instructions to a target format that can be executed or otherwise processed by host 1201.
As one example, in the case where the software is written for execution on a platform using an IBM PowerPC or other specific processor and the host 1201 is a personal computer using a different (e.g., Intel) processor, emulator 1303 fetches one or a sequence of binary-image program instructions from storage medium 1305 and converts these program instructions to one or more equivalent Intel binary-image program instructions. The emulator 1303 also fetches and/or generates graphics commands and audio commands intended for processing by the graphics and audio processor 114, and converts these commands into a format or formats that can be processed by hardware and/or software graphics and audio processing resources available on host 1201. As one example, emulator 1303 may convert these commands into commands that can be processed by specific graphics and/or or sound hardware of the host 1201 (e.g., using standard DirectX, OpenGL and/or sound APIs).
Certain emulators of system 50 might simply "stub" (i.e., ignore) the commands to move the hidden surface removal operation within the graphics pipeline 118. It is always possible to perform z buffering at the end of the graphics pipeline since z buffering at that location will work for all rendering modes. However, if the application writes to control register 701 (e.g., address 0x43 within the register address space provided by system 50), an emulator or other platform that ignores such a write does so at the risk of not performing a synchronization the application programmer may expect. This could result in anomalous imaging effects under certain circumstances. Therefore, some such emulators may respond to such a command to provide synchronization between events (e.g., texture copy operations) occurring within different parts of the pipeline.
An emulator 1303 used to provide some or all of the features of the video game system described above may also be provided with a graphic user interface (GUI) that simplifies or automates the selection of various options and screen modes for games run using the emulator. In one example, such an emulator 1303 may further include enhanced functionality as compared with the host platform for which the software was originally intended.
FIG. 12B illustrates an emulation host system 1201 suitable for use with emulator 1303. System 1201 includes a processing unit 1203 and a system memory 1205. A system bus 1207 couples various system components including system memory 1205 to processing unit 1203. System bus 1207 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory 1207 includes read only memory (ROM) 1252 and random access memory (RAM) 1254. A basic input/output system (BIOS) 1256, containing the basic routines that help to transfer information between elements within personal computer system 1201, such as during start-up, is stored in the ROM 1252. System 1201 further includes various drives and associated computer-readable media. A hard disk drive 1209 reads from and writes to a (typically fixed) magnetic hard disk 1211. An additional (possible optional) magnetic disk drive 1213 reads from and writes to a removable "floppy" or other magnetic disk 1215. An optical disk drive 1217 reads from and, in some configurations, writes to a removable optical disk 1219 such as a CD ROM or other optical media. Hard disk drive 1209 and optical disk drive 1217 are connected to system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. The drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, game programs and other data for personal computer system 1201. In other configurations, other types of computer-readable media that can store data that is accessible by a computer (e.g., magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, random access memories (RAMs), read only memories (ROMs) and the like) may also be used.
A number of program modules including emulator 1303 may be stored on the hard disk 1211, removable magnetic disk 1215, optical disk 1219 and/or the ROM 1252 and/or the RAM 1254 of system memory 1205. Such program modules may include an operating system providing graphics and sound APIs, one or more application programs, other program modules, program data and game data. A user may enter commands and information into personal computer system 1201 through input devices such as a keyboard 1227, pointing device 1229, microphones, joysticks, game controllers, satellite dishes, scanners, or the like. These and other input devices can be connected to processing unit 1203 through a serial port interface 1231 that is coupled to system bus 1207, but may be connected by other interfaces, such as a parallel port, game port Fire wire bus or a universal serial bus (USB). A monitor 1233 or other type of display device is also connected to system bus 1207 via an interface, such as a video adapter 1235.
System 1201 may also include a modem 1154 or other network interface means for establishing communications over a network 1152 such as the Internet. Modem 1154, which may be internal or external, is connected to system bus 123 via serial port interface 1231. A network interface 1156 may also be provided for allowing system 1201 to communicate with a remote computing device 1150 (e.g., another system 1201) via a local area network 1158 (or such communication may be via wide area network 1152 or other communications path such as dial-up or other communications means). System 1201 will typically include other peripheral output devices, such as printers and other standard peripheral devices.
In one example, video adapter 1235 may include a 3D graphics pipeline chip set providing fast 3D graphics rendering in response to 3D graphics commands issued based on a standard 3D graphics application programmer interface such as Microsoft's DirectX 7.0 or other version. A set of stereo loudspeakers 1237 is also connected to system bus 1207 via a sound generating interface such as a conventional "sound card" providing hardware and embedded software support for generating high quality stereophonic sound based on sound commands provided by bus 1207. These hardware capabilities allow system 1201 to provide sufficient graphics and sound speed performance to play software stored in storage medium 62.
All documents referred to above are hereby incorporated by reference into this specification as if expressly set forth.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.
|Cited Patent
|Filing date
|Publication date
|3 Jul 1979
|23 Jun 1981
|Takashi Sakamoto
|Linear interpolator for color correction
|20 Mar 1981
|2 Nov 1982
|Combined Logic Company
|Interactive video production system
|5 Jan 1981
|14 Jun 1983
|Atari, Inc.
|Method and apparatus for generating elliptical images on a raster-type video display
|2 Jun 1980
|10 Jan 1984
|Atari, Inc.
|Method and apparatus for generating line segments and polygonal areas on a raster-type display
|25 Sep 1981
|31 Jul 1984
|Vought Corporation
|Image processing system
|13 Sep 1982
|1 Jan 1985
|Calma Company
|Graphics display system and method including two-dimensional cache
|1 Jul 1982
|11 Feb 1986
|The Singer Company
|Modular digital image generator
|12 Dec 1983
|29 Apr 1986
|General Electric Company
|True-perspective texture/shading processor
|3 Aug 1982
|15 Jul 1986
|New York Institute Of Technology
|Three dimensional animation
|2 Aug 1983
|30 Sep 1986
|The Singer Company
|Method and apparatus for texture generation
|9 Jan 1985
|25 Nov 1986
|Evans & Sutherland Computer Corp.
|Computer graphics system of general surface rendering by exhaustive sampling
|15 Aug 1984
|24 Mar 1987
|Marconi Avionics Limited
|Display systems
|30 Jul 1984
|14 Apr 1987
|Cornell Research Foundation, Inc.
|Pipelined, line buffered real-time color graphics display system
|15 Nov 1985
|8 Sep 1987
|General Electric Company
|Memory efficient cell texturing for advanced video object generator
|27 Sep 1984
|22 Sep 1987
|Honeywell Information Systems Inc.
|Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
|5 Jun 1985
|1 Dec 1987
|General Electric Company
|System and method for the display of surface structures contained within the interior region of a solid body
|27 Apr 1984
|16 Feb 1988
|Xtar Corporation
|High-speed video graphics system and method for generating solid polygons on a raster display
|27 Jun 1986
|30 Aug 1988
|Honeywell Bull Inc.
|Read in process memory apparatus
|27 Jun 1986
|15 Nov 1988
|Honeywell Bull Inc.
|Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
|26 Sep 1985
|6 Dec 1988
|Dainippon Screen Mfg. Co., Ltd.
|Processing method of image data and system therefor
|13 Apr 1984
|28 Feb 1989
|Megatek Corporation
|Digital vector generator for a graphic display system
|29 Aug 1986
|14 Mar 1989
|U.S. Philips Corporation
|Processor for the elimination of concealed faces for the synthesis of images in three dimensions
|4 May 1987
|28 Mar 1989
|Schlumberger Systems And Services, Inc.
|Video stream processing system
|25 Mar 1987
|9 May 1989
|Namco Ltd.
|Image synthesizer
|5 Jul 1984
|9 May 1989
|Xerox Corporation
|Small angle image rotation using block transfers
|28 May 1987
|23 May 1989
|Bull Hn Information Systems Inc.
|Cache resiliency in processing a variety of address faults
|3 Oct 1986
|8 Aug 1989
|Evans & Sutherland Computer Corporation
|System for texturing computer graphics images
|7 Mar 1986
|29 Aug 1989
|Star Technologies, Inc.
|Geometry processor for graphics display system
|30 Oct 1987
|12 Sep 1989
|International Business Machines Corporation
|Pipelined lighting model processing system for a graphics workstation's shading function
|4 Nov 1987
|19 Dec 1989
|Schlumberger Systems, Inc.
|Guardband clipping method and apparatus for 3-D graphics display system
|19 Jun 1985
|30 Jan 1990
|Pseudo-random point sampling techniques in computer graphics
|4 Nov 1987
|13 Feb 1990
|Schlumberger Technologies, Inc.
|Normal vector shading for 3-D graphics display system
|2 Jun 1988
|6 Mar 1990
|Sun Microsystems, Inc.
|Z-buffer allocated for window identification
|18 Feb 1987
|3 Apr 1990
|Nippon Gakki Seizo Kabushiki Kaisha
|Method of filling polygonal region in video display system
|18 Jul 1989
|17 Apr 1990
|Cae-Link Corporation
|Method and apparatus for processing translucent objects
|5 Aug 1988
|19 Jun 1990
|Daikin Industries, Ltd.
|Texture mapping apparatus and method
|20 Nov 1989
|31 Jul 1990
|Schlumberger Technologies, Inc.
|Triangle processor for 3-D graphics display system
|18 Aug 1987
|23 Oct 1990
|Hewlett-Packard Company
|Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size
|18 Dec 1987
|27 Nov 1990
|General Electric Company
|Microtexture for close-in detail
|14 Jun 1989
|27 Nov 1990
|Daikin Industries Ltd.
|Mapping circuit of a CRT display device
|28 Nov 1989
|4 Dec 1990
|Hitachi, Ltd.
|Rotation processing method of image and system therefor
|14 May 1990
|29 Jan 1991
|Tektronix, Inc.
|Single bus graphics data processing pipeline with decentralized bus arbitration
|26 Aug 1988
|26 Mar 1991
|Eastman Kodak Company
|Page memory control in a raster image processor
|13 Sep 1988
|14 May 1991
|Computer Design, Inc.
|Textile design system and method
|16 Sep 1988
|21 May 1991
|Chips And Technologies, Inc.
|Method and circuitry for dual panel displays
|7 Sep 1989
|27 Aug 1991
|International Business Machines Corporation
|Graphics system shadow generation using a depth buffer
|8 Aug 1990
|8 Oct 1991
|Hewlett-Packard Company
|Graphics frame buffer with programmable tile size
|9 Dec 1988
|29 Oct 1991
|E-Machines Incorporated
|Computer display controller with reconfigurable frame buffer memory
|16 Dec 1988
|4 Feb 1992
|International Business Machines Corporation
|Solid modelling system with logic to discard redundant primitives
|10 Apr 1989
|25 Feb 1992
|Dainippon Screen Mfg. Co., Ltd.
|Method of extracting contour of a subject image from an original
|26 Mar 1991
|17 Mar 1992
|Hewlett-Packard Company
|Texture mapping for computer graphics display controller system
|23 Feb 1988
|4 Aug 1992
|Bersack Bret B
|Pixel rendering
|2 Nov 1987
|1 Sep 1992
|Matsushita Electric Industrial Co., Ltd.
|Means for eliminating hidden surface
|10 May 1990
|10 Nov 1992
|International Business Machines Corporation
|Method for adaptively providing near phong grade shading for patterns in a graphics display system
|18 Aug 1987
|8 Dec 1992
|Hewlett-Packard Company
|Graphics system with shadow ram update to the color map
|26 Apr 1990
|12 Jan 1993
|Honeywell Inc.
|Method and apparatus for generating a texture mapped perspective view
|28 Jul 1989
|20 Apr 1993
|The Trustees Of Columbia University In The City Of New York
|Separable image warping methods and systems using spatial lookup tables
|16 Mar 1990
|29 Jun 1993
|Hewlett-Packard Company
|Gradient calculation for texture mapping
|17 Apr 1991
|24 Aug 1993
|Pseudo-random point sampling techniques in computer graphics
|21 Aug 1990
|31 Aug 1993
|Apple Computer, Inc.
|Apparatus for storing information in and deriving information from a frame buffer
|20 Apr 1992
|19 Oct 1993
|Ricoh Company, Ltd.
|Three-dimensional shadow processor for an image forming apparatus
|21 Nov 1990
|7 Dec 1993
|Motorola, Inc.
|Method for executing graphics Z-compare and pixel merge instructions in a data processor
|20 Dec 1990
|7 Dec 1993
|General Electric Company
|Computer image generation method for determination of total pixel illumination due to plural light sources
|21 Aug 1992
|11 Jan 1994
|International Business Machines Corporation
|Parametric surface evaluation method and apparatus for a computer graphics display system
|28 Sep 1993
|26 Apr 1994
|Silicon Graphics, Inc.
|Z-subdivision for improved texture mapping
|18 Aug 1992
|24 May 1994
|Hughes Training, Inc.
|Multiple object pipeline display system
|20 Dec 1991
|6 Sep 1994
|Apple Computer, Inc.
|Method and apparatus for approximating a value between two endpoint values in a three-dimensional image rendering device
|19 Nov 1991
|4 Oct 1994
|Digital Equipment Corporation
|Fast tag compare and bank select in set associative cache
|15 Jul 1993
|18 Oct 1994
|Martin Marietta Corporation
|Multi-layer atmospheric fading in real-time computer image generator
|17 Aug 1993
|1 Nov 1994
|Evans & Sutherland Computer Corp.
|System for polygon interpolation using instantaneous values in a variable
|5 Dec 1989
|8 Nov 1994
|Rediffusion Simulation Limited
|Image generator for generating perspective views from data defining a model having opaque and translucent features
|29 Jan 1992
|27 Dec 1994
|International Business Machines Corporation
|Computer graphics display method and system with shadow generation
|22 May 1992
|21 Feb 1995
|International Business Machines Corporation
|Parallel rendering of smoothly shaped color triangles with anti-aliased edges for a three dimensional color display
|4 Jun 1993
|21 Feb 1995
|Sun Microsystems, Inc.
|Architecture for a high performance three dimensional graphics accelerator
|28 Jun 1991
|28 Feb 1995
|U.S. Philips Corporation
|Generating an image
|30 Sep 1994
|28 Mar 1995
|International Business Machines Corporation
|Direct display of CSG expression by use of depth buffers
|31 Oct 1991
|4 Apr 1995
|Toshiba America Information Systems, Inc.
|External interface for a high performance graphics adapter allowing for graphics compatibility
|29 Jun 1993
|18 Apr 1995
|Digital Equipment Corporation
|Memory analysis system for dynamically displaying memory allocation and de-allocation events associated with an application program
|22 Apr 1991
|2 May 1995
|Rediffusion Simulation Limited
|Method and apparatus for generating images simulating non-homogeneous fog effects
|21 Mar 1991
|16 May 1995
|Atari Games Corporation
|Method for coloring a polygon on a video display
|23 Sep 1994
|16 May 1995
|Canon Kabushiki Kaisha
|Method and apparatus for encoding or decoding an image in accordance with image characteristics
|31 Mar 1994
|30 May 1995
|Hewlett-Packard Company
|Processing commands and data in a common pipeline path in a high-speed computer graphics system
|9 Jul 1993
|6 Jun 1995
|Kabushiki Kaisha Toshiba
|Texture address generator, texture pattern generator, texture drawing device, and texture address generating method
|1 Oct 1992
|11 Jul 1995
|University Corporation For Atmospheric Research
|Virtual reality imaging system
|16 Jun 1994
|11 Jul 1995
|Intel Corporation
|Integrated graphics and video computer display system
|12 Nov 1993
|1 Aug 1995
|Toshiba America Information Systems
|External interface for a high performance graphics adapter allowing for graphics compatibility
|28 Apr 1994
|5 Sep 1995
|Hitachi, Ltd.
|Graphic data processing system
|15 Sep 1993
|10 Oct 1995
|International Business Machines Corporation
|High performance triangle interpolator
|18 Apr 1994
|24 Oct 1995
|International Business Machines Corporation
|Quadrant-based two-dimensional memory manager
|24 May 1993
|14 Nov 1995
|Matsushita Electric Industrial Co., Ltd.
|Method and apparatus for compensating for color in color images
|2 Aug 1993
|14 Nov 1995
|Board Of Regents Of The University Of Washington
|Imaging and graphics processing system
|4 May 1992
|21 Nov 1995
|Midway Manufacturing Company
|Three-dimensional, texture mapping display system
|26 Apr 1993
|5 Dec 1995
|Chroma Graphics
|Method and apparatus for ordering and remapping colors in images of real two- and three-dimensional objects
|10 Jul 1992
|12 Dec 1995
|Lsi Logic Corporation
|Method for 2-D affine transformation of images
|8 Mar 1994
|23 Jan 1996
|Texas Instruments Incorporated
|Plural memory access address generation employing guide table entries forming linked list
|9 Jul 1993
|6 Feb 1996
|Silicon Graphics, Inc.
|System and method of generating interactive computer graphic images incorporating three dimensional textures
|15 Jan 1991
|27 Feb 1996
|U.S. Philips Corporation
|Apparatus for converting pyramidal texture coordinates into corresponding physical texture memory addresses
|29 Jun 1993
|2 Apr 1996
|Hitachi, Ltd.
|Computer aided color design
|14 Jan 1994
|2 Apr 1996
|National Instruments Corporation
|Method and apparatus for providing picture generation and control features in a graphical data flow environment
|6 Apr 1994
|9 Apr 1996
|Cirrus Logic, Inc.
|Apparatus, systems and methods for processing video data in conjunction with a multi-format frame buffer
|17 Apr 1995
|9 Jul 1996
|Rediffusion Simulation Limited
|Method and apparatus for generating images simulating non-homogeneous fog effects
|28 Aug 1995
|6 Aug 1996
|Sun Microsystems, Inc.
|Apparatus for selecting frame buffers for display in a double buffered display system
|15 Jan 1991
|6 Aug 1996
|U.S. Philips Corporation
|Display apparatus having a display processor for storing and filtering two dimensional arrays forming a pyramidal array, and method of operating such an apparatus
|7 Mar 1994
|20 Aug 1996
|Silicon Graphics, Inc.
|Apparatus and method for integrating texture memory and interpolation logic in a computer system
|19 Sep 1994
|3 Sep 1996
|International Business Machines Corporation
|Accelerated interface between processors and hardware adapters
|16 Feb 1994
|17 Sep 1996
|Apple Computer, Inc.
|Color map tables smoothing in a color computer graphics system avoiding objectionable color shifts
|29 Mar 1995
|24 Sep 1996
|Intel Corporation
|Method & apparatus for displaying pixels from a multi-format frame buffer
|26 Aug 1993
|1 Oct 1996
|Namco Ltd.
|Image synthesizing system with surface data perspective transformation
|3 Feb 1995
|1 Oct 1996
|Apple Computer, Inc.
|Multipass graphics rendering method and apparatus with re-traverse flag
|30 Sep 1993
|8 Oct 1996
|Canon Kabushiki Kaisha
|Apparatus and method for performing lighting calculations for surfaces of three-dimensional objects
|21 Nov 1994
|15 Oct 1996
|Konami Co., Ltd.
|Image processing apparatus capable of mapping texture to each polygon of a three dimensional image
|21 Nov 1994
|12 Nov 1996
|Atari Games Corporation
|System and method for coloring polygon using dithering
|29 Nov 1995
|26 Nov 1996
|Evans & Sutherland Computer Corp.
|Direct rendering of textured height fields
|13 May 1993
|17 Dec 1996
|Fujitsu Limited
|Parallel processing three-dimensional drawing apparatus for simultaneously mapping a plurality of texture patterns
|4 Nov 1994
|14 Jan 1997
|Thrustmaster, Inc.
|Video game card having interrupt resistant behavior
|24 Mar 1995
|14 Jan 1997
|3Dlabs Inc. Ltd.
|Graphics subsystem with coarse subpixel correction
|21 Jul 1994
|4 Feb 1997
|Apple Computer, Inc.
|Error-bounded antialiased rendering of complex scenes
|7 Jun 1995
|25 Feb 1997
|Apple Computer, Inc.
|Method and apparatus for storage and retrieval of a texture map in a graphics display system
|11 Apr 1994
|4 Mar 1997
|Sega Enterprises, Ltd.
|Multi-connection device for use in game apparatus
|25 Oct 1993
|4 Mar 1997
|Nintendo Co., Ltd.
|Moving picture display apparatus and external memory used therefor
|29 Apr 1994
|4 Mar 1997
|Cirrus Logic, Inc.
|Variable pixel depth and format for video windows
|15 May 1995
|1 Apr 1997
|Atari Games Corporation
|System and method of shadowing an object in motion
|26 Aug 1993
|15 Apr 1997
|Namco Ltd.
|Image synthesizing system
|31 Jul 1995
|13 May 1997
|Microsoft Corporation
|Apparatus and method for bidirectional data communication in a game port
|15 May 1995
|10 Jun 1997
|Nvidia Corporation
|Method and apparatus for providing flow control with lying for input/output operations in a computer system
|18 Apr 1994
|1 Jul 1997
|Avid Technology, Inc.
|Media pipeline with multichannel video processing and playback
|20 Mar 1995
|15 Jul 1997
|Silicon Graphics, Inc.
|Efficient method and apparatus for determining texture coordinates for lines and polygons
|16 Aug 1996
|22 Jul 1997
|Neomagic Corporation
|Graphics controller integrated circuit without memory interface
|25 Apr 1995
|22 Jul 1997
|Evans & Sutherland Computer Corporation
|Computer graphics system and process for adaptive supersampling
|28 Apr 1995
|12 Aug 1997
|Hitachi, Ltd.
|Graphic pattern processing apparatus
|16 May 1995
|12 Aug 1997
|Hewlett-Packard Company
|Enhanced test system for an application-specific memory scheme
|16 May 1996
|12 Aug 1997
|Rendition, Inc.
|Method and apparatus for batchable frame switch and synchronization operations
|25 Apr 1996
|19 Aug 1997
|International Business Machines Corporation
|Method and apparatus for shading graphical images in a data processing system
|28 Mar 1995
|19 Aug 1997
|Canon Kabushiki Kaisha
|Image processing apparatus
|8 May 1996
|19 Aug 1997
|Vlsi Technology, Inc.
|Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control
|3 Nov 1994
|2 Sep 1997
|Cirrus Logic, Inc.
|Graphics accelerator with dual memory controllers
|25 May 1994
|9 Sep 1997
|Canon Kabushiki Kaisha
|Outline discrimination and processing
|16 Sep 1994
|14 Oct 1997
|Vlsi Technology, Inc.
|Hardware graphics accelerator system and method therefor
|18 Jul 1995
|28 Oct 1997
|Silicon Integrated Systems Corp.
|Shared memory architecture of graphics frame buffer and hard disk cache
|28 Aug 1996
|4 Nov 1997
|Cirrus Logic, Inc.
|Interpolation rendering of polygons into a pixel grid
|22 Nov 1996
|11 Nov 1997
|Parametric Technology Corporation
|Real-time image generation system for simulating physical paint, drawing media, and feature modeling with 3-D graphics
|14 Apr 1995
|11 Nov 1997
|Nvidia Corporation
|Register array for utilizing burst mode transfer on local bus
|31 Jul 1996
|25 Nov 1997
|Winbond Electronics Corp.
|Digital video format conversion by upsampling decompressed data using on-the-fly interpolation and color conversion
|2 Jun 1994
|2 Dec 1997
|Accelerix Limited
|Single chip frame buffer and graphics accelerator
|7 Jun 1995
|9 Dec 1997
|The Walt Disney Company
|Method and apparatus for providing animation in a three-dimensional computer generated virtual world using a succession of textures derived from temporally related source images
|24 Mar 1995
|23 Dec 1997
|3Dlabs Inc. Ltd.
|Three-dimensional graphics subsystem with enhanced support for graphical user interface
|16 Aug 1996
|30 Dec 1997
|Neomagic Corporation
|Graphics controller integrated circuit without memory interface
|22 May 1996
|6 Jan 1998
|Silicon Graphics, Inc.
|Apparatus and method for integrating texture memory and interpolation logic in a computer system
|29 May 1996
|6 Jan 1998
|Nec Corporation
|Memory access controller
|21 Apr 1995
|3 Feb 1998
|Advanced Gravis Computer Technology, Ltd.
|Gameport communication apparatus and method
|15 May 1995
|24 Feb 1998
|Nvidia Corporation
|Apparatus adapted to be joined between the system I/O bus and I/O devices which translates addresses furnished directly by an application program
|3 Nov 1995
|3 Mar 1998
|3Dfx Interactive, Incorporated
|System and method for efficiently determining a fog blend value in processing graphical images
|11 Jul 1995
|10 Mar 1998
|Mitsubishi Denki Kabushiki Kaisha
|Mapping apparatus and method
|25 Apr 1996
|10 Mar 1998
|Mitsubishi Denki Kabushiki Kaisha
|Synchronous semiconductor memory device suitable for graphic data processing
|1 May 1996
|10 Mar 1998
|3Dlabs Inc. Ltd.
|Serial rendering system with auto-synchronization on frame blanking
|8 Sep 1995
|31 Mar 1998
|Evans & Sutherland Computer Corporation
|System and method for displaying textured polygons using planar texture interpolation
|5 Feb 1996
|14 Apr 1998
|Scitex Corporation Ltd.
|Method and apparatus for generating an artificial shadow in a two dimensional color image
|3 Nov 1995
|14 Apr 1998
|3Dfx Interactive, Incorporated
|Texture compositing apparatus and method
|22 Dec 1995
|14 Apr 1998
|Cirrus Logic, Inc.
|Dynamic arbitration priority
|15 May 1995
|14 Apr 1998
|Nvidia Corporation
|Method and apparatus for providing fifo buffer input to an input/output device used in a computer system
|20 Feb 1996
|21 Apr 1998
|Silicon Graphics, Inc.
|Method and apparatus for shadow generation through depth mapping
|27 Jun 1994
|21 Apr 1998
|Sun Microsystems, Inc.
|Method and apparatus for providing a configurable display memory for single buffered and double buffered application programs to be run singly or simultaneously
|6 Jun 1995
|28 Apr 1998
|Hewlett-Packard Company
|3D bypass for download of textures
|2 Jul 1996
|28 Apr 1998
|Sun Microsystems, Inc.
|Floating point processor for a three-dimensional graphics accelerator which includes floating point, lighting and set-up cores for improved performance
|20 Dec 1995
|5 May 1998
|Synthonics Incorporated
|Method and apparatus for converting a two dimensional motion picture into a three dimensional motion picture
|25 Mar 1996
|5 May 1998
|Peerless Systems Corporation
|Method and apparatus for displaying a page with graphics information on a continuous synchronous raster output device
|26 Jul 1996
|12 May 1998
|Hewlett-Packard Company
|System and method for accelerated occlusion culling
|6 Jun 1995
|12 May 1998
|Hewlett-Packard Company
|Texture mapping method and system
|27 Apr 1995
|12 May 1998
|Control Systems, Inc.
|Graphics accelerator chip and method
|16 Mar 1994
|12 May 1998
|Hitachi, Ltd.
|Graphic processing system
|22 Dec 1995
|19 May 1998
|Cirrus Logic, Inc.
|Method and apparatus for optimizing pixel data write operations to a tile based frame buffer
|28 Dec 1995
|26 May 1998
|Daewoo Electronics Co., Ltd.
|Apparatus for tracing contours of segmented regions
|18 Aug 1997
|26 May 1998
|Nvidia Corporation
|DMA controller translates virtual I/O device address received directly from application program command to physical i/o device address of I/O device on device bus
|6 Nov 1995
|2 Jun 1998
|Silicon Graphics, Inc.
|Method and system for providing texture using a selected portion of a texture map
|1 May 1996
|9 Jun 1998
|3Dlabs Inc., Ltd.
|Graphics pre-processing and rendering system
|10 Oct 1995
|9 Jun 1998
|Kaneko; Koichi
|Texture mapping apparatus computing texture address by fill address
|1 May 1996
|9 Jun 1998
|3Dlabs Inc. Ltd.
|Rendering architecture with selectable processing of multi-pixel spans
|15 Mar 1996
|16 Jun 1998
|Rendition, Inc.
|Pixel engine pipeline for a 3D graphics accelerator
|1 Dec 1995
|16 Jun 1998
|International Business Machines Corporation
|Computer graphics system with texture mapping
|13 Jun 1997
|16 Jun 1998
|Intel Corporation
|Method and apparatus for servicing a plurality of FIFO's in a capture gate array
|7 Jun 1995
|16 Jun 1998
|Discovision Associates
|Token-based adaptive video processing arrangement
|7 Jul 1993
|30 Jun 1998
|3Dlabs Ltd.
|Computer system with improved pixel processing capabilities
|15 Feb 1996
|7 Jul 1998
|Canon Kabushiki Kaisha
|Apparatus and method for performing perspectively correct interpolation in computer graphics in a variable direction along a line of pixels
|24 Mar 1995
|7 Jul 1998
|3Dlabs Inc. Ltd.
|Graphics subsystem with smart direct-memory-access operation
|30 Jan 1996
|14 Jul 1998
|United Microelectronics Corporation
|Main memory arbitration with priority scheduling capability including multiple priorty signal connections
|31 May 1995
|11 Aug 1998
|Sony Corporation
|Video signal reproducing apparatus
|1 May 1996
|25 Aug 1998
|3Dlabs Inc. Ltd.
|Graphics rendering system with reconfigurable pipeline sequence
|20 Apr 1995
|1 Sep 1998
|Hitachi, Ltd.
|Special purpose memory for graphics and display apparatus using the special purpose memory for graphics
|8 Aug 1995
|1 Sep 1998
|Hewlett Packard Company
|Polyline and triangle strip data management techniques for enhancing performance of computer graphics system
|13 Aug 1991
|1 Sep 1998
|Canon Kabushiki Kaisha
|Pipeline structures for full-color computer graphics
|20 Feb 1996
|1 Sep 1998
|National Semiconductor Corporation
|Data transfer from a graphics subsystem to system memory
|14 Apr 1995
|8 Sep 1998
|Nvidia Corporation
|Method and apparatus for providing a plurality of color formats from a single frame buffer
|24 Mar 1995
|8 Sep 1998
|3Dlabs Inc. Ltd.
|Graphics subsystem with fast clear capability
|8 Nov 1996
|15 Sep 1998
|Samsung Electronics Co., Ltd.
|Real-time rendering method of selectively performing bump mapping and phong shading processes and apparatus therefor
|3 Nov 1995
|15 Sep 1998
|Sierra Semiconductor Corporation
|Split video architecture for personal computers
|15 Apr 1996
|15 Sep 1998
|Silicon Graphics, Inc.
|Analytic motion blur coverage in the generation of computer graphics imagery
|23 Dec 1994
|15 Sep 1998
|Kabushiki Kaisha Toshiba
|Circuit for controlling access to a common memory based on priority
|26 Nov 1993
|29 Sep 1998
|Blixt; Stefan
|Graphics processor
|24 Mar 1995
|29 Sep 1998
|3Dlabs Inc., Ltd.
|Graphics subsystem with slaveable rasterizer
|30 Apr 1996
|6 Oct 1998
|Evans & Sutherland Computer Corporation
|Computer graphics system with adaptive pixel multisampler
|22 Aug 1995
|6 Oct 1998
|Silicon Graphics, Inc.
|Apparatus and method for selectively storing depth information of a 3-D image
|3 Aug 1992
|13 Oct 1998
|Ball Corporation
|Computer graphics vertex index cache system for polygons
|1 Jul 1996
|13 Oct 1998
|Sun Microsystems, Inc.
|Three-dimensional graphics accelerator with direct data channels for improved performance
|21 Jan 1997
|13 Oct 1998
|Hewlett-Packard Company
|Enhanced test method for an application-specific memory scheme
|2 Aug 1996
|27 Oct 1998
|Cirrus Logic, Inc.
|Apparatus for dynamic XY tiled texture caching
|21 Dec 1995
|27 Oct 1998
|S3 Incorporated
|Controller for processing different pixel data types stored in the same display memory by use of tag bits
|7 Jun 1995
|27 Oct 1998
|Discovision Associates
|Token-based adaptive video processing arrangement
|30 Apr 1996
|3 Nov 1998
|3Dfx Interactive Inc
|Level of detail texture filtering with dithering and mipmaps
|10 Jun 1996
|3 Nov 1998
|Integrated Device Technology, Inc.
|Wavelet texturing
|20 Dec 1996
|3 Nov 1998
|Cirrus Logic, Inc.
|Enhanced texture map data fetching circuit and method
|1 May 1996
|10 Nov 1998
|3D Labs
|Rendering system using 3D texture-processing hardware for accelerated 2D rendering
|7 Jun 1995
|10 Nov 1998
|Discovision Associates
|Token-based adaptive video processing arrangement
|30 Nov 1995
|17 Nov 1998
|Dye; Thomas A.
|Memory and graphics controller which performs pointer-based display list video refresh operations
|30 Dec 1996
|1 Dec 1998
|Cirrus Logic, Inc.
|Tiled linear host texture storage
|15 Dec 1995
|15 Dec 1998
|Raindrop Geomagic, Inc.
|Apparatus and method for geometric morphing
|9 Jan 1997
|22 Dec 1998
|S3 Incorporation
|Pixel reordering for improved texture mapping
|10 May 1996
|5 Jan 1999
|Cagent Technologies, Inc.
|Inverse Z-buffer and video display system having list-based control mechanism for time-deferred instructing of 3D rendering engine that also responds to supervisory immediate commands
|24 Jun 1996
|12 Jan 1999
|Loral Corporation
|Method for point sampling in computer graphics systems
|27 Nov 1996
|19 Jan 1999
|Vlsi Technology Inc
|Method and a system for the nonlinear storage of a texture map within a linear memory device
|27 May 1997
|19 Jan 1999
|Intel Corporation
|System and method for graphics data concurrency and coherency
|27 Jun 1996
|2 Feb 1999
|Microsoft Corporation
|Method and system for generating images using Gsprites
|27 Jun 1996
|9 Feb 1999
|Microsoft Corporation
|Method and system for improving shadowing in a graphics rendering system
|26 Feb 1997
|9 Feb 1999
|Evans & Sutherland Computer Corporation
|Method for rendering shadows on a graphical display
|8 Apr 1998
|9 Feb 1999
|3Dfx Interactive, Incorporated
|Texture compositing apparatus and method
|6 Jun 1997
|9 Feb 1999
|Digital Equipment Corporation
|Graphic system with read/write overlap detector
|20 Mar 1996
|9 Feb 1999
|International Business Machines Corporation
|Information-handling system, method, and article of manufacture including a mechanism for providing an improved application binary interface
|19 Jun 1995
|16 Feb 1999
|Nihon Unisys, Ltd.
|Method and apparatus for rendering of fractional pixel lists for anti-aliasing and transparency
|1 Jul 1996
|23 Feb 1999
|Sun Microsystems, Inc.
|Three-dimensional graphics accelerator which implements multiple logical buses using common data lines for improved bus communication
|19 Apr 1996
|2 Mar 1999
|Seiko Epson Corporation
|System and method for implementing an overlay pathway
|19 Apr 1996
|2 Mar 1999
|Sharp Kabushiki Kaisha
|Texture pattern memory circuit for providing plural texel data in response to a single access operation
|12 Jul 1996
|2 Mar 1999
|Silicon Graphics, Inc.
|Method and apparatus for supersampling based on the local rate of change in texture
|20 Jun 1997
|9 Mar 1999
|Silicon Graphics, Inc.
|Method system and computer program product for shading
|27 Jun 1996
|9 Mar 1999
|Microsoft Corporation
|Method and system for accessing texture data in environments with high latency in a graphics rendering system
|1 Dec 1995
|16 Mar 1999
|Lucas Digital, Ltd.
|Method and apparatus for creating lifelike digital representations of computer animated objects by providing corrective enveloping
|27 Jun 1996
|23 Mar 1999
|Microsoft Corporation
|Graphics rendering device and method for operating same
|17 May 1996
|23 Mar 1999
|Seiko Epson Corporation
|Texture memory organization based on data locality
|25 Jul 1996
|23 Mar 1999
|Microunity Systems Engineering, Inc.
|Vertex based geometry engine system for use in integrated circuit design
|7 Jun 1995
|30 Mar 1999
|Intel Corporation
|Frame buffer for storing graphics and video data
|10 Jun 1996
|6 Apr 1999
|Integrated Device Technology, Inc.
|Shared access texturing of computer graphic images
|11 Oct 1995
|6 Apr 1999
|Sega Enterprises Ltd.
|System for sub-data processor identifies the peripheral from supplied identification data and supplies data indicative of the kind of peripheral to main data processor
|9 Sep 1996
|13 Apr 1999
|Nec Corporation
|Color image display apparatus and method therefor
|20 Nov 1996
|4 May 1999
|Ikedo; Tsuneo
|Computer graphics circuit
|27 Aug 1997
|11 May 1999
|Chips & Technologies, Inc.
|Video memory controller with dynamic bus arbitration
|24 Apr 1997
|1 Jun 1999
|Matsushita Electric Industrial Co., Ltd.
|Transmitter-receiver of three-dimensional skeleton structure motions and method thereof
|30 May 1997
|1 Jun 1999
|Hewlett-Packard Co.
|Frame buffer cache for graphics applications
|19 Dec 1996
|15 Jun 1999
|Avid Technology, Inc.
|System and method using bounding volumes for assigning vertices of envelopes to skeleton elements in an animation system
|14 Jun 1996
|15 Jun 1999
|Lsi Logic Corporation
|MPEG decoder frame memory interface which is reconfigurable for different frame store architectures
|19 Jun 1992
|22 Jun 1999
|Lim; Hong Lip
|Visibility calculations for 3D computer graphics
|7 Mar 1996
|22 Jun 1999
|Powertv, Inc.
|Interpolation of pixel values and alpha values in a computer graphics display device
|28 Aug 1997
|22 Jun 1999
|Intel Corporation
|Visual frame buffer architecture
|14 Apr 1998
|29 Jun 1999
|Hitachi, Ltd.
|Special purpose memory for graphics and display apparatus using the same
|30 May 1997
|6 Jul 1999
|Hewlett Packard Company
|Caching and coherency control of multiple geometry accelerators in a computer graphics system
|23 Apr 1997
|6 Jul 1999
|Sun Microsystems, Inc.
|Performing exact garbage collection using bitmaps that identify pointer values within objects
|8 Jul 1996
|13 Jul 1999
|Ricoh Company, Ltd.
|Image processing device
|27 Sep 1996
|13 Jul 1999
|International Business Machines Corporation
|Polyhedral environment map utilizing a triangular data structure
|19 Nov 1996
|20 Jul 1999
|International Business Machines Corporation
|Efficient rendering utilizing user defined shields and windows
|11 Oct 1996
|20 Jul 1999
|Divicom Inc.
|Processing system with dynamic alteration of a color look-up table
|6 Aug 1996
|3 Aug 1999
|Interval Research Corporation
|System for image manipulation and animation using embedded constraint graphics
|30 Sep 1994
|3 Aug 1999
|Apple Computer, Inc.
|Multi-panel video display control addressing of interleaved frame buffers via CPU address conversion
|6 Nov 1996
|3 Aug 1999
|Silicon Graphics, Inc.
|System and method for buffering multiple frames while controlling latency
|24 Dec 1996
|3 Aug 1999
|Daewoo Electronics Co., Ltd.
|Method of tracing a contour of an object based on background information of the object
|27 Jun 1997
|10 Aug 1999
|Object Technology Licensing Corp
|Graphics hardware acceleration method, computer program, and system
|29 Sep 1997
|10 Aug 1999
|Neo Magic Corp.
|YUV-to-RGB conversion without multiplies using look-up tables and pre-clipping
|10 Jan 1997
|17 Aug 1999
|Hewlett Packard Company
|System and method for dynamically allocating data among geometry accelerators in a computer graphics system
|12 Nov 1996
|17 Aug 1999
|Ati Technologies
|Method and apparatus for displaying multiple windows on a display monitor
|5 Aug 1996
|17 Aug 1999
|Spiegel; Ehud
|Apparatus and methods for object border tracking
|25 Jan 1996
|24 Aug 1999
|Silicon Graphics, Inc.
|Texture mapping circuit for performing data interpolations
|17 Mar 1998
|24 Aug 1999
|Evans & Sutherland Computer Corp.
|Computer graphics system with adaptive pixel multisampler
|26 Jun 1997
|31 Aug 1999
|S3 Incorporated
|Block- and band-oriented traversal in three-dimensional triangle rendering
|31 Mar 1997
|7 Sep 1999
|Cirrus Logic, Inc.
|Method and system for efficient register sorting for three dimensional graphics
|30 Sep 1997
|7 Sep 1999
|Hewlett Packard Company
|Z buffer with degree of visibility test
|28 Feb 1997
|7 Sep 1999
|Silicon Graphics, Inc.
|Method, system, and computer program product for bump mapping in tangent space
|27 Jun 1996
|7 Sep 1999
|Microsoft Corporation
|Method and apparatus for resolving pixel data in a graphics rendering system
|25 Nov 1997
|7 Sep 1999
|Hewlett Packard Compnay
|Method and apparatus for processing graphics primitives in multiple modes using reconfigurable hardware
|30 Apr 1997
|21 Sep 1999
|Hewlett-Packard Co.
|Graphics accelerator with improved lighting processor
|18 Sep 1997
|21 Sep 1999
|Novell, Inc.
|Textured tile rotation system and method
|29 Oct 1997
|28 Sep 1999
|Vlsi Technology, Inc.
|Real time event determination in a universal serial bus system
|13 Jan 1997
|28 Sep 1999
|Hewlett-Packard Company
|Display controllers
|8 Feb 1996
|5 Oct 1999
|Industrial Technology Research Institute
|Mip map/rip map texture linear addressing memory organization and address generator
|28 Jun 1996
|12 Oct 1999
|Simulating cel animation and shading
|30 May 1997
|19 Oct 1999
|Hewlett-Packard Co.
|Caching and coherency control of multiple geometry accelerators in a computer graphics system
|31 Oct 1995
|2 Nov 1999
|International Business Machines Corporation
|Simulated three-dimensional display using bit-mapped information
|22 Dec 1997
|2 Nov 1999
|Sony Corporation
|Rendering apparatus and method
|14 Feb 1996
|9 Nov 1999
|Hitachi, Ltd.
|Three-dimensional graphic display apparatus with improved high-speed anti-aliasing
|24 Mar 1997
|9 Nov 1999
|Stan Stoneking
|Controlling personality manifestations by objects in a computer-assisted animation environment
|25 Oct 1995
|16 Nov 1999
|U.S. Philips Corporation
|Blurring for computer graphics generated images
|10 Oct 1997
|16 Nov 1999
|Cirrus Logic, Inc.
|Auto level of detail-based MIP mapping in a graphics processor
|30 Sep 1997
|16 Nov 1999
|Compaq Computer Corporation
|Accelerated graphics port read transaction merging
|30 Sep 1996
|16 Nov 1999
|Apple Computer, Inc.
|System and method for caching texture map information
|3 Feb 1997
|23 Nov 1999
|Micron Technologies, Inc.
|Method and apparatus for performing chroma key, transparency and fog operations
|21 Feb 1996
|30 Nov 1999
|Interactive Silicon, Inc.
|Graphics system including a virtual frame buffer which stores video/pixel data in a plurality of memory areas
|16 Oct 1997
|30 Nov 1999
|Hewlett-Packard Company
|Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the frame buffer
|27 Jun 1996
|7 Dec 1999
|Microsoft Corporation
|Image compression to reduce pixel and texture memory requirements in a real-time image generator
|29 Jul 1998
|7 Dec 1999
|Sun Microsystems, Inc.
|System and method for data multiplexing within geometry processing units of a three-dimensional graphics accelerator
|9 Sep 1997
|7 Dec 1999
|Compaq Computer Corporation
|Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device
|16 Dec 1997
|14 Dec 1999
|Oak Technology, Inc.
|Cache memory and method for use in generating computer graphics texture
|29 Oct 1997
|14 Dec 1999
|Cirrus Logic, Inc.
|Arbitration for shared graphics processing resources
|25 Aug 1997
|14 Dec 1999
|Chromatic Research, Inc.
|Reconfigurable texture cache
|27 Jun 1996
|21 Dec 1999
|Microsoft Corporation
|Method and system for texture mapping images with anisotropic filtering
|30 Apr 1997
|21 Dec 1999
|Hewlett-Packard Company
|Precise gradient calculation system and method for a texture mapping system of a computer graphics system
|5 Dec 1997
|21 Dec 1999
|Sega Enterprises, Ltd.
|Method of blending a plurality of pixels on a texture map and a plural pixel blending circuit and image processing device using the same
|23 Apr 1997
|28 Dec 1999
|Nintendo Co., Ltd.
|Operation controlling device and video processing system used therewith
|27 Jun 1996
|28 Dec 1999
|Microsoft Corporation
|Processor for controlling the display of rendered image layers and method for controlling same
|23 Feb 1998
|4 Jan 2000
|Avid Technology Inc.
|Method and system employing an NLE to create and modify 3D animations by mixing and compositing animation data
|9 Apr 1998
|4 Jan 2000
|S3 Incorporated
|Non-stalled requesting texture cache
|3 Feb 1998
|11 Jan 2000
|Sun Microsystems, Inc.
|Rapid computation of local eye vectors in a fixed point lighting unit
|30 Jul 1997
|18 Jan 2000
|Microsoft Corporation
|Sprite compositor and method for performing lighting and shading operations using a compositor to combine factored image layers
|12 Sep 1997
|18 Jan 2000
|Neomagic Corp.
|3D triangle rendering by texture hardware and color software using simultaneous triangle-walking and interpolation for parallel operation
|29 Oct 1996
|25 Jan 2000
|Real 3D, Inc.
|Illumination and shadow simulation in a computer graphics/imaging system
|24 Apr 1997
|1 Feb 2000
|George S. Sheng
|Video composition and position system and media signal communication system
|31 Oct 1997
|1 Feb 2000
|Foto Fantasy, Inc.
|Method of stimulating the creation of an artist's drawing or painting, and device for accomplishing same
|22 Nov 1995
|8 Feb 2000
|Nintendo Co., Ltd.
|Video game system using memory module
|30 Mar 1998
|8 Feb 2000
|Konami Co., Ltd.
|Translucent-image display apparatus, translucent-image display method, and pre-recorded and computer-readable storage medium
|30 Mar 1998
|8 Feb 2000
|Nvidia Corporation
|Method and apparatus for accelerating the transfer of graphical images
|24 Mar 1995
|15 Feb 2000
|3Dlabs Inc. Ltd.
|Integrated graphics subsystem with message-passing architecture
|4 Jun 1996
|15 Feb 2000
|Microsoft Corporation
|Feature segmentation
|9 May 1997
|22 Feb 2000
|Jenkins; Barry
|System and method of perception-based image generation and encoding
|29 Aug 1996
|22 Feb 2000
|Apple Computer, Inc.
|Modular digital image processing via an image processing chain
|11 Feb 1997
|29 Feb 2000
|Gmd - Forschungszentrum Informationstechnik Gmbh
|Image processing method and arrangement for the display of reflective objects
|29 Oct 1997
|7 Mar 2000
|International Business Machines Corporation
|Multi-port SRAM access control using time division multiplexed arbitration
|7 Mar 1997
|14 Mar 2000
|Silicon Graphics, Inc.
|Method, system, and computer program product for updating texture with overscan
|4 Aug 1997
|14 Mar 2000
|Pixar Animation Studios
|Texture mapping and other uses of scalar fields on subdivision surfaces in computer graphics and animation
|28 Jul 1997
|14 Mar 2000
|3Dlabs, Ltd
|3D graphics object copying with reduced edge artifacts
|24 Jul 1996
|14 Mar 2000
|Oak Technology, Inc.
|Pixel image enhancement system and method
|29 Oct 1998
|21 Mar 2000
|Sparta, Inc.
|System for transmission and recovery of digital data using video graphics display processor and method of operation thereof
|24 Jul 1997
|21 Mar 2000
|Sony Corporation
|Apparatus and method for storing and accessing picture generation data
|26 Jun 1997
|21 Mar 2000
|Neomagic Corporation
|Graphics controller integrated circuit without memory interface pins and associated power dissipation
|21 Mar 1997
|28 Mar 2000
|Alliance Semiconductor Corp.
|Color pixel format conversion incorporating color look-up table and post look-up arithmetic operation
|30 Jun 1997
|28 Mar 2000
|Ati Technologies, Inc.
|Method and apparatus for rendering pixel information from blended texture maps
|1 Jul 1996
|4 Apr 2000
|Sun Microsystems, Inc.
|Method and apparatus implementing high resolution rendition of Z-buffered primitives
|4 Aug 1997
|4 Apr 2000
|Hewlett-Packard Company
|Graphics application programming interface avoiding repetitive transfer of texture mapping data
|9 Feb 1999
|4 Apr 2000
|Intergraph Corporation
|Peer-to-peer parallel processing graphics accelerator
|19 Nov 1997
|11 Apr 2000
|U. S. Philips Corporation
|Method and apparatus for adjusting relative offsets between texture maps dependent upon viewpoint
|1 Apr 1998
|11 Apr 2000
|Hewlett-Packard Company
|Spatial filter for surface texture navigation
|7 Jan 1998
|18 Apr 2000
|Evans & Sutherland Computer Corporation
|Method for reducing the rendering load for high depth complexity scenes on a computer graphics display
|29 Oct 1996
|18 Apr 2000
|Fujitsu Limited
|Parallel processing three-dimensional drawing apparatus for simultaneously mapping a plurality of texture patterns
|30 Dec 1996
|18 Apr 2000
|Cirrus Logic, Inc.
|Circuit for determining non-homogenous second order perspective texture mapping coordinates using linear interpolation
|1 Oct 1997
|18 Apr 2000
|International Business Machines Corporation
|Method and apparatus for deferred clipping of polygons
|27 Jun 1997
|18 Apr 2000
|S3 Incorporated
|Multi-function controller and method for a computer graphics display system
|17 Sep 1997
|25 Apr 2000
|Cirrus Logic, Inc.
|Chroma-keyed specular texture mapping in a graphics processor
|3 May 1994
|25 Apr 2000
|Strandberg; Oerjan
|Method and apparatus for computer supported animation
|9 May 1997
|2 May 2000
|Jenkins; Barry
|System and method of image generation and encoding using primitive reprojection
|11 Sep 1997
|2 May 2000
|Gsf-Forschungszentrum Fuer Umwelt Und Gesundheit Gmbh
|Method of displaying geometric object surfaces
|2 Apr 1998
|2 May 2000
|International Business Machines Corp.
|Computer graphics system having efficient texture mapping with perspective correction
|30 Apr 1997
|2 May 2000
|Hewlett-Packard Company
|Graphics accelerator with constant color identifier
|31 Mar 1997
|2 May 2000
|Katrix, Inc.
|Limb coordination system for interactive computer animation of articulated characters with blended motion data
|2 Jun 1999
|2 May 2000
|Industrial Technology Research Institute
|Mip map/rip map texture linear addressing memory organization and address generator
|1 Jul 1997
|2 May 2000
|Memtrax Llc
|Computer system having a common display memory and main memory
|31 Oct 1997
|2 May 2000
|Compaq Computer Corporation
|Dual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfaces
|7 Mar 1997
|9 May 2000
|Phoenix Licensing, Inc.
|Digital cartoon and animation process
|16 Mar 1998
|16 May 2000
|Oak Technology, Inc.
|Method and apparatus for generating non-homogenous fog
|6 Apr 1998
|23 May 2000
|Interactive Silicon, Inc.
|Video/graphics controller which performs pointer-based display list video refresh operation
|6 Jan 1998
|30 May 2000
|Intel Corporation
|Method and apparatus for using universal serial bus keyboard to control DOS operations
|8 Jun 1998
|6 Jun 2000
|Microsoft Corporation
|Method and system for capturing and representing 3D geometry, color and shading of facial expressions and other animated objects
|22 Dec 1998
|13 Jun 2000
|Silicon Graphics, Inc.
|System and method for buffering multiple frames while controlling latency
|10 Nov 1997
|13 Jun 2000
|Silicon Grahphics, Inc.
|Packetized command interface to graphics processor
|10 Jul 1997
|20 Jun 2000
|Pacific Digital Peripherals, Inc.
|Joystick game adapter card for a personal computer
|20 Feb 1998
|20 Jun 2000
|Gmd - Forschungszentrum Informationstechnik Gmbh
|Images and apparatus for carrying out the method
|22 Apr 1998
|20 Jun 2000
|Sharp Kabushiki Kaisha
|3-D texture mapping processor and 3-D image rendering system using the same
|11 Mar 1998
|20 Jun 2000
|Compaq Computer Corporation
|Accelerated graphics port programmable memory access arbiter
|28 Aug 1997
|27 Jun 2000
|Ricoh Company, Ltd.
|Shading processing device
|12 Aug 1997
|11 Jul 2000
|Virtue, Ltd.
|Method for displaying a graphic model
|31 Mar 1997
|11 Jul 2000
|Katrix, Inc.
|Interactive motion data animation system
|5 Nov 1996
|11 Jul 2000
|Sony Corporation
|Apparatus and method for changing a video image to a drawing-style image
|14 Nov 1997
|11 Jul 2000
|3Dfx Interactive, Incorporated
|Command data transport to a graphics processing device from a CPU performing write reordering operations
|18 Dec 1997
|18 Jul 2000
|Intel Corporation
|Method and apparatus for improving processor to graphics device local memory performance
|17 Apr 1998
|18 Jul 2000
|Nvidia Corporation
|Method and apparatus for accelerating the rendering of images
|13 Jun 1997
|18 Jul 2000
|Intel Corporation
|Method and apparatus for arbitrating between command streams
|6 Feb 1998
|25 Jul 2000
|Hewlett-Packard Company
|System and method for accelerated occlusion culling
|31 Jan 1997
|1 Aug 2000
|Hughes Electronics Corporation
|Video system with selectable bit rate reduction
|18 Dec 1997
|1 Aug 2000
|Samsung Electronics Co., Ltd.
|Format converter
|26 Mar 1998
|15 Aug 2000
|Silicon Graphics, Inc.
|Method for accelerating minified textured cache access
|13 Sep 1996
|15 Aug 2000
|Silicon Graphics, Inc.
|Unified memory computer architecture with dynamic graphics memory allocation
|26 Jan 1998
|15 Aug 2000
|Adaptec, Inc.
|Method and apparatus for allocating exclusive shared resource requests in a computer system
|10 Feb 1998
|22 Aug 2000
|Intel Corporation
|Technique for performing DMA including arbitration between a chained low priority DMA and high priority DMA occurring between two links in the chained low priority
|23 Jul 1997
|29 Aug 2000
|Jenkins; Barry L.
|System and method of image generation and encoding using primitive reprojection
|4 Jun 1996
|29 Aug 2000
|3Dlabs Inc. Ltd.
|Rendering system with mini-patch retrieval from local texture storage
|18 Mar 1998
|5 Sep 2000
|Sun Microsystems, Inc.
|Method and apparatus for implementing efficient floating point Z-buffering
|30 Sep 1996
|5 Sep 2000
|Apple Computer, Inc.
|Method and apparatus for high performance antialiasing which minimizes per pixel storage and object data bandwidth
|9 Sep 1997
|12 Sep 2000
|Memtrax Llc
|Computer system controller having internal memory and external memory control
|24 Jul 1998
|3 Oct 2000
|S3 Incorporated
|Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same
|15 Apr 1998
|7 Nov 2000
|S3 Incorporated
|System and method for performing blending using an over sampling buffer
|3 Apr 1998
|7 Nov 2000
|Liu; Mei-Chi
|Guard region and hither plane vertex modification for graphics rendering
|25 Mar 1998
|21 Nov 2000
|Inprise Corporation
|Database system with methods providing a platform-independent self-describing data packet for transmitting information
|16 May 1997
|5 Dec 2000
|Nintendo Co., Ltd.
|Video game system and method with enhanced three-dimensional character and background control
|2 Jun 1998
|5 Dec 2000
|Nippon Telegraph And Telephone Corporation
|Image generating apparatus and method
|12 Dec 1997
|26 Dec 2000
|Nintendo Co., Ltd.
|Interface for a high performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
|1 Jul 1996
|9 Jan 2001
|Ricoh Company, Ltd.
|Image processing method and apparatus including hidden surface removal
|19 May 1999
|9 Jan 2001
|Ati Technologies, Inc.
|Method and apparatus for accessing graphics cache memory
|18 Sep 1998
|23 Jan 2001
|International Business Machines Corporation
|Two phase rendering for computer graphics
|22 Mar 1999
|30 Jan 2001
|Nvidia Corporation
|Graphics pipeline selectively providing multiple pixels or multiple textures
|8 Apr 1998
|20 Feb 2001
|Nvidia Corporation
|Method and apparatus for scaling texture maps for graphical images
|6 Dec 1999
|6 Mar 2001
|Transform, lighting and rasterization system embodied on a single semiconductor platform
|16 Feb 1999
|13 Mar 2001
|Nintendo Co., Ltd.
|Controller pack
|3 Apr 1998
|20 Mar 2001
|Intergraph Corporation
|Apparatus and method for applying effects to graphical images
|23 Jul 1998
|10 Apr 2001
|Microsoft Corporation
|Sprites with depth
|12 Aug 1998
|10 Apr 2001
|Monolithic System Technology, Inc.
|Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system
|2 Apr 1998
|1 May 2001
|Nvidia Corporation
|Method and apparatus for accelerating the rendering of graphical images
|21 Jan 1998
|1 May 2001
|Sun Microsystems, Inc.
|Apparatus and method for queueing structures in a multi-level non-blocking cache subsystem
|26 Mar 1998
|15 May 2001
|Silicon Graphics, Inc.
|Method for improving texture locality for pixel quads by diagonal level-of-detail calculation
|14 Aug 1998
|22 May 2001
|Silicon Graphics, Inc.
|Method and system for a RISC graphics pipeline optimized for high clock speeds by using recirculation
|17 Feb 1999
|29 May 2001
|Nintendo Co., Ltd.
|High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
|22 Oct 1998
|26 Jun 2001
|Microsoft Corporation
|Method and system for improving shadowing in a graphics rendering system
|29 May 1998
|26 Jun 2001
|Silicon Graphics, Inc.
|Method and apparatus for efficiently switching state in a graphics pipeline
|9 Oct 1996
|24 Jul 2001
|Nintendo Co., Ltd.
|Video game system with data transmitting/receiving controller
|25 Aug 1998
|31 Jul 2001
|Silicon Graphics, Incorporated
|Volumetric three-dimensional fog rendering technique
|21 Dec 1998
|14 Aug 2001
|Silicon Graphics, Inc.
|High precision texture wrapping method and device
|2 Aug 1999
|4 Sep 2001
|Trident Microsystems
|Floating-point complementary depth buffer
|29 Jul 1999
|18 Sep 2001
|Microsoft Corporation
|Image compression method to reduce pixel and texture memory requirements in graphics applications
|4 Dec 1998
|11 Dec 2001
|Silicon Motion, Inc.
|3-D graphics chip with embedded DRAM buffers
|22 Nov 1995
|18 Dec 2001
|Nintendo Co., Ltd.
|Video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
|16 Jul 1999
|15 Jan 2002
|Ati International Srl
|Method and apparatus for compressed texture caching in a video graphics system
|5 Nov 1998
|29 Jan 2002
|Nintendo Co., Ltd.
|Video game system and coprocessor for video game system
|3 Feb 1999
|5 Mar 2002
|Cache organization—direct mapped cache
|21 Dec 1999
|12 Mar 2002
|Neomagic Corporation
|Graphics controller integrated circuit without memory interface
|24 Jun 1999
|18 Jun 2002
|International Business Machines Corporation
|Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data
|23 Dec 1998
|9 Jul 2002
|Microsoft Corporation
|Processor for geometry transformations and lighting calculations
|4 Jun 1999
|30 Jul 2002
|Microsoft Corporation
|Optimization of mesh locality for transparent vertex caching
|30 May 1997
|20 Aug 2002
|Hewlett-Packard Company
|Computer graphics system having per pixel fog blending
|14 Jun 1999
|1 Oct 2002
|Sun Microsystems, Inc.
|Segmenting compressed graphics data for parallel decompression and rendering
|24 Mar 1999
|15 Oct 2002
|Microsoft Corporation
|Method and apparatus for texture memory management
|19 Jan 2000
|22 Oct 2002
|Nvidia Corporation
|Method for efficiently rendering color information for a pixel in a computer system
|14 Oct 1999
|5 Nov 2002
|S3 Graphics Co., Ltd.
|Token-based buffer system and method for a geometry pipeline in three-dimensional graphics
|30 Aug 1999
|5 Nov 2002
|Ati International Srl
|Method and apparatus for displaying images
|27 Dec 1999
|17 Dec 2002
|Sun Microsystems, Inc.
|Graphics system configured to perform parallel sample to pixel calculation
|10 Jun 1992
|5 May 1998
|Benny Chi Wah Lau
|Graphics display system
|2 Aug 1994
|14 Nov 2001
|Philips Electronics N.V.
|Image processing
|4 Aug 2000
|5 Jan 2005
|ATI International SRL
|Method and apparatus for controlling compressed Z information in a video graphics system
|6 Jul 2000
|7 Feb 2001
|ATI International SRL
|Method and apparatus for compressing and storing image data
|1 Sep 2000
|3 Jan 2007
|ATI International SRL
|Apparatus and method for image compression
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|"5.13.1 How to Project a Texture," from web site: www.sgi.com, 2 pages.
|"ATI RADEON Skinning and Tweening," from ATI.com web site, 1 page (2000).
|"Cartoon Shading, Using Shading Mapping," 1 page, http://www.goat.com/alias/shaders.html#toonshad web site information, CartoonReyes, http://www.zentertainment.com/zentropy/review/cartoonreyes.html.
|"Computer Graphics, Principles and Practice," Second Edition, The Systems Programming Series, Foley, van Dam, Fiener, Hughes, Addison Wesley, 1990.
|"Developer Relations, ATI Summer 2000 Developer Newsletter," from ATI.com web site, 5 pages (Summer 2000).
|"Developer's Lair, Multitexturing with ATI Rage Pro," (7 pages) from ati.com web site (2000).
|"DexDrive Bridges Gap", The Tampa Tribune, Mar. 12, 1999.
|"Dreamcast: The Full Story", Next Generation, Sep. 1998.
|"First PlayStation II Gameplay Screens Revealed!", Next Generation, Sep. 1999.
|"HowTo: Animate Textures in Direct3D Immediate Mode," printed from web site support.microsoft.com, 3 pages (last reviewed Dec. 15, 2000).
|"Inside Direct3D", Microsoft Programming Series, Peter J. Kovach, Microsoft Press, 1999.
|"OpenGL Programming Guide, The Official Guide to Learning OpenGL, Release 1", Jackie Nieder, Tom David, Mason Woo, Addison-Wesley Publishing Co., 1993.
|"OpenGL Projected Textures," from web site:HTTP://reality.sgi.com, 5 pages.
|"Principles of Three-Dimensional Computer Animation", Revised Edition, Michael O'Rourke, W.W. Norton & Company, 1998.
|"Procedural Elements for Computer Graphics," Second Edition, David F. Rogers, McGraw Hill, 1998.
|"Real-Time Rendering," Tomas Molleir, Eric Haines, AK Peters, 1999.
|"Renderman Artist Tools, PhotoRealistic Renderman Tutorial," Pixar (Jan. 1996).
|"Sega To Launch Video Camera for Dreamcast", Reuters Business News, Feb. 16, 2000.
|"Skeletal Animation and Skinning," from ATI.com web site, 2 pages (Summer 2000).
|10.2 Alpha Blending, http://www.sgi.com/software/opengl/advanced98/notes/node146.html.
|10.3 Sorting, http://www.sgi.com/software/opengl/advanced98/notes/node147.html.
|10.4 Using the Alpha Function, http://www.sgi.com/software/opengl/advanced98/notes/node148.html.
|2D/3D Graphics Card User Manual, Guillemot (C)1999.
|2D/3D Graphics Card User Manual, Guillemot �1999.
|A Microprocessor With a 128b CPU, 10 Floating-Point MAC's, 4 Floating-Point Dividers, and an MPEG2 Decoder, 1999 IEEE International Solid-State Circuits Conference, Feb. 16, 1999.
|Akeley, Kurt, "Reality Engine Graphics", 1993, Silicon Graphics Computer Systems, pp. 109-116.
|Alpha (transparency) Effects, Future Technology Research Index, http://www.futuretech.vuurwerk.n1/alpha.html.
|AM News: Japanese Developers Not All Sold on PS2, Next Generation, Mar. 16, 1999.
|Arkin, Alan, email, subject: "Texture distortion problem," from web site: HTTP://reality.sgi.com (Jul. 1997).
|ATI Radeon 64 Meg DDR OEM, Aug., 19, 2000, www.hexus.net.
|Blythe, David, 5.6 Transparency Mapping and Trimming with Alpha, http://toolbox.sgi.com/TasteOfDT/d...penGL/advanced98//notes/node41.html, Jun. 11, 1998.
|Cambridge Animo—Scene III, info sheet, Cambridge Animation Systems, 2 pages, http://www.cam-ani.co.uk/casweb/products/software/SceneIII.htm.
|Chris Charla, "Play Station II: The Latest News", Next Generation, Sep. 1999.
|Chris Johnston, "PlayStation Part Deux", Press Start, (C)1999.
|Chris Johnston, "PlayStation Part Deux", Press Start, �1999.
|Computer Graphics World, Dec. 1997.
|Datasheet, SGS-Thomson Microelectronics, nVIDIA™, RIVA 128™ 128-Bit 3D Multimedia Accelerator (Oct. 1997).
|David Pescovitz, "Dream On", Wired, Aug. 1999.
|David Sheff, "Sony Smackage: Test Driving The PlayStation II", Wired, Nov. 1999.
|Debevec, Paul, et al., "Efficient View-Dependent Image-Based Rendering with Projective Texture-Mapping," University of California at Berkeley.
|Decaudin, Philippe, "Cartoon-Looking Rendering of 3D Scenes," Syntim Project Inria, 6 pages, http://www-syntim.inria.fr/syntim/recherche/decaudin/cartoon-eng.html.
|Digimation Inc., "The Incredible Comicshop," info sheet, 2 pages, http://www.digimation.com/asp/product/asp?product_id�33.
|DirectX 7.0 Programmer'Reference, Microsoft Corporation, 1995-1999 (as part of the DirectX 7.0 SDK on the Companion CD included with "Inside Direct3D", Microsoft Programming Series, Peter J. Kovach, Microsoft Press, 1999).
|Dreamcast Instruction Manual, Sega Enterprises, Ltd., (C)1998.
|Dreamcast Instruction Manual, Sega Enterprises, Ltd., �1998.
|Duke, "Dreamcast Technical Specs", Sega Dreamcast Review, Sega, Feb. 1999, www.game-revolution.com.
|Efficient Command/Data Interface Protocol For Graphics, IBM TDB, vol. 36, issue 9A, Sep. 1, 1993, pp. 307-312.
|Elber, Gershon, "Line Art Illustrations of Parametric and Implicit Forms," IEEE Transactions on Visualization and Computer Graphics, vol. 4, No. 1, Jan.-Mar. 1998.
|Feth, Bill, "Non-Photorealistic Rendering," email@example.com, CS490—Bruce Land, 5 pages (Spring 1998).
|Game Enthusiast Online Highlights, Mar. 1, 1999.
|Game Enthusiast Online Highlights, Mar. 17, 1999.
|Game Enthusiast Online Highlights, Mar. 18, 1999.
|Game Enthusiast Online Highlights, Oct. 20, 1999.
|GDC 2000: Advanced OpenGL Game Development, "A Practical and Robust Bump-mapping Technique for Today's GPUs," by Mark Kilgard, Jul. 5, 2000, www.nvidia.com.
|Gibson, Simon, et al., "Interactive Rendering with Real-World Illumination," Rendering Techniques 2000; 11th Eurographics Workshop on Rendering, pp. 365-376 (Jun. 2000).
|Gustavo Oliveira, "Refractive Texture Mappig, Part One", www.gamasutra.com, Nov., 10, 2000.
|Hachigian, Jennifer, "Super Cel Shader 1.00 Tips and Tricks," 2 pages wysiwyg://thePage.13/http://members.xoom.com/_XMCM.jarvia/3D/celshade.html.
|Haeberli, Paul et al., "Texture Mapping as a Fundamental Drawing Primitive," Proceedings of the Fourth Eurographics Workshop on Rendering, 11pages, Paris, France (Jun. 1993).
|Hart, Evan et al., "Graphics by rage," Game Developers Conference 2000, from ATI.com web site (2000).
|Hart, Evan et al., "Vertex Shading with Direct3D and OpenGL," Game Developers Conference 2001, from ATI.com web site (2001).
|Heidrich et al., "Applications of Pixel Textures in Visualization and Realistic Image Synthesis," Proceedings 1999 Symposium On Interactive 3D Graphics, pp. 127-134 (Apr. 1999).
|Hook, Brian, "An Incomplete Guide to Programming DirectDraw and Direct3D Immediate Mode (Release 0.46)," printed from web site: www.wksoftware.com, 42 pages.
|Hoppe, Hugues, "Optimization of Mesh Locality for Transparent Vertex Caching," Proceedings of Siggraph, pp. 269-276 (Aug. 8-13, 1999).
|Hourcade et al, "Algorithms for Antialiased Cast Shadows", Computers and Graphics, vol. 9, No. 3, pp. 260-265 (1985).
|Info: Rendering a Triangle Using an Execute Buffer, printed from web site support.microsoft.com, 6 pages (last reviewed Oct. 20, 2000).
|Inside Sony's Next Generation Playstation (C)1999.
|Inside Sony's Next Generation Playstation �1999.
|Introducing The Next Generation PlayStation, Sony Computer Entertainment Inc., (C)1999.
|Introducing The Next Generation PlayStation, Sony Computer Entertainment Inc., �1999.
|James F. Blinn, "Simulationof Wrinkled Surfaces," Caltech/JPX, pp. 286-292, SIGGRAPH 78 (1978).
|Jim Bushnell et al. "Advanced Multitexture Effects With Direct3D and OpenGL", Pyramid Peak Design & ATI Research, Inc., GameDevelopers Conference, (C)1999.
|Jim Bushnell et al. "Advanced Multitexture Effects With Direct3D and OpenGL", Pyramid Peak Design & ATI Research, Inc., GameDevelopers Conference, �1999.
|Joel Easley, "PlayStation II Revealed", Game Week, Sep. 29, 1999.
|John Schlag, Fast Embossing Effects on Raster Image Data, Graphics Gems IV, Edited by Paul S. Heckbert, Computer Science Department, Carnegie Mellon University, Academic Press, Inc., 1994, pp. 433-437.
|Leadtek GTS, Aug. 3, 2000, www.hexus.net.
|MacWeek.Com Gets Inside Story on Connectix VGS for Windows; Controversial Emulator of Sony PlayStation Games Cureently Available for Macs Only, Business Wire, Mar. 12, 1999.
|Markosian, Lee et al., "Real-Time Nonphotorealistic Rendering," Brown University site of the NSF Science and Technology Center for Computer Graphics and Scientific Visualization, Providence, RI, 5 pages (undated).
|Marlin Rowley, "GeForce 1 & 2 GPU Speed Tests", May 11, 2000, www.g256.com.
|Michael McCool, "Shadow Volume Reconstruction from Depth Maps", ACM Transactions on Graphics, vol. 19, No. 1, Jan. 2000, pp. 1-26.
|Microsoft Xbox-The Future of Gaming, Microsoft Xbox Performance Sheet, www.xbox.com.
|Microsoft Xbox—The Future of Gaming, Microsoft Xbox Performance Sheet, www.xbox.com.
|Mitchel et al., "Multitexturing in DirectX6", Game Developer, Sep. 1998, www.gdmag.com.
|Moller, Tomas et al., "Real-Time Rendering," pp. 179-183 (AK Peters Ltd., 1999).
|Mulligan, Vikram, Toon, info sheet, 2 pages, http://digitalcarversguild.com/products/toon/toon.thml
|Neider, Jackie et al., "OpenGI Programming Guide, The Official Guide to Learning OpenGL, Release 1," p. 204, Addison-Wesley Publishing Company (1993).
|Nikkei Shimbun, "Sony Making SME, Chemical and SPT into Wholly-Owned Subsidiaries", Mar. 9, 1999.
|Nintendo 64 Instruction Booklet, Nintendo of America, 1998.
|NVIDIA Product Overview, "GeForce2Ultra", NVIDIA Corporation, Aug. 21, 2000, www.nvidia.com.
|NVIDIA.com, technical presentation, "Advanced Pixel Shader Details" (Nov. 10, 2000).
|NVIDIA.com, technical presentation, "AGDC Per-Pixel Shading" (Nov. 15, 2000).
|NVIDIA.com, technical presentation, Introduction to DX8 Pixel Shaders (Nov. 10, 2000).
|Peercy et al., "Efficient Bump Mapping Hardware", Computer Graphics Proceedings, Annual Conference Series, 1997.
|Peter J. Kovach, Inside Direct 3D, "Alpha Testing," ppp 289-291 (1999).
|Photograph of Nintendo 64 System.
|Photograph of Sega Dreamcast System.
|Photograph of Sony Playstation II System.
|PlayStation II: Hardware Heaven or Hell?, Next Generation, Jan. 2000.
|Press Release, Mar. 18, 1999.
|Press Releases, "ATI's RADEON family of products delivers the most comprehensive support for the advance graphics features of DirectX 8.0," Canada, from ATI.com web site, 2 pages (Nov. 9, 2000).
|Product Presentation, "RIVA 128™ Leadership 3D Acceleration," 2 pages.
|Randy Nelson, "Dreamcast 101: Everything You Ever Wanted To Know About Sega's Powerful New Console", Official Sega Dreamcast Magazine, Jun. 1999.
|Raskar, Ramesh et al., "Image Precision Silhouette Edges," Symposium on Interactive 3D Graphics1999, Atlanta, 7 pages (Apr. 26-29, 1999).
|Render Man Artist Tools, Using Arbitrary Output Variables in Photorealistic Renderman (With Applications), PhotoRealistic Renderman Application Note #24, 8 pages, Jun. 1998 http://www.pixar.com/products/renderman/toolkit/Toolkit/AppNotes/appnote.24.html.
|RenderMan Artist Tools, PhotoRealistic Renderman 3.8 User's Manual, Pixar (Aug. 1998).
|RenderMan Interface Version 3.2 (Jun. 2000).
|Reynolds, Craig, "Stylized Depiction in Computer Graphics, Non-Photorealistic, Painterly and 'Toon Rendering," an annotated survey of online resources, 13 pages, last update May 30, 2000, http://www.red.com/cwr/painterly.html.
|Robert L. Cook, "Shade Trees", Computer Graphics, vol. 18, No. 3, Jul. 1984.
|Schlechtweg, Stefan et al., "Emphasising in Line-drawings," Norsk samarbeid innen grafisk databehandling: NORSIGD Info, medlemsblad for NORSIGD, Nr 1/95, pp. 9-10.
|Schlechtweg, Stefan et al., Rendering Line-Drawings with Limited Resources, Proceedings of GRAPHICON '96, 6th International Conference and Exhibition on Computer Graphics and Visualization in Russia, (St. Petersburg, Jul. 1-5, 1996) vol. 2, pp 131-137.
|Search Results for: skinning, from ATI.com web site, 5 pages (May 24, 2001).
|Segal, Mark, et al., "Fast Shadows and Lighting Effects Using Texture Mapping," Computer Graphics, 26, 2, pp. 249-252 (Jul. 1992).
|Shade, Jonathan et al., "Layered Depth Images," Computer Graphics Proceedings, Annual Conference Series, pp. 231-242 (1998).
|Singh, Karan et al., "Skinning Characters using Surface-Oriented Free-Form Deformations," Toronto Canada "Hardware Technology," from ATI.com web site, 8 pages (2000).
|Slide Presentation, S�bastien Domin�, "nVIDIA Mesh Skinning, OpenGI".
|Softimage/3D Full Support, "Toon Assistant," 1998 Avid Technology, Inc., 1 page, http://www.softimage.com/3dsupport/techn...uments/3.8/features3.8/rel_notes.56.html.
|Sony PlayStation II Instruction Manual, Sony Computer Entertainment Inc., (C)2000.
|Sony PlayStation II Instruction Manual, Sony Computer Entertainment Inc., �2000.
|Sony To Turn PlayStation Maker Into Wholly Owned Unit-Nikkei, Dow Jones News Service, Mar. 8, 1999.
|Stand and Be Judged, Next Generation, May 2000.
|Steven Levy, "Here Comes PlayStation II", Newsweek, Mar. 6, 2000.
|Technical Brief: Transform and Lighting, Nov. 10, 1999, www.nvidia.com.
|Technical Brief: What's New With Microsoft DirectX7, posted Nov. 10, 1999, www.nvidia.com.
|Technical Presentation: Computations for Hardware Lighting and Shading, Mar. 17, 2000, www.nvidia.com.
|Technical Presentation: D3D 7 Vertex Lighting, Mar. 15, 2000, www.nvidia.com.
|Technical Presentation: DirectX 7 and Texture Management, Nov. 12, 1999 www.nvidia.com.
|Technical Presentation: Dot Product Lighting, Nov. 12, 1999, www.nvidia.com.
|Technical Presentation: Emboss Bump Mapping, Nov. 3, 1999, www.nvidia.com.
|Technical Presentation: GeForce 256 and RIVA TNT Combiners, Dec. 8, 1999, www.nvidia.com.
|Technical Presentation: GeForce 256 Overview, Nov. 12, 1999, www.nvidia.com.
|Technical Presentation: GeForce 256 Register Combiners, Mar. 17, 2000,www.nvidia.com.
|Technical Presentation: Guard Band Clipping, Nov. 3, 1999, www.nvidia.com.
|Technical Presentation: Hardware Accelerated Anisotropic Lighting, Nov. 3, 1999 www.nvidia.com.
|Technical Presentation: Hardware Bump-mapping Choices and Concepts, Jun. 7, 2000, www.nvidia.com.
|Technical Presentation: Hardware Transform and Lighting, Nov. 12, 1999, www.nvidia.com.
|Technical Presentation: Hardware Transform and Lighting, www.nvidia.com, posted Jun. 12, 2000.
|Technical Presentation: How to Bump Map a Skinned Polygonal Model, Jun. 7, 2000, www.nvidia.com.
|Technical Presentation: Multitexture Combiners, Nov. 3, 1999, www.nvidia.com.
|Technical Presentation: Per-Pixel Lighting (by S. Dietrich) Mar. 14, 2000 www.nvidia.com.
|Technical Presentation: Phong Shading and Lightmaps, Nov. 3, 1999, www.nvidia.com.
|Technical Presentation: Practical Bump-mapping for Today's GPUs, Mar. 17, 2000 www.nvidia.com.
|Technical Presentation: Shadows, Transparency, & Fog, Mar. 17, 2000 www.nvidia.com.
|Technical Presentation: TexGen & The Texture Matrix, Mar. 15, 2000 www.nvidia.com.
|Technical Presentation: Texture Coordinate Generation, Nov. 3, 1999, www.nvidia.com.
|Technical Presentation: The ARB_multitexture Extension, Nov. 3, 1999 www.nvidia.com.
|Technical Presentation: Toon Shading, Mar. 15, 2000, www.nvidia.com.
|Technical Presentation: Vertex Blending, Nov. 12, 1999, www.nvidia.com.
|Technical Presentation: Vertex Buffers, posted Jun. 12, 2000, www.nvidia.com.
|Technical Presentation: Vertex Cache Optimization, Nov. 12, 1999, www.nvidia.com.
|Technical Presentations: "Texture Space Bump Mapping," Sim Dietrich, Nov. 10, 2000 www.nvidia.com.
|The RenderMan Interface Version 3.1, (Sep. 1989).
|The RenderMan Interface, Stephen R. Keith, Version 3.1, Pixar Animation Studios, Sep. 1989.
|The RenderMan Interface, Version 3.2, Pixar Animation Studios, Jul. 2000, www.pixar.com.
|Thompson, Nigel, "Rendering with Immediate Mode," Microsoft Interactive Developer Column: Fun and Games, printed from web site msdn.microsoft.com, 8 pages (Mar. 97).
|Thompson, Tom, "Must-See 3-D Engines," Byte Magazine, printed from web site www.byte.com, 10 pages (Jun. 1996).
|Tomas M�ller and Eric Haines "Real-Time Rendering", AK Peters, Ltd., (C)1999, pp. 127-142.
|Tomas M�ller and Eric Haines "Real-Time Rendering", AK Peters, Ltd., �1999, pp. 127-142.
|Toony Shaders, "Dang I'm tired of photorealism," 4 pages, http://www.visi.com/˜mcdonald/toony.html.
|U.S. patent application Ser. No. 09/337,293, filed Jun. 21, 1999, Multi-Format Vertex Data Processing Apparatus and Method [issued as U.S. Pat. No. 6,501,479 B1 on Dec. 31, 2002.].
|Videum Conference Pro (PCI) Spcification, product of Winnov (Winnov), published Jul. 21, 1999.
|VIDI Presenter 3D Repository, "Shaders." 2 pages, http://www.webnation.com/vidirep/panels/renderman/shaders/toon.phtml.
|VisionTek, "GeForce3 GS Graphics Processing Unit", (C)2000 www.visiontek.com.
|VisionTek, "GeForce3 GS Graphics Processing Unit", �2000 www.visiontek.com.
|Voodoo 5 500 Review, Jul. 26, 2000, www.hexus.net.
|Wang et al., "Second-Depth Shadow Mapping", Department of Computer Science, Univ. N.C, Chapel Hill, N.C. pp. 1-7.
|Web site information, CartoonReyes, REM Infografica, http://www.digimotion.co.uk/cartoonreyes.htm.
|Web site materials, "Renderman Artist Tools, PhotoRealsitic RenderMan 3.8 User's Manual," Pixar.
|White paper, Dietrich, Sim, "Cartoon Rendering and Advanced Texture Features of the GeForce 256 Texture Matrix, Projective Textures, Cube Maps, Texture Coordinate Generation and DOTPRODUCT3 Texture Blending" (Dec. 16, 1999).
|White paper, Huddy, Richard, "The Efficient Use of Vertex Buffers," (Nov. 1, 2000).
|White paper, Kilgard, Mark J., "Improving Shadows and Reflections via the Stencil Buffer" (Nov. 3, 1999).
|White paper, Rogers, Douglas H., "Optimizing Direct3D for the GeForce 256" (Jan. 3, 2000).
|White paper, Spitzer, John, et al., "Using GL_NV_array_range and GL_NV_Fence on GEForce Products and Beyond" (Aug. 1, 2000).
|Whitepaper: "Z Buffering, Interpolation and More W-Buffering", Doug Rogers, Jan. 31, 2000, www.nvidia.com.
|Whitepaper: 3D Graphics Demystified, Nov. 11, 1999, www.nvidia.com.
|Whitepaper: Anisotropic Texture Filtering in OpenGL, posted Jul. 17, 2000, www.nvidia.com.
|Whitepaper: Color Key in D3D, posted Jan. 11, 2000, www.nvidia.com.
|Whitepaper: Cube Environment Mapping, posted Jan. 14, 2000, www.nvidia.com.
|Whitepaper: Dot Product Texture Blending, Dec. 3, 1999, www.nvidia.com.
|Whitepaper: Guard Band Clipping, posted Jan. 31, 2000, www.nvidia.com.
|Whitepaper: Implementing Fog in Direct3D, Jan. 3, 2000, www.nvidia.com.
|Whitepaper: Mapping Texels to Pixels in D3D, posted Apr. 5, 2000, www.nvidia.com.
|Whitepaper: Optimizing Direct3D for the GeForce 256, Jan. 3, 2000, www.nvidia.com.
|Whitepaper: Technical Brief: AGP 4X with Fast Writes, Nov. 10, 1999, www.nvidia.com.
|Whitepaper: Using GL_NV_vertex_array and GL_NV_fence, posted Aug. 1, 2000, www.nvidia.com.
|Whitepaper: Vertex Blending Under DX7 for the GeForce 256, Jan. 5, 2000, www.nvidia.com.
|Whitepapers: "Texture Addressing," Sim Dietrich, Jan. 6, 2000, www.nvidia.com.
|Williams, Lance, "Casting Curved Shadows on Curved Surfaces," Computer Graphics (SIGGRAPH '78 Proceedings), vol. 12, No. 3, pp. 270-274 (Aug. 1978).
|Winner, Stephanie, et al., "Hardware Accelerated Rendering Of Antialiasing Using A Modified A-buffer Algorithm," Computer Graphics Proceedings, Annual Conference Series, 1997, pp 307-316.
|Woo et al., "A Survey of Shadow Algorithms," IEEE Computer Graphics and Applications, vol. 10, No. 6, pp. 13-32 (Nov. 1990).
|Yumiko Ono, Sony Antes Up Its Chips In Bet On New Game System, Dow Jones News Service, Mar. 4, 1999.
|ZDNet Reviews, from PC Magazine, "Other Enhancements," Jan. 15, 1999, wysiwyg://16/http://www4.zdnet.com...ies/reviews/0,4161,2188286,00.html.
|ZDNet Reviews, from PC Magazine, "Screen Shot of Alpha-channel Transparency," Jan. 15, 1999, wysiwyg://16/http://www4.zdnet.com...ies/reviews/0,4161,2188286,00.html.
|Zeleznik, Robert et al."SKETCH: An Interface for Sketching 3D Scenes," Computer Graphics Proceedings, Annual Conference Series 1996, pp. 163-170.
|Citing Patent
|Filing date
|Publication date
|26 Feb 2002
|21 Dec 2004
|Sun Microsystems, Inc.
|Synchronizing data streams in a graphics processor
|8 Mar 2002
|8 Mar 2005
|Sun Microsystems, Inc.
|Graphics data synchronization with multiple data paths in a graphics accelerator
|31 Jan 2002
|5 Apr 2005
|Sony Corporation Entertainment Inc.
|Image generation method and device used thereof
|12 Nov 2003
|8 Aug 2006
|Microsoft Corporation
|Methods and systems for rendering computer graphics
|23 Dec 2004
|5 Jun 2007
|Apple Inc.
|Manipulating text and graphic appearance
|16 Apr 2004
|12 Jun 2007
|Apple Computer, Inc.
|System for reducing the number of programs necessary to render an image
|11 Jun 2004
|24 Jul 2007
|Apple Inc.
|System and method for processing graphics operations with graphics processing unit
|24 Dec 2002
|11 Sep 2007
|Intel Corporation
|Z-buffering techniques for graphics rendering
|24 Jun 2004
|8 Jul 2008
|Apple Inc.
|Gaussian blur approximation suitable for GPU
|12 Oct 2005
|19 Aug 2008
|Microsoft Corporation
|Methods and systems for rendering computer graphics
|25 Jun 2004
|10 Feb 2009
|Apple Inc.
|Layer for accessing user interface elements
|7 Mar 2006
|10 Mar 2009
|Apple Inc.
|Remote access to layer and user interface elements
|7 Mar 2006
|5 May 2009
|Apple Inc.
|User interface element with auxiliary function
|3 Jun 2005
|9 Jun 2009
|Apple Inc.
|Widget authoring and editing environment
|4 Nov 2005
|18 Aug 2009
|Microsoft Corporation
|Methods and systems for rendering computer graphics
|12 May 2006
|27 Oct 2009
|Nvidia Corporation
|Pixel load instruction for a programmable graphics processor
|4 Apr 2007
|3 Nov 2009
|Apple Inc.
|System for reducing the number of programs necessary to render an image
|16 Apr 2004
|22 Dec 2009
|Apple Inc.
|Blur computation algorithm
|1 Oct 2004
|26 Jan 2010
|Apple Inc.
|Partial display updates in a windowing system using a programmable graphics processing unit
|4 Apr 2007
|23 Feb 2010
|Apple Inc.
|System and method for processing graphics operations with graphics processing unit
|30 May 2003
|16 Mar 2010
|Adobe Systems Incorporated
|Embedded reuse meta information
|28 Feb 2007
|13 Apr 2010
|Nvidia Corporation
|System, method and article of manufacture for a programmable processing model with instruction set
|5 May 2006
|27 Apr 2010
|Apple Inc.
|Management of user interface elements in a display environment
|10 May 2006
|22 Jun 2010
|Apple Inc.
|Widget security
|10 May 2006
|6 Jul 2010
|Apple Inc.
|Workflow widgets
|19 Nov 2007
|13 Jul 2010
|Nvidia Corporation
|System, method and article of manufacture for a programmable processing model with instruction set
|23 Jun 2005
|20 Jul 2010
|Apple Inc.
|Unified interest layer for user interface
|15 Dec 2005
|31 Aug 2010
|Apple Inc.
|System for reducing the number of programs necessary to render an image
|14 Jan 2009
|7 Sep 2010
|Apple Inc.
|User interface element with auxiliary function
|7 Mar 2006
|7 Sep 2010
|Apple Inc.
|Unified interest layer for user interface
|16 Apr 2004
|7 Dec 2010
|Apple Inc.
|System for emulating graphics operations
|18 Jan 2011
|Apple Inc.
|Configuration bar for lauching layer for accessing user interface elements
|4 Apr 2007
|15 Mar 2011
|Apple Inc.
|Resolution independent user interface design
|15 Dec 2005
|22 Mar 2011
|Apple Inc.
|System for reducing the number of programs necessary to render an image
|1 Feb 2006
|31 May 2011
|Apple Inc.
|Multiple dashboards
|4 Apr 2007
|28 Jun 2011
|Apple Inc.
|Partial display updates in a windowing system using a programmable graphics processing unit
|19 Jul 2011
|Apple Inc.
|Web view layer for accessing user interface elements
|11 Mar 2003
|2 Aug 2011
|Broadcom Corporation
|Multi-pass system and method supporting multiple streams of video
|5 Apr 2011
|30 Aug 2011
|Apple Inc.
|System and method for processing graphics operations with graphics processing unit
|31 Mar 2009
|13 Sep 2011
|Apple Inc.
|Optimizing the execution of media processing routines using a list of routine identifiers
|14 Dec 2005
|20 Sep 2011
|Canon Kabushiki Kaisha
|Apparatus and method for processing data
|15 Oct 2010
|18 Oct 2011
|Apple Inc.
|System for emulating graphics operations
|15 Oct 2010
|18 Oct 2011
|Apple Inc.
|System for emulating graphics operations
|15 Oct 2010
|25 Oct 2011
|Apple Inc.
|System for emulating graphics operations
|24 Jun 2004
|29 Nov 2011
|Apple Inc.
|User-interface design
|29 Dec 2004
|6 Dec 2011
|Intel Corporation
|Efficient Z testing
|4 Nov 2004
|20 Dec 2011
|Qualcomm Incorporated
|Depth buffer for rasterization pipeline
|21 Mar 2005
|3 Jan 2012
|Qualcomm Incorporated
|Tiled prefetched and cached depth buffer
|22 May 2009
|17 Jan 2012
|Nintendo Co., Ltd.
|Graphics processing system with enhanced memory controller
|4 Apr 2007
|6 Mar 2012
|Apple Inc.
|User-interface design
|21 Jul 2006
|6 Mar 2012
|Apple Inc.
|Resolution independent user interface design
|16 Apr 2004
|13 Mar 2012
|Apple Inc.
|System for optimizing graphics operations
|27 Dec 2005
|20 Mar 2012
|Apple Inc.
|Slide show navigation
|19 May 2011
|27 Mar 2012
|Apple Inc.
|Partial display updates in a windowing system using a programmable graphics processing unit
|27 Aug 2007
|10 Apr 2012
|Adobe Systems Incorporated
|Reusing components in a running application
|6 Dec 2007
|8 May 2012
|Adobe Systems Incorporated
|System and method for generating an application fragment
|1 Nov 2007
|24 Jul 2012
|Nvidia Corporation
|Early Z testing for multiple render targets
|1 Nov 2007
|31 Jul 2012
|Nvidia Corporation
|Z-test result reconciliation with multiple partitions
|2 Jun 2005
|7 Aug 2012
|Apple Inc.
|Procedurally expressing graphic objects for web pages
|1 Nov 2007
|14 Aug 2012
|Nvidia Corporation
|Late Z testing for multiple render targets
|10 Aug 2011
|14 Aug 2012
|Canon Kabushiki Kaisha
|Apparatus and method for processing data
|9 Dec 2002
|4 Sep 2012
|Broadcom Corporation
|System and method for processing data using a network
|19 Nov 2007
|4 Sep 2012
|Nvidia Corporation
|System, method and article of manufacture for a programmable processing model with instruction set
|19 Nov 2007
|11 Sep 2012
|Nvidia Corporation
|System, method and article of manufacture for a programmable processing model with instruction set
|11 Sep 2012
|Apple Inc.
|Remote access to layer and user interface elements
|8 Sep 2003
|18 Sep 2012
|Nvidia Corporation
|System, method and computer program product for updating a far clipping plane in association with a hierarchical depth buffer
|23 Dec 2008
|16 Oct 2012
|Apple Inc.
|Layer for accessing user interface elements
|26 Jun 2009
|30 Oct 2012
|Apple Inc.
|Widget authoring and editing environment
|14 May 2004
|2 Apr 2013
|Nvidia Corporation
|Method and system for computing pixel parameters
|14 May 2004
|9 Apr 2013
|Nvidia Corporation
|Method and system for interpolating level-of-detail in graphics processors
|14 May 2004
|30 Apr 2013
|Nvidia Corporation
|Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline
|7 Aug 2007
|14 May 2013
|Nvidia Corporation
|Interpolation of vertex attributes in a graphics processor
|11 Feb 2011
|21 May 2013
|Apple Inc.
|System for optimizing graphics operations
|7 Jun 2005
|28 May 2013
|Apple Inc.
|Preview and installation of user interface elements in a display environment
|20 Jan 2012
|13 Aug 2013
|Apple Inc.
|User-interface design
|11 Feb 2008
|13 Aug 2013
|Apple Inc.
|Optimization of image processing using multiple processing units
|13 Jul 2011
|27 Aug 2013
|Apple Inc.
|System and method for processing graphics operations with graphics processing unit
|2 Nov 2006
|17 Sep 2013
|Nvidia Corporation
|Method and system for deferred coverage mask generation in a raster stage
|20 Apr 2006
|24 Sep 2013
|Apple Inc.
|Safe distribution and use of content
|16 Nov 2005
|24 Sep 2013
|Apple Inc.
|Preview including theme based installation of user interface elements in a display environment
|4 Aug 2006
|22 Oct 2013
|Apple Inc.
|Synchronization of widgets and dashboards
|7 Aug 2012
|12 Nov 2013
|Broadcom Corporation
|System and method for configuring a display pipeline using a network
|30 Nov 2011
|26 Nov 2013
|Kabushiki Kaisha Toshiba
|Video display apparatus for shortened-delay processing of a video signal and video processing method
|3 Mar 2010
|17 Dec 2013
|Canon Kabushiki Kaisha
|Information processing apparatus, process control method, and program for scheduling a plurality of processes arranged in a recognizable manner
|14 Jun 2006
|4 Feb 2014
|Qualcomm Incorporated
|Convolution filtering in a graphics processor
|29 Jul 2008
|18 Feb 2014
|Adobe Systems Incorporated
|Configuring mobile devices
|6 Aug 2007
|4 Mar 2014
|Apple Inc.
|Web widgets
|21 Jan 2013
|25 Mar 2014
|Broadcom Corporation
|Multi-pass system and method supporting multiple streams of video
|14 May 2004
|1 Apr 2014
|Nvidia Corporation
|Arbitrary size texture palettes for use in graphics systems
|16 Apr 2004
|22 Apr 2014
|Apple Inc.
|High-level program interface for graphics operations
|14 May 2004
|29 Apr 2014
|Nvidia Corporation
|Early kill removal graphics processing system and method
|4 Sep 2009
|6 May 2014
|Samsung Techwin Co., Ltd.
|Image processing apparatus
|14 May 2004
|27 May 2014
|Nvidia Corporation
|Kill bit graphics processing system and method
|11 Nov 2013
|27 May 2014
|Broadcom Corporation
|System and method for configuring a display pipeline
|14 May 2004
|27 May 2014
|Nvidia Corporation
|Single thread graphics processing system and method
|14 May 2004
|3 Jun 2014
|Nvidia Corporation
|Unified data fetch graphics processing system and method
|6 Jul 2006
|10 Jun 2014
|Nvidia Corporation
|Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
|26 Apr 2006
|1 Jul 2014
|Qualcomm Incorporated
|Graphics system with configurable caches
|21 Jun 2006
|1 Jul 2014
|Qualcomm Incorporated
|Unified virtual addressed register file
|3 Apr 2008
|2 Sep 2014
|Panasonic Corporation
|Image generating apparatus and image generating method for generating images by rendering a polygon
|17 Dec 2007
|14 Oct 2014
|Nvidia Corporation
|Early Z scoreboard tracking system and method
|4 Aug 2006
|21 Oct 2014
|Apple Inc.
|Management and generation of dashboards
|31 May 2006
|21 Oct 2014
|Qualcomm Incorporated
|Multi-threaded processor with deferred thread output control
|25 May 2006
|11 Nov 2014
|Qualcomm Incorporated
|Graphics processor with arithmetic and elementary function units
|4 Sep 2007
|11 Nov 2014
|Apple Inc.
|Dynamically reconfigurable graphics layer system and method
|14 Dec 2007
|10 Feb 2015
|Apple Inc.
|User-centric widgets and dashboards
|24 Jun 2011
|3 Mar 2015
|Nvidia Corporation
|Bounding box-based techniques for improved sample test efficiency in image rendering
|7 May 2010
|12 May 2015
|Apple Inc.
|Widget security
|12 Apr 2006
|11 Aug 2015
|Apple Inc.
|Linked widgets
|24 Jun 2011
|22 Sep 2015
|Nvidia Corporation
|System and method for improved sample test efficiency in image rendering
|24 Jun 2011
|29 Sep 2015
|Nvidia Corporation
|Bounding plane-based techniques for improved sample test efficiency in image rendering
|9 Dec 2002
|22 Apr 2004
|Patrick Law
|Network environment for video processing modules
|11 Mar 2003
|22 Apr 2004
|Patrick Law
|Multi-pass system and method supporting multiple streams of video
|24 Dec 2002
|24 Jun 2004
|Piazza Thomas A.
|Z-buffering techniques for graphics rendering
|23 Sep 2004
|8 Sep 2005
|Anderson Michael H.
|Graphics pipeline and method having early depth detection
|4 Nov 2004
|8 Sep 2005
|Anderson Michael H.
|Depth buffer for rasterization pipeline
|16 Apr 2004
|20 Oct 2005
|John Harper
|System for optimizing graphics operations
|11 Jun 2004
|20 Oct 2005
|Apple Computer, Inc.
|System and method for processing graphics operations with graphics processing unit
|16 Apr 2004
|20 Oct 2005
|John Harper
|System for reducing the number of programs necessary to render an image
|16 Apr 2004
|20 Oct 2005
|Mark Zimmer
|Blur computation algorithm
|16 Apr 2004
|20 Oct 2005
|John Harper
|System for emulating graphics operations
|14 May 2004
|22 Dec 2005
|Hutchins Edward A
|Kill bit graphics processing system and method
|25 Jun 2004
|29 Dec 2005
|Apple Computer, Inc.
|Display-wide visual effects for a windowing system using a programmable graphics processing unit
|1 Oct 2004
|29 Dec 2005
|Apple Computer, Inc.
|Partial display updates in a windowing system using a programmable graphics processing unit
|24 Jun 2004
|29 Dec 2005
|Apple Computer, Inc.
|User-interface design
|24 Jun 2004
|29 Dec 2005
|Apple Computer, Inc.
|Gaussian blur approximation suitable for GPU
|14 May 2004
|12 Jan 2006
|Hutchins Edward A
|Coincident graphics pixel scoreboard tracking system and method
|15 Dec 2005
|15 Jun 2006
|John Harper
|System for reducing the number of programs necessary to render an image
|15 Dec 2005
|15 Jun 2006
|John Harper
|System for reducing the number of programs necessary to render an image
|14 Dec 2005
|22 Jun 2006
|Canon Kabushiki Kaisha
|Apparatus and method for processing data
|29 Dec 2004
|29 Jun 2006
|Intel Corporation
|Efficient Z testing
|23 Dec 2004
|29 Jun 2006
|Apple Computer, Inc.
|Manipulating text and graphic appearance
|14 Mar 2005
|14 Sep 2006
|Kirchner Peter D
|Real-time rendering of embedded transparent geometry in volumes on commodity graphics processing units
|21 Mar 2005
|21 Sep 2006
|Anderson Michael H
|Tiled prefetched and cached depth buffer
|6 Jul 2006
|30 Nov 2006
|Nvidia Corporation
|Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
|21 Jul 2006
|21 Dec 2006
|Apple Computer, Inc.
|Resolution Independent User Interface Design
|4 Sep 2007
|5 Mar 2009
|Apple Inc.
|Dynamically reconfigurable graphics layer system and method
|4 Mar 2010
|Samsung Techwin Co., Ltd.
|Image processing apparatus
|3 Mar 2010
|24 Jun 2010
|Canon Kabushiki Kaisha
|Information processing apparatus, process control method, and program thereof
|30 Nov 2011
|6 Sep 2012
|Kenichi Horikoshi
|Video display apparatus and video processing method
|7 Aug 2012
|7 Feb 2013
|Broadcom Corporation
|System and Method for Processing Data Using a Network
|15 Feb 2008
|10 Jul 2013
|Efficient 2-d and 3-d graphics processing
|13 May 2005
|11 Apr 2007
|MAIWALD, Walter
|Graphics processing system and method
|U.S. Classification
|345/422, 345/582, 345/532, 345/421, 345/536, 345/502, 345/506
|International Classification
|Cooperative Classification
|European Classification
|9 May 2001
Owner name: NINTENDO CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEATHER, MARK M.;FOULADI, FARHAD;REEL/FRAME:011787/0299;SIGNING DATES FROM 20010213 TO 20010216
|20 Mar 2007
|Fee payment
Year of fee payment: 4
|23 Mar 2011
|Fee payment
Year of fee payment: 8
|8 Apr 2015
|Fee payment
Year of fee payment: 12