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Parkway by the Lake Banquets
For many years we have provided the best in wedding receptions at an affordable price. We take great pride in offering the best in service, the most picturesque setting for ceremony and reception, a huge dance floor and food to rave about for months after the event.
Around the Corner Candy
Old-fashioned neighborhood candy store.
CITY:West Dundee
Fox and Hound Arlington Heights
Neighborhood sports bar featuring 28 big screen TVs, billiards, darts, ping pong, video gaming, and late night entertainment. Private party space available! Full menu till close! Best party in town 7 days a week!
CITY:Arlington Heights
Morning Glory Bed & Breakfast
Located in the quite farm country on the outskirts of Harvard enjoy a quite night stay close to apple orchards, farm markets, golfing, and the annual Harvard Milk Days celebration.
Twilight Shuffle 5K Run
Run through the historic neighborhoods of the east side of Libertyville. Professional timing. Families are encouraged (no children under 9) to run. After finishing the course, all participants are invited to join their fellow racers for a fabulous post-race party (including light dinner and non-alcoholic drinks for all registered participants) at the new Mickey Finn's Brewery. No registrations will be accepted or processed after 12pm on race day.
USML Conference Center
Situated on 900 acres of wooded land, the Conference Center at the University of St. Mary provides meeting space for groups from 3 to 300.
Exel Inn - Prospect Heights
123 clean and comfortable rooms at affordable rates. King beds, continental breakfast. 10% senior citizen discount. Kids 17 and under stay free with adult.
CITY:Prospect Heights
Doyles Irish Pub and Eatery
Full service Family Friendly Pub style restaurant. Steaks, pasta, hand-packed burgers, fresh salads, kids menu, home-made soup, chili, apple pie, sauces and pizza. Full bar with over 40 imported beers.
R & V Italian Market & Deli
Italian Market & Deli serving authentic homemade Italian recipes daily. The full deli offers sandwiches, salads, soups, pizza, fresh bread, and an Italian bakery. Also enjoy shopping the specialty grocery store's olive oils, pesto, gift baskets and many Italian favorites.
CITY:Lake Forest
Dolce Italian Caffe and Bakery
Dolce is a unique experience that our customers love. We are a full service restaurant as well as a bakery! Stop in for our delicious dishes or our variety of fresh desserts. Our family recipes comes straight from Italy. These recipes have passed from generations of cooks and we are proud to bring them to you!
CITY:Arlington Heights
Days Inn - Barrington Chicago Northwest
Newly renovated, value-driven rates, weekly rates, business class rooms.
Solid Brass Fine Antiques
A complete line of fine antiques, lighting, furniture, military, tools, linen, china, silver and dolls.
Salutos Pizza & Pasta
Salutos, a favorite Italian restaurant in Gurnee draws residents from various local communities. Owners Bob and Melody Bode recently renovated and enlarged Salutos to better accommodate patrons. The restaurant features a two-story bar, a large dining room.
Holiday Inn Express Hotel & Suites - Waukegan
Super 8 Hotel - Mundelein
A "Pride of Super 8" motel featuring clean and friendly accommodations.
Cobblestone's on the Square
The place to visit for a charming shop offering a wide selection of furniture, home furnishings, gifts, candy, and more!
Candlewood Suites Chicago – Hoffman Estates
All suite hotel with 24 hour convenience pantry and laundry facilities. Pet friendly Hotel.
CITY:Hoffman Estates
The Vine Martini & Wine Bar
The Vine first started out as a small tapas bar and within two years had expanded their bar and restaurant into a full operation that continues to focus on using fresh and local ingredients and features over 75 cocktails. Everything, from food to drinks, is made in-house and prepared to order. We hope you enjoy your time at The Vine as much as we enjoy having you here.
Carlos & Carlos
In the heart of Arlington Heights down town, is an elegant French Italian Bistro, limited sitting (70 guests) offering the best of Italy and France, and featuring a Chef's Table to experience special gourmet menus. Our whole mission is to give you the best experiences, whether you enjoy a light dinner or an elaborate one let us assure you that all of us at Carlos & Carlos will do what it takes to see you and your guests enjoy.
CITY:Arlington Heights
Donahue Furniture
Family owned -- fine furniture. 53 years of business
David's Bistro
David's Bistro in Antioch serves contemporary American cuisine in a casual bistro environment. Visitors will find plenty to choose from steaks, salads, pizza and pasta to a kids menu and desserts including Creme Brulee, Chocolate Oooooze Cake, White Chocolate Mousse Tower and more. The Bistro Bar is a great place to relax with a good cocktail before dinner. David's Bistro also offers catering services and cooking classes.
Super 8 Prospect Heights/Northbrook
Hotel guests will enjoy a continental breakfast, large-vehicle parking and free WiFi Internet. On-site fitness center and laundry facilities. This hotel has 120 rooms and is conveniently locatedoff Interstate 294 and adjacent to the Chicago Executive Airport
CITY:Prospect Heights
Candlewood Suites
Candlewood Suites is carefully designed with spacious rooms, queen size beds, full kitchens and business desk with executive chair. Among all amenities included in the rate are fitness center, laundry facility, local calls, high speed internet and more.
Savanna House Restaurant
Savanna House takes its name from the lush green forest preserve it is located in front of, in the beautiful town of Wadsworth, Illinois. Our restaurant promotes an eco-friendly environment, and has recently undergone a massive remodeling to better serve our customers. Take a look at our decadent menu and wide selection of drinks and daily specials including fish fry on Fridays and prime rib on Saturdays.
Holiday Inn Express and Suites
Start your day off right with our new Express Start Breakfast featuring the world's best cinnamon roll.
Asian Bistro
Asian bistro has a modern, contemporary environment, fusion presentation of entrees and authentic in taste. Specializing in SzeChuan and Mandarin Cuisine as well as some popular Thai entrees and Vietnamese noodle soups.
CITY:Arlington Heights
Copper Fiddle Distillery
They are a local craft distilling business that sources grains from the Midwest and distilling equipment proudly made in the USA. All of their spirit products are handmade, grain to bottle, at their Lake Zurich location.
CITY:Lake Zurich
El Niagara Mexican Restaurant
Authentic Mexican restaurant. Daily lunch specials and children's menu. Reservations recommended for groups of 5 or more.
Holiday Inn Rolling Meadows-Schaumburg
Complimentary shuttle within 5 miles, complimentary high-speed wireless Internet throughout, indoor Polynesian atrium with tropical gardens and waterfalls, 2 indoor pools, 2 Jacuzzi's, tiki bar, basketball court, volleyball court and arcade area.
CITY:Rolling Meadows
Round Lake Park District
Round Lake Area Park District offers visitors a wide range of activities and facilities to enjoy. They include the Renwood Golf Course, the new sports center, the Prairie Grass Nature Museum, community theatre, outdoor pool/aquatic center, fitness center, child development center, teen center, senior center and acres of picturesque parklands. Private parties/outings at any of the facilities can be accommodated.
CITY:Round Lake
Super 8 Motel - Mundelein
Bangkok Cafe
Serving authentic, home style Thai Cuisine to Chicago's Northwest Suburbs since 1994. We offer traditional flavors that delight your taste buds and warm your soul. Fresh from our kitchen to your table.
CITY:Arlington Heights
Wingate Inn by Wyndham
Offering 108 rooms and suites, coffeemaker, iron & board, 2-line cordless phone with dataport conference call and voicemail. Enjoy the fitness center, whirlpool and breakfast bar.
CITY:Prospect Heights
Heritage Inn & Suites - Harvard
Fitness center, indoor pool, sauna/spa, meeting facility. Complimentary breakfast.
Lippold Park Family Golf Center
The mini putt courses have been designed with separate themes, including the handicapped accessible Sports-N-Courts with a sports theme, and Tees-N-Trees with a prairie theme.
CITY:Crystal Lake
Holiday Inn Gurnee Convention Center
This Gurnee's Premier Destination for both leisure and business serving all of Gurnee, Waukegan & Libertyville when it comes to hotel accommodations and banquet facilities. Six Flags Great America is a two minute drive and Great Lakes Naval Training Center is conveniently located 7 miles from the hotel. Travelers enjoy the convenience of Chicago's O'Hare International Airport (ORD) & Milwaukee's General Mitchell Airport (MKE) easy accessibility to the hotel. "Kids Eat Free" is a great value when you stay and the indoor swimming facility features the area's largest pool, fitness room and a full buffet breakfast. The lounge is a favorite among guests serving an array of hospitality & relaxation. Guests enjoy a selection of golf courses and leisure activities minutes away, complimentary wireless Internet, premium movie channels and a free shuttle.
Hanan Hall Romantica Boutique
Original fashion jewelry designs from romantic to Renaissance. Special occasion, wedding and prom, are our specialty.
CITY:West Dundee
Saddle Ridge Restaurant & Banquets
A full service restaurant offering breakfast, lunch, dinner, including steaks, chops, Italian dishes, prime rib, daily specials and the best Sunday Brunch in Lake County. Also offering a Friday Night Fish Fry and Thursday Night Southern Style Catfish Fiddlers. An ideal place for business meetings, conferences, or family get-togethers that is sure to please everyone! The outstanding ballroom has been accommodating brides, private parties, corporate and business people for over 25 years.
Clementi's Pizzeria and Bar
A neighborhood Italian ristorante just steps from Arlington Park. Clementi's strives to serve the freshest dishes in a relaxed setting at an affordable price. A true family-owned and operated restaurant, our wish to you is that you should be treated as one of our own.
CITY:Arlington Heights
McGonigal's Pub
A traditional Irish Pub setting with a warm, fun and inviting atmosphere. We have twenty beers on tap and have been repeatedly told by customers that our Guinness pint is nothing short of outstanding. The menu has a nice variety of options and features delicious Irish fare, fish and chips, shepherd's pie and boxtys are some of our top sellers, plus we easily have the best burger in the region!
Super 8 Motel - Woodstock
Motel with 62 rooms. Standard rooms, presidential suites and jacuzzi theme suites.
Celtic Home and Hearth
Celtic Home & Hearth offers unique selections of Celtic and Renaissance inspired and imported items all specially chosen for their quality and appeal.
Chef Ping
Chef Ping recreates the unique moderrn Chinese and Asian flavors with the balances use of fresh herbs and spices. Simply delicious, healthy, and refreshing! Remember at Chef Ping, the goal is to eat, relax, and enjoy happily together!
CITY:Rolling Meadows
Super 8 Motel - McHenry
Conveniently located with clean, comfortable rooms, friendly, courteous staff and affordable rates. Private hot tub rooms available. Children 12 and under are free.
Candlewood Suites - Libertyville
Big and built for comfort these comfortable studio and one bedroom suites feature a full kitchen complete with microwave, stove and full size refrigerator. Work efficiently at the oversized executive desk with two separate phone lines and complimentary high-speed Internet. Relax in the over stuffed recliner while enjoying the CD player and VCR. Borrow a favorite from the free video and CD library or work off some stress in the fitness center. Visit the convenient store, Candlewood Cupboard, where meals and snacks can be purchased. On-site laundry facilities are also available.
The Village Squire - West Dundee
This English pub-style casual dining restaurant has been part of the Fox Valley since 1974. Family owned and operated featuring nightly live music and a unique atmosphere.
CITY:West Dundee
Armand's Pizzeria is a family owned business that has been delivering some of Chicago's best thin crust pizza since 1956. Besides pizza, Armand's also offers a variety of other signature dishes.
CITY:Arlington Heights
Residence Inn by Marriott, Chicago Waukegan/Gurnee
This home away from home offers suites with 50% more space than ordinary hotel rooms. These versatile suites offer separate living, dining and sleeping areas, fully equipped kitchens and a comfortable work area including free high-speed Internet, desk-level outlet and voice mail. Free buffet breakfast and a free dinner social Monday-Thursday offered to all guests. Work out in the on-site fitness center or attend a meeting in the 644 sq ft. meeting room. Close to the Great Lakes Navy Base, Six Flags Great America, Gurnee Mills and a variety of shops and restaurants.
Comfort Inn - Waukegan
This hotel is conveniently located just minutes from the Naval Station Great Lakes, Six Flags Great America, Chicago Botanic Gardens, Gurnee Mills outlet mall and Lake Michigan. This hotel offers many fine features and amenities, including free deluxe continental breakfast, free coffee, and free wireless high-speed Internet access. The surrounding area boasts a variety of entertainment venues, restaurants and cocktail lounges. Business travelers will welcome additional conveniences like the public computer with Internet access, in-room desks, and access to copy and fax services.
Bill's Pub North
Unique northwoods atmosphere serving pizza, sandwiches, appetizers and complimentary baskets of peanuts. Great game room for children. Only minutes from Six Flags. Offering carry out and delivery.
My Honey Co.
At My Honey Co, we take pride in our honey. We promise you the best quality honey possible. It is natural, completely raw, and unpasteurized. We invite you to enter our special world of honey and let one of nature's finest foods sweeten your day!
Towneplace Suites - Dundee
Hotel amenities include fully equipped kitchens, large work spaces with 2 phone lines, personalized voicemail, on-site business services, and more.
CITY:West Dundee
Tea room, restaurant, loose tea retail sales, Sunday brunch and afternoon tea service. A wonderful place to relax and receive the royal treatment!
Denny's - Carpentersville
Serving breakfast, lunch, and dinner seven days a week!
Chessies Restaurant
Chessie's was built around Barrington's former train station and features a unique dining experience in a vintage Illinois Central railroad dining car. The Menu ranges from appetizers to salads, sandwiches, pasta, fresh fish, and USDA choice steaks from the Stockyards Packing Company. Daily specials including $5 Burger Day, Friday Fish Fry, Saturday Prime Rib Specials and Sunday Brunch. Our banquet facility is available for your next event for groups of 25-80.
Forest Lodge
King or double beds, guest laundry, cable TV, jacuzzi suites. Efficiency apartments for extended stays.
CITY:Prospect Heights
Around the Clock Restaurant and Bakery
We offer quality food at a great value - breakfast, lunch and dinner 7 days a week, along with delicious specials and seasonal features and our own in-house bakery, featuring the best in homemade pies, cakes, pastries and other tempting desserts. Our on-site bakers will also be happy to create any specialty-themed item appropriate for your special event.
CITY:Crystal Lake
Rocky Vanders Cafe and Bar
American food including pizza, 25 wide screen TVs, live entertainment, 9500 square feet of party rooms. Many food and drink specials.
CITY:Prospect Heights
Castle Gardens
Garden decorations, lawn furniture, plants, flowers, shrubs and trees. Come see our selection and find just what you're looking for!
La Roca Tapas Restaurant
To Us, food is synonymous with freshness, and quality . We are your quintessential tapas restaurant which preserves one of Spain's greatest traditions, excellent Tapas.We stay away from assembly-line work and still prepare our dishes fresh upon ordering and entirely from scratch. Where Tim Trujillo promises "The worlds greatest homemade sangria."
CITY:Arlington Heights
Econo Lodge Waukegan
If you're looking for a clean, quiet room with a friendly and helpful staff, Econo Lodge is the place to stay. With the newly-remodelled rooms full of amenities, your stay is sure to be comfortable and enjoyable! Rooms feature 56-channel cable televisions, king and queen beds, and free local calls. Rollaways and cribs are available, along with a complimentary continental breakfast.
Expressly Leslie
Vegetarian specialties
Primrose Lane
Antiques, home decor, one-of-a-kind architectural pieces and unique gift items.
CITY:West Dundee
Javier's Sabor Mexicano
Javier's Sabor Mexican is an everyday celebration of fresh food, margaritas, and a large selection of fine tequila. This Mexican restaurant has been around since 1967. Consistency, quality, and generous portions are what keeps everyone coming back. Javier's Sabor Mexicano features four separate dining rooms and a full service bar for your dining pleasure as well as private parties and special events.
CITY:Arlington Heights
Marriott Suites Chicago Deerfield
his hotel features 248 suites with a private parlor room separated by French doors. Suites include a spacious bedroom with a separate living area with sleeper sofa, wet bar, microwave, refrigerator, coffee maker, Plug-In Panel to connect your laptop, iPod
Bank Block Antiques and More
Antiques, collectibles, furniture, floral arrangements, jewelry, glassware, made-to-order furniture and shelves, in-home help with decorating and more.
Egor's Tobacco and Gift Shoppe
Cigar and pipe tobacco accessories.
Arlington Heights Downtown Business Association
Stroll through our 8-block Downtown Business Association and find a great array of shops, many of which have provided quality services to our community for decades. The Downtown Business Association is home to a pharmacy and grocery store, to jewelry stores and art galleries, to clothing stories and home décor boutiques. Transportation services are also available if you wish to take in other Chicagoland sites.
CITY:Arlington Heights
Holiday Inn Express - Riverwoods
Country Inn and Suites has a charming, home-like atmosphere with a hardwood lobby and fireplace.
A campground nestled in Marengo.
Ridgefield Antique Dealers
Escape for the ordinary! A blend of dealers featuring quality, affordable American and English antiques including oak, pine, walnut & mahogany, quilts, china, glassware & unusual antique accessories.
Hyatt Place - Hoffman Estates
All suite accommodations, includes complimentary continental breakfast, indoor pool & fitness center.
CITY:Hoffman Estates
McKenna's - Holiday Inn Rolling Meadows
Casual dining restaurant and bar, featuring Wednesday night prime rib buffet. In the Rolling Meadows Holiday Inn.
CITY:Rolling Meadows
44th Annual Gurnee Days Celebration
Gurnee Days returns this week for 4 days of family fun. Activities include a bicycle rodeo, live entertainment, Farmers Market, Gurnee Idol, golf tournament, and amusement rides, a 10K race, baby contest, rib fest and eating contest, fireworks, a pancake breakfast, parade, Scoop the Loop Car Show, petting zoo, pony rides, a talent show, exhibitors, games, food booths and stage events. Please visit the website for times and entertainment schedule.
Oregano's Corner Café
Oregano's serves Italian comfort food, using the same old country recipes passed down for over 100 years - one generation to the next. Only the freshest ingredients available are used, and of course, each dish is prepared the old fashioned way - from scratch order by order, so it does take just a little longer to serve you. Come hungry, enjoy, take home what you don't finish and leave happy!
CITY:Hawthorn Woods
D & J Bistro
This chef owned since 1987 restaurant, offers a great line-up of "True Bistro Dishes", with special menu items available monthly. Offering Daily Specials available "A la Carte" or as a 3 Course Prix-Fixe Dinner. Gluten free, vegetarian and kids menus available. Private room for parties of up to 50 people.
CITY:Lake Zurich
Steel Heart Ltd.
Practical and stylish home and garden products for today's changing lifestyles!
Colonial Cafe - Crystal Lake
For over 100 years, Colonial Cafe and Ice Cream has been a family favorite restaurant - satisfying everyone's taste buds. All day, everyday our menu provides delicious options varying from eggceptional breakfasts, lunches, dinners, and ice cream!
CITY:Crystal Lake
Asian Tokyo
Asian Tokyo, located in Rolling Meadows, offers an all you can eat sushi deal Sunday thru Thursday for $21.95.
CITY:Rolling Meadows
Saluto's Pizza & Pasta
Saluto's, a favorite Italian restaurant in Gurnee features a two-story bar, a large dining room with booths and a private banquet meeting room. Famous for their homemade pasta and the "secret recipe" salad dressing, Saluto's has been a hit in northern Lake County since 1990. This full service restaurant's claim to fame is the pizza, pasta and the courteous service. From their delectable appetizers like Artichoke Heart Fondue, Toasted Ravioli and so much more; to their homemade sauces and pastas; to their pizza, either thin, pan or stuffed, everyone will find something to enjoy on their menu. Very family oriented, Saluto's also offers a children's menu for the smaller guests.
Anvil Club
Established in 1956, The Anvil Club is Chicago's premier private dining club, renowned for great steaks & seafood and unsurpassed service.
CITY:East Dundee
Francesca's Tavola
Contemporary, casually sophisticated trattoria ambience with authentic rustic cooking, firendly service, and fair prices. Perfect location for a great night out or a private party.
CITY:Arlington Heights
Stage Left Cafe
Decorated in back-stage motif, the new Stage Left Cafe offers a variety of beverages, souvenirs, entertainment and more. All presented in a unique atmosphere of theatrical tradition! Enjoy desserts too.
Tom's Vegetable Market
Seasonal - April through December. Garden center featuring baskets, fresh produce, bakery and gift shop, and a fall festival.
Holiday Inn Express Hotel & Suites Deerfield-Lincolnshire
This beautiful hotel is conveniently located close to Six Flags Great America Amusement Park, Chicago Botanic Gardens, Gurnee Mills Outlet Mall, Great Lakes Naval Base, Ravinia and just 15 minutes from O'Hare International Airport. Our new contemporary rooms and whirlpool suites are a refreshing retreat and include a complimentary hot breakfast, microwave, mini refrigerator and wireless and wired high-speed Internet. The hotel offers an indoor pool, whirlpool and modern fitness center featuring Life Fitness Cardio equipment. Hotel also offers complimentary local shuttle.(Based upon availability) Business travelers can relax in one of the Executive suites, hold a meeting in the 900 sq. ft. meeting room and take advantage of the 24-hour business center.
Community Thrift Store
Resale business.
CITY:East Dundee
Motel 6 - Chicago/Rolling Meadows
Located just off Highway 53 North in the hear of the Rolling Meadows business district. Arlington Park Racecourse - 1 mile, Woodfield Mall - 5 miles. Complimentary morning coffee, swimming pool. WiFi available in all rooms. Motel 6 offers clean comfortable rooms and great service at the lowest price of any national chain.
CITY:Rolling Meadows
Harry's of Arlington
Harry's of Arlington is a local's favorite bar and restaurant. Located in downtown Arlington Heights it is where fun is had by all! Come on by with family and friends for dinner and one of our many drink options.
CITY:Arlington Heights
California Pizza Kitchen
California Pizza Kitchen is a casual-dining restaurant serving up California creativity through its innovative menu items. CPK provides a range of inspired dishes, from hearth-baked pizzas, to creative salads, pastas, entrees, soups and sandwiches. Offering dine-in, take-out, catering, online ordering and an award-winning CPKids Menu.
CITY:Arlington Heights
Mago Grill and Cantina
A celebration of Mexico's heritage, Mago Grill & Cantina's original Mexican and Latin menu is comprised of authentic favorites of freshly smashed tableside guacamole, seafood ceviches, savory salsas, fresh salads, and main dishes of steak, chicken, pork and seafood including the chef's own Grandma Paula's family recipes.
CITY:Arlington Heights
Harvard Antique Emporium
Come see our selection of antiques. Something for everybody's taste.
Motel 6
Newly Renovated Hotel Property, Outdoor Pool, Free High Speed Wireless Internet, Free Coffee, Pets Are Welcome, 3 Miles From Six Flags Great America, The Great Lakes Naval Training Center And Gurnee Mills Mall.
Super 8 - Richmond
Free Superstart Breakfast, High Speed Internet. Close to Bike and Snowmobile Trail, Fishing, Boating, Skiing, Golf Course and Richmond Historic District. King or Double Beds, Expanded Cable, HBO, ESPN, CNN, Fridge-Micro In Some Rooms. Pets Accepted - 10.00 per day.
Courtyard by Marriott, Chicago Waukegan/Gurnee
This newly renovated, hotel located in the Fountain Square Plaza, is near the Great Lakes Naval Training Center, Abbott and Cardinal Health and minutes from Six Flags. Relax and get ready for the day in one of 137 spacious guest rooms or 12 suites. Enjoy high-speed Internet access, premium pay movies and free in-room coffee - plus an indoor heated pool and hot tub. Start the day at the Courtyard Café with a hot breakfast buffet or grab a snack from "The Market" which offers a variety of food and beverages 24/7. Use the business center to charge your phone, plug in a laptop or fax/print documents. The 1,284 sq ft of meeting space is available for small meetings and social events. Hotel offers shuttles to Navy Graduation.
Shakou Sushi
Modern Japanese Cuisine Restaurant offering gorgeous decor in the venue and fresh and delicious items on the menu. Shakou features city caliber cuisine in a city caliber venue with city caliber service.
The Black Orchid Boutique
The Black Orchid Boutique has fashionable apparel, jewelry and footwear for women.


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Hey, I'm Katherine!
Westby, Wisconsin, United States · Member since June 2011
I'm Katie, and I'm studying a master's in tourism management in Girona, Spain at the moment. I grew up on a small dairy farm in western Wisconsin, and I've been traveling the world since I was 18. My craziest adventures have taken me to hike to Kaieteur Falls in Guyana, catch a ride on a semi truck in Mozambique, and work in Antarctica.

subset: commoncrawl


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Did anybody ever transcribe Mike Moreno (or Adam Rogers, Kurt Rosenwinkel, Jonathan Kreisberg or another modern jazz guitar player) when he comps behind a solist ? Any help would be great.
some examples :
Mike Moreno : comping(9 posts)
Did anybody ever transcribe Mike Moreno (or Adam Rogers, Kurt Rosenwinkel, Jonathan Kreisberg or another modern jazz guitar player) when he comps behind a solist ? Any help would be great.
Hi Neither,
I can't see the videos as I'm at work but there are two sources of information on this subject I would recommend:
1. The book 'Jazz Guitar Comping' by Andrew Green;
2. The 5 part video lesson series 'Modern Jazz Guitar' by Tim Lippencott at mikemasterclasses.com - the 'harmony' video has plenty of information on "contemporary" comping approaches.
Thanks Benny for your answer.
I've got Andrew Green's book. It's a great book but it talks about a much more traditional comping than Mike Moreno plays.
I've got the Tim Lippincott video about modern Jazz Guitar (Harmony), and it's one of the best thing I saw on the subject.
But my question is about the "real thing" great players play (voicing, rythm and harmony), about transcription of what they play.
I search for this kind of thing, but for a modern guitar player :
Does anyone know what song they are playing in the video?
The tune is UMMG (Upper Manhattan Medical Group) by Billy Strayhorn.
I don't know what your money situation is like, but you could email him about lessons. He teaches via Skype and could probably tell you his chordal philosophy directly. I haven't studied with him so I have no idea if he is a good teacher.
Who knows the name of this song?
Wonderful tune! I would love to know too if anyone has any idea??
Mike's one of my favorite players. I've transcribed a lot of his stuff, although I haven't really gotten into his comping so much--mostly single-note lines.
You can see my transcriptions here: http://www.williamflynnmusic.com/transcriptions/
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Patriot Day tribute
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To commemorate Patriot Day and the 12th anniversary of the Sept. 11, 2001 terrorist attacks in New York City, the Boone Fire Department raised the ladder on truck 8-66 with a flag at half staff at 7:46 a.m. CST - the time that Fligh 11 impacted 1 World Trade Center. The flag was raised to full at 3:43 p.m. to honor the 343 New York firefighters that died during the attack. "We ask that everyone take some time…to do something in the spirit of those that lost their lives," the department posted on their Facebook page, "Help those around you…and keep those that lost their lives on that day in your memories.


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Flanders News
Local news for Flanders, NJ continually updated from thousands of sources on the web.
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Safety measures ordered for butane, propane filled rail cars in Mount Olive
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A big plus about this hotel is the free parking. It seems like most hotels in the LA/Orange County area charge for parking, but here, it's included. The room was decent and I got one with a microwave, and a fridge. Free internet is included and it worked pretty well. The staff were super friendly. I had a problem with the flat screen TV, as it froze and none of the controls worked. When I informed the front desk, they sent someone up fairly quickly. He sorted it out by unplugging the TV and plugging it back in again. This hard boot seemed to unfreeze it. It happened 2 more times during my 3 day stay, but I was able to fix it myself the second and third times. I ate 2 breakfasts and one dinner at the hotel restaurant. The food was okay and resonably priced. The waitresses were very pleasent and friendly. The hotel is easy to get to. From the I 405 Freeway, get off at Atlantic Avenue and head south. It's a little way south of the Pacific Coast Highway (PCH). I see other reviewers commenting on the bad neighborhood. I agree, but if you're driving, it's not a problem. There were some dodgy looking characters hanging around in front of the hotel a couple of nights, but I just drove into the underground car park and took the elevator to my floor. No need to come into contact with these characters, unless you want to. My room was clean and, overall, I was satisfied.
- Official Description (provided by the hotel):
- Welcome to the Holiday Inn Downtown Long Beach Hotel, Located just minutes from the Long Beach Convention Center, Carnival Cruise Terminal, The Aquarium of the Pacific, The Historic Queen Mary and much more. We offer complimentary shuttle services within 3 mile radius, free high speed wireless internet access, 24 hour fitness center, and a heated pool/jacuzzi. Your Constant Caring Friends at the Holiday Inn Downtown Long Beach Hotel are dedicated to providing you with extraordinary service assuring safety and satisfaction. ... more less
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- TripAdvisor is proud to partner with Booking.com, Hotels.com, IHG, Hotwire, Expedia, Priceline, Travelocity and Odigeo so you can book your Holiday Inn Long Beach (Dwtn Area) reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.
- Also Known As:
- Holiday Inn Long Beach (Dwtn Area) Hotel Long Beach
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|Publication number
|Publication type
|Application number
|Publication date
|Aug 22, 2000
|Filing date
|Jun 24, 1998
|Priority date
|Jun 24, 1998
|Fee status
|Publication number
|George Z. Chrysos, Joel S. Emer, Bruce E. Edwards, John H. Edmondson
|Original Assignee
|Digital Equipment Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (4), Non-Patent Citations (6), Referenced by (71), Classifications (15), Legal Events (8)
|External Links: USPTO, USPTO Assignment, Espacenet
Generally, a computer program is an ordered set or sequence of instructions to be processed, or executed, by a computer processor. The processor fetches the program instructions and executes them. Normally, instructions are fetched sequentially, with breaks in the sequence occurring when a branch or jump instruction is encountered. The order in which the instructions are fetches is the program order.
Many modern microprocessors allow instructions to execute out of order. In particular, instructions are executed from a set of already fetched instructions, out of program order, but still require certain dependencies, such as register and memory dependencies, to be preserved. A register dependency results from an ordered pair of instructions where the later instruction needs a register value produced by the earlier instruction. A memory dependency results from an ordered pair of memory instructions where the later instruction reads a value stored in memory by the earlier instruction.
Thus, on the one hand, the out-of-order execution of instructions improved performance because it allows more instructions to complete in the same amount of time by efficiently executing independent operations. However, problems may occur when executing load and store instructions out-of-order.
The terms load, load instruction and load operation instruction are used herein interchangeably and refer to instructions which cause data to be loaded, or read, from memory. This includes the usual load instructions, as well as move, compare, add, and so on where these instructions require the reading of data from memory. Similarly, store, store instruction and store operation instruction are used interchangeably and refer to instructions which cause data to be written to memory.
When a load instruction executes before an older, i.e., earlier fetched, store instruction referencing the same address, the load may retrieve an incorrect value because the data the load should use has not yet been stored at the address by the store instruction. Hardware detects this memory dependency violation, and squashes the load instruction and its subsequent dependent instructions, i.e. these instructions are ignored and must be re-executed (replayed). Because valuable time and resources have been wasted, such hardware recovery degrades processor performance.
Memory reference tagging stores have been proposed in which information from prior memory order violations is used to product subsequent memory dependencies, and consequently to prevent reordering of certain instructions as appropriate. This general method is described in U.S. Pat. No. 5,619,662 (Steely), "Memory Reference Tagging", dated Apr. 8, 1997 (hereinafter '662 patent), and incorporated herein by this reference in the entirety.
The '662 patent describes a means of detecting dependent load and store instructions which have executed out of order, by using a write buffer to keep track of executed load and store instructions until it is determined whether or not they have executed in their proper order. Four different approaches to having such detection of an out-of-order execution are described. In the first, part of the referenced (or target) memory address is used as a tag to be associated with each of the out-of-order instructions. If these instructions layer appear again in the instruction queue, the fact that they have identical tags will cause them to be issued in program order.
The second approach uses an assigned "problem number" as a tag. Two instruction referencing the same memory address and with the same problem number are not re-ordered.
The third approach simply associates a tag bit with an instruction to indicate that other memory reference instructions should not be re-ordered around the tagged instruction.
Finally, the fourth approach turns off reordering for some number of instructions when entering a subroutine.
U.S. Pat. No. 5,615,350 (Hesson), "Apparatus to Dynamically Control the Out-of-Order Execution of Load-Store Instructions in a Processor Capable of Dispatching, Issuing and Executing Multiple Instructions in a Single Processor Cycle," issued Mar. 25, 1997, teaches a store barrier cache for constraining the reordering of loads and stores to reduce memory order violations. A store barrier cache keeps track of stores that tend to cause memory-order violations. The cache is accessed in parallel with the instruction cache, and is notified when a memory-order violation occurs. The store causing the violation is noted in the store carrier cache as problematic. The next time the store is fetched, the processor inhibits all subsequent loads from executing until that store executes. However, processor performance in large machines still suffers because loads which will not cause memory order violations are often prohibited from executing as early as possible, reducing the processor's efficiency.
Moshovos et al., in "Dynamic Speculation and Synchronization of Data Dependence", CS Department, University of Wisconsin-Madison, refines the goals for memory dependence prediction: not only should loads be delayed when necessary to avoid memory-order violations, they should also be released as soon as possible when they can safely execute. Their solution is a set of small, fully-associative tables which hold load/store pairs that have caused memory-order violations in the past, and which are used to synchronize the execution of the two instructions to avoid more violations in the future. However, when the table size is limited to reasonable hardware constraints, there is significantly less performance than an oracle (perfect) memory dependence predictor would provide. In addition, the tables are complex and cumbersome to generate and maintain, and are slow to access.
Moshovos et al. continued their work in "Streamlining Inter-operation Memory Communication via Data Dependence Prediction", MICRO-30, December, 1997, and extended it to using memory dependence prediction to reduce load latency. They do this by a mechanism they call memory cloaking in which a load/store pair has an identifier that is used to bypass the store's data value directly to the consumers of the load. As such, this solution involves the passing of data to the consumer which is typically beyond an instruction scheduler.
Tyson and Austin, "Improving the Accuracy and Performance of Memory Communication through Renaming", MICRO-30, December, 1997, suggest that the memory trap penalty can be effectively reduced by re-executing only the load instruction and its tree of dependent instructions, without affecting other instructions fetched after the load but which are not dependent on it. They combine memory dependency prediction and load value prediction to directly satisfy load instructions without having to access the cache.
Another solution to the problem of reordering dependent load instructions is to remember recently squashed loads, and to force those loads to wait for all prior stores the next time they are fetches.
Some of the above approaches suffer a performance degradation because loads are delayed longer than necessary.
The goals of memory dependence prediction are 1) to predict which load instructions, if allowed to execute, would violate a true data dependence and 2) to delay the execution of these loads only as long as is necessary to avoid a memory-order violation. When a memory dependence predictor makes a mistake, it fails one of these two goals.
The memory dependence predictors described by Hesson and Steely do not address certain memory dependence characteristics found in some programs, which can complicate prediction. In particular, a memory dependence predictor needs to handle cases where a load depends on multiple stores or a store has multiple loads that depend on it.
The present invention uses a predictor that addresses these types of memory dependencies, based on the concept of a store set for use in memory dependence prediction. Each load operation instruction, or load, in a program has a specific set of store operation instructions, or stores, upon which it depends. These stores are determined by first allowing loads and stores to execute speculatively out of order, causing memory order violations. Each store which causes a memory order violation with a load is added to the load's store set. The store set is then used to predict which stores a load must wait for before executing.
While Tyson and Austin's approach should significantly reduce the memory trap penalties, designing a processor to be able to re-execute only the dependent instructions may be difficult. The present invention reduces the memory trap rate to negligible amounts, making the memory trap penalty relatively unimportant.
The intent in Hesson is to reduce memory-order violations by enforcing strict ordering around stores which tend to conflict with nearby loads, effectively creating store barriers. The weakness of this approach is that many loads which do not depend on the store barriers are unnecessarily delayed. These false dependencies degrade performance.
The present invention focuses on program behavior that tends to reduce memory dependence prediction accuracy. As different paths of code are executed, a single load instruction can become dependent on multiple store instructions. In addition, multiple load instructions can be dependent on the same store. In order to achieve nearly optimal performance, a memory dependence predictor must handle these cases.
Accordingly, a method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory. Some of the fetches instructions are loads including any instructions which cause load operations. Other fetches instructions are stores, including any instructions which cause store operations.
The fetched instructions are issued out of program order. A load/store order violation occurs when a load executes prior to a store on whose data the load depends. On such an occurrence, the effects of the load operation and its dependent instructions are undone and the instructions are re-executed. The load is then associated with the store on whose data the load depends.
Finally, on a later fetch of the load instruction, its execution is delayed until after the execution of any previously-fetched store instruction which has been associated with the load instruction.
In a preferred embodiment, all load and store instructions among which dependencies are detected are grouped together into a store set.
When a subsequent load/store order violation is detected and the store already belongs to some store set, the load is added to that store set if the load does not already have its own store set. If the load does have a non-empty store set, its store set is merged with the store set to which the store belongs.
In a preferred embodiment, merging occurs gradually by moving one load or store to the other's store set when a violation occurs. At each violation involving two store sets, one of the store sets is declared a winner. The load or store which is in the losing store set is removed from the losing store set and added to the winning store set. In a preferred embodiment, every store set is assigned a unique store set identifier (SSID), and a numerical comparison of SSIDs is used to declare the winner. For example, the store set with the lower SSID may be declared the winner.
Alternatively, the store set with fewer instructions is declared the winner.
In a preferred embodiment, stores within a store set must execute in fetched order. In a further embodiment, both stores and loads within a store set must execute in fetched order. The important point is that stores precede the load on which they depend.
A preferred embodiment utilizes a Store Set Identifier Table (SSIT) for storing store set identifiers (SSIDs). The SSIT is indexed by respective load and store instruction program counters (PCs). The index for the SSIT may comprise part of an instruction PC, including a hash of a part of the instruction PC.
A Last Fetched Store Table (LFST) holds an instruction identifier for each store set and is indexed by the SSIDs associated in the SSIT with the perspective load and store instructions. Each instruction identifier references the most recently fetched store instruction from the store set identified by the respective SSID. Execution of any load or store instruction under consideration is delayed if the instruction is associated with a store set whose respective entry in the LFST refers to a store instruction which has not yet executed.
Eventually, the instruction under consideration is executed after the store instruction, identified in the LFST at the time the instruction under consideration accessed the LFST, is executed.
In a preferred embodiment, SSIT entries are intermittently, or alternatively, cyclically, invalidated.
In a further embodiment, a tag portion of a load or store PC is saved in the SSIT, such that when the load or store is later fetched, its tag portion is compared with the tag retrieved from the SSIT, and if they match, the corresponding SSID in the SSIT if valid. Thus, instructions having matching indexes but not belonging to the same store set are not forced to wait needlessly for instructions on which they do not depend.
In yet another embodiment, a counter, preferably a 2-bit counter, is associated with each SSIT entry. Each counter is set to a predetermined value, preferably its maximum value, when a load/store violation occurs involving the store instruction associated with the SSIT entry. If it is determined that a real dependence does not exist on a subsequent non-reordered issuance of the store instruction, the associated counter is decremented. Otherwise the counter is incremented. If the counter's value is less than some threshold, the associated store is removed from the load instruction's store set. Real dependence is determined by comparing the two instructions' memory-reference (target) addresses after both have executed.
Finally, yet another embodiment of the present invention represents setoff items in a direct-mapped table, by associating an item with a set. If no appropriate set already exists, a new set is created for the item, and the item is associated with the new set. A unique set identifier (SID) is assigned to each set. SIDs are then stored in a table at locations indexed by an index which is based on the item.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a block diagram showing the typical stages of a processor's instruction pipeline.
FIG. 2 is a schematic diagram showing an instruction stream as it enters the instruction queue of FIG. 1.
FIG. 3 is a schematic diagram illustrating a re-ordered execution order of the instruction stream of FIG. 2.
FIG. 4 is a schematic diagram illustrating the executed instruction stream of FIG. 3 before and after an instruction squash.
FIG. 5 is a schematic diagram illustrating dependent loads and stores in an instruction stream, with the associated store sets of the present invention.
FIGS. 6A-6E are schematic diagrams illustrating the preferred embodiment of the present invention which employs two tables.
FIGS. 7A-7C are schematic diagrams illustrating the merging technique of the present invention.
FIG. 8 is a schematic diagram illustrating how unrelated loads with the same index point to the same table entry in the present invention.
FIG. 9 is a schematic diagram of a preferred embodiment of the present invention using tags.
FIGS. 10A and 10B are schematic diagrams of a 2-bit counter used in a preferred embodiment of the present invention to invalidate table entries.
FIG. 1 shows the various stages of a typical instruction pipeline 100. In step 101, one or more instructions are fetched, typically from an instruction cache. Next, in step 103, the instructions are decoded. In step 105, architectural registers named in the instructions are mapped to physical registers. Instruction identifiers are assigned to instructions during this stage.
In step 107, instructions are written into the instruction queue. The instruction queue decides which instructions are to issue based on available resources such as registers and execution units, and on register dependencies, and re-orders the instructions accordingly, assigning the issuing instructions to execution units.
Next, in step 109, any registers are read as required by the issued instructions. In step 111, the instructions are executed. Any memory references which must be derived are calculated during this stage. Step 112 is the memory access stage in which memory addresses derived in step 111 are accessed. In step 113, data is written into the registers. Finally, in step 115, instructions are "retired".
FIG. 2 shows an instruction stream 201 as it enters the instruction queue 107 (FIG. 1). Instructions are placed in the queue in the order in which they are encountered in the stream 201. The instruction labeled 203, "st R7,0(R30)" is a store instruction. When it is executed at stage 111 of FIG. 1, the data in register R7 is stored in a target memory location whose address is the sum of 0 and the contents held in register R30. This target address must be computed during the execution stage 111 of the instruction pipeline 100.
The instruction labeled 205, "ld R29,0(R30)" is a load instruction. When it is executed at stage 111 in FIG. 1, the memory location is referenced whose address is again the sum of 0 and the contents held in register R30, and the data held in this referenced memory location is loaded into register R29. Other instructions 207 may be fetched between store instruction 203 and load instruction 205, and of course, additional instructions 208 may be fetched after instruction 205. When the value held by register R30 is the same for both instructions 203, 205, the load instruction 205 is dependent on the store instruction 203 because the load instruction 205 needs to read the data stored in memory by the store instruction 203.
As instructions from stream 201 enter the queue 107, they are assigned instruction identifiers 209, here shown in decimal form. Specifically, a value of 1012 has been assigned as the instruction identifier to the store instruction 203, and a value of 1024 has been assigned as the instruction identifier to the load instruction 205.
As stated above, depending on available resources and register dependencies, instructions are issued out-of-order from the instruction queue 107. An execution order of instructions 301 is depicted in FIG. 3. Here the load 205 and store 203 instructions have executed out of program order. This could be, for example, because register R7 is not yet available to the store instruction 203. In any event, if register R30 contains the same value for both instructions 203, 205, the load instruction 205 will potentially be reading in the wrong data because it needs the data to be stored by the store instruction 203.
This out-of-order load/store pair is detected when the store 203 executes. The load instruction 205 and the instructions 208 (FIG. 2) issued after it are squashed and re-issued. Note that the instruction identifiers 309 previously assigned stay with the instructions after re-ordering.
FIG. 4 depicts the issued instructions 401 before and after an instruction squash. The same out-of-order instructions 203, 205 shown in FIG. 3 are shown in FIG. 4. The out-of-order execution is detected as the store instruction 203 issues, and the load instruction 205 and its subsequent instructions 208 (FIG. 2) are squashed at 403. After the store 203 has executed, it is safe for the load 205 to execute and it is re-issued at 405 along with the subsequent instructions 407 corresponding to instructions 208.
Within the context of load/store memory order dependencies and instruction reissuing, the present inventions's concept of store set is based on two underlying assumptions. The first is that the historic behavior of memory-order violations is a good predictor of memory dependencies. The second is that it is beneficial to predict dependencies of loads where one load is dependent on multiple stores or multiple loads depend on the same store. The present invention provides these functions with direct-mapped structures or table which are time and space-efficient in hardware.
FIG. 5 illustrates how the store sets of the present invention are associated with dependent loads and stores in an instruction stream 451 before reordering. Loads 469 and stores 467 are identified by their program counters (PCs) 453. Each instruction 455 is shown with its corresponding program counter 453, and an indication such as M[A], for example, which represents an access to memory location A.
Each load instruction 469 is associated with a set of store instructions. For a given set of store instructions, the respective PCs of the store instructions in the set form a store set 457 of the associated load instruction 469. A load's store set 457 consists of every store PC that has caused the load to suffer a memory-order violation in the past. Assuming that the loads 469 tend to execute before the prior stores 467, causing memory-order violations, then the store sets 457 have been filled in accordingly as illustrated in FIG. 5.
In particular, the load instructions 469 indicating "load M[B]" are associated with store instruction 467 stating "store M[B]". The program counter 453 of this store instruction is PC 8 in the illustrated example. The respective store sets 459, 465 of the associated load M[B] instructions (at PC 28 and 40) thus each have an element "PC 8". Likewise, load instructions 469 "load M[C]" (at PC 36) is associated with store instructions "store M[C]" at PC 0 and PC 12. The store set 463 for that load instruction (PC 36) thus has elements "PC 0" and "PC 12". The load instruction at PC 32 has no associated store instruction and thus has an empty store set 461.
When a program begins executing, all of the loads have empty store sets 457, and the processor allows full speculation of loads around stores. For example, when load PC 36 and store PC 0, both of which access some memory address C, cause a violation by executing in the wrong order, the store's PC 0 is appended to the store set 463 of the associated load (at PC 36). If another store, e.g., PC 12, conflicts with that same load (PC 36), that store's PC is also added to the associated load's (PC 36) store set 463. The next time the processor sees that load (PC 36), the load is delayed from execution only until after execution of any recently fetched stores identified in the load's store set 463. In the depicted example, the processor executes load PC 36 only after store PC 0 or PC 12, assuming either store has been recently fetched.
When a load 469 is fetched, the processor determines which stores in the load's store set 457 where recently fetched but not yet issued, and creates a dependence upon those stores. Loads which never cause memory-order violations have no imposed memory dependencies, and execute as soon as possible. Loads which do cause memory-order violations become dependent only on those prior stores upon which they have depended in the past.
If a store PC 8 in the store set 459 of load PC 28 causes a memory-order violation with a second load PC 40, it (the store PC 8) becomes part of that load's store set 465 also.
Note that a load can have multiple store dependencies, for example, the load at PC 36 depends on the stores at PC 0 and PC 12. Furthermore, multiple loads can depend on the same store. For example, the loads at PC 28 and 40 both depend on the store at PC 8.
This situation where multiple loads depend on the same store is fairly common, occurring when there is one writer and multiple readers of a value. One load depending on multiple stores is somewhat more obscure. Three situations where this happens are:
1) a load can depend on stores from different paths, e.g.,. (if (expr) then x=a; else x=b; . . . c=x;)
2) A load can depend on multiple stores to fields of a structure packed in a data work that are all read together, e.g. (writes of the red, green and blue components of a color structure) and
3) Assuming that memory write-after-write hazards are treated as creating dependencies among a series of stores to the same location (e.g., multiple spills to the same location), a load can depend on all the stores in the series.
Since store sets 457 allow a load to be dependent on multiple stores, it would theoretically be necessary to have a mechanism that delayed the load until all the stores in the store set had executed. However, constructing such a mechanism can be expensive. It is preferable to make the load dependent on just one of those stores, yet it is not known which of the load's store dependencies will be the last to execute.
To solve this problem, in a preferred embodiment, stores indicated within a store set 457 must execute in program order. This is accomplished by making each of the stores indicated in a given store set 457, dependent on the last fetched store indicated in the store set 457. Each store specifies one dependence and each load specifies one dependent to form an in-order chain resulting in correct program behavior. By requiring that the stores indicated in a store set 457 execute in order, the present invention eliminates the need for complicated write-after-write hazard detection and data forwarding. If two sequential stores to location X are followed by a load to location X, the load effectively depends only on the second store in the sequence. Since ordering within store sets 457 is enforced, special hardware is not needed to make this distinction.
FIG. 6A is a diagram of a preferred embodiment of the present invention comprising two tables. The first is a PC-indexed table called a Store Set Identifier Table (SSIT) 601. A recently fetched load accesses the SSIT 601 based on the load's PC 603 and reads its store set identifier (SSID) 605 from the SSIT 601. If the load 603 has a valid SSID, as indicated by valid bit 607, then it has a valid store set.
The valid SSID 605 points to an entry 611 in a second table, the Last Fetched Store Table (LFST) 609. The value stored in the LFST entry 611 identifies a store instruction 619 which is part of the load's store set if the corresponding valid bit 612 is set. This store instruction 619 is the most recently fetched store instruction from the load's store set. Validity of the outputs of both tables 601, 609 is checked by an AND gate 621.
As FIG. 6B shows, a subsequently fetched store 615 also accesses the SSIT 601. If the store 615 finds a valid SSID 629, then the store 615 belongs to a valid store set of an associated load. The store 615 must then do two things. First, it accesses the LFST 609 using the valid SSID index 629 from table 601 and retrieves from LFST entry 617 a pointer (St ID) to the most recently fetched store instruction 619 in its store set. The new store 615 is made dependent upon the store 619 pointed to in the LFST 609 and informs the scheduler of this dependency. Second, the LFST 609 is updated by inserting the identifier of the new store 615 at entry 617, since it is now the last fetched store in that particular store set.
The mechanism for memory dependence prediction using these tables is shown in FIG. 6C. Assume that at the start of a program, all entries in the SSIT 601 are invalid. Initially, store and load instructions access the table 601 and get no valid memory dependence information. If a load 651 commits a memory-order violation with a store 653, a store set is created in the SSIT 601 for that load 651. The load 651 and store 653 instructions involved in the conflict are assigned a store set identifier, say SSID X. SSID X is written into two locations in the SSIT 601: the first location 655 is indexed by an index portion 651A of the load PC 651, and the second location 657 is indexed by an index portion 653A of the store PC 653.
The next time that store 653 is fetched, it reads the SSIT entry 657 indexed by the store's 653 PC. Since the store set's SSID 657 is valid, it is used to access the LFST 609 where it finds no valid entry 659 for store set X. Therefore, store 653 is not made dependent on another store.
As FIG. 6D shows, the store 653 proceeds to write its own instruction instance identifier K into the LFST 609 at location 659. When the load instruction 651 is subsequently fetched, it accesses the SSIT 601, reads store set ID X from location 655 and then accesses the LFST 609 with SSID X. The LFST 609 conveys to the instruction scheduler that the load 651 is dependent upon the instruction whose identifier is indicated at the table entry 659. Thus this time, the instruction scheduler will impose a dependence between the load 651 and store 653 due to entry 659 now indicating instruction identifier K (the store's 653 instruction number).
As shown in FIG. 6E, if the load 651 then conflicts with a different store 663 (having instance identifier J), the SSIT 601 is updated to reflect the new memory-order violation. SSID X is copied into the SSIT entry 665 indexed by the new store's PC 663.
Now there are three valid entries in the SSIT 601 that point to SSID X. The next time the two stores 653, 663 and the load 651 are fetched, the second fetched store 663 will depend on the first store 653, and the load 651 will depend on the second store 663. After a store instruction executes, it accesses the LFST 609 and invalidates the entry 659 if it is equal to the store's own identifier. This ensures that loads and stores are only made dependent on unexecuted stores. If the stores are from different code paths and not executed every time the load is executed, only the store that is fetched will access the SSIT 601 and modify the LFST 609. The load is always dependent on the appropriate store and the stores will never be forced to depend on each other, since they are executed at different times.
Preferably stores are constrained to be in only one store set at a time to keep the SSIT 601 and the LFST 609 simple. Alternatively, a store could be part of more than one store set if the SSIT 601 were allowed to hold more than one SSID in each entry. The multiple SSIDs would then have to access the LFST 609, increasing the number of read ports needed. Also, each load would then be dependent on up to two stores, adding more size and complexity to the instruction scheduling hardware that needs to impose dependencies.
The embodiment of FIGS. 6A-6E requires that a store be in only one store set at a time. At first this appears to violate the premise that a memory dependence predictor should allow multiple loads to be dependent on the same store. However, an algorithm using the simple hardware of FIGS. 6A-6E while retaining multiple load-store dependency functionality is now described.
When a memory-order violation occurs, entries are created in the SSIT. When neither the load's nor the store's SSID is valid, a new SSID is created and assigned to both instructions. On the other hand, if the load's SSID is valid and the store's is not, the store inherits the load's SSID, and becomes part of the load's store set as in the discussion of FIGS. 6A-E. What happens when the store already has a valid SSID different from the load's SSID has not yet been discussed. Overwriting the store's old SSID effectively removes the store from its old store set and puts the store into a new one. This is the effect of limiting a store to be in only one store set at a time. To govern the decisions made when determining whether to overwrite one valid SSID with another, the preferred embodiment establishes some store-set assignment rules.
Limiting the number of store sets to which a store can belong could create new possibilities for memory-order violations. Multiple loads may cause memory-order violations due to the same store, and since a store can only belong to one store set, a conflict can occur where the loads compete to have the store in their own store set. This can result in very poor behavior, similar to a cache thrash where two loads always cause each other to miss. The following FIGS. 7A-B are illustrative.
In FIG. 7A, two loads 701, 703 have conflicted with different respective stores in the past. Load 701 has conflicted with the three stores having PCs X, Y and Z as specified in its store set 705. Load 703 has conflicted with the two stores having PCs J and K as specified in its store set 707. Assume that store set 705 has an SSID of 1 while store set 707 has an SSID of 2. Now suppose that load 701 causes a memory-order violation when executing out of order with the store having PC J. That store PC (i.e. PC J) should then be added to the load 701's store set 705. However since a store's PC is allowed to only exist in one store set at a time, it is removed from load 703's store set 707.
The next time the second load 703 executes and conflicts with the store at PC J, the load is trapped because no memory dependence is enforced since store PC J is no longer in store set 707. It is apparent that this could result in an oscillation where the two loads 701, 703 take turns trapping and removing store PC J from the other load's store set. To avoid this destructive interference, store sets merge with each other when appropriate. To facilitate this merging, three rules are established for assigning store sets to loads and stores.
Store Set Assignment Rules:
1. When a load-store dependency has been detected by a trap due to memory ordering, if the store instruction which trapped the load is not currently in a store set, the store becomes part of the load's store set.
2. When a load has been trapped due to memory ordering, if the store instruction which trapped the load is currently part of a store set, and the load's store set is empty, the load adopts the store's store set.
3. When a load has been trapped due to memory ordering, if the store instruction which trapped the load is currently part of a store set not associated with the load, and the load's store set is not empty, one of the two store sets is declared the "winner". If the load's store set is the winner, the store trapping the load leaves its old store set and becomes part of the load's store set. If the store's store set is the winner, the load abandons its old store set, and now adopts the store's store set.
Rule 3 alludes to an arbitration algorithm that chooses a "winner" among two store sets. The arbitration algorithm should be one that, when asked to choose a winner among two specific sets, will always choose the same set.
A preferred embodiment chooses a store set based on a convergence algorithm such as a numerical comparison of SSIDs, for example, choosing the store set with the smaller store set identification number. Thus, the store sets will be merged after some constant number of traps. Of course, other converging algorithms may also be used. For example, choosing the store set with the most entries as the winner.
To understand how the store set assignment rules promote dynamic store set merging, refer again to FIGS. 7A-7C. Suppose the first load 701 causes a memory-order violation by executing before store PC J. The conditions for Rule 3 are satisfied: the store involved in the violation is already in a store set and the load's store set is non-empty. Now a "winning" store set must be declared. Assume that store set 705, having the smaller identifier is declared the winner, so that store PC J is removed from store set 707 and placed in store set 705. In the near future, load 703 causes a memory-order violation by executing before store PC J, since it has been removed from its store set 707. Again, the conditions to trigger Rule 3 exist. If store set 707 were declared the winner, the two loads 701, 703 would alternately cause memory-order violations because of store PC J. Therefore, according to Rule 3, store set 705 is selected as the winner again (where 705 is a smaller number than 707). This causes load 703 to adopt the store set 705 of the first load 701 as illustrated in FIG. 7B.
To continue, assume the second load 703 later causes a memory-order violation with store PC K, since store PC K is no longer in the load's designated store set, which is now store set 705. Store PC K is in its own store set 707 (although no load points to it), and the load's 703 current store set 705 is not empty. Again, Rule 3 specifies the winner, and once again to avoid oscillating memory-order violations, store set 705 is chosen, bringing load 703's final conflicting store (PC K) into its adopted store set 705. Now, both loads 701, 703 point to store set 705, and all the stores (PC X, Y, Z, J and K) are in store set 705, as illustrated in FIG. 7C. All further memory-order violations are avoided by this dynamic merging of store sets 705 and 707.
FIG. 8 is a schematic diagram demonstrating how unrelated loads 801, 803 having the same index values point to the same entry 805 in the SSIT 601. As a program runs, the SSIT 601 registers valid SSIDS, creating valid store sets. Every load and store instruction accesses the table 601. In FIG. 8, the two loads, one 801 that has a store set, and one 803 that does not, have a common index pointing to the same SSIT entry 805. This can have a negative impact on performance, potentially causing load-wait mispredictions for loads such as load 803 that are not in danger of committing memory-order violations.
FIG. 9 illustrates the use of tags in an alternate embodiment of the present invention to avoid the above problem. A tag field 901 is provided in the SSIT 601. When an instruction is assigned to a store set, the tag portion 903 of its PC 603 is written into the tag field 901 of the indexed entry 605. When an instruction is fetched, the index portion 905 of its PC 603 indexes into the SSIT 601 to retrieve a store set index 909, as discussed previously. In addition, the tag 907 is retrieved and compared at comparator 905 with the tag portion 903 of the PC 603. If tag 907 and tag portion 903 are equal, then the retrieved store set identifier 909 is valid for the fetched instruction, as indicated by the comparator output 907.
Finally, without a method of invalidating the SSIT 601, all of its entries will eventually become valid, randomly imposing ordering restrictions on whatever program executes in the processor. To avoid this, the valid bits 602 of the SSIT 601 are intermittently or, preferably, periodically cleared, so that the table must retrain. For example, clearing of the valid bits of the SSIT 601 at some large regular interval can be easily implemented with two counters, one that specifies a clearing interval, and the other that sweeps through the SSIT, invalidating entries. Of course, other schemes may be used to clear valid bits 602.
Alternatively, as FIGS. 10A and 10B illustrate, a counter may be appended to each SSIT 601 entry. If false dependencies are incorrectly imposed on certain loads, the counters decrement and eventually invalidate the entry, reducing the number of load-wait mispredictions. This is implemented by appending each SSIT entry with a counter as shown in FIG. 10A, preferably, but not limited to, a two-bit counter 950 having a low bit 952 and a high bit 951, as shown in FIG. 10B. When a store instruction 680 first creates its entry in the SSIT 601, the counter 950 is set to some initial value 953, preferably its maximum value. As long as some threshold is exceeded, preferably indicated by the high bit 951 of the counter 950, the instruction scheduler (not shown), which receives the indication through signal 959, enforces memory dependencies predicted by the SSIT 601 and LFST 609.
The target addresses of a predicted load/store dependence are compared to determine whether there was a load-wait misprediction in which a decision has been made to delay execution of a load based on a false assumption of dependency. If the addresses do not match, there was a load-wait misprediction, and the counter 950 associated with the store is decremented via signal 955. Otherwise the counter is incremented via signal 957. Preferably, these counters 950 are only consulted for store instructions. Of course, instead of using the high bit 951 as an indicator, a comparator may alternatively be used to compare the counter value with some threshold.
The number of store set entries needed is much smaller than the number of entries in the SSIT 601 because store sets can be more effectively shared. If two loads share one store set, it is quite possible that one load's conflicting stores and the other load's conflicting stores are never in the processor at the same time. This means that although one store set identifier is shared, temporally one load and its stores never intersect with the other load and its stores, and therefore no false dependencies are created.
A preferred embodiment of the present invention has 4K entries in the SSIT 601, 128 entries in the LFST 609, and uses cyclic clearing to invalidate the SSIT every million cycles.
A good example of the difficulty in predicting memory dependencies is found in the standard benchmark applu routines "blts" and "buts", both of which contain the following loop:
______________________________________0 do ip = 1, 41 tmp1 = 1.0d+00 / tmat[ip, ip]2 do m = ip+1, 53 tmp = tmp1 * tmat[m, ip]4 do 1 = ip+1, 55 tmat[m, 1] = tmat[m, 1] - tmp * tmat[ip, 1]6 end do7 v(m, i, j, k) = v(m, i, j, k) - v(ip, i, i, k) * tmp8 end do9 end do______________________________________
This triply nested loop creates a scenario where a load and store sometimes conflict. The problem is on line 5. The store instruction that writes tmat[m,1] and the load instruction that reads tmat[ip,1] will sometimes conflict. To see this more clearly, the problem can be reduced to:
______________________________________ do ip = 1, 4 do m = ip+1, 5 do l = ip+1, 5 load tmat[ip, 1] ; PC A store tmat[m 1] ; PC B end do end do end do______________________________________
Multiple iterations of the loop are in-flight simultaneously in the processor, so that multiple instances of the load and store PC are in-flight at the same time. Consider a point in the loop execution when ip equals 3. The inner loops will produce this sequence of the load and store PCS:
______________________________________PCA load tmat (3,4) ip=3, m=4, 1=4 - iter VB store tmat (4,4)A load tmat (3,5) ip=3, m=4, 1=5 - iter WB store tmat (4,5)A load tmat (3,4) ip=3, m=5, 1=4 - iter XB store tmat (5,4)A load tmat (3,5) ip=3, m=5, 1=5 - iter YB store tmat (5,5)A load tmat (4,5) ip=4, m=5, 1=5 - iter ZB store tmat (5,5)______________________________________
Here the load in iteration Z is dependent on the store in iteration W. When those two instructions execute out of order they cause a memory-order violation, and the store at PC B becomes a member of the load's store set. This is unfortunate, because the load will always wait for the most recent iteration of the store before executing. So, the next time this triply nested loop is executed, the second iteration load will wait for the first iteration store, the third iteration load will wait for the second iteration store and so on. Yet, only certain iterations of the load are actually dependent on certain iterations of the store. The preferred store set implementation does not keep track of iteration information. Most of the parallelism in the loop is serialized in hardware, resulting in a severe performance degradation for this loop.
To eliminate this problem, a compiler could fully unroll the triply nested loop. This would create separate PCs for the loads and stores in different iterations. Then the store set memory dependence predictor would allow a load to specify which specific store conflicts with it.
When the CPU recovers from a misspeculation (branch mispredict, jump mispredict, or memory-order violation) the SSIT does not need to be modified. Ideally, the LFST rolls back each entry to the last live store which wrote that entry. Alternatively, simply invalidating aborted store entries in the table is sufficient. As a third, simpler alternative, all store entries in the LFST are invalidated.
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described specifically herein. Such equivalents are intended to be encompassed in the scope of the claims.
For example, although the focus is on memory dependence prediction, the present invention could be extended to propagate data values from stores to dependent loads to increase performance further.
In addition, the present invention can be used to predict non-memory-based dependencies such as register dependencies and the like.
Furthermore, the present invention may also be used to represent sets of items in a direct-mapped table. Other similar uses are in the purview of one skilled in the art based on the foregoing disclosure.
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text:
OLD Taxis!
Taxis in Guayaquil are OLD and DIRTY!!! If you can find one that isn't a 1980 or older Lada, you are exceptionally lucky. With airconditioning? Buy a lottery ticket, because it MUST be your lucky day.
The best way to get a good taxi in Guayaquil is to call one of the many radio taxi services - such as Taxi Amigo, whose number is easy to remember 222-2222 or 233-3333.
Phone: 222-2222 or 233-3333
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Guayaquil have many...
Guayaquil have many international flight, Americain Airlines, Continental, Iberia, KLM, Avianca, Copa, and many more.
Transportation in Guayaquil is not a problem, you will find many taxi on the street or buses. The buses go for 25 cents, a taxi from the airport to downtown will cost you usually 2.50(around)how ever if you take a Taxi from the inside of the airport they will charge you around 4.$ ASK FOR THE PRICE before you get in so you wont have any surprise!
The city's main bus station,...
The city's main bus station, called Terminal Terrestre Jaime Roldos Aguilera, is located 2 KM north of the city center, just beyond the airport. The Station offers an abundance of ticket counters and bus companies. Fixed prices allow you to choose whatever bus company or travel times are most convenient. Some destinies have only one or two bus per day, Is recommended buy your ticket in advance.
Buses are Guayaquil's most efficient and economical form of transportation. Dozens of bus routes run from the city's center to its outskirts but no buses actually run within the center - walking or taxis are your only options. When in doubt, head to Malecón Avenue because the majority of the buses pass along Malecón during their route. In the evening, you are advised to carry limited luggage because petty theft is common.
Ask locals for the going rate and negotiate fares before entering taxis. Taxistas have been hurt by Ecuador's economic crisis as much as everyone else and will occasionally overcharge tourists. Don´t be afraid to get out of the car, there are plenty more taxis waiting to give you a ride.
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