text:
|Publication number
|Publication type
|Application number
|PCT number
|Publication date
|May 17, 2011
|Filing date
|Oct 18, 2006
|Priority date
|Nov 2, 2005
|Fee status
|Also published as
|Publication number
|Tom Waayers, Richard Morren
|Original Assignee
|Nxp B.V.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (20), Non-Patent Citations (6), Referenced by (3), Classifications (7), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention generally relates to testing of semiconductor integrated circuits, and in particular relates to a core test method and apparatus.
One common testing technique for the testing of semiconductor integrated circuits (ICs) is a scan testing technique. This essentially involves launching a test pattern (termed "vector") into the pins of a device package and monitoring an output response at a specific time, dependent on the clock speed of the device. A set of test vectors is used to enable the behaviour of the device under test to be determined. These vectors are designed to enable detection of manufacturing defects in the device.
As the number of transistors used in integrated circuits grows, the ability to reuse integrated circuit designs becomes increasingly important. One important issue concerning the reuse of design functions (termed "cores") is the ability to test these cores without re-engineering the testing methodology, so that test reuse can be implemented as well as design reuse. The testing of System on Chip (SoC) circuits with multiple functional cores also becomes an increasing challenge.
Primarily to address these issues, the IEEE P1500 working group was formed, and has developed a core level solution to facilitate test integration and test reuse. The standard has now been adopted as IEEE STD 1500 and provides a standard interface and a set of rules defining the boundary between a core and the logic external to the core. This boundary is termed a "wrapper", and allows the isolated test of a core with minimum signals that must be routed outside the system on chip structure. The wrapper comprises so-called "wrapper cells" for each functional input and functional output of the core.
The Wrapper Boundary Register WBR comprises a chain of cells 8, each associated with an individual functional input or output of the core. These cells are configured into a scan chain to supply the desired test vectors for the control of the core functional inputs or to shift out the results present on the core functional outputs. The cells of the WBR thus essentially implement a scan test technique by providing a selected test vector to the functional inputs and outputs of the core.
The wrapper 2 has a Wrapper Serial Input (WSI) and a Wrapper Serial Output (WSO), and these communicate with an instruction register, termed Wrapper Instruction Register (WIR) and with the Wrapper Boundary Register (WBR).
The Wrapper Boundary Register WBR controls and observes the ports 4 of the functional core. The cells 8 of the WBR are configured in response to the instructions provided to the wrapper instruction register WIR, and the Wrapper Instruction Register essentially controls the testing process.
In particular, the WIR and WBR are configured to operate in response to control signals which indicate the commands "Select", "Capture", "Shift" and "Update".
A shift comprises the advance of the data in the WBR one storage position closer to the test output (and also the advance of data in the WIR or other register). Thus, the shift commands load the WBR cells with the desired test vector.
A capture comprises the storing of the data present on the functional inputs or outputs of the WBR into the WBR cells.
An update comprises storing of the data within the WBR cell shift storage element, using an additional update storage element.
A transfer comprises the movement of data to the WBR cell shift storage element.
Although not shown in
The Wrapper Instruction Register (WIR) is used to configure the wrapper into a desired mode of operation, determined by the instructions shifted into the WIR. This instruction may be tens or hundreds of bits in length, and can define different test and diagnosis modes of operation. Additional circuitry of the WIR (not shown) is used to interpret the loaded WIR instruction and provide the appropriate control signals to the WBR which controls the interaction with the core.
The wrapper uses the same serial input for the loading of the serial test vectors to be shifted into the WBR cells as for the loading of instruction data, and the SelectWIR signal determines which mode of operation is in use.
The WIR thus decodes loaded instructions and then controls the Wrapper Boundary Register WBR to implement the specified control. The WIR circuitry receives the signals CaptureWR, ShiftWR, UpdateWR and the clock signal WRCK, a reset signal WRSTN signal and the signal SelectWIR, discussed above.
The Wrapper Instruction Register can also control a Wrapper Bypass Register (WBY), which is operable to pass a wrapper serial input (WSI) to the wrapper serial output (WSO) without any interaction with the core. This is in response to a WIR instruction. In addition, an external test can be controlled by the WIR to provide external controllability and observability of the core, and this test involves connecting the Wrapper Boundary Register WBR to the Wrapper Serial Input and Output (WSI and WSO). This enables the loading of customer specified data into the WBR cells.
The Wrapper Instruction Register receives its control input from a Wrapper Serial Control (WSC) input.
The terminals above are from the serial port. The wrapper can also have parallel ports, shown in
This invention relates in particular to the testing of multiple cores surrounded by a wrapper. In this case, a path for the test signals needs to be provided between the multiple cores, so that a selected core or cores can be tested using the test signal path. If one particular core is to be tested, the others need to be bypassed, so that the test vectors can be routed to the desired core.
One way to achieve this is to couple scan chains for different wrappers together in series. For the cores which are not to be tested, a bypass is provided around the internal core scan chain, for example using a single shift register bypass element, which is in parallel with the internal core scan chain.
The bypass element can comprise a single latch element which enables the signal being fed along the pipeline to bypass the internal core scan chain and the WBR cells of the wrapper. One problem with this approach is that the different bypass configurations need to be tested for correct functioning, as part of the overall test procedure. As these bypass configurations represent different internal configurations of the wrapper, it is not typically possible to test the different bypass configurations using a single run of an automatic test pattern generation (ATPG) system. Instead, dedicated tests need to be performed to test the different configurations themselves, before the actual core internal and external tests can be performed.
According to the invention, there is provided a testing circuit for the testing of an integrated circuit core or circuitry external to an integrated circuit core, the testing circuit comprising:
a shift register circuit comprising a plurality of cells, for passing test signals, the cells being arranged as a plurality of banks of cells in series;
a serial input and a serial output for connection to the input and output of the shift register circuit;
a plurality of parallel inputs and outputs, wherein the parallel inputs are for passing test signals to the integrated circuit core for testing of the core,
wherein a plurality of scan chain segments are defined, each between a parallel input and a respective parallel output, the scan chain segments each comprising a bank of cells of the shift register circuit, a core scan chain portion, a first bypass path around the core scan chain portion and a second bypass path around the bank of cells of the shift register circuit,
wherein each scan chain segment further comprises a latching element in series with the bank of cells and the core scan chain portion.
This arrangement essentially uses series elements as part of the bypass mechanism. The bypass paths themselves preferably introduce no delay and can thus comprise a feedforward path around the respective scan chain portion or bank of cells to an output multiplexer.
Thus use of latching elements in series with the core scan chain and shift register cells enables data to be latched between the latching elements while the bypass paths are in use and the circuit is in a test mode. This means that testing of the bypass paths is possible as part of the core internal or external test, and this enables full testing of the core, circuitry external to the core and the wrapper hardware without requiring a dedicated test run for the wrapper bypass structure. Typically one test run will be carried out for core internal test, and one for core external test, and one of these can include the wrapper bypass path testing.
The circuit preferably comprises a first bank of bypass multiplexers which is controllable either to connect integrated circuit core outputs to the multiplexer outputs or to implement the first bypass path.
The circuit preferably comprises a second bank of bypass multiplexers which is controllable either to connect the output of the bank of cells of the shift register circuit to the multiplexer outputs or to implement the second bypass path.
The multiplexers implement zero delay bypass paths (ignoring the signal propagation delay), and the latching elements provide the required latch delay to provide correct timing in a bypass mode
The scan chain segments are preferably connectable in series to define a single pipeline between the serial input and serial output. This pipeline connection enables data to be latched between the latching elements of different scan chain segments to enable the testing of the bypass paths set up between the latching elements.
The testing circuit is preferably operable in a shift mode and in a test mode. The shift mode comprises the shifting of data along each scan chain segment, and the test mode has this shifting of data disabled. The shifting of data between the latching elements is however implemented during this test mode, and this therefore has no influence on the data held in the core scan chain or shift register cells. The test modes may include a core internal test mode and a core external test mode.
During the shift mode in advance of a core internal test mode, the parallel inputs may be coupled to the core scan chain portions and the outputs are coupled to the banks of shift register cells. During the shift mode in advance of a core external test mode, the first bypass path is implemented and the parallel inputs are coupled to the banks of shift register cells.
The circuit is operable during a test cycle of either or both of these test modes to implement the first and second bypass paths, and to shift data between successive latching elements, thereby providing testing of the implemented bypass paths.
The shift register circuit can comprise a Wrapper Boundary Register for an embedded core test architecture, for example an IEEE STD 1500 embedded core test architecture.
The invention also provides an IEEE STD 1500 wrapper comprising:
a testing circuit of the invention, the shift register circuit comprising a Wrapper Boundary Register;
a Wrapper Instruction Register; and
a Wrapper Bypass Register.
The invention also provides an integrated circuit comprising a circuit core and an IEEE STD 1500 wrapper of the invention. The integrated circuit may comprise a plurality of circuit cores, each with an IEEE STD 1500 wrapper of the invention, and a further wrapper around the plurality of wrapped cores.
The invention also provides a method of testing an integrated circuit core or circuitry external to an integrated circuit core and for testing a series of bypass paths of a testing circuit, the method comprising:
operating the testing circuit in a shift mode in which a test vector is shifted into a set of parallel input ports of the testing circuit, the test vector being provided a core scan chain of the integrated circuit core for testing of the core or to a shift register circuit for testing of the circuitry external to the core;
operating the testing circuit in a test mode to implement the testing of the core or the external circuitry,
wherein during the test mode, the core scan chain and shift register circuit are placed in a bypass mode using bypass paths around portions of the core scan chain and portions of the shift register circuit, and the testing circuit is configured to provide a plurality of latching elements and the bypass paths in series between the serial input and output, and wherein data is latched between the latching elements to provide testing of the bypass paths.
This method makes use of the test mode cycle or cycles to perform testing of the bypass paths provided for the core scan chain and shift register of the testing circuit. These bypass paths are required to enable different test modes to be provided and to enable one core to be bypassed within a multiple core arrangement. The testing of the bypass paths can be carried out as part of the core internal or core external test, which can therefore be carried out as a single test pattern procedure.
The shift mode is also used to shift a test result out of a set of parallel output ports of the testing circuit, through the latching elements.
The shift register circuit can comprise a Wrapper Boundary Register for an embedded core test architecture, for example an IEEE STD 1500 embedded core test architecture.
An example of the invention will now be described in detail with reference to the accompanying drawings, in which:
The example of the invention described below provides a wrapper architecture in which the WBR cells are arranged in parallel banks, to support the receipt of parallel data from parallel wrapper ports.
Scan chain segments are defined between each parallel input and a respective parallel output, and the scan chain segments comprise a bank of cells of the shift register circuit, a core scan chain portion, a first bypass path around the core scan chain portion and a second bypass path around the bank of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment has a series latching element, and this provides additional testing capability. In particular, the shifting of data between these latching elements can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.
Before describing the invention in further detail, a more detailed outline of the wrapper structure and operation will be given.
As mentioned above, the Wrapper Boundary Register is formed as a plurality of cells, and
This cell can be configured as an input cell or as an output cell. For an input cell, the hold_inputs/outputs signal is "hold_inputs" and for an output cell, the hold_inputs/outputs signal is "hold_outputs".
These hold signals control the WBR cells, and the hold signals are static, to select between core internal (inward facing) and core interconnect (outward facing) tests. The hold signals are generated in response to the interpretation of the WIR instruction, and are controlled in dependence on the selected test (or diagnostic or application) mode. The application mode essentially comprises the disabling of the wrapper to allow normal functionality of the core.
The cell 20 receives a serial input "si", which is the cell test input "cti". This serial input is clocked to the serial output "so", which is the cell test output "cto" by the flip flop 22 when a shift enable control line "se" is high. This shift enable control signal controls a multiplexer 23. The shift enable control line thus controls shifting of signals along the scan chain. Note that the shift enable control lines "se" are related to the command "shiftWR".
For an input cell, in order to provide a signal to the core, in response to a high hold signal at the control line "hold_inputs", the output of the flip flop 22 is provided to the cell functional output "cfo" through multiplexer 24. This is also fed back to the multiplexer 23, and with the shift enable line low, this signal is fed to the flip flop 22 to maintain the cell functional output stable. Thus, a cell test input signal stored in the flip flop is held on the cell test output. The input cell can also observe the environment external to the core, and route this to the serial output.
For an output cell, a signal can be received from the core at the cell function input, and with the hold_outputs signal low, this can be routed (with shift enable low) to the serial output. Similarly, a cell test input can be routed to the cell functional output.
It can be seen that an input cell can provide a test signal to the core, and an output cell can receive a response from the core, and can also provide an outward facing test signal to the circuitry outside the core. These functions are controlled by the hold signal values, which provide the control of the way the WBR operates.
The serial input "si" is supplied to the "1" input of a multiplexer 30 which is controlled by the shift signal. When the shift signal is high, this serial input is fed to a first flip flop 32, which clocks the input signal to the serial output "so". This provides a serial chain operation.
The output is also fed back to a second multiplexer 34 which implements the capture function. In the absence of a capture command, the output is fed to the "0" input of the multiplexer 30. This maintains the output stable until the next high shift signal, which replaces the input to the multiplexer 30 with the next serial input value.
The serial output is also provided to a third multiplexer 36, and this passes the output to a second flip flop 38 in response to a high update signal. After an update signal, the output of the flip flop 38 is stable, as the output is fed back to the "0" input of the multiplexer 36. Thus, after the update action, the output of the flip flop 38 is stable and stores the value in the flip flop 32. This defines the wrapper instruction register (WIR) output.
The reset signal resets the WIR output, and the application mode is also implemented (effectively disabling the wrapper) during the reset mode of operation.
It can be seen that the functionality of the circuit shown in
The circuit of
This circuit uses the capture signal as an internal test control. When the capture signal goes high, the inverse of the WIR output is supplied to the multiplexer 30, and this in turn is supplied to the flip flop 32 when there is no shift signal input. This inverted WIR output thus can be controlled to propagate through the structure to the WIR output using the update control signal.
As shown, the WIR comprises a series chain of the elements of
This register provides serial loading of data using the WIR serial input ("si") port and the parallel provision of the WIR output, which can comprise a test vector to be applied to the core under test.
However, the architecture also allows testing of the instruction register, in particular to monitor the propagation of 1s and 0s through the serial flip flops and through the capture and shift multiplexers and the propagation of 1s and 0s through the update flip flops through the update multiplexers. The propagation of 1s and 0s through the series scan chain connections between slices can also be monitored using the serial output.
As mentioned above, the WBR cells are controlled to implement inward facing or outward facing tests (using the hold signals). For efficient core based testing, multiple scan chain configurations are needed to support efficient core internal and core external testing.
For example, multiple cores may be contained within a larger wrapper, and the ability to test a subset of the cores is then desirable, and it is known to enable this using parallel bypass elements around each core.
The arrangement of
The internal core scan chain is shown as 62, and this is also represented as a number of blocks. For completeness, a separate memory chain of the internal core is also shown as 64, again represented as a number of blocks.
The internal core scan chains 62, memory chains 64 and the WBR chains 60 are each controlled by a shared shift enable signal "se", which is active during the shifting of data along the pipeline and is inactive during the normal (internal or external) mode test.
Each of the blocks 62, 64, 60 is provided with a multiplexer at its output so that a bypass can be implemented.
The internal core chain blocks 62 each have a multiplexer 72 at their output, and this bank of multiplexers implements an internal core bypass mode, under the control of the signal "internal_bypass". When this bypass signal is low, the multiplexers 72 feed the inputs to the core scan chain blocks 62 directly to the outputs of the multiplexers.
The memory chain blocks 64 each have a multiplexer 74 at their output, and this bank of multiplexers 74 implements a memory bypass mode, under the control of the signal "memory_bypass". When this bypass signal is low, the multiplexers 74 feed the inputs to the memory chain blocks 64 directly to the outputs of the multiplexers.
The WBR cell blocks 60 each have a multiplexer 70 at their output, and this bank of multiplexers implements a WBR bypass mode, under the control of the signal "WBR_bypass". When this bypass signal is low, the multiplexers 70 feed the inputs to the WBR cell blocks 60 directly to the outputs of the multiplexers.
The configuration can also be used to implement a single serial chain between a serial input "si" and a serial output "so", and a further bank of multiplexers 76 is provided for this purpose. This serial chain is of particular interest for a debug operation, in which all data is transported along a serial path, with no internal testing. The multiplexers 76 are controlled by a "cell_concat" control line, which controls the concatenation of the latch cells into a continuous pipeline.
The arrangements of multiplexers enable various bypass configurations to be implemented. However, the correct functioning of these multiplexers and the bypass paths also needs to be tested as part of a test procedure.
The invention provides additional latching elements 80 in series between each parallel input/output pair, wpi and wpo. These latching elements enable both a test function and provide the latching for a bypass mode of operation. They may be considered to be series bypass elements, and they have a simple flip flop latch structure, for forming a link within a sequential scan chain. They introduce a delay of a single clock pulse of the wrapper clock used to clock the latching elements 80.
The elements 80 function as monitoring devices for monitoring the correct operation of the bypass configurations. As they are placed in series with the scan chains, they can be used for monitoring the bypass configuration as part of the core internal or external testing, as will be apparent from the description below. In this way, no additional test configurations are required to enable testing of the bypass multiplexers 72,74,70 and bypass paths.
In the architecture of
The table below shows the different test modes which may be used by the circuit of
scan test
The table above shows the signals applied to the control inputs discussed above.
The test modes comprise a shifting mode (of multiple clock cycles with se=1) to load the test vector, followed by a test cycle (se=0), followed by a further shifting mode (of multiple clock cycles with se=1) to output the test result. The value S is used to represent the value of se, and /S is the logical inverse.
The first row defines the application mode, in which the wrapper is effectively in a transparent mode. The control signals are all low, so there is no shifting of data along the scan chains. Furthermore, the WBR cells are configured (using the hold inputs) so that they are isolated from the internal core and from the external circuitry, and thereby have no influence on the correct functioning of the wrapped core, which can be in normal operation.
The application mode has the same configuration as a bypass mode, in which the wrapper essentially acts to couple the parallel inputs to the parallel outputs. This can be seen from the sixth row of the table, and
The latch elements 80 introduce a delay of one shift cycle, and this single cycle delay is in any case required in the bypass mode to provide stable and reliable timing. Thus, the arrangement does not introduce additional delay to the bypass mode compared to the conventional bypass mechanism in which a delay bypass element is provided in a feedforward path.
The second row defines a core internal test. This involves scanning a test vector into the core scan chain (with se=1), and subsequently with the scan enable low (se=0), the internal test mode is carried out. During the scanning period, the cell_concat signal is low, so that test vectors provided to the parallel inputs wpi are fed into the scan chains. During the scanning operation, the chains 62,64,60 are connected in series so that data is pipelined along the combined scan chain. The memory chains and WBR wrapper cells are connected in the pipeline as control signals are provided to the memory cells and WBR cells as part of the internal test being carried out.
The other control lines are also varied when switching between the shift and test mode, so that all control lines therefore have dynamic values dependent on the value "S".
During the test operation (S=0), the cell_concat signal is brought high so that the scan chain segments are all connected in series. With the bypass paths all set up (the other three control signals internal_bypass, memory_bypass and WBR_bypass are all low), the test elements 80 are effectively connected in series between the serial input and output si, so.
The normal mode test which is carried out during the test mode typically lasts one wrapper clock cycle, so that during the normal mode test, the data present at the test elements 80 shifts one place along the serial chain. In this way, the bypass paths between each adjacent pair of test elements 80 are tested, and the results of this test are obtained when the data is scanned out during the subsequent serial shift mode.
This approach enables testing of the bypass paths and the correct operation of the multiplexers as part of the ATPG test.
By providing appropriate data values at the positions of the test elements 80 when the internal test mode is carried out, the propagation of 1s and 0s through the bypass paths and the multiplexers can be monitored.
The third row of the table shows the same set of conditions, and this is also suitable for testing of an embedded core. In this case, the parallel inputs wpi[0] . . . wpi[N−1] can be used to provide test vectors for dynamic control of the testing process for embedded cores.
The fourth row shows an external test mode, "extest". This mode connects the WBR chains 60 between the parallel inputs and outputs and bypassing the internal core and memory chains. Thus, the signals cell_concat, internal_bypass and memory_bypass are all low, and the WBR_bypass is high.
The fifth row shows a memory scan test, in which the core scan chains and WBR chains are bypassed and the data path is only through the memory chains (and the latching elements 80), as shown in
The bypass mode functions in the same way as the application mode, as mentioned above.
The last row of the table is a debug mode, as shown in
In the table above, the testing of the bypass paths has been explained as implemented during a core (internal) test mode. However, this testing may take place during any of the testing modes, when the shift enable line is low and data is not being shifted along the core, memory or WBR cell chains. The testing of the bypass paths will comprise part of the overall test procedure, and can be implemented at different times.
The configuration described above provides efficient modular test, and enables full testing using standard ATPG.
The architecture above also enables the formation of a serial chain for debug data dumps. When in bypass mode, the architecture presents only a single serial element (the latching element 80) between the parallel inputs and outputs, and this supports efficient data transport to neighbouring cores in multiple core architectures. As demonstrated above, the additional test functionality supplements the other test modes and does not preclude other scan chain configurations. The serial placement of the latching elements with the other scan chain configurations provides the ability to provide complete scan chain and bypass testing with standard ATPG.
In the example above, the memory chains are separate from the core scan chains, but this is only by way of example, and they will often be combined.
Although not shown in the figures, the serial input and output will each be connected to a WBR cell for the monitoring of the data provided to and received from the scan chain during the bypass testing part of the test procedure. The data output from the parallel ports is monitored as part of the test process and this provides monitoring of the data values in the latching elements 80, and thereby enables the correct propagation of data into each latching element which was carried out during the test mode to be verified. However, an additional WBR cell is needed at the serial output "so", so that data leaving the last latching element 80 during the test mode can be monitored. Similarly, the data provided to the first scan chain segment is monitored/controlled by a first WBR cell at the serial input "si".
The clocking of the latching elements will typically use the wrapper clock, and this can be independent of the clock signals used during internal or external test modes. Thus, a first clock signal or set of clock signals may be used within the memory chain and the core chain, and a different clock signal can be used for the shifting of data along the WBR cells. The test elements 80 may be clocked using the same WBR cell clock, or an additional clock signal may be used during the testing of the bypass paths, when data is shifted along successive test elements 80. For example, the wrapper clock may be gated and turned off during the test mode, in which case a different clock signal is needed for the latching elements.
The invention has been described with reference to the IEEE STD 1500 wrapper architecture. However, the invention is applicable more generally to registers used in core testing architectures in which parallel and serial inputs are provided.
The term multiplexer has been used above, and this is simply intended to be interpreted as a controllable switching device, in particular for routing one of many inputs to one or more outputs.
In the description and claims, where one port, terminal or signal is described as being for "connection" to another or "coupled" to another, this does not exclude intermediate elements in the path. For example, in
The term "zero delay" has been used above, and this should be understood as a delay which is insignificant compared to the clock period, and which therefore does not change the functioning of the circuit. Thus, a zero delay bypass path is a connection which will of course have a propagation delay, but the delay is negligible compared to the delay in a subsequent latch, and the bypass path does not therefore introduce a delay which needs to be taken into account, and can therefore be considered to be zero.
Various other modifications will be apparent to those skilled in the art.
|Cited Patent
|Filing date
|Publication date
|Oct 30, 1998
|Jun 5, 2001
|Texas Instruments Incorporated
|Parallel scan distributors and collectors and process of testing integrated circuits
|Nov 4, 1998
|Jan 29, 2002
|Nec Corporation
|Large-scale integrated circuit and method for testing a board of same
|Jul 3, 2001
|Aug 26, 2003
|Texas Instruments Incorporated
|Boundary scan test cell circuit
|Dec 21, 1999
|Sep 2, 2003
|Synopsys Inc.
|Dynamic scan chains and test pattern generation methodologies therefor
|Oct 25, 2002
|Nov 4, 2003
|Texas Instruments Incorporated
|Integrated circuits carrying intellectual property cores and test ports
|Oct 25, 2002
|Nov 2, 2004
|Texas Instruments Incorporated
|IC test cell with memory output connected to input multiplexer
|Sep 17, 2002
|Jan 17, 2006
|Koninklijke Philips Electronics N.V.
|Test arrangement for assemblages of intergrated circuit blocks
|Apr 11, 2002
|May 16, 2006
|Xilinx, Inc.
|Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller
|Jan 26, 2004
|Jul 15, 2008
|Ricoh Company, Ltd.
|Semiconductor integrated circuit and scan test method therefor
|Jan 28, 2004
|Aug 5, 2008
|Nxp B.V.
|Testing of integrated circuits
|Aug 5, 2002
|Dec 9, 2008
|Mitsubishi Denki Kabushiki Kaisha
|Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores
|Jun 27, 2007
|Mar 17, 2009
|Industrial Technology Research Institute
|Wrapper testing circuits and method thereof for system-on-a-chip
|Nov 3, 2003
|May 26, 2009
|Marvell Israel (Misl) Ltd.
|Integrated circuit testing using segmented scan chains
|Jan 13, 2005
|Nov 17, 2009
|Nxp B.V.
|Test access architecture and method of testing a module in an electronic circuit
|Dec 30, 2002
|May 29, 2003
|Whetsel Lee D.
|IC test cell with memory output connected to input multiplexer
|Nov 10, 2003
|Jun 3, 2004
|Whetsel Lee D.
|IP core design supporting user-added scan register option
|Apr 6, 2004
|Oct 7, 2004
|Whetsel Lee D.
|Changing scan cell output signal states with a clock signal
|Jul 10, 2003
|Jan 13, 2005
|International Business Machines Corporation
|Method and apparatus of reducing scan power in the process of unloading and restoring processor content by scan chain partition and disable
|Jun 1, 2005
|Jul 13, 2006
|Industrial Technology Research Institute
|Wrapper testing circuits and method thereof for system-on-a-chip
|Feb 17, 2005
|Feb 7, 2008
|Oussama Laouamri
|Integrated Circuit Chip with Communication Means Enabling Remote Control of Testing Means of Ip Cores of the Integrated Circuit
|DaSilva et al., "Overview of the IEEE PI500 Standard", 2003, ITC International Test Conference, pp. 988-997.
|Dervisoglu, "A Unified DFT Architecture for use with IEEE 1149.1 and VSINIEEE P1500 Compliant Test Access Controllers", Jun. 18-22, 2001, DAC 2001, pp. 53-58.
|Fang et al., "Power-Constrained Embedded Memory BIST Architecture", 2003, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 451-458.
|Li, et al., "Hierarchical Test Scheme for System-on-Chip Designs", Mar. 4-8, 2002, Design, Automation and Test in Europe Conference and Exhibition (DATE'02), pp. 486-490.
|Marinissen, E. J; et al "Infrastructure for Modular SOC Testing" Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, Oct. 3, 2004, pp. 671-678.
|Vermeulen, B; et al "IEEE 1149.1-Complaint Access Architecture for Multiple Core Debug on Digital System Chips" Proceedings International Test Conference 2002. ITC 2002, Oct. 7, 2002, pp. 55-63.
|Citing Patent
|Filing date
|Publication date
|Oct 31, 2011
|Oct 30, 2012
|Apple Inc.
|Dynamic scan chain grouping
|Dec 22, 2009
|Oct 22, 2013
|Nxp B.V.
|Testing circuit and method
|Jun 23, 2011
|Vladimir Aleksandar Zivkovic
|Testing Circuit and Method
|U.S. Classification
|714/729, 714/742, 714/727, 714/724
|International Classification
|Cooperative Classification
|European Classification
|Apr 30, 2008
Owner name: NXP B.V., NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WAAYERS, TOM;MORREN, RICHARD;REEL/FRAME:020878/0464
Effective date: 20080425
|Dec 24, 2014
|Maintenance fee reminder mailed
|May 17, 2015
|Lapse for failure to pay maintenance fees
|Jul 7, 2015
|Expired due to failure to pay maintenance fee
Effective date: 20150517
|Mar 7, 2016
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND
Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058
Effective date: 20160218


text:
I'm saving all my scrapbooking for this weekend during the crop (can't wait!!!), so I decided to work on more cards while Kayson napped and watched his cartoons this morning. These are some I finished lastnight and this morning:
"you add something special to the mix"
I went ahead and used that quote because this card will be going to my sister-in-law. I thought it'd be a fun inlaws card. The mixer is the one my friend cut me from the new Kitchens cart, the letters are from Sans Serif at 1/2 inch. (great font for tiny lettering btw) I stickled the letters. The "lace" is just white paper cut with my Martha Stewart punch.
"hello friend" is from Wild Card, telephone is from the Kitchen cartridge
"abundance" is cut from Jasmine. The cornacopia (sp?) is from the Speaking of Fall cartridge. I used a pen to create the fake "stitching" around the image to immitate the paper.
"wish"...I'll use this one as a birthday card. I loooove how I did this chandelier....I took the "flower" cut on Home Accents and trimmed off the top and bottom and it resembled a chandelier to me! YAY for finding a fun, new chandelier cut. I then cut three lowercase "i" from Sans Serif font for the "candles". The leftovers from the flower I cut off are the pieces I used for the envelope.
"Beary Christmas". Bear and present are from Joys of the Season, the title is Lyrical Letters.
I love this one!! The flamingo is from Life's a Beach. I've been wanting to cut my Christmas flamingo since I got the cartridge, so had fun with it! The "happy Christmas" is from the Christmas Solutions cartridge. I used some boa feathers for the tail...lol.
the angel is from Joys of the Season. I stickled the paper where it says Peace on Earth. You can't see it so well from the photo, but it looks better IRL.
And them I need a lot of QUICK thank you notes for people who gave things to Kayson on his birthday, so I threw together two sets:
train is from New Arrivals, "thank you" is from Alphalicious.
the lizard is from Life's a Beach. The "thanks" is DonJuan.
Thanks for looking! I am going to miss card making when I start back at work tomorrow. Atleast it'll give you girls a break!

subset: commoncrawl


text:
What does counselling help with?
You can come to us about any worries or concerns; these may include:
- Family problems
- Feeling lonely and misunderstood
- Racism, sexism, bullying
- Feeling depressed or confused
- Abuse
- Lack of confidence
- Loss and grief
- Worries about food and weight, sex, drugs or alcohol
Youth Talk offers a wide variety of services including:
One-to-one counselling
Group work
Information services
You may come just once, or you may want regular appointments over a period of time.FIND OUT MORE
Related Links
Parents & Carers
Supporting your child in their choice to seek help through counselling can be one way of helping them back to health.FIND OUT MORE
Friends & Fundraising
This isn't just about fundraising – it is also about networking, winning the hearts and minds in this powerful and wealthy district.FIND OUT MORE
If you are concerned about a young person between the ages of 13-25, then talking to Youth Talk staff could help.FIND OUT MORE
NewsVIEW ALL
Walking out of Darkness - the Youth Talk team
Many thanks to all those who completed the Walking out of Darkness event (organised by CLASP) on Saturday, 14 May 2016. Over £1,201 was raised for Youth Talk. Thank you all for your valuable support and for rai...
St Albans Cathedral Mission Giving Fund
Youth Talk was awarded a grant of £1,000 from the St Albans Cathedral Mission Giving Fund. We are most grateful for this continuing support.
Marks and Spencer Charity of the Year - St Albans' branch
Youth Talk was recently presented with a cheque for £4,004 by the St Albans' branch of Marks and Spencer. The staff at Marks and Spencer voted for Youth Talk to be their 2015-16 charity of the year. Some of the staff have giv...


text:
Firing up: Favorable regulation and accelerating construction activity will boost demand
The Firestop Contractors market research report provides key industry analysis and industry statistics, measures market size, analyzes current and future industry trends and shows market share for the industry's largest companies. IBISWorld publishes the largest collection of industry reports so you can see an industry's supply chain, economic drivers and key buyers and markets.
The Firestop Contractors industry has experienced strong growth over the five years to 2015, thanks to increasing levels of private investments in nonresidential construction, one of the industry's primary downstream markets. Industry revenue is expected to continue growing during the next five years, as continued accommodative lending rates benefit firestopcontractors. Moreover, increased investment in industrial infrastructure will ultimately result in higher demand for firestopconstruction projects.... purchase to read more
Based on data from the Firestop Contractors International Association, IBISWorld estimates that the most heavily concentrated regions of industry establishments are the Southeast, Mid-Atlantic and West. Because this industry specializes in fireproofing design, installation, inspection, maintenance and management for commercial buildings, industry locations tend to cluster in areas of high population densities and commercial activity. By state, California, Texas and New York comprise the top-three spots by number of firestopping establishments. Large commercial hubs in Los Angeles, New York City and Dallas help generate ongoing demand for installation and inspection services... purchase to read more
Contractors in this industry primarily construct and maintain firestops, which are passive fire-protection systems used to seal openings and joints in wall and floor assemblies. Firestops include fire and smoke dampers as well as fire doors. The industry does not provide fireproof insulation services.
Industry Definition
Main Activities
Similar Industries
Additional Resources
Executive Summary
Key External Drivers
Current Performance
Industry Outlook
Industry Life Cycle
Supply Chain
Products & Services
Major Markets
Business Locations
Competitive Landscape
Market Share Concentration
Key Success Factors
Cost Structure Benchmarks
Barriers to Entry
Capital Intensity
Industry Data
Annual Change
Key Ratios


text:
The pleasure to visit burgundy(France)with good wine , dinner and the pleasure to play golf on wonderfull golfcourses.....
A taste of the real Burgundy off the tourist route, tasting in small family owned cellars, meeting the locals & enjoying the best wine & local cuisine that Burgundy has to offer! Cellars Visits, Truffle Hunt, Cheese Tasting, Cooking Classes & more!
Gourmet Cuisine and Cooking Classes in the beautiful Loire Valley
Enjoy an unique insight into a French country kitchen. Learn to cook, with Sinéad, the French way in half an day or indeed over a period of 3/6 days. Tailor made courses on request.Tell us what you want and we'll do our best to facilitate your needs
Designed for people who love and appreciate fine wine and food, Gourmet On Tour offers the ultimate in gourmet holidays. Choose from over 80 cooking courses and wine tours in Italy, France, Spain, UK, Morocco, Asia and the US.
F&W is a Tour designer specializing in Culinary vacations and wine Tours. Our small group Tours feature in -depth exploration of a particular region, the kind that takes you to the real place you are visiting. All inclusive
Luxury self catering villa near Les Arcs in France. Large summer villa for families and big groups. Self catering accommodation.
With over 25 years experience we specialise in hotel, inn-to-inn or lodge based active holidays - walking, cycling, boating or barging, bike & barging, sailing, horse riding and more in most areas of Europe, Australia or New Zealand.
Luxury cruise on the beautiful Burgundy canal, through a region rich in history, art and breathtaking countryside. Gourmet food, famous wines, open bar, heated pool, bicycles. 2-6 passengers, 3 suites, Charters. 3 or 6 nights. English speaking crew.
Select your destination in Roanne France. Browse thousands of listings for accommodations, adventures, tours and travel services.


text:
Arizona Wildcats
Arizona freshmen shine in annual Red-Blue Game
The Arizona Wildcats hosted their annual Red-Blue Game on Saturday, and the UA's stellar freshman class stole the show in a sold-out McKale Center.
Top recruit Aaron Gordon put on an athletic display in the dunk contest, winning over Nick Johnson with a 360 between-the-legs dunk, then put on an all-around performance during the game with 12 points, 13 rebounds, three assists and two steals.
"The word unique is at the forefront when you describe Aaron as a player," head coach Sean Miller said. "You saw how he can pass. With someone of his size and athleticism, it might be one of the best things he does."
Fellow freshman Rondae Hollis-Jefferson tied for a team-high with 18 points during the actual scrimmage, which consisted of two 15-minute halves. Sophomore center Kaleb Tarczewski also scored 18, and sophomore forward Brandon Ashley scored 14. Each of Arizona's expected contributors in the front-court scored in double figures.
"I think we could have as many as five players in double figures," Miller said. "That balance is going to make us more difficult to beat. You don't have that one player who takes all the shots."
Check out a pair of highlight videos released by Arizona Athletics below:
Most Popular
Wildcats Audio
Greg Byrne, University of Arizona Athletic Director
Monday June 27
Byrne talks about UA's unlikely run to the College World Series championship game.
Bickley Blast
Monday June 27
Is Arizona, not Arizona State, the real "baseball school"?
Vinny Joe Trivia - Pac-12 in the NBA Draft
Thursday June 23
Vince Marotta takes on Pac-12 analyst Casey Jacobsen in Pac-12 NBA Draft trivia
Kurt Warner, NFL Network analyst and Cardinals great
Thursday June 9
Warner talks 2016 Cardinals + HS athletes getting a fair shot in college camps.
4-8-16 The Sports Kabob with Jarrett Carlen
Friday April 8
Topics include Star Wars, UConn women + The Masters. It's sports news skewered.


text:
When I need a limousine for Entertainer's that I book into the Milwaukee area. I only trust one Company and that's Badger State Limousine. They have been our number one choice for not only their professional service, but also for their ethical business practices. I personally have met the owner of Badger State Limousine and I have seen his credentials. This company came highly recomended by other concert promoters in the Wisconsin area. I never have to worry when I use this company I know they will do the job with out a problem. In the Entertainment industry things just have to be handled in a very discreet and professional manner, and the people over at Badger State limousine understand these issues. We also like the fact that this company offers drivers that are trained body guards, which makes our clients feel safe and secure, and keeps us from having to hire outside security personnel. I just want to personally thank Badger State Limousine for taking such great care of our clients
Brewer's Hill Go Airport Connection
1. Go Airport Connection - CLOSED
5140 S 3rd StMilwaukee, WI 53207
From Business: Go Airport Connection, founded in 1983, offers door-to-door shuttle and executive car transportation services linking southeastern Wisconsin with Milwaukee and Chic…
2. Go Airport Connection - CLOSED
this service is great. the drivers are very nice.... but the company treats their employees poorly. most people assume that the drivers earn a…
3. Go Riteway Transportation Group
Milwaukee, WI 53202
4. GO Riteway Transportation Group
6970 S 6th StOak Creek, WI 53154
Showing1-4 of 4results
Needed to book transportation to the airport for relatives that were visiting from out of town, the company that would be taking them to the airport HAD to be on time because they only had one shot at getting out of here or they were screwed. Some friends said they had used this company for many years and they never let them down so we ordered a cab for them at 3:30am on Christmas Day. At exactly 3:20am on Christmas morning there they were in the driveway, ready to go (what a relief)!. They said the driver was very helpful and friendly and got them safely to the airport with time to spare. We would unconditionally recommend this company without hesitation to anyone that is concerned about having someone show up on time for the airport.
I called Airport Service to book a ride to and from the airport for my elderly parents, on the day of the reservation they pulled up in their driveway 5 minutes early and loaded all their luggage for them and assisted them carefully into the cab and proceeded to the airport in a timely and safe fashion. He even took their luggage into the airport for them and then explained what door he would pick them up at upon their return. They called him from the airport and within 3 minutes he was right where he said he would be got them and their luggage in and got them back home. Their rates seemed very reasonable considering the high service level, would use again and recommend them to anyone looking for a safe clean and reasonable ride.


text:
Is this restaurant good for special occasions?
Is this restaurant romantic?
Is this restaurant good for business meetings?
Does this restaurant serve dinner?
Does this restaurant serve lunch?
Is this restaurant wheelchair accessible?
Is this restaurant family-friendly?
Is this restaurant good for brunch?
Does this restaurant serve breakfast?
Does this restaurant offer takeout or food to go?
Thanks for helping!
Best in Vigo for fish and Galicean food, the ambiance is nice and the restaurant is new with a great kitchen
I fell in love with this resto as soon as I walked in. We had a rez for 20.30 (which is when the place opens for dinner service) and were shown to a good table on the small mezzanine area at the back. We were hoping for Paella but it wasn't on the menu this time ~ so chef made...
Vigo is described as one of the seafood capitals of Europe, certainly Spain. It gets my vote from my two experiences at this lovely, understated restaurant. I was lucky enough to eat twice in this super restaurant specialising in fish offering an a la carte menu plus a fabulous "suggested specials menu". Dishes i ate included Octopus with potatoes and...
This restaurant came well recommended for its high quality sea food, so we made reservations for 3 the day before. The place is nicely decorated, reception by the staff nice, but a bit too 'touristy' friendly, which made me feel a bit uneasy. On the table we found the menu in Spanish, handwritten in a little notebook. which the waiter...
Own or manage this property? Claim your listing for free to respond to reviews, update your profile and much more.


text:
From Publishers Weekly
Bob is a flower, an angry flower. Joined by Stumpy the branch, the forlorn Love-Bot and a host of targets strip-mined from politics and popular culture, he's out to let everyone know that angry can be zany, if not exactly funny. The setup is surreal comedy gold, promising just enough Bloom County and Zippy the Pinhead to make for a great underground comic. Unfortunately, Bob (who stars in a weekly print and Web comic) has already sold out, and much of the book seems to have been hastily assembled. Occasional strips, such as Bob asking God for a sign of His existence or Bob's near-death experience, show the character's potential, but overall Notley may be more concerned with achieving wackiness than tightly constructed jokes or trenchant observations. A 28-page Pure Action insert feels like little more than filler to round out the book's page count. Notley's art is inconsistent, ranging from clean and tight to rushed and sloppy. Not polished enough for prime time, but not angry enough for the underground, Bob sort of languishes in the middle. This collection will likely appeal to existing fans, without drawing in many new ones. (June)
Copyright © Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Copyright © Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
From Booklist
Notley's syndicated Bob the Angry Flower exemplifies the new science-fiction comics. Instead of rocketing around the galaxies, it generally stays on terra firma and lets the aliens come to it. It features robots, especially the lugubrious author's alter ego, Lovebot, and, getting brainy for a change, quantum phenomena, as when Bob, instead of just chopping a "spunky crippled kid" up with an ax, whacks him with a "quantum waveform decollapser" that renders the annoying child into innumerable, identical, possible spunky crippled kids. Trenchant references are made to highbrow fantasy (Kafka) and sf (Brave New World), but Notley is obviously most inspired by 1950s "sci-fi" flickers and their progeny of giant reptile/bug/thing attack yarns (though the big critter that most excites him is the already-big-enough bear; see the long, wordless story in the center of the book, "Pure Action"). And he's incensed by the Bush administration. Bob is pretty transparently another Notley alter ego----the main one--yet he also seems an ambulatory bud from The Little Shop of Horrors' Audrey. Energetically drawn, top-drawer madness. Ray Olson
Copyright © American Library Association. All rights reserved
Copyright © American Library Association. All rights reserved


text:
Hi! I have an issue on the display. When i click on any of the categories, the posts don't line up nicely in the manner. I have slider and showroom appearing duplicates at one time. Can anyone tell me what's the problem here?
My website link: [NSFW] http://www.yourlovings.com
Your help will be truly appreciated.


text:
No dogs allowed? Not always so in some Washington stores.
Email subscribers across the country recently received a message from BarkBox on "dog-friendly chain stores." The list included several area retailers, including Marshalls, Lowe's, Jo-Ann Fabric and Craft, Michaels, Petco and some local restaurants.
You must login to view the full content on this page.
Or, use your linked account:


text:
Although this area is a work in progress, we are slowly adding blogs for each classroom. This provides a space for individual teachers to communicate about their curriculum and the daily activity in their class. See what we're up to:
Aug10Wedall-day Cloud Club DeadlineCloud Club DeadlineAug 10 all-dayClud Club is an extra-curricular activity for students in Grades 6/7/8. This deadline is for ordering tickets for the Sound of Music + Phantom of the Opera. For more details see the sign up link below.Aug15Monall-day Teacher Work DayTeacher Work DayAug 15 all-dayAug16Tueall-day Teacher Work DayTeacher Work DayAug 16 all-dayAug17Wedall-day New Students Only: Primary + Low...New Students Only: Primary + Low...Aug 17 all-dayThis day is for students who are new to McGuffey or new to their classroom in PreKindergarten through Grade 3. A detailed list will be provided closer to the start of school. All Grades 4-8 students begin this day.


text:
Hexapod - Fun with Matlab (work in progress)
simulation of a hexapod in matlab,
work in progress
for more projects, visit http://retardokiddo.blogspot.com/
By Gonzik @ Wed, 2011-10-12 12:11
Great project. Any chance
Great project. Any chance you could share the MATLAB code?
By xochitl @ Mon, 2012-02-27 15:56
Your project is amazingcould
Your project is amazing
could you share the code in matlab, i would like to make an hexapod robot


text:
Getting Old Without Getting AnxiousInformative and full of hope, Getting Old Without GettingAnxious assists older people and their caregivers in overcoming one of the more crippling and misunderstood human afflictions: anxiety. Geriatric psychiatrist and bestselling author of The 36-Hour Day Dr. Peter V. Rabins explains how the many changes that occur as a person ages can trigger severe andlife-altering anxiety, often destroying
Hans Brinker or the Silver SkatesHans Brinker or The Silver Skates was published in 1865 and received more reviews than any other children's book that year. Today it continues to delight countless readers with its story of a virtuous family who inspires us all to have the courage to pursue our dreams.
Theology Questions Everyone Asks
Christian Faith in Plain LanguageEveryone has questions about God and what matters most in life. When we ask those questions, we are asking about theology. Isnt talk about God really a guessing game? What good is the Old Testament? How can we have free will if God controls everything? The virgin birth. Really? What does an earthquake say about God? Is the Holy Spirit still at work in churches today? What did Jesus think about
Listen to Me: Writing Life into MeaningAn inspirational guide to charting your inner landscape through personal writing.Why write out of our lives? What can it do for us? How can sharing our stories connect us with others? Acclaimed novelist and essayist Lynn Lauber chronicles her journey as a writer and longtime teacher at creative writing programs around the country. She explores how writing—both fiction and creative nonfiction—has
The Untold Story of America's 21st Century ShakersThis book takes a look at the faith, philosophy, and way of life of the country's one remaining Shaker community. Lauber explores their spiritual and daily lives by weaving together proprietary Shaker quotations, interviews, and photographs. The result is a book that pierces many misconceptions, most notably that the Shakers and their faith are dead. Lauber places the topics of faith, community,
Safety of Computer Control Systems: Proceedings of the IFAC Workshop, Stuttgart, Federal Republic of Germany, 16-18 May 1979Safety of Computer Control Systems is a collection of papers from the Proceedings of the IFAC Workshop, held in Stuttgart, Germany on May 16-18, 1979. This book discusses the inherent problems in the hardware and software application of computerized control to automated systems safeguarding human life, property, and the environment. The papers discuss more specific concerns, such as railway
The Successful Caregiver's GuideYou may be among the tens of millions of Americans who provide care for your parent — or you may be among the ten of millions who will. So many children are caught unprepared when physical and mental health declines in aging parents. Life cannot readily prepare you to furnish excellent eldercare while balancing the demands on your time. This book provides practical tips, realistic guidance,
Caregiver's Guide for CanadiansOne in five Canadians are now providing eldercare to a parent in need, and as baby-boomers age, this number is likely to grow. What do you do when your mother or father grows old? It's the natural course of life, but so many children of aging parents are unprepared. When a parent's health begins to fail, an adult child is left scrambling to find help, to balance their time, and to cope. The
The Untold Inside Story of the 2008 Championship SeasonRelive one of the most memorable seasons in the Phillies' storied 126-year history, as broadcaster Gary Matthews takes you into the clubhouse, the dugout, and onto the field, giving fans an inside look at the 2008 Major League season. The book includes details of the pivotal offseason trade for closer Brad Lidge, how they managed to withstand their midseason slide, and the late-season rally in
T&T Clark Companion to the Doctrine of SinThe T&T Clark Companion to the Doctrine of Sin provides a comprehensive treatment of the doctrine of sin. The Companion includes an examination of the biblical and rabbinic accounts of sin, and it provides accounts of sin and its effects offered by key theologians throughout Christian history. It also explores debates surrounding the implications of sin for various doctrines, including God,


text:
Abstract:For the past decade EPA has been in the process of developing numerous requirements applicable to design and permitting of facilities intended to ensure proper management of wet weather flows. These requirements have been issued in a number of contexts and have, at times, been subject to widely varying interpretation across the country. These actions include:
Issuance of various combined sewer overflow policies;
Development of regulations to require elimination of sanitary sewer overflows;
Enforcement actions against municipal entities interpreting various NPDES regulations adopted under different circumstances;
Objections to state program permits;
Informal guidance to Regional Offices; and
Regional Office initiatives.
The purpose of this paper is to review the major inconsistencies in current program implementation, evaluate the proper application of the applicable federal regulations and permit approaches and to recommend broadly, how communities with SSO and CSO related flows should approach state and federal agencies in resolving these matters.
Document Type: Research Article
DOI: http://dx.doi.org/10.2175/193864701790860470
Publication date: January 1, 2001
More about this publication?
- Proceedings of the Water Environment Federation is an archive of papers published in the proceedings of the annual Water Environment Federation® Technical Exhibition and Conference (WEFTEC® ) and specialty conferences held since the year 2000. These proceedings are not peer reviewed. WEF Members: Sign in (right panel) with your IngentaConnect user name and password to receive complimentary access.
- Subscribe to this Title
- Membership Information
- About WEF Proceedings
- WEFTEC Conference Information
- Ingenta Connect is not responsible for the content or availability of external websites


text:
I spent two nights here on a tour and the hotel room was adequate but required some arguing at reception to get things fixed. There is a large surface with a mirror above and also a TV but you can sit at the table with plenty of space and good lighting. Initially the controller for the aircon didn't work.
At reception when I asked to get it fixed I was told to come back later but I refused. Then I was given the run around, send to the barman who sent me back to reception until eventually I got them together. Again I was told to go away and refused. Then the barman insisted that the reception man changed the batteries but he said no. I offered to put them in myself and eventually he gave me the key to an unoccupied room and suggested I change rooms. Instead, I swapped the controllers and suggested he make a note that the empty room now had no working aircon.
The shower attachment in the room was falling off the wall and in any case the bath was raised which meant anyone over six feet tall such as me, had to duck down to get wet all over.
All the staff are keen to say "Can I help you?" but then say "You need to talk to..." instead of themselves going and doing the talking for you.
If you accept that it's a bit rough and ready in the rooms then fine but the external appearance is that it's quite plush. In fact, they're not spending the money on the necessary maintenance.
- Reservation Options:
- TripAdvisor is proud to partner with Expedia, Hotels.com, Booking.com, Travelocity and Priceline so you can book your Hotel Sofia reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.
- Also Known As:
- Sofia Hotel Fes