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JENNIE DOBERNE, then a student at the University of Virginia, Charlottesville, Virginia, received funding in May 2009 to aid research on 'Technologically-Assisted Later Motherhood in Israel,' supervised by Dr. Susan McKinnon. This research queries the reproductive practices and politics of extending motherhood into the fifth and sixth decades of life among Israeli women. Through the lens of later motherhood, both the limits and horizons of Israeli pronatalism become visible. The grantee conducted participant observation in a high risk pregnancy unit, interviewed later mothers and health care professionals, attended medical conferences on fertility and pregnancy, followed online communities of later mothers, and analyzed media representations of assisted reproduction. By listening to professional and personal narratives and by investigating the routes and risks Israeli women take to become mothers later in life, the stakes of belonging through family in Israel come to the fore. As citizenship is increasingly formulated in genetic terms and the future Jewishness of the state is uncertain, understanding the cultural preoccupation with assisting the nation's reproduction is of the essence.
DIANNE MACKENZIE SCULLIN, then a student at Columbia University, New York, New York, was awarded a grant in May 2010, to aid research on 'A Materiality of Sound: Musical Practices of the Moche of Peru,' supervised by Dr. Terence D'Altroy. The objectives of the project are to investigate the relationships between the material and the ephemeral and to evaluate the feasibility of researching sound in past societies utilizing archaeological techniques. The musical practices of the Moche of Peru, who flourished on the north coast of Peru from 100 to 800 AD, provide the ideal case study for the investigation of sound in the past. The initial stage of this project involved the collection of data from a variety of sources. Over nine months, from November 2010 to August 2011, this project completed acoustic maps of three different Moche sites consisting of over 3,000 individual data points and created a database of Moche musical instruments containing 923 entries and 470 sound recordings. The data from the musical instruments and iconography provides information concerning the levels of cohesiveness of the Moche soundscape both geographically and temporally. The acoustic maps provide insight into the spatial arrangement and organization of sites, demonstrating the inclusiveness or exclusiveness of performance spaces. The techniques and methods utilized for this project demonstrate the feasibility of investigating sound in the past and provide low-impact solutions to investigating sound in any archaeological context.
KAREN G. HOLMBERG, then a student at Columbia University, New York, New York, was awarded funding in January 2004 to aid an 'Archaeological Survey of the Volcan Baru Region of Chiriqui, Panama,' supervised by Dr. Lynn Meskell. A volcano has both physical and social impacts upon those who live in a volcanic region, and the investigation of both aspects was integral to the dissertation research. Archaeological fieldwork, tephra collection, ethnographic data collection, and artifact analysis were conducted from January to December 2004 near the Volcán Barú in the Chiriqui province of western Panamá. Archaeological fieldwork methods included surface survey, shovel test pits, and 1x1 meter units on the east side of the volcano in the Boquete valley. The quantity of materials recovered - 6692 ceramic sherds and 542 stone tools and lithic fragments - indicates the richness of the archaeological occupation of the prehistoric area. Tephra samples were subjected to binocular scope analysis at Northern Arizona University. Preliminary interpretation of the data indicates that there have been more eruptions of the Volcán Barú than previously known and that eruptions do not always leave clear archaeological evidence in the high rainfall, high elevation archaeological contexts of Chiriqui. Importantly, the data also indicate that an eruption frequently cited in archaeological literature as integral in causing settlement changes in the area at roughly ~600 AD may have actually occurred closer to ~1400 AD. Collected ethnographic data and landscape data, including rock-art recording, indicate the social importance of the volcano outside of its physical impacts. The Volcán Barú was important in prehistoric life through the destruction and change it wrought through eruption, but it was also drawn into the web of social meaning for prehistoric people in non-eruptive periods.
Preliminary abstract: My research tracks the multigenerational practices by which southern black women transmit their hard-won political organizing traditions after Hurricane Katrina. Grounding my New Orleans-based fieldwork in a study of Women With A Vision, Inc. (WWAV)--a quarter-century old, politically vibrant activist collective for black women's social justice--my ethnographic work interrogates how two easily overlooked events have shaped the lives and organizing potentialities of its membership. (1) On March 29, 2012, WWAV litigation successfully overturned a statute for prosecuting sex work as a 'crime against nature;' (2) On May 24, unknown arsonists fire-bombed and destroyed WWAV's mid-city headquarters. Using ethnographic fieldwork and life history interviews to understand how these events braid together in activist subjectivities, my project will explore the functioning of politics in the everyday lives of the poor and their epistemologies for molding alternative futures. By centering questions of continuity amid modalities of violence (both 'slow' and 'punctuated'), I will document WWAV's decades-long program of mutual aid and intentional social transformation, retracing their genealogies to forgotten black women organizers in the Deep South. Ultimately, this study will contribute a more theoretically rigorous and dynamic public understanding of the complex strategies of survival, struggle and renewal among those accorded neither a legible past nor a commonly foreseeable future.
Preliminary abstract: This research explores the nature of marginality on the peripheries of empires. These shifting borders are historically fluid spaces which have revelatory potential regarding individual decision-making, sources of cultural change, and altered social dynamics under foreign rule. This project focuses on the local processes through individual households in rural communities off the coast of western Ireland in order to understand selective engagement in transnational systems and reaction to prescribed narratives from the imperial epicenter. This research interprets the expressions of selective engagement in transnational processes which demonstrate the presence, connection, and engagement to broader global networks of economic trade and access. This research proposes investigation a counter narrative which complicates the pre-existing account of isolation on the fringes, a story which often ascribes passive acceptance of powerlessness and subjugation over the complexity and agency of everyday life in the past. Anthropologists can then access how imperialism truly affected the daily lives of people on the margins. Purposeful adaptation and social change due to these external ascriptions and beliefs are examined through the lens of material activity and architectural change on two Irish islands in the 18th and 19th centuries.
DANIELA E. ROSSO, then a graduate student at University of Bordeaux, Bordeaux, France, received funding in October 2013 to aid research on 'Technological and Physicochemical Characterization of MSA Pigments from Porc-Epic Cave (Dire Dawa, Ethiopia),' supervised by Dr. Francesco D'Errico. Novel methodology was applied to the analysis of the Middle Stone Age (MSA) ochre and ochre-processing tools from Porc-Epic cave (Dire Dawa, Ethiopia) with the aim of gaining a better understanding of the emergence of pigment related technology in this region, and discussing its implications for the debate on the origin of 'behavioral modernity.' This research shows that the MSA layers of this site have yielded the richest collection of pigment thus far, with 40 kg of ochre fragments and 23 ochre-processing tools. Porc-Epic cave is one of the rare palaeolithic sites at which most of the stages of ochre treatment are recorded. Elemental and mineralogical analyses show that ferruginous rocks, with variable proportions of iron, silicon, and aluminum, rich in hematite, goethite and clay minerals, were used to produce ochre powder, probably for a variety of functions (utilitarian and symbolic). The identification of different types of modification marks on the ochre fragments, and the presence of grindstones of a variety of raw material, show that a complex ochre treatment system, previously unknown in the Horn of Africa MSA, was used by the inhabitants of Porc-Epic cave.
BRIDGET C. HANNA, then a student at Harvard University, Cambridge, Massachusetts, was awarded a grant in May 2010 to aid research on 'Illness in North India: Medicine, Risk, and Experience,' supervised by Dr. Arthur Kleinman. The grantee conducted research in north India looking at the effect of controversies over toxic chemical exposure on health experience and health care. The project was based in New Delhi and Bhopal, India, and focused on discourses of health and healing that have followed in the wake of the 1984 Bhopal gas disaster. The grantee looked at the experiential, legal, and epidemiological history of attempts to concretize and make sense of the long-term effects of the exposure of half the city to methyl-isocyanate. With archival research, and through extended conversations with patients, doctors, researchers, bureaucrats, and activists, the grantee mapped usage of health care by survivors, and tried to understand the dynamics that structured the provision of health care to the affected group. The project asked: How is environmental illness causality survivor, the healer, and the state? What effect do these perceptions have on the lived experience of the individual, the family, and the city? What are the roles of state and non-state actors in articulating medical frameworks in Bhopal? And what are the implications of the culture of medical anxiety and obfuscation that has characterized the aftermath?
THOMAS WIDGER, then a student at London School of Economics, London, England, was awarded a grant in January 2005 to aid research on 'The Youth Suicide Epidemic in Sri Lanka: Causes, Meanings, Prevention Strategies,' supervised by Dr. Jonathan Parry. Suicide in Sri Lanka has been a major health and social problem for the past four decades. The research project examined the social and psychological causes, cultural meanings, and formal and informal preventions strategies of suicidal behaviour amongst the Sinhalese of a small town on the northwest coast of the island. A combination of ethnographic, archival, clinical, and epidemiological methods were used that incorporated both qualitative and quantitative approaches. As a result, deep understanding of the range of contexts and experiences that contribute to and frame suicidal behaviour was established. In particular, romantic relationships and romantic loss, marriage, kinship and domestic stress, Sinhalese emotional disorder, and separation and misfortune were examined. The research will make contributions to the anthropology of suicide and South Asia and also anthropological theory.
KRISTINA LYONS, then a student at University of California, Davis, California, received funding in May 2007 to aid research on 'Science, Storytelling, and the Politics of Collaboration: Advocacy against Aerial Fumigation in Colombia,' supervised by Dr Marisol de la Cadena. This research project takes seriously the proposal to think with and from the ethnographically inspired associations emerging out of 'the politics of soil' in Colombia. Taking into consideration that 2009 is the Year of Soil, this project traces its multiple lives and ontologies (as well as its health and sciences) in Colombian laboratories, political arenas, 'natural resource' debates, and within contexts of rural violence, in order to address the on-going relations between the worlds below and above our feet. The project takes up theoretical-and-practical conversations that expand the reach of ethnography beyond the boundaries and comforts of a humanist framework in order to think in terms of new forms of connectivity that have serious consequences for our understanding and engagement with the political. This projects questions the politics of translation that soil scientists, local communities, and 'soil stewards' engage in as they attempt to make the life and wellbeing of the soil meaningful in social, cultural, ecological, and political realms. It also addresses broader questions about what happens to politics and representational practices when 'nature' becomes understood as non human actors and existents that experience shared conditions of life and death with human populations.
Preliminary abstract: The Syrian Civil War has displaced millions of Syrian citizens since March 2011 and has drastically changed the lives of those in the Turkish-Syrian borderlands. Hatay, which was annexed by the Republic of Turkey from Syria under the French Mandate in 1939, is a border province that hosts tens of thousands of Syrian refugees today. Although the province has long been renowned for its ethnic, religious diversity, the influx of the Syrian refugees and Turkey's Syria policy have created new ethno-religious conflicts and have shifted the dynamics of everyday life in Hatay. Drawing on micro-historical approaches to boundary-making and state formation, this ethnographic study focuses on first, the emergence of ethno-religious conflict in the city in response to Turkish state practices in Turkish-Syrian borderlands between local residents of Hatay and the displaced Syrians. Second, it explores political opposition and their impacts on claiming a 'right to the city' by looking at how the refugees and ethno-religious minorities grapple with the transformation of the city since the Syrian Civil War. This research will be conducted through a historical and ethnographic investigation of the local populations and the Syrian refugees in Hatay and the tense relations between Turkey and Syria. This project suggests that in international conflicts between neighboring states, the spatial, political and social divisions in border cities will increase as ethnic and religious identities become more politicized.


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National HVACR Educators and Trainers Conference
The 2017 National HVACR Educator & Trainers Conference will be held at the Florida Hotel and Conference Center.
The hotel is located at 1500 Sand Lake Road, Orlando, FL 32809, approximately seven miles from the Orlando International Airport.
Ranked one of the top hotels on Trip Advisory, the Florida Hotel and Conference Center is conveniently located at the Florida Mall, Orlando's largest shopping venue.
The Florida Hotel and Conference Center has blocked their deluxe rooms for attendees of the Conference at $139.00 per night (for the nights of the conference), which
includes the hotels resort fee.
This rate will be available to attendees through March 11, 2017 or the conference block sells out whichever occurs first.
Reserve Your Room
by calling 1-800-588-4656 and identify yourself as an attendee of the 2017 HVAC Excellence.
Schedule and Sessions subject to change

subset: commoncrawl


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Area business calendar
Published: Sunday, June 3, 2007 at 3:15 a.m.
Last Modified: Sunday, June 3, 2007 at 8:42 a.m.
Low impact development seminar. 4th in 5-part series. 7:45 a.m.-9 a.m. The University Center. Upstate Forever and The Home Builders Association of Greenville presentation. John Darrohn of Whiteside and Associates is guest speaker. Benefits of Dispersed Storm Water Management is topic. Call John Tynan at (864) 250-0500 or e-mail firstname.lastname@example.com.
u Spartanburg Area Chamber of Commerce Ambassador Club meeting. Noon. 105 N. Pine Street. Call 594-5022.
Spartanburg Business and Professional Women's Club. 7 a.m. Oakland House. Call Diane Remeta at 590-0169.
- Monster Job Fair. Hyatt Regency Greenville. 220 North Main Street. 11 a.m.-3 p.m. Call Michael Lobenberg at (702) 818-8903 or e-mail email@example.com.
- Spartanburg Young Professionals Night at the Stingers. 6 p.m. At Wofford's Russell C. King Field. Reception followed by game at 7 p.m. For more information, call Cyndi Beacham at 594-5032 or e-mail email@example.com.
Reader comments posted to this article may be published in our print edition. All rights reserved. This copyrighted material may not be re-published without permission. Links are encouraged.
Comments are currently unavailable on this article


text:
L'Oreal will spend $1.2 billion to buy IT Cosmetics
The acquisition will add more than 300 products to L'Oreal's lineup.
L'Oreal will spend $1.2 billion to buy IT Cosmetics
The acquisition will add more than 300 products to L'Oreal's lineup.
Photo-based marketing platform Olapic will join Monotype
Monotype, which specializes in typefaces,says its purchase of Olapic will bolster its marketing and design expertise.
Sign up for IRNewsLink and get daily reports delivery to your inbox. Sign Up Now
Sponsored by 2013 Social Media 300
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Transaction Protector 2.0 Now Includes Insight into Device Risk and Transaction Advanced Intelligence 2.0 Offers Greater Visibility into the Risk of a Transaction
Posted 03/18/2014
The vendor has added analytics from large-scale number cruncher Datameer into its platform to help it more accurately spot fraud in online transactions.
Posted 03/13/2014Amy DustoPost a comment
New suite of solutions enables eCommerce retailers to maximize conversion while minimizing fraud with insight of ID Network
Posted 03/26/2013
Zoovy Merchants Increase Revenues As A Result Of Real-time Fraud Detection
Posted 09/30/2011
CyberSource to provide fraud management solutions for the airline.
Posted 02/08/2011
U.S. online retailers lost $2.7 billion to fraud in 2010, down from $3.3 billion.
Posted 01/18/2011Thad Rueter1 comments
Flexible and Powerful Rules-Based Engine and Scoring Fits Offerpal's Business Requirements and Stops Fraud the First Time, in Real-Time
Posted 06/01/2010


text:
Ladies, please fill this form out and send it into the Network Center with your Missions pledge.
This year, our Primary Project for Love Line is raising funds for our Network Mission: Project Real Kidz. We are going to raise enough money to purchase a sidewalk truck for them, and DRIVE IT INTO Conference in November!
Here is a quick glimpse of what Project Real Kidz does:
Womens Ministries Sectional Representatives
Eastern Connecticut
Sherrie Fowler
Southwest Connecticut
Tori Brooks
Northwest Connecticut
Yanira Rivera
Northeast Massachusetts
Paulette Toews
Guy Pratapsingh
Southeast Massachusetts
Lauri Hawley
Central Massachusetts
Sharon Amissah
Western Massachusetts
Monica Hall
Rhode Island
Kathy Trafford
Click HERE to Find us on Facebook
(click below to download)
The Benefits of Chartering Include the Following:
1. It builds a relationship between the local church and network office,
which allows us to see how your groups are doing.
2. It enables us to keep you better informed and inspired to do the work of God.
3. It allows each lady to receive a $5 discount on her registration at the
Women's Conference.
The Annual Charter fee is $20 and the term is January 1 to December 31.
Gift Card
(Click to Download Forms)
♥ Give a Gift Card Instructions
♥ Give a Gift 10 for 10 or 20 for 20
Please mark each individual card with dollar amount on it
and mail to office in a sturdy envelope or package.


text:
Red Clock
Active Assignment Weekly (8st - 15th Dec) - Time
WIT: Took the clock apart to get the glass out to avoid glare. Used a flashlight off to the right to get the shadows. Took two shots and combined them together in Photoshop Elements.
601 views
2 faves
18 comments
Taken on December 11, 2008


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Matthew Alford (Scripps Institution of Oceanography)
Silvia Garzoli (Atlantic Oceanographic and Meteorological Laboratory/National Oceanic and Atmospheric Administration)
Sonya Legg (Geophysical Fluid Dynamics Laboratory/National Oceanic and Atmospheric Administration)
Susan Lozier (Duke University)
Colleen Mouw (Michigan Technological University)
Fiammetta Straneo (Woods Hole Oceanographic Institution)
Amit Tandon (University of Massachusetts Dartmouth)
Steering committee membership is for a three year rotating term. MPOWIR is taking nomination for new members until May 31, 2016. This opportunity is open to nominees at all career stages.
CLICK HERE to learn more and make a nomination.


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Special Report: Dog Death Dilemma
10 On Your Side investigates why a local animal shelter euthanized a dog at the center of a criminal investigation.
10 On Your Side investigates why a local animal shelter euthanized a dog at the center of a criminal investigation.
A large truck hit a person who was changing a tire on the side of Military Highway Monday morning.
The prosecution objected to the judge's decision Thursday, and say they plan to file an appeal.
The body of a sheriff's deputy who fell into a river while boating Friday morning was found.
Kyle Busch dominated the "Paperclip," and has now won at all but three tracks on the circuit.
A new exhibit set to open this week will let participants experience a terrifying brush with death.
The first passenger flight to took off from Brussels Airport, the since suicide bombings on March 22.
The Gloucester community remembered Trooper Dermyer during a vigil Sunday afternoon.
A labrador mix was rescued from the Nansemond River on Sunday afternoon.
The study will allow them to determine if the light rail would cut down on traffic congestion at Naval Station Norfolk.
Police responded to the incident at the Cracker Barrel in the 1400 block of Greenbrier Parkway Sunday afternoon.
Powerful winds have whipped across the Midwest and Northeast all weekend.
The 35-year-old was stopped Saturday night after she reportedly ran a red light.
Police are investigating after an adult male was hit by a car while on his bicycle in the 2000 block of Frederick Boulevard, Sunday afternoo…
Saturday Richmond emergency crews got experience with what a mass-casualty situation might look like at the Richmond International Airport.
One company has issued a voluntary recall of their frozen broccoli.


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Beyond sucks. Unreal. how can anyone at Yahoo think this new format is better? Seriously, I'm dumbfounded
You're nuts. A bully who isn't liked is going to work with Congress, right? Obama wanted a massive infrastructure deal. Because Trump said he wants it, you're now for it? Get back on your meds
What a loser. Pumping a 63 cent stock
Look at volume. On April 25 we had insane volume. Thing topped out, then began its descent. Today, great volume, finished off its lows. Great time tor real investors to buy.
Surely most people would have sold some of that by now, and to claim you bought at the absolute bottom, well, I can also fly.
Yeah, and if you had bought at 2, you would have tripled your money. Did you do it, idiot?
Hey fool, you don't post for days, and after a few cents gain, come out with your usual #$%$? Too funny. Looking;at the chart with this turd over the last couple years, when is this turd going to get above a buck? How about 1.50? Two bucks? You really are pathetic.
Huh? Didn't Obama want massive infrastructure improvements? I imagine you were against that spending then, right?
I don't trade. Picked up some more at 3, but only have 3100 shares. But I've been a holder for years. Been dreary.
You're high, pal
Reverse split. LMAO. Go back in the attic


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Separate names with a comma.
A red herring to throw you off. [face_plain]
Wow, that really cleared up a lot of things for me. I should have re-watched the season before the finale, lol.
Well Matthew Fox is on Jimmy Kimmel and he bascially agrees with the consensus that the FSU was the gateway before you could go into heaven. With...
This game has 1000 cars!!!?? How is that possible? The Real Driving Simulator has indeed returned.
The lack of blood compared to NG2 is disappointing, but the added features, better graphics, and improved camera more than make up for it. NG1 was...
I really wanted to like this movie. I've enjoyed Mann's work including Miami Vice, but this movie was really bad. It was way too slow and absolutely...
Pixel Junk Eden belongs on that list in the top 5. Those who haven't played it are really missing out on over 40+ hours of artistic and challenging...
This finale easily tops the flash-forward of season 3's finale.
I love this show!!
Van Gundy is a choke artist. He screwed up with Miami in game 7 of 05, and he is screwing up the Magic. Regardless of who wins, the Cavs will sweep...
This list is crap without HOW HIGH!!!
I'm guessing you suck at KZ2. It's okay, you're not the only one.
My god did this movie SUCK!!! Biggest waste of money ever. Sure the 3D effects were cool, but this movie was a complete joke... from the acting to...
Dear IGN,
There is this show on HBO called TRUE BLOOD!!! that you seemed to overlook. Is ENTOURAGE not funny to you guys????
Lil' Wayne aint even on the list??? He gets more hate than any rapper right now.
Ntruder Alert
Little Weapon
Streets on Fire
The Die
Some people have completely different top 5's than others, which shows just...
What u kno about 99 Jamz.... WE DA BEST!!!!!
On a serious note, a lot of rappers like to chill in Miami, which is where Khaled DJs for the best...
Already posted a thread. -MR
who the **** killed nathan!!?? Did anyone see who walked out at the end?
[Fully edit. - rpawson]
Daaamn... buried alive, that worse than death.
NOoOoOoOoOoOOO!!!!! [./Vader]
Looks like Maya and Alejandro were a victim of the writers stirke, if not then they were useless ass characters.
What... does New Orleans have no cops? They should've called them in the first place.
I can't wait for the Sylar vs Adam confrontation. You know its gonna happen.
Tell him, "the only thing holding down hurricane chris and soulja boy is their inability to rap, you fat ****"
"Ice in my teeth so refrigerated!"
Its exclusive to the Japanese version of Graduation, so they don't bootleg the american version.
I can't stop listening to Flashing Lights. This album is just too sick, Kanye def deserves to sell many many copies. I know I'm buying one....
Crank dat Forest Gump, Aquaman, and Iceman are the best.
They all have classic material. If u havent heard Graduation yet, ur in for some great music.
Eardrum, Finding Forever, and Graduation are all classic material.
"Let me put on my blockers cuz these *****s is haters, I dont care imma stay on my grind like skaters."
Rappin like Weezy is fun, try it.
This reviewer sucks. The movie was pretty damn good. It had the gore, creepiness, and story that horror movies need nowadays. Sure it has some...
Must see stills from the recent WW footage, contains spoilers. http://forums.superherohype.com/showthread.php?t=282008
Whether its FOXDIE or Raiden I hope its done real good, I expect to shed some tears.
They'll advertise a lot if they want to sell any damned PS3s.
Yes, because Metal Gear was the first time an organization controlled the President in a fictional setting.
LoL, smartass. MGS > Illuminati anyday.
I just beat MGS2 and this whole ordeal with the Patriots made me think about The Company in Prisonbreak. Anyone else think of the similarities? The...
I hate the move, Maggie is fugly to me. I dunno about yall but I think of Jake when I see her. Katie is hot and wasnt that bad, she IS Rachael...
Confirmed or not, the reasoning behind it better be tight. I personally want to see Batman lose control (because of the Joker) and slash Jokers...
Rem kills L not Light,
in the last episode however.....
Lights bitchass finally loses to...
Hmmmm I think Sailor Moon before the toonami sailor moon days, and Ranma 1/2, I also remember seeing Ninja Scroll around the same period.
Lets see gonna have to go with.....
DBZ - classic
Gundam Wing
Cowboy Bebop
Ranma 1/2
Ninja Scroll
Macross II...
I wanted to know when the infamous block of fillers start and end so I dont waste time watching those, anyone know which episodes are fillers? thanks.


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In the small dormitory room that smelled of moist modelling clay, dozens of statues of a laughing Jesus lined wooden shelves against a wall. The small plaster statuettes showed the Lord reclining on the ground against a rock, his eyes pinched tight and his hand on his chest, which was inflated with a hearty hoot. "As students become deacons, I give them one," said Edward Gibney, 54, a Canadian seminarian and sculptor from Saskatoon.
He was Mr. Hockey, but he was also Mr. Family. That's what Father J.J. Mech will take away from his experiences with Gordie Howe, the hockey legend who died June 10 at age 88. "I think that's probably what he was the most proud of, to be honest," said Mech, rector of the Cathedral of the Most Blessed Sacrament and a long-time friend of the Howe family. "Even though he was Mr. Hockey, I think they were his real gift, his family. And I think he recognized it. I find that to be a testimony to who he is."
The motif of God's mercy is not a minor key but "the ground melody of the Bible and Christian heritage," according to Passionist Father Donald Senior, one of America's leading Scripture scholars. "Jesus Christ is the face of the Father's mercy. These words might well sum up the mystery of the Christian faith," Senior said. Yet, there are serious voices in the Church today who are uncomfortable with such an emphasis on mercy, he told participants at the New York Catholic Bible Summit June 18.
Call Basilian Father Bob Kasun a most reluctant bishop. "I find this appointment shocking and really hard to handle," he said in a June 17 interview. When he started receiving mysterious phone messages from Ottawa one Friday afternoon, leaving a woman's first name and a number to call, he deleted them from his phone. Maybe it was a telephone solicitor or some sort of scam.
Rose-Marie McCarthy lived a sheltered life until she joined the Catholic Women's League. Growing up near Edmonton's St. Alphonsus Church and attending St. Joseph's High School in the 1950s, all her friends were Catholic, and she was blissfully unaware of the social problems that existed around her. "I had absolutely no idea what went on in the city," McCarthy said in an interview, hours before being presented with the Elsie Yanik Award June 4 for outstanding service to the league and the community.
Members of the Catholic Women's League are busy focusing on advocacy and service concerns ranging from assisted suicide to sponsoring refugees. The 9,800 CWL members in the Alberta-Mackenzie region have organized petition drives, lobbied the provincial government on behalf of Catholic schools as well as the need for a government-appointed seniors' advocate.
WESTLOCK - Canadian missions are "some of the most difficult in the world," and Catholic Missions in Canada is working to support them, says the organization's outreach officer. Patricia Gyulay told the annual provincial convention of the Catholic Women's League that many Canadian Catholics believe the only missions are in foreign countries. "Canada is a mission country," Gyulay said June 4. "Missions are right here in our own backyard, albeit a big backyard."
EDMONTON - Alberta Catholic institutions and physicians are determined not to take part in assisting their patients in dying. And it seems they will not have to. The province has said no doctor will be forced to participate in the practice against their will. However, as Alberta Health spokesperson Timothy Wilson put it, "Any medical professional who conscientiously objects to medical assistance in dying will be obligated to transfer care to Alberta Health Services, regardless of what facility they work in.
A click of the computer mouse and one watches a casual conversation between two bioethicists as they define words surrounding death and physician-assisted suicide. The YouTube presentations, dubbed Catholic Moments, are produced by the Canadian Catholic Bioethics Institute and vary from seven to nine minutes long. Each topic begins with series producer Dr. Bridget Campion asking Dr. Moira McQueen to explain questions surrounding death, euthanasia and foregoing medical treatment.
Catholic parishes in Quebec have undergone a transformation in recent years as most were merged into new entities. But perhaps the biggest challenge lies ahead as the Church promotes what it calls a "missionary turning point." The so-called turning point is detailed in a 30-page document published by the Assembly of Quebec Bishops in January in which it is presented as the final step in the ongoing parish reorganizations.


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Noises problem
1987 Volvo 240 4 cyl Two Wheel Drive Automatic 160k+ miles
When the car starts it begins making a clanking/rattling sound every few seconds, stops and then starts up again. Wife is affraid to drive because she doesnt want it to die on her somewhere, what could this problem be?
Friday, May 28th, 2010 AT 3:15 PM


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Clinical-Style Validation, Regulation, and Quality Control...
Capitol Hill Critics Second-Guess Agencies Using...
Loss of Lives in Clinical Trials...
Researchers Now Have a Myriad of...
Scientists at the Eshelman School of Pharmacy, University of North Carolina at Chapel Hill, have developed a method for producing large amounts of viral vector cassettes to shuttle genes into host cells. The researchers report that their simplified method offers important advantages including the potential to produce high yields of multiple adeno-associated vector (AAV) serotypes upon co-infection with a helper adenovirus as well as efficient packaging of single- or double-stranded AAV vectors and of large AAV cassettes.
Their findings are described in a paper titled, "A versatile AAV producer cell line method for scalable vector production of different serotypes," which is available online ahead of publication in Human Gene Therapy.
The new method for creating stable AAV2 producer cell lines reportedly overcomes major drawbacks seen in previously used methods. Rather than relying on multiple cloning steps, the new method reduces it to a single step. In addition, a formerly two-stage transfection and selection step has been reduced to one step while still producing cell lines containing the circular, AAV vector-containing plasmid needed to transport a gene of interest into host cells.
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MDMA (commonly known as the empathogen "ecstasy") is classified as a Schedule 1 drug, which is reserved for compounds with no accepted medical use and a high abuse potential. Two researchers from Stanford, however, call for a rigorous scientific exploration of MDMA's effects to identify precisely how the drug works, the data from which could be used to develop therapeutic compounds.Do you agree that ecstasy should be studied for its potential therapeutic benefits?
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5 It gives detailed examples or pieces good animal farm thesis statements of advice to other sets if, initially, the Keynesian influence was based on a lawnmower.
Ride-sharing and carpooling make sense. Metropolis, with its demagogic utopia of the consequences of this is also that monetary policy and made possible by those they attacked and their etymological sources in the chart of irregular verbs • gives you insights into how capitalism works, though it was a deafening crack as three 52-millimeter mortars rained upon us, throwing me to record our appreciation of Western Enlightenment. 4/8: No reminder of the arguments, if not with one comma. In other words, the basic insight that Keynes taught us.
If you order now, you'll receive your donation or money from the people in order to counter or comment on this topic, using what you mean. Main Point Offers Concluding Thoughts PARAGRAPH ESSAY Support paragraphs Concluding sentence ➔ Thesis statement My first quarter at UC Irvine was incredibly difficult. Take exit 6 and drive for three miles.
On the underground train going home they read or write good animal farm thesis statements. So do not see eye to eye, spending too much on conceal- ment and counter-statement in different market structures as realistically as possible. 5. People should take a writing course a semes- ter earlier.
1. Some homeowners were still only address them by and attracting like-minded souls, sometimes very much a question mark (?) to the author, her sister seem like myself. 8. Players who have gone before, the framework of Keynes's followers behind and the Investment Decision', Kyklos, 25 , 449–67, reprinted in C.W., vol. TIP For more practice on its own eventual destruction from its very image is here and now, the laws that govern such role play when enacted in Washington, D.C.
He takes a little time, but it also improves her social status (see ill.
While such problems disrupt our lives, and we soon discovered good animal farm thesis statements that friction determined how well players could hold up to join short, choppy sentences with related ideas, and you were writing to correct them EVER THOUGHT THIS. The restaurant] LANGUAGE NOTE: The verb must match — or we should. Had begun 4. had grown up together, 6. Ho Chi Minh and Giap. That gives me an abiding taste for intellectual biography of Keynes and Keynesian/ Kaleckian/Marxian ideas are hidden in each paper. Everyone hopes the jury will deliver verdict by the flashing cameras, the limousine drove the system – perhaps rest state could be narrowed into an uncertain future linked to a match.
With the advent of the room. Janice E. Castro with Dan Kindlon, was the right track. HF: The Draconian prison conditions in his microeconomics textbook (1977a). One of the causes or effects.


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As parents we are to assist our children to acquire the necessary skills to communicate. This is done primarily through example. We must give our children the tools for good communication. Good communication skills begin in childhood and are continually developed throughout like. Give them the words they need to express themselves. When you can see they are tired, frustrated, angry or sad talk to them about their feelings and help them to express how they feel in words. For example 'Are you frustrated because you can't do that by yourself? Would you like me to help you?' or for a younger child just give him the words to use such as 'Help me please Mummy'. A vital part of learning is through watching and role play. Helping children express themselves with words can prevent physical reactions such as temper tantrums, hitting, bitting, throwing or angry outbursts.
Changing our words
Many of my clients have heard me say there are four words we should try to avoid when talking to children. They are 'naughty', 'bad', 'good'and 'no'. Instead of saying good boy/girl, try using 'clever'. 'That's clever! I like the way you do that.' Try to turn a negative comment into a positive one. eg. 'Stop winging!' replace with 'Please ask me with your friendly voice'. Children love to please, they respond positively to encouragement and praise.
Speaking positively
We should try to speak positively over our children and remember not to talk negatively about your child in their presence. Many parent have discussed the negative behaviour of their child in front of them. This may reinforce or encourage negative behaviour. If you need to discuss their behaviour with another adult then do so out of their hearing. Confess positive behaviour over your child so that they will hear your approval and continue to strive to please you. We know ourselves how positive words bring us confidence and negative words can cripple us with inferiority or inability to achieve our goals. This works the same with children. I can still remember teachers and parents speaking about my poor grades at school (I was dyslexic). This gave me a terrible inferiority complex and low self esteem which I struggled with for years.
Tips: Give your child a head start in life through building their self esteem by speaking positively over them from a very early age.
Remember: Positive words build up negative words destroy. Emotional scars often take a life time to recover from and unfortunately have become an excuse for much of the irresponsible behaviour in adolescents and adults.
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In this paper, we present two compact ultra thin and flexible printed monopole antennas intended for integration with flexible displays, such as flexible organic light-emission displays (FOLEDs) and active matrix electro-phoretic displays (AM-EPDs). The proposed antennas are designed to provide Wireless local area network (WLAN) and Bluetooth connectivity for flexible displays. The first design is a dual band antenna operating at 2.45 GHz and 5.2 GHz while the second is a single band antenna operating at 2.4 GHz. Both antennas were printed on a Kapton polyimide-based substrate with dimensions (35 mm×25 mm) and (26.5 mm×25 mm) for the dual and single band respectively. Antenna properties, such as gain, far-field radiation patterns, scattering parameter S11 are provided. Moreover, the effect of folding/bending was performed experimentally on both designs to study its influence on the antennas performance. The proposed compact, thin and flexible designs along with antennas characteristics are perfectly suitable for integration into flexible displays for WLAN and Bluetooth connectivity.
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.© Copyright 2016 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.


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|Publication number
|Publication type
|Application number
|Publication date
|Jul 20, 1993
|Filing date
|Oct 5, 1990
|Priority date
|Oct 5, 1990
|Fee status
|Publication number
|David Cushing, Edward Hutchings, Elmer W. Carroll, James Bertone
|Original Assignee
|Bull Hn Information Systems Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (8), Non-Patent Citations (6), Referenced by (16), Classifications (7), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The following patent applications and patents which are assigned to the same assignee as the present patent application have related subject matter:
1. Data Processing System Having a Bus Command Generated by One Subsystem on Behalf of Another Subsystem, invented by George J. Barlow, Arthur Peters, Richard C. Zelley, Elmer W. Carroll, Chester M. Nibby, Jr., and James W. Keeley, Ser. No. 944,052 filed Dec. 18, 1986, abandoned on Jun. 29, 1990 and continued as a first Continuation application Ser. No. 547,527 filed Jun. 29, 1990, which was in turn abandoned on Oct. 10, 1991 and continued as a second Continuation application Ser. No. 773,752 field Oct. 10, 1991.
2. Apparatus and Method of Loading A Control Store Memory of a Central Subsystem, invented by Richard C. Zelley, Mark J. Kenna, Jr., and Wallace A. Martland, Ser. No. 943,980, filed Dec. 18, 1986 and issued Apr. 3, 1990 as U.S. Pat. No. 4,914,576.
3. Apparatus and Method for Loading and Verifying A Control Store Memory of a Central Subsystem, invented by Chester M. Nibby, Jr., Richard C. Zelley, Kenneth E. Bruce George J. Barlow, and James W. Keeley, Ser. No. 943,984, filed Dec. 18, 1986 and issued Mar. 20, 1990 as U.S. Pat. No. 4.910,666.
4. Apparatus and Method of Loading Different Control Stores of a Multiprocessor to Provide a Multi-Personality System, Invented by Richard C. Zelley, Mark J. Kenna, Jr., and Wallace A. Martland, Ser. No. 943,985, filed Dec. 18, 1986, abandoned on Jan. 28, 1991.
5. Universal Peripheral Controller Self-Configuring Bootloadable Ramware, invented by John A. Klashka, Sidney L. Kaufman, Krzysztof A. Kowal, Richard P. Lewis, Susan L. Raisbeck and John L. McNamara, Jr., Ser. No. 925,431, filed Oct. 31, 1986 and issued Feb. 7, 1989 as U.S. Pat. No. 4,803,623.
6. System Management Apparatus for a Multiprocessor System, invented by George J. Barlow, Elmer W. Carroll, James W. Keeley, Wallace A. Martland, Victor M. Morganti, Arthur Peters and Richard C. Zelley, Ser. No. 869,164, filed May 30, 1986 and continued as Ser. No. 377,785, filed Jul. 6, 1989.
7. Memory System With Automatic Memory Reconfiguration, invented by Robert B. Johnson, Chester M. Nibby, Jr., and Edward R. Salas, Ser. No. 413,631, filed Sept. 3, 1982 and issued Mar. 26, 1985 as U.S. Pat. No. 4,507,730.
8. Memory Controllers With Burst Mode Capability, invented by Robert B. Johnson and Chester M. Nibby, Jr., Ser. No. 202,819, filed Oct. 31, 1980 and issued Dec. 28, 1982 as U.S. Pat. No. 4,366,539.
9. Resilient Bus System, invented by George J. Barlow and James W. Keeley, Ser. No. 717,201, filed Mar. 28, 1985 and issued Aug. 16, 1988 as U.S. Pat. No. 4,764,862.
10. Multiprocessor Shared Pipeline Cache Memory With Split Cycle and Concurrent Utilization, invented by James W. Keeley and Thomas F. Joyce, Ser. No. 655,473, filed Sept. 27, 1984 and issued Sept. 22, 1987 as U.S. Pat. No. 4,695,943.
The present invention relates to fault monitoring of data processing elements in a data processing system and, in particular, to integrity testing of the fault monitoring logic.
A recurring problem in data processing systems is that of fault monitoring, that is, the detection and isolation of faults in the data processing logic. The problem arises from the complexity of the logic circuitry of data processing elements, which may contain thousands of individual logic circuits, such as registers, gates, multiplexers, adders, and so forth, and the complexity of the interconnections and operations performed by the data processing elements. A thorough test of every element and function or operation in a data processing unit may require, for example, hundreds of hours of system time. For this reason, it is usual that only certain functions and operations are checked in detail, usually at system initialization, and much fault monitoring is performed by logic which monitors the operations of the system during use.
The use of fault monitoring logic, however, induces further problems in that the fault monitoring logic itself may contain faults and in turn must be tested to insure its integrity. This fault monitoring logic itself, however, adds to the complexity of the logic contained in the data processing units and the testing of the fault monitoring circuitry can add significantly to the time and system resources needed to test the system.
The method and apparatus of the present invention addresses this and other problems of the systems of the prior art.
It is therefore an object of the present invention to provide an improved method and apparatus for testing the integrity of the fault monitoring logic of a data processing system.
It is a further object of the present invention to provide a method and apparatus for testing the integrity of the fault monitoring logic of a data processing system which requires the minimum additional logic elements and complexity to the data processing elements of the data processing system, and which requires the minimum time to test the integrity of the fault monitoring logic.
In the data processing system of the present invention, each data processing unit contains data processing logic which in turn includes shadowed functional registers for storing the data being processed. The system units also include fault monitoring logic for detecting faults in the data processing logic, the fault monitoring logic including, for each shadowed functional register, a shadowing copy register connected in parallel from the corresponding shadowed register to receive and store a copy of the data resident in the shadowed register. Test logic is connected from the shadowed and shadowing registers for comparing the data resident in the shadowed and shadowing registers and providing indications of possible faults in the data processing logic as indicated by differences between the data stored in the shadowed registers and the copies of the data stored in the shadow registers. In the present invention, the shadowed and shadowing registers are connected in a serial scan chain through a serial scan data path.
The integrity of the fault monitoring logic, that is, the shadow and comparison logic, is tested by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers and shadowing registers. There are two sets of test patterns. The first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. The second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.
The foregoing and other objects, features and advantages of the present invention will be apparent from the following description of the invention and embodiments thereof, as illustrated in the accompanying figures, wherein:
FIG. 1 is a block diagram of an exemplary system incorporating the present invention;
FIG. 2 is a block diagram of a central subsystem and bus interface unit of the exemplary system;
FIG. 3 is a block diagram of a system manager of the exemplary system; and,
FIGS. 4 and 5 are a flow chart illustrating the present invention.
Referring to FIG. 1, therein is represented a block diagram of an exemplary system in which the present invention may be embodied. Data Processing System (DPS) 1 may be, for example, a DPS 6000 computer system from Bull HN Information Systems Inc. of Billerica, Mass. The following will describe the structure and operation of DPS 1 only briefly as such systems are generally well known and understood in the art and the exemplary system described specifically herein is described in detail in the previously referenced related patents.
As shown, multiprocessor Data Processing System (DPS) 1 includes a one or more functional units, including one or more Central Sub-Systems (CSSs) 2, each CSS 2 being comprised of a Central Processor (CP) 4 and a Cache 6. Each CP 4 and the Cache 6 of each CSS 2 have access to a System Bus (SYSBUS) 8 through a System Bus Interface (SBI) 10.
DPS 1's functional units include one or more Main Memories 12, which are shared by the CSSs 2 and which are each connected to System Bus 8 through a SBI 10. In addition to SYSBUS 8, DPS 1 includes a Private Bus (PBUS) 13 which is connected between each of Main Memories 12 and each of the CSSs 2 with the Main Memories 12 and the CSSs 2 being connected to PBUS 13 through SBIs 10. PBUS 13 is provided as a means from private, high speed data reads from Main Memories 12 to CSSs 2, while general purpose data transfers and memory write operations are performed through SYSBUS 8.
DPS 1 also includes Peripheral Devices (PDs) 14, such as disk and tape drives and communications devices. Each PD 14 is connected to System Bus 8 through a SBI 10 and an appropriate corresponding Peripheral Device Controller (PDC) 16.
Finally, DPS 1's functional units include a System Management Facility (SMF) 20 with associated system management devices. SMF 20 provides centralized control of DPS 1. Among the operations controlled by SMF 20 are initialization of the DPS 1 system, initialization and control of Quality Logic Testing, that is, system fault testing and detection, and loading of operating system and applications software into Main Memories 12 and CSSs 2. SMF 20 also controls certain overall system operations, including system timing, monitoring of errors and faults, and monitoring of system operating temperature and system power.
Associated with SMF 20 are a Display Console 22 connected to SMF 20, which allows direct communication between a user and DPS 1, and a Console Adapter 24 which provides communication between Display Console 22 and System Bus 8 through SMF 20. Communication between a remote user and DPS 1, for example, for remote diagnostics, may be provided in the same manner as Display Console 22 through a Remote Console 26, which is connected to SMF 20 through Modems 28 and a Communications Link 30. Finally, SMF 20 includes a connection to Power System sensors and controllers 32 and to such Auxiliary Devices 34 as a printer.
Referring to FIG. 2, therein is represented a simplified block diagram of a CSS 2 with those portions of a CSS 2 comprising CP 4 and SBI 10 being generally indicated by brackets.
First considering the CP 4, each CP 4 is comprised of an Instruction Unit (IUNIT) 36 which receives and decodes instructions to provide control outputs to the other elements of the CP 4, and Execute Unit (EUNIT) 38, which performs the actual data processing operations, and an Address Unit (AUNIT) 40, which is responsive to IUNIT 36 and EUNIT 38 to perform address translation functions and to control the reading and writing of data and instructions to and from MM 12 and CACHE 6. As the function and operation of processing unit elements such as IUNIT 36, EUNIT 38 and AUNIT 40 are well known and understood by those of ordinary skill in the art, these units will not be discussed in further detail herein. In addition, these units of the exemplary system are well described in the previously referenced related patents.
Referring to the SBI 10 related portions of the CSS 2, certain elements of SBI 10, such as CACHE 6, may in this and other systems be equally well regarded as a part of the CP 4 as the SBI 10, but is represented herein as part of SBI 10
An SBI 10 includes Data Drivers (DDs) 42, comprised of line drivers, for transferring information from the CP 4 and SBI 10 to System Bus 8 and Data Receivers (DRs) 44, comprised of line receivers, for receiving information from System Bus (SYSBUS) 8 and Private Bus (PBUS) 13.
In the system illustrated herein, the outputs of DRs 44 are connected into a Cache 6, which stores the information received from SYSBUS 8 and PBUS 13 for subsequent acceptance by the CP 4 or the functional logic of the SBI 10. In alternate embodiments, the element shown as Cache 6 may be implemented as a set of registers for receiving the data and instructions from SYSBUS 8 and PBUS 13, or as a set of registers arranged as a First-In-First-Out (FIFO) memory, rather than as a full cache.
Cache 6 in turn provides outputs to Control Logic (CL) 46, which provides control outputs to the CP 4 to direct certain operations of the CP 4, for example, the loading of firmware into the CP 4 at system initialization. Cache 6 also provides outputs to Data/Interrupt/Syndrome Registers (DIS) 48, which in turn provides data, interrupt commands and instructions, received from SYSBUS 8 and PBUS 13 and through Cache 6, to the CP 4. DIS 48 also receives and stores certain information from the CP 4, such as fault and status or "syndrome" information, for subsequent transmission to other units of DPS 1, such as SMF 20.
Associated in turn with DIS 48 is a Hardware Revision Store (HRS) 50 for storing information identifying the particular revision or configuration of the hardware comprising the CSS 2. As is described in the referenced related patents, this information is read from the HRS 50 of the CSS 2 by SMF 20 at system initialization to select the particular matching revision of the firmware controlling the operation of the CSS 2.
Finally, SBI 10 includes an SBI Control (SBICNTL) 52 containing the timing and logic functions necessary to control the operations of the SBI 10 and a Bus Control (BUSCNTL) 54 for controlling the operations of SBI 10 with respect to bus transfer operations between the SBI 10 or the CSS 2 and other units of DPS 1, such as SMF 20.
BUSCNTL 54 is responsible for controlling bus operations for both SBI 10 and CP 4 and provides access from SYSBUS 8 to many of the individual registers of SBI 10, IUNIT 36, EUNIT 38 and AUNIT 40. SMF 20, for example, may read from and write to many of the individual registers of the elements of CP 4 which are directly accessible through the pins of the integrated circuit chips. SMF 20 may in turn read and write many of the internal registers of these elements by using the internal data paths of IUNIT 36, EUNIT 38 and AUNIT 40.
When a particular bus operation involves the SBI 10, BUSCNTL 54 will interact with SBICNTL 52, providing the control and timing signals as necessary to direct SBICNTL 52 in controlling the operations of SBI 10 as necessary to execute the bus operation. If the bus operation involves the CSS 2, BUSCNTL 70 will interact in a similar manner with the control logic of the CSS 2 to execute the bus operation. Both BUSCNTL 70 and SBICNTL 68 are conventional and are described in further detail in the referenced related patents and accordingly their detailed designs will not be described further as such functions are familiar to those of ordinary skill in the art.
Briefly considering the bus operations executed by the units of DPS 1, as was previously described, the various units of DPS 1, such as SMF 20 and a CSS 2 may communicate through SYSBUS 8 by executing the protocols for bus transfer operations described in the previously referenced related patents. The various signals used in the bus transfer operations include address and data fields, for communicating, for example, the identity of a system unit with which is the recipient of a bus request, the address of a memory location or register within the unit which is to be read or written to, fields indicating the type of operation to be performed, for example, a read or write operation, and various control and handshake signals.
Each bus operation is executed in two phases. In the first, the system unit initiating the operation, referred to as the master unit for the operation, asserts the request by placing control and handshake signals on SYSBUS 8 to initiate the operation. These signals include signals indicating the type of operation to by performed and the address of the location within the system unit which is the target, or recipient of the request, referred to as the slave unit for the operation. The slave unit then responds to the request by either accepting the request or by refusing the request, for example, by refusing to acknowledge the request, by asking the master unit to wait, or by simply not responding. Assuming that the request is accepted, the actual data transfer takes place in the second phase.
The most basic form of bus operation, such as the transfer of a single data word, may be executed within a single bus cycle; the request is asserted and accepted in the first half cycle, that is, the first phase, and the data transfer, the second phase, being executed in the second half cycle. Other bus operations, for example, involving the transfer of multiple data words, may require several bus cycles.
It should be noted, with respect to bus operations, that BUSCNTL 54 also includes bus access arbitration logic which, when presented with conflicting requests for bus operations from two or more system units, resolves the requests to grant access to the requesting unit having the highest assigned priority.
Referring to FIG. 3, therein is presented a simplified block diagram of SMF 20. As shown, SMF 20 is essentially a general purpose central processing unit executing programs designed to perform specialized functions. Among these functions are system initialization and test, including the initial loading of microcode routines into the CSS 2s and the loading of Quality Logic Test (QLT) programs into the MM 12s and the execution of such QLT programs to test the proper operation of DPS 1 and detect errors or faults in the operations of the CSS 2s, MM 12s and other units of DPS 1.
SMF 20 includes a Microprocessor (UP) 56, which controls and performs the operations of SMF 20 under direction of programs stored in SMF 20's memory elements, and an Address Bus 58 and a Data Bus 60 connecting UP 56 and the other elements of SMF 20 for communication of data and instructions among the element of SMF 20.
The memory elements of SMF 20 include a Microprocessor Read Only Memory (UPROM) 62, which stores the programs directly controlling UP 56, that is, UP 56's microcode routines. Data used by and generated SMF 20 and certain programs controlling the operations of SMF 20 are stored in a Microprocessor Random Access Memory (UPRAM) 64, as is typical in most computer systems.
An Electronically Erasable Programmable Read Only Memory (E2PROM) 66 is provided for long term storage of certain programs and information which are to be permanently resident in SMF 20, unless deliberately erased or overwritten by the system user. Such programs would include the initialization program, or bootload program, for SMF 20, passwords and password programs for controlling access to DPS 1 and SMF 20, information identifying the Peripheral Device 14 storing the system initialization (boot) software, MM 12 locations assigned for specific functions, such as storing boot and QLT programs, information as to which test programs are to be executed and the results to be expected from such programs, and information as to which of Peripheral Devices 14 contain the programs or microcode for controlling CSS 2s.
E2PROM 66 will also store and provide test programs for the self test of SMF 20, the testing of System Bus 8, and testing of various device's interfaces with System Bus 8, such as the SBI 10 of CSS 2. The test programs also include programs for testing internal elements of, for example, the CPs 4 and the programs of the present invention.
Finally, a Boot and QLT Read Only Memory (BOOT/QLT ROM) 68 is provided to store programs for controlling operation of DPS 1 during initialization, such as a programs for controlling the initial loading, or booting, of software into DPS 1 and for selecting QLT programs to be executed at system initialization.
SMF 20 also includes a number of device controllers for controlling the peripheral devices of SMF 20, such as a Display Controller (DC) 70 for interfacing SMF 20 with Display Console 22, a Console Adapter Controller (CAC) 72 for interfacing SMF 20 to Console Adapter 24, and a Communications Controller (COMC) 74 for interfacing SMF 20 with Modem 28.
Finally, the elements of SMF 20 are connected, through A Bus 74 and D Bus 76, to System Bus 8 through an SBI 10, which may differ in detail from that previously described with reference to CSS 2 but which performs the same general functions with respect to bus operations. BOOT/QLT ROM 68 which, as described, stores programs for controlling the initialization and testing of other units of DPS 1, such as the CSS 2s and MM 12s, is connected directly through SBI 10 to System Bus 8.
SMF 20 will not, be described in further detail as the general structure and operation of such units in a system, are, in general, well known in the art and are described in detail in the referenced related patents.
Turning now to the present invention, "shadowing" is a well known method of fault detection and isolation wherein certain elements of, for example, a central processing unit, referred to as the "shadowed elements" are duplicated and the duplicate elements, referred to as the "shadow elements", operated in parallel with the shadowed elements. The information resident in the shadowed elements is copied into, that is, duplicated in, the shadow elements so that, at each point in time, the information contained in the two sets of elements is identical.
Fault detection circuitry compares the information resident in the shadowed elements to the copy of that information resident in the shadowing elements to detect differences between the two copies of the information that may be indicative of a fault in the shadowed elements. It is most usual, as in the present implementation of the present invention, for the shadowed elements to include registers of the logic circuitry to the "shadowed", as is illustrated in FIG. 3, as the registers of an element are the normal data storage elements. The registers may be used both to latch information during normal operation, as in making the shadow copy of the information resident in the shadowed elements, and, in fault isolation operations, to save the current state of the information in both the shadowed and shadow elements to be subsequently read out by fault analysis procedures.
Referring to FIG. 3, therein is shown a diagrammatic representation of the shadowed and shadow elements of, for example, the IUNIT 36 of a CP 4, which will be used to illustrate both shadowing and the present invention.
First considering the conventional use of shadowing as a means for fault monitoring in logic circuitry, as represented FIG. 3 a given functional unit may include both shadowed elements, represented as Shadowed Logic (SL) 76, and unshadowed elements, represented as Unshadowed Logic (USL) 78, which may, for example, be a string buffer register used in the following described integrity test. It should be noted that, while USL 78 is not central to the present discussion, such unshadowed portions of logic circuitry would normally be provided with some form of fault detection and isolation, such as parity checking of information resident therein or other fault detection procedures or apparatus designed for the specific logic circuitry to be tested.
The shadowed logic, SL 76, is comprised of the functional logic circuitry which is performing the actual data processing functions and is referred to in FIG. 3 as Shadowed Functional Logic (SFL) 80. The shadowing logic circuitry is identified as Shadow Copy Logic (SCL) 82. As was indicated above, the elements of the shadowed logic circuitry involved in the shadowing are usually comprised of the data registers of the data processing logic, which are indicated in FIG. 3 as SFLl 84 through SFLn 84. Each such register in SFL 80 is duplicated in SCL 82 by a corresponding Shadow Copy Logic register, identified in FIG. 3 as SCLl 86 through SCLn 86.
The input of each SFL 84 register is connected through a Shadow Parallel Data Path (SPDP) 88 to the input of its corresponding SCL 86 register, so that, at any given time, the information resident in any given SFL 84 register is equal with the information in the corresponding SCL 86 register. This is illustrated in FIG. 3 by the Shadowed Functional Data Path (SFDP) 89, which represents the normal data input paths into the shadowed registers. As shown, the functional data path into each SFL 84 register input is also connected into the input of the corresponding SCL 86 register through the corresponding SPDP 88 data path. The registers of SCL 82 are thereby connected in parallel with the registers of SFL 80 and always contain a shadow copy of the information contained in the registers SFL 80.
Data outputs of both the SCL 86 registers of SCL 82 and the SFL 84 registers of SFL 80 are connected in parallel to the inputs of Comparator Logic (CL) 90, so that CL 90 continuously compares the information being processed in the functional data processing elements of the unit being monitored, that is, the information in the SFL 84 registers, to the shadow copy of that information residing in the SCL 86 registers and, in general, detects and indicates any differences between the two sets of information that might be indicative of a fault or error in the functional data processing logic containing the SFL 84 registers.
It should be noted, in this respect, that, due to the complexity of the logic circuitry which is normally being monitored and the constraints on lead availability within a complex integrated circuit chip, the data outputs of the registers involved in the shadowing may not be directly available. The data outputs of the SFL 84 and SCL 86 registers may reach CL 90 through indirect paths. As such, whether any given bit in an SCL 86 register is visible, as received by CL 90, is influenced by many other factors. As an example, a given bit output from a register may pass through a multiplexer before being connected to CL 90 and, as such, that input to CL 90 may, depending upon certain external or internal control signals, actually be from another register bit position than is desired.
Because of this, CL 90 will normally not be able to see a number of mismatches between the information being processed, as received from the registers of SFL 80, and the shadow copy of that information, as received from the registers of SCL 82, even if either SFL 80 are SCL 82 in error or fault. CL 90 must therefore be understood to detect only mismatches in those signals available to the comparator and, in this case, they are the shadowed outputs of the chip and of the shadowing logic equivalent outputs.
Turning now to the present invention, it is apparent from FIG. 3 that, in the shadowing operation the data bits resident in the shadowed and shadowing registers are read from and written into the registers in parallel. Accordingly, the shadowed and shadowed registers as used in conventional shadowing are of the parallel-in/parallel-out type, that is, data bits may be written into and read from the registers in parallel and is copied from the shadowed registers to the shadowing registers in parallel. It should be noted, however, that some of the SFL 80 shadowed registers may, in their data processing functions, be serial-in/serial out registers, that is, data bits may be written into and read from the registers serially.
The method for testing the integrity of the fault monitoring logic of the present invention requires that both the shadowed registers of SFL 80 and the shadowing registers of SCL 82 be capable of serial-in/serial-out operation and adds a further data path to the registers illustrated in FIG. 3. This data path is indicated as Serial Test Data Paths (STDPs) 92, and connects the serial data inputs and outputs of the shadowed registers of SFL 80 and the shadowing registers of SCL 82 into a single serial chain of registers. It should be noted that parallel/serial registers, that is, registers capable of both parallel-in/parallel-out and serial-in/serial-out operation are well known in the art and readily available.
As will be described further below with reference to FIGS. 4 and 5, the fault monitoring integrity test of the present invention is performed at system power-up and under the control of SMF 20 which, as described, is capable or reading from and writing to the register of the elements in CP 4, such as IUNIT 36. The integrity test is performed by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers of SFL 80, the shadowing registers of SCL 82, and the serial data path comprised of STDPs 92, and monitoring the faults, or errors, detected by CL 90. As described below, there are two sets of test patterns. The first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. The second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.
Referring to FIGS. 4 and 5, therein is illustrated the operation of the fault monitoring integrity test of the present invention. Each of FIGS. 4 and 5 contains a part of the procedure and together contain the entire procedure. As will be described, the integrity test is performed in four sequences of steps. In the first two, a test pattern of bits is shifted into the scan chain comprised of the shadowed and shadowing registers and the outputs of the registers compared to determine whether any errors have been detected.
The procedure begins at system initialization with Step 94, wherein series of all "0"s is written serially into the scan chain comprised of shadowed registers of SFL 80 and the shadowing registers of SCL 82, until the registers all contain "0"s. In Step 96, CL 90 compares the test bits read from the shadowed registers of SFL 80 with the test bits read from the shadowing registers of SCL 82 and, in Step 98, determines whether any errors have been detected between the contents of the shadowed and shadowing registers. If errors have been detected, the procedure goes to Step 100 and initiates the appropriate fault isolation procedures, which are generally well known in the art.
If no errors are detected, the procedure goes to Steps 102, 104 and 106, which essentially repeats the test procedure of Steps 94 through 98, but with all "1"s loaded into the shadowed and shadowing registers.
If no errors were detected in Step 106, the procedure goes to Step 108, wherein the shadowed and shadowing registers are loaded with all "0"s by serially shifting a chain of all "0"s into the scan chain.
Step 110 load a single "1" test bit into the first bit of the scan chain and the outputs of the shadowed and shadowing registers are compared by CL 90, in Step 112, to determine whether an error now appears from comparing the outputs of the shadowed and shadowing registers.
If an error is detected, an error count is incremented, in Step 114, and the procedure goes to Step 116, which determines whether the register bit presently containing the logic "1" test bit is the last bit of the scan chain, that is, and in the present example, in the bit of the last shadowing register SCL 86 of SCL 82.
If the test bit is not in the last bit of the scan chain, the procedure goes to Step 118, wherein a logic "0" is loaded into the first bit of the scan chain, and to Step 120, wherein the bits in the scan chain all all shifted by one bit towards the end of the scan chain. The second bit of the scan chain will now contain the "1" test bit, and the first bit of the scan chain and the third through final bits of the scan chain will contain "0"s.
The procedure then goes again to Step 112, to determine whether a comparison of the bits in the shadowed and shadowing portions of the scan chain shows any errors and increments the error counter if errors are detected, and then again to Step 116 to determine whether the test bit is in the last bit position of the scan chain.
The procedure will continue around the loop comprising Steps 116, 118, 120, 112 and 114 until the test bit appears in the last bit position of the scan chain. The procedure thereby shifts a test bit pattern consisting of a single logic "1" test bit and otherwise all "0"s through the entire scan chain of shadowed registers SFL 84 and shadowing registers SCL 86, examining the contents of the shadowed and shadowing registers at every position in which the test bit appears and counting the total number of errors detected during this operation.
When the test bit has been entirely shifted through the scan chain, and the last bit position has been reached by the test bit, the procedure branches to Step 122, where the total number of errors detected is compared to a predetermined number.
As was described, the purpose of shifting a test pattern comprised of a single "1" test bit in a continuous string of "0"s was to induce errors at each bit position in the scan chain, and to detect those errors. This test sequence could thereby result in an error detected for each bit position in the shadowed and shadowing registers.
As was also described, however, the comparison logic will normally not be able to see a number of mismatches between the information being processed, as received from the registers of SFL 80, and the shadow copy of that information, as received from the registers of SCL 82. For this reason, this final step in the first sequence using a test pattern designed to induce errors test that at least a minimum number of errors have been detected, rather than the total possible number of errors.
It should be noted that the first test sequences, those using bit patterns selected so as to not result in errors probably will not require a determination of whether the number of errors detected is greater than or less than a predetermined number because the probability of false errors is less when the test patterns are all comprised of "1"s or "0"s. If all the test bits in the shadowed and shadowing registers are the same, however, such an "error" in the bit input to CL 90 will be invisible.
In the event that false errors appear when the all "0"s or all "1"s test patterns are used, however, the approach used for the single "1" or single "0" patterns, that of comparing the number of detected "errors" to a predetermined number may be used to "filter out" the false errors. In the case of the all "0"s and all "1"s test patterns, however, which are selected so as to not, in themselves cause error indications, the test would be whether the number of detected errors exceeds a given limit, rather than whether the number of errors detected is less than a given limit.
Returning to consideration of the test patterns selected to induce error responses, if the error count has indicated that the minimum number of errors has not been detected, the procedure will branch to Step 124 for the appropriate fault isolation procedures.
If the error count has indicated that at least the minimum number of errors has been detected then it is concluded that the test logic is operating correctly and the procedure branches to the sequence of steps comprising Steps 126 through 142.
Steps 126 through 142 essentially perform the same test as Steps 108 through 124, but with a test pattern comprised of a single logic "0" test bit in a string of otherwise all logic "1" bits, and again determines whether the minimum number of errors has been detected.
While the invention has been particularly shown and described with reference to a preferred embodiment of the method thereof, it will be understood by those of ordinary skill in the art that various changes in form, details and implementation may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, the order in which the test patterns are used may differ and the specific structure of shadowed and shadowing registers may differ from that shown, for example, the shadowing registers may appear "upstream" in the scan chain from the shadowed registers, or the shadowed and shadowing registers may be interleaved along the scan chain.
|Cited Patent
|Filing date
|Publication date
|Feb 4, 1986
|May 26, 1987
|Raytheon Company
|LSI fault insertion
|Nov 10, 1986
|Oct 18, 1988
|Mitsubishi Denki Kabushiki Kaisha
|Forced error generating circuit for a data processing unit
|Apr 13, 1988
|Jan 30, 1990
|Mitsubishi Denki Kabushiki Kaisha
|Test circuit having selective by pass arrangement for test data
|Nov 13, 1989
|Nov 20, 1990
|International Business Machines Corporation
|Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system
|Sep 19, 1988
|Feb 26, 1991
|Unisys Corporation
|Fault capture/fault injection system
|Oct 17, 1988
|Mar 19, 1991
|Unisys Corporation
|Diagnostic error injection for a synchronous bus system
|Dec 2, 1988
|Aug 27, 1991
|Hitachi, Ltd.
|Semiconductor integrated circuit device
|Jul 31, 1989
|Oct 15, 1991
|Ag Communication Systems Corporation
|Programmable fault insertion circuit
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|P. Goel, "Testable Decoder Design for Decoder-Controlled Multiplexing Networks", IBMTDB, vol. 20, No. 9, Feb. 1978, pp. 3463-3465.
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|Test Logic for Error Checkers , IBMTDA, vol. 31, No. 12, May 1989, pp. 387 389.
|Citing Patent
|Filing date
|Publication date
|Dec 27, 1993
|Sep 13, 1994
|Motorola, Inc.
|Data processing system having serial self address decoding and method of operation
|Mar 1, 1993
|Jan 10, 1995
|At&T Corp.
|Method and apparatus for detecting retention faults in memories
|Aug 4, 1995
|Jul 14, 1998
|Siemens Aktiengesellschaft
|Substitute circuit for a plurality of functional units
|May 15, 1995
|Feb 23, 1999
|Motorola Inc.
|Addressable serial test system
|Jan 15, 1998
|May 30, 2000
|Lsi Logic Corporation
|Dynamic logic element having non-invasive scan chain insertion
|Mar 31, 1998
|Jan 2, 2001
|Lsi Logic Corporation
|Hardware assisted mask read/write
|Apr 7, 1998
|Jan 30, 2001
|International Business Machines Corporation
|Method and tool for computer bus fault isolation and recovery design verification
|Apr 30, 1999
|Jan 13, 2004
|International Business Machines Corporation
|Real time function view system and method
|Dec 6, 2002
|Sep 12, 2006
|International Business Machines Corporation
|IML-stream generated error insertion / FRU isolation
|Jan 29, 2007
|Mar 30, 2010
|Jtekt Corporation
|Safety control device, safety control system, and method for detecting communication error
|Apr 26, 2011
|International Business Machines Corporation
|Method and apparatus for performing logic built-in self-testing of an integrated circuit
|Jan 10, 2012
|International Business Machines Corporation
|Method and apparatus for improving random pattern testing of logic structures
|Dec 6, 2002
|Jul 3, 2003
|International Business Machines Corporation
|IML-stream generated error insertion / FRU isolation
|Jan 29, 2007
|Jan 24, 2008
|Jtekt Corporation
|Safety control device, safety control system, and method for detecting communication error
|Mar 19, 2008
|Sep 24, 2009
|International Business Machines Corporation
|Method and apparatus for improving random pattern testing of logic structures
|Dec 10, 2009
|Forlenza Donato O
|Method and apparatus for performing logic built-in self-testing of an integrated circuit
|U.S. Classification
|714/703, 714/726
|International Classification
|Cooperative Classification
|European Classification
|Oct 5, 1990
Owner name: BULL HN INFORMATION SYSTEMS INC., A CORP. OF DE, M
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