text:
|Numéro de publication
|Type de publication
|Numéro de demande
|Date de publication
|13 févr. 2007
|Date de dépôt
|5 janv. 2004
|Date de priorité
|5 janv. 2004
|État de paiement des frais
|Autre référence de publication
|Numéro de publication
|Raminda Udaya Madurawe
|Cessionnaire d'origine
|Viciciv Technology
|Exporter la citation
|BiBTeX, EndNote, RefMan
|Citations de brevets (21), Citations hors brevets (3), Référencé par (57), Classifications (10), Événements juridiques (13)
|Liens externes: USPTO, Cession USPTO, Espacenet
This application is related to application Ser. No. 10/267,484 entitled "Methods for Fabricating Three-Dimensional Integrated Circuits", application Ser. No. 10/267,483 entitled "Three Dimensional Integrated Circuits", and application Ser. No. 10/267,511 entitled "Field Programmable Gate Array With Convertibility to Application Specific Integrated Circuit", all of which were filed on Oct. 8, 2002 and list as inventor Mr. R. U. Madurawe, the contents of which are incorporated herein by reference.
The present invention relates to electronic circuits that retain identical functionality and performance under Random Access Memory (RAM) and Hard-Wire Read Only Memory (ROM) fabrication options.
Traditionally, application specific integrated circuit (ASIC) devices have been used in the integrated circuit (IC) industry to reduce cost, enhance performance or meet space constraints. The generic class of ASIC devices falls under a variety of sub classes such as Custom ASIC, Standard cell ASIC, Gate Array and Field Programmable Gate Array (FPGA) where the degree of user allowed customization varies. In this disclosure the word ASIC is used only in reference to Custom and Standard Cell ASICs where the designer has to incur the cost of a full fabrication mask set. The term FPGA denotes an off the shelf programmable device with no fabrication mask costs, and Gate Array denotes a device with partial mask costs to the designer. The devices FPGA include Programmable Logic Devices (PLD) and Complex Programmable Logic Devices (CPLD), while the devices Gate Array include Laser Programmable Gate Arrays (LPGA), Mask Programmable Gate Arrays (MPGA) and a new class of devices known as Structured ASIC or Structured Arrays.
The design and fabrication of ASICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. In the event of finding a logic error in the custom or semi-custom ASIC during final test phase, the design and fabrication cycle has to be repeated. Such lengthy correction cycles further aggravate the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost. The high cost of masks and unpredictable device life time shipment volumes have caused ASIC design starts to fall precipitously in the IC industry. ASICs offer no device for immediate design verification, no interactive design adjustment capability, and require a full mask set for fabrication.
Gate Array customizes pre-defined modular blocks at a reduced NRE cost by designing the module connections with a software tool similar to that in ASIC. The Gate Array has an array of non programmable (or moderately programmable) functional modules fabricated on a semiconductor substrate. To interconnect these modules to a user specification, multiple layers of wires are used during design synthesis. The level of customization may be limited to a single metal layer, or single via layer, or multiple metal layers, or multiple metals and via layers. The goal is to reduce the customization cost to the user, and provide the customized product faster. As a result, the customizable layers are designed to be the top most metal and via layers of a semiconductor fabrication process. This is an inconvenient location to customize wires. The customized transistors are located at the substrate level of the Silicon. All possible connections have to come up to the top level metal. The complexity of bringing up connections is a severe constraint for these devices. Structured ASICs fall into larger module Gate Arrays. These devices have varying degrees of complexity in the structured cell and varying degrees of complexity in the custom interconnection. The absence of Silicon for design verification and design optimization results in multiple spins and lengthy design iterations to the end user. The Gate Array evaluation phase is no different to that of an ASIC. The advantage over ASIC is in a lower upfront NRE cost for the fewer customization layers, tools and labor, and the shorter time to receive the finished product. Gate Arrays offer no device for immediate design verification, no interactive design adjustment capability, and require a partial mask set for fabrication. Compared to ASICs, Gate Arrays offer a lower initial cost and a faster turnaround to debug the design. The end IC is more expensive compared to an ASIC.
In recent years there has been a move away from custom, semi-custom and Gate Array ICs toward field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user "in the field" prior to use. Off the shelf FPGA products greatly simplify the design cycle and are fully customized by the user. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to improve Silicon performance. In an FPGA, a complex logic design is broken down to smaller logic blocks and programmed into logic blocks provided in the FPGA. Logic blocks contain multiple smaller logic elements. Logic elements facilitate sequential and combinational logic design implementations. Combinational logic has no memory and outputs reflect a function solely of present input states. Sequential logic is implemented by inserting memory in the form of a flip-flop into the logic path to store past history. Current FPGA architectures include transistor pairs, NAND or OR gates, multiplexers, look-up-tables (LUT) and AND-OR structures in a basic logic element. In a PLD the basic logic element is labeled a macro-cell. Hereafter the terminology logic element will include both logic elements and macro-cells.
For sequential logic designs, the logic element may also include flip-flops. A MUX based exemplary logic element described in Ref-1 (Seals & Whapshott) is shown in
Provision of this programmability is expensive in terms of Silicon real estate, but reduces design cycle time, time to solution (TTS) and upfront NRE cost to the designer. FPGAs offer the advantages of no NRE costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the other two approaches. Compared to FPGA, an ASIC and Gate Array both have hard-wired logic connections, identified during the chip design phase. ASIC has no multiple logic choices and both ASIC and most Gate Arrays have no configuration memory to customize logic. This is a large chip area and a product cost saving for these approaches to design The larger Silicon area for programmability in an FPGA causes two events that aggravate cost: larger chip area leads to less total available die in a wafer, larger chip area has a higher chance of having a defect that will make it non-functional. Of the two events, the former is proportional to die area while the latter is exponential to die area and dominates the cost of the product. A full custom ASIC has customized logic functions which take less gate counts compared to Gate Arrays and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count FPGA. A Gate Array is also smaller, faster and cheaper compared to an equivalent FPGA. The trade-off is between time-to-market (FPGA advantage) versus low cost and better reliability (ASIC advantage). A Gate Array falls in the middle with an improvement in the ASIC NRE cost at a moderate penalty to product cost and performance. The killer defects found in the extra area for programmability in an FPGA compared to ASIC and Gate Array contribute to a significant portion of the extra cost the user has to bear for customer re-configurability of logic functions. A method to reduce an FPGA final die cost would greatly enhance the cost parity between an FPGA and an ASIC.
FPGA and Gate Array architectures are discussed in Hartmann et al. (U.S. Pat. No. 4,609,986), Carter (U.S. Pat. No. 4,706,216), Turner et al. (U.S. Pat. No. 4,761,768), El-Ayat et al. (U.S. Pat. No. 4,857,774), Freeman (U.S. Pat. No. 4,870,302), El Gamal et al. (U.S. Pat. No. 4,873,459), Freeman et al. (U.S. Pat. No. 5,343,406), Freeman et al (U.S. Pat. No. 5,488,316), Tsui et al. (U.S. Pat. No. 5,835,405), Trimberger et al. (U.S. Pat. No. 5,844,422), Wittig et al. (U.S. Pat. No. 6,208,163), Or-Bach (2001/0003428), Mendel (U.S. Pat. No. 6,275,065), Or-Bach (U.S. Pat. No. 6,331,789), et al. (U.S. Pat. No. 6,448,808), Agrawal et al. (2002/0186044), Sueyoshi at al. (2003/0001615) and Pugh et al. (2003/0085733). These patents disclose programmable AND/OR array, MUX and LUT structures and routing blocks to build logic blocks that are user configurable. The configuration memory element comprises multiple transistors. SRAM memory has six transistors in a cell. Single poly EEPROM has three transistors, one capacitor and one tunneling diode in a cell. In all cases the memory element together with a configuration circuit allows the user to program the device. This programmable overhead creates a significant cost burden due to enhanced Silicon area and killer defects compared to a non-configurable solution. Addition of redundant circuits in an FPGA to repair some faulty circuits is not sufficient to reduce the cost disparity. There is no provision in the referenced disclosures for a user to get to a lower cost solution from an FPGA without having to re-engineer the entire design to either a Gate Array or an ASIC platform.
Logic elements include programmable point to point connections. Four exemplary methods of programmable point to point connections, synonymous with programmable switches, between node A and node B are shown in
Most commercially available high density FPGA's use SRAM memory elements. A volatile six transistor SRAM based configuration circuit is shown in
For an emulation device, the cost of programmability is not the primary concern if such a device provides a migration path to a lower cost production solution. Today an FPGA migration to a Gate Array requires a new design to ensure timing closure. The FPGA and the Gate Array devices are completely different dies, manufactured with completely different mask sets, having identical functionality. A desirable migration path is to keep the timing of the original FPGA design intact. That would avoid valuable re-engineering time, prevent opportunity costs and save invaluable time to solution (TTS). Such a conversion is preferable in the same base die to avoid manufacturing logistics complexity, save on Silicon and system re-qualification costs and avoid implementation delays. Such a conversion should also realize a lower cost end product that is competitive with an equivalent standard cell ASIC or a Gate Array product in cost. Such an FPGA device will readily target applications that are cost sensitive, have short life cycles and demand medium volumes.
In one aspect, an integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises a hard-wired circuit in lieu of said user configurable circuit.
In a second aspect, a programmable logic device (PLD) comprising two selectable memory construction options to control logic, wherein: a first selectable option comprises a random access memory (RAM) construction; and a second selectable option comprises a hard-wire read only memory (ROM) construction.
In a third aspect, a configurable pass-gate logic element for a PLD, said pass-gate electrically coupling two nodes, said configuration achieved by a memory element, said memory element comprising two selectable construction options, wherein: a first selectable option constitutes a random access memory (RAM) construction; and a second selectable option constitutes a hard-wire read only memory (ROM) construction.
Implementations of the above aspects may include one or more of the following. A system design may be specified by the user in VHDL or Verilog design input language and synthesized to a gate-level netlist description. Synthesized netlist may be ported into a PLD, an FPGA, a Gate Array or used to construct a standard cell or custom ASIC. The final Integrated Circuit may include a programmable logic core to incorporate glue logic or other logic functions that could change at the last minute of system design. The programmable logic core may also provide some flexibility into otherwise a fixed IP Integrated Circuit to allow some degree of customer configurability. A PLD or an FPGA may include some fixed IP such as memory, adders, multipliers and I/O (Input/Output) to provide some standard features. Programmability in an FPGA and FPGA core is achieved by a configuration circuit that includes a memory module.
The memory in a first selectable construction is a Random Access Memory (RAM) module. The memory is one of volatile or non-volatile memory. Volatile memory includes DRAM, SRAM, and Optical cells, among other types of memory. Non-volatile memory includes fuses, anti-fuses, EPROM, EEPROM, Flash, Ferro-electric, Electro-Chemical and Magnetic memory. The most common memory element is a six transistor SRAM cell. The memory element generates an output signal which controls the logic state of a pass-gate logic element. A pass-gate logic element is also known as a switch. A pass-gate is an NMOS transistor, or a PMOS transistor or a CMOS transistor pair that can electrically connect two points. Programming these pass-gate devices include forming one of either a conducting path or a non-conducting path in the connecting device. The configuration circuit consumes a large Silicon area. The larger area reduces the total die available in a wafer, increasing the die cost. The larger area is more prone to collecting a killer defect. The killer defects reduce the number of good die in a wafer, thus impacting the cost of a good die. The user benefits by the ability to configure circuits at the expense of a higher die cost. The RAM memory provides an off-the-shelf programmable device and saves TTS for the user.
The memory in a second selectable construction is a Read Only Memory (ROM). The ROM comprises hard-wire connections to power and ground buses. The ROM module cannot provide user configurability. The ROM is therefore generated by a finalized RAM pattern from the first selectable option. Both RAM and ROM options are provided in the same base Silicon die, with no changes to a majority of manufacturing mask sets and fabrication process. Both RAM and ROM elements control the very same logic gates. Each RAM pattern will generate a unique ROM pattern to duplicate identical logic functionality. Hard-wire ROM pattern may include coupling power-bus and ground-bus to pass-gate logic in lieu of RAM control signals. The ROM option may include one custom mask. The hard-wire ROM option may include two or more custom masks. The goal is to minimize the number of customized masks and to keep the non recurring engineering (NRE) costs to a minimum. Signal propagation wires and transistors are unchanged between the two memory options. There is no timing impact between the two options avoiding lengthy re-engineering time and cost. The die is identical between the two options avoiding re-qualification costs. There are only one or two custom masks in the ROM option, keeping the logistics involved in manufacturing RAM and ROM versions simple. The hard-wire ROM circuits mitigate the risk of killer defects in configuration circuits. The hard-wire ROM option uses less available logic choices, leaving unused circuits redundant. Unused circuits do not impact ROM die yield. ROM option provides an apparent defect density reduction and a higher yield. The ROM option provides a significant cost reduction for a RAM based FPGA.
Once the programming is finalized by the user, the programmable connections set by RAM bit pattern are fixed for most designs during product life cycle. Programmability is no longer needed and no longer valuable to the user. The user may convert the design to a lower cost hard-wire ROM circuit without altering the original RAM design. The programmed choices are mapped from RAM to hard-wire ROM. RAM outputs at logic one are mapped to ROM wires connected to power. RAM outputs at logic zero are mapped to ROM wires connected to ground. This may be done with a single metal mask. Such elimination of configuration circuits, including configuration memory, reduces the die cost of the ROM version. The propagation delays and critical path timing in the Integrated Circuit may be substantially identical between the two memory module options. Duplicated ROM pattern may be done with a customized thru-hole mask. Customization may be done with a thru-hole and a metal mask or a plurality of thru-hole and metal masks. Hard wire pattern improves reliability and reduces defect density of the final product. The ROM pattern provides a cost economical final product to the user at a very low NRE cost. The total solution provides a programmable and customized solution to the user in a single die.
The programmable circuits described constitute fabricating a VLSI IC product. The IC product is re-programmable in its initial stage with turnkey conversion to a one mask customized ASIC. The IC has reasonable cost parity with an ASIC cost and has initial off the shelf FPGA with re-programmability. The IC product offering occurs in two phases: the first phase is a generic PLD that has re-programmability contained in a programmable module, and a second phase is an ASIC that has the entire programmable module replaced by one or two customized hard-wire masks. Both FPGA version and turnkey custom ASIC has the same base die. No re-qualification is required by the conversion. The design and layout of these product families adhere to alterable memory concept: ensuring the functionality and timing of the product in its RAM and ROM canonicals. An easy turnkey customization of an end ASIC from an original programmable device would greatly enhance time to market, performance, product reliability and solution cost.
In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
Definitions: The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, SOI material as well as other semiconductor structures well known to one skilled in the art The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors.
The term module layer includes a structure that is fabricated using a series of predetermined process steps. The boundary of the structure is defined by a first step, one or more intermediate steps, and a final step. The resulting structure is formed on a substrate.
The term pass-gate refers to a structure that can pass a signal when on, and blocks signal passage when off. A pass-gate connects two points when on, and disconnects two points when off. A pass-gate can be a floating-gate transistor, an NMOS transistor, a PMOS transistor or a CMOS transistor pair. The gate electrode of pass-gate determines the state of the connection. A CMOS pass-gate requires complementary signals coupled to NMOS and PMOS gate electrodes. A control logic signal is connected to gate electrode of a pass-gate for programmable logic.
The term configuration circuit includes one or more configurable elements and connections that can be programmed for controlling one or more circuit blocks in accordance with a predetermined user-desired functionality. The configuration circuit includes the memory element and the access circuitry, herewith called memory circuitry, to modify said memory element. Configuration circuit does not include the logic pass-gate controlled by said memory element. In one embodiment, the configuration circuit includes a plurality of RAM circuits to store instructions to configure an FPGA. In another embodiment, the configuration circuit includes a first selectable configuration where a plurality of RAM circuits is formed to store instructions to control one or more circuit blocks. The configuration circuits include a second selectable configuration with a predetermined ROM conductive pattern formed in lieu of the RAM circuit to control substantially the same circuit blocks. The memory circuit includes elements such as diode, transistor, resistor, capacitor, metal link, wires, among others. The memory circuit also includes thin film elements. In yet another embodiment, the configuration circuits include a predetermined conductive pattern, contact, via, resistor, capacitor or other suitable circuits formed in lieu of the memory circuit to control substantially the same circuit blocks.
The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal direction as defined above. Prepositions, such as "on", "side", "higher", "lower", "over" and "under" are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense.
The present invention attempts to realize a significant cost reduction in the conversion of RAM circuits to hard-wire ROM circuits. RAM circuits are useful for the user to configure circuits. ROM circuits have no user configurability. Such a RAM to ROM conversion needs to maintain the functionality and timing characteristics of the original RAM circuits, not change the die foot-print, simplify or maintain the fabrication process steps and have minimal customization cost. First a conversion method is described to map a user configured RAM pattern to a hard-wire ROM pattern. The method of conversion makes no impact to timing and functionality of logic in the resulting cheaper die. Second, the usefulness of such a scheme is discussed. Such a conversion makes all of the configuration memory and a plurality of extraneous circuits redundant in an integrated circuit. Most defects associated with those do not hurt the die yield. Furthermore, multiple logic choices are eliminated by the hard-wire option to a single choice. Any defect impacting the unselected logic choices also do not hinder the die yield.
Programmable logic use point to point connections that utilize programmable pass-gate logic as shown in
A volatile DRAM based configuration circuit to use with this invention is shown next in
A non-volatile anti-fuse based configuration circuit is shown next in
These configuration circuits, and similarly constructed other configuration circuits, can be used in programmable logic devices. Those with ordinary skill in the art may recognize other methods for constructing configuration circuits to generate a valid S0 output. The pass-gate logic element is not affected by the choice of the configuration circuit.
SRAM memory technology has the advantage of not requiring a high voltage to configure memory. The SRAM based switch shown in
The RAM point to point connection in
The programmable RAM circuit shown in
This method of ROM substitution is possible in all RAM applications where the output generated by the RAM bit is at binary voltage levels. Binary voltages are easily realized by hard-wire connections to power-bus and ground-bus. All SRAM based FPGAs and single poly PLDs commercially available, listed in Ref-1 & Ref-2 and discussed in the listed patents have binary voltage outputs. Commercially available anti-fuse based FPGAs only provide anti-fuse elements between two wires. Under the method disclosed, the Anti-fuse RAM elements are replaced in the ROM version with either a thru-holes connection or an absence of a thru-hole connection with one custom mask. There are many PLDs designed with double poly EPROM and FLASH processing technologies that do not lend to this method of easy ROM conversion. In a single floating-gate double poly transistor, the floating-gate is fully buried under the control gate, and there is no easy access to the floating gate. However, the floating-gate transistors may be replaced by normal transistors for a ROM option, with all the "on" bits in a row line having their gates coupled to a common row line, and all the "off" bits in that row line having their gates disconnected from the row line and tied to ground.
The impact of programmability on die cost is discussed next to demonstrate the value in replacing RAM circuits with ROM circuits. In this analysis, 6-transistor SRAM memory is used to illustrate the salient features. The discussion is equally valid under any other volatile and non-volatile programmable elements such as DRAM, EPROM, and EEPROM among others. Four factors contribute to the cost of programmability: the area penalty for memory elements, the area penalty of providing multiple logic choices, the total available die in a wafer and the cost penalty for wasted die due to killer defects.
The memory required for programmable logic is illustrated in a 4-input look-up-table (LUT) based logic element (LE) shown in
A second limitation in programmable logic is in the expense of providing multiple logic choices. Multiple logic choices provided in a 2:1 MUX is illustrated in
When the ROM utilization area is very small compared to RAM area, the apparent defect density becomes very small. A true estimate of A versus A′ is quite complicated to achieve. A simpler method is to take the FPGA die area A, and estimate an equivalent ASIC die area A′ that can provide the same functionality as the FPGA. ROM version of the FPGA would hard-wire a similar die area A′. For a commercially available FPGA device on 0.15μ process technology, we have estimated the following:
A(FPGA)=300 mm2 , A′(ASIC)=88 mm2
A typical FPGA core is estimated to be at least 10–20×larger in Silicon area compared to an ASIC. The commercial die example above includes memory, I/O pads, multipliers and other fixed area circuitry common to both FPGA and ASIC. Under such conditions, a process with D=0.5 def/cm2 reduces to D′=0.147 def/cm2 from EQ-1 for the ROM option of the FPGA. As some defects in the extraneous circuitry such as Vcc shorts and Vss shorts can still lend to killer defects, not all of this lower apparent defect density is realized in a real situation. That can be easily incorporated into a higher defect density by setting D′ higher than estimated by EQ-1 as follows:
In the example discussed, the 10% higher defect density yields D′=0.16 def/cm2 for the 88 mm2 ROM version of a 300 mm2 RAM based FPGA. The functional die yield Y (%) in a Semiconductors IC is modeled by the die area A (cm2), defect density D (def/cm2) and the probability of no defects in the Gamma Distribution function from Ref-3 (Sze) as:
N=0.90*π*(20/2)2 /A EQ. 4
n=Y*N EQ. 5
where, S is the square of the coefficient of variance, taken as 1/12 in this discussion. N is the total available die in a 200 mm diameter Silicon wafer assuming 90% of the wafer can be efficiently used to print full die. The parameter π, which is ˜3.14, is the ratio of circumference to diameter of a circle. The cost of a good die decreases as the number of good die per wafer (DPW) n in the wafer increase.
For the FPGA with RAM option, where A=300 mm2, using D=0.5 def/cm2 and S= 1/12 in EQ-3, EQ-4 and EQ-5:
Y=24.3%, N=94 DPW, n=22 DPW
The same FPGA converted to a ROM option, where A′=88 mm2, but A=300 mm2 is unchanged, using D′=0.16 and S=112 in EQ-3, EQ-4 and EQ-5:
Y=62.5%, N=94 DPW, n=58 DPW
As the process and wafer cost remain identical between the two options, the latter ROM die cost is seen to be 2.6×cheaper than the identical RAM option. One can easily compare this to the ideal ASIC die cost by using A=88 mm2, using D=0.5 def/cm2 and S= 1/12 in EQ-3, EQ-4 and EQ-5:
Y=64.9%, N=321 DPW, n=208 DPW
In this example, the ASIC die is 9.5×cheaper than the RAM option of the FPGA, and 3.6×cheaper than the ROM option of the FPGA. However, to obtain an ASIC die the user has to incur 0.5–1.0 year Silicon fabrication, debug and qualification time and spend over 2M$ in NRE costs just for chip layout, masks and fabrication. At $2400 wafer prices, the RAM FPGA is economical for life time volumes less than 20,500 while the ROM FPGA is economical for life time volumes under 67,000 units. The cost associated with saving 8 months in shipping a product for an organization having a burn rate of 250 K$/month (20 person engineering team in the US) is another 2M$. A more meaningful economical balance is for an ASIC design option to save over 4M$ during life time shipments compared to an FPGA solution. For a 4M$ overall ASIC NRE cost, the RAM based FPGA is more economical when life time volume is under 41,000 units, while the ROM based FPGA is more economical when life time volume is under 134,000 units. Over 50% of designs ship under 100,000 units over a life time. The ROM based FPGA provides a significant cost advantage compared to the RAM based FPGA, and is more economical than an ASIC design for a majority of design opportunities. In this disclosed product duality, the system designer uses the RAM FPGA to debug, tweak and proto-type the initial system solution, then moves to cheaper ROM version for mass production. There is no engineering involved with the change, there is a single custom mask cost to the user. In a first embodiment the fabrication process steps do not change as RAM and ROM constructions use identical steps. In a second embodiment the fabrication process is made simpler by removing the custom processing steps needed only for RAM construction.
The disclosure describes a programmable logic device and an application specific device fabrication from the same base Silicon die. The PLD is fabricated with a programmable RAM module, while a cheaper option is fabricated with a conductive ROM pattern in lieu of the RAM. Both RAM module and ROM module provide identical control of logic circuits. For each set of RAM bit patterns, there is a unique ROM pattern to achieve the same logic functionality. The apparent defect density reduction in the hard-wire circuits leads to a significant cost reduction for the ROM version. Such conversions allow the user a lower cost and more reliable end product. These products offer an enormous advantage in lowering NRE costs and improving TTS in the ASIC design methodology in the industry.
Although an illustrative embodiment of the present invention, and various modifications thereof, have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to this precise embodiment and the described modifications, and that various changes and further modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.
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|26 déc. 2007
|13 oct. 2009
|Tier Logic, Inc.
|Using programmable latch to implement logic
|14 juil. 2008
|22 déc. 2009
|Tier Logic, Inc.
|Multi-port thin-film memory devices
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|MPGA products based on a prototype FPGA
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|Programmable interconnect structures
|30 mars 2010
|Easic Corporation
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|11 mai 2007
|20 juil. 2010
|Tier Logic, Inc.
|Semiconductor devices fabricated with different processing options
|14 sept. 2010
|Tier Logic
|Programmable latch based multiplier
|12 oct. 2010
|Tier Logic, Inc.
|Pad invariant FPGA and ASIC devices
|25 janv. 2011
|Altera Corporation
|Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits
|21 juin 2011
|Xilinx, Inc.
|Formation of columnar application specific circuitry using a columnar programmable device
|17 avr. 2012
|Raminda Udaya Madurawe
|Memory for metal configurable integrated circuits
|17 avr. 2012
|Raminda Udaya Madurawe
|Metal configurable integrated circuits
|17 avr. 2012
|Raminda Udaya Madurawe
|Interconnect structures for metal configurable integrated circuits
|25 sept. 2012
|Raminda Udaya Madurawe
|Programmable structured arrays
|23 avr. 2013
|Raminda Udaya Madurawe
|Three dimensional integrated circuits
|31 mars 2004
|9 juil. 2013
|Icera Inc.
|Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths
|9 déc. 2010
|9 juil. 2013
|Icera Inc.
|Apparatus and method for control processing in dual path processor
|16 avr. 2008
|30 juil. 2013
|Raminda Udaya Madurawe
|Timing exact design conversions from FPGA to ASIC
|19 nov. 2007
|4 févr. 2014
|Raminda Udaya Madurawe
|Pads and pin-outs in three dimensional integrated circuits
|29 aoűt 2012
|19 aoűt 2014
|Raminda U. Madurawe
|Programmable structured arrays
|12 juil. 2010
|9 sept. 2014
|Raminda Udaya Madurawe
|Three dimensional integrated circuits
|10 sept. 2012
|7 oct. 2014
|Raminda Udaya Madurawe
|Three dimensional integrated circuits
|6 janv. 2014
|30 juin 2015
|Yakimishu Co. Ltd. L.L.C.
|Pads and pin-outs in three dimensional integrated circuits
|23 juil. 2012
|21 juil. 2015
|Raminda U. Madurawe
|Automated metal pattern generation for integrated circuits
|13 aoűt 2014
|19 janv. 2016
|Callahan Cellular L.L.C.
|Three dimensional integrated circuits
|12 nov. 2004
|18 aoűt 2005
|Samsung Electronics Co., Ltd.
|Damping structure of a hard disk drive
|31 mars 2004
|6 oct. 2005
|Simon Knowles
|Apparatus and method for asymmetric dual path processing
|31 mars 2004
|6 oct. 2005
|Simon Knowles
|Apparatus and method for dual data path processing
|30 juin 2005
|4 janv. 2007
|Jason Messier
|Device and method to reduce simultaneous switching noise
|1 mars 2007
|5 juil. 2007
|Madurawe Raminda U
|MPGA products based on a prototype FPGA
|25 janv. 2006
|26 juil. 2007
|Easic Corporation
|Programmable via modeling
|22 févr. 2006
|23 aoűt 2007
|International Business Machines Corporation
|Method for using partitioned masks to build a chip
|16 aoűt 2007
|20 déc. 2007
|Altera Corporation
|Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits
|19 nov. 2007
|20 mars 2008
|Madurawe Raminda U
|Insulated-gate field-effect thin film transistors
|19 nov. 2007
|8 mai 2008
|Madurawe Raminda U
|Multi-port memory devices
|16 avr. 2008
|11 sept. 2008
|Raminda Udaya Madurawe
|Timing Exact Design Conversions from FPGA to ASIC
|9 sept. 2008
|1 janv. 2009
|Raminda Udaya Madurawe
|Thin film transistors and fabrication methods
|16 févr. 2008
|12 févr. 2009
|Raminda Udaya Madurawe
|Programmable Interconnect Structures
|19 nov. 2007
|21 mai 2009
|Raminda Udaya Madurawe
|Pad invariant FPGA and ASIC devices
|19 nov. 2007
|21 mai 2009
|Raminda Udaya Madurawe
|Three dimensional programmable devices
|14 juil. 2008
|21 mai 2009
|Raminda Madurawe
|Multi-port thin-film memory devices
|23 janv. 2008
|28 mai 2009
|Raminda Udaya Madurawe
|Programmable structured arrays
|19 nov. 2007
|11 juin 2009
|Raminda Udaya Madurawe
|Pads and pin-outs in three dimensional integrated circuits
|26 déc. 2007
|2 juil. 2009
|Nij Dorairaj
|Using programmable latch to implement logic
|16 janv. 2008
|2 juil. 2009
|Nij Dorairaj
|Programmable latch based multiplier
|12 mai 2008
|2 juil. 2009
|Raminda Madurawe
|Programmable logic based latches and shift registers
|12 mai 2008
|2 juil. 2009
|Raminda Madurawe
|Programmable logic based latches and shift registers
|11 mars 2009
|2 juil. 2009
|Teradyne, Inc.
|Device and method to reduce simultaneous switching noise
|9 déc. 2010
|31 mars 2011
|Icera Inc.
|Apparatus and method for control processing in dual path processor
|12 juil. 2010
|5 mai 2011
|Raminda Udaya Madurawe
|Three dimensional integrated circuits
|2 mars 2012
|2 sept. 2014
|Raminda Udaya Madurawe
|MPGA products based on a prototype FPGA
|Classification aux États-Unis
|326/38, 326/40, 326/47
|Classification internationale
|Classification coopérative
|Classification européenne
|6 juil. 2007
Owner name: VICICIV TECHNOLOGY, INC., CALIFORNIA
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|29 aoűt 2011
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Owner name: YAKIMISHU CO. LTD., LLC, DELAWARE
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- November 24, 2013
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It's not working, Trey.
For those who follow the antics of Calvin and Hobbs, I found a story entitled Calvin Does High School in a fanfiction site consisting of 15 chapters. I thought it would be worth a look-see and a few comments: Cavin Does High School.
Needz better tie, too
Should see my Monday ones…
Not really.
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subset: commoncrawl


text:
-I'm outdoorsy, by that I mean that like to drink beer on patios.
-I enjoy going to crappy dive bars. Its a nice, calm place to meet friends and hang out or watch a game.
-I have a Godson who is now 9, I wish I could spend more time with him.
-I am a big fan of the summer time, and as you could expect, not so much of winter.
-I can admit that I'm a pretty good cook. You name it, and I can probably make it... except for toast, I have trouble with toast.
-I prefer gloves to mittens, but sandles to flip-flops; go figure.
-When it comes to making long-term plans, I prefer to make it up as I go.
-I'm a life long Cardinals fan; I'm willing to date a Cubs fun, but she should be prepared to get all kinds of trouble in October.
- I like to think of myself as that sweet-spot between "city boy" and "country boy."
That's all for now, but if there's something you want to know, ask me.
I have found my grown-up job and absolutely love it.
Except for toast, have a rough time making toast.
I am also told that I'm a good listener.
No, I have no idea what people notice about me first.
A radio
And two other things...


text:
To get Marin Science Seminar updates subscribe to our email list. If you don't like it, you can easily unsubscribe. Fall 2016 Schedule coming at the end of August.
Founded in spring 2008, the Marin Science Seminar (MSS) is a free, science cafe type event for teens & community in Marin County, California. Seminar sessions are 12 Wednesdays during the school year, from 7:30 to 8:30 pm in a science classroom, room 207, at Terra Linda High School, 320 Nova Albion Way, San Rafael, 94903. The seminar includes a presentation with question and answer period and is open to teens & community members. Speakers are scientists, technologists, mathematicians, engineers, medical professionals & computer programmers. Topics presented are in an area of the speaker's expertise, geared to interested high school students. See our past speakers here. We also offer science journalism and videography internships to MarinCounty high school students.
The Marin Science Seminars were founded and are run by Alfia and Art Wallace.
Local & Cool! Astronomy on Mt. Tam - Bay Area Science - Science at Cal - Wonderfest
Marin Science Seminar will be back in September!
Links to more free local science talks and opportunities here
Links to more free local science talks and opportunities here


text:
Anxious Pets
If your pooch doesn't like strangers, he's definitely not going to enjoy heavy-booted contractors tromping around his turf. Angie Hicks, founder of the service-provider referral network Angie's List, has a simple fix: "Send him to a kennel. Or, even better, to stay with a trustworthy family member."
Ask TOH users about Remodels & Upgrades


text:
San Francisco 49ers coach Mike Nolan on Wednesday defined the role of Ted Tollner, naming the longtime NFL assistant as the team's new quarterbacks coach.
The appointment of Tollner continues the reshaping of Nolan's offensive staff after a 2007 season in which San Francisco suffered through what was arguably the least-productive campaign in franchise history. The 49ers statistically ranked last in the league in both total yards and points.
Nolan hired former St. Louis Rams coach Mike Martz as his new offensive coordinator.
Tollner's role will be key, because he will work with three-year veteran quarterback Alex Smith, the top overall choice in the 2005 draft but a player who seemed to regress in 2007 before a shoulder injury that required surgery prematurely ended his season. Tollner was brought aboard by Nolan in a consulting role at midseason in 2007 to help then-offensive coordinator Jim Hostler, who was fired at the end of the year. After the season, Nolan said that Tollner would remain with the 49ers in a full-time role, with his responsibilities to be determined.
The veteran Tollner last coached with the Detroit Lions under Steve Mariucci in 2005, serving for 11 weeks as offensive coordinator before Mariucci was let go. Tollner finished out that season as the tight ends coach. Before his time with the Lions, Tollner was with the 49ers from 2002-05, coaching quarterbacks for two seasons before he was promoted to offensive coordinator.
Tollner began his NFL career as a wide receivers assistant with the Buffalo Bills in 1987. He moved to the San Diego Chargers, where he was offensive coordinator, a year later, serving in that capacity through 1991. He was then the quarterbacks coach for the Los Angeles Rams 1992-93.
The club also announced that Adam Gase has been added as an offensive assistant. Gase joins the 49ers after spending five seasons with the Lions. He began in the scouting department in 2003 and then began assisting the Detroit coaching staff in 2005.
Len Pasquarelli is a senior NFL writer for ESPN.com.


text:
"Cirebon, Heritage of Old Kingdom" Cirebon by dhita_yudhistira
Cirebon Travel Guide: 44 reviews and 86 photos
Many old Indonesian's old Mosque are located in Jakarta. Some dated back to aroun 1400M. Unfortunately, this go unnoticed. The mosques are not well maintained and in some cases of renovation, they change the architecture.
I was fortunate enough to know them from my friends, Old Mosque observer from Institut Teknologi Bandung. Had not I go with them, I wouldn't notice the mosques.
- Pros:Nice Seafood, Old Palace (Keraton) and Mosque
- Cons:Hot climate
Reviews (1)
This hotel name Saresae means sleep well in Sundanese/Javanese. This hotel is a minimalist hotel, the floor made of low... more travel advice
Have you been to Cirebon? Share your travels with the world!
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text:
Hi, I am fairly new to WordPress and I am looking for a good UK host.
I have WordPress 3.3.1 running off of my machine, and I have it all working correctly.
I looked on the hosting tab but it only recommends American hosting, which is fine, but if I need support its nice to know I can ring up and speak to someone in the day time.
If anyone knows of any UK based hosting and recommends it then please let me know.
Thank you,


text:
The Chevy Chase DC Library's book club selection for October is Extremely Loud and Incredibly Close by Jonathan Safran Foer.
The Chevy Chase Library is pleased to announce that David Shaman, author of The World Bank Unveiled: Inside the Revolutionary Struggle for Transparancywill be giving an author talk at our branch on Monday, September 20th at 7 pm. Mr. Shaman will be reading from his book and answering questions from readers.
From Nessie's Diary: Wednesday, September 1, 2010Greetings! Allow me to introduce myself. My name is Nessie. I am 10. I am white, soft, and fluffy. I am a PAL dog.
Forget what you used to know about Bogota, Colombia. Fifteen years ago it was considered one of the world's worst cities. Today, thanks to several remarkable mayors who thought way outside the box, Bogota is a city transformed. The changes have been dramatic and inspiring. Our library is featuring a display on this transformation through October 15.
Cooler days are coming, and what better time of year to sit and enjoy reading in the lush greenery of our Reading Garden? If you haven't tried it yet, give yourself a little treat. Come, sit and read a while!
This year the summer reading theme centered around water. Every month, when children reached their goals they got to design a "splasher" and put their name on it. Each month the shape of the "splasher changed; the three shapes were shell, starfish and fish. As you can see, we had a lot of people contribute to the wall, and the goals ranged from five books a month to 120 books per month! Well done everyone who made this a success.
Starting Thursday September 2nd at 11 AM the Chevy Chase Library will be offering a five week program on reading to your baby. Each week will focus on a new skill. Space is limited to 15 caregivers.
This Saturday September 4th starting at 10 AM the Chevy Chase Library will be having a party to celebrate the end of the Summer reading program. This years theme was "Make a Splash", and we will be having games, prizes and fun!


text:
Multiple moderators on my blog, and it looks like one of the polls created was deleted by mistake. We use polldaddy. The poll is still active on my blog, but doesn't show up on my list of blogs from my admin site.
Any idea how to retrieve the results of a deleted poll (we made the results private)
Thank you!


text:
Journal of the American Oil Chemists' Society
, Volume 73, Issue 8, pp 983-989
First online:
Restructuring butterfat through blending and chemical interesterification. 3. Rheology
- Dérick RousseauAffiliated withDepartment of Food Science, University of Guelph
- , Arthur R. HillAffiliated withDepartment of Food Science, University of Guelph
- , Alejandro G. MarangoniAffiliated withDepartment of Food Science, University of Guelph
Rent the article at a discountRent now
* Final gross prices may vary according to local VAT.Get Access
Interesterified and noninteresterified butterfat-canola oil blends, ranging from 100% butterfat to 60∶40 butterfat-canola oil (w/w) in 10% increments, were evaluated for hardness index (HI), dropping point, viscosity, and viscoelastic properties at small deformation. Both blending and chemical interesterification diminished HI in a nonlinear fashion. HI changes in interesterified blends were more pronounced than in noninteresterified blends. Dropping points yielded information on the structure of the blends. Butterfat's dropping point (DP) was 34.4°C, whereas that of interesterified butterfat was 37.0°C, which is indicative of a more structured network for the latter. DP values of blends with 60–90% butterfat (interesterified vs. noninteresterified) were not significantly different (P<0.05). Interesterified blends had a higher crystallization onset temperature than did noninteresterified blends. All blends in the liquid state displayed Newtonian behavior. Oscillatory frequency sweep measurements at small amplitude showed that interesterified blends generally had lower storage moduli (G′) than their noninteresterified counterparts. BothG′ andG″ were frequency-dependent. Replacement of 30% butterfat by canola oil led to notable changes in small deformation measurements, whereas replacement of 20% butterfat led to big changes in large deformation measurements.
Key WordsCone penetrometry dropping point hardness index viscoelasticity viscosity
Reference tools
- Title
- Restructuring butterfat through blending and chemical interesterification. 3. Rheology
- Journal
Journal of the American Oil Chemists' Society
Volume 73, Issue 8 , pp 983-989
- Cover Date
- 1996-08
- Print ISSN
- Online ISSN
- 1558-9331
- Publisher
- Springer-Verlag
- Additional Links
- Topics
- Keywords
- Cone penetrometry
- dropping point
- hardness index
- viscoelasticity
- viscosity
- Industry Sectors
- Authors
- Dérick Rousseau (1)
- Arthur R. Hill (1)
- Alejandro G. Marangoni (1)
- Author Affiliations
- 1. Department of Food Science, University of Guelph, N1G 2W1, Guelph, Ontario, Canada


text:
27 April, 2010@6:20 am
0 comments
Seems like everyone moved their release dates around to make sure they weren't competing with a little old artist named B.o.B. and his Atlantic Records / Grand Hustle debut, The Adventures of Bobby Ray. Atlantic's direct deal preorder packages are done with, so let's see where the best place to cop this album is……
Itunes – $11.99: The Apple edition includes two bonus tracks, "Letters From Vietnam" and "I See Ya", as well as two bonus videos, which include an interview and "Nothin' On You".
Target – $9.99: Target's edition is offering pretty much the same thing you get at Itunes, but in a physical sense. The Target edition includes a 30 minute bonus DVD, which we assume is the interview and "Nothin' On You" video, same as Itunes. It also included two bonus tracks, which are not listed on the website, but we assume are also "Letters From Vietnam" and "I See Ya", as the two companies have partnered and are cross promoting one another.
Verdict: Target, hands down. Sorry Itunes, but Target's got you beat on price, and you get to keep the disc. How this slipped past the suits, we don't know. HHS Adventures Of Bobby Ray album review coming later this week…..
Leave a Reply
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text:
create facebook covers
This project received 44 bids from talented freelancers with an average bid price of $106 USD.Get free quotes for a project like this
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Project Budget$30 - $250 USD
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Project Description
Hello. I am in a need of 5 facebook covers. we a radio station and we need to advertise our new radio shows.
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- Forbes
- The New York Times
- Time
- Wall Street Journal
- Times Online


text:
Right now carriage returns are not showing up in my comments. Users, including myself, can hit ENTER a dozen times between two lines, and those lines will still be smooshed (technical term) together when the coment displays. I've tried adding paragraph and line break tags, but those get ignored as well.
Is there some way to allow returns to be made into paragraph breaks for all comments, please?


text:
I have created a live usb of Ubuntu 12.04 with a 4GB persistence file. Firefox and other software get updated when running update manager. However, the linux kernel will not update and I am unable to install synaptic package manager, ubuntu tweak, etc. Is there a fix for this. Thanks in advance.
i found this solution also on askubuntu and i apply it and worked for me and i share again here:
Comment out line 15
Run the configuration script:
You should see a lot of debugging, and NOT the error line at the end.
To be sure, re-run the configuration. It should end immediately without any logs:
Now, you can restore the zz-update-grub file, just in case you want to install an other kernel later and Grub start to work with overlayfs...


text:
Survey Suggests Class Sizes Exceed the Official Averages
By JACQUES STEINBERG
Published: April 14, 1997
At Public School 32 in Flushing, Queens, a sprawling building crammed with children of Asian and Latin American immigrants, it takes Janice Gellman three days to read with each of the 27 students in her first-grade class.
And it would take even longer, if the school didn't bus half of its kindergarten pupils to another elementary school a mile away, to free additional space and keep classes from getting even larger.
With the school system growing by 20,000 students a year, the situation at P.S. 32, where the average first-grade class has 28 students, is far from unusual. In fact, a survey of city elementary schools by The New York Times last month suggests that classes are larger on average than city and school officials acknowledge.
Officials say their goal is to hold class sizes in kindergarten through third grade to an average of 25, and a report released in February by Mayor Rudolph W. Giuliani concluded that the system had met that target this year.
But when asked about The Times's findings, the school officials who supplied that data to City Hall acknowledged that their numbers were simply guesses -- and that they made sure to keep the guesses under the target of 25 pupils.
The officials said they had since used actual enrollments to calculate the average class size for all elementary grades through fifth grade, and the number was 25.5.
But The Times's telephone survey of 45 elementary schools -- selected at random and representing 7 percent of the 660 citywide -- found that the average class size overall was 28.4.
And of the 38 schools that responded to a question asking them to list average class sizes in the first grade, more than three-quarters said their classes exceeded the average of 25 reported by the Mayor. And nearly half reported having an average of at least 28 students: no small difference, given the intensive one-on-one attention required in a class of early learners.
The survey of elementary schools was part of a broad effort by The Times to examine services throughout the city in the fourth year of the Giuliani administration.
In an update of a similar effort in the fall of 1995, reporters visited schools, parks, municipal hospitals and subway stations to measure a dozen city and state services. They rated the cleanliness of city streets, and they timed how long it took to get prescriptions filled at a city hospital and to pay parking tickets at the Parking Violations Bureau. They also analyzed the city's own statistics to evaluate changes in social services and to measure the length of lines at the Buildings Department. What emerged was a mixed picture, with some aspects of city life -- most notably crime statistics -- significantly improved, while some services are still feeling the cumulative effects of budget cuts.
Asked about The Times's findings on class size, a spokeswoman for the Board of Education, Karen Crowe, said that the board's most recent calculations were based on dividing the total citywide enrollment of each grade, as of Oct. 31, by the total number of classes.
''In computing an average class size,'' she said, ''there are bound to be classes above average and some below average.''
The Deputy Mayor for Operations, Randy M. Mastro, also questioned the survey, saying the number of schools canvassed was small.
In fact, the survey's margin of sampling error was small, because the average class size in each of the 45 schools, which had more than 1,000 classrooms altogether, did not vary much from school to school. According to statistical standards, 19 times out of 20 that sample would yield a result within 0.7 students of the true citywide average.
At P.S. 32, one of the schools selected at random, Ms. Gellman spends most of her time helping her pupils in individual programs of study that she has tailored to each student's abilities. And those abilities are varied, given that her students speak eight foreign languages, including Pashto, Korean, Urdu and Punjabi. At any given moment, 27 students may be doing 27 different things, with a large percentage tugging at her sleeve for help.
On a recent afternoon, Sabreet Kang, 6, labored alone to make sentences out of the words ''make'' and ''mother,'' coming up with ''My mother makes a book.'' Renee Han worked to turn a plastic cup into a rabbit. And Ms. Gellman read aloud at her desk with Stephanie Chow -- or at least tried to, for the interruptions were continuous, with one girl announcing she had a headache and needed to see the nurse, and two others insisting that Ms. Gellman drop what she was doing and help them turn on the classroom computer.
Ms. Gellman said that having no more than 25 students -- or ideally no more than 22 -- would let her serve her students better.
''Let's pretend you have 45 minutes to wrap gifts,'' she said. ''At the end of the 45 minutes, whether you have 22 gifts or 27, all will be wrapped. But if you had 22, you'd have time to do something special: put a bow on or tie a frilly ribbon.''
After imposing substantial budget cuts on the city school system during his first two years in office, Mayor Giuliani chose this election year to hold overall school spending relatively constant. But those who occupy the schools each day said that they had noticed little improvement despite the fiscal reprieve. Services that were pared in recent years -- like guidance counselors and art teachers -- have not been restored, they said, and many buildings remain in desperate need of expansion and renovation.


text:
Every once in a while I will do something like
ssh user@host sudo thing
and I am reminded that ssh doesn't allocate a pseudo-tty by default. Why doesn't it? What benefits would I be losing if I aliased
ssh to
ssh -t?
The primary difference is the concept of interactivity. It's similar to running commands locally inside of a script, vs. typing them out yourself. It's different in that a remote command must choose a default, and non-interactive is safest. (and usually most honest)
I would caution against using
You can also test for the presence of a terminal in your own shell scripts. To test STDIN with newer versions of bash:
Here is the same bash test as earlier, but for STDOUT:
While it's possible to work around these issues, you're inevitably going to forget to design scripts around them. All of us do at some point. Your team members may also not realize/remember that this alias is in place, which will in turn create problems for you when they write scripts that use your alias.
SSH escape characters and transfer of binary files
One advantage that hasn't been mentioned in the other answers is that when operating without a pseudo-terminal, the SSH escape characters such as
Proof of concept
Copy a binary file using a pseudo-terminal:
Copy a binary file without using a pseudo-terminal:
The two files aren't the same:
The one which was copied with a pseudo-terminal is corrupted:
while the other isn't:
Transferring files over SSH
This is particularly important for programs such as
OpenSSH helps protects you from yourself
It's worth noting that even if the
However, it sensibly doesn't care if
This allows you to get a "shell" of sorts to the remote server. For servers that do not grant shell access but allow SSH (i.e, Github is a known example for SFTP access), using this flag will cause the server to reject your connection.
The shell also has all your environmental variables (like
Think about backward-compatibility.
The 2 primary modes of ssh are interactive-login with a tty, and specified-command without a tty, because those were the exact capabilities of
So the defaults were decided before ssh was born. Combinations like "I wanna specify a command and get a tty" had to be accessed with new options. Be glad that at least we have that option now, unlike when we were using


text:
$W$ is a subspace of the vector space $V$. Show that $W^{\perp}$ is also a subspace of $V$.
You need to show three things:
Recall that $\bf v$ is in $W^\perp$ if and only if ${\bf v}\cdot {\bf w}=0$ for all ${\bf w}\in W$.
Towards showing 1) holds, note (and verify) that the zero vector is in $W^\perp$.
Towards showing 3) holds, suppose that ${\bf v}_1$ and ${\bf v}_2$ are both in $W^\perp$. We have to show that the vector ${\bf v}_1+{\bf v}_2$ is in $W^\perp$; so we need to verify that $({\bf v}_1+{\bf v}_2)\cdot {\bf w}=0$ for all ${\bf w}\in W$. Towards this end, use the fact that $({\bf v}_1+{\bf v}_2)\cdot {\bf w}= {\bf v}_1\cdot {\bf w}+{\bf v}_2\cdot {\bf w} $.
I'll leave the verification that 2) holds, and the rest of the verification that 3) holds for you.


text:
This in-person event is for accelerated partners interested in Optimized Desktop messaging. In addition to upgrading your computer, you'll receive all the materials needed to host your very own Windows 7 Launch event for your company or customers. A separate Windows 7 Loadfest for small- and medium-sized business partners is coming soon. Once in the Partner Learning Center course description, click on the register button for a complete list of cities and dates.
Due to high demand, Partners are limited to 2 seats per company per city.


text:
Plextor M6e 256GB PCIe SSD Review - Breaking the Chains of SATA III
AIDA64 Random Access Time
Version and / or Patch Used: 1.60
Developer Homepage: http://www.aida64.com
Product Homepage: http://www.aida64.com
AIDA64 offers several different benchmarks for testing and optimizing your system or network. The Random Access test is one of very few, if not the only, that will measure hard drive random access time in hundredths of milliseconds as oppose to tens of milliseconds.
Latency and random performance at QD1 remain close to speeds we see on Marvell's SATA based controllers.
This is an area we're still coming to terms with because, in theory, when you remove the PCH or South Bridge and move the connection directly to the CPU, it would seem that latency should decrease. In every PCIe SSD we've tested, our theory didn't pan out, but we think AHCI is the reason why. Still, latency is very low.
PRICING: You can find products similar to this one for sale below.
United States: Find other tech and computer products like this over at Amazon's website.
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text:
Will it pay off for the airline?
Copy the habits of the successful
Join the NASDAQ Community today and get free, instant access to portfolios, stock ratings, real-time alerts, and more!
After a long week of big news affecting the U.S. markets --
from the results of the General Election to Hurricane Sandy and
the follow-up Nor-easter to a 3.3+% sell-off in the Dow over the
past 2 trading days -- Friday's markets come in on a relatively
quiet background. Futures are still down ahead of the market
open, which looks as if it may cap a disappointing weak of
The views and opinions expressed herein are the views and opinions of the author and do not necessarily reflect those of Nasdaq, Inc.
Enter up to 25 symbols separated by commas or spaces in the text box below. These symbols will be available during your session for use on applicable pages.
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text:
Hi all,
Please accept my sincere apologies if a question along similar lines has been posted before. I have followed various tutorials prior to coming here, to no avail.
My site is: departours.com
Theme: silverOrchid
Theme Author: Gazpo
WP Vers: 3.5.1
Site intention: travel site
If you take a gander at my site, you can see I have created menu items already. Destinations has drop-down subcategories, plus further subcategories for regions of countries.
My problem is that I want to feature my travel articles as blog posts on these subcategory pages. So, if I wrote 10 about Cumbria, I'd feature them all on that page as new posts, and perhaps 1 or 2 select ones on the England page too.
I've tried creating categories with Destinations as a parent for England and so forth, however, in doing so, I lose the dropdown capability for subcategories. I can't have a custom menu in the header as my theme doesn't allow it, and I've also tried using a Dropdown Menu Widget which obviously won't work for that reason.
My knowledge of code isn't very advanced. I can get by with CSS and know certain bits to look for/ alter in php files. I was wondering if anyone would be kind enough to give me a prod in the right direction on how to achieve the above.
Many thanks,


text:
|"Uncanny X-Men" #501 on sale August 20
Famed crooner Tony Bennett is known for singing about how he left his heart in San Francisco, and the cast of Marvel Comicsâ âUncanny X-Menâ are starting to see what he means. In issue #500, in stores now, the mutant team relocated to the City by the Bay. CBR News spoke with co-writer Matt Fraction about what he and Ed Brubaker have planned for the book.
Fraction and Brubaker wanted to get the X-Men out of New York, and San Franciscoâs long history of tolerance and acceptance made it the perfect new home for the team. âOne thing we wanted to play with was, âWhat if the X-Men lived somewhere where they werenât feared and hated and theyâre instead celebrated and embraced?ââ Fraction told CBR News. âSan Francisco honors and celebrates diverse cultures and there are few more unique and diverse than the X-Men. When the fires of anti-Mutant hysteria get restoked, the city continues to embrace them and when the rest of the world starts to turn against the X-Men their new home stays with them.
âThe move to San Francisco also fits with where the Marvel Universe has been going lately,â Fraction continued. âPlus thereâs a giant Dreaming Celestial standing in Golden Gate Park.â
|Art from "Uncanny X-Men" #501
San Franciscoâs many distinctive neighborhoods and their inhabitants are going to become an important part of âUncanny X-Menâ in the coming months. âSan Francisco is really a new team member in a lot of ways,â Fraction said. âThe flavor of the city, its history, the people, the really diverse ethnic groups, cultures, and religions are going to influence the book. Iâm doing a Colossus story that takes place in the old Russian neighborhoods. Colossus goes out one night looking for some home cooking, finds it and gets tied into a big adventure. Itâs the kind of story we couldnât do when he lived in a mansion in upstate New York.â
In âUncanny X-menâ #500, readers got their first glimpse of the X-Menâs new base of operations, which is located in an area just outside of San Francisco known as the Marin Headlands. âThe Marin Headlands is a gift from our editor Axel Alonso, who is a San Francisco kid through and through,â Fraction said. âItâs basically an area of old military bases built into the mountains of Marin. They were gun batteries and observation posts during the second World War and theyâre still there. Itâs also one of the most beautiful locales on Earth; itâs home to spectacular sunsets and incredible views. Itâs a beautiful piece of land right there overlooking the bay.â
The X-Menâs new headquarters is a building that can serve many purposes. âItâs a lot of different stuff; an embassy, a sanctuary, a community center, a school, and a museum. Itâs a cultural headquarters but itâs also a secret superhero headquarters since itâs ten times as big underground than it is above,â Fraction explained. âThereâs very much a public face thatâs manifested through the building, which as youâll see in issue #501 they come to call Graymalkin.â
|Art from "Uncanny X-Men" #501
The X-Menâs new base has a public face but itâs also a building designed to protect its inhabitants from any siege attempts. âInevitably the X-Men are going to have to walk it like theyâve been talking it,â Fraction stated. âThereâs not many mutants left and as these waves of anti-mutant hysteria build, like youâll see start to happen in issue #504, people start knocking on their door saying, âI need help. These guys burned down my house.ââ
The X-Menâs move to San Francisco means theyâll be rubbing elbows regularly with people in the cityâs infrastructure, like the police and local politicians. Recent issues of âUncannyâ have shown the cityâs mayor assisting the X-Men with their set up in San Francisco. The Mayor is a character who first appeared in issues #6-7 of Fractionâs previous series, âThe Order.â âWe wanted to use someone like the current Mayor of San Francisco, Gavin Newsom, whoâs young and well aware of the polycultural city heâs on top of,â Fraction explained. âOur Mayor is definitely optimistic and based on what little weâve seen of her it may be easy to assume that sheâs naieve, but when she goes into crisis mode she really shines. She becomes quite confidant and capable and absolutely the right person for the job.â
|Art from "Uncanny X-Men" #501
Warren Worthington III --aka Angel -- was instrumental in the X-Menâs move to San Francisco, having used his wealth, political connections, and good looks to help expedite things. But in a recent issue of âX-Force,â Angel was transformed back to the blue skinned, metal winged Archangel. Future issues of âUncannyâ will explore Angelâs transformation and the many other ways, X-Force -- Cyclopsâs secret team of mutant âwetworkâ operatives -- affects the dynamic of the core X-Men group. âThe stuff with Angel and Archangel is happening at the same time,â Fraction said. âWeâre going to start to see the ways in which having dual memberships in these teams affects people. The weight of these secrets will get very heavy very fast.â
The existence of X-Force will impact all of the members who serve in both teams, especially current X-Men leader Cyclops, who sends X-Force on their missions. âItâs not a thing that comes lightly to Scott. Heâs an intractably good man. Heâs the steward and the shepherd; the Mutant Moses trying to lead his people out of certain doom and heâs going to lead them out however he has to,â Fraction said. âHeâs not a killer or a soldier but this is who heâs been trained to be his entire life. The sort of slow and sad realization heâs going to come to is that in a lot ways Professor Xavier was right in terms of whom Scott needs to be. His whole life has been training for what he is now.â
|Art from "Uncanny X-Men" #501
In âUncanny X-Menâ #500, Cyclops and his fellow X-Men battled their oldest foe, Magneto, who was given a suit created by the amoral geneticist the High Evolutionary that replicated the mutant abilities stripped from him by his daughter the Scarlet Witch. Magneto seemed to relish having the suit, attacking the X-Men with an angry gusto he hadnât exhibited in years. âBecause of how heavy things had been in storylines like âMessiah Complexâ and âDivided We Standâ we wanted to write a fun, self-contained, special-effects laden adventure story. And part of that meant writing Magneto like how he was in the early days of âUncanny X-Men,â Fraction said. âBut that was also a gag and stunt which he used to flummox and distract the X-Men while the High Evolutionary and Kingo Sunen [A member of the Eternals who currently believes heâs a Japanese filmmaker] were lobotomizing the Dreaming Celestial. Later, we see Magneto with the High Evolutionary heâs much more the character we know, a lion in winter.â
Fraction has great affinity for the character of Kingo Sunen, but the Eternal wonât be appearing in âUncannyâ again for awhile. However, Magneto and the High Evolutionaryâs mysterious partnership will continue to be one of the bookâs central plot threads. âIts nature will be revealed,â Fraction teased. âWeâll learn why the two came together. And why theyâre working together.â
Another character that manipulated the X-Men in âUncannyâ #500 was the mysterious Simon Trask, whose surname means heâs connected to the family that designed the mutant killing Sentinels. Like Magneto and the High Evolutionary, Traskâs enigmatic agenda will be an ongoing story thread. âHeâs a long range seed,â Fraction said. âThat stuff is going to develop for the next few years. Weâve got a real road map weâre driving on and itâs pretty exciting. It gives us the opportunity to do detailed foreshadowing like this.â
|Art from "Uncanny X-Men" #501
The adversaries in the X-Menâs immediate future appeared on the final pages of âUncanny X-Menâ #500. Theyâre known as the Hellfire Cult and the X-Men will have their first encounter with them in âUncanny X-Menâ #501, the next chapter in the current âSFXâ storyline. The Hellfire Cult appears to be an anti-mutant hate group who wear the helmets of the soldiers employed by the Hellfire Club, a Clandestine group whose inner circle is composed of power hungry mutants. This left many to wonder why would mutants be running an anti-mutant hate group, but thereâs definitely more going on than meets the eye in the final scene of âUncannyâ #500; especially since Fraction revealed the man driving the Hellfire Cult van and ordering itâs members into battle is the emotion controlling mutant known as Empath. âSan Francisco is an awful big city and the X-men werenât the first mutants there,â Fraction remarked.
Things wonât get any better for the cast of âUncanny X-Menâ once their clash with the Hellfire Cult concludes, because waiting in the wings to take them on is the new Sisterhood of Evil Mutants. âThey pop up immediately after the âSFXâ arc,â Fraction confirmed. âIn the months ahead weâre going to watch their membership grow and youâll get hints about their agenda.â
âUncanny X-Menâ features a revolving door of guest-stars, but is based around a core group of heroes. âThe core is Scott, Emma, Wolverine, Storm, Angel, Beast and Nightcrawler. Your main guys are here but then as we extend out from there people can come and go,â Fraction explained. âWe didnât want to get ourselves trapped and not able to tell a Nightcrawler story because heâs in another book. So part of the idea of having everyone live in the big city is that everyone lives in the big city and readers arenât going, âJesus how big is that mansion?â Everybody is here and theyâre going to rotate in and rotate out as we need them. So itâs fun because where else do we get to write every character we want to write and not have our hands tied?â
|"Uncanny X-Men" #502 on sale in September
Fraction and co-writer Ed Brubaker will each write different arcs of âUncanny,â with Fraction penning the current âSFXâ arc. Artist Greg Land draws âSFXâ while Terry Dodson brings to life the arc that begins in âUncanny X-Menâ #504. The two artists will also rotate in and out between arcs, and each of them will work with both Fraction and Brubaker.
The X-Menâs move to San Francisco isnât the only big change in the heroesâ future. When Marvelâs current âSecret Invasionâ storyline wraps up, big changes will rock the Marvel Universe, ones that will even affect the cast of âUncanny X-Men.â âEven though they moved out of New York weâre going to start to see the X-Men tying into the Marvel Universe in ways they havenât for quite awhile,â Fraction promised.
The X-Menâs impending dip into the deeper end of the main Marvel U means Fraction and Brubaker are going out of their way to make âUncanny X-Menâ a book that satisfies both veteran fans as well as new readers. âIâm having the time of my life writing this book,â Fraction remarked. âWe hope issue #500 was a place where people came in. Weâre trying to write inclusively instead of exclusively and bring in as many new readers as we can. So this is a great jumping on point for new people.â


text:
From Wikipedia, the free encyclopedia
A mechanized process is one that uses machines. Related articles:
- Mechanised agriculture, agriculture using powered machinery
- Mechanization, doing work with machinery
- Military:
- Self-propelled artillery, also known as mechanized artillery, artillery that has its own propulsion system
- Armoured warfare, also known as mechanized warfare, warfare fought using tanks and other armored vehicles
- Mechanized infantry, infantry that is equipped with armored vehicles
- Mechanize, an album by Fear Factory
|This disambiguation page lists articles associated with the title Mechanized.
If an internal link led you here, you may wish to change the link to point directly to the intended article.


text:
Chapter 12 - Energy
Science Bulletin
Earth's Magnetic Shield
Curriculum Materials
White Light and Colored Light
When does mixing every color under the rainbow create pure white rather than a murky brown or black? When light, not paint, is the medium—and you're subtracting, not adding, color.
Peer at the world through the eyes of Einstein—a scientist who saw a beam of light and imagined riding it, a self-proclaimed "citizen of the world" who spoke out on global issues from pacifism to racism.
November 15, 2002 - January 1, 2003
Online Resource, Article
Profile: Ole Roemer and the Speed of Light
While studying one of Jupiter's moons, Ole Roemer happened upon the first good estimate of the speed of light. Before his 1676 discovery, scientists assumed that light could not be measured.
Online Resource, Article
Profile: Lyman Spitzer and the Space Telescope
The idea of launching a telescope into orbit was first suggested in 1923, but the idea wasn't realized until nearly 70 years later. Along the way, there were several obstacles and setbacks.


text:
Jump to navigation
Copyright © 2016 Rodale Inc. No reproduction, transmission or display is permitted without the written permissions of Rodale Inc.
We've all heard the excuse: "I would quit smoking, but I don't want to go up a pants size." But new research in the journal Obesity seems to debunk that claim—and even suggests that lighting up can contribute to packing on pounds.
The researchers served 47 women four cups of vanilla pudding, each with a different amount of fat, and asked them to rate the snacks' creaminess, sweetness, and the pleasure they experienced while eating it. What they found: Obese women who smoked thought all of the puddings were less sweet and creamy and enjoyed the treats less than non-smokers did.
MORE: 4 Major Problems with "Social" Smoking
What's the link between cigs and sweets? Both obesity and smoking may hinder your ability to detect flavor, possibly due to a decrease in serotonin levels, a brain chemical that controls the response of your taste buds, the scientists say.
And it's not just dessert you have to worry about: Smokers of any weight tended to crave high-fat foods more often than non-smokers, which may explain why they had higher waist-to-hip ratios than women without a nicotine habit. Pair those cravings with a reduced ability to detect the flavor of your food, and you'll likely end up eating way more than you would if you could fully appreciate the taste.
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text:
This nylon organizer from Prestige Medical has four front pockets plus a closed coin pocket, key chain clip, and tabs to secure instruments. Features a sturdy plastic clip for belt or waistband, 5 1/2" bandage scissor, disposable penlight, and three-color chart pen.
suites it's purpose at an affordable price, just wish there were more color options.
Fine product over all Except the pen light did not work !
*Offer excludes Littmann, Welch Allyn & International Orders. Cannot be combined with any other coupon offer.


text:
Solomon among the Postmoderns - eBook
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Publisher's Description
Exploring the strengths and weaknesses of postmodernism, Leithart shows how the theory reflects an important biblical theme: the elusiveness and instability of the world. But he goes on to show that biblical faith takes us beyond cynicism and despair. Solomon among the Postmoderns will appeal to academics and laypeople alike seeking a biblical view of postmodernism.
Author Bio
Author Bio
"Here is a vivacious account of postmodern culture from a true Renaissance man. With characteristic verve, Leithart deftly narrates the postmodern critique of modernity---without the typical fixation on epistemology and questions of knowledge. But the story doesn't end on the postmodern bandwagon; rather, Leithart pushes further to show that the postmodern critique of idolatry still fails to yield wisdom. In the wake of Derrida and Foucault, we still find ourselves waiting not for Godot or St. Benedict, but Solomon. Amidst the ruins of modernity, this book is an invitation to feast in the temple." -James K.A. Smith, associate professor of philosophy, Calvin College and author of Who's Afraid of Postmodernism? Taking Derrida, Lyotard and Foucault to Church
"Peter Leithart's Solomon among the Postmoderns is welcome evidence of a maturing evaluation of postmodernism in Christian circles that neither lionizes nor demonizes. Engaging in conversation rather than caricature, the author takes his interlocutors seriously precisely because he is so confident in the power of the biblical narrative to pull down all of our towers of Babel, whatever we call them. For those weary of wholesale denunciations or wholesale endorsements of postmodernism, this patient, well-informed and well-written essay in godly wisdom will illumine and inspire." -Michael Horton, Westminster Seminary
Publisher Description
Exploring the strengths and limits of postmodernism, he displays how the theory reflects an important biblical theme: the elusiveness and instability of the world. But he goes on to show that biblical faith takes us beyond cynicism and despair, exploring Solomon's frequent call to "eat, drink, and rejoice."
A skilled theologian and widely published author, Leithart writes for audiences including professors and students of philosophy, apologetics, biblical studies, and theology, as well as laypeople seeking a biblical view of postmodernism. Those familiar and unfamiliar with postmodernism will learn from the book's forthright exegetical approach, which is unique among the many books about postmodernism available today.


text:
Hey Sharpie, what are your price points for Start and End for Elliott Wave 1 Down Major that gives you the 19.14 ish price?
29.17 / 23.87 on 9/13 ,, 262 fib = 15.14 . . . 27.24 on 9/19 to 23.61 on 9/24 . . 361 fib = 14.17. Also the low yesterday may have been the Gann 50% point of the decline. Prices quickly eyeballed. Also a deep retrace instead of sub 17.75 is still a possibility, Just have to see if price keeps hitting my marks. Deep retrace, say to 18.00 or about a double bottom would be easier for people to accept, just can't tell which yet. But 23.87 from 29.17 may be all you ask for, that wave is either an A wave or a wave one down.
Thanks for your prompt reply Sharpie. From (06/26 ish Low) 17.78 - 29.17 on my chart it shows a 78.6% retrace to 20.22 which is a typical Fib retrace number for W2 retrace. Do you see this as a possible bottom?


text:
Adjustable T-Pad Arms for Metro Series Extended-Height Chairs, Black/Chrome
Brand: Safco®
Item #: SAF3495BL
- Offer multiple adjustments for supreme comfort.
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Offer multiple adjustments for supreme comfort. Help reduce strain on neck and shoulders. Install with ease. Color: Black/Chrome; For Use With: Safco® Metro™ Chair Collection; Safco® Metro™ Extended Height Chairs; Overall Height: 3"; Arm Style: T-Pad.
Offer multiple adjustments for supreme comfort. Help reduce strain on neck and shoulders. Install with ease. Color: Black/Chrome; For Use With: Safco® Metro™ Chair Collection; Safco® Metro™ Extended Height Chairs; Overall Height: 3"; Arm Style: T-Pad.
|Global Product Type
|Chair Accessories-Chair Arms
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|Safco® Metro™ Chair Collection, Safco® Metro™ Extended Height Chairs
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text:
A pair of flex-condominiums (one office, one industrial) totaling 7,000 square feet at 6160-6162 Innovation Way, Carlsbad 92009, have been sold for $1.32 million.
The two condos are in The Towers at Bressi Ranch, itself within the masterplanned Bressi Ranch Corporate Center.
The buyer was 6160 Innovation Way LLC, a California limited liability company, 560 Stevens Ave., Solana Beach 92075, Attn.: Jody Watkins.
The acquisition was financed with loans of $674,000 and $533,910 from Western Alliance Bank.
The seller of the units (213-262-14-23 and 24) was DG Global Inc., with Huarui Guo as the president.
The units were built in 2007, feature 22-foot clear height ceilings and have a 65 percent office build-out.
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