text:
|Publication number
|Publication type
|Application number
|Publication date
|Dec 26, 2000
|Filing date
|May 20, 1997
|Priority date
|May 20, 1997
|Fee status
|Publication number
|Lawrence Letham
|Original Assignee
|Vlsi Technology, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (24), Non-Patent Citations (8), Referenced by (14), Classifications (12), Legal Events (8)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates to sequentially accessible memories and more particularly, but not exclusively, relates to a technique to conserve First-In First-Out (FIFO) memory space.
Sequentially accessible memories, such as FIFO devices, are frequently employed in digital processing systems. In one application, FIFO's are utilized to buffer digital information being transferred from one device to another. Sometimes this information includes data and an address to direct the data before or after buffering. The buffering capacity of such arrangements depends on the number of FIFO locations available. Thus, there is a demand for a storage technique which optimizes utilization of the FIFO memory to buffer a digital information stream including data and associated addresses. This need exists not only for FIFO buffering applications, but also for any FIFO system that routinely stores data and associated address information.
The present invention meets this need and provides other significant advantages.
The present invention relates to a technique to conserve memory space for a sequentially accessible memory device. Various aspects of the invention are novel, non-obvious, and provide various advantages. While the actual nature of the invention covered herein can only be determined with reference to the claims appended hereto, certain features which are characteristic of the preferred embodiment disclosed herein are described briefly as follows.
In one feature of the present invention, digital memory space is conserved by sequentially transmitting a first address and a second address on a first bus coupled to a first-in first-out memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address, and has a bit size smaller than the second address. As used herein, an "address" includes any digital value or code utilized to access, channel, or otherwise direct one or more data bits associated therewith.
In another feature of the present invention, a first address is stored in a sequential access memory. The first address is paired with a first data segment. The first data segment is also stored in the memory. The first address and a second address paired with a second data segment are compared. A value corresponding to the second address is stored in the memory after this comparison unless the address for the first data segment and address for the second data segment are the same. The second data segment is stored in the memory after it is determined whether the second address should be stored.
In yet another feature of the present invention, a decoding technique is provided that includes reading a number of sets of digital information from a first-in first-out memory. The sets each have a data portion and a corresponding code portion. The code portion of each of the sets corresponds to an address for the data portion and is established as a function of a difference between at least two different addresses. The address for the data portion is generated from the code portion corresponding thereto for each of the sets. This address has a bit size larger than the code portion for each of the sets.
A further feature of the present invention includes a system for storing information that has a sequential access memory with a number of multibit locations. A digital device is configured to sequentially transmit a number of sets of digital information. These sets each have a data string and an address corresponding to the data string. Control logic is operatively coupled to the digital device and memory. This logic generates a number of coded multibit segments each representing the address of a corresponding one of the sets. The segments each correspond to a difference between two of the addresses consecutively received from the digital device and each has fewer bits than either of the two addresses.
Still another feature of the present invention is a system for storing information having a first digital bus configured to sequentially transmit a number of digital information groups that each have a data string paired with an associated address of multiple bits. The system includes a second digital bus configured to transmit the groups. Furthermore, a first-in first-out memory is included that has a number of multibit locations. This memory also has an input port coupled to the first bus and an output port coupled to the second bus. The memory buffers transmission of the groups from the first bus to the second bus. Control logic is operatively coupled to the memory, the first bus, and the second bus. This logic generates a plurality of values each representing the associated address for a corresponding one of a first number of the groups. The values are each stored in the memory and have fewer bits than the associated addressing being represented.
Accordingly, it is one object of the present invention to conserve memory space for a sequentially accessible memory device.
It is another object to optimize storage in a FIFO memory.
Yet another object of the present invention is to buffer a digital information stream including data and associated addresses with a FIFO memory.
Further objects, features, benefits, aspects, and advantages of the present invention will be apparent from the description and drawings provided herein.
FIG. 1 is a schematic view of a digital information buffering system of the present invention.
FIG. 2 is a schematic view of an address encoding format utilized by the system of FIG. 1.
FIG. 3 is a code table corresponding to the encoding format of FIG. 2.
FIGS. 4-6 are schematic examples of encoded addresses.
FIGS. 7A-7B schematically illustrate an uncoded address.
FIG. 8 is a schematic diagram depicting selected details of the system of FIG. 1.
FIG. 9 is a state diagram corresponding to the operation of the write logic depicted in FIG. 8.
FIG. 10 is a state diagram corresponding to the operation of the FIFO manager depicted in FIG. 8.
FIG. 11 is a state diagram corresponding the operation of the read logic depicted in FIG. 8.
For the purposes of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and further modifications in the described device, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.
FIG. 1 depicts a digital information buffering system 20 of the present invention. System 20 includes digital information bus 22 operatively coupled to buffer 30 and digital device 26. System 20 also includes digital information bus 24 operatively coupled to buffer 30 and digital device 28. Buffer 30 includes a dual port First-In First-Out memory (FIFO) 40 having a number of memory locations 42. Each memory location 42 has multibit word portion 42a and flag bit 42b. Only a few of memory locations 42 are designated by reference number to preserve clarity.
Several logical locations corresponding to memory locations 42 of FIFO 40 are represented in FIG. 1. Logical location L1 corresponds to memory location 42 storing the oldest information that has not yet been read out of FIFO 40--the "first-in" location. Logical location Ln corresponds to memory location 42 storing the newest unread information--the "last-in" location. The sequence of logical locations from the oldest unread location to the newest unread location is L1, L2, L3-10, . . . , L(n-2), L(n-1), Ln.
System 20 is configured to send a digital stream of information from bus 22 to bus 24 via buffer 30. The digital information includes data words paired with associated addresses. This digital information is input to buffer 30 from bus 22 through a write operation. Buffer 30 is configured to recognize an address/data pair as a set and directs storage in FIFO 40 accordingly. The buffered information is output to bus 24 through a read operation. Buffer 30 outputs address/data sets in a first-in first-out sequence determined relative to the order received from bus 22.
In one embodiment, device 26 puts an address/data pair onto bus 22 and initiates the write operation of buffer 30. Device 28 later initiates a read operation of buffer 30 to transmit the pair to device 28 via bus 24. Digital device 28 then directs the data to an appropriate internal location or I/O port designated by the associated address for this pair. In other embodiments, the address/data pairs are routed and utilized in such other manner as would occur to those skilled in the art.
Typically, the data bit width is less than the address bit width for each address/data pair. For the illustrated embodiment, the data word width is 16 bits and the address width is 28 bits. In this embodiment, word 42a has a width of 16 bits to facilitate storage of a data word in a single memory location 42; however, the 28 bit address width still requires two memory locations 42 for storage in FIFO 42. Alternatively, a FIFO memory wide enough to accommodate the address could be used; however, higher cost, increased device complexity, and wasted data location memory space are likely to result.
To further illustrate, an address/data set 44 is stored in logical locations L1, L2, L3. The full 28 bit address of set 44, address A, is stored in consecutive logical locations L1, L2 as address A word 0, address A word 1, respectively. For set 44, data word A00, is stored logical location L3.
To conserve memory space in FIFO 40, an address encoding technique of the present invention is utilized to facilitate address information storage for an address/data pair in one word 42a as opposed to two words 42a. For example, encoded information set 46 has an encoded address EA1 stored in logical location L4 and corresponding data word EA10 stored in logical location L5. A similar two location set is depicted in locations L9 and L10. The compression of address information from two memory locations 42 to one memory location is based on identifying a relationship between addresses of address/data pairs sent for buffering at different times. This relationship facilitates generation of encoded address EA1 with only a 16 bit width, avoiding the need to occupy two memory locations 42 with the associated address of data word EA10. For this embodiment, data words are stored without encoding; however, in other embodiments, data words may also be encoded using techniques known to those skilled in the art. The address encoding compression technique is further explained further in connection with FIGS. 2-11 and accompanying text hereinafter.
Information group 48 illustrates another memory conservation technique of the present invention. Group 50 depicts a full 28 bit address B and data word B00 sent as an address/data pair to FIFO 40 for storage. Address B is stored in two words as address B word 0 in location L(n-5) and address B word 1 in location L(n-4). Data word BOO is stored adjacent address B in logical location L(n-3). Sometimes, address/data pairs consecutively sent to buffer 30 have the same associated address. Such pairs may occur, for instance, when a stream of data is directed to the same I/O port (e.g. same associated address) of a device on bus 24. Buffer 30 recognizes when redundant addresses are being consecutively sent and stores only the first occurrence to conserve memory space. The data words for consecutively redundant addresses from bus 22 are consecutively stored thereafter.
To distinguish data words and address words, flag bit 42b is employed. Flag bit 42b is active (set to 1) if the corresponding word 42a contains address information and is inactive (set to 0) otherwise. Thus, flag bit 42a is set 1 for logical locations L(n-5) and L(n-4) containing address B, and is set to 0 for data word B00.
Group 50 also includes data words B01, B02, B03. Data words B01, B02, B03 were each consecutively sent to buffer 30 after data word B00, but were also paired with address B. As a result, data words B01, B02, B03 are stored in logical locations L(n-2), L(n-1) Ln; respectively, without repetitively storing address B again. Flag bit 42b is set to 0 for locations L(n-2)-Ln to indicate data contents.
Referring to encoded information group 48, The memory conservation techniques represented by set 46 and group 50 are combined. In group 48, encoded address EA2 is stored in logical location L6 with two consecutive data words EA20, EA21 stored in logical locations L7, L8, respectively. Encoded address EA2 occupies only one word 42a as described for set 46. Data word EA20 is the data word sent to buffer 30 in the pair having the address corresponding to encoded address EA2. This corresponding address was also consecutively sent in a second pair having the data word EA21. Buffer 30 recognized this redundancy, and only stored the accompanying data information, data word EA21, in FIFO 40. The previously stored encoded address EA2 provides the address information for data word EA21. Flag bit 42b is set to 1 for logical location L6 and set to 0 for logical locations L7 and L8 of group 48 to distinguish the information types.
FIG. 2 depicts encoding format 51 which has a 16 bit width corresponding to word 42a. Format 51 is utilized to provide the values of the encoded addresses depicted, for example, as EA1, EA2, EA3, in FIG. 1. Notation for various contiguous multibit ranges designated herein is provided by "[x:y]7" were the argument "x" is the most significant bit and the argument "y" is the least significant bit of the range. Thus, word 42a has the 16 bit range [15:0]. Similarly, hexadecimal values are designated herein by the "0x" prefix and binary values are designated herein by a "b" suffix. Using these conventions, the decimal value 26 is equivalent to 0x1A in hexadecimal notation and 0001 1010b in binary notation. Format 51 has four consecutive bit ranges, R1-R4, where range R1=[3:0], range R2=[7:4], range R3=[11:8], and range R4=[15:12]. The bits of the four bit Range R4 describe code 51a. The remaining ranges R1-R3 of format 51 define changed address portion 51b.
Referring additionally to FIG. 3, encoding table 52 is illustrated. Table 52 maps the integer value of code 51a, ranging from 0-10 (0000b-1010b), to a segment of the 28 bit full address. This 28 bit full address [27:0] is illustrated in seven consecutive ranges of 4 bits each. Values 0-6 (0x00-0x06, 0000b-0110b) of code 51a each map to a corresponding 4 bit nibble N1-N7 segment of the full 28 bit address, where: N1=[3:0], N2=[7:4], N3=[11:8], N4=[15:12], N5=[19:16], N6=[23:20], and N7=[27:24]. Values 7-8 (0x07-0x08, 0111b-1000b) of code 51a each map to a corresponding 8 bit byte segment B1 or B2 of the full 28 bit address, where; B1=[7:0] and B2=[8:15]. Values 9-10 (0x09-0x0A, 1001b-1010b) of code 51a each map to a corresponding 12 bit segment S1 or S2 of the full 28 bit address where S1=[15:4] and S2=[27:16].
To encode a full 28 bit address of a data/address pair sent to buffer 30 by bus 22, a comparison with the most recently sent previous address is performed. This comparison identifies any bits of the address presented for encoding (the current address) which differ from the most recent previous address sent.
If this comparison indicates that all the bits are same--the current address and the most recent previously sent address are identical--then the current address is not stored or encoded and the data word is stored in a logical location next to the most recently stored data as previously discussed. This technique eliminates storage of unneeded, consecutively redundant address information. Set 48 and group 50 provide examples of this technique.
On the other hand, if bits of the current address differ from the most recent previous address, then the segments of the current address represented by one or more of N1-N7, B1-B2, and S1-S2 of table 52 are identified which include all the changed bits. If the changed address bits cannot be fully encompassed by one of the bit ranges corresponding to segments N1, N2, N3, N4, N5, N6, N7, B1, B2, S1, S2; then the current address cannot be encoded by format 51 and table 52. As a result, the current address is stored in two memory locations 42 as in the example given for sets 44 and 50.
If the changed bit or bits provided by the comparison of the current address and the most recent previously sent address may be included in one or more of the table 52 segments (N1-N7, B1-B2, S1-S2), then an encoded address in accordance with format 51 is established and stored in one memory location 42.
To provide an encoded address, the shortest segment N1-N7, B1-B2, S1-S2 from table 52 which still encompasses all the changed bits is selected. The code 51a corresponding to this segment is written in range R4 of format 51. The changed bits corresponding to the segment from table 52 are written into the changed address portion 51b of format 51. If the segment is a nibble N1-N7, then the corresponding nibble of the current address which contains the changed bits is written into segment Nx of format 51. Segment Nx is written into range R1 and ranges R2, R3 are filled with 0 (R2, R3=0x00). If the shortest segment from table 52 that encompasses changed address bits is a byte (B1, B2), then the corresponding byte of the current address is written into segment Bx of format 51. Segment Bx is written into ranges R1, R2=[7:0] and range R3 is filled with 0 (R3=0000b). If the shortest segment from table 52 that encompasses the range of changed bits is a 12 bit segment, then the corresponding 12 bit segment from the current address is written into segment Sx of format 51, where segment Sx occupies ranges R1, R2, R3=[11:0]. As previously discussed, a changed bit segment of the current address which cannot be included within a full address range defined by table 52 (such as a segment of more than 12 bits), precludes encoding in accordance with format 51 and table 52. Consequently, the address is written into two memory locations 42 for this embodiment.
Referring additionally to FIGS. 4-6, a few examples of address encoding in accordance with format 51 and table 52 are provided. In FIG. 4, encoded address EX1 is illustrated. For EX1, the most recent previous address is designated by 0x8888888 and the current address is designated by 0x88F8888. From table 52, the code 51a values which apply are 0100b corresponding to nibble N5 and 1010b corresponding to segment S2. The smaller applicable segment is N5, therefore, code 51a is set to 0100b and stored in range R4 and the changed nibble N5 is stored in segment Nx (range R1) with ranges R2, R3 =0x00. Thus, EX1=0100 0000 0000 1111b=0x400F.
FIG. 5 depicts encoded address EX2 as another example of the encoding technique. For EX2, the most recently sent previous address is designated 0x9999999 and the present address is designated 0x999AA99. Because more than one nibble has changed, a code corresponding to a single nibble (one of N1-N7) cannot fully designate the bits of the current address. Thus, only the byte code valve 1000b designating byte B2 and the segment code valve 1001b designating segment S1 can encompass the changed bits. Applying the policy of selecting the segment with the least number of bits that encompass the change, code 51a is set to byte code 1000b (range R4) and segment Bx (ranges R1, R2) is set to 0XAA=1010 1010b. The remaining nibble, range R3, is set to 0000b, so that EX2=1000 0000 1010 1010b=0x80AA.
FIG. 6 shows encoded address EX3. For EX3, the most recently sent previous address is designated as 0xBBBBBB and the current address is designated as 0x555BBB. Because the segment encompassing the changed bits exceed a byte, then the applicable code value 1010b corresponding to segment S2 applies. Correspondingly, encoded address EX3 has code 51a set to 1010b and the remaining bits, corresponding to segment Sx (ranges R1, R2, R3), are set to 0x555=0101 0101 0101b. Thus, EX3=1010 0101 0101 0101b=0xA555.
It should be noted that not all possible combinations of address bit changes may be encoded with table 52. Preferably, the particular encoded portions, such as nibbles (4 bits), bytes (8 bits) and 12-bit segments, are selected to correspond to the particular application. For example, if a system frequently writes to the same eight locations, then nibble codes would likely be preferred. If a different system frequently transfers information between two banks of memory that are widely separated in the memory map, then codes for the 12-bit groups would be more efficient. In still other embodiments, non-contiguous groups of bits expected to change in a predetermined pattern may be designated by a selected code. Typically, the particular code arrangement will vary with the bit-width of the data, the bit-width of the address, the application, and the relative difference between the data and address format.
FIGS. 7A and 7B depict an uncoded address resulting when the difference between the previous and current addresses cannot be encoded in accordance with format 51 and table 52. For this example, the previous address is given as 0x4444244 and the current address is given as 0x4D442D4. Although both segments S1 and S2, corresponding to codes S1a of 1001b and 1010b collectively encompass the changed bits, only one 12 bit segment may be accommodated by segment Sx of format 51. As a result, two memory locations 42 are utilized to store the address. The two words of the 28 bit address are illustrated as Word W0 in FIG. 7A and Word W1 in FIG. 7B. Nonetheless, in other embodiments, the mapping of table 52 may be adjusted to accommodate the widely spaced bit differences presented in FIGS. 7A and 7B. For instance, a code value of 1011b could be used to write a segment Bx mapped to the non-contigent nibbles N6 and N2, such that Bx=N6N2=0XDD. Such other variations as would occur to those skilled in the art are also within the spirit of the present invention.
Referring back to FIG. 3, it should be noted that when FIFO 40 is empty, the first address stored in FIFO 40 will generally occupy two memory locations 42 in the manner indicated for set 44. However, depending on the particular encoding table, it is likely that the next address may be compressed into one word such as illustrated for set 46. Similarly, set 48 depicts encoded address EA2. Encoded address EA2 is determined by comparing the current full address to the full address corresponding to EA1. As a result, the full address corresponding to the most recently written address information, whether encoded or not, is retained for comparison to the next full address. If the next full address is the same, then it is discarded. If it is different, then it is stored in FIFO 40 as a full address or an encoded address in accordance with table 52. In either case, the full address is retained for the next comparison until a later address is stored in the full or encoded address format.
Referring additionally to FIG. 8, further details concerning one implementation of the encoding and decoding techniques within buffer 30 are illustrated. Bus 22 is illustrated with 28 address lines 22a and sixteen data lines 22b operatively coupled to buffer 30. Similarly, bus 24 is operatively coupled to buffer 30, by twenty-eight address lines 24a and sixteen data lines 24b. Preferably, bus 22, 24 and the respective interfaces with buffer 30 are of a conventional variety. Within buffer 30, address lines 22a are input to comparator 54 and MUX/encoder 56. The output of comparator 54 is also input to MUX/encoder 56. Data lines 22b are operatively coupled to input 58a of to multiplexer 58. Input 58b of multiplexer 58 is operatively coupled to the output of MUX/Encoder 56. The output of multiplexer 58 is operatively coupled to input port 40a of FIFO 40.
Write logic 60 is operatively coupled to comparator 54 and MUX/encoder 56 to direct operation thereof. Write logic 60 is also operatively coupled to FIFO manager 62 to provide a WRITE signal thereto. Write logic 60 receives input signal W along control coupling 22c and various inputs from FIFO manager 62. Signal W initiates storage of a data/address pair from bus 22 into buffer 30. Under direction of write logic 60, comparator 54 provides for the comparison of the current address and the most recently sent previous address. In addition, write logic 60 directs MUX/encoder 56 to assemble an encoded address in accordance with format 51 and table 52, sends through each word of a full two word address, or ignore the address as determined from the output of comparator 54. When encoding, MUX/encoder 56 generates the code value, appends the appropriate differing bit segment (N1-N7, B1-B2, or S1 or S2) from the current address, and fills with zeros as required.
FIFO manager 62 controls the input and output of digital information from FIFO 40. FIFO manager 62 cooperates with write logic 60 and read logic 64 to collectively provide buffer control logic 32. Manager 62 includes a write pointer WP designating the next memory location 42 for a write or store operation. Also, manager 62 includes a read pointer RP to designate the next location available for output to bus 24 via output port 40b. As a result RP points to logical location L1. In addition, manager 62 includes the logic necessary to determine whether one, two, or more than two locations are available for a write operation corresponding to signals L1, L2, L3, respectively. Furthermore, manager 62 is configured to generate a FULL signal when all locations of FIFO 40 have been written. Similarly, manager 62 is configured to generate an EMPTY signal when all locations written to FIFO 40 have been read.
Read logic 64 is coupled to FIFO manager 62 and receives the EMPTY signal therefrom. The FULL and EMPTY signals are also distributed to busses 22 and 24 for reception by corresponding bus managers along control couplings 22c, 24c, respectively. Read logic 64 is configured to recognize and decode the encoded addresses stored in FIFO 40. Read logic 62 responds to signal R from coupling 24c to initiate output of a data/address pair from buffer 30 onto bus 24. Read logic 64 provides a READ signal to FIFO manager 62 to initiate a read of data or address. Read logic 64 is coupled to flag bits 42a by lines 66a, 66b, to input the flag bits of the next two memory locations 42 to be read. These bits are examined to determine whether a full address (2 words), an encoded address (1 word), or a data word to be output next. Read logic 64 directs address MUX/decoder 68 to regenerate the full address by substituting the changed segment of the address being read into the previous output address in latch 70. Notably, data read from FIFO 40 is presented directly from output port 40b to bus 24 via data lines 24b. Address latch 70 is coupled to bus 24 via address lines 24a and contains the most recently output address of an address/data pair. Notably, various different control signals and status signals may be included as part of couplings 22c, 24c and 25.
FIG. 9 depicts state diagram 600 corresponding to the operation of write logic 60. Write logic 60 idles in state 601 if there is no active write operation signal W (W=0) or FIFO 40 is full as indicated by activation of signal FULL (FULL=1); such that logic 60 idles as long as (W'+FULL=1). As used herein, a prime (') or an overbar indicates the inverted boolean value of the associated signal or variable. Once signal W is active (W=1), and FULL is inactive (FULL=0), such that (W* FULL=1); then operation proceeds to state 602. In state 602, a comparison with comparator 54 is activated to compare the full two word address currently on lines 22a with the previous full two word address stored in comparator 54. The previous full address stored in comparator 54 is the previous address most recently sent to FIFO 40 by bus 22, which was stored as a full address in two memory locations 42 or stored in encoded form in one memory location 42. Write logic 60 examines any differences detected by this comparison to decide whether two locations, one location, or no locations need to be stored in FIFO 40.
If FIFO 40 is empty (EMPTY=1) or the difference between the current and previous address determined in state 602 cannot be encoded in accordance with table 52, then a full two-word address is needed which activates IFA (IFA=1). Furthermore, if FIFO manager 62 indicates that two or more consecutive locations are available by setting signal L3 active (L3=1), then operation proceeds to state 603 (IFA*L3=1).
In state 603, write logic 60 directs MUX/encoder 56 to put the first address word (word 0) on the output and correspondingly directs multiplexer 58 to present word 0 of the address to input port 40a of FIFO 40. Also, an appropriate bit of input port 40a is set by MUX/encoder 56 to activate corresponding flag bit 42b. Write logic 60 generates a WRITE signal and sends it to manager 62 to write address word 0 (with bit 42a set) to the location designated to by pointer WP. The specific operation of manager 62 in response to the WRITE signal is further detailed in state diagram 620 of FIG. 10 described more fully hereinafter.
After storing address word 0, control flows to state 604 where the output of MUX/encoder 56 presents address word 1 to multiplexer 58. Logic 60, directs multiplexer 58 to input word 1 to input port 40a of FIFO 40 with corresponding flag bit 42b set. Write logic 60 sends an active WRITE signal (WRITE=1) to manager 62 to provide for the storage of word 1 immediately after word 0 to conclude state 604. Operation then proceeds to state 605 where multiplexer 58 is directed to present the data from line 22b of bus 22 to input port 40a of FIFO 40. Write logic 60 then sends an active WRITE signal (WRITE=1) to manager 62 to write the data into the next location of FIFO 40. Notably, the address flag 42b is not set for the data write operation of state 605. The write cycle is then complete and control flows back to wait state 601 of state diagram 600 to idle until the next active write signal W (W=1) and not FULL (FULL=0) condition.
Returning to state 602, if the comparison of the current and previous address indicates the current address may be encoded in accordance with table 52, then an encoded address input is indicated which sets signal IEA active (IEA=1). Furthermore, if manager 62 indicates that at least two locations of FIFO 40 are available, as indicated by an active signal L2 (L2=1), then control proceeds to state 605 (IEA* L2=1). In state 605, the difference between the current and previous address is evaluated by logic 60 and the corresponding code from table 52 is generated. The generated code 51a and corresponding changed address portion 51b are output by MUX/encoder 56 under the direction of logic 60. For example, logic 60 directs MUX/encoder 56 to output code 51a in range R4 and selects the portions of the current and most recently sent previous address to combine as portion 51b. Write logic 60 directs multiplexer 58 to present the resulting encoded address to input port 40a of FIFO 40 and activates an appropriate bit to set the corresponding flag bit 42b. Write logic 60 then sends an active WRITE signal (WRITE=1) to manager 62 to write the encoded address and flag bit 42b into the memory location 42 designated by pointer WP. Control then flows to state 606 where data is directed to input port 40a of FIFO 40 by write logic 60 via multiplexer 58 and subsequently stored before returning to wait state 601.
If the comparison of state 602 determines that the current and previous addresses are the same then no address information is stored and signal ISA is set active (ISA=1). If at least one location 42 is available in FIFO 40, then signal L1 is set active (L1=1). When both ISA and L1 are active, (ISA*L1=1), then control flows directly from state 602 to state 606 to write the corresponding data word to FIFO 40 at the memory location 42 designated by pointer WP. Control then returns to the wait state 601 until another write operation is initiated by signal W.
FIG. 10 depicts a state diagram 620 for the operation of the FIFO manager 62. State 621 of state diagram 620 is a wait state. If an active WRITE signal is received (WRITE=1), then control flows to state 622. This signal is sent by write logic 60 in states 603, 604, 605, and 606 of state diagram 600. In state 622, the word 42a and flag bit 42b presented at input port 40a of FIFO 40 are stored in the memory location 42 of FIFO 40 designated by write pointer WP. The operation then flows to 623 which evaluates the memory location 42 designated by write pointer WP and the memory location 42 designated by read pointer RP (logical location L1) to determine how many memory locations 42 are still available for writing. In response, the signals L1, L2, L3 are updated accordingly and the signal FULL is set (FULL=1) if there are no locations available. If FULL=1, then control returns to wait state 621. If FULL is not active (FULL=0, FULL'=1), then control advances to state 624. In state 624, the write memory pointer WP is advanced to the next memory location 42 available for storage, then control returns to wait state 621.
State diagram 620 also describes the FIFO reading operation for manager 62. Beginning with wait state 621, if a active READ is received from read logic 64, then the operation advances to state 625. In state 625 the contents of memory location 42 designated by pointer RP (logical location L1) is output at output port 40b of FIFO 40. Control then flows to state 626 to evaluate the locations designated by the read pointer RP and write pointer WP. The state 626 evaluation determines memory location 42 availability and updates L1, L2, L3 accordingly. If it is determined that all memory locations 42 have been read, then the EMPTY signal is set active (EMPTY=1) and control flows back to the FIFO manager wait state 621. On the other hand, if EMPTY is inactive (EMPTY=0, EMPTY'=1), then control advances to state 627. In state 627, the read pointer RP is advanced to the next location designated for output on a first-in first-out basis. Control then returns the wait state 621.
FIG. 11 further describes the operation of read logic 64 with state diagram 640. State 641 is a wait state. If signal R is inactive (R=0, R'=1) or FIFO 40 is empty as designated by an active EMPTY signal (EMPTY=1), then read logic 64 continues to idle at state 641 (R'+EMPTY=1).
On the other hand, if R is active (R=1) and EMPTY is inactive (EMPTY=0, EMPTY'=1), such that (R*EMPTY'=1), then operation flows to state 642. In state 642, read logic 64 interrogates the flag bit 42b for the output location designated by RP and for the next output location to be read after RP (RP+1) to determine whether a one word encoded address, a full two-word address, or data is to be output through output port 40b of FIFO 40. If a full address output is indicated, (two flag bits 42a set in a row), then signal OFA is set active (OFA=1). As a result, operation flows to state 643. In state 643, read logic 64 sends a READ signal to manager logic 62 and latches the first address word (WORD 0) from the memory location 42 designated by pointer RP into latch 70. Control then flows to state 644. In state 644, another READ signal is sent to manager 62, and the second address word (word 1) is latched into latch 70 as directed by decoder 68 via read logic 64. Control then flows to state 645 where another READ signal is sent to manager 62 to output the data corresponding to the full two-word address output through states 643 and 644. In state 645, data is output from port 40b directly to bus 24 via lines 24b by sending a READ to FIFO manager 62.
If the interrogation of state 642 detects an encoded address (one flag bit 42a set), then signal OEA is active (OEA=1), and control flows to state 646. In state 646, read logic 64 sends a READ signal to manager 62 and activates MUX/decoder 68 to insert the changed address portion 51b corresponding to segment (Nx, Bx, or Sx), as determined from code 51a, into the previous address remaining in address latch 70 from the most recent previous read operation. Control then continues to state 645 where another READ signal is sent by read logic 64 to manager 62 to output data from port 40b directly to bus 24 via lines 24b. The read cycle is then complete and control returns to wait state 641 to idle until another read cycle is activated.
If the interrogation of state 642 indicates that two data words are next to each other (two consecutive flag bits 42b not set), then signal OSA becomes active (OSA=1), indicating that data having the same address as the most recently read address is being output. State 645 is triggered by OSA=1 and read logic 64 sends a READ signal to manager 62 to output the data word designated by read pointer RP on port 40b of FIFO 40. Control then returns to idle at wait state 641 until the next occurrence of R*EMPTY'=1.
In alternative embodiments, the system defined herein may be embedded into one or more logic devices, programmed in software or firmware, or provided by a combination thereof using techniques known to those skilled in the art. Furthermore, while the preferred embodiment illustrates a buffering operation between two parallel bus configurations, it is envisioned that other embodiments may include serial busses, busses that multiplex data and address information, or a single bus having both a read and write interface with buffer 30. In still other embodiments, the compression technique of the present invention may be used for FIFO storage of groups containing data and associated addresses for purposes other than buffering.
In addition, the present invention may be adapted to recognize additional information types besides data/address pairs. By way of non-limiting example, an additional flag bit could be employed to designate an information type which has no associated address--with control logic 32 configured accordingly. In addition, undesignated code values 1011b-1111b may be used to designate different digital information arrangements or blocks other than data/address pairs.
Furthermore, in another embodiment it is recognized that instead of halting writes and reads when the FIFO is full or empty, respectively; the FIFO may be configured in a circular fashion to overwrite the least recently written information when full, or re-read the least recently read information when empty. In still other embodiments the FULL or EMPTY signals may be utilized by devices coupled to busses 22 and 24 to provide for FIFO underflow or overflow control. It is also envisioned that the memory and logic devices disclosed herein may be provided by one or more solid state devices, optical devices, electromagnetic devices, or such other variety as would occur to one skilled in the art. Also, it is recognized that conflicts between reads and writes cycles may be arbitrated as part of the manager logic 62 of buffer 30, or arbitrated by devices and systems external to system 30.
All publications, patents, and patent applications cited in this specification are herein incorporated by reference as if each individual publication, patent, or patent application were specifically and individually indicated to be incorporated by reference.
While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only the preferred embodiment has been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.
|Cited Patent
|Filing date
|Publication date
|Jul 2, 1976
|Jun 13, 1978
|International Business Machines Corporation
|First in-first out memory array containing special bits for replacement addressing
|Jun 5, 1980
|Apr 6, 1982
|International Telephone And Telegraph Corporation
|Elastic storage and synchronization control apparatus for use in a telephone switching system
|Sep 14, 1984
|Jul 22, 1986
|Kabushiki Kaisha Toshiba
|Storage of image data in both original and compressed forms
|Aug 19, 1985
|Jun 14, 1988
|American Telephone And Telegraph Company, At&T Bell Laboratories
|Memory access circuit with pointer shifting network
|Mar 31, 1987
|Jul 4, 1989
|U.S. Philips Corporation
|Memory comprising simultaneously addressable memory elements
|Oct 1, 1991
|Oct 12, 1993
|Mitsubishi Denki Kabushiki Kaisha
|Semiconductor memory used for changing sequence of data
|Aug 21, 1991
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|Digital Equipment Corporation
|Graphics command processing method in a computer graphics system
|Dec 1, 1992
|Aug 23, 1994
|C-Cube Microsystems, Inc.
|System for compression and decompression of video data using discrete cosine transform and coding techniques
|Oct 31, 1990
|Nov 22, 1994
|Waferscale Integration, Inc.
|Programmable controller
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|Dec 6, 1994
|Digital Equipment Corporation
|Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching
|Jul 22, 1994
|May 9, 1995
|Motorola, Inc.
|Method and data structure for performing address compression in an asynchronous transfer mode (ATM) system
|Mar 11, 1994
|Aug 8, 1995
|Motorola, Inc.
|Variable length string matcher
|Jun 4, 1992
|Sep 12, 1995
|International Business Machines Corporation
|Sequential pipelined processing for the compression and decompression of image data
|Dec 30, 1992
|Dec 5, 1995
|Intel Corporation
|FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers
|Aug 11, 1994
|Dec 19, 1995
|Fujitsu Limited
|Memory control device
|Nov 23, 1994
|Jan 23, 1996
|Samsung Semiconductor, Inc.
|Page-in, burst-out FIFO
|Aug 2, 1993
|Feb 20, 1996
|Motorola, Inc.
|Addressing method for conserving power in distributed information receivers
|Apr 29, 1994
|Jun 11, 1996
|Winbond Electronics Corp.
|Serial access memory device
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|Jul 9, 1996
|Sun Microsystems, Inc.
|TCP/IP header compression X.25 networks
|May 18, 1994
|Aug 27, 1996
|Altera Corporation
|Programmable logic array integrated circuits
|Apr 24, 1995
|Nov 19, 1996
|Canon Kabushiki Kaisha
|Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation
|Mar 18, 1996
|Dec 31, 1996
|Nec Corporation
|Memory data copying apparatus
|Jun 29, 1994
|Apr 1, 1997
|The 3Do Company
|Method for communicating a value over a transmission medium and for decoding same
|Jul 15, 1993
|Jun 24, 1997
|Unisys Corporation
|Invalidation queue with "bit-sliceability"
|Degermark et al. "Header compression for IPv6," [Online] http://www.dc.luth.se/doc/id/draft-degermark-ipv6-hc-02.txt, Nov. 1996.
|Degermark et al. Header compression for IPv6, Online http://www.dc.luth.se/doc/id/draft degermark ipv6 hc 02.txt, Nov. 1996.
|Faber et al. "A Thinwire Protocol for connecting personal computers to the Internet," RFC914, [Online] http://www.faqs.org/rfcs/rfc914.html, Sep. 1984.
|Faber et al. A Thinwire Protocol for connecting personal computers to the Internet, RFC914, Online http://www.faqs.org/rfcs/rfc914.html, Sep. 1984.
|Jacobson, V. "Compressing TCP/IP Headers for Low-Speed Serial Links," RFC 1144, [Online] http://www.strategis.com/rfc/RFC11XX/rfc1144.ps, Feb. 1990.
|Jacobson, V. Compressing TCP/IP Headers for Low Speed Serial Links, RFC 1144, Online http://www.strategis.com/rfc/RFC11XX/rfc1144.ps, Feb. 1990.
|Stallings, W. "IPv6: The New Internet Protocol," IEEE Communications: 96-108, Jul. 1996.
|Stallings, W. IPv6: The New Internet Protocol, IEEE Communications: 96 108, Jul. 1996.
|Citing Patent
|Filing date
|Publication date
|Oct 1, 1999
|Sep 2, 2003
|Hitachi, Ltd.
|Circuit for storing trace information
|Oct 1, 1999
|Jan 27, 2004
|Hitachi, Ltd.
|Circuit for processing trace information
|Oct 1, 1999
|May 4, 2004
|Hitachi, Ltd.
|Apparatus and method for storing trace information
|Oct 1, 1999
|Jul 12, 2005
|Hitachi, Ltd.
|Method for compressing and decompressing trace information
|Oct 2, 2001
|Jan 24, 2006
|National Taiwan University
|Self-routing data switching system
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|Oct 10, 2006
|Micron Technology, Inc.
|Column/row redundancy architecture using latches programmed from a look up table
|Oct 11, 2006
|Mar 17, 2009
|Micron Technology Inc.
|Column/row redundancy architecture using latches programmed from a look up table
|Feb 13, 2009
|Mar 22, 2011
|Micron Technology, Inc.
|Column/row redundancy architecture using latches programmed from a look up table
|Apr 16, 2001
|Jan 3, 2002
|Mark Vange
|Method and system for redirection to arbitrary front-ends in a communication system
|Oct 2, 2001
|Apr 3, 2003
|National Taiwan University
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|Jan 29, 2004
|Vinod Lakhani
|Column/row redundancy architecture using latches programmed from a look up table
|Oct 11, 2006
|Feb 15, 2007
|Vinod Lakhani
|Column/row redundancy architecture using latches programmed from a look up table
|Feb 13, 2009
|Jun 11, 2009
|Vinod Lakhani
|Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table
|Oct 27, 2008
|Aug 11, 2011
|Micro Motion, Inc.
|Method and apparatus for compressing and decompressing data records
|U.S. Classification
|711/212, 710/52, 341/76
|International Classification
|Cooperative Classification
|European Classification
|May 20, 1997
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text:
Hotel Esmeralda
No prices found through our partners. Please contact the business directly or check some of our recommended alternatives.
How has this hotel rated in the past?
Travelers also recommend:
TravelPod Member ReviewsHotel Esmeralda Coroico
Expensive for a town which offers several accommodation options but slightly more reasonably priced without breakfast. Clean rooms and bathroooms. Good food from restaurant and very friendly barman. INCREDIBLE SETTING AND VIEWS OF THE VALLEY plus pool. If you decide to walk to the waterfalls, avoid the path up the hill near the church as there is a huge dog there that bites! Very scary experience - ask hotel staff for better route before you set off.
B$150 with shared bathroom, without breakfast.
This review is the subjective opinion of a TravelPod member and not of TravelPod.com.
Stayed in the dorm room, Clean nice bunk beds, hot water and clean amenities. AMAZING views out over the Yungas shame about the lack of smile and friendlyness of the manageress!
This review is the subjective opinion of a TravelPod member and not of TravelPod.com.

subset: commoncrawl


text:
Atrial Fibrillation Health Center
How Do New Blood Thinners Compare to Warfarin?
Not too long ago, if your doctor said you needed a blood thinner to prevent a stroke, you didn't have to think too hard about it. Warfarin (Coumadin) was the only way to go. But not anymore. With four other medications to pick from, you'll have to do a little homework to figure out what's best for you.
"It's not a one-size-fits-all choice," says Bruce Lindsay, MD, from Cleveland Clinic. A lot depends on your overall health and your lifestyle.
Recommended Related to Atrial Fibrillation
Atrial Fibrillation (AFib) Myths and Facts
Atrial fibrillation, also known as AFib, happens when your normal heartbeat or rhythm is thrown off. Yes, it can be dangerous. Your heart may not be able to pump enough blood. On the other hand, millions of people with long-lasting AFib live quite well, says Gordon F. Tomaselli, MD, chief of the division of cardiology at Johns Hopkins University School of Medicine. "It's very possible to live a normal life for many years." So let's clear up those ideas that may be limiting you when they don't...
Read the Atrial Fibrillation (AFib) Myths and Facts article > >
What Are My Options?
Besides warfarin, you and your doctor will take a look at these new drugs:
- Apixaban (Eliquis)
- Dabigatran (Pradaxa)
- Edoxaban (Savaysa)
- Rivaroxaban (Xarelto)
Which One Works Best?
Studies show the latest drugs work as well as warfarin. But trying to figure out how the new medicines compare to each other is a bit trickier. There isn't any research that compares them head to head.
"We can't rank the new ones from one to four," says Richard Kovacs, MD, clinical director of Krannert Institute of Cardiology at Indiana University. "We don't have enough data to suggest one of them over another."
Are the New Drugs Safer?
No matter which one you use, there will be a risk of bleeding problems. Blood thinners work by making it hard for clots to form. That's a good thing when you're trying to prevent a stroke, but it's not so great if it makes it tough to stop a cut from healing.
It's less of a risk with the new medications. And since they wear off faster than warfarin, bleeding problems may not be as serious when they happen.
If you get a dangerous bleeding problem while taking warfarin, doctors can turn to an "antidote" of Vitamin K or a combination of prothrombin complex concentrate (PCC) and fresh frozen plasma to stop it. In addition, approval has been given for using idarucizumab (Praxbind) in emergencies to reverse the anit-clotting effects of Pradaxa.
How Do the New Drugs Fit Into My Lifestyle?
They have convenience on their side. You don't need as many blood tests. With warfarin, you need them at least once a month to make sure it's working right.


text:
The directory below provides a listing of current staff, core faculty, faculty affiliates, and students of the Program in Arms Control & Domestic and International Security (ACDIS) at the University of Illinois. Click on an individual's name to view detailed information about that person. ACDIS also maintains listings of alumni of the program.
Staff | Core Faculty | Faculty Affiliates | Research Associates | Graduate Students | Visiting Scholars | go to the Alumni directory page
Office Manager
Core Faculty
ACDIS core faculty members have academic appointments at the University of Illinois through home disciplinary departments. However, they interact closely with ACDIS by participating in the program's research initiatives and policy engagement activities, contributing to ACDIS publications, and teaching international security courses.
Computer Science
Art + Design
Political Science
Physics and Astronomy
Political Science
Philosophy and Law
Political Science
Lecturer in Global Studies
Faculty Affiliates
ACDIS faculty affiliates are employed as faculty or research scholars at institutions other than the University of Illinois. These individuals retain close connections with ACDIS and interact on a periodic basis with the program.
International Studies, Bradley U.
Political Science & History, Brookings Inst.
University of Texas-Dallas
Political Science, University of Alabama
Political Science
Science and Peace Research, University of Hamburg
International Studies, University of Miami
Political Science & Asian Studies, U. of Cincinnati
Geography, U. of Kansas
Geography, Ball State University
Stanton Fellow, RAND
Geography and KlimaCampus, University of Hamburg
Political Science & History
Atmospheric Sciences
Graduate Students
Political Science
Political Science
Political Science
Political Science
Political Science
Political Science


text:
Diesel Generator Dealer In Nagpur
- View All ▼
Electrical Services
Electrical Contractor In Nagpur
Contractor For HT And LT UG Cabling Line In Nagpur
Contractor For Overhead Line & Substation In Nagpur
Contractor For Street Lighting In Nagpur
AMC For HT And LT Installation In Nagpur
HT And LT Hardware Suppliers In Nagpur
AMC For Diesel Generator
Electrical Transformer Services In Nagpur
New Items
Electrical Services
Electrical Installation
We are engaged in offering reliable services for electrical installation. Under these services, we undertake large scale projects and contracts for electrical installation in various industries. We also provide these services for residential establishments. For this, we make use of is standard equipment as per the application requirements. Further, we carry forward all the activities keeping in view the safety measures. All these services are rendered using advanced technologies as per the set industrial standards.
33/11KV Substation
Our clients can avail from us services for the maintenance of 33/11 kv substation. Under these services, we undertake protection and automation of all types of electrical substations. We hold vast experience in this domain, which enables us to cater to the needs of our clients in best possible manner. We make use of advanced technologies to render these services and work as per the exact needs of our clients.
Annual Maintenance Of Transformer Substation
Our clients can avail from us reliable solutions for Annual Maintenance Of Transformer Substation. Our teammates work hard to maintain all the operations of the substation. All these activities take place under the close supervision of our experienced engineers. They ensure the safety measures so as to ensure standards in our services. We ensure that all these services are rendered as per the international standards to ensure reliability.
Electrical Consultancy
Owing to our expertise in the domain, we have been able to offer services for electrical consultancy. These services cover various factors related to electrical power system such as cable sizing, single-line diagrams, load calculations and fault studies. Our services also cover control system design and power distribution & associated consultation. For this, we have hired a team of proficient workers, who hold vast practical experience in this domain.
To,Carways Engineers And Contractors


text:
Simply Brittany Marie (ebook)
by Friend O. Brittany
This book contains fine-art nudes and glamour images of the beautiful Brittany Marie. She's an incredibly talented, beautiful and charming young lady and I think it shows through in her nudes. She has an incredible face and figure with an innocent girl-next-door attitude intertwined with her sexuality.
Category: Fine Art Photography


text:
American English: /ˌjuθəˈneɪʒ(i)ə/ , /ˌjuθəˈneɪziə/ British English: /ˌjuːθəˈneɪzɪə/
Translation of euthanasia in Spanish:
- Example sentences
- Once the disease reaches this stage, euthanasia or mercy killing is the only recourse.
- This separation has not resulted in moral desensitisation of assisted suicide and euthanasia.
- Forty per cent of the doctors said they had been asked by patients to assist in their suicide or in euthanasia.
Definition of euthanasia in:
What do you find interesting about this word or phrase?
Comments that don't adhere to our Community Guidelines may be moderated or removed.
Grammar and usage help for Spanish:
= trending


text:
Overnight (literally), I "lost" home use of a pair of i5 / 8GB / Win 8.1 Laptops (Lenovo and Asus) I used for home development.
I use Visual Studio 2013 and Sql Server. Besides that I surf the web. I'm not a gamer! So while my apps are memory hogs, I don't run a production DB. Just development level.
Both computer losses are temporary:
The Lenovo motherboard burned out and Lenovo will replace it. But this could take while (I've read about Lenovo's service track record and they already warned me the mother board is on back order).
I use the Asus at a client site for next 2 months.
I also have Desktop with an underwhelming AMD E2-3200 processor (benchmark), 4GB RAM / Win 7 64bit (3.49GB RAM usable,graphics card hoggs 510MB). I have run VS2012 on it, but have never leaned on it and have never run a DB on it.
Instead of buying a home development machine for what seems like a 2 month gap until I get both back, can I get good performance boost by upgrading the desktop to 8GB RAM and 120GB internal ssd drive.
I've priced this option out to be less than $150.


text:
There Will Be "No Reinventing" of the President
"There's no need to," says Axelrod.
White House senior adviser David Axelrod is shaking off suggestions that Obama's re-hiring of David Plouffe to run the midterm campaigns is a sign that the president is reinventing himself, telling Politico "There's no need to." Axelrod also says the same forces that got Obama elected, a desire for change, got Scott Brown elected in Massachusetts. [Politico]


text:
Nicole Richie
Nicole Richie in Levi's Cut off Shorts
Nicole Richie showed off her long legs in a pair of her Levi's cut off shorts while out running errands in Studio City. We see Nicole out in shorts quite frequently, usually a distressed or vintage pair.
I am surprised that we haven't seen her try out the overall trend, especially in a shorter length. I could definitely see her wearing a pair with a cropped top or even around her waist like we've seen Gwen Stefani style them lately.
Nicole Richie in Citizens of Humanity Rocket in Black Diamond
Nicole Richie was spotted walking to her car ahead of promoting her new show Candidly Nicole in New York. The socialite wore a pair of the Citizens of Humanity Rocket in Black Diamond with a muscle shirt and some pumps. She then finished her look off with some Chanel suspenders.
Nicole is very petite, but I find these jeans to be really flattering on her. Well actually, I haven't really seen the Rockets by Citizens look bad on anyone. They really are the perfect pair of high-waisted jeans if you are looking for that style. You can click here to purchase these jeans from the Citizens of Humanity website.
Nicole Richie in Acquaverde Jeans Skinny Jeans in White
Nicole Richie was photographed while heading into MTV Studios to promote her newest show, Candidly Nicole. The show is based off of her Twitter. I love Nicole's tweets, they always crack me up, so I am sure the show will be equally as funny!
For her appearance, Nicole wore a pair of Acquaverde white skinny jeans with a white lace cut out Givenchy sweatshirt and white heels. I like that Nicole chose all white for the outfit, I always thinks it looks really fresh and her purple hair is a great splash of color! You can buy Acquaverde online from Revolveclothing.com.
Nicole Richie in GENETIC Shya Skinny Jeans in Gaze
Nicole Richie was escorted by some bodyguards through the airport after arriving in Sydney, Australia. I wonder if she is in town because husband Joel Madden is back on The Voice? The socialite wore her favorite pair of grey jeans by GENETIC. She wore the Shya in Gaze with some patent ankle boots and a long grey coat.
I wonder what other styles by GENETIC we will be seeing on Nicole? I would like to see her wear a pair of their leathers or maybe a distressed style. I think their Loren in Destroy would look awesome paired with her ankle boots. You can click here to purchase these jeans from the GENETIC website for $213.


text: I am currently building my blog. When I import my saved work, the website theme always pops up as the classic and not the theme that I chose. Also, all of the example post, pages and links pop back up...the links that I created did not upload. What am I doing wrong or how can I disable these defaults?


text:
OS X Support Essentials (Apple Pro Training Series)
by Kevin M White and Gordon Davisson.
Peachpit Press
Pearson Education
Price: $64.99
Mountain Lion (Mac OS 10.8) has matured remarkably quickly. As has now become the norm, printed guides, tutorials, reference books and introductions of all sorts have appeared equally speedily in the months following Mountain Lion's release. Indeed, we have already reviewed Galen Gruman's "Bible" (Wiley).
Most of these titles reflect the fact that, good and stable though it is, Mountain Lion has few startling or groundbreaking aspects. It hardly contains enough new features to fill a substantial book of its own. So it is with this Mountain Lion volume in the Apple Pro Training Series, OS X Support Essentials, by Kevin M White and Gordon Davisson.
Actually, it's only in the subheading, "Supporting and Troubleshooting OS X Mountain Lion", that you know that this is indeed a book for users of the latest Apple OS. But it is; and it does its job extremely well. So well, in fact, that it should be considered a leader in the couple of dozen or so books available now.
Continue reading »
Continue reading »
About Mark Sealey
Mark Sealey is a British expatriate working and living in Southern California with his artist/writer wife, Roberta Lannes-Sealey, whom he met in 1996, when the web, she and he were much younger. Mark's interest in computers began in the the early '80s when his father suggested that, If we don't understand how to control them, they'll creep up behind us and make life unbearable. Have they? Using the venerable Acorn system until his move to the US, Mark wrote extensively about the BBC and RISC machines. He concentrated chiefly on education, music and productivity/system software; at the time Micronet and Prestel led the way for wide area networking… he published over 2,000 articles for these outlets. After graduating with a humanities degree, Mark was a teacher for 20 years until 1994 - first in Italy then the UK. Becaming increasingly attracted to the world of information technology as a major contributor to children's learning and development, he eventually moved to editing the UK's chief journals in the educational computing. He has always enjoyed freelance reviewing, consulting, editing and writing. When he moved to the US, he was fortunate enough to find full time employment at a major arts non-profit as a software engineer; though it's doubtful if there's a single skill which he was originally hired to use that's still in daily use. Mark is also a composer of chamber and orchestral music, music critic, a published poet, photographer and environmentalist with an enthusiasm for fitness, vegan nutrition and long distance running. He is now convinced that only humans' humility can save our planet.
- Web |
- More Posts (41)


text:
I will miss those Jay Wilson comments on youtube... :p
18/01/2013 12:27Posted by TheColonelI really want the new lead developer of the came to say this : "We see that the community wants PvP really bad, so we will focus on the patch 1.1 now"
17/01/2013 20:00Posted by ThyveneI will be moving off of the Diablo III project and transitioning elsewhere within Blizzard.
Without Jay Wilson at the helm this game can only get better. Good riddance to bad rubbish!
Oh, and Blizzard? Keep him away from Project Titan as far as possible!
Put him on WoW when you start your new MMO so players will change game
Threats of violence. We take these seriously and will alert the proper authorities.
Posts containing personal information about other players. This includes physical addresses, e-mail addresses, phone numbers, and inappropriate photos and/or videos.
Harassing or discriminatory language. This will not be tolerated.


text:
Cello Group Reunion
Reporter Alice Furlaud visits a group of cellists who gather twice a year in Boston for a multi-cello jam session.
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text:
List of airports in Croatia
From Wikipedia, the free encyclopedia
This is a list of airports in Croatia, grouped by type and sorted by location.
Airport names shown in bold indicate the airport has scheduled service on commercial airlines.
See also[edit]
- Transport in Croatia
- List of airports by ICAO code: L#LD – Croatia
- Wikipedia:WikiProject Aviation/Airline destination lists: Europe#Croatia
- "ICAO Location Indicators by State" (PDF). International Civil Aviation Organization. 17 September 2010.
- "IATA Airline and Airport Code Search". International Air Transport Association.
- "UN Location Codes: Croatia". UN/LOCODE 2012-1. UNECE. 14 September 2012. – includes IATA codes
- "Airports in Croatia". World Aero Data. – ICAO codes
- "Airports in Croatia". Great Circle Mapper. – IATA and ICAO codes


text:
Marine mammal rescue crews from the Dolphin Research Center and the Miami Seaquarium were working to save the manatee Thursday and Friday but were unable to catch it before dark.
The manatee was spotted by boaters at Sunshine Key Marina early Thursday morning with several fresh boat-propeller scars on its head.
Crews tried for hours to get the manatee on the boat ramp, where it could be transported into a waiting truck.
Dolphin Research Center spokeswoman Mary Stella said the animal likely would need to be brought to the Miami Seaquarium for
treatment of its injuries because it is the nearest facility equipped to handle manatees.
(Copyright 2008 by The Associated Press. All Rights Reserved.)


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Posts in Mobile
In-app advertising: One user's experience
Over the past few months our Internet Statistics Compendium has seen some increasingly detailed mobile advertising data hit its pages, thanks in part to some free-to-download research over at Kenshoo and IHS.
For today's post I want to reflect on some of these trends and relate them to some of my own recent experiences of mobile ads – particularly the ever-surprising world of in-app advertising.
Why there should be more plaudits for digital audits
Now do you think we're sexy?
Let's be honest, digital website or media campaigns audits don't sound all that sexy.
How five charities are innovating with contactless payment technology
I'm one of those people that always forgets to carry cash.
Which usually makes walking past a charity collection bucket (and buying a single pack of gum) slightly awkward.
How can digital brands adapt content strategy for high growth markets?
How can brands such as Amazon Prime and Netflix ensure they approach high growth markets fully prepared, to maximise the viable revenue opportunities on offer?
As advanced economies are rapidly reaching saturation point and consumer acquisition is becoming increasingly challenging, digital content brands seeking expansion have no option, but to look for new revenue streams.
Snapchat Bitmoji: What does it mean for brands and marketers?
Earlier this year, Snapchat paid more than $100m to buy Bitstrips, the company behind the popular sticker app Bitmoji.
Last week, Snapchat announced Bitmoji features were properly integrated into the app.
10 sizzling digital marketing stats of the week
It's been a scorcher of a week in the Econsultancy London office, and so naturally, we've got some equally sizzling stats for you to get your teeth into!
This week's roundup includes news about online searching behaviour, mobile commerce and social media usage in Europe.
Don't forget the download the Internet Statistics Compendium for lots more.
Pokémon GO: Zappar founder tells us what it really means for augmented reality
Trendjackers as ever, we've already discussed Pokémon a plenty on the Econ blog.
What can brands learn from Nintendo's digital transformation? And what does it mean for augmented reality (AR)?
But now I've caught up with Zappar co-founder and CEO Caspar Thykier, to give him his right to reply on the future for AR in the light of the gaming sensation.
Four ways brands are marketing through dating services
Online dating services might not seem like ideal platforms for marketing.
After all, many are monetized primarily through paid subscriptions, and users, for obvious reasons, are probably more focused on finding a date than clicking on ads.
But in recent years, brands have found ways to insert themselves into the online dating experience. Here are four examples.
10 notable digital marketing stats of the week
This week's stat round-up includes news about Amazon, data regulation, ad spend and, of course, Pokemon Go.
Check out the Internet Statistics Compendium for lots more information and insight.
The week's news in digital (in five minutes)
Yes, yes, we'll be talking about Pokémon.
But also Amazon's new programmatic creative video ads, ASOS' one-hour delivery, Nissan's autonomous cars and much more.
Here's your five minute update on the week's digital news.
Who will win the live-streaming battle: Facebook Live or Periscope?
In the age of ephemeral content and channel proliferation, it's no wonder some marketers feel like they are forever playing a game of catch-up.
Shiny new technologies regularly appear, hit critical mass, and inevitably get surpassed by better tools.
Take the recent rise of live-streaming for example – it is a popular medium transformed into an entirely new format.
Mobile marketing strategy: Four key charts from our latest research
While mobile has become an increasing focus for digital organisations in the past few years, when it comes to executing a streamlined strategy, it appears many are still lagging behind.
As the latest Econsultancy/Adobe Digital Intelligence Briefing highlights, 48% of organisations don't have a proper plan in place.
And out of the rest that do, many admit to a lack of cohesion.


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"Garvin Gardens" Top 5 Page for this destination Hot Springs Off The Beaten Path Tip by grandmaR
Hot Springs Off The Beaten Path: 6 reviews and 17 photos
We drove a short distance from the hotel over to the Garvin Woodland Garden. We had another coupon, and we got in for the senior rate $5 minus $1 each took the golf cart tour which was $6 each. This was very enjoyable. There were snowdrops and crocuses out, and some daffodils, some camellias, and an occasional azalea. There were a lot of water features, waterfalls and bridges.
Afterwards they asked me to fill out a questionnaire about how we had liked it, and one of the questions was what other Botanical Gardens we had visited. I started to try to list them and remembered 12 of them, but I forgot the Santo Domingo Botanical Garden, the Birmingham Botanical Garden and the Brookgreen Gardens in SC. That would have made 15.
This year (in addition to Santo Domingo and Birmingham) we've been to
*Dallas Arboretum and Botanical Garden
*Bellingrath Gardens
*Harry Leu Garden
Previous years
*Fairchild Gardens
*Edison Estate in Ft. Myers
*Key West Botanical Garden
*Sugar Mill Gardens in Port Orange
*Elizabethan Garden on Roanoke Island
*Bouchart Gardens in Canada
Long ago
*Golden Gate Park
*Longwood Gardens
More Reviews (12)
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""..an adventure is an inconvenience rightly considered." G.K. Chesterton"
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Community Candlelight Xperience
- When Sunday, December 16, 2012 at 5 p.m.
- Where First United Methodist Church, 2111 Camino del Rio South, San Diego Map | Website
- Age limit All ages
- Categories Family, Holidays, Vocal Music
- Cost Free
Above: Promotional graphic for the Community Candlelight Xperience on December 16th, 2012.
Want to get away from the malls and get in the mood for the holidays? This casual, yet festive community event lets you celebrate a week ahead with your friends, family and neighbors.
At The Community Candlelight Xperience, we'll listen to a great live band and a short, accessible Christmas message and sing some Christmas Carols. Cookies and punch will add to the good cheer. Come to in Linder Hall (next to the big church). All are welcome.
Date: December 16th starting at 5pm
For more information, visit http://www.fumcsd.org
Location: First United Methodist Church, 2111 Camino Del Rio South San Diego Google Map


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Item No. » AA-FRB
Sorry, this item is Out of Stock and cannot be purchased at this time.
Mountain Biking is made even better with a comfortable pair of Baggy Shorts, and Fox, as usual, answers the call. The Ranger Cargo Baggy 12 Shorts have a longer inseam (12") for better coverage, a removable spandex liner with a Pro Form M Chamois, and plenty of pockets to stow all your trail necessities.


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Sep 19
Event is in planning
Oct 11
Birthday bash for Michael Boudreaux
Jan 26
It's just about time for another outdoor live show at tbecks! Event date subject to change until I obtain permission.....Luv u Sis
Sounds Like: Dan Fogelberg, Poco, Jars Of Clay, Jeremy Camp, Pink Floyd
Label: Sharpie
Manager: S. Joseph Boudreaux
Mr. Stacey, or "Bdx" as he is called (an abbreviated version of his last name, "Boudreaux") began playing around 1976 when he thought the 4 strings he had on his nifty Silvertone from the Western Auto was the thing.
Most of the groups he made an effort with usually focused on the music he would ...See Full Bio
Acoustic Guitar, Vocals, drums, effects, downmix, electric guitar, lead guitar
Perry "Cue" Curol
"Friendship soothes over the ripping notes and brilliant design of these compositions. The sounds collide together, revealing the complexity of these shared paths."


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Prostate Cancer Health Center
Treat Prostate Cancer in Older Men?
Dec. 12, 2006 -- To treat or not to treat? That is the question for older men with early-stage prostate cancer.
The jury is still out, but new research suggests a survival advantage for older prostate cancer patients with localized disease who chose active treatment over close observation without treatment, known as watchful waiting.
The look-back study included data from nearly 45,000 patients between the ages of 65 and 80 with low- to intermediate-risk prostate cancer.
Over 12 years of follow-up, patients treated with either surgery or radiation were found to have a 31% lower risk of death than patients who did not opt for treatment.
The National Institutes of Health-funded trial is published in the Dec. 13 issue of The Journal of the American Medical Association.
"Our findings suggest that there may be a [survival] benefit associated with treating older patients with early-stage disease," researcher Yu-Ning Wong, MD, of Philadelphia's Fox Chase Cancer Center, tells WebMD.
"While treatment is clearly not the right decision for every patient, the potential for a survival advantage should enter into the decision making."
Ongoing Trials
The latest findings appear to contradict a large Scandinavian trial, published last year, which directly compared prostate cancer surgery to watchful waiting. In that trial, the treatment-related survival advantage was largely confined to men under the age of 65.
Two other large trials directly comparing treatment to nontreatment are under way, one in the U.S. and the other in the U.K. Results from these trials are expected before the end of the decade.
UCLA urology and public health professor Mark S. Litwin, MD, MPH, says these trials should help clarify the issue of who needs treatment and who doesn't.
He tells WebMD that the study by Wong and colleagues, while very well done, falls short of proving that older prostate cancer patients derive a survival advantage with treatment.
This study should not be seen as a foot on the accelerator for the treatment of these patients, he says. "It is provocative and encouraging. But at the end of the day it is still an observational study, and the ultimate answer has to come from randomized, control trials."


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Are Arians and Scorpios
Suitable For Each Other?
Aries and Scorpio. Fire and Water. You are both under the sign of Mars, the god of war, but you have different ways of expressing yourselves.
Fortunately for the Aries in love with a Scorpio, the latter has at least some common qualities with the first one: Sscorpio is loud, passionate and ardent. This is really a relationship full of action!
It is not a typical combination on the list of the happy couples, because you both want to be winners. So it will only last if both of you are willing to make some efforts.
Sexually, both Aries and Scorpio have an insatiable appetite, enough energy and passion to lit the Sun, although Scorpio's feelings are stronger and deeper than Aries'. Sometimes you may not reach the depth where Scorpio lives his/her inner life, and this might hurt him/her.
Scorpio needs to be understood. It is worth trying, all you need is a little patience (you will need to exercise this muscle, it is a little atrophied at Aries) and goodwill, which you already have. In return, you will have a partner with whom you will be able to be yourself.
Scorpio is very sensual, so you could learn something from this sun sign that is a master of making love. But remember that Scorpio demands total attention, faithfulness and devotion. You will receive the same thing, because (s)he has these qualities in his/her turn. That means you have to close that eye that chases other men or women!
You never know for sure if you want to belong to someone or not and you will often get bored in a relationship like this one: no flirt, no frivolity, no adventure at all - precisely the salt in the food, isn't it? Scorpio decides much sooner whether (s)he wants you two to be together or not, and, attention, once you've had a physical contact, (s)he considers this like an unwritten contract that gives him/her full right over you.
Still, there is so much energy and action in an Aries-Scorpio relationship that it is worth the effort!
Aries Woman - Scorpio Man
Love Match
The Scorpio man and the Aries woman make a very unstable combination. From the erotic point of view, the Aries woman will prove to be ingenious, and the Scorpio man will take part enthusiastically. However, the Aries woman is too thoughtless for the jealous Scorpio.
The Scorpio man and the Aries woman have a lot in common: they are equally egocentric, dynamic and ambitious. Even if chemistry seems to work like a strong liaise between the Scorpio man and the Aries woman, the individualism of both of them manages to set them apart.
Between the Scorpio man and the Aries woman there can be a short-term relationship, but a long-term relationship will prove to be very unstable.
Astrologer: Galadriel
Next Up:
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Related Articles for Aries:
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Astrology Compatibility Around the Zodiac


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Maurice Sendak's Really Rosie
Maurice Sendak's Really Rosie
HarperTrophy, Paperback, 9780064431385, 64pp.
Publication Date: December 17, 1986
This sturdily bound paperback contains the script of the TV special Really Rosie, the text of [the four Nutshell Library volumes], and music arranged for easy piano and guitar chords for the seven Carole King songs from [the program].A delight for TV fans of all ages.' 'Language Arts.
He received the 1964 Caldecott Medal for Where the Wild Things Are; the 1970 Hans Christian Andersen Award for Illustration; the 1983 Laura Ingalls Wilder Award, given by the American Library Association in recognition of his entire body of work; and a 1996 National Medal of Arts in recognition of his contribution to the arts in America. In 2003, he received the first Astrid Lindgren Memorial Award, an international prize for children's literature established by the Swedish government.