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What's a better way to start off the new year than with a bang, right? Preferably a bang that involves lots of sparkles. Our dazzling earrings consist of clusters of sparkly diamonds encrusted onto a circular plate and are perfect to go with that chic LBD for the first party or with your first great outfit of 2012. They come in a clear or a turquoise color and will add that much-needed "POP" to any ensemble. Start off your new year on the right foot (hopefully a foot wearing a cute shoe!!) with these sparkly stunners.
- Archives
Happy Sparkly New Year Dolls!!
Posted in: BabyDoll events
Hello Dolls!!
With the launch of the 2nd Edition CRAVE Chicago this month, we'd like for you to take a moment to think about what you really CRAVE… If you are someone who is constantly looking for things that inspire, you will be delighted to pick up this book!!
We are so thankful to be one of the few business selected to share their story through CRAVE Chicago. This fabulous edition innovatively connects urban gals to the sassiest, gutsiest, most inspiring people they need to know in Chicago. We'd LOVE for you to have the chance to stay connected to everything there is to CRAVE about the Windy City through CRAVE Chicago.
Happy Holidays from BabyDolls!
Posted in: Uncategorized
Happy Holidays Dolls!
As the joy of the holiday season fills the air, the BabyDolls Boutique Team would personally like to wish you a very warm, sparkly and safe holiday! This season we hope you have the pleasure of spending time with close friends and family while truly enjoying each others company.
We are constantly reminding ourselves to be thankful for all the wonderful blessings in our life. Therefore, we would like to give you a BIG "Thank You" from the bottom of our hearts for all your support this wonderful and amazing year! We are thrilled to know that our gifts have been a part of so many special occasions in your lives. It is with great satisfaction and pleasure that you help us do what we LOVE most- helping you find the perfect gifts.
Thank you for your support, shopping local and spreading the holiday cheer this season!
Xoxo, BabyDolls Team
We have always thought there was something magical about our jewelry. Who knew that some of it actually is thought to have metaphysical properties?! Our precious stone earrings embedded in hammered Gold come in oval or teardrop shapes in a beautiful array of colors thought to have various healing properties including ruby, tiger's eye, sapphire, emerald, and black. For example, emerald is thought to promote clear thinking and to enhance memory, sapphire is thought to open the mind to beauty and love and to rid the mind of bad thoughts. So if you ever need the perfect excuse to shop for jewelry, just say your insides need healing!
Your Little Angel!
Posted in: Baby Trends, Beautiful Inspiration
We're sure you have a multitude of oohhh and ahhh cutey names for your baby– peanut, cupcake, darling, sweetheart, love, my little angel… if the last one is one of them, we have the perfect onesie for you! The onesie comes in a pink, blue or white (as shown above) color and has a gorgeous pair of white wings sewn onto the back. This sure brings a whole new meaning to the phrase she or he is "a gift from the heavens", doesn't it? It's also a sure show stealer in your baby's photo shoot. SERIOUSLY what could be cuter than your sleeping little angel?
Frosty and Rudolph!
Posted in: Baby Trends
What is the perfect edition to that festive holiday outfit, you ask?? These fabulous clips. We're having a hard time deciding our favorite: the snowman with the green scarf, the turkey with "googly" eyes, Rudolph the red nosed reindeer or the Christmas tree speckled with colorful ornaments! Tough pick, however we are sure you will find the perfect match with our incredible selection…or you can simply get one of each!
Happy Holidays Dolls!!!
Natural Beauty!
Posted in: Beautiful Inspiration, Fashionista Trends
Dolls, we have survived a long journey. We've dived into strange and mystical waters to pluck aquamarine beads out of mermaids' hair, trekked through volcanoes to find ancient molten rocks the perfect shade of mahogany, and flown to the sky to grab fistfuls of beautiful cyan sky. Well, something like that. Either way, the beautiful blues and oranges of our beaded bracelets with flat square stones in the middle look so beautiful they're out of this world. The beads are made of agate, which was a stone thought to attract strength and protect people from bad dreams in Babylonian times. People have been using agate for jewelry since Biblical times, so SOMETHING must be right about it! Its smooth texture and breathtaking colors are seven trillion percent sure to "wow" you.


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My theme supports 3 menus. I can place my menus in my header, on my portfolio page or my gallery page.
What I want to do is create a menu called online store and place it at a certain location on my online store template page.
How can i do this?
Is there a plugin that does this?
Can I create a menu and simply "call"(whatever the php term is) the name of that menu and place it on my online store template page?

subset: commoncrawl


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Those misunderstood, callow trotters, the Bad Piggies, are in for further egg-swiping adventures in their "Angry Birds" spin-off, courtesy of a free Rise & Swine expansion.
Included in the Rise & Swine update, along with 15 new levels, are two extra items for the Piggies' makeshift vehicles, and an Everyplay widget to record and upload the sweetest slices of egg-moving action.
On the game's iOS version, with an Android equivalent to follow, users can record their favorite moments, before sharing them with friends on Facebook, Twitter and YouTube.
Official website: badpiggies.comcp/kc


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Democratic National Convention
Highlights from the 2012 Democratic National Convention.
Highlights from the 2012 Democratic National Convention.
Will: The Content of the DNC emails should be what upsets EVERY American, not who did it ! Did we care if it was Toto or Dorothy who pulled back the curtain to reveal the fraud of the great and powerful OZ ? No , just that it was a fraud ! Scott Pelley "looking into Hillary's eyes, I could tell she was being honest, The NBC politicos being warned to back off by the DNC and they honoring the requests, Wolf Blitzer drinking champagne and dancing with Demo Delegates and the American Sheeple think Fox news is biased, REALLY ? Hillary is corrupt and solely in the pocket of WALL STREET and The WASHINGTON ELITE! If you think she is for you, the average American then you are are way more Naive than I thought possible !


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Monday 19th
Discussion and debate with Joe Duffy
Discussion and debate with Joe Duffy
Michelle Burke bought a house in Killaloe , County Clare in 2006 . Seven years later she has still not been able to move in . The development has been caught in a series of delays, recievership and resale. Callers offered advice as to how Michelle can resolve her difficulty.
Madge Clabby is Imelda May's mother . She and her husband Tony talked to Joe about their day out at the Aras for the recording of An Glaoch , the programme hosted by President Higgins and Sabina featuring poets , writers , musicians and singers, including Imelda , who sang her song 'Kentish Town waltz'.
Michelle describes the trauma of owning a house on a ghost estate, still paying the mortgage but having no access to it
The pride is obvious in Imelda May's parents who describe their trip to Áras an Uachtaráin to watch the recording of the 'Glaoch' television programme
Miriam has lost a valuable business asset for the sake of a few thousand euro
Title: Kentish Town Waltz
Performer(s): May, Imelda
Duration: 5:05
Call: 1850-715815 / 08457-853333 from Northern Ireland & U.K
Text: 51551


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Panzer Dragoon (Demo Disc)
| |
Panzer Dragoon Cheats & Codes
| Cheats | Unlockables | Hints | Easter Eggs | Achievements
Be the first to submit a cheat for Panzer Dragoon.
You must be Logged in to submit a cheat.
Game Details
Published by: SEGA
Developed by: Team Andromeda
Genre: Sampler
Release Date:
United States: Released
Also Available On:
Games You May Like
- Sampler
- Saturn
Race the world's most exciting supercars, each modeled after its real-life counterpart on six challenging, scenic tracks.


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Free U.S. Shipping and Returns
A trouser short with side dart detailing.
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Don't Miss out on latest news and promotionsPlus, receive 15% OFF your next order upon sign-up!
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text:
It seemed there was nothing I could do to make my Editor's Letter flow this month. Stewing in frustration, I hit "select all, delete"… Read More
There's something about Alicia Keys that makes you feel at ease. Maybe it's the warm, megawatt smile or infectious laugh. Or perhaps it's… Read More
From the 1970s through the '90s, some of the most legendary models, race notwithstanding, were introduced to the world, and the industry was… Read More
We are not "old Black" nor "new Black" we are ALL Black.
Sneakers, tennis shoes, trainers… no matter what you call them, the one thing that always rings true is that a fresh and fly… Read More
By Marielle Bobo Designer goods for the entire family without the hefty price tag? Sounds like a tall order to… Read More
By Nana Ekua Brew-Hammond Almost every spring season, designers send a parade of mostly white models down the… Read More
By Najja Parker Read More
By MARIELLE BOBO Photo 1: Easy Riders The classic one-piece gets… Read More
We are not "old Black" nor "new Black" we are ALL Black.
Vernon Reid Talks 30 Yrs of the Black Rock Coalition
Justin Adu Explains African Amedia
Beautifully Brown Grace Jones
Why Did Ben Carson Mock Police Brutality
Detroit's New Activist Generation


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Al-Sadr Faces Pressure to Call Off Truce
Shiite cleric Muqtada al-Sadr is expected to announce his decision in the next few days about whether to maintain the ceasefire he ordered six months ago. There has been pressure from rank-and-file members of his militia to end it.
Related NPR Stories
Iraqi Radical Cleric Al-Sadr Studies for Ayatollah Jan. 2, 2008
Iraq's Sadr City Not Helped by U.S. Troop Surge Dec. 17, 2007
Resentment Grows over Shiite Cleric's Militias Oct. 6, 2007
Al-Sadr Loyalists Defect from Iraq Shiite Alliance Sept. 16, 2007
It's Badr Versus Mahdi in Karbala Aug. 29, 2007
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American Civil Liberties Union (ACLU) CU Law Chapter brings together students interested in defending civil liberties on campus. As law students, we have a special obligation to be out front and visible on these issues. ACLU CU Law Chapter participates in outreach to undergraduate students, rapid response to situations that develop on campus, and partnering with the ACLU Boulder Chapter. Throughout the year, we also invite guest speakers to discuss and foster debate around prominent issues regarding individual freedom.
Other resources:


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Alachua County School Bus Drivers Get Small Pay
Published June 26th, 2008
Story By: Brittany Soeder WCJB TV20 News.
The people in charge of the Transportation Department switched up pay dates for their drivers so they would get an equal dollar figure in both summer paychecks but that's not going to happen.
According to the School Board, the change of date for bus driver's paychecks was done in good faith. The only problem is the Transportation Department is no different than any other school department, and they cannot change their own pay system. The School Board will pay the drivers like any other employee working summer school, which means a three day paycheck to last until the next pay date on July 13th.
Related Stories
- School Bus Beatdown, Levy County Driver Fired
- Alachua County school bus aide out on bail
- Alachua County school bus schedule concerns
- School bus safety in Alachua County
- Private School Bus Company Meets with Bus Drivers
- Bus driver cleared after running over 7-year-old
- School Officials: Bus Driver Broke the Rules
- Driver hurt, kids OK in Lake City school bus crash
- Driver killed after rear-ending school bus
- School Bus Driver Grabs Student by the Neck


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I want to be able to automate the initial language selection and WDS auth credentials. I am guessing I can't set that in an answer file to be provided by WDS? How can I achieve this?
In WDS there are two unattend files. One for the install image and one for the boot image. You set the settings that you're asking about in the WinPE section of the answer file for the boot image.


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Three weeks ago, Daniel J. Hilferty, 57, president and chief executive of Independence Blue Cross, joined other insurance executives in Washington to meet with U.S. Secretary of Health and Human Services Kathleen Sebelius.
The topic? The massive computer software nightmare that has complicated enrollment in the new health insurance exchanges and set off a war of partisan sniping in Washington.
Question: What's your reaction to the glitches and what did you tell the White House?
Answer: It's disappointing. The CEOs articulated our concerns - both that we believe reform is right and this is hurting our chances for bringing in as many new people into the plan.


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Welcome to the British Finn Association…
This is the home of UK Finn sailing where you will find our race calendar, information on international regattas, training, tuning & technique advice, an active forum & marketplace plus all the info you need to start Finn sailing. See the latest membership benefits from our supporting Partners.
Britain has a rich heritage of success in the Finn at Olympic and World Championship level, but the majority of the UK fleet is made up of Junior, Club and Masters sailors who enjoy racing Finns at all levels.
Enter now for the GAC Pindar UK Nationals
Congratulations to Giles Scott on a historic fourth Gold Cup win in Gaeta, and to Ed Wright finishing 9th, with Ben Cornish 19th.
The great attraction of the Finn is that you don't need a brand new boat to be competitive – top regattas are regularly won by 10-yr-old boats.
A growing route in for sailors on a budget is the 'Classic with Carbon' option – any pre-1985 hull super-charged with a second-hand modern rig. Classic boats are warmly welcomed at all BFA events and are often seen in the top 10 with the Modern Race Boats.
Latest Race Reports…
The Finn fleets have a very active racing programme at all levels from Olympic events though to the equally keenly fought Classic fleet through the CVRDA.
To read the latest regatta reports click the images below.
Next Event


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Institutions have bought around 18 million shares over the last nine months. The purchase of the last 12 million shares repositioned the price at less than $10.
The buyers of the 6.9 million shares in the recent offering can book a swift 20% profit if they sell for around $12. But they may have considerable trouble finding enough buyers for that sort of volume.
Those recent buyers will surely not be expecting any serious demand for shares any time soon, and will doubtless be looking to jump the gun on one another rather than risk their investments being dead money for the rest of the year.
Who can we (or they) now expect to accumulate the volume of shares necessary to outweigh the profit-taking from the recent offering - in order for the share price to move higher?
Any ideas?
We surely can't expect an influential analyst to risk recommending INSM after Hayden and Lewis made UBS and the other four look stupid.
What's the next anticipated development likely to draw new investors to INSM in sufficient numbers to outweigh the profit-taking from this latest offering?
I would expect a run up in anticipation of EMA approval for CF as well as accumulation in anticipation of positive NTM phase 2 results.
FDA feedback on those NTM results, and FDA guidance on the possibility of CF approval based on the current EU CF and US NTM studies could also provide a pop. Other wild cards would be unexpected licensing or partnership opportunities.
Ultimately, revenue will move the share price. I'm patient.
Sentiment: Strong Buy
Now that you and your alter ego "Michael Cohen" ID have combined, you've turned into a brand new incarnation of Hi-lee evolved. Did it ever occur to you that the massive demand for Arikace could be completely waisted by a lack of preparation to supply? That preparation must happen now, not later. Billions in future revenue is at stake. Will Lewis know what he's doing and a multi-billion dollar valuation will be the pay-off. And you're not going to have to wait several years!
Fud. The only one looking stupid.....is....YOU. The laughing stock of this mb.
Sentiment: Buy


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Out of Print
This intimate family album is a revealing photographic look at the Beat Generation as chronicled by the movement s great poet Allen Ginsberg. Allen Ginsberg began photographing in the late 1940s when he purchased a small, second-hand Kodak camera. For the next fifteen years he took photographs of himself, his friends, and lovers, including the writers and poets Jack Kerouac, William Burroughs, and Gregory Corso as well as Beat personality Neal Cassady. He abandoned photography in 1963 and took it up again in the 1980s, when he was encouraged by photographers Berenice Abbott and Robert Frank to reprint his earlier work and make new portraits; these included more images of longtime friends as well other acquaintances such as painters Larry Rivers and Francesco Clemente and musician Bob Dylan. Ginsberg's photographs form a compelling portrait of the Beat and counterculture generation from the 1950s to the 1990s. Far more than historical documents, his photographs and the extensive inscriptions he added to them years later preserve what he referred to as 'the sacredness of the moment, ' the often joyous communion of friends and the poignancy of looking back to intensely felt times. More than seventy prints are brilliantly reproduced in this book and accompanied by Sarah Greenough's essay on Ginsberg's photography in relation to his poetry and other photographers of the time, a chronology of his photographic activity, and selections from interviews with Ginsberg between 1958 and 1996
About the Author
Sarah Greenough is the chief curator and head of the department of photographs at the National Gallery of Art, Washington, DC.
Allen Ginsberg was a member of the American Academy of Arts and Letters as well as a winner of the National Book Award for Poetry. He was born in Newark, New Jersey, in 1926, and died in New York City in 1997.


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Profile Photos
Album for profile photos
Mar 26, 2014
Photos: 1
Shelf Road 12-2011
Pictures from a winter trip to Shelf Road.
Dec 26, 2011
Photos: 55
The Rostrum, 5.11, Yosemite CA
I've wanted to climb The Rostrum (5.11, 8 pitches) for a while now. It has a reputation of being one of the finest free climbs in Yosemite Valley and it did not disappoint. The climbing is really sustained and high quality from start to finish. It was definitely a good challenge for Nat and me: harder than Positive Vibrations, which we had climbed a few days before, but also substantially less committing.
Sep 14, 2011
Photos: 23
Positive Vibrations (5.11a), Incredible Hulk, CA
Though school hasn't started yet for us quarter system folk, Nat and I decided to head out to California a bit early to climb in the Sierra Mountains and Yosemite region. Our first objective was Positive Vibrations (5.11a) on the Incredible Hulk, an amazing formation in the High Sierra. With 8 consecutive pitches of 5.10 or harder climbing, Positive Vibrations is quite sustained and features some incredible crack climbing on perfect granite. The climb itself went really well for us, but we got caught in a downpour and a freaky lightning storm as we tried to descend. Although we got thoroughly soaked and spent a cold, unexpected second night at camp, I felt like the awesome climb was worth every second of the subsequent misery, and then some.
Sep 11, 2011
Photos: 33
Sandias Climbing 2011: Mountain Momma (5.10c) and Little Yellow Jacket (5.11a)
When the Sandia Mountains (along with most of the rest of the state) were closed for fire danger in June, I figured I wouldn't get a chance to climb there at all this summer. But the monsoons finally came, and I was able to get out there and climb two stellar routes: Mountain Momma (5.10c) on 8/6 with my sister, and Little Yellow Jacket (5.11a) on 8/28 with Nat.
Aug 6, 2011
Photos: 26
Fire Evacuation Climbing (Colorado, 2011)
After the evacuation of Los Alamos, my sister and I drove up to meet our parents in Pagosa Springs, where we were able to sample one of the local crags, Piedra River. I then headed up to Boulder to stay with George and his family and climb in the low-lying crags in the area. Still a lot of snow in the high country up there.
Jun 29, 2011
Photos: 62
El Rito Rad Wall
Allison, Nat and I enjoying a day at El Rito (mid June, 2011). Most photos are by Fritzer, except the second set of Nat, which I took.
Jun 18, 2011
Photos: 22
Sugarloaf (CA) climbing, 4/9 - 4/10, 2011
Despite a marginal forecast, Nat and I headed to Sugarloaf, a granite dome in the Tahoe Vicinity, for a day and a half of climbing. The weather cooperated (for the most part) and we had a great time.
Apr 9, 2011
Photos: 29
Serenity - Sons (5.10d), Yosemite Valley, CA
The weather has been really warm in California, and Anna and I were able to take advantage of it by making one last day trip to Yosemite before midterms begin to dominate our time. We climbed "Serenity-Sons", the contiguous link-up of the three-pitch Serenity Crack (5.10d) with the five-pitch Sons of Yesterday (5.10a/b), which begins off of the big ledge atop Serenity Crack. It was great, albeit tiring, day. I didn't take too many photos because I was trying to concentrate on climbing (and belaying!).
Jan 29, 2011
Photos: 12
Yosemite Cragging (January 2011)
Anna and I took advantage of the relatively nice weather in CA these past few weeks by making a couple of day trips to Yosemite. We mostly did single-pitch climbs because most of the longer climbs looked really snowy and wet. That's ok though, because Yosemite has some of the best trad cragging in the country.
Jan 17, 2011
Ecuador Part 3: Cotopaxi (19,347 feet).
The day after climbing Illiniza Norte, we hiked past the refuge on Cotopaxi to work on our glacier-climbing skills. I was really looking forward to this because I only have theoretical knowledge of crevasse-rescue systems, but we didn't get a chance to work on that (bad weather). It wasn't really a wasted day though, as we got a chance to take some nice pictures of the mountain.
We then headed back down to lower altitudes to get a good night's sleep in preparation for a summit attempt Wednesday night / Thursday morning.
Dec 23, 2010
Photos: 47
Ecuador Part 2: Illiniza Norte (16,817 ft)
The day after our climb of Pichincha, we hiked up to the refuge under Illiniza Norte, spent the night there and went for the summit the next day. As on Pichincha, we had to deal with a lot more snow than was usual, but it turned out ok.
Dec 21, 2010
Ecuador Part 1: Quito and Rucu Pichincha
My family and I went to Ecuador to climb a few of the many volcanoes there. We climbed with mountain guides, partly for logistical reasons and partly because none of us were familiar with these mountains or the routes themselves. Our big goal was Cotopaxi, at 19,347 ft, but we climbed two shorter peaks (but still tall, by US standards) to help us acclimate to the high altitude.
We spent our first day in Ecuador exploring Quito, a city of about two million people. The next day, we did our first climb, Rucu Pichincha (15,413 ft).
Dec 17, 2010
Photos: 16
Central Pillar of Frenzy, 5.9. Middle Cathedral Rock, Yosemite Valley, California
Anna and I managed to get away from school for a day to climb in the Valley. Because of an early afternoon shower, we only got to do one one route, but we made it count. Central Pillar of Frenzy has five consecutive pitches of superb and eclectic crack climbing, with techniques ranging from fingers to hands to fists to offwidth and even a fun bit of chimneying. As can be expected on a five-star north-facing climb at this time of year, the crowds were out of control. We were the first party on the route, so it worked out ok.
Oct 2, 2010
Photos: 15
The Snaz (Snazzette Variation), 5.10, Death Canyon, Grand Teton National Park
The Snaz is the classic Teton 5.10a. With pitch after pitch of fun climbing, great rock and great views, my sister and I felt it deserved its classic status. Being short on time (this was our last day in the Tetons so we needed to pack in the evening), so we rappelled off after 6 pitches.
There are a lot of notable variations to The Snaz and we climbed one of them: The Snazzette, a 5.10 variation to pitch 6. This was an outstanding pitch of crack climbing, as good as any I have ever experienced.
Aug 20, 2010
Photos: 19
Grand Teton National Park, 8/15-8/17, 2010
Mom, Anna and I headed up to Wyoming for some beautiful climbing and hiking in Grand Teton National Park.
Aug 18, 2010
Photos: 39


text:
Video Industry News Video Company News Technology Industry News Technology Company News Novelty Industry News Novelty Company News Gay Industry News Gay Company News Legal Industry News All Company News
Released: Sep 01st, 2004
Running Time: 85
Director: David Stanley
Company: Vivid Entertainment Group
Cast: Eric Masterson, Lola (I), Rick Patrick, Jean Val Jean (I), Holly Hollywood, Evan Stone, Malezia, Peter Shaft
Critical Rating: AAA 1/2
Genre: Feature
Pitch to fans of Malezia.
David Stanley pokes fun at artsy porn directors (including, possibly, himself) in a movie that's mostly intended as a showcase for the newest Vivid Girl, Malezia.
The exotic brunette shows lots of promise in three sex scenes. She plays the star of the movie within the movie that frustrated, burnt-out Eric Masterson is directing.
Eric and Holly Hollywood have most of the dialogue, and they handle it well. There are wryly funny moments and some industry in-jokes. The sex is okay - best with Malezia, who gives head like she loves it.


text:
Anaergia is a company of passionate people working in one of the most exciting industries in the world - renewable energy. The Anaergia team believes that makinMore
$25 mil. - $50 mil.in Revenue
250 - 500EmployeesContact people at this company
renewable energyintegrated turnkey solutionsMore
Energy, Utilities & Waste TreatmentElectricity, Oil & GasMore
4210 South ServiceBurlingtonOntarioL7L 4X5Canadaview map
(905) 766-3333
Enterprise_Iteration-NT.1545[01] SEIDXWK-31


text:
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Ancient Egypt: Prelude to the New Kingdom Warfare (blackwellpublishing.com)
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Gould & Lewontin - The Spandrels of San MarcoArticle (blackwellpublishing.com)
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Review of the week 2: Bad sampling practice (blackwellpublishing.com)
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This has been posted before, but I feel it deserves its own thread. (blackwellpublishing.com)
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TIL that in 1642, a man by the name of George Spencer was suspected of bestiality because his pig gave birth to a piglet that looked like him. Upon questioning, he admitted to the crime, and he, and his baby pig, were later hanged. (blackwellpublishing.com)
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text:
Paul by Paul Smith - women's sleeveless red shift dress. The fitted dress features a round neckline, two shallow front vents, a concealed rear zip fastening and rear cut-out opening. The dress is fully lined and sits above the knee. Model is 5'9" and a UK size 10. Model wears a Coggles S (UK size 10).
A Paul Smith size S is equivalent to a Coggles XS. A Coggles XS is equivalent to a UK size 8.
Paul by Paul Smith at Coggles.com
60% Cotton, 40% linen, lining 51% viscose, 49% acetate
|Clothing Style:
Please remember to add postal time (2-3 working days) to obtain a complete estimate of delivery to your door.
You will receive an email to confirm when your item has been sent.
You can also check the status of your order and individual items by accessing My Account details and following the prompts.
Please allow 10 working days from dispatch of your order before notifying us of any late deliveries.
It may be advisable to check with your neighbours to see if a parcel has been left with them, check any outhouses you might have where it may be left if it cannot fit through your letterbox and contact your local sorting office to see if the item has been returned to the depot as undelivered and awaiting collection.
Please see our returns policy.
There are currently no reviews.


text:
The next great revolution in motoring may be driverless cars. But before that, we can expect to see great evolution in economy.
That might not sound particularly sexy. But with the number of cars on the road expected to rise to two billion by 2050 – and with liquid fuels still accounting for most sales, despite growth in the electric sector – Earth's car fleet must become more economical.
Every year, so-called "Eco-marathons" are held around the world, in which hundreds of university teams compete against each other in self-built cars. The aim is to travel as far as they can on a litre of fuel or a kilowatt hour of energy. Some run on petrol, others diesel. Many feature solar panels, hydrogen fuel cells or are powered by biofuels.
Design varies hugely (as do budgets) – but the top teams achieve economy figures of around 2,500mpg.
Staggering as that figure is, these aren't real-world numbers. Rather, they're averages taken from short, 10-lap stints, with drivers carefully managing speed and braking. Traffic is minimal, pedestrians aren't a problem and even factors such as wind speed are taken into account.
This takes nothing away from the students' achievements – their machines are incredible. It's just that these eco-cars are unsuitable for the real world. They're difficult to drive, incredibly fragile and generally piloted by petite women to keep weight down.
But – this aside – could they be on to something?
By making the kinds of drastic design tweaks seen on these eco-cars to our standard road cars, we could see significant economical improvements.
Slender wheels reduce friction and are fine for city runarounds that don't need to corner quickly. Lightweight materials, such as carbon fibre, are becoming cheaper. Computer models coupled with modern manufacturing techniques allow car makers to create ultra-aerodynamic bodies.
More advanced technologies such as kinetic energy recovery systems (Kers), used in F1, can recover energy lost during braking and feed it back into the motor as an electric boost.
Of course, such hyper-economy, would have a significant impact on the car's comfort. Extreme aerodynamics mean they could be very narrow, with passengers required to sit almost in tandem. Think skinny, bicycle-like wheels (to lessen friction) and a lack of significant sound dampening (to keep weight down).
Luxury saloon this is not. But such ideas may be indicative of an emerging class of car: one built with fuel economy at its core and creature comforts taking a back seat. If such vehicles are given significant tax breaks, are cheap to buy and decent enough to drive, they may see widespread success.
After all, if the eco-marathon students are anything to go by, the next generation of drivers is already thinking about a car's green footprint.
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This plugin gives a ton of flexibility to publishers for if they want to list just one post, all posts from a category, or just a few - with plenty of options like showing thumbnails, excerpts, dates, and more. The documentation on the plugin explains all of the capabilities in better detail here
My favorite part of this is the multiple taxonomy. This means you can display a custom list of posts - for instance, you can have ONLY posts that are BOTH categorized a certain thing AND tagged a certain thing be displayed. This is wonderful in it's robustness.
Another great plus is it plays nice with qTranslate - a plugin I personally use for all of our our site translations - with no need to patch it or anything!! Talk about great!!!
Wonderful work on this plugin.


text: I'd suggest the AR-10, as you are already familiar with it's nomenclature and ergonomics from the AR-15. The .308 for the AR will be a bit tricky to find, but it is definitley more available than the 5.7mm rounds are, and have much,much better ballistics. That, coupled with the fact that the AR will be around $1000, leaving money for ammo and accessories, and the PS-90 is around $1900 last I saw. But, it is your money to spend as you wish. Good luck with whatever you decide.


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About HEINEKEN USA HEINEKEN USA Inc., the nation's leading upscale beer importer, is a subsidiary of Heineken International NV, the world's most international brewer. European brands imported into the U.S. include Heineken®, the world's most international beer brand, Strongbow Hard Apple Ciders, Amstel Light, and Newcastle Brown Ale. HEINEKEN USA also imports the Dos Equis Franchise, Tecate Franc...
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(Topeka, KS)--Congresswoman Lynn Jenkins disagrees with the Obama administration on the proposed stimulus plan. She said she doesn't think it will work, and needs to focus on more tax cuts.
"We're talking about a trillion dollars here, nearly a trillion dollars and I don't even think it's going to stimulate the economy," Jenkins said.
She said she feels the package is filled with projects like education, universal health care and social services that would not immediately stimulate the economy. She also says it does not focus on infrastructure as much as some may think.
Jenkins, a CPA and former Kansas State Treasurer, says cutting taxes would be a better way to go. She suggests cutting the payroll tax in half to immediately help employers and employees.


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Droid authentication error. I get a really long string basically telling me it failed to authenticate me. Any ideas?
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I did the same with my other gmail and i still can't re-add it. Annoying.
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|Map Legend
|Yoga Teacher Training in Goa, INDIA
Mandrem Beach, Goa, India
|Oceanic Yoga
Goa Beach Estate Land, Morjim, Goa 403512, India
Oceanic Yoga's style of teaching is unique in many ways. From the Asana postures to Yoga Philosophy, our teachers support you and adapt to your individual needs. Safety precautions are essential principles at the school. While stressing the fundamentals, we also encourage our students to see and explore Yoga in creative ways so they are able to discover their own personal teaching style. Oceanic Yoga is teaching 3 diffrent types of 200 hrs Yoga teacher training courses, you can choose which one suits you.
200 hrs Hatha Yoga Teacher Training
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Fixed PriceBudget: $50
Start DateNovember 13, 2012
I have got pictures which are copyrighted and posted on website and i am not allowed to put them on a website. The job is to create those as new pictures, The new pictures should look very close to original picture. Please apply only if you are expert in creating picture by looking at existing picture.
About the Client
United States
Lilburn 02:05 PM
Jobs Posted
55% Hire Rate, 1 Open Job
Total Spent
90 Hires, 2 Active
Avg Hourly Rate Paid
268 Hours


text:
Graham Walker
Graham Walker
Department : Mechanical Engineering
Email : firstname.lastname@example.com
Phone : 718-862-7405
Office : RLC 207
- B.S. in Mechanical Engineering from University of Strathclyde (UK)
- Ph.D. in Aerospace Engineering from University of Southampton (UK)
Dr. Walker has worked at Manhattan College more than 20 years, and is currently conducting research in the area of biomechanics specifically on various orthodontic projects and one long term study that is examining Shaken Baby Syndrome. He has also been a consultant on various projects that have included system failure issues, testing protocols, and signal data analysis.
In the past, Dr. Walker did research on rocket nozzle design, which involved obtaining blast and sound wave data and processing the signals to extract salient pressure wave information. His work in signal processing introduced him to the field of system dynamics with an emphasis on instrumentation and robot sensors.
- Biomechanics of Orthodontics and Tooth Movement
- Shaken Baby Syndrome
Professional Experience
Consulting: Data Technologies Inc., Consolidated Edison.
Member of ASME and Sigma Xi Honor Society
Publications & Professional Activities
- WALKER, G. (2014), "Statistical Product Control," Fuel Fabrication Process Handbook, ANT International.
- Maestre, M.E., Nicolay, O.F., WALKER, G., Levi, M., and Cisneros, G.J. (2012), "Dental Varnish and their Impact on Enamel Demineralization and Bacterial Inhibition: an in vivo Model," Orthodontic Practice, Vol. 4, No. 2.
- Ryan, R., WALKER, G., Freeman, K., and Cisneros, G. J. (1997), "The Effects of Ion Implantation upon the Rate of Tooth Movement: An in vitro Model," American Journal of Orthodontics and Dentofacial Orthopedics, Vol.112, No. 1, pp. 64-68.
- Mosier, C.T., Yelle, J., and WALKER, G. (1997) "Survey of Similarity Metrics Applied to the Group Technology Cell Configuration Problem," Omega: International Journal of Management Science, Vol. 25, No. 1, pp. 65-79.
- Bassett, J. and WALKER, G. (1995), "A Split Image Vision Sensor," ASME Journal of Engineering for Industry, Vol. 117, No. 1, pp. 94-101.
- Tang, J. and WALKER, G. (1995), "The Variable Structure Control of A Pneumatic Actuator," ASME Journal of Dynamic Systems, Measurement, and Control, Vol. 117, No.1, pp. 88-92.
- WALKER, G. (1991), "The Variable Structure Control of Non-simple Input Systems," International Journal of System Science, Vol. 22, No. 12, pp. 2361-2376.
- WALKER, G., Salem, N., Varghese, M., Fuchs, A., and Mukundan, R. (1991), "Instabilities in the feedback linearization of a double inverted pendulum," IEEE International Conference on Systems Engineering, August.
- Sakal, R.L., Chow, J.G., and WALKER, G. (1991), "An Integrated System for the Machining of Sculptured Surfaces," Proceedings of the 7th International Conference on Computer-aided Production Engineering, August.
- Sakal, R.L., Chow, J.G., and WALKER, G. (1991), "A Semigenerative Computer-aided Fixture Design System using AutoCAD and a CAD Fixturing Database," Proceedings of the 7th International Conference on Computer-aided Production Engineering, August.
Honors & Awards
SAE Ralph R. Teetor Educational Award Winner 1992
U.S. Patent 6,247,234: Razor and Blade, Inventors James L. Hill and Graham Walker
Courses Taught/Teaching
- ENGS115: Introduction to Engineering
- ENGS201: Material Science
- ENGS206: Statics
- ENGS220: Dynamics
- ENGS230: Solid Mechanics
- MECH211: Graphical Communication
- MECH311: System Dynamics
- MECH312: Mechatronics
- MECH323: Machine Design
- MECH332: Finite Element Analysis
- MECH336: Manufacturing
- MECH401/402: Senior Design
- MECH405: Thermal/Fluids Laboratory
- MECH407: Advanced Strength of Materials
- MECH411: Vibration
- MECH446: Computer-Aided Manufacturing
- ENGS620: Applied Instrumentation
- ENGG652: Project Management
- ENGG654: Quality Engineering
- MECG605: Flight Mechanics
- MECG702: Gas Dynamics
- MECG723: Advanced Solid Mechanics


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|Publication number
|Publication type
|Application number
|Publication date
|Jul 11, 1995
|Filing date
|Aug 1, 1994
|Priority date
|Jul 28, 1989
|Fee status
|Also published as
|Publication number
|Ross H. Freeman, Hung-Cheng Hsieh
|Original Assignee
|Xilinx, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (20), Non-Patent Citations (3), Referenced by (91), Classifications (6), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This is a divisional of application Ser. No. 07/387,566, filed Jul. 23, 1989, now U.S. Pat. No. 5,343,406.
This invention relates to means and methods of performing custom logic functions in an integrated circuit logic device.
As integrated circuit devices have become able to perform more functions within a single integrated circuit chip, the manufacturers of integrated circuit chips have developed ways of automatically and quickly responding to orders for custom chips to perform specific functions for specific applications. On the one hand, gate array manufacturers apply custom metallization layers as a final step in a-standard manufacturing process in order to connect transistors located within a semiconductor substrate to perform a particular logic function ordered by a customer. On the other hand, for customers who make frequent design changes, who want only small numbers of identical devices, or who may not have fully tested a new design, user programmable integrated circuit chips are available. In a user programmable device, there are many pass transistors which can be turned on or off to connect or not connect corresponding lines to logic circuits, to other lines, or output pins. By turning on the proper combination of pass transistors and connecting the proper set of lines a user can obtain a desired logic function. The user can reprogram a different design into the chip by turning on different combinations of pass transistors.
Xilinx, Inc. the assignee of the present invention, manufactures configurable logic arrays having a higher level of integration than typical programmable logic arrays. A Xilinx configurable logic array includes an array of logic blocks, each of which can be configured to perform a desired logic function (each logic block combining multiple AND, OR, MUX gates or FLIP-FLOPs for example). The Xilinx configurable logic array also includes interconnect lines which can be programmed to connect individual logic blocks to achieve the overall complex logic function provided by the entire chip. In the current Xilinx products, two kinds of configurable blocks are used in a configurable logic array chip. Around the perimeter of the chip, and connected to each of the external pins are input/output logic blocks which can be programmed to connect input buffers or output buffers to the pin and to perform some logic functions. In the interior of the chip are logic blocks which do not offer the input/output buffer option but offer more logic functions within a single block.
FIG. 1 shows part of one of the configurable logic array chips for which automatic programming is available. Configurable input/output blocks IO1 through IO15 are shown. Configurable logic blocks CLB11-CLB14, CLB21-CLB24, CLB31-CLB34 and CLB41-CLB44 are shown. Each of the configurable blocks implements a plurality of logic gates such as AND, OR, XOR, INVERT, and MUX, as well as TRISTATE buffers and FLIPFLOP's which can be combined to implement a plurality of more complex logic functions.
The logic gates of a logic block are formed into flexible functions which are specified when the block is configured. For example the logic block may include a four-input AND gate. Zero, one two, three or four AND gate inputs need be used, the unused inputs being connected to the positive voltage supply. An input signal may pass directly or through an inverter to the AND gate. Since gates within a block are physically located and connected together in the substrate and adjoining layers of the semiconductor material, any desired one of a plurality of functions such as AND, OR, NAND, NOR, XOR of two inputs A and B can be performed by electronic components located in close physical proximity, therefore the signal delay caused by the logic block is minimal in spite of the flexibility and complexity of the logic block. One type of logic block is programmed to provide a desired function of several input signals by loading memory cells of a look-up table with the truth table of a desired logic function. This way great flexibility is achieved with minimum signal delay.
These configurable blocks each have input and output leads for receiving input signals and providing output signals. These leads are shown in FIG. 1 as short lines extending outward from each of the blocks and not connected to other portions of the array. These configurable blocks also have configuration leads not shown in FIG. 1 for programming the particular logic function or loading the truth table. The configuration leads determine what logic function will be applied by the block to signals entered on its input leads to generate a signal placed by the block on its output lead or leads. These logic blocks are discussed in U.S. Pat. No. 4,706,216 issued Nov. 10, 1987, which is incorporated herein by reference.
Available to connect these logic blocks to each other are interconnect lines with programmable interconnects, such as shown in FIG. 2. FIG. 2 shows in more detail a smaller portion of a configurable logic array chip with the interconnect lines for connecting one configurable logic block (CLB) or input/output block (IOB) to another CLB or IOB. Some of the interconnect lines are short segments which extend only a short part of the distance across the entire array, and others typically extend in one dimension the entire length or width of the array. FIG. 2b is a legend showing meanings for the marks in FIG. 2a. Diagonal lines indicate programmable pass transistors for connecting horizontal lines to vertical lines. Each transistor will have one current carrying terminal connected to a horizontal line and one to a vertical line. The control terminals of the transistors are not shown in FIG. 2a but are each connected to a memory cell into which a zero or one is entered. The zero or one in the memory cell causes the horizontal line to be connected or not connected to the vertical line. Transistors are also placed at ends of segmented lines to control the continuity of adjacent segments. Each of these transistors is also controlled by a memory cell. FIG. 2c shows in more detail this full-exchange interconnection indicated by an "X" in FIG. 2a. Line 90-4 is segmented from line 90-1 in that it is connected to line 90-1 by N-channel pass transistor T5 when memory cell M5 holds a logical 1 and disconnected from line 90-1 when memory cell M5 holds a logical 0. Likewise line 90-4 is connected to line 90-3 by transistor T1 when memory cell M1 holds a logical 1 and disconnected when memory cell M1 holds a logical 0. A set of memory cells thus controls the configuration of the interconnect lines interconnecting the logic blocks in the array. FIGS. 2a through 2d are discussed more fully in U.S. Pat. No. 4,870,302 incorporated herein by reference.
FIG. 3a shows one possible CLB which is part of a configurable logic array and can be configured to perform many different logic functions. FIG. 3a shows combinatorial function generator 354 having input lines 381-385 for receiving logic block inputs a-e and input lines 367 and 380 for receiving output signals from D-flipflops 352 and 357 respectively. Combinatorial function generator 354 also provides two combinatorial output, functions F and G on lines 374 and 378, each of .which may serve as input to either or both flipflops 352 and 357 as controlled by multiplexers 350, 351, 355 and 356. Output functions F and G may also be provided as logic block output signals X and Y respectively on lines 395 and 396 as controlled by multiplexers 353 and 358. Which functions are actually implemented by the logic block of FIG. 3a depends upon the settings of configuration control lines not shown in FIG. 3a. For an embodiment similar to that of FIG. 3a having four input lines A-D instead of the five input lines 381-385 of FIG. 3a, configuration control lines are shown in FIG. 3b as lines extending from RAM 108 or 109 to select multiplexer 110 or 111. Combinatorial function generator 354 of FIG. 3a generates two cominatorial functions F and G just as block 100 of FIG. 3b generates two combinatorial functions F1 and F2. FIG. 3b is discussed in U.S. Pat. No. 4,706,216, ibid. Combinatorial function generator 354 can generate any combinatorial function of five variables, or can generate two functions of four variables each. In current Xilinx logic blocks combinatorial function generator 354 is programmed by loading a truth table into a row of memory cells. As is well known, an n-input multiplexer can select one of 2n locations in response to an n-bit address. Function generator 354 is a multiplexer which reads one of 32 (25) memory cells in response to an address which comprises the five input signals on lines 381-385, or alternatively reads one of sixteen memory cells to provide a first function of four of the variables on a first output line, and reads one of a second sixteen memory cells to provide a second function of any four of the five variables on a second output line 378. The operation of the logic block of FIG. 3a is described more thoroughly in the Xilinx "Programmable Gate Array Data Book", copyright 1988 by Xilinx, Inc., available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
A logic array including configurable blocks such as shown in FIG. 3a or 3b and interconnect lines such as shown in FIG. 2a can be configured to perform a multiplicity of complex logic functions. For example, it can be programmed to perform the function which is represented by the schematic diagram of FIG. 3c. The schematic of FIG. 3c includes input buffers, logic gates AND1OUT, XOR1OUT, OR1OUT, and OR2OUT, flip flops Q1OUT and Q2OUT, and output buffers. As shown in FIG. 3d, the input and output buffers are provided by input/output blocks P2 through P9. These blocks are located at the periphery of the logic array chip. Gates AND1OUT and OR1OUT and flip flop Q1OUT are implemented in logic block AB; gate XOR1OUT and flip flop Q2OUT are implemented in logic block AC, and gate OR2OUT is implemented in logic block AA. Logic blocks AA, AB, and AC can be of the type shown in FIG. 3b. By placing the output of buffers P9, P8, and P7 (FIG. 3d) on leads A, B, and C (FIG. 3b) respectively, setting MUX 104 of FIG. 3b (by loading a memory cell not shown) to provide signal A, MUX 105 to provide signal B, and MUX 106 to provide signal C, and by loading the appropriate truth table into 8-bit RAM 109, signals A, B, and C will cause multiplexer 111 to select the value from RAM 109 to represent the function in FIG. 3d of a two input AND gate plus a third signal serving as input to a two input OR gate. By setting MUX 114 to provide this output as signal F1 and setting MUX 126 to provide this signal as input to flip flop 121, flip flop 121 can be configured to implement flipflop Q1OUT of FIG. 3d. Multiplexers 122 and 142 of FIG. 3b can be configured to provide the Qff output signal of flip flop 121 as the Y output of the logic block. In this way the logic block of FIG. 3b implements the logic shown in block AB of FIG. 3d. Similarly, other logic blocks of the type shown in FIG. 3b can implement the logic shown in blocks AC and AA of FIG. 3d.
Although memory cells have been used in existing logic arrays to control the logic functions performed by the arrays by writing values to the memory cells such as 8-bit RAM 109 of FIG. 3b during a configuration step, these memory cells have not been accessible to a user of the logic array for writing, storing, and reading data during operation of the logic array, as will now be explained.
The prior art memory cell of FIG. 4 comprises two inverters 41 and 42 connected in a loop such that the input of one inverter is connected to the output of the other inverter. Data line (or bit line) Dy is connected to or disconnected from the inverter by address line (or word line) Ax. Either output line Q or its inverse Q controls the state of one of the configuration transistors in a logic block such as shown in FIG. 3a or 3b. A preferred embodiment of this prior art memory cell achieves a known state on power-up and is described in U.S. Pat. No. 4,821,233 issued Apr. 11, 1989, incorporated herein by reference. The memory cell of FIG. 4 is loaded during configuration of the array. This configuration step requires that certain of the pins at the external perimeter of the array be used for configuration signals. When configuration is complete, these same external pins are most frequently configured to serve as data input or output pins. One or two pins have been used to switch the chip from configuration to operation mode but no provision has been available to alter these memory cells during operation after the configuration step is complete. Memory needed by a user during operation of such an array has generally been provided on a separate chip.
In some applications, it may be desirable to have memory distributed within the logic array, and to have the distributed memory available for access by the user during operation of the array. For example, in an application in which the user intends to use a configurable logic array chip as a combination central processing unit, a memory, and a first-in-first-out output buffer, it may be desirable to locate the memory storage close to where the information is generated. If the logic steps are performed by a logic block, storage of, say, one byte of information physically close to the logic block which generates the information requires less silicon area for interconnect lines and fewer interconnect transistors to route the generated information to its storage location.
The present invention provides means and method for programming a configurable logic block so that some of the configuration memory cells of the block can be changed during operation and may be used as a RAM (random access memory) for storing data of the user as well as for generating a logic function. The same logic block can be reconfigured so that at another time the memory cells which were once under control of the user during operation are configured to provide a static logic function which does not change during operation. The present invention offers flexibility not only in how certain memory cells are used but also in where within the logic array the user-accessible data cells are placed.
In one embodiment, the memory cells which may alternatively be used for storing data are those which store the lookup table used for configuring a combinatorial logic function which is within a logic block. Other memory cells may be used only for their configuration function and not alternatively for storing data, for example those which control the interconnection between logic blocks. The MUX memory cells which control connection of flip flops to other elements within a logic block may be alternatively used for data in one embodiment, though in a presently preferred embodiment these MUX internal configuration cells are used for configuration only. It is not presently preferred to use the MUX internal configuration cells alternatively for memory in an embodiment in which there are relatively few MUX configuration cells and the MUX configuration cells are not grouped in groups of eight such that they could be conveniently dedicated to storing at least a byte of information. To use the MUX cells for storage would result in a relatively inefficient use of the powerful logic options available with the preferred embodiment, therefore address lines necessary for such use are not presently provided.
When the option of allowing the user to store data in memory cells is available, there must also be provision for entering the user's data into these cells and reading from the cells. This option is provided by including two means for accessing each dual function cell, one which is used to supply off-chip signals during configuration of the cell and another which is used during operation to store signals which may be generated on-chip.
FIG. 1 shows part of one of the configurable logic array chips for which automatic programming is available.
FIGS. 2A through 2D show a small portion of a configurable logic array chip with interconnects for connecting leads of one CLB or IOB to another CLB or IOB.
FIG. 3a shows one prior art configurable logic block.
FIG. 3b shows another prior art configurable logic block in which memory cells for storing the configuration of the combinatorial logic functions are shown.
FIG. 3c shows a representative logic function which can be implemented by two logic blocks of the type shown in FIG. 3b.
FIG. 3d shows the portions of logic which will be implemented h of the logic blocks.
FIG. 4 shows a prior art 5-transistor memory cell of a type which can be used to configure the configurable logic blocks of FIG. 3a or 3b.
FIG. 5a shows a configurable logic block incorporating the present invention.
FIG. 5b shows a portion of a configurable logic array incorporating the logic block of FIG. 5a.
FIG. 6 shows a 5-transistor memory cell having dual access means for use with the present invention.
FIG. 7 shows a schematic representation of a logic array chip having logic blocks, each logic block providing two logic functions under control of a configuration memory array.
FIG. 8 shows part of one circuit for providing the distributed memory cells of FIG. 6 in the logic block of FIG. 5a.
The overall structure of a logic array chip is represented in FIG. 7. FIG. 7 illustrates a logic array chip having 16 logic blocks. The principles discussed here will of course apply to a chip having any number of logic blocks. The logic blocks shown in FIG. 7 are identical, that is, they can all be programmed to perform the same functions. (Once they have been configured, each logic block performs a specific function as specified by the user, typically not identical to that of other logic blocks. Interconnect lines can provide outputs from one logic block as input to another logic block, again as specified by the user, The blocks in an array are generally not configured identically.) As a feature of the present invention, some of the blocks in an array may serve as memory devices rather than function generators. The user can build a logic system which contains combinatorial logic, flip-flops for logic storage, and groups of memory cells for data storage.
FIG. 7 includes a grid M7 of memory cells for configuring the sixteen logic blocks B1,1 through B4,4. Address lines A1 through A32 run horizontally and data lines D1 through D32 run vertically through grid M7. Ax and Dy denote representative address and data lines respectively. A memory cell is located at each intersection of the grid of FIG. 7. The group of memory cells C1,1 comprises a lookup table for the configuration of function generators F1,1 and G1,1 in block B1,1. The memory cells at the intersections of address line A1 through A4 and data lines D1 through D4 store the lookup table for the function generator F1,1 and each of them may be formed as shown in FIG. 6. The memory cells at the intersection of address lines A5 through A8 and data lines D1 through D4 store the lookup table for the function generator G1,1. Memory cells at the intersections of address lines A1 through A8 with data lines D5 through D8 store configuration information for other parts of the block B1,1 not part of the combinational function generators F1,1 and G1,1. These memory cells may be formed as shown in FIG. 4. Memory cells for the other blocks in FIG. 7 follow the same pattern.
In one embodiment, the combinatorial logic table memory cells at the intersection of address lines A1 through A32 and data lines D1-D4, D9-D12, D17-D20, and D25-D28 have the dual control shown in FIG. 6 so that they may be loaded during configuration of the chip by applying data on lines D1-D4, D9-D12, D17-D20, and D25-D28 while accessing cells through address lines A1 through A32, then loaded (written to) or read by other logic on the chip at any time during operation of the logic array as will be discussed below. Other memory cells preferably have the single access shown in FIG. 4.
FIG. 5a shows a generalized one of the logic blocks Bj,k of FIG. 7 in more detail. FIG. 5b shows the configurable logic block of FIG. 5a surrounded by interconnect structure which is also part of the configurable logic array of FIG. 7. Reference numerals in FIG. 5b which are the same as those in FIG. 5a have the same meaning as they have in FIG. 5a. Referring to FIG. 5a, function generator F1,1 is a multiplexer which reads one of sixteen memory cells (shown in FIG. 7 as at the intersections of address lines A1 through A4 and data lines D1 through D4 but not shown in FIG. 5a) in response to an address provided on four input lines F1, F2, F3 and F4. The loading alternatives of the static memory cell of FIG. 6 make it possible to write into the memory cell of FIG. 6 at a time after the array is configured as well as during the configuration, making certain memory cells in each logic block of the array, for example memory cell Bj,k, separately available to the programmed logic. Previously, data for configuring a function generator came from outside the chip. With the present invention, the data in the function generators such as F1,1 and G1,1 of FIG. 5a are potentially generated on the chip. The user, when configuring the logic array will program the appropriate circuitry to generate the data for memory cells in any function generator being used for memory storage as well as to address these function generator memory cells. Further, with this invention, it is possible to read the memory cell contents during operation as well as to use the memory cell contents to control a logical operation performed by the logic block in which the memory cells reside. The user can write new data into the memory cells and he can then perform the new function represented by the new data or read the data out for use elsewhere in the logic array. Data can be changed one table at a time, under control of the logic programmed into the array. The architecture is more flexible and more efficient because the same memory cells can be used for more than one purpose. Since in a preferred embodiment, logic blocks have the same architecture throughout the array, the distributed memory provided by this invention can be used where needed.
The memory cells of this invention can be used as a RAM. If the user wants a byte-wide register set with 16 bytes of registers, he can program 8 function blocks to be loaded as a RAM, and control these 8 function blocks as a register. Similarly, if the user needs a 256 by 1 bit organization, the outputs of function blocks (each with 32 bits) are multiplexed together to form the required organization by configuring appropriate memory cells during configuration of the array.
Once the array has been configured and memory cells M1 through M5 of FIG. 5a have been set, the use of the memory cells which control function generators G1,1 and F1,1 is established. If they are to be used as memory, the memory contents can be changed, as RAM memory is typically changed, but the fact that the memory in function generators G1,1 and F1,1 can be changed will not be changed until memory cells M1 through M5 are changed. The memory contents in function generator F1,1 can also be used to generate a function F' of inputs F1, F2, F3, and F4. The same is true with function generator G1,1. But the function generator now has the property that other logic in the array can change the function performed by the logic block without the user having to reconfigure the entire logic array.
The circuit of FIG. 5a incorporates the two means for accessing memory cells such as shown in FIG. 6. Write enable line WE can be controlled by a user during operation of the cell to allow for loading data on line DIN into function generator F1,1 or on one of lines DIN or H1 through line Du into function generator G1,1.
The data loaded into the sixteen memory cells of function generator F1,1 or the sixteen memory cells of function generator G1,1 become the truth table entries provided in response to an address input on lines G1 through G4 or F1 through F4. Write enable line WE disables flip-flop storage means FF1 and FF2 by applying the low write-enable signal to AND gates 55 and 56, causing the set and reset inputs of flip-flops FF1 and FF2 to hold data present on their Q output ports regardless of signals applied to the D and clock input lines of flip-flops FF1 and FF2. Thus data provided on line DIN to load memory cells in function generators F1,1 and possible G1,1 is not provided through multiplexers 53 and 54 to flip-flops FF1 and FF2. As can be seen from FIG. 5a, line DIN can be used when the write enable line is high (function generators F1,1 and G1,1 are not being loaded) to provide data to flip flops FF1 and/or FF2 if memory cells M2 through M13 are programmed so that data on line DIN is received on the D input port of flip flops FF1 and/or FF2.
The dual means for controlling the memory cell of FIG. 6 as used in the function generators F1,1 and G1,1 of FIG. 5a will now be explained. The operation of function generators F1,1 and G1,1 is shown in more detail in FIG. 8. Function generator inputs F1 through F4 shown in FIG. 5a are shown in FIG. 8 as selected from among a plurality of signals. In one embodiment, 18 lines are provided from which to select the F4 input signal. Many variations and means for selecting from a plurality of signals are possible. FIG. 5b shows 16 lines from which the F1 signal is taken and 14 from which the F4 signal is taken, each line separately controlled by a memory cell. The variation shown in FIG. 8 provides for selecting the signal from only one of 18 lines by a two step selection process. The signal on each of these 18 lines is buffered through a buffer such as B81. The signals are grouped into three groups of five and one group of three signals. Pass transistors such as transistor M81 are controlled by a multiplexer to select one signal of each group of signals and pass transistors such as transistor M82 are controlled by this multiplexer to select one of the groups of signals, such that a single signal from the 18 lines is presented as the F4 signal. This F4 signal is inverted by inverter I81 and provided as input to NOR gates NOR81 and NOR82. The signal is inverted again by inverter I82 and provided as input to NOR gates NOR83 and NOR84.
A similar operation generates function F2 which is inverted by inverter I83 and provided as input to NOR gates NOR82 and NOR84, and inverted again by inverter I84 and provided to NOR gates NOR81 and NOR83. With this arrangement, only one of NOR gates NOR81 through NOR84 will provide a logical "1" output, thus only one of transistors T81b through T84b will be turned on.
As shown in FIG. 8, a plurality of memory cells, of which memory cells M1,1 and M1,2 are shown, each provide bits of a word stored in function generator F1,1. Each of the memory cells such as memory cells M1,1 and M1,2 are formed as illustrated in FIG. 6. In FIG. 8, the lines for configuring memory cells M1,1 and M1,2 during the process of configuring the entire logic array are labeled Dy1 and Dy2 respectively, and their respective address lines are labeled Ax1 and Ax2. (Of course, memory cells M1,1 and M1,2 may be configured by data applied under control of the same address line, Ax1 for example.)
If it is desired that memory cells M1,1 through M1,16 be accessible during operation of the logic array, memory cell WE-F will be loaded with a logical zero during configuration, thereby providing a logical one to NOR gate NORFHl and enabling NOR gate NORFHl to respond to a write enable signal on line WE if NOR gate NORFHl is also enabled by AND gate ANDFHl.
FIG. 8 does not show the memory cells of the G function generator G1,1, nor does it show means for addressing the memory cells of the G function generator. However, the memory cells of the G function generator F1,1 are addressed, read, and written by circuitry which is identical to that for addressing the F function generator except for the following differences which are shown in FIG. 8. The signal H1 is provided to AND gate ANDFHl and its complement H1 is provided to AND gate ANDGHl. Multiplexer MUX 51 selects which of signals DIN and H1 are provided to the G function generator. If signal DIN is provided to the G function generator, only one of the F function generator and the G function generator will be addressed at one time, since H1 and H1 are complementary signals. Thus the single data line DIN can be used for providing data to memory cells in both F function generator F1,1 and G function generator G1,1. The embodiment discussed in detail here uses 16 memory cells in each of function generators F1,1 and G1,1, and uses four input lines to address each of these sets of memory cells. It is clear that the invention is not limited to this embodiment, since other numbers of memory cells and address lines, for example 128 memory cells and six address lines, could also be used. Further, a logic block need not be limited to providing two functions.
In the embodiment of FIG. 8, there are sixteen memory cells, M1,1 through M1,16 in function generator F1,1 of which only two are shown. Control of the remaining memory cells can be understood from the level of detail shown in FIG. 8. Memory cell M1 enables both AND gate ANDFHl and AND gate ANDGHl and determines whether the logic block of FIG. 5a will treat the 32 memory cells in function generators F1,1 and G1,1 as a single bank of 32 cells for which a single output is selected in response to signals on the eight lines F1 through F4 and G1 through G4, or whether the logic block of FIG. 5a will treat the 32 memory cells in function generators F1,1 and G1,1 as two banks of 16 cells each, for which separate outputs are selected, an F output in response to signals on lines F1 through F4 and a G output in response to signals on lines G1 through G4. Data to be written to memory cells of the F function generator F1,1 (for example memory cells M1,1 and M1,2) are provided on line DIN (shown in both FIG. 5a and FIG. 8).
A logical 1 in memory cell M1 produces a logical 0 on the inverted output of memory cell M1, turning off transistor T51b of MUX 51 and disabling the H1 and H1 inputs to AND gates ANDFHl and ANDGHl respectively. The logical 1 in memory cell M1 turns on transistor T51a in MUX 51, which allows the signals on line H1 to be used as data signals to function generator G1,1. A logical 0 in memory cell M1 turns off transistor T51a so that the signals on line Hi are not provided as data to G function generator G1,1. The high signal provided on the inverted output of memory cell M1 turns on transistor T51b, causing the G function generator G1,1 to receive data on line DIN. This high signal on the inverted output of memory cell M1 is also provided to AND gates ANDFHl and ANDGHl, enabling the signal on lines H1 and H1 to be provided to NOR gates NORFHl and NORGHl respectively. As can be seen in FIG. 8, a logical 1 in memory cell WE-F produces a logical 0 to NOR gate NORFHl. The combination of a logical 1 in memory cell WE-F, a logical 0 in memory Cell M1 (producing a logical 0 to AND gate ANDFHl) and a low signal on write enable line WE allows a high signal on line H1 (logical zero on line H1) to cause NOR gate NORFHl to place a high signal on transistor T81H so that memory cells M1,1, M1,2 and other memory cells (fourteen others in this embodiment) in function generator F1,1 can be written to in response to addresses provided on lines F1 through F4 as decoded by nor gates NOR81 through NOR88 to control transistors such as T85,1 and T81a.
Only one of memory cells M1,1 through M1,16 will be connected at any one time to line DIN by having all three of its write enable transistors such as T85,1, T81a and T81H turned on. In the embodiment of FIG. 8, the decoding is performed in two stages (other decode logic is also possible, as is well known). Writing to memory cells M1,1 through M1,4 is controlled by NOR gate NOR85 which provides a high output signal only when lines F1 and F3 are low. Three other groups of memory cells M5 through M16 (not shown) are addressed by other combinations of signals on lines F1 and F3.
Taking the case when lines F1 and F3 are low, transistors T85,1 through T85,4 will be high. If lines F2 and F4 are low, NOR gate NOR81 will provide a high output signal (and NOR gates NOR82 through NOR84 will all provide low output signals). The high output signal on NOR gate NOR81 will turn on transistors T81a and T81b. If transistor T81H is also on, the data on line DIN as inverted by inverter IIN will be written to memory cell M1,1.
Since transistors T81b and T85b are also turned on by the combination of low signals on lines F1 through F4, the data on DIN which is inverted and entered to memory cell M1,1 will be inverted again by inverter I1,1 and provided on F function generator output line FA. (Of course, rather than providing a separate inverter I1,1, it is possible to provide the Q output of memory cell M1,1 to the output line FA of function generator F1,1. And rather than providing inverters I1,1, I1,2, etc on each of sixteen cells M1,1 through M1,16, it is possible to provide a single inverter to invert and buffer the signal on node N85. However such an embodiment is not preferred because signal propagation would be slower.
If memory cells M1 through M16 are configured as RAM storage, in the embodiment of FIG. 8, they will be read as serial output on the FA output line from F function generator F1,1. The F output signal from function generator F1,1 shown in FIG. 5a is derived by providing the FA output signal of FIG. 8 to an inverter. This data is accessed by connecting, during configuration of the array, the F output line shown in FIG. 5b to a desired input line of another configurable logic block like that shown in FIG. 5b located in another part of the array. As shown in FIG. 5b, the four signals H1, DIN, WE and clock enable signal CE can be taken from interconnect lines physically spaced apart around the logic block. In one embodiment these signals are decoded within the logic block and applied to desired lines, adding another level of programmability.
Of course many other embodiments which provide for loading data both during configuration of the logic array cell and for loading data during operation of the logic array cell are also possible.
In light of the above disclosure, other embodiments of the present invention will become obvious to those skilled in the art. For example, though a table look-up means of using memory cells to provide a combinatorial logic function has been described, other arrangements are also possible such as using memory cells to connect or disconnect AND, OR, XOR, and invert logic gates. For another example, though a memory cell comprising two inverters in series has been described, a typical six-transistor static memory cell can be used and provided with access from two sources. For yet another example, although a logic block having two function generators is shown, it is clear that logic blocks having other numbers of function generators can also be provided, and that memory cells within a plurality of function generators can be controlled to provide different numbers of words of output. Such variations are intended to fall within the scope of the present invention.
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|U.S. Classification
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|International Classification
|Cooperative Classification
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|Nov 30, 1998
|Fee payment
Year of fee payment: 4
|Dec 23, 2002
|Fee payment
Year of fee payment: 8
|Jan 10, 2007
|Fee payment
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|Oct 22, 2009
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Declaration concerning the Laws of Naval War. London, 26 February 1909.
Chapter IV : Destruction of neutral prizes - Art. 54.
Art. 54. The captor has the right to demand the handing over, or to proceed himself to the destruction of, any goods liable to condemnation found on board a vessel not herself liable to condemnation, provided that the circumstances are such as would, under Article 49
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text:
, Volume 39, Issue 4, pp 721-731
First online:
Grounding Concepts: The Problem of Composition
- Gábor ForraiAffiliated withDepartment of Philosophy, University of Miskolc Email author
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In a recent book C.S. Jenkins proposes a theory of arithmetical knowledge which reconciles realism about arithmetic with the a priori character of our knowledge of it. Her basic idea is that arithmetical concepts are grounded in experience and it is through experience that they are connected to reality. I argue that the account fails because Jenkins's central concept, the concept for grounding, is inadequate. Grounding as she defines it does not suffice for realism, and by revising the definition we would abandon the idea that grounding is experiential. Her account falls prey to a problem of which Locke, whom she regards as a source of inspiration was aware and which he avoided by choosing anti-realism about mathematics.
KeywordsA priori Arithmetic Knowledge Mathematics Concept
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- Title
- Grounding Concepts: The Problem of Composition
- Journal
Volume 39, Issue 4 , pp 721-731
- Cover Date
- 2011-12
- 10.1007/s11406-011-9307-8
- Print ISSN
- 0048-3893
- Online ISSN
- 1574-9274
- Publisher
- Springer Netherlands
- Additional Links
- Topics
- Keywords
- A priori
- Arithmetic
- Knowledge
- Mathematics
- Concept
- Authors
- Gábor Forrai (1)
- Author Affiliations
- 1. Department of Philosophy, University of Miskolc, 3515, Miskolc-Egyetemváros, Hungary


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Petroplus Slumps on Plan to File for Insolvency: Zurich Mover
Petroplus Holdings AG, the largest independent European refiner, said it plans to file for insolvency. The stock plunged 84 percent.
The Zug, Switzerland-based company said in a statement today that it will seek to ensure that operations are "safely shut down and to preserve value for all stakeholders."
The announcement marks a further decline in Europe's refining industry after BP Plc and Royal Dutch Shell Plc cut capacity as margins thinned and fuel demand stopped growing. Petroplus had about $1 billion in credit lines frozen last month, preventing it from supplying plants with crude. It said last week it may sell three of its five European plants.
"With the bankruptcy, the worst scenario for the company came true," Martin Schreiber, an analyst at Zuercher Kantonalbank, wrote in a note to investors. "How much shareholders will be entitled to from the bankruptcy can barely be estimated due to the opaque situation of Petroplus."
BP and Shell, Europe's biggest oil companies, said the supply of fuels to their services stations hasn't been disrupted. BP sold the Coryton refinery in the U.K. to Petroplus in 2007, and Shell sold Petroplus the Petit Couronne plant in France a year later. Essar Energy Plc said its Stanlow refinery in the U.K. would look to "fill gaps in the market" caused by Coryton's closure.
Sell Refineries
Petroplus said last week that it might sell refineries in France, Belgium and Switzerland, while continuing to operate the plants in the U.K. and Germany. As well as trying to renegotiate financing with its banks, Petroplus had also been seeking a crude supply deal on terms that would reduce the cash needed to keep refineries going.
"We have worked hard to avoid this outcome, but were ultimately not able to come to an agreement with our lenders to resolve these issues given the very tight and difficult European credit and refining markets," Chief Executive Officer Jean-Paul Vettier said in the statement.
Petroplus slid 1.23 francs to 24 centimes at the close in Zurich. The company's shares were suspended from trading in Switzerland yesterday. The stock has lost 98 percent of its value in the past year. Petroplus's market value is now 23 million francs ($25 million).
Default Event
Petroplus's lenders yesterday sent a notice of acceleration to the company, demanding immediate repayment of its $1.1 billion revolving credit facility. The acceleration also "constitutes an event of default" on $1.75 billion of outstanding senior and convertible bonds, the company said in today's statement.
The credit line was frozen Dec. 27 after Petroplus breached covenants in September when earnings before interest, tax, depreciation and amortization fell below the required 2.5 times net interest expense. Banks had earlier waived some loan terms until the end of the first quarter of 2012 to give the company time to renegotiate the loan and secure crude supply.
BNP Paribas
BNP Paribas SA, Commerzbank AG, Credit Suisse Group AG, ING Groep NV, Fortis Bank Nederland and Natixis SA arranged the credit line in 2009, which paid interest of 300 basis points more than the London interbank offered rate, or Libor, according to data compiled by Bloomberg.
The refiner had halted deliveries from its U.K. plant after lenders forced it to stop selling fuel, Richard Howitt, a European Parliament member for the east of England, said in a statement yesterday.
Earlier this month, the company reached a temporary agreement with creditors to keep plants in Coryton, and Ingolstadt, Germany, in operation. Petroplus's credit rating was cut by Standard & Poor's for a second time on Jan. 17.
The outlook for oil refining in the next two decades is "dire" given excess capacity in the industry, BP's Chief Economist Christof Ruehl said on Jan. 18. Other refineries in Europe have been forced to close because overcapacity is making it unprofitable to turn crude oil into gasoline and other fuels.
LyondellBasell Industries NV decided to close its 105,000 barrel-a-day Berre refinery in France after failing to find a buyer.


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In the Management Page Tab, in the Messages section, there are four formatting buttons above each message. Those buttons are: Bold, Italic, Link, and Image.
They don't seem to do anything.
I've highlighted text, clicked any/all of the buttons and nothing happens.
I've tried using the buttons without highlighting text as well. Still, nothing happens.
What am I doing wrong?


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Without manually changing the content and without relying on .htaccess redirects (or the Redirection plugin), I'm trying to write a script that finds and alters specific URLs within the content of pages or posts.
The hurdle I'm facing is that I want this to work with shortcodes and the like -- for example I'd like it to work with Dagon Design's sitemap generator.
So it needs to filter URLs generated by those shortcodes before the content is rendered to the browser. Odd problem to create for myself and try to solve, I know.
Any ideas?