text:
|Publication number
|Publication type
|Application number
|Publication date
|12 Aug 2003
|Filing date
|18 Oct 2001
|Priority date
|23 Jun 1998
|Fee status
|Also published as
|Publication number
|Sau C. Wong
|Original Assignee
|Sandisk Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (46), Non-Patent Citations (16), Referenced by (50), Classifications (31), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This patent document is a continuation of U.S. patent application Ser. No. 09/670,764, filed Sep. 27, 2000, now U.S. Pat. No. 6,314,025, which is a continuation of U.S. patent application Ser. No. 09/128,225, filed Aug. 3, 1998, now U.S. Pat. No. 6,134,145, which is a continuation-in-part of U.S. patent application Ser. No. 09/103,623, filed Jun. 23, 1998, now U.S. Pat. No. 5,969,986, which are incorporated by this reference in their entirety.
1. Field of the Invention
This invention relates to write processes for non-volatile memories and particularly to methods of reducing the current required when writing at a high data rate.
2. Description of Related Art
Semiconductor non-volatile memories such as EPROM, EEPROM, and flash memories, which permit electrical erasing and programming of memory cells, are well known. Such memories conventionally include arrays of memory cells where each memory cell includes a floating gate transistor. Write and erase circuits coupled to an array write to or erase a memory cell in the array by electrically charging or discharging the floating gate of the floating transistor in the memory cell to change the threshold voltage of the transistor. In particular, to write to a selected memory cell, the write circuit charges the floating gate of the floating gate transistor in the selected memory cell until the threshold voltage of the transistor is at a level that represents the value being written.
One write method for a non-volatile memory cell uses channel hot electron injection. A typical channel hot electron injection process applies a high voltage (about 12 volts) to the control gate of a floating gate transistor, applies a high voltage (about 5 volts) to the drain of the floating gate transistor, and grounds the source of the floating gate transistor. The high drain-to-source voltage causes a relatively large current through the floating gate transistor. The high control gate voltage attracts energetic (or hot) electrons that can pass from the channel through an insulating layer to the floating gate of the floating gate transistor. As electrons accumulate in the floating gate, the threshold voltage of the floating gate transistor increases, the drain-to-source current falls, and the rate of increase in the threshold voltage drops.
Conventional integrated circuit non-volatile memory currently uses a supply voltage between about 3 volts and about 5 volts. Accordingly, a non-volatile memory using channel hot electron injection for programming typically requires charge pumps to generate the high control gate voltage and the high drain voltage. The sizes of such charge pumps determine the number of memory cells that can be programmed in parallel. In particular, to program N cells in parallel a charge pump must be able to supply N times the current drawn by a single memory cell. At the start of a programming operation, the drain-to-source current through a memory cell being programmed is highest and places the greatest load on the charge pump supplying the drain voltage. Specifically, the charge pump supplies a maximum drain-to-source current Idsmax to each of N memory cells at the start of a parallel programming operation, and the charge pump must be able to supply a total current of N*Idsmax without an unacceptable drop in the drain voltage. If the required programming current could be reduced, a smaller charge pump could be employed which can reduce the overall memory circuit size and cost. Additionally, power consumption could be reduced, which is crucial for portable or battery operated applications.
Another concern in a non-volatile memory that stores an analog value or multiple bits of information in each memory cell is the precision of the write operation. Best precision and repeatability require nearly constant supply and programming voltages during programming. However, as noted above for programming operations, current drain is high at the beginning of the programming operation and falls as a memory cell threshold voltage rises. Accordingly, the charge pumps and the supply voltage in the memory are subject to changing current demands which cause voltage fluctuations or noise that can affect the accuracy and repeatability of write operations. Thus, methods of reducing current consumption, voltage fluctuations, and noise during programming are desired.
In accordance with the invention, a non-volatile memory has multiple write pipelines that are sequentially started on programming operations and has a shared charge pump that supplies drain-to-source currents during the programming operations. With sequential starts, the programming operations are staggered, and the peak current for the multiple programming operations do not occur at the same time. Accordingly, sequential starting of programming operations in the write pipelines avoids the high combined peak current that occurs in memories that simultaneously start multiple programming operations. The staggered operations of the write pipelines also provide a high data rate because all of the write pipelines can operate at the same time to provide the same data rate as a conventional memory that performs parallel programming operations. The smaller peak current allows the charge pump and associated voltage regulation circuitry to be smaller than similar circuitry used in conventional memory that performs parallel programming operations. Additionally, since spikes in the current from the charge pump are relatively small, memories with sequential or staggered programming operations generate less noise in the supply voltage during programming, and permit accurate programming for applications such as analog or multiple-bits-per-cell storage.
One embodiment of the invention is a non-volatile semiconductor memory that includes multiple write pipelines, a shared charge pump, and a timing circuit. Each of the write pipelines includes an array of non-volatile memory cells and a write circuit coupled to the associated array. When started on a programming operation for a selected memory cell in the associated array, a write circuit applies a programming voltage to the selected memory cell to drive a current through the selected memory cell, for example, to cause channel hot electron injection which raises a threshold voltage in the selected memory cell. The charge pump generates the programming voltage from a supply voltage and supplies the programming voltage to all of the write pipelines for the programming operations. The timing circuit sequentially starts the programming operations by the write circuits. Accordingly, at most one write pipeline at a time requires the maximum programming current from the charge pump, and the charge pump and any associated voltage regulation circuitry can be smaller than that required in a memory that simultaneously starts multiple programming operations. The shared charge pump and sequential starting of programming operations can be beneficially employed in a binary memory, a multiple-bits-per-cell memory, and an analog memory.
Each write pipeline may additionally include selection circuitry that selects a voltage applied to the selected memory cell during programming. The selection circuitry selects the programming voltage for changing the threshold voltage of the selected memory cell during a series of programming cycles and selects a second voltage for testing the threshold voltage of the selected memory cell during a series of verify cycles. The programming operation in a pipeline ends when a verify cycle determines that the threshold voltage of the selected cell reaches its target level. The write pipelines can be divided into two banks, a bank of even numbered pipelines and a bank of odd numbered pipelines, such that when a programming operation in an even pipeline overlaps a programming operation in an odd pipeline, the even pipeline performs programming cycles and verify cycles when the odd pipeline respectively performs verify cycles and programming cycles. The interleaving programming and verify cycles in this fashion cuts the peak and average current requirement in half because at most one half of the write pipelines draw current from the charge pump at a time. Alternatively, the pipelines can be partitioned into three or more banks where each bank starts programming cycles at a different time.
FIG. 1 is a block diagram of a non-volatile semiconductor memory in accordance with an embodiment of the invention.
FIG. 2 is a timing diagram for a recording operation performed by the non-volatile memory of FIG. 1.
FIG. 3 is a plot of programming current versus time during a pipelined write operation using eight write pipelines.
FIG. 4 is a plot of programming current versus time during a pipelined write operation using sixty-four write pipelines.
FIG. 5 is a block diagram of an analog or multiple-bits-per-cell non-volatile memory in accordance with an embodiment of the invention.
FIG. 6 is a timing diagram for recording operations performed by the memory of FIG. 5.
Use of the same reference symbols in different figures indicates similar or identical items.
A non-volatile floating-gate memory in accordance with an embodiment of the invention performs pipelined writes that stagger the starts of channel hot electron injection processes. The pipelined writes provide a high data rate by programming multiple memory cells at a time. However, the programming operations do not start or end simultaneously and are at different stages of completion. In accordance with an aspect of the invention, a single charge pump supplies a high voltage that drives drain-to-source currents for programming processes such as channel hot electron injection in multiple memory cells. Since the programming operations have staggered starts, the maximum current that the charge pump must provide is less than the peak current for a single programming operation times the number of memory cells being simultaneously programmed. Accordingly, at a fixed data rate, the charge pump required for the pipelined write scheme can be smaller than the charge pump required for a parallel write scheme that starts multiple programming operations simultaneously. Further, staggering starts of programming operations smoothes the current drawn for the write operation and reduces noise that could disturb the accuracy of the write operation. These aspects of the invention can be beneficially applied in binary (i.e., one-bit-per-cell) memories, multiple-bits-per-cell memories, and analog memories.
FIG. 1 is a block diagram of a non-volatile memory 100 in accordance with an embodiment of the invention. Memory 100 includes multiple arrays 130-1 to 130-N of Flash memory cells in respective write pipelines 110-1 to 110-N. Write pipelines 110-1 to 110-N and memory arrays 130-1 to 130-N are sometimes referred to herein as pipelines 110 and arrays 130. Although FIG. 1 shows three pipelines 110, memory 100 can include any number N of pipelines. The number of pipelines provided determines the number of programming operations memory 100 conducts at a time and accordingly controls the maximum write frequency or data rate of memory 100. As described more fully below for a pipelined write or recording of data, a timing circuit 140 sequentially starts pipelines 110 on programming operations, and pipelines 110 operate individually to complete the programming operations.
Each non-volatile memory array 130 can be a conventional non-volatile memory array. Such memory arrays are known for storing a binary, analog, or multi-bit digital value in each memory cell. Arrays 130 include rows and columns of memory cells, where each memory cell is, for example, a single floating gate transistor, a split gate transistor, or a multiple-transistor memory cell. In an exemplary embodiment of the invention, which is described below, memory 100 is a flash EEPROM, and each memory cell consists of a single N-channel floating gate transistor. Other memory architectures are also suitable. Control gates of the memory cells in a row of an array 130 are coupled to a row line associated with the row. Drains of the memory cells in a column of an array 130 are coupled to a column line associated with the column, and sources of the memory cells in a sector of an array 130 are coupled to a source line associated with the sector. In the exemplary embodiment, each sector contains multiple columns of memory cells but alternative memory architectures use different kinds of sectors, for example, sectors containing one or multiple rows of memory cells.
Memory arrays 130 are separate in that a programming operation in one array 130 does not directly affect programming operations in other arrays 130. Each memory array 130 has a row decoder 132 and a column decoder 134. Each row decoder 132 receives a row address signal, selects a row line in the associated array 130, and during a programming operation, conveys bias voltages to the selected row line and unselected row lines in the associated array 130. Each column decoder 134 receives a column address signal, selects a column line in the associated array 130, and conveys bias voltages to the selected column line and unselected column lines in the associated array 130 during write operations.
Memory 100 is capable of performing two types of write operations. The first type, referred to herein as a pipelined write operation, sequentially starts programming operations in pipelines 110-1 to 110-N and ends when the programming in memory array 130-N is complete. The second type of write operation, referred to herein as a recording operation, cyclically starts programming operations in pipelines 110-1 to 110-N and continues until after a signal RESET is asserted to stop the recording. In general, the pipelined write operation stores a fixed amount of data in arrays 130, and a recording operation stores a continuous data stream of variable length in memory arrays 130.
Timing circuit 140 starts and controls pipelined write operations and recording operations in pipelines 110. In the exemplary embodiment of the invention, timing circuit 140 includes N flip-flops 144-1 to 144-N that are connected to operate as a shift register. Flip-flops 144-1 to 144-N respectively correspond to read/write pipeline 110-1 to 110-N and start the corresponding pipelines 110 on programming operations at falling edges of output signals SR1 to SRN.
Write circuits 120-1 to 120-N (some times referred to herein as write circuits 120) control programming operations in respective pipelines 110-1 to 110-N. In particular, write circuits 120-1 to 120-N receive respective data values from respective data sources 125-1 to 125-N, and as timing circuit 140 starts each write circuit 120, the write circuit generates programming signals VROW and VCOL that associated row and column decoders 132 and 124 apply to a selected memory cell being programmed in the associated array 130. The structures of write circuits 120 and data sources 125 depend on the type of data values being stored the associated memory array. In one alternative embodiment, memory 100 is an analog memory, and data sources 125-1 to 125-N are sample-and-hold circuits that sample an input analog signal at rising edges of the associated signals SR1 to SRN. U.S. Pat. No. 5,680,341 to Wong et al., which is hereby incorporated by reference in it entirety, describes analog memories with multiple read/write pipelines and describes use of sample-and-hold circuits and write circuits for analog memories.
In another alternative embodiment, memory 100 is a binary or multiple-bits-per-cell memory. For binary and multiple-bits-per-cell memories, each data source 125 can include one or more latches, flip-flops, or volatile memory cells (e.g., SRAM or DRAM cells) that temporarily hold one or more bits of data for writing to the selected non-volatile memory cell in the associated array 130. When the associated one of signals SR1 to SRN starts a write circuit 120, the write circuit 120 generates programming signals VROW and VCOL which row decoder 132 and column decoder 134 respectively apply to the selected row and column lines to write the data value from the associated data source 125 to the selected memory cell.
In one specific embodiment of the invention, memory 100 is a binary memory where each memory cell has a low threshold voltage when in an erased state representing a binary 0. (Clearly, other interpretations of the threshold voltages of memory cells are possible. For example, a low threshold voltage could represent a binary 1.) For this embodiment, each data source 125 includes a latch, and at the start of a pipelined write operation, data sources 125 collectively and in parallel latch a multi-bit input data value, one bit per data source 125. Timing circuit 140 then begins sequentially starting write circuits 120-1 to 120-N on programming operations. Each write circuit 120 receives a data bit from the associated data source. If the data bit is a binary one, the write circuit 120 generates row signal VROW and column signal VCOL at high voltages Vcp and Vw. (Typically, voltage Vcp is about 12 to 13 volts and voltage Vw is about 5 to 6 volts.) In accordance with an aspect of the invention, a single charge pump 150 generates voltage Vw for all of the write circuits 120-1 to 120-N. The combination of a grounded source line, voltage Vcp being applied to the selected row line, and Vw being applied to the selected column line induces channel hot electron injection in the selected memory cell which increases the threshold voltage of the selected memory cell. Write circuit 120 continues programming the selected memory cell for a fixed time that is sufficient to raise the threshold voltage of the selected memory above a cut-off level so that the threshold voltage of the selected memory cell after programming represents a binary one. If the data bit from a data source 125 is binary zero, the associated write circuit grounds signal VCOL so that the selected memory cell remains in the threshold voltage state representing a binary zero.
The pipelined write operation for the binary memory embodiment is complete when the last write pipeline 110-N finishes its programming operation. However, another pipelined operation can begin before a previous pipelined write operation is complete if latching a new input value into data sources 125 will not interfere with the previously started pipelined operation and if starting a programming operation in pipeline 110-1 will not interfere with a programming operation previously started in pipeline 110-1. Accordingly, memory 100 can achieve the same write frequency or data rate as a memory using N simultaneously-started, parallel programming operations.
A recording operation is equivalent to a series of pipelined write operations where one pipelined write operation starts immediately after the other. FIG. 2 shows a timing diagram for a recording operation in memory 100. To start recording operation, a signal ENABLE is asserted to an OR gate 142 in timing circuit 140. OR gate 142 has an output terminal coupled to the data input terminal of flip-flop 144-1. At time 210, the rising edge of a clock signal SAMPLECLK causes flip-flop 144-1 to register the high output signal from OR gate 142 and assert signal SR1 high. In some embodiments, the rising edge of signal SR1 activates data source 125-1. For example, in an analog memory, a sample-and-hold circuit in data source 125-1 can sample an analog input signal in response to the pulse 215 in signal SR1. In a binary or multiple-bits-per-cell memory, data source 125-1 responds to pulse 215 by registering one or more bits of information for writing to memory array 130-1.
At a time 220, signal SAMPLECLK triggers flip-flops 144-1 to 144-N. Flip-flop 144-1 deasserts signal SR1, and flip-flop 144-2 asserts signal SR2. The falling edge of signal SR1 starts write circuit 120-1 on a programming operation that writes the data value from data source 125-1 to the selected memory cell in memory array 130-1. The rising edge of signal SR2 activates data source 120-2 which makes the next data value available to write circuit 120-2. With each consecutive rising edge of signal SAMPLECLK, another write circuit 120 and another data source 125 are activated. For the recording operation, signal RECORD is asserted so that an AND gate 146 passes signal SRN via OR gate 142 to the data input of flip-flop 125. Accordingly, timing circuit 140 asserts signal SR1 the sample clock cycle after asserting signal SRN. The frequency of clock signal SAMPLECLK depends on the required write time and is such that a programming operation started in any of the pipelines 110 completes in less than N clock cycles of signal SAMPLECLK. The recording operation continues cyclically starting programming operations in this fashion until a signal RESET is asserted or signal RECORD is deasserted and a last programming operation begins in pipeline 110-N.
An advantage of the recording operation and the pipelined write operation over a parallel write operation having the same data rate is a reduction in the maximum current that write circuits 120 draw from shared charge pump 150. FIG. 3 illustrates this advantage by showing a simulation of the current drawn from charge pump 150 for a pipelined write operation when memory 100 includes eight pipelines 110. A characteristic of channel hot electron injection in standard programming operations is that the drain-to-source current through the memory cell almost instantly rises to its maximum level and then decreases with time as the floating gate charges and the threshold voltage of the memory cell rises. For example, FIG. 3 shows a current-versus-time plot 311 for the programming operation in pipeline 110-1. For plot 311, the peak current of about 475 μA occurs almost immediately after the start of the programming operation. The current drops sharply during programming until little after 10 μs when the programming operation in pipeline 110-1 is complete and write circuit 120-1 shuts off the current. Current-versus-time plots 312 to 318 are for the independent programming operations in pipelines 110-2 to 110-N (where N is 8) but follow the same pattern as plot 311. Plots 311 to 318 are offset in time relative to each other because timing circuit 140 staggers the starts of the programming operations.
FIG. 3 presumes that programming operations are required in each of eight write pipelines and that the programming time is the same for each programming operation. This presumption provides the highest peak total current and is correct, for example, in a binary memory writing eight bits of value 1 or in analog or multiple-bit-per-cell memories where the row line voltage is selected so that the programming time is constant (e.g., independent of the data value being written.)
Plot 320 is the sum of plots 311 to 318 and indicates the total current drawn from charge pump 150. As shown by plot 320, a maximum total current is about 1.2 mA. In contrast, if programming operations where started simultaneously in pipelines 110-1 to 110-N, the plot of the total current would be shaped like plot 311 but be eight times greater in magnitude. Accordingly, for simultaneously started programming operations, the maximum total current would be about 3.8 mA or more than three times the maximum total current required for the pipelined write operation. Further, the write methods, parallel and pipelined, have the same effective write frequency or data rate because a pipelined write operation permits starting another pipelined write operation immediately after the programming operation in the first pipeline 110-1 is complete even if the programming operation in the last pipeline 110-N has not completed. Accordingly, charge pump 150 can be small to save circuit area and cost and still provide current necessary for a high data rate.
Another advantage the pipelined write operation with a shared charge pump is that total current drawn has less severe spikes. In particular, each local maxima 321 to 328 in plot 320 is a spike that is less than one eighth as sharp as the spike which would occur for a parallel write operation. Accordingly, noise generated in the memory caused by changing current and voltage drops are reduced in severity. This advantage is better illustrated in FIG. 4 which shows a total current-versus-time plot 420 for the total current drawn from pipelined write operation that writes to sixty-four memory cells. In FIG. 4, the current draw from charge pump 150 remains in a range between about 7.0 and 7.5 mA, rather than being sharply peaked at the start of each write operation. It should be further noted that the maximum total current of about 7.5 mA is only about 13 times greater than the maximum current (about 0.5 mA) for each individual programming operation, and that parallel programming of sixty-four memory cells would require about five times more current than the pipelined write operation.
FIG. 5 is a block diagram of a non-volatile analog memory 500 in accordance with an embodiment of the invention. Memory 500 includes multiple arrays 130-1 to 130-N of non-volatile memory cells in respective read/write pipelines 510-1 to 510-N. Arrays 130-1 to 130-N are non-volatile memory arrays as described above in regard to FIG. 1, and each memory array 130 has a row decoder 132 and a column decoder 134 as described above. Additionally, each array 130 has a sense amplifier circuit 536, which may contain multiple sense amplifiers. Column decoders 134 also connect associated sense amplifier circuits 536 to the associated memory arrays 130 for read operations and for verify operations when writing to an array 130. Sense amplifier circuits and row, column, and erase decoders are well known. As described more fully below, output signals from sense amplifier circuits 536 clock or trigger sample-and-hold circuits or other temporary storage circuits and may include circuitry such as a one-shot circuit in addition to conventional sense amplifier circuitry. U.S. patent application Ser. No. 5,687,115, which is hereby incorporated by reference in its entirety, illustrates examples of such circuits.
Memory arrays 130 are separate in that write and read operations in one array 130 do not affect write and read operations in other arrays 130. However, a global sector erase decoder 572 conveys the appropriate bias voltages to source lines for all sectors in arrays 130. For an erase operation, an erase control circuit 570 generates an erase signal Verase (typically about 12 V during an erase) and causes decoder 572 to select one or more sectors in arrays 130. In particular, decoder 572 receives erase signal Verase and one or more address signals identifying one or more sectors selected for erasure. Decoder 572 then applies erase signal Verase to the source lines of the selected sectors and grounds the source lines associated with the unselected sectors. Row decoders 132 ground all of the row lines in the arrays containing one or more of the selected sectors, and column decoders 134 allow all column lines associated with the sectors being erased to float. Erase control circuit 570 uses a voltage generator 586, typically a charge pump with regulator circuits, for generating a high voltage Vcp for erase signal Verase. As described below, erase control circuit 570 shares charge pump 586 with a row write voltage generator 550.
A recording operation or a pipelined write operation sequentially writes a series of values in a number of memory cells. In memory 500, the values written are samples of an analog input signal Ain representing either analog data values or multi-bit digital data values. A playback operation reads and outputs the series of values (or samples from memory 500) to reproduce the recorded sequence (or signal). In one embodiment of the invention, memory 500 uses pipelines 510-1 to 510-N in a staggered fashion during playback to provide a high read data transfer rate. An alternative playback operation performs parallel read operations in pipelines 510 and serially shifts out the values read from the memory cells, if necessary to reproduce the timing of an input signal Ain.
In memory 500, row write voltage generator 550 generates two write signals Vpp and Vvfy from input signal Ain. Write signal Vpp provides a programming voltage that write circuitry applies to the control gate of a memory cell during programming to change the threshold voltage of the memory cell. The voltage of write signal Vpp has a one-to-one correspondence with the present level of input signal Ain. Typically, write voltage generator 550 selects a higher voltage level for signal Vpp when a higher threshold voltages is being written. Appropriate selection of voltage for signal Vpp makes programming time for writing a target threshold voltage nearly independent of the target threshold voltage. Thus, the write resolution is uniform across the range of threshold voltages. Write signal Vvfy, which has a voltage corresponding to the target threshold voltage to be written to the memory cell, is used to accurately determine when the target threshold voltage is reached whereupon the programming operation stops. An interative program-and-verify write process such as described in more detail below minimizes effects of memory cell variation. Alternatively, a timed programming operation stops after a specific time and does not require write signal Vvfy or the circuitry associated with generating or holding signal Vvfy. In this case, one sample-and-hold circuit per pipeline is sufficient.
In the exemplary embodiment memory 500, generator 550 includes voltage shifters that linearly map input signal Ain, which is, for example, in a range from 3 to 6 volts, to signal Vpp in a range from 9 to 12 volts and to signal Vvfy in a range from 3 to 6 volts. Voltage generators for write circuits in analog or multiple-bits-per-cell memories are further described in U.S. patent application Ser. No. 5,687,115. Charge pump 586 supplies voltage Vcp to voltage generator 550 for generation of signal Vpp. A charge pump 584 can supply a voltage Vsh, which is greater than the highest threshold voltage, to voltage generator 550 for generation of signal Vfy.
Column write voltage generator 555 provides a constant voltage signal Vw for driving the drain-to-source current through a memory cell during a programming operation and a constant voltage signal Vr for read and verify operations described below. Typically, signal Vw has a voltage between 5 and 6 volts, and a charge pump and voltage regulator circuit 582 generates signal Vw from a supply voltage Vcc between 3 and 5 volts. Signal Vr typically has a voltage of about 1 to 1.5 volts and can be generated from supply voltage Vcc using a voltage divider.
The write circuitry in each pipeline 510 includes row decoder 132, a row line voltage selection circuit 533, column decoder 134, a column line voltage selection circuit 535, sense amplifier circuit 536, sample-and-hold circuits 521 and 522, and multiplexers 523, 524, and 526. (Sample-and-hold circuits 521 and 522 and multiplexers 523, 524, and 526 are involved in both read and write operations.) Multiplexers 523 and 524 are coupled to sample-and-hold circuits 521 and 522 and respectively select trigger signals and input signals for sample-and-hold circuits 521 and 522. For a write operation, multiplexer 523 selects the output signal of the associated flip-flop 144 to trigger both sample-and-hold circuits 521 and 522, and input selection circuit 524 selects and applies signals Vpp and Vvfy to respective input terminals of sample-and-hold circuits 521 and 522. When the output signal from the associate flip-flop 144 transitions, sample-and-hold circuits 521 and 522 sample and store the current voltages of respective write signals Vpp and Vvfy.
Row voltage selection circuit 533 selects the bias voltage that row decoder 132 applies to the selected row line. During a write, row voltage selection circuit 533 selects the voltage from selection circuit 526, and selection circuit 526 alternates between selecting sampled signals Vpp and Vvfy from sample-and-hold circuits 521 and 522 respectively. Row decoder 132 applies the signal VROW from selection circuit 533 to the selected row line and grounds unselected row lines. Column voltage selection circuit 535 selects the bias voltage that column decoder 134 applies to the selected column line. Column decoder 134 allows the voltage on the unselected column lines to float. During a write, voltage selection circuit 535 alternates between selecting signal Vw and signal Vr. More specifically, column voltage selection circuit 535 selects signal Vw for application to the selected column line of the associated array 130 when row voltage selection circuits 526 and 533 select the sample of signal Vpp for application to the selected row of the associated array. Column voltage selection circuit 535 selects signal Vr for application to the selected column line of the associated array 130 when row voltage selection circuits 526 and 533 select the sample of signal Vvfy for application to the selected row of the associated array.
Memory 500 uses three internal elevated voltages Vcp, Vsh and Vw which charge pump and voltage regulation circuits 582, 584, and 586 respectively generate from the supply voltage Vcc. Voltage Vcp is normally a 12-13 volt supply which supports all of the on-chip high-voltage needs, including the generation of the erase voltage Verase and the variable control-gate voltage Vpp. Voltage Vcp is also supplied to sample-and-hold circuits 521 for sampling of signal Vpp for a programming operation. Voltage Vsh is a voltage greater than the highest threshold voltage used in a memory cell and is normally a 7-8 volt supply. Voltage ramp circuit 560 uses voltage Vsh when n generating a control-gate voltage signal Vsr for a read operation. Sample-and-hold circuits 521 and 522 use voltage as a supply voltage when sampling signal Vsr during a read, and write voltage generator 550 uses voltage Vsh in generating the variable control-gate signal Vvfy for a verify operation. Voltage Vw is normally a 5-6 v supply used for supplying the programming current of the memory cell. Current sourcing requirements for voltages Vcp and Vsh are relatively low since voltages Vcp and Vsh predominantly charge capacitance. Accordingly, charge-pumps 586 and 584 typically require a relatively small area of silicon in an integrated circuit. However, current sourcing requirement of voltage Vw are potentially large. Generally, the current that charge pump 582 must supply depends on the programming current characteristics of the non-volatile memory cell in arrays 130 and the total number of memory cells which need to be programmed at the same time, which in turn is determined by the write data bandwidth requirement.
FIG. 6 shows timing diagrams for an exemplary recording process in memory 500. Initially, a signal RESET resets flip-flops 144, and memory arrays 130 are prepared for write operations. For most non-volatile memories such as EEPROM, EPROM, or Flash memory preparation for a write operation includes erasing storage locations to which information will be written. To start recording, signal RESET is deasserted, and a pulse 605 in an input signal ENABLE to OR gate 142 is asserted high for about one clock cycle of a clock signal SAMPLECLK. OR gate 142 provides enable pulse 605 as the input signal to flip-flop 144-1, and output signal SR1 from flip-flop 144-1 goes high at a rising edge 610 of signal SAMPLECLK. Signal SR1 triggers sample-and-hold circuits 521 and 522 in pipeline 510-1. In response to the next rising edge 620 of sampling clock SAMPLECLK, flip-flop 144-1 deasserts signal SR1, and flip-flop 144-2 asserts signal SR2. A pulse thus propagates through flip-flops 144-1 to 144-N, and signals SR1 to SRN sequentially trigger sample-and-hold circuits 521 and 522 in pipelines 510-1 to 510-N. Each pipeline 510 thus begins sampling write signals Vpp and Vvfy at different times. The last flip-flop 144-N is coupled to an input terminal of OR gate 142 so that signal SR1 is asserted again after signal SRN. The recording process continues starting write operations by cyclically triggering sample-and-hold circuits 521 and 522 until signal RESET stops the pulse from propagating around the ring of flip-flops 144.
During a write, sample-and-hold circuits 521 and 522 in pipelines 510-1 to 510-N sample write signals Vpp and Vvfy in response to the corresponding signals SR1 to SRN. When signal SR1 is asserted at time 610, sample-and-hold circuits 521 and 522 in pipeline 510-1 sample write signals Vpp and Vvfy, and pipeline 510-1 begins writing in a memory cell of array 130-1 a value that signal Ain represented during interval 615. When signal SR2 is asserted at time 620, sample-and-hold circuits 521 and 522 in pipeline 510-2 sample write signals Vpp and Vvfy, and pipeline 510-2 begins writing in a memory cell of array 130-2, a value signal Ain represented during interval 525. Each row voltage select circuits 538 uses the sampled values of the write signals Vpp and Vvfy from multiplexer 526 for a write process that sets the threshold voltage of a selected memory cell to a target threshold voltage. The target threshold voltage is the level that represents the voltage of input signal Ain when write signals Vpp and Vvfy were sampled.
The write process for memory 500 includes generating a series of programming cycles that are interleaved with verify cycles. FIG. 6 shows the example of write processes that start with a programming cycle, but an alternative write process can begin with a verify cycle. During each programming cycle, multiplexer 526 selects the Vpp sample from sample-and-hold circuit 521, and row decoder 132 applies the sampled voltage to a row line selected according to an input address signal identifying a selected memory cell in array 130. Voltage Vpp is typically in the range from 9 to 12 volts. Row decoder 132 grounds unselected row lines. Selection circuit 535 selects voltage Vw during a programming cycle, and column decoder 134 applies voltage Vw to the column line connected to the selected memory cell and grounds unselected column lines. Decoder 572 grounds the source line of the sector containing the selected memory cell. The combination of voltages applied to the control gate, source, and drain of the selected memory cell during a programming cycle causes channel hot electron injection into the floating gate of the selected memory cell and increases the threshold voltage of the selected memory cell.
During a verify cycle, multiplexer 526 selects the Vvfy sample from sample-and-hold circuit 522. Row decoder 132 applies the sampled level of signal Vvfy to the selected row line and grounds the unselected row lines. Select circuit 135 selects read voltage Vr, and column decoder 134 applies read voltage Vr and connects sense amplifier 536 to the selected column line. Column decoder 134 grounds the unselected column lines. Decoder 572 continues to ground the source line coupled to the selected memory cell. When the programming cycles raise the threshold voltage of the selected memory cell to the sampled level of signal Vvfy, sense amplifier 536 senses during a verify cycle that the memory cell does not conduct and sends a signal to stop further programming cycles. Programming cycles can be stopped for example, by stopping further applications of sampled voltage Vpp to the selected row line, stopping application of voltage Vw to the selected column line, or both. Thus, the programming cycles raise the threshold voltage to the level of sampled voltage Vvfy and then stop. The available write time for a pipeline 510 is N times the period of clock signal SAMPLECLK where N is the number of pipelines 510. Accordingly, the number of pipelines can be selected according to the required write time per pipeline 510 and the desired write frequency. For example, with a write time Tw of 10 μs, 64 pipelines are required to achieve a sampling rate of 6.4 MHz.
In the exemplary recording operation illustrated in FIG. 6, both programming cycles and verify cycles are one clock cycle of signal SAMPLECLK in duration. To achieve this, the frequency of signal SAMPLECLK and the duration of each programming cycle is selected according to the minimum time required for a verify cycle. Additionally, the starts of programming operations are separated by one clock cycle. For example, pipeline 510-1 starts a first programming cycle at a time 620 in response to the pulse 615 in signal SR1 from timing circuit 140. During the programming cycle, the signal VCOL1 applied to the selected column line in array 130-1 is at voltage Vw, and charge pump 582 supplies a current I1 that flows through array 130-1. Current I1 falls during the programming cycle in the characteristic fashion of channel hot electron injection. At time 630, selection circuit 535 in pipeline 510-1 switches signal VCOL1 to read voltage Vr for a verify cycle, and current I1 from charge pump 582 through array 130-1 stops. Also at time 630 when pipeline 510-1 starts the verify cycle, pipeline 510-2 starts a programming cycle. Accordingly, pipelines 510-1 and 510-2 never perform programming at the same time. More generally, only odd numbered pipelines perform programming cycles at the same time as pipeline 510-1, and only even numbered pipelines perform programming cycles at the same time as pipeline 510-2. This effectively cuts the peak current as well as the average current drawn from charge pump 582 in half because at most one half of the pipelines 510 simultaneous performing programming. Additionally, since write operations in pipelines 510 start at different times, most of the programming cycles simultaneously being performed draw much less than the peak programming current for the memory cell. Both factors contribute to significantly reducing the peak total current when compared to a parallel programming operations.
In an alternative embodiment, the duration of a programming cycle can be different from the duration of a verify cycle. Further, the offset between starts of write operations in sequential pipelines can be different from the duration of either a programming cycle or a verify cycle. Staggering the starts of write operations still reduces the peak current when compared to conventional parallel write operations.
For the recording process of FIG. 6, pipelines 510 are effectively partitioned into two banks of pipelines where pipelines in one bank perform programming cycles when pipelines in the other bank perform verify cycles. In other embodiments, pipelines 510 can be partitioned into three or more banks where the pipelines that are in the same bank start programming cycles at the same time, but pipelines in different banks start programming cycles at different times. For example, if a verify cycle is twice the duration of a programming cycle, pipelines 510 can be partitioned into three banks where pipelines in the second bank start programming cycles when programming cycles of pipelines in the first bank end, pipelines in the third bank start programming cycles when programming cycles of pipelines in the second bank end, and pipelines in the first bank start programming cycles when programming cycles of pipelines in the third bank end. Accordingly, only one bank at a time performs programming cycles. This cuts the current from a shared charge pump by two thirds when compared to starting programming operations simultaneously in all of the write pipelines. A similar technique when the programming cycles are twice as long as the verify cycles has two banks at a time performing programming cycles and reduces current by one third. Other partitions of pipelines 510 into banks and staggering of the starts of programming cycles for the banks can be selected according to the ratio of the duration of a programming cycle to the duration of a verify cycle. Additionally, as described above, pipelines within a bank can start programming operations at different times so that at most one pipeline at a time is performing the first programming cycle of a write operation.
Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. In particular, even though much of preceding discussion was aimed at staggering programming operations that program single memory cell in an array, alternative embodiments of this invention include staggering programming operations where each programming operation programs multiple memory cells in the array. Various other adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.
|Cited Patent
|Filing date
|Publication date
|15 Sep 1975
|18 Oct 1977
|Commissariat A L'energie Atomique
|Method and device for the storage of analog signals
|6 Oct 1975
|8 Nov 1977
|Raytheon Company
|Semiconductor memory structures
|15 May 1978
|1 Jan 1980
|Electronic Arrays, Inc.
|Acquisition and storage of analog signals
|11 Oct 1978
|29 Apr 1980
|Sanyo Electric Co., Ltd.
|Preset tuning apparatus using floating gate type field effect device
|21 May 1979
|2 Mar 1982
|Siemens Aktiengesellschaft
|Semiconductor device for the reproduction of acoustic signals
|23 Aug 1983
|2 Dec 1986
|Sanyo Electric Co., Ltd.
|Analog storing and reproducing apparatus utilizing non-volatile memory elements
|18 Jun 1987
|28 Feb 1989
|West Virginia University
|Apparatus and method for long term storage of analog signals
|11 Oct 1988
|25 Jul 1989
|Ford Aerospace & Communications Corporation
|Programmable voltage offset circuit
|13 Jul 1988
|26 Dec 1989
|Information Storage Devices
|High density integrated circuit analog signal recording and playback system
|9 Dec 1988
|19 Jun 1990
|Synaptics, Inc.
|Subthreshold CMOS amplifier with offset adaptation
|12 Oct 1989
|29 Jan 1991
|Information Storage Devices, Inc.
|High density integrated circuit analog signal recording and playback system
|18 May 1990
|2 Jul 1991
|Intel Corporation
|Four quadrant synapse cell employing single column summing line
|27 Jul 1988
|8 Oct 1991
|Intel Corporation
|Semiconductor cell for neural network and the like
|26 Sep 1990
|30 Jun 1992
|Information Storage Devices, Inc.
|Writable distributed non-volatile analog reference system and method for analog signal recording and playback
|22 Jul 1991
|10 Nov 1992
|Sundisk Corporation
|Multi-state EEprom read and write circuits and techniques
|22 Jan 1991
|17 Nov 1992
|Information Storage Devices, Inc.
|Cascading analog record/playback devices
|15 Jan 1991
|1 Dec 1992
|Eliyahou Harari
|Highly compact EPROM and flash EEPROM devices
|11 Apr 1990
|15 Dec 1992
|Sundisk Corporation
|Multi-state EEprom read and write circuits and techniques
|8 Feb 1991
|8 Jun 1993
|Banks Gerald J
|Electrically alterable non-volatile memory with n-bits per memory cell
|2 Jan 1991
|15 Jun 1993
|Information Storage Devices, Inc.
|Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog signal recording and playback
|5 Nov 1992
|24 Aug 1993
|Centre Suisse D'electronique Et De Microtechnique S.A.
|Process of storing analog quantities and device for the implementation thereof
|26 Sep 1990
|31 Aug 1993
|Information Storage Devices
|Integrated circuit system for analog signal recording and playback
|4 Sep 1992
|7 Sep 1993
|Information Storage Devices, Inc.
|Integrated MOSFET resistance and oscillator frequency control and trim methods and apparatus
|28 Jul 1989
|16 Nov 1993
|Mitsubishi Denki Kabushiki Kaisha
|Non-volatile memory device capable of storing multi-state data
|20 Feb 1991
|21 Dec 1993
|Sundisk Corporation
|Method and structure for programming floating gate memory cells
|25 Nov 1992
|15 Mar 1994
|Information Storage Devices
|Single-transistor cell EEPROM array for analog or digital storage
|23 Jun 1993
|16 Aug 1994
|Vlsi Technology, Inc.
|AC drain voltage charging source for PROM devices
|4 Jun 1993
|28 Feb 1995
|Banks; Gerald J.
|Electrically alterable non-voltatile memory with N-bits per memory cell
|8 Nov 1993
|4 Jul 1995
|Elantec, Inc.
|Differential analog memory cell and method for adjusting same
|2 Jun 1994
|4 Jul 1995
|Intel Corporation
|Method and apparatus for sequential programming of a flash EEPROM memory array
|25 May 1995
|21 May 1996
|Kabushiki Kaisha Toshiba
|Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit
|30 Jun 1993
|21 May 1996
|Intel Corporation
|Method of pipelining sequential writes in a flash memory
|10 Sep 1993
|16 Jul 1996
|Intel Corporation
|Method and apparatus for sequential programming of the bits in a word of a flash EEPROM memory array
|25 Sep 1995
|18 Mar 1997
|Sgs-Thomson Microelectronics, S.R.L.
|Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process
|18 Apr 1996
|5 Aug 1997
|Samsung Electronics
|Circuit for applying a stress voltage in sequence to selected memory blocks in a semiconductor device
|16 Jan 1996
|21 Oct 1997
|Invoice Technology
|Pipelined record and playback for analog non-volatile memory
|2 Nov 1994
|2 Dec 1997
|Invoice Technology, Inc.
|High resolution analog storage EPROM and flash EPROM
|22 Apr 1996
|27 Jan 1998
|Advanced Micro Devices, Inc.
|Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
|30 Sep 1996
|14 Jul 1998
|Sgs-Thomson Microelectronics, S.R.L.
|Parallel programming method of memory words and corresponding circuit
|24 Jan 1997
|21 Jul 1998
|Sgs-Thomson Microelectronics S.R.L.
|Method for erasing an electrically programmable and erasable non-volatile memory cell
|27 Mar 1997
|8 Dec 1998
|Sgs-Thomson Microelectronics S.R.L.
|Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method
|20 Dec 1996
|2 Feb 1999
|Advanced Micro Devices Inc
|Bank architecture for a non-volatile memory enabling simultaneous reading and writing
|2 Jun 1997
|18 May 1999
|Agate Semiconductor, Inc.
|Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
|3 Aug 1998
|17 Oct 2000
|Sandisk Corporation
|High data rate write process for non-volatile flash memories
|23 Dec 1986
|7 Jul 1988
|Siemens Ag
|Frame buffer
|17 Mar 1997
|1 Oct 1997
|Invoice Technology, Inc.
|Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell
|"Solutions OEM," A Publication of Intel Corporation, vol. 2, No. 2, (Autumn) Sep., 1994, pp. 1-8.
|Ajika et al., "A 5 Volt Only 16M BIT Flash EEPROM Cell With A Simple Stacked Gate Structure", (Reprinted from IEDM Tech. Dig., 1990, pp. 115-118), LSI R & D Lab., Paper 5.11, pp. 209-212.
|Chen et al., "Subbreakdown Drain Leakage Current in MOSFET", IEEE, 1987, pp. 515-517.
|Dov Frohman-Bentchkowsky, "A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory" (reprinted from IEEE J. Solid-State Circuits, vol. SC-6, #5, 10/71, pp. 301-306) pp. 63-68.
|Haddad et al., "Degradations Due To Hole trapping in Flash Memory Cells", 1989, IEEE Electron Device Lett., vol. 10, No. 3, pp. 117-119.
|Hoe et al., "Cell and Circuit Design for Single-Poly EPROM", 1989, IEEE Journal of Solid-State Circuits, vol. 24, No. 4, pp. 1153-1157.
|Johnson et al., "A 16Kb Electrically Erasable Nonvolatile Memory", IEEE ISSCC, Dig. Tech. pap. 1980, pp. 125-127.
|Kamiya et al, "EPROM Cell With High Gate Injection Efficiency", IEDM Tech. Dig. 1982 (reprint) pp. 741-744.
|Kazerounian et al., "A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell", IEDM Tech. Dig., 1988 (reprint) pp. 202-205.
|Kynett et al., "An In-System Reprogrammable 32Kx8 CMOS Flash Memory", IEEE J. Solid-State Circuits, vol. 23, No. 5, 10/88 (reprint), pp. 170-175.
|Kynett et al., "An In-System Reprogrammable 32K×8 CMOS Flash Memory", IEEE J. Solid-State Circuits, vol. 23, No. 5, 10/88 (reprint), pp. 170-175.
|Lenzinger et al., "Fowler-Nordheim Tunneling into Thermally Grown SiO2", Journal of Applied Physics, vol. 40, No. 1, 01/69, pp. 278-283.
|Naruke et al., "A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate On Its Source Side", IEDM Tech. Dig., 1989 (reprint) pp. 183-186.
|Perlegos et al., "A 64K EPROM Using Scaled MOS Technology", IEEE ISSCC Dig. Tech. Pap., 1980 (reprint) pp. 69-71.
|Press Release: Intel Announces Multilevel Cell Flash Technology, Intel Corporation, 1994, 3 pages.
|Wu et al., "A Novel High-Speed, 5 Volt Programming EPROM Structure With Source-Side Injection", IEDM Tech. Dig., 1986 (reprint) pp. 108-111.
|Citing Patent
|Filing date
|Publication date
|25 Jul 2005
|19 Jun 2007
|Atmel Corporation
|Reduction of programming time in electrically programmable devices
|30 Sep 2005
|29 Jan 2008
|Stmicroelectronics S.R.L.
|Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line
|29 Dec 2006
|21 Oct 2008
|Sandisk Corporation
|Unified voltage generation method with improved power efficiency
|29 Dec 2006
|13 Jan 2009
|Sandisk Corporation
|Unified voltage generation apparatus with improved power efficiency
|30 Mar 2007
|7 Apr 2009
|Sandisk 3D Llc
|Method for load-based voltage generation
|30 Mar 2007
|7 Jul 2009
|Sandisk 3D Llc
|Device with load-based voltage generation
|30 Mar 2007
|25 Aug 2009
|Sandisk 3D Llc
|Load management for memory device
|30 Mar 2007
|25 Aug 2009
|Sandisk 3D Llc
|Method for managing electrical load of an electronic device
|12 Dec 2007
|8 Sep 2009
|Sandisk Corporation
|Low voltage charge pump with regulation
|12 Dec 2007
|8 Sep 2009
|Sandisk Corporation
|Diode connected regulation of charge pumps
|2 Feb 2010
|Sau Ching Wong
|Adaptive operations for nonvolatile memories
|25 Jun 2008
|23 Mar 2010
|Sandisk Corporation
|Techniques of ripple reduction for charge pumps
|14 Sep 2010
|Sandisk Corporation
|Regulation of recovery rates in charge pumps
|28 Jun 2011
|Sandisk Corporation
|Self-adaptive multi-stage charge pump
|21 Jul 2009
|5 Jul 2011
|Sandisk Corporation
|Charge pump with current based regulation
|25 Oct 2011
|Sandisk Technologies Inc.
|Bottom plate regulation of charge pumps
|1 Nov 2011
|Round Rock Research, Llc
|System and memory for sequential multi-plane page memory operations
|16 Oct 2012
|Round Rock Research, Llc
|System and memory for sequential multi-plane page memory operations
|23 Oct 2012
|Sandisk Technologies Inc.
|Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances
|25 Dec 2012
|Sandisk Technologies Inc.
|Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories
|20 Dec 2010
|25 Dec 2012
|Sandisk 3D Llc
|Charge pump system that dynamically selects number of active stages
|22 Sep 2011
|19 Mar 2013
|Sandisk Technologies Inc.
|High voltage charge pump regulation system with fine step adjustment
|24 Sep 2012
|16 Apr 2013
|Sandisk Technologies Inc.
|Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances
|22 Sep 2011
|20 Aug 2013
|Sandisk Technologies Inc.
|Dynamic switching approach to reduce area and power consumption of high voltage charge pumps
|9 Sep 2011
|15 Apr 2014
|Sandisk Technologies Inc.
|Charge pump system dynamically reconfigurable for read and program
|24 Jun 2008
|29 Apr 2014
|Sandisk Technologies Inc.
|Clock generator circuit for a charge pump
|14 Sep 2012
|29 Apr 2014
|Sandisk Technologies Inc.
|Circuits for prevention of reverse leakage in Vth-cancellation charge pumps
|9 Dec 2013
|16 Sep 2014
|Sandisk 3D Llc
|Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple
|22 Apr 2014
|14 Oct 2014
|Sandisk 3D Llc
|Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple
|18 Jun 2013
|17 Mar 2015
|Sandisk Technologies Inc.
|Efficient voltage doubler
|27 Jun 2013
|14 Apr 2015
|Sandisk Technologies Inc.
|Efficient high voltage bias regulation circuit
|24 Jun 2013
|5 May 2015
|Sandisk Technologies Inc.
|Efficiency for charge pumps with low supply voltages
|25 Jun 2013
|7 Jul 2015
|SanDisk Technologies, Inc.
|Capacitive regulation of charge pumps without refresh operation interruption
|30 Sep 2013
|14 Jul 2015
|Sandisk Technologies Inc.
|Amplitude modulation for pass gate to improve charge pump efficiency
|9 Dec 2013
|6 Oct 2015
|Sandisk Technologies Inc.
|Dynamic load matching charge pump for reduced current consumption
|30 Sep 2005
|3 Aug 2006
|Stmicroelectronics S.R.I.
|Memory device and method for operating the same with high rejection of the noise on the high-voltage supply line
|25 Jul 2005
|25 Jan 2007
|Johnny Chan
|Reduction of programming time in electrically programmable devices
|29 Dec 2006
|3 Jul 2008
|Sandisk Corporation
|Unified voltage generation apparatus with improved power efficiency
|30 Mar 2007
|2 Oct 2008
|Tyler Thorp
|Load Management for Memory Device
|30 Mar 2007
|2 Oct 2008
|Tyler Thorp
|Device with Load-Based Voltage Generation
|30 Mar 2007
|2 Oct 2008
|Tyler Thorp
|Method for Managing Electrical Load of an Electronic Device
|30 Mar 2007
|2 Oct 2008
|Tyler Thorp
|Method for Load-Based Voltage Generation
|28 Aug 2007
|5 Mar 2009
|Prajit Nandi
|Bottom Plate Regulation of Charge Pumps
|12 Dec 2007
|18 Jun 2009
|Feng Pan
|Low Voltage Charge Pump with Regulation
|12 Dec 2007
|18 Jun 2009
|Feng Pan
|Diode Connected Regulation of Charge Pumps
|9 Jun 2008
|10 Dec 2009
|Feng Pan
|Charge Pump with Vt Cancellation Through Parallel Structure
|3 Aug 2009
|14 Jan 2010
|Micron Technology, Inc.
|System and memory for sequential multi-plane page memory operations
|17 Dec 2008
|17 Jun 2010
|Man Lung Lui
|Regulation of Recovery Rates in Charge Pumps
|27 Jan 2011
|Feng Pan
|Charge Pump with Current Based Regulation
|7 Jul 2011
|Round Rock Research, Llc
|System and memory for sequential multi-plane page memory operations
|U.S. Classification
|365/185.22, 365/185.23, 365/185.28
|International Classification
|Cooperative Classification
|European Classification
|12 Feb 2007
|Fee payment
Year of fee payment: 4
|16 Oct 2007
|Certificate of correction
|13 Nov 2007
|Certificate of correction
|14 Jan 2011
|Fee payment
Year of fee payment: 8
|4 May 2011
Owner name: SANDISK TECHNOLOGIES INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026224/0526
Effective date: 20110404
|21 Jan 2015
|Fee payment
Year of fee payment: 12


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Blossom Grocery
blossom? AWESOME!
By: jonah carpenter (Aug 5, 2010)
the store staff are kind, helpful, polite, informative, patient, and generous
the products are pure. there is a huge variety available in a humble and warm environment. they offer excellent prices ( i would expect to pay more but they were even cheaper than where i shop in seattle)
i love this store. i will return again. again.
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Welcome to the San Francisco Skiers and Snowboarders
March 19 · 5:00 AMNorthstar Bus Day Trip on March 19, 2016Our corporate Ski and Snowboard Club is having our annual 2016 Northstar Ski Bus Trip on March 19, 2016. We have a few spaces left and we are opening it to 5 lucky... Learn more
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January 19 · 8:15 AMLearn Your Turns! - Telemark Instruction - MT ROSELearn Your Turns! - Telemark Instruction You must be signed up as a member to attend--no 'add-ons/guests'. Read the original posting of LEARN YOUR TURNS! for greater... Learn more
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Original Article
The greatest magic of Harry Potter: Reducing prejudice
Version of Record online: 23 JUL 2014
DOI: 10.1111/jasp.12279
© 2014 Wiley Periodicals, Inc.
Journal of Applied Social Psychology
Volume 45, Issue 2, pages 105–121, February 2015
Additional Information
How to Cite
Vezzali, L., Stathi, S., Giovannini, D., Capozza, D. and Trifiletti, E. (2015), The greatest magic of Harry Potter: Reducing prejudice. Journal of Applied Social Psychology, 45: 105–121. doi: 10.1111/jasp.12279
Publication History
- Issue online: 11 FEB 2015
- Version of Record online: 23 JUL 2014
- Abstract
- Article
- References
- Cited By
Recent research shows that extended contact via story reading is a powerful strategy to improve out-group attitudes. We conducted three studies to test whether extended contact through reading the popular best-selling books of Harry Potter improves attitudes toward stigmatized groups (immigrants, homosexuals, refugees). Results from one experimental intervention with elementary school children and from two cross-sectional studies with high school and university students (in Italy and United Kingdom) supported our main hypothesis. Identification with the main character (i.e., Harry Potter) and disidentification from the negative character (i.e., Voldemort) moderated the effect. Perspective taking emerged as the process allowing attitude improvement. Theoretical and practical implications of the findings are discussed in the context of extended intergroup contact and social cognitive theory.


text:
House M.D. Falls in Preview for Series Finale
Creator David Shore once teased that "House M.D." will have a bittersweet ending and it has been hinted in a preview for the final episode. The titular character is seen falling through a floor and lying next to a blonde woman, possibly Cameron, in the promo set to the song "Live Forever" by Drew Holcomb and the Neighbors.
Described as an emotional series finale, "Everybody Dies" is preceded by an hour-long retrospective at 8/7c on Monday, May 21. After treating a drug addict patient (guest star James Legros), House begins examining his life, his future and his own personal demons.
Beside Olivia Wilde's Thirteen, familiar faces like Jennifer Morrison's Cameron, Amber Tamblyn's Masters, Kal Penn's Kutner and Jesse Spencer's Chase are expected to return to help the show bid farewell to fans. Gushing about how the story ends for his character, Spencer who will next star on NBC's "Chicago Fire" recently said, "It's actually very short, but it's so great."
"It's this tiny little bit [that] opens up a whole new story, and we go 'Oh my God.' And [it leaves you] wondering," the Australian actor went on sharing. "You kind of know where it is going, but you'd like to see where it goes from there. Then the series ends. I like it. I can't wait."
- You Won't Believe How Much Mila Kunis Spent on Her Wedding Ring
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- 'Sesame Street' Fires Three Longtime Cast Members
- Find Out Which Joe Jonas' Famous Exes He Would Like to 'Shag, Marry and Kill'
- Cameron Diaz and Benji Madden's Baby Struggles Reportedly Cause Marriage Problems
- Andrew Garfield Is World War II Hero in First 'Hacksaw Ridge' Trailer
- 'Scream Queens' Adds Jerry O'Connell in Mystery Role
- Troian Bellisario Has Harsh Words for Both Kim Kardashian and Taylor Swift


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Phildel is an artist whose deep appreciation for sound stems from an understanding of silence.
During a childhood in which music was forbidden by her religious stepfather, she came to know silence well. Despite her natural love for music, for 10 years Phildel was left to imagine the sounds she would fill the silence with, if she could. Her sound world is, subsequently, a departure into the world of imagination. Ultimately, the spectral compositions, that make up her debut album, 'The Disappearance Of The Girl', are intimate documents from an unusual and difficult childhood.
Phildel's debut album contains twelve magical songs of resistance and escape, written in the years after she took the difficult decision to break away from the oppressive household. Composing day and night, Phildel created the epic, haunting and innovative music she had dreamt of. Her music is a journey into the landscape of her imagination, at times beautifully enchanting, at others, raw and horrific.
You've already heard Phildel's music, though you may not know it. Her music is a journey into the landscape of her imagination, at times beautifully enchanting, at others, raw and horrific. Her songs have been used on a wealth of TV adverts, from Marks & Spencers to Expedia, including a (particularly poignant) award-winning Persil ad and most recently Apple iPad. They have sound-tracked movies and are cited as an inspiration by Mariah Huehner, author of the True Blood and Angel comic books. They have been used in theatre productions and by celebrity fashion designer Henrietta Ludgate's live shows.
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Venue: St Pancras Old Church
Pancras Road
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UCSD Concilio Retreat 1/24/09
Eva Amezola, Agustín Orozco, Melissa Naranjo
Dr. Rodolfo Acuña
Dr. Rudy Acuña, Dr. Patrick Velásquez
Mechistas listen to Dr. Acuña
Mechistas discussion
Harry Simón, Rudy Acuña, Jorge Mariscal, Patrick Velásquez
Armando Navarro lecture, 2/20/09
Community organizers Ernesto Bustillos and Herman Baca; UCSD student Jorge Narvaez
Dr. Patrick Velásquez interviews Dr. Charles Tatum on UCSD-TV, April 7, 2009
Dr. Tatum and UCSD-TV producer John Menier
Celebration of Dr. Patrick Velásquez (middle) 20 years of service at UC San Diego, April 17
Lumumba-Zapata: 40 Years Later (April 24)
Carlos Blanco Aguinaga
Marta Lomelí
Arturo Madrid, Joe Watson, Keith Lowe, Mary Watson
Lucinda Rubio, Beatrice Pita, Cecilia Ubilla
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Former UCSD students Martha Salinas, Maria Blanco, Marta Lomelí
CLAH collaboration with Centro Cultural de la Raza, April 30
Melissa Naranjo (de rodillas) and Cesar Cruz welcome audience members
UCSD represents! Dr. Patrick Velásquez, Dr. Edwina Welch, Dr. Jorge Mariscal
Jade Power and Centro director Stephanie de la Torre talk with Quino and his daughter
Quino performs
Teatro Izcalli
Revolutionary poet Cesar Cruz
Luis Juarez of Oakland's own headRush Crew
Mario Torero, "Chicano History." Designed by UCSD students, this temporary mural will hang on Peterson Hall during the fall quarter of 2009. The first community based art ever given a prominent place in the heart of the UC San Diego campus!
Senator Edward Kennedy, 1937-2009. ¡PRESENTE!


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Isabelle Vauquelin
Published: Tuesday, March 27, 2007 at 12:18 p.m.
Last Modified: Tuesday, March 27, 2007 at 1:37 p.m.
Isabelle "Billie" Toups Vauquelin, 98, a native of Houma and resident of Schriever, died at 2:28 a.m. Monday, March 26, 2007.
Visitation will be from noon to prayer service Wednesday at Chauvin Funeral Home. Prayer service will be at 2 p.m. Wednesday at the funeral home chapel, with burial in St. Francis de Sales Cemetery No. 2.
She is survived by one son, Wayne Vauquelin and wife, Marie Louise Richard Vauquelin, of Schriever; one daughter, Gwen Vauquelin LaCoste of Schriever; and five grandchildren, David Vauquelin, Christina LaCoste, Sabrina LaCoste, Keith Vauquelin and Jerri Ann Vauquelin.
She was preceded in death by her husband, Jeffery J. Vauquelin Sr.; her parents, Thomas J. Toups and Ida Duplantis Toups; one son, Jerry Vauquelin; and one sister, Delnot Moore.
She was a homemaker, a member of the American Legion and a parishioner of St. Bridget Catholic Church.
Chauvin Funeral Home is in charge of arrangements.
Obituaries and related photos received from funeral homes by 4 p.m. will be published in the next days newspaper. Information received afterward will be published as abbreviated death listings. Death listings will be expanded to full obituaries and posted today at houmatoday.com or dailycomet.com. The full obituary will also be published in the following day's newspaper.
Reader comments posted to this article may be published in our print edition. All rights reserved. This copyrighted material may not be re-published without permission. Links are encouraged.
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About this Library Research Guide
This research guide highlights campus wide resources, including the ACELAB, VLAB and the Accountancy Department, as well as a number of useful web resources available for accounting research.
Use the tabs at the top of the page to navigate between content areas.
If you have any questions about this guide or need further assistance researching your topic please Ask a Librarian.
Frequently Asked Questions.
Selected answers (links open in new window):
- Where can I get an annual report (10-K)?
- I need to write a paper in IFRS and Accounting Information Systems but I don't know where to start.
- How do I access FASB database off campus?
- Do you have study guides for the CPA exam or other exams?
- How do I find a literature review?
- How do I write a literature review?
Popular links
- ACELAB (Jennison 300 and 305)
- Accountancy Department
- Accounting ResourcesListing of library accounting databases. Off campus access is available using your full Bentley e-mail address and network password.
- FASB Accounting Standards CodificationBentley University also has access to FASB authoritative literature through Accounting Research Manager.
- Financial Accounting Standards Board (FASB) Homepage
- Financial Ratios Library Research Guide
- Government Accounting Standards Board (GASB)Bentley University has access to GASB authoritative literature through Accounting Research Manager in the Government section.
- Massachusetts Society of Certified Public Accountants
Get Research Help
Click the above link to open a chat session, visit the Reference Desk, or contact us by phone or e-mail.
Book a Research Consultation
For more in depth research projects, personalized reference consultations are available.
Please note that consultations:
- Take about 30 to 60 minutes.
- Occur during normal Reference Librarian Hours.
- Need at least 48 hours advanced notice.
Click here to sign up for a consultation.
A librarian will contact you to confirm your consultation.


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Pathway Tools Tutorial June 4-8, 2007
SRI's Bioinformatics Research Group will be holding a Pathway Tools
tutorial session on June 4-8, 2007 at SRI International in Menlo
Park, CA.
The goal of the tutorial is to teach scientists how to use the Pathway
Tools software to create a Pathway/Genome Database (PGDB) for an
organism of interest, how to interactively update and curate a PGDB,
and how to publish a PGDB on the web, and how to use the Pathway
Tools omics viewers.
Pathway Tools includes a unique combination of bioinformatics
algorithms including a predictor of metabolic pathways, an operon
predictor, and an algorithm for predicting which genes in a genome
code for missing enzymes in predicted metabolic pathways ("pathway
Each day's tutorial will last from 9:30am-5:00pm. Each day will
combine lectures with lab sessions in which students apply the
software to a sample genome. No programming experience is required
for days 1-4, but a basic knowledge of Unix is helpful, as is
knowledge of a Unix text editor such as vi or emacs.
Day 5 requires programming experience in Perl, Java, or Lisp. Day 5
is optional.
Three example PGDBs are:
o EcoCyc http://EcoCyc.org/
o Yeast pathway database: http://pathway.yeastgenome.org/biocyc/
o Arabidopsis pathway database: http://www.arabidopsis.org/biocyc/index.jsp
Day 1 (June 4)
Introduction to Pathway Tools
Overview of Pathway/Genome Navigator
Pathway Tools Omics Viewers: Cellular Overview, Regulatory Overview, Genome Overview
Querying PGDBs with BioVelo
Day 2
Pathway prediction using PathoLogic
Matching enzyme names to reactions
Pathway hole filler
Day 3
Operon predictor
Pathway Tools schema
Administering Pathway Tools
Pathway/Genome Database Registry
Day 4
Transport Inference Parser
Editing Pathway/Genome Databases
Day 5 (optional)
The Pathway Tools APIs -- Programmatic querying and updating of PGDBs
using the Perl, Java, and Lisp languages.
If you wish, you may bring with you to the tutorial the annotated
genome of an organism for which you wish to build a PGDB, in which
case you will most likely leave the tutorial with a draft version of
the database.
Please reply to Wilma Lenz (firstname.lastname@example.com) to reserve a space at the
tutorial; space is limited. There will be a tutorial fee of $75 to
cover food and other expenses. Please indicate if you will attend Day 5.
For more information about the tutorial please see:
Peter Karp
Bioinformatics Research Group
SRI International
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All Workout
Workout in style with Sweaty Betty's range of workout wear for women. From gym accessories to dance leggings, trust your sportswear to help you move with confidence. Our carefully designed workout clothes and fitness wear are great for hitting the gym, but that's not all – they're perfect for grabbing a quick smoothie afterwards too.
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text:
Photo 291 of 331 Show all
13 September 2010
Photo by Saeed Adyani - © 2010 Fish Head Productions, LLC. All Rights Reserved.
Titles: Let Me In
Names: Chloë Grace Moretz
Characters: Abby
Let Me In (85)
Find showtimes, watch trailers, browse photos, track your Watchlist and rate your favorite movies and TV shows on your phone or tablet!IMDb Mobile site
|Amazon Affiliates


text:
My name is Sid, I live in the northern most part of New York State. I love photography and am glad for the opportunity to be able to share some of my photos with such a talented community. So many of the photos on this site are outstanding and inspiring. I love experimenting, looking for the unusual,which makes for more deleted photos than keepers, but it's all fun!
WunderPhotos Upload
Male Hooded Merganser
Uploaded by: 81Gibson
Monday April 7, 2014
Gouverneur, NY (Current Weather Conditions)
Caption:No caption given.
Manufacturer: Canon
Model: Canon PowerShot SX20 IS
Orientation: top - left
x-Resolution: 180.00
y-Resolution: 180.00
Resolution Unit: Inch
YCbCr Positioning: centered
Compression: JPEG compression
Exposure Time: 1/320 sec.
FNumber: f/5.7
ISO Speed Ratings: 100
Exif Version: Exif Version 2.2
Components Configuration: Y Cb Cr -
Shutter speed: 8.31 EV (APEX: 17, 1/317 sec.)
Aperture: 5.03 EV (f/5.7)
Exposure Bias: 0.00 EV
Flash: Flash did not fire, compulsory flash mode.
Focal Length: 100.0 mm
User Comment:
FlashPixVersion: FlashPix Version 1.0
Color Space: sRGB
PixelXDimension: 1773
PixelYDimension: 1643
Focal Plane x-Resolution: 16393.44
Focal Plane y-Resolution: 16393.44
Focal Plane Resolution Unit: Inch
File Source: DSC
Custom Rendered: Custom process
Exposure Mode: Auto exposure
White Balance: Auto white balance
Digital Zoom Ratio: 1.00
Scene Capture Type: Standard
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RelatedImageWidth: 1773
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Someone recently asked me whether the Rambam had any students. In addition to the Rambam's son and the student for whom he wrote the Moreh Nevuchim, I could think of only one other student. (רבינו פרחיה who wrote a commentary on שבת is a talmid, I think, but I would appreciate information about him too.) Does anyone have any information about other students and whether the Rambam had a yeshiva, etc.?
Sign up
- Anybody can ask a question
- Anybody can answer
- The best answers are voted up and rise to the top
Found a brief discussion here:
Also found this article which discusses the importance of recently published writings of the Rambam's students for understanding the Rambam.
There is a Sefer - Maamar Rabbi Yosef Ben Yehuda Talmid HaRambam.


text:
Chocolate Chip Sour Cream Cake
|1⁄2 Cup (8 tbs), softened
|1 Cup (16 tbs)
|All purpose flour
|2 Cup (32 tbs)
|Baking powder
|1 Teaspoon
|Baking soda
|1 Teaspoon
|Commercial sour cream
|8 Ounce (1 Carton)
|Vanilla extract
|1 Teaspoon
|Semi-sweet chocolate morsels
|6 Ounce (1 Package)
|Chopped pecans
|1 Cup (16 tbs)
|Firmly packed brown sugar
|1⁄4 Cup (4 tbs)
Cream butter; gradually add 1 cup sugar, beating at medium speed of an electric mixer until fight and fluffy.
Add eggs, one at a time, beating well.
Combine flour, baking powder, and soda; add one-third of dry ingredients to creamed mixture, stirring with a spoon until blended.
Add half of sour cream, stirring until blended.
Repeat procedure, ending with flour mixture.
Stir in vanilla.
Combine chocolate morsels, pecans, and brown sugar; set aside.
Spoon half of batter into a well-greased and floured 10-inch tube pan.
Sprinkle with half of chocolate morsel mixture.
Spoon remaining batter into pan, and top with remaining chocolate morsel mixture.
Bake at 350° for 50 minutes or until a wooden pick inserted in center comes out clean.
Remove from pan, and cool completely.
Rate It
Nutrition Rank
Nutrition Facts
Serving size: Complete recipe
Calories 4931 Calories from Fat 2412
% Daily Value*
Total Fat 278 g428.4%
Saturated Fat 124.4 g622.1%
Trans Fat 0 g
Cholesterol 782.8 mg260.9%
Sodium 2117.8 mg88.2%
Total Carbohydrates 581 g193.6%
Dietary Fiber 17.7 g70.8%
Sugars 365.3 g
Protein 55 g109.2%
Vitamin A 93.4% Vitamin C 5.5%
Calcium 86.4% Iron 98.4%
*Based on a 2000 Calorie diet


text:
by Lauren C. Williams Mar 21, 2016
Only 5 percent of Cubans have household internet access. That's about to change.
by Beenish Ahmed Mar 21, 2016 Updated: Mar 21, 2016
"[Obama] needs to know that we are here being repressed simply for exercising our right to express ourselves and manifest in a non-violent way," said Berta Soler of Ladies in White, a Cuban rights' group.
by Alice Ollstein Mar 13, 2016
Millions of immigrants could become citizens and decide this year's election.
by Samantha Page Dec 24, 2015
Allowing MLB to deal directly with Cuba could cut down on human trafficking.
by Beenish Ahmed Nov 19, 2015
Fears that Jewish refugees would work as spies for the Nazis was part of the reason why they were denied entry into the United States.
by Alice Ollstein Nov 5, 2015
"It's a false narrative that you have to know everything," he told reporters in Miami when asked for his stance on U.S.-Cuba relations.
by Justin Salhani Aug 14, 2015
Calling for the return of Guantanamo and embargo reparations is a position that is well-received among Cubans.
by Alice Ollstein Aug 14, 2015
"In the eyes of Barack Obama and Hillary Clinton, the Cuban people are suffering because not enough American tourists visit the country."
by Justin Salhani Jul 28, 2015
This year alone there have been at least 15 defections by Cubans representing their countries in international competitions.
by Alice Ollstein Jul 20, 2015
The embassies have opened, but the travel ban and the embargo remain.


text:
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Don't Steal, Practice Asteya
The Yamas and Niyamas are the 10 ethical guidelines behind the practice of yoga. They encompass non-violence, truth, non-stealing, non-excess, non-possessiveness, purity, contentment, self-discipline, self-study, and surrender.
Lately, I've been thinking about Asteya, the yama of non-stealing. In day-to-day life, we think of this as not stealing material possessions from stores or other people, however, there are many ways to steal and they don't all encompass material goods.
Yoga Research: Five Proven Facts that Make Yoga Awesome
How many times have you tried to tell your friends about the energy body but you just can't seem to convince it's real?
How many times have said friends stopped talking to you altogether, or at the very least mentally categorized you as the cuckoo?
Yoga teachers are famous for saying funny things that don't make sense to non-practitioners. It's hard to put into words the things we feel sometimes, especially words that everyone can understand.
But those days might soon come to pass. Stephanie Shorter, PhD, presented a lecture at the Dallas Yoga Conference on yoga research, summarizing past and current scientific research in words that yoga teachers and students can understand and most importantly, connecting all our crazy new age rhetoric into hard science.
Here are five enlightening facts to help you understand what is happening in the body on a physiological level, plus practical applications to integrate into your daily practice (good news: you probably do these things already!)
March: Just in Time
The March film selections from Spiritual Cinema Circle focus on how we measure the value of our time.
Chinese Take-Away (Un Cuento Chino) is the feature film for subscribers in the U.S. and Canada. Directed by Ricardo Darin, this film from Argentina is a powerful story about two men from completely different worlds who, in the most unlikely ways, help each other heal their broken hearts and spirits. Film critic Roger Ebert awarded it his top rating.
Awaken, this month's feature film for international subscribers, is a mind-bending and heart-opening time-travel love story where two lovers meet and change each other's lives in a completely unique environment.
The Camera is a haunting, wordless short film that reminds us of the power of love and the magic of memories.
In Tick Tock Time Emporium, a girl who desperately wants more time with her mother enters a strange shop where time is actually for sale.
Pioneer focuses on a mysterious, haunting bedtime story that a father tells his son. This powerful short film was voted the Best Narrative Short at the South by Southwest Film Festival.
5 "No Excuses" Training Tips
Excuses are easy to make. They're also contagious and can paralyze your progress, not only physically, but in other aspects of your life. I have had many clients get a good momentum going with their fitness and then, because of a bump in the road (a hectic schedule, business trip, vacation or illness), they drop off and then have trouble getting back into their routine. If you aren't careful, all of your hard-won progress can slip away in a matter of days.
Want to Eat Healthier? Plan Ahead!
With today's hectic schedules, it seems like there is just no time for anything besides the day-to-day hustle. This can make taking time to make healthy choices seem like a luxury.
What's your typical day like? For many people, it's up in the morning and off to work with no time for breakfast, or up in the morning, drive through the closest fast food joint and haul butt to work. And that's just breakfast. The rest of the day will likely include snacking at your desk and lunch at some place that, while close to work, may or may not have healthy options.
Change Your Numbers!
Are you the type of person who has to see numbers change in order to feel like you are making progress on your fitness path?
Do any of these ring a bell?
- Getting up and weighing yourself every morning and rejoicing or grieving over every ounce lost or gained.
Calling in Balance: Make Time to Self Nurture
How to Use Your To-Do's to Fit in Some Exercise
I get this question a lot: "How can I fit exercise into my super-busy life?"
We all have different life experiences, yet we all share this one need: to move! The body needs it, the mind, our hearts, our organs, our moods … all of it depends on the general wellness of the body. But some of you are home with three kids and a dog and chores all day long, or at work behind a desk, with no chance to go to a gym during the week.