text:
|Publication number
|Publication type
|Publication date
|Mar 19, 1974
|Filing date
|Dec 15, 1972
|Priority date
|Dec 15, 1972
|Publication number
|Huebner T
|Original Assignee
|Johnson Service Co
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (8), Referenced by (59), Classifications (9), Legal Events (1)
|External Links: USPTO, USPTO Assignment, Espacenet
United States Patent [1 1 Huebner 1 DIGITAL SIGNAL TRANSMISSION APPARATUS [751 lnventor: Thomas W. Huebner, New Berlin,
{73} Assignee: Johnson Service Company,
Milwaukee, Wis.
22 Filed: Dec. 15, 1972 211 Appl. No.: 315,464
152] US. Cl 340/1725, 178/68. 307/269. 307/282 [51] Int. Cl. H03k 5/00 [58] Field of Search 307/208. 261, 268, 269. 307/282. 289 106'. 328/34. 63. 72. 74; 340/1725 [56] References Cited UNITED STATES PATENTS 3.104.331 9/1963 Zinke 328/34 3.153.200 10/1964 Wahrman et a1. 328/34 3.161.830 12/1964 Frysinger..... 328/34 3.183.372 5/1965 Chin 328/74 3.497.724 2/1970 Harper l 307/261 3.538.342 11/1970 Jensen et a1. l 307/106 3.557.308 1/1971 Alexander l 328/72 3.187.260 6/1965 Dove 178/68 Primary E.raminerPaul J. Henon Assistant Examiner-Michael Sachs Attorney. Agent. or FirmAndrus, Sceales. Starke &
Sawall Mar. 19, 1974 [57] ABSTRACT A bi-polar data signal of a nominal period is transmitted over a loop cable to a plurality of series connected remote stations. each of which includes means to process the bit. Each bit signal is divided into a plurality of three successive intervals. During each of the first two periods. the one polarity pulse signal occurs on one line followed by an opposite polarity pulse on the line. A negative and positive signal detector generates a pair of corresponding pulses. The first pulse fires a timing means to generate a short pre-clock pulse employed as a timing pulse in the processing of the data bit signal. The trailing edge of the pre-clock pulse fires clock timing means having a longer timing period. The output of the clock timing means is connected to the pre-clock means and to the receiving means to inhibit further signal formation. A clock pulse is derived even if one of the data polarity pulse is lost to continue proper transmission of the successive bits of a message frame even if the data bit is transmitted with erroneous information. The processing circuitry further includes a parity check on the received data to indicate such a fault.
17 Claims, 2 Drawing Figures DIGITAL SIGNAL TRANSMISSION APPARATUS BACKGROUND OF THE INVENTION This invention relates to a digital data clock signal generating apparatus and in particular to means for receiving of digital information in a communication system.
Digital logic signals are advantageously employed in the transmission of information or data from one point to a remote point in connection with automated control and communication systems and the like. Generally information can be reliably transmitted over relatively long transmission lines of a twisted line pair or coaxial cable by selective transmission of digital logic level voltage signal or the like. The proper detection of the successive digital signals produces a coded information transfer. For example, a loop communication is disclosed in the copending application of Buchanan et al., entitled DATA COMMUNICATION SYSTEM EM- PLOYING A SERIES LOOP" bearing Ser. No. 315,567 which was filed on the same day as this application and which is assigned to the same assignee. The information may be advantageously transmitted as balanced bi-polar differential signals. In such a system, one line of the pair is inductively driven between two voltage levels from a single power supply. Each data bit is conveniently transmitted as a bi-polar or alternating pulse signal. A logic 1 is defined by the bi-polar pulse signal including an initial positive pulse followed by a negative pulse on the transmission line. Similarly, a logic 0, by convention, is defined when the signal first includes a negative pulse followed by a positive pulse. The data transmitter, particularly for high speed data transmission, can conveniently and practically consist of a pair of identical bit transmitting transistor units, each of which includes a transistor and a differentiating network to pulse a dual-winding, series connected phase coupling transformer. A single output winding is provided and coupled through a relatively low impedance transmission line to a receiver at the receiving stationv The receiver similarly includes a coupling transformer with an output winding connected to positive and negative pulse detectors or comparators to generate corresponding logic data signals. However, only the first pulse may be used as the operative data pulse.
Although such systems are employed, they require relatively expensive and special purpose integrated circuitry as line drivers to provide the necessary power level at the transmitting end and similarly receivers with special synchronizing means at the receiving end. In such digital systems it is, of course, important to continuously monitor the transmission of the digital information to ensure error free detection with necessary correction where required. Such systems have generally been limited to transmission of data information at a rate of 50,000 bits per second to minimize the difiiculty of monitoring the data transmission, although the digital bits can be readily generated and transmitted at rates of the order of 500,000 to 10,000,000 bits per second, the system is extremely dependent on clock pulses synchronized at the transmitting and receiving ends of the transmission system. Some transmission systems include means to detect an error in a message with a resulting retransmission of total data. The retransmission, however, results in a delay of the transmission of subsequent information until the first has been checked with loss in overall operating system speed. Other detection systems include continuously scanning similar samples to permit the making of a weighted decision regarding the validity of the information based on a number of similar samples which are checked or analyzed to ensure the validity of transmission.
Where the transmission rate is in excess of 50,000 bits per second, the monitoring systems are extremely dependent upon proper clock synchronization at the transmitting and receiving end of the systems. Although the prior art has suggested use of digital information with internal clock data, the systems are generally difficult to operatively control and, of course, the loss of a clock pulse can result in the loss of data. Further, the system requires relatively expensive circuitry to provide completely satisfactory operation.
The digital transmission art includes a need for a reliable, self-generating clock means for digital data and particularly such a means which may also generate related timing and control pulses to ensure reliable and continuous transmission of data.
SUMMARY OF THE PRESENT INVENTION The present invention is therefore particularly directed to a bi-polar transmitted data signal with a special recovery means for ensuring reliable recovery of the digital data information and particularly the selfgenerating of clock and related signals to properly analyze and validate each data bit and properly retransmit the data.
Generally, in accordance with the present invention, each bi-polar pulse signal has a corresponding nominal time period or interval and defines a message logic bit. Each bit is divided into a plurality of three successive intervals. During each of the first two periods, the one polarity pulse signal occurs on one line of the transmission cable, followed by an opposite polarity pulse. For example, in a practical system the pulse signals may include a total time of two microseconds per data bit with the initial polarity pulse being generated with fivetenths of a microsecond interval followed by a similar opposite polarity pulse, followed by a quiet period of approximately one-half the bit period. The information is transmitted over the transmission lines as succeeding adjacent bits as a series of bi-polar signals separated by short quiet periods between the second polarity pulse and the generation of the subsequent initial pulse. Each pulse is detected and a relatively square wave signal generated by a suitable logic threshold detector. The leading edge of the pulse is employed to fire a timing pulse generating means such as a one-shot retriggerable unit to generate a timing pulse defined as a pre-clock pulse of approximately one-half period of the first interval. The trailing edge of the preclock pulse, in turn, fires a longer timed pulse generating means such as a retriggerable one-shot unit having a timing period equal to approximately one-half the total time of the bit period. The output of this second timing circuit provides the clock signal associated with the data. The output of the clock pulse means is in a particularly novel and optimum construction also connected to the preclock pulse generating means and to the receiver to positively inhibit further signal formation by these latter two elements. Thus, it positively prevents the receipt of the second pulse of the bi-polar signal, thereby eliminating the necessity of waiting for the transmission of such pulse. It also inhibits the recognition of signals on the received lines during which period erroneous noise or other erroneous information may appear on the line and tend to cause malfunctioning.
In the present invention, the clock pulses derived from the polarity pulse continue to operate the system for proper transmission of the successive bits of a message frame as long as at least one pulse per time period is generated. Thus, both of the bi-polar portions of the pulse are effective to provide a pulse source for generating of the necessary clock signal as well as the other related signals, to ensure the continued transfer of successive bits in each frame.
If the second pulse of the bi-polar signal is lost for any reason such as noise, there is no affect on the system as this pulse is not employed in the normal transmission, based on the first pulse convention. If the first pulse of the bi-polar signal, however, is lost, the received data may be in error. However, the processing circuitry as shown in the previously identified Buchanan et al application or system may include a parity check on the received data which would indicate such failure.
Thus, the data transmission system will be in operation as long as either pulse is generated, though the data as such may be erroneous.
The present invention has been found to provide a simple, reliable and relatively inexpensive means and apparatus for high speed digital signal transmission and readily accommodates transmission of digital information in the order of 500,000 bits per second, with each bit automatically providing interlocking control and with the necessary timing, data validating and interlocking signals to ensure the integrity of processing of the total message frames.
BRIEF DESCRIPTION OF THE DRAWING The drawing furnished herewith illustrates a preferred construction of the present invention in which the above advantages and features are clearly disclosed as well as others which will be readily understood from the subsequent description of such illustrated embodiment.
In the drawing:
FIG. 1 is a schematic illustration of a loop communication system employing digital bi-polar transmission signals, with a pulse detection and conversion system constructed in accordance with the present invention; and
FIGv 2 is a typical receiver timing illustration showing the received signals and the interrelated pulse signals generated under varying conditions of proper and erroneous data received.
DESCRIPTION OF THE ILLUSTRATED EMBODIMENT Referring to the drawing, the present invention is shown in connection with a data communication loop system employing a loop controller 1 serially coupled by a loop communication cable 2 to a plurality of similarly constructed remote stations 3, generally as more fully disclosed in the previously referred to Buchanan et al. application. Each of the remote stations 3 generally includes a message frame handling means 4 coupled via a common bus cable 5 which is connected to a cable 2 to receive and retransmit the message frames. The frame handling means 4 selectively transmits information to the several point modules 6 from a message frame 7. Thus, the central controller 1 generates message frames 7, each of which includes a plurality of digital logic bits 8. The frames 7 are circulated in serial fashion throughout the loop to establish communication with the remote stations 3 in a selected manner.
Each of the point modules 6 include similar logic means for receiving the information from the message frame 7 and processing the information to provide for the selected operation of operating hardware or other load means such a set point adjustment, checking the status of the hardware and/or receiving information from the hardware. For example, the system may be adapted to read an analog output of a temperature sensor. Alternatively, the point modules 6 may control the start-stop motor controls with sensing of the status of the motor operation.
The message frames 7 are divided into a plurality of bit subgroups to provide for selective addressing of the remote station 3, a point modules 6 as well as the particular load means and function as more fully disclosed in the Buchanan et al application.
The present invention is particulary directed to the apparatus for generating and transmitting of a binary logic signal for each bit with one transmitter means and one receiver means shown in detail in the drawing.
Each bit 8 of a message frame 7 is a bi-polar signal which, of course, originates at the loop controller 1 and particularly a bi-polar signal generator 9 connected to cable 2, which is a suitable twisted pair of lines or a coaxial line. Cable 2 is shown simply including a pair of transmission wires or lines 10. Each binary bit 8 is thus transmitted as a bi-polar or alternating pulse having both a positive half-cycle pulse and a negative halfcycle pulse, with the binary logic I and logic Orelated to correspondingly have the initial pulse or positive polarity or negative polarity. The frame handling means 4 of the remote station 3 includes a data receiver 11 to receive the bi-polar bit signal, properly process the bit for action by a point module 6 if required, and retransmit it via a data transmitter 12 in either modified or unmodified form. The present invention is particularly directed to the initial processing of the signal by a timing an clock signal forming means 13 connected to the receiver 11. If the data frame 7 is to be employed by the corresponding remote station 3, each bit 8 is coupled to the appropriate point module 6, properly modified, and retransmitted by transmitter 12 through the following loop cable 2 to a receiver at the next station 3 and finally to a receiver 8a at the loop controller 1 where the modified message frame 7 is interpreted and necessary subsequent action taken, if any.
Although the data transmitters 9 and receivers 11 can be of any suitable construction a particularly satisfactory unit is shown in FIG. 1.
More particularly, the transmitter 9 includes a pair of logic transistors, identified as a logic 0" transistor 14 and a logic 1 transistor 15. The transistors 14 and 15 are normally cut off to create a zero voltage level or quiet period on cable 2. A logic input signal is applied to the base of the appropriate transistor 14 15 in accordance with the desired logic signal to be generated.
Each of the transistors 14-15 is similarly connected to a positive power supply 16 through a related load resistor 17 and 18 to selectively connect a common ground 19 to end of one resistor 17-18. A similar differentiating network 20 and 21 each of which similarly includes a capacitor 22 in series with a damping resistor 23, one connected to the differentiating networks 20 and 21. A pulse transformer 24 includes a pair of windings 25 and 26 connected with a common center return 27, between the differentiating networks 20-21. The respective capacitors 22 through charge through the associated load resistors 17 and 18. When a transistor 14 or 15 is biased on, the corresponding capacitor discharges through the associated primary winding 25 or 26. The pulse transformer windings 25 and 26 with the two transistors selectively establish an opposite flux flow through a related winding 27. The windings 25 27 are appropriately wound on a common core and thus generate oppositely directed flux which in turn generate a related signal in the common transmitting winding 27 which is connected directly to the transmission lines 10. Thus, when transistor 14 is biased on, a related polarity signal in the secondary winding 27, as shown by the illustrated polarity dots 28 is created. The signal is an alternating or bi-polar signal as shown typically at 29 in FIG. 2, with the dot illustration corresponding to the first half cycle or pulse in the signal.
When the opposite transistor 15 is triggered, the polarity of winding 26 is similarly shown by dot 30 but winding 26 is wound to reverse the relative polarity in winding 27 with generation of a bi-polar or alternating pulse signal of opposite phase. For example, as shown diagrammatically at 31 in FIG. 2.
The bi-polar pulse signals 29 and 31 are transmitted by the transmission lines which are preferably of a low impedance characteristic and generally of the order of 50 ohms. Thus, each logic bit includes the initial bi-polar pulse signal generated by the switching of the logic transistors 14 or on and off followed by a dwell quiet time to define a complete period for each bit. In a practical system employing a 500,000 bit per second system, each bit may include a total period of 2 microseconds with the initial polarity pulse of each signal assuming an initial period of essentially 0.5 microseconds and with the opposite polarity employing a similar period followed by a zero or quiet period of approximately one microsecond. The binary bit signal may be transmitted over the transmission lines and if a total 2,000 foot line 10 is employed in approximately one and one-half microseconds. Thus the time between the initial generation of each bit 8 and the receipt of the bit at an adjacent station is approximately 3- lmicroseconds for 2,000 feet of cable. The circuitry starts the clock within 200 us after the receipt of the leading edge of the pulse. Assuming there are no cable delays, the data will be ready for processing 200 ns after it was transmitted.
The bi-polar signals 29 and 31 are received and transmitted by a coupling transformer 32 having a single primary winding 33 connected directly to the signal lines 10 and having an isolated secondary winding 34 with a parallel damping resistor 35. The transformer 32 may correspond to transformer 24 with only one of the two similarly constructed windings employed as the secondary 34. The low impedance characteristic of the transmission line system in combination with the transformer coupling permits transmission with direct current signal isolation and a high degree of noise immunity even though the transmission is unbalanced. Thus, this system has been applied to reliably transmit order of 500,000 bits per second, with distances between the transmitter and receiver of the order of 2,000 feet. Further distances can be created, of course, by introducing of additional combinations of transmitter 9 and receiving transforming pairs at a given remote point, either at a remote station 3 or at a special coupling station, not shown. The data receiver 11 further converts each corresponding bi-polar signal into a corresponding logic signal by response to the first polarity pulse.
The transformer secondary 34 is connected to a pair of polarity detectors 36 and 37, which have a selected positive and negative threshold voltage level. The detectors 36 and 37 are diagrammatically shown as operational amplifiers having inverting and non-inverting inputs connected appropriately to a positive voltage reference which is compared to each pulse of the alternating signals 29 and 31. Thus each alternating pulse will activate both of the detectors 36 and 37. The positive or logic 1 signal 29 received results in a generation of a square wave pulse 40 shown in FIGv 2 at the positive voltage detector line 38 and then a similar square wave pulse, not shown, at the negative voltage detector line 39. The logic 0 signal 31 will first trigger the negative voltage detector 37 to generate a pulse 41 as shown in FIG. 2, and then and immediately thereafter activate the opposite polarity detector 36 to generate a corresponding positive pulse signal, not shown, at the opposite voltage output output line 38.
In accordance with the present invention, the received signals 29 and 31 are processed through a novel conversion circuit 13 to produce the necessary pulse processing signal directly from each bit to analyze the same bit and retransmit it, either modified or unmodified. In the illustrated embodiment each received bit 8 is processed to generate a pre-clock pulse at a preclock signal line 42 for proper timing within frame handling means 4 and other related processing hardward, a clock pulse at a clock line 43 to ensure continued transmission of the successive data bit at a serial data transmission line 44, and finally a clear signal at a clear line 45 to reset the frame handling means 4 and other related reprocessing hardware for receipt of a subsequent message frame 7. Thus, the time related and indepen' dent signals on the two data receiver lines 38 and 39 are interconnected to yield the necessary pulsing signals directly. These signals at lines 42 45 can then be assembled or employed with any of the relatively wellknown techniques to assemble the serial data material at line 44 for selectively transmitting and grouping for processing and modification within a remote station 3 or for directly retransmitting of the bit unmodified to the next remote station 3, without the necessity of auxiliary sources of clocking and timing devices. Each bit 8 is immediately transmitted, modified or unmodified.
More particularly, in the illustrated embodiment of the invention, the polarity related lines 38 and 39 are connected to a data register 46, shown as a conventional integrated Ser. No. 7,474 flip-flop circuit. The register 46 includes a first set terminal 47 connected to the positive polarity receiver lines 38 and responsive to a positive polarity signal to set line 44 at a positive logic 1. The negative polarity line 39 is connected to the clear terminal 48 of register 46 and will establish a corresponding low level or logic 0 at the serial data line 44. This infonnation is properly processed in response to the clock and timing signals as well as parity checking in any suitable or known parity check unit 49 forming a part of the handling means 4.
The signals at lines 42, 43 and 45 are generated as follows. Both of the negative and positive polarity lines 38 and 39 are connected as one of the inputs to a logic OR circuit or gate 50 having a pair of inverting inputs 51 and 52 such that a logic at either input generates a logic 1 output. The output of the logic gate 50 is connected to a pre-clock pulse generator 53, such as a retriggerable one-shot Ser. No. 74123 integrated circuit unit. The leading edge of either a pulse on the polarity lines 38 and 39 will simultaneously set the flip-flop circuit 46 and activate the one-shot unit 53. The latter is selected to have a relative short time period and particularly a period which is significantly less than that of the activating pulse period. For example, where the polarity pulse is ofa 500 nanosecond period, the one-shot unit 53 may generate a pre-clock pulse of approximately 200 nonoseconds as shown at 54 in FIG. 2. This produces a corresponding prepulse signal at the preclock line 42 which is connected to positive output 55 of the circuit 53, for initiating the timing of the data processing period.
The trailing edge of the pre-clock pulse 54-( FIG. 2) is employed to further generate the desired block pulse and interlocking signals, as follows.
The not-output 56 of the one-shot unit 53 is connected as an input to a second pulse generator 57, also shown as a one-shot integrated circuit, the positive output of which is connected to the clock line 43. Thus, the clock line 43 will rise to a logic 1 level at the negative edge of the pre-clock pulse, as shown in FIG. 2, to define the clock pulse 58.
The clock output pulse 58 is also fed by an inhibit line 59 to the second or inhibit input of the pre-clock pulse generator 53 and positively holds circuit off. This ensures that a single pre-clock timing pulse 54 is generated for each clock pulse 58 generated.
Further, the not-output of the clock unit 57 is connected by an inhibit signal line 60 to the data receiver 1 l. The not output pulse of clock 57 prevents reception of the second half-cycle of the logic I bi-polar signal 29 (FIG. 2). Thus, only the pulse 40 is generated and transmitted by the receiving circuitry. Consequently, the circuitry does not have to delay its functioning during the time that such negative pulse would otherwise be received and in particular avoids the necessity of a delay of 500 to 700 nanoseconds during which the op posite polarity pulse exists. The inhibiting of the receiver 11 also positively prevents the transmission of any other extraneous information or noise which may exist on the transmission lines 10. If such extraneous information does exist, data receiving means simply ignores the signals.
In FIG. 2, the transmission characteristic is illustrated for six successive bits, each of a two microsecond duration as shown by the time scale and illustrating the various conditions including errors which may be encountered by a remote station 3 and the related pulse signals generated thereby.
The error conditions are appropriately identified along the corresponding logic time column for the successive bits which were transmitted and decoded at the serial data line 44 for retransmission. Thus, the first time column includes a proper transmission condition for the logic 1 signal 29 which is properly decoded and retransmitted as a logic 1 signal as shown by the alleged data line 61 which is at a relatively high voltage level for the 2 microsecond bit interval. This signal will be properly processed by the remote station 3 and retransmitted as a logic l or modified and retransmitted as a logic 0 in accordance with the encoding of the message frame 7. The first column thus illustrates the several pulse signals as discussed in the description of the circuit of FIG. 1.
The second time column illustrates a proper condition transmission for the logic 0 signal 31, with the decoding and retransmission at the serial data line 42 as a proper logic 0 signal, shown by the decrease in the signal level of data line 64.
Under these conditions, the bi-polar signal 31 received first generates the negative half-cycle which in turn generates the first pulse 41 at the negative polarity signal line 39 of the receiver detector 37 to generate a corresponding pre-clock pulse 62 at the pre-clock line 42 as a result of the actuation of the OR gate 50. The related trailing edge of the pre-clock pulse 62 activates the clock pulse generator 57 to generate a clock pulse 63. This simultaneously activates the inhibit signal lines 59 and 60 to prevent reception of further signals including the positive half-cycle of pulse 31 and to inhibit the pre-clock unit 53. The serial data line 44 has been converted to a logic 0 approximately in synchronism with the generation of the leading edge of the pre-clock pulse 62 by the signal applied to terminal 48 of unit 46, and thus the serial data is properly transmitted and decoded as a logic 0 as at 64.
In the third column, an error condition is shown associated with a transmitted logic 1 bi-polar signal 65 and in particular where the positive pulse portion has been lost. Thus, the logic 1 signal does not activate the positive polarity detector 36 as it should to generate a pulse signal at line 38 which is shown in FIG. 2 by the continuing zero output. Each half of each bi-polar pulse is operative unless inhibited, and the negative pulse of the logic 1 signal 65 is therefore detected by the negative polarity detector 37 to establish the related pulse signal 66. The second pulse of the bi-polar signal 65 therefore creates a pre-clock pulse 67 and an associated clock pulse 68 in the same manner as previously described but delayed by the period of a bipolar pulse.
Consequently, as a result of the lost pulse and the loss of the inhibiting signal, the second polarity signal is transmitted and also activates the data unit 46. Consequently, the serial data line 44 is established, or held, at the logic 0 level, as shown in FIG. 2. This is an erroneous piece of information which is being transmitted through the system. However, the parity check unit 49 will detect the creation of the erroneous information and prevent execution of a command or instruction contained in the message for a frame. Thus, in the system based on the previous description, the frame 7 inactivates the station hardware and converts a frame bit 8 to indicate a parity error which is transmitted to the controller 1. The generation of the clock signal 68 ensures the retransmission of the admittedly erroneous information through the subsequent loop system and particularly back to the loop controller 1 where proper action can be taken.
The fourth time column illustrates a condition where the positive polarity pulse has been lost in a logic 0 transmitted signal 69. As the logic 0 signal is dependent upon the negative pulse and the related output of the negative pulse detector which establishes a proper signal 70 at the negative polarity output line 39 to correspondingly generate the preclock signal 71 and clock signals 72 and with the serial data properly transmitted as a logic 0. Thus, the loss of the subsequent positive polarity pulse does not affect the system as it is not, in fact a data type error.
in the next or fifth time column, a logic 1 bi-polar signal 73 was transmitted. in which the negative polarity pulse was lost and the detector output remains at null. This is the reverse of the previous situation. The positive polarity detector 36 has responded to the first positive polarity pulse of the incoming bi-polar signal 72 to generate the data signal 74 with a pre-clock signal 75 and a clock signal 76 with the resulting proper information transfer as a logic 1 as at 77. Thus, the negative cycle and related negative polarity pulse is not operative for a properly transmitted logic I, and, consequently, its loss has no effect or consequence.
in the sixth time column, the negative polarity pulse lost condition for a logic bi-polar signal 78 has been received. The loss of the negative pulse in this condition results in an improper transmission by failure to establish a signal at line 39 and the activating of circuit 13.
The subsequent positive pulse, however, activates the positive polarity detector 36, with the appropriate output signal 79 at the line 38. This triggers the serial data flip-flop circuit 46 to improperly transmit the signal via serial line 44 as a logic 1. However, this positive polarity related signal 79 also generates the necessary preclock signal 80 and clock signal 81 at the lines 42 and 43 to transmit the erroneous data bit 8. The erroneous nature of the data will again be readily detected by the parity check unit 49 and a commanded execution prevented, as well as an activated parity bit being carried by the message frame 7 back to the loop controller 1 for the necessary response and processing.
Thus, each of the message frame bits 8 as received is serially processed, with each bit automatically generating the necessary timing and clock pulses to produce the desired transfer. Further, through the inhibiting and lock-out circuitry, the malfunctioning due to noise, erroneous signals and the like is essentially eliminated.
In addition, the illustrated circuit automatically generates the necessary clear signal to reset the frame handling means 4 for subsequent receipt of a new frame 7. Thus, the output of the OR gate 50 is also connected to one input of a clear signal timing means or generator 82, also shown as a one-shot unit with the clear output signal line 45 connected to the not-output. The clear signal generator 82 is provided with a substantially longer timing period, such as an eight micro-second time period. Consequently, as long as a pulse signal is established on either the positive or negative receiver lines 38 and 39 so as to generate the pre-clock pulse, the resettable one-shot unit 82 is set to maintain the not-output at a logic 0 level at the clear line 45, as illustrated at 83 in FIG. 2. Once the complete message frame 7 has been processed by the remote station 3, a quiet period of 10 microseconds is introduced into the system by the circuitry of the loop controller 1 which spaces the frames 7 by at least 10 micro-seconds. The clear signal resettable one-shot unit 82 will, therefore, after approximately eight microseconds, reset and generate a logic 1 signal at its not-output and the connected clear line 45, as shown at 84 in F IG. 2. This provides the necessary clear signal for resetting of the system to permit the subsequent receipt of a new message frame 7.
The present invention thus provides a continuous generation of the necessary control pulse such as the timing, clocking and clearing signal pulses for each bit as a result of the receipt of a bi-polar bit signal, particularly either polarity pulse of the bit signal. In this manner, the necessity for separate synchronizing means, scanning means or the like to monitor the message information is eliminated while permitting rapid or high speed digital signal transmission.
Various modes of carrying out the invention are contemplated as being within the scope of the following claims, particularly pointed out and distinctly claiming the subjet matter which is regarded as the invention.
1 claim:
1. A digital signal transmission apparatus employing bi-polar bit signals having a first polarity pulse and a second opposite polarity pulse for each information bit, the improvement in a control pulse generating means for processing a bi-polar bit signal comprising a receiving means having an input for receiving the bi-polar bit signal and generating a correspondingly related polarity signal in response to the receipt of each pulse of the generated bipolar a bit signal, means to select the first of said pair generated opposite polarity pulses as the data information,
a pulse forming means connected to said receiving means for generating a pulse output in response to the receipt of the pulse of said generated bipolar bit from said receiving means and connected to initiate transfer said generated bi-polar bit signal.
2. The digital signal transmission apparatus of claim 1 wherein each of said bi-polar bit signals has a predetermined bit period and said pulse forming means includes a pre-clock timing means establishing a first preclock pulse of a period substantially less than the bit period, said preclock pulse having a leading edge and a trailing edge, and
a clock timing means connected lo said pre-clock timing means and activated by the trailing edge of said pre-clock pulse of said pre-clock timing means, said clock timing means having a clock output defining a clock pulse for controlling transfer of said corresponding bi-polar bit signal.
3. The digital signal transmission apparatus of claim 1 having an inhibit means interconnecting the output of the pulse forming means to the receiving means to inhibit receipt of further information during the period of the pulse output of the pulse forming means.
4. The digital signal transmission apparatus of claim 2 having said clock output connected to said preclock timing means to inhibit operation of said pre-clock timing means during the period of the clock pulse.
5. The digital signal transmission apparatus of claim 1 having a clear timing means connected to the pulse forming means and generating a logic clear signal a predetermined quiet time after the creation of pulse output by said pulse forming means.
6. The digital signal transmission apparatus of claim 5 having a plurality of adjacent bit signals grouped to define message frames separted by quiet periods, and
said clear timing means being operative upon the termination of a message frame and during the quiet period between successive message frames to time out and generate a clear signal to reset the apparatus for subsequent processing of a succeeding message frame.
7. The apparatus of claim 1 including a transmission system comprising a transmitter having a pair of logic switches one responding to a first polarity pulse, and
the second of which responds to a second polarity pulse connected to generate a pulse signal in response to a binary logic signal, a single differentiating transformer network coupling each of said logic switch outputs to one of the transmission lines to produce one of said bipolar bit signals, said receiving means further including a transformer coupled to said transmission lines and a positive voltage detector and a negative voltage detector connected in common to the output of said transformer and responsive to said bi-polar bit signal to generate pulses on a related positive pulse signal line and a negative pulse signal line.
8. A digital signal transmission apparatus employing bi-polar bit signals for each information bit, the improvement in the control pulse generating means for processing of the bit signal comprising a receiving means having an input for receiving the bi-polar signal having a pair of signal lines having polarity related signals generated by the receiving means, for each polarity of the bi-polar signal,
a data storage means coupled to the receiving signal lines and establishing a correspondingly related output data signal in accordance with the first plarity pulse of the bi-polar bit signal,
a pre-clock timing means having a pair of inputs connected to both of said signal line means and generating a pulse output in response to the first incoming pulse on said lines, said timing means generating a pulse having a time period less than the total time period of a bi-polar bit signal,
a clock timing means connected to said pre-clock timing means and activated by the trailing edge of said output of said pre-clock timing means, said clock pulse means having an output defining a clock pulse for transfer of said corresponding bit signal,
an inhibit means interconnecting the output of the clock timing means and to the receiving means and to the preclock timing means to inhibit the receiving means and the preclock timing means during the period of the clock pulse.
9. The digital signal transmission apparatus of claim 8 wherein said apparatus encodes a plurality of information bits into time spaced message frames having preselected quiet periods between the successive message frames, and
having clear timing means having a reset input means connected to the output of the pre-clock timing means and generating a logic clear pulse a predetermined time after reset,
said clear timing means responding to the termination of a message frame and the quiet period between successive message means to time out and generate a clear signal to reset the apparatus for subsequent processing of a message frame.
10. The apparatus of claim 9 wherein the clear timing means is a resettable one-shot circuit having a time out period less than the quiet period between message frames but significantly longer than the timing period of each logic bit.
11. The apparatus of claim 8 wherein the pre-clock timing means is a one-shot circuit having a timing period substantially less than the total period ofa bi-polar signal.
[2. The apparatus of claim 8 wherein said clock timing means is a one-shot circuit having a positive output and a not-output, said clock timing means having a timing period significantly greater than the first timing means but less than the time period of the bi-polar signal following such pre-clock timing means, the positive output of said clock timing means constituting a clock output signal and being interconnected to the pre-clock means to inhibit the subsequent operation and said notoutput being interconnected to the receiving means to inhibit the receiving means.
13. The apparatus of claim 8 wherein the pre-clock timing means is a one-shot circuit having a timing period essentially corresponding to one-quarter of the total period of a bi-polar signal,
said clock timing means is a one-shot circuit having a timing period significantly essentially corresponding to one-half the period of a bi-polar signal.
14. The apparatus of claim 13 wherein said clock one-shot circuit has a positive output and a not-output, the positive output of said clock one-shot circuit constituting the clock output signal and being interconnected to inhibit the subsequent operation of the pre-clock one-shot circuit, said not-output being interconnected to the receiving means to inhibit the receiving means.
15. The digital transmission apparatus of claim 13 wherein said apparatus encodes the information bits into time spaced message frames having preselected quiet periods between the successive message frames, and having a resettable one-shot circuit having a time out period less than the quiet period between message frames but significantly longer than the timing period of each logic bit, said resettable circuit having a reset input means connected to the output of the pre-clock timing means and generating a logic clear pulse a predetermined time after reset,
said timing means being operative upon the termination of a message frame and during the quiet period between successive message means to time out and generate a clear signal to reset the apparatus for subsequent processing of a message frame.
16. The apparatus of claim 15 including a transmission system including a transmitter having a pair of opposite polarity logic switches connected to apply a pulse signal in response to its binary logic input signal, a single differentiating transformer network connecting outputs of each of said logic switches to one of the transmission lines to produce a bi-polar signal, said transmission system including a receiver including a transformer coupled to said transmission lines and a positive voltage detector and a negative voltage detector connected in common to said transformer and responsive to said bi-polar signals to establish a related positive pulse signal and a negative pulse signal in immediate time sequence.
17. A digital signal transmission apparatus employing bi-polar signals having a first polarity pulse and a second opposite polarity pulse for each information bit, the improvement in a control pulse generating means for processing each of said bit signals comprising a receiving means having an input for receiving each bipolar signal and generating a pair of corresponding related polarity signals in response to each bi-polar bit signal and having means to select only a predetermined one of each of said pair of opposite polarity signals as the data information,
a pulse forming means connected to said receiving means and generating a control pulse output in response to an incoming pulse of said generated bipolar bit signals from said receiving means and connected to initiate a transfer of said generated bi-polar bit signal.
UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION THOMAS W. HUEBNER Patent No.
Inventor(s) Column 1,
Column 4,
Column 4,
Column 4,
Column 5,
Column 6,
Column 6,
Column 7,
Column 7,
Column 10,
Column 10,
Line 15,
Line 10,
Line 19,
Line 34,
Line 5,
Line 25,
Line 34,
Line 15,
Line 21,
Line 21,
Line 22,
It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
after "voltage" delete "signal" and insert signals after "such" delete "a" and substitute as after "point" delete "modules" and insert module after "22" delete "through" and insert thus after "voltage" cancel output";
after "processing delete "hardward" and insert hardware after "200" delete "nonoseconds" and insert nanoseconds after "desired" delete "block" and insert clock after "bi-polar" cancel a before "generated" insert of FORM F'O-IOSO (ID-69) USCOMM-DC 60876-P69 a 0.5, GOVERNMENT Pnm'rms OFFICE; Isis o-ase-su.
Patent No. 3, 798, 608
Inventor(s) McCOY M. GIBSON JR. Attesting Officer Column 10, Line 26,
Column 10, Line 36,
Column 12, Line 52 Column 12, Line 57 Signed and sealed (SEAL) Attest:
UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Dated March 19, 1974 THOMAS W. HUEBNER It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
after "the" and before "of" delete "pulse" and insert pulses after "connected" delete "lo" and insert to after "bi-polar" and befiore "signals" insert bit after "of" cancel "corresponding" and insert correspondingly this 24th day of September 1974.
C. MARSHALL DANN Commissioner of Patents FORM F'O-105D110-69) USCOMM-DC 60376-P69 mu... .an
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|Feb 7, 2008
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|Multiplexed rf isolator
|Jan 22, 2008
|Jun 12, 2008
|Baoxing Chen
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|Dec 27, 2007
|Jul 17, 2008
|Baoxing Chen
|Signal isolators using micro-transformers
|Jun 30, 2007
|Oct 30, 2008
|Silicon Laboratories Inc.
|Bidirectional multiplexed rf isolator
|Jun 30, 2008
|Dec 25, 2008
|Silicon Laboratories Inc.
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|Jun 30, 2008
|Jan 29, 2009
|Silicon Laboratories Inc.
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|Mar 30, 2009
|Aug 27, 2009
|Silicon Laboratories Inc.
|Capacitive isolation circuitry
|Mar 30, 2009
|Oct 1, 2009
|Silicon Laboratories Inc.
|Capacitive isolation circuitry with improved common mode detector
|Jun 30, 2009
|Mar 4, 2010
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|Jan 31, 1990
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|Jan 31, 1990
|Oct 27, 1993
|Digital Equipment Corporation
|Transmitting high-bandwidth signals on coaxial cable
|U.S. Classification
|375/258, 375/282, 327/304
|International Classification
|Cooperative Classification
|European Classification
|Mar 8, 1982
Owner name: JOHNSON CONTROLS INTERNATIONAL, INC., 229 SOUTH ST
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:JOHNSON SERVICE COMPANY, A CORP. OF DE.;REEL/FRAME:003962/0639
Effective date: 19820302


text:
Is SIEMENS ENTERPRISE COMMUNICATIONS PVT. LTD. incorrect or missing key business information? Update your Hotfrog listing today.
Contact details
Are these details correct?
Siemens Enterprise Network Group is a premier provider of enterprise network solutions. More than 14,000 employees in 80 countries carry on the tradition of voice and data excellence started more than 160 years ago with Werner von Siemens and the invention of the pointer telegraph. Today the company leads the market with its "Open Communications" approach that enables teams working within any IT infrastructure to improve productivity through a unified collaboration experience.
The SEN Group is a joint venture of the financial investor The Gores Group and Siemens AG. It includes not just Siemens Enterprise Communications, but also Enterasys Networks, SER Solutions, Cycos and iSEC.
Open Communications approach – a unified communications experience that enables people to collaborate, irrespective of their different IT infrastructures, and thus to increase their productivity
What many of our customers expect from us as voice experts today is an excellent telephony system with the potential of being an open platform for Unified Communications later.
Our Performance data:
42 million connections and work points overall
Market leadership
A look at the numbers shows that we are the global market leader in enterprise communications. Our focal area for growth is the North American market. Unified communications is a growth market:
We are…
No. 1 in Germany with 32% (market share of lines)
No. 1 in Europe with 14%
No. 1 in India with16%
No. 2 in LAM with 14%
No. 2 in Argentina with 17%
No. 2 in Brazil with 27%
(Source: MZA, 2008)
Our Total Communication Portfolio of end to end communication solution are following.
· Complete Data portfolio of Siemens-Enterasys Networks for LAN –WAN setup
· Complete Voice portfolio ranging from converged IP solution to pure SIP solution ( 8 port to 1,00,000 ports ).
· Complete Secure controller based Wireless LAN solution with seamless Voice over WiLAN functionality
· Interface application for any available Property Management System for Hospitality Industry.
· Complete range of Video conferencing solution.
· Unified Messaging solution.
· Wide range of Mobility solutions
· Contact
Is SIEMENS ENTERPRISE COMMUNICATIONS PVT. LTD. in 3RD FLOOR, OHM BUSINESS PARK, NEAR BALAJI HOSPITAL, ELLORA PARK(EAST) SUBHANPURA,, Vadodara Gujarat 390023 your business? Claim your listing and attract more leads by adding more content, photos and other business details.
We have more REAL ESTATE services in Vadodara Gujarat available on Hotfrog INDIA. You can update your search for Vadodara REAL ESTATE by location, keyword or service options.
NIZAMPURA Vadodara Gujarat 390002
OPP WAKASKAR RAOPURA Vadodara Gujarat 390001
OPP RAILWAY STATION BAJWA Vadodara Gujarat 391310
DANDIA BAZAR Vadodara Gujarat 390001
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subset: commoncrawl


text:
Lodusky (Dodo Press)
By (author) Frances Hodgson Burnett
Format: Paperback / softback
Normal Price: $15.21
Your Price: $13.69 AUD, inc. GST
Shipping: $7.95 per order
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Availability: Available, ships in 8-11 days
Lodusky (Dodo Press) by Frances Hodgson Burnett
Book DescriptionFrances Hodgson Burnett (1849-1924) was an English- American playwright and author. She was best known for her children's stories, in particular The Secret Garden (1911) and Little Lord Fauntleroy (1886). Her first story was published in Godey's Lady's Book in 1868. Her main writing talent was combining realistic detail of workingclass life with a romantic plot. Her first novel was published in 1877; That Lass o' Lowrie's was a story of Lancashire life. After moving to Washington, D.C., Burnett wrote the novels Haworth's (1879), Louisiana (1880), A Fair Barbarian (1881), and Through One Administration (1883), as well as a play, Esmeralda (1881), written with William Gillette. Her later works include Sara Crewe, or, What Happened at Miss Minchin's (1888) - later rewritten as A Little Princess (1905); and A Lady of Quality (1896) - considered one of the best of her plays. The Lost Prince was published in 1915, and The Head of the House of Coombe was published in Canada in 1922. During World War I, Burnett put her beliefs about what happens after death into writing with her novella The White People (1917).
Buy Lodusky (Dodo Press) book by Frances Hodgson Burnett from Australia's Online Bookstore, Boomerang Books.
Book DetailsISBN: 9781406580334
(229mm x 152mm x 3mm)
Imprint: Dodo Press
Publisher: Dodo Press
Publish Date: 1-Nov-2007
Country of Publication: United Kingdom
Books By Author Frances Hodgson Burnett
Little Lord Fauntleroy, Paperback (January 2017)
Beautifully illustrated by Peter Bailey, this new edition contains extra material for young readers.
Project X Origins Graphic Texts: Dark Blue Book Band, Oxford Level 16: The Secret Garden, Paperback (September 2016)
Project X Origins Graphic Texts can help children to reach higher standards in comprehension. When Mary goes to live with her Uncle, she discovers a secret, locked garden. Will she ever find her way in and what other secrets does Misselthwaite Manor hold?
Little Princess, Paperback (May 2016)» View all books by Frances Hodgson Burnett
When Sara Crewe's father dies, her fortunes at Miss Minchin's boarding school are reversed. Once, she had the finest toys - now, she is forced to become a servant. But as Sara knows, being a princess has nothing to do with being rich. And as she will learn, there is nothing that bravery, imagination, kindness and friendship, cannot overcome.
» Have you read this book? We'd like to know what you think about it - write a review about Lodusky (Dodo Press) book by Frances Hodgson Burnett and you'll earn 50c in Boomerang Bucks loyalty dollars (you must be a member - it's free to sign up!)
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text:
Annual Meeting 2016
HCFA-WA Direct Actions, Winter 2016
HCFA-WA is committed to working with our natural allies in a broad-based movement for social justice, including state-based universal healthcare coverage. We are protesting the arrival of for-profit ZoomCare in our state, which turns away Medicaid and Medicare patients, treating the young and near-healthy. Join us for the May Day/Immigrant Rights March as we continue this year connecting with others in our state. Find us at email@example.com.
One Payer States conference, Chicago, Fall 2015
The 2015 Single-Payer Strategy Conference was sponsored by Healthcare-NOW, Labor Campaign for Single Payer, and OPS (One Payer States, our nationwide network of state-based campaigns). PNHP held their annual meeting at the same time. We are all working for Improved and Expanded Medicare for All, aka a Single-Payer Plan.
HCFA-WA and Health Care for All Oregon members attended with 300 others from around the country. Besides numerous workshops, OPS and PNHP joined forces for this rally outside the Chicago Blue Cross/Blue Shield offices. For more on multi-state efforts firstname.lastname@example.com.


text:
by Lauren Chattman
Traditional icebox pies have been favorites at backyard barbecues and family gatherings for decades, but few people know what an icebox pie really is. They are simple pies that require no rolling of pastry dough—the crusts are made from cookie crumbs and quickly crisped in the oven; the fillings are uncooked or prepared on the stovetop; and the pies set in the refrigerator or freezer for a few hours before being served. It may seem too good to be true, but Lauren Chattman proves that these pies are really that simple. Icebox Pies: 100 Scrumptious Recipes for No-Bake No-Fail Pies has delicious and varied recipes that range from classic to exotic, with everything in between. Accompanied by 25 stunning full-color photos, Chattman's recipes are sure to be the hit of every outdoor party and barbecue.
Chattman starts her exploration of icebox pies with a chapter on crusts. Although they are all simple to prepare, Chattman's recipes range from Classic Graham Cracker Crust to Amaretti Crust and from Chocolate Cookie Crust to Sugar Cone Crust (perfect for ice cream icebox pies). After crusts come the fillings themselves: mousse, pudding. And custard pies; chocolate-based pies; fruit- and cream pies; ice cream and sorbet pies; and more. Although appropriate—and delicious—all year 'round, icebox pies are especially welcome in the warmer months when the last thing you want to do is turn on the oven. Try Gianduia Pie to dazzle guests at your next dinner party or Triple Chocolate Mint Pie to impress your favorite chocolate lover. Classic flavor combinations shine in icebox pies like Milk Chocolate and Cherry Pie, Mango and Coconut Ice Cream Pie, and Black Bottom Butterscotch Pudding Pie. and more exotic ones shine too in White Chocolate Tapioca Pie with Mangoes, Chocolate and Honey Pudding Pie, and Cranberry and Butterscotch Chip Ice Cream Pie. Chattman finishes off with toppings to dress up your icebox pies. She offers tidbits and tips throughout to make shopping and assembling as easy as possible.
Icebox Pies
100 Scrumptious Recipes for No-Bake No-Fail Pies
by Lauren Chattman
Harvard Common Press
$16.95 (U.S.) paperback
Information provided by the publisher.
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text:
Palm Seti Long Sleeve Womens
With its grid-like Core 2 waffle fabric, the Seti is just thatexceptionally breathable insulation you need under yourpaddle jacket. And it dries quickly too. Athletic cut forfreedom of movement, with thumb loops, a low profileneck zip and a chest pocket.
MATERIALS - Core 2 (91% polyester, 9% spandex)
WEIGHT - 295 g (L)
CUT - Female Specific form fitting • Anatomical shaping for fit and comfort• No underarm seams prevent chafing • Droppedrear hem
CONSTRUCTION - ActiveSeam stitching for extra strong andcomfortable seams • Waffle construction forenhanced breathability
POCKETS - Zipped chest pocket
OTHER FEATURES - Half length front zip • Lifted collar to prevent chafing• Thumb loops
Additional Information


text:
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Established by our Chairman, John Whittaker, over 40 years ago, The Peel Group has grown through an ethos of recycling capital and delivering long-term investment, primarily in the North West of England.
The family-owned Group is an investor in tangible assets comprising land, air or water. Our principal investments encompass the transport, retail and leisure, property, land, energy and media sectors.
Our investments are made either directly through Peel Land and Property Group or via a wide range of partnerships and shareholdings in private and public companies.
We invest for tomorrow.
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text:
Dbl End Thd Stud, 1/2-20, Alum
VALUE BRAND| Zoro #: G1868806| Mfr #: LINK50018EA
Zoro #: G1868806Mfr. Part #: LINK50018EA
$18.10 /ea
Orders over $50.00 ship free. DetailsStandard ground shipping
Technical Specifications
|Zoro #: G1868806 Mfr #: LINK50018EA
|System of Measurement: Inch
|Thread Type: UNF
|Item: Double End Threaded Stud
|Thread Length Type: Equal
|Grade: -
|Class: 2A
|Thread Direction: Right Hand
|Min. Tensile Strength (PSI): 35, 000
|Rockwell Hardness: B85-B95
|Shank Type: Round
|Overall Length: 18"
|Thread Size: 1/2"-20
|Material: Aluminum
|Finish: Plain
|Workable Length: 16"
|Thread Length (B): 2"
|Thread Length (A): 2"
|Country of Origin (subject to change): United States
Product Description
Double End Threaded Stud, Aluminum, Finish Plain, Thread Size 1/2-20, Overall Length 18 In, Thread Length (A) 2 In, Thread Length (B) 2 In, Thread Length Type Equal, Thread Type UNF, Shank Type Round, Thread Direction Right Hand, Class 2A, Min. Tensile Strength 35, 000 PSI, Rockwell Hardness B85-B95


text: Hey, i couldn't find any information on a search i did about this information. Just wandering what the WMS of a Front Chevy Dana 44 and Rear Ford 9 Inch are? I got a friend who wants to put full size axles on his jeep, and this thinking about these two, since he can get them almost free. Thanks. Tyler


text:
- Forum: Streetwear and Denim
- Thread: NIKE Thread
Do any of you guys know how much the tech fleece sweats stretch from the knee down? I recently picked up a pair and from the knee up fits perfectly in my normal size but from the knee down is pretty tight and fitted. I don't want to size up because I'm sure a large will give my butt the diaper look.


text:
Market Research
This project was awarded to neatcodersl for $59.5 USD.Get free quotes for a project like this
Project Budget$30 - $100 USD
Total Bids2
Project Description
I need a short report on the news agency and photo agency industries. Market size, market growth, sales volumes, employees, major companies, trends, customer segments etc. I need to look at this from three different perspectives: 1. World wide 2. US and Western Europe 3. Sweden and Nordic countries. I guess you'll need around 2 pages of text for this. I will edit the text, so there's no need for your to put time on editing. Just give me the research, facts and don't forget to include sources to where you got the info (web sites, telephone calls or whatever).
## Deliverables
## Platform
Awarded to:
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- Forbes
- The New York Times
- Time
- Wall Street Journal
- Times Online


text:
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|"Andrzej Bialecki (JIRA)" <j...@apache.org>
|[jira] Commented: (NUTCH-443) allow parsers to return multiple Parse object, this will speed up the rss parser
|Wed, 14 Feb 2007 15:15:06 GMT
[ https://issues.apache.org/jira/browse/NUTCH-443?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12473114 ] Andrzej Bialecki commented on NUTCH-443: ----------------------------------------- The contract for ParseUtil.getFirstParseEntry() seems unclear - since in most cases this is a HashMap, there is no predictable way to get the first entry added to the map ... I propose also that we should use a specialized class instead of general-purpose Map; and then we can record in that class which entry was the first. Also, the naming of some methods seems a bit awkward - why should we insist that we createSingleEntryMap while we create an ordinary Map, and we don't use this special-case knowledge later? I suggest to simply name it createParseMap. In recent versions of Hadoop there is a GenericWritable class - it replaces ObjectWritable when classes are known in advance, and provides a more compact representation. Changes to MapWritable must preserve old code values, at most adding some new ones - otherwise the new code will get confused when working with older data. CrawlDbReducer, TODO item: this should be the time stored under Nutch.FETCH_TIME_KEY, no? If I'm not mistaken, ParseUtil doesn't need the import of HashMap, only Map. The new model for returning results from parse plugins allows a much better approach to parsing archives (eg. zip files) containing multiple documents in supported formats - although this should be a separate patch. > allow parsers to return multiple Parse object, this will speed up the rss parser > -------------------------------------------------------------------------------- > > Key: NUTCH-443 > URL: https://issues.apache.org/jira/browse/NUTCH-443 > Project: Nutch > Issue Type: New Feature > Components: fetcher > Affects Versions: 0.9.0 > Reporter: Renaud Richardet > Assigned To: Chris A. Mattmann > Priority: Minor > Fix For: 0.9.0 > > Attachments: NUTCH-443-draft-v1.patch, NUTCH-443-draft-v2.patch, NUTCH-443-draft-v3.patch, NUTCH-443-draft-v4.patch, NUTCH-443-draft-v5.patch, NUTCH-443-draft-v6.patch, parse-map-core-draft-v1.patch, parse-map-core-untested.patch, parsers.diff > > > allow Parser#parse to return a Map<String,Parse>. This way, the RSS parser can return multiple parse objects, that will all be indexed separately. Advantage: no need to fetch all feed-items separately. > see the discussion at http://www.nabble.com/RSS-fecter-and-index-individul-how-can-i-realize-this-function-tf3146271.html -- This message is automatically generated by JIRA. - You can reply to this email to add a comment to the issue online.
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Stefano Pioli apologised to the Bologna fans, while Cesena President Igor Campedelli relishes their first victory.
Bologna 0-1 Cesena [12]
Bologna Coach Stefano Pioli: "It's a heavy defeat for us. This was a very important game and was meant to be a turning point in our season. We apologise to the fans and the club."
Cesena President Igor Campedelli: "Daniele Arrigoni won't talk to the media when playing away from home. It's his superstition. We wanted this victory for a long time and it really fires us up."
Keep up to date with the latest news and action from Spain's Primera Division with Football Espana - from the team behind Football Italia. [13]


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I don't know what is going on.. but it is a shame that we are all being
punished. Someone complains and then suddenly no more pictures. I happen
enjoy getting those pictures. It is making my wish list grow by leaps and
bounds. If someone is having problems then there are choices that can be
1. just get off the list.
2. the owner can kick that person off the list.
3. simply just hit the delete key.
Instead someone has to complain and step on the owners feelings....to
benefit what????
These people do this as a FAVOR to us. They are not getting paid. It is
not their job and just how do we say thank you...? By degrading all their
hard work... Why do people have to make such a fuss over something that can
be easily fixed with a click of a mouse
Hey CLYDE....... I would still like to receive pics from you and any other
who has a great pic of a Hosta that they want to share
To sign-off this list, send email to firstname.lastname@example.com with the
message text UNSUBSCRIBE HOSTA-OPEN


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Sherlock on BBC One
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BTS Sherlock . I don't think these have been posted already but let me know if they have. . Wallpaper and background images in the Sherlock on BBC One club tagged: sherlock sherlock holmes john watson bbc series 2 benedict cumberbatch the reichenbach fall andrew scott moriarty.
Submitted by MichaelxxRupert over a year ago
Keyword: sherlock, sherlock holmes, john watson, bbc, series 2, benedict cumberbatch, the reichenbach fall, andrew scott, moriarty


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"Spell-Mageddon" premiered on ABC Family Wednesday night (July 24), featuring host Alfonso Ribeiro of "The Fresh Prince of Bel-Air" guiding contestants through spelling challenges while also being pelted with fire extinguisher foam or dunked into icy water.
Ribeiro did a conference call about the show and he wants you all to know how funny it is, which we think is maybe a case of the lady doth protesting too much. But anyway, here are the best lines from the call:
"It's really a comedy show … the things that we are doing to these contestants are amazing."
We'll be the judge of how funny it is.
"Obviously, this is on ABC Family's comedy Wednesdays following Melissa and Joey and Baby Daddy."
Don't forget to pimp the other stuff that's on.
"I think that the comedy aspect of this show is what's really going to drive people to the show and keep people coming back week after week. It is really, really funny. Every episode that we've shot I'm laughing in the episode because I can't do anything other than laugh. It really is just that funny."
Yeah, we get it — it's funny.
"This is one of those shows were you go, this is an obvious television show. I think America, when they see it, will fall in love with it. I think it's just so funny."
We aren't sure this is something that just screams "television show," but OK.
When asked if people will like the lowbrow aspect: "I don't think it's lowbrow in any way because we're not spelling cat. We're not spelling dog. We're spelling psychedelic, psychology. We're spelling words that some people have a hard time spelling if they're not good at spelling."
It's still a little lowbrow, though. You zap people.
On having been Calrton Banks on "Fresh Prince": "It's a blessing and a curse at the same time. Obviously, the fans who have adored me and loved me and show me their love on a daily basis is flattering to say the least. … The curse part is when you're literally at a urinal in a public bathroom and people walk up to you, tap you on the shoulder and ask you to do a dance for them."
But how would Carlton do on "Spell-Mageddon"?
"I think Carlton Banks would win Spell-Mageddon. Obviously, he was super smart. He was still relatively athletic. He was unwavering in his convictions. I think Carlton would've done very well on that show."
We'll give you that one.
What did you think of "Spell-Mageddon"? Are disappointed it's not a wizard-themed movie on Syfy?


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Can a vegetarian person get a good meal at this restaurant?
Can a gluten free person get a good meal at this restaurant?
Is this restaurant good for brunch?
Is this restaurant good for large groups?
Is this a dessert shop?
Does this restaurant have waiters and waitresses?
Is this restaurant good for lunch?
Is this restaurant good for breakfast?
Is this restaurant good for dinner?
Is this restaurant wheelchair accessible?
Thanks for helping!
Stopped for dinner after a 5k run ... great friendly service with a smile, plentiful portions, excellent flavors in a homey atmosphere well worth finding and waiting for .... it takes a while for a pizza, but this is GOOD food, not fast food.
the best of greek..the gyros and salads are huge..you can take leftovers for dinner so much great food..the staff is so friendly and accommodating..the fresh cookies are excellent
A small restaurant with a big business. The staff are very friendly and efficient. The food is very good, prepared and served efficiently. Their mussacaka is my favorite.
Short, sweet and to the point. Simply the best Greek food within 100 miles. Please, don't pass it by. The hours are a little strange open for dinner only on weekends but so worth the additional effort and inconvenience.
Another great place to get a gyro! They probably have the best hummus in Las Cruces! I love to stop in this place for a quick lunch!
There are not many places in Las Cruces to get Greek food. I was really looking forward to this experience. My husband ordered lamb gyro sandwich and I ordered a moussaka plate. My husband said his food was decent. My moussaka tasted like nothing I have ever tried before. It was dried up tidbits of food (eggplant was hard to...
Each time I have gone to Tiffany's it has been a very pleasurable experience. The portions are good and the food is excellent. From the Spanakopita to the Salads we have never been disappointed.
Any choice you make will be a good choice! The food is fresh, seasoned perfectly and so good! The atmosphere is very homey and the whole family works here. Great choice! The hummus and gyros are my favorite.
Not much to say other than it must be tried to be believed. Everything is outstanding. Way above normal for the area. The hours are a little screwy but worth the trouble.
The portions are quite large for the price you pay. The gyros are extremely good. The Greek salad is a good compliment to the gyro.
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New Wales captain Bradley Davies has expressed his delight at being named to lead the squad in Japan next month.
New Wales captain Bradley Davies has expressed his delight at being named to lead the squad in Japan next month.
The Cardiff Blues lock endured a difficult season with injuries and suspensions, but has come out the other side and will now lead a weakened Wales squad in a two-Test tour due to 15 players being away with the British and Irish Lions.
"Any chance to play for Wales is a massive honour but to captain my country is a feeling I've never experienced before," said Davies.
"It's amazing, especially after the time I've had. I've been injured, banned, knocked out – everything that could happen to me has happened.
"My family are very proud. I think my Nan told everyone in Llantrisant before it was even announced."
Davies has not played for Wales since last November, after he was knocked out by a swinging arm from All Blacks hooker Andrew Hore. He then missed the successful 2013 Six Nations campaign due to an ankle injury.
"It's been difficult because I went through a stage where I played 10 to 15 internationals, starting every game, then I ended up on the bench a lot and my career got a bit messy, with small injuries and decisions not going your way," added Davies.
"But I've learned from things and see this as the halfway point in my career. I've been a bit unlucky. I've taken my eye off the ball at times, but I've refocused. When you are away from the Wales camp and you watch the boys play on television, it gives you a kick up the backside and a desire to get back in.
"Sometimes you might take things for granted and, if there's a savage fitness session, ask yourself what you're doing there.
"But being out of the camp puts it in perspective. Sitting in my local pub watching Wales win a Grand Slam is not a nice feeling."
Despite his focus being on leading Wales, Davies admits that if he were needed by the British and Irish Lions in Australia then he would be available to make the relatively short journey south.
"It's an easy flight down from Japan – not too far. I would row it if they wanted me to join the squad," stated Davies.
"Obviously, I don't want to wish an injury on anyone, but if the chance does come I'll grasp it with both hands."


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30:25–43 God sovereignly blessed Jacob's flocks at Laban's expense in spite of the inexcusable cunning of both men. Jacob appears to outwit Laban, repaying Laban's trickery, but he obtained his family and wealth entirely by God's grace (29:31–30:24; 31:9).
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text: Dr. Pepper Is the Secret to Living Long, Healthy Life for 104-Year-OldMark Shrayber3/20/15 6:00pm685EditPromoteGo to permalinkWe've had a lot of discussion on how to stay alive forever. More and more people are living to 100 and whether it's staying away from men or eating White Castle on the regular, every centenarian has their own way of doing things to prolong their lives. Meet Elizabeth Sullivan, who owes it all to Dr. Pepper.


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Top Videos
2016 State of the Valley
More than 1,200 people packed the San Jose McEnery Convention Center February 12, 2016 for Joint Venture's annual State of the Valley conference, where they heard an update on the region's economy, keynote remarks by former House Speaker Newt Gingrich and former Rep. George Miller, former HUD Secretary Henry Cisneros, United States Patent and Trademark Office Director Michelle Lee and NAUTO co-founder and Stanford professor Stefan Heck of the Precourt Center for Energy Efficiency. The audience also heard a lively debate by a distinguished panel of auto industry executives and environmental experts arguing the future of the combustion engine. The Packard Award went to Code for America founder Jennifer Pahlka, an exhibition hall showcased a dozen nonprofit organizations and local school bands provided musical entertainment.
Briefing on the 2016 Silicon Valley Index
Joint Venture CEO Russell Hancock explored the data in the 2016 Silicon Valley Index, which shows that the regional economy is continuing its powerful trend upwards. However, the explosive increases in jobs and population are overwhelming transit systems and roadways and keeping affordable homes out of reach for many.
The comprehensive yearly analysis of the economic strength and overall vitality of Silicon Valley shows 134,000 new Bay Area jobs created between mid-2014 and mid-2015, average annual earnings up to $122,000, $24.5 billion in venture capital investments in 2015, 19,000 new patent registrations in 2014 and more than 23 million square feet of new development approvals over the past two years.
At the same time, widening income inequality persists, the median sale price for a home is up six percent to $830,000, rental rates are up eight percent, and average commute times rose to 27 minutes.
Here is Joint Venture President and CEO Russell Hancock's report on the 2016 Index, produced by the Silicon Valley Institute of Regional Studies, an arm of Joint Venture.
Learn more about the Silicon Valley Index online at www.siliconvalleyindicators.org.
Top Downloads
Economic Update: The Peninsula Economy - November 2016
This brief, the third in a series, provides an update on the economy in Silicon Valley and San Francisco, here referred to as "the Peninsula economy." The Peninsula sub region includes Santa Clara, San Mateo and San Francisco counties.
Bridging the Gap: 21st Century Wireless Telecommunications Handbook - September 2016
To keep pace with rising demand for wireless data, we must embrace new technologies and adjust local ordinances to account for them. This handbook was written primarily for municipal employees, elected officials, and civic leaders to help guide their understanding of new and future wireless technologies.
California Regulations and Employment in Silicon Valley - July 2016
This report addresses the extent to which state level regulation of business activities affects job growth in Silicon Valley.
Silicon Valley Index - 2016
The 2016 Silicon Valley Index reveals Silicon Valley's economy is thriving from San Jose to San Francisco, surging to levels that are overwhelming the Bay Area's capacity to handle it.
Learn more about the Silicon Valley Index online at www.siliconvalleyindicators.org.


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Review Summary
- Intimate family-owned hotel with scenic grounds and wildlife
- One- or two-bedroom suites with patios/balconies, kitchenettes
- Outdoor pool and bar area, and weekly cocktail parties
- On-site perks include spa, fitness center, and art gallery
- Rooms have flat-screen TVs with satellite TV
- Daily shuttle to the beach
- All-inclusive packages available
- Free parking and Wi-Fi
- Not within walking distance to the beach or area sites
- Some suites have two twin beds and lack natural light
- Kitchenettes can be narrow and hard to move around
- Older shower/tub combos
- No iPod docks or CD players
Bottom Line
This Mediterranean-style hotel and spa is tucked away in the hills of northern Barbados. Although it lacks oceanfront property, it has something other area hotels don't: Scenic wildlife such as green monkeys, warblers, and roosters roam freely on the expansive property. All-inclusive packages are available, although there is only one restaurant, La Salsa, for breakfast, lunch, and dinner. (A "rum shop" is also on premise, though open hours are limited.) One- and two-bedroom suites are clean and include kitchenettes, but lack natural light and some modern amenities (such as iPod docks). A large outdoor pool, spa, fitness center, art gallery, nature trail, and beach shuttle may help guests forget about the inland location.


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Exodus 32:1-6New International Version (NIV)
The Golden Calf
32 When the people saw that Moses was so long in coming down from the mountain, they gathered around Aaron and said, "Come, make us gods[a] who will go before us. As for this fellow Moses who brought us up out of Egypt, we don't know what has happened to him."
2 Aaron answered them, "Take off the gold earrings that your wives, your sons and your daughters are wearing, and bring them to me." 3 So all the people took off their earrings and brought them to Aaron. 4 He took what they handed him and made it into an idol cast in the shape of a calf, fashioning it with a tool. Then they said, "These are your gods,[b] Israel, who brought you up out of Egypt."
5 When Aaron saw this, he built an altar in front of the calf and announced, "Tomorrow there will be a festival to the Lord." 6 So the next day the people rose early and sacrificed burnt offerings and presented fellowship offerings. Afterward they sat down to eat and drink and got up to indulge in revelry.
Cross references:
New International Version (NIV)
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Editorial Review
- Rating:
- 13 / 20
- Price:
- $$$$$
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Write a review!
3 reviews of Xo Asian Cuisine, first by you?
September 16, 2012
Good "chinese" options for lunch if you work downtown GR. Conveniently located.
November 1, 2010
Wonerful flavor combos
The food is great. Its not your typical asian cuisine. They blend sushi, Chinese and Thai dishes and flavors. If you want something a little different but VERY good try some of the house specials. They look almost as good as they…
July 11, 2008
good food, but menu items rated spicy are not spicy at all. waitstaff are usually attentive, but once i was left waiting about 20 minutes for my bill - had to ask for it. decor is very nice. atmosphere is upscale. \r even though i…
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12/28/2014 A diner from Chicago, IL tried it, liked it, and rated it . They liked the food, liked the service, and liked the ambiance.
5/15/2014 A diner from Chicago, IL tried it.


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Here's the summary of the book:
My name is Chloe Saunders and my life will never be the same again.
All I wanted was to make friends, meet boys, and keep on being ordinary. I don't even know what that means anymore.It all started on the day that I saw my first ghost---and the ghost saw me.
Now there are ghosts everywhere and they won't leave me alone. To top it all off, I somehow got myself locked up in Lyle House, a "special home" for troubled teens. Yet the home isn't what it seems. Don't tell anyone, but I think there might be more to my housemates than meets the eye. The question is, whose side they on? It's up to me to figure out the dangerous secrets behind Lyle House.....before its skeletons come back to haunt me.
© Copyright 2017 Barbarolvr93. All rights reserved.
Status: Finished
Genre: Other
hi! olivia.
1. OLIVIA: The name of Olivia has given you sensitivity and appreciation for the finer and deeper things in life. You can enjoy reading, study, and contemplation about many different subjects. When your interests or curiosity are aroused, you work intensely at new undertakings, but your interests often wane when you encounter drudgery and monotony, with the result that you leave many things unfinished. Your name has taken you into many bitter experiences. The greatest lack in your life is stability and peace of mind. A peaceful and quiet environment, especially out in nature, is one of your greatest desires, but you are constantly taken into chaotic conditions. The name Olivia creates an interest in the deeper aspects of life.
Book / Romance
Book / Romance
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Read along with the Sword and Laser book club! From classic science fiction to the latest gritty fantasy, we cover it. Subscribe for book discussions, author interviews, hot releases, and news from the genre fiction world!
April 11th, 2014
Episode 71 of 228 episodes
How did Brent Weeks get from Montana to writing novels on napkins to becoming the bestselling author of the Lightbringer Series? We'll ask him about that, find out his favorite word and whether he still has those napkins. Download audiohere.Download videohere.
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Welcome to the daily audio workout for your head.


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More Videos...
Legendary CRASHES
A compilation of historic wrecks...from 1931, to just the other day. You've never seen anything like this before. Very rare footage. MUSIC by the HOT ROD REBELS!!! To the men who paved the way in motorsports; to your bold attempts at dodging fate: We salute you.
Mazda RX-7 Crash at 225 MPH!!
Bonneville Salt Flats: 3rd gen Mazda RX-7 race car trying to beat the land speed record for a production vehicle. At this speed, the tire patch that is touching the ground is LESS than the width of your index finger across each tire. Furthermore each patch is encountering dust and small sand-like particles often. If you could keep the pace with this car and remain standing next to it, you could reach over and push it away from you sideways with little effort. The announcer claims that an additional burst of oxygen in the fuel causes a loss of control, but in all likelyhood, the wind just changes ever so slightly, or began to blow (even lightly) and it was actually this that nudged the cars nose off by just enough to start a flat spin. Yes, a flat spin, like an airplane goes into! No rudder on this vehicle, so no control!
230 MPH RX7 crash at Bonneville
200 MPH Motorcycle Crash
wiped out twice while trying to set a world record ron cook: http://www.pureguts.com/sdm.asp?pg=stories&specific=1


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Below are poems written by poet
Jermaine Kirimi. Click the Next or Previous links below the poem to navigate between poems. Remember, Poetrysoup is an environment of encouragement and growth. Thank you.
List of ALL
Kirimi poems
Jermaine Kirimi
I am in deed messed up,
My heart pounding on the rock,
As I pierce my pain on the phase of a tanzanite,
I Grimm as I reap down the valley,
My stress is too dim trying to get hold of the rest,
Test me twice thrice is no test,
The psychology played tormenting!
Facts are stated but never illuminated,
Light is darker but why not show the light,
I alight my path but the eerie of the air,
Still black as coal as stuffy as foul,
My play is to wait for the dark clouds to pass,
But I see no hope only the reapers touch,
I lie to ground and wait my fate,
Let the earth and sky decide or weigh,
Am at peace let me relax and wait.
Copyright © Jermaine Kirimi | Year Posted 2016


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Today's Deals
ASUS Nexus 7 FHD Official Travel Cover for $5 + free shipping
ANTOnline offers the ASUS Nexus 7 FHD Official Travel Cover in Pink for $5.29 with free shipping. That's pennies under our mention from last week and the lowest total price we could find in any color today by $3. It features inserts for connectors.
Note: It's also available in Light Blue or Orange for $5.59 with free shipping.


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This short, immersive piece from Cie des Femmes à Barbe is billed as a "unique theatrical experience", which is always a dangerous boast to make at the world's largest arts festival. In fact, there are several shows straddling theatre and fairground attraction at this year's Fringe, notably HUFF, Shona Reppe and Andy Manley's inspired walk-through installation based on The Three Little Pigs. Antiquithon, performed in the basement of the French Institute, is a parody of an early 20th-century cabinet of curiosities, a room full of strange artefacts, some genuine and some faked.
There is always a sense of excitement about waiting