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Hotfrog Canada provides information regarding The Western Producer in Saskatoon SK. The Western Producer is located at 2310 Millar Ave, Saskatoon SK S7K 2Y2 and provides Entertainment services. Contact them on (306) 665-3500 or by visiting them on their website http://www.producer.com.
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227 Pinehouse Drive SASKATOON SASKATCHEWAN S7K 6N9
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text: Join the Community! Creating your account only takes a few minutes. Join Now Monthly information regarding the total number of voting rights and the total number of shares of the Company Read More Reply Subscribe This discussion has been inactive for over a year. You may get a better answer to your question by starting a new discussion. Oops, something's wrong below. Text Quote Post | Replace Attachment Add link Text to display: Where should this link go? Add Cancel × Insert code Language Apache AppleScript Awk BASH Batchfile C C++ C# CSS ERB HTML Java JavaScript Lua ObjectiveC PHP Perl Text Powershell Python R Ruby Sass Scala SQL VB.net Vimscript XML YAML Insert Cancel Follow this vendor page Reply

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Interaction of Fatty Acid Monolayers with Cobalt Nanoparticles
Readership Statistics
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Announcement "You'll see a thread of simplicity throughout the handmade jewelry collection. The gemstones are so beautiful on their own -- they don't need much intervention from me!" See Policies and Profile for more information.
"You'll see a thread of simplicity throughout the handmade jewelry collection. The gemstones are so beautiful on their own -- they don't need much intervention from me!" See Policies and Profile for more information.
colleen bowcock on Feb 18, 2017
I ordered 2 bracelets from this page and the owner was a delight to deal with!! She responded back with in 2 hours of me contacting her about a customer order and I had them with in a week! Super professional and amazing to deal with! The bracelets are gorgeous and beautiful quality thank you!
MARY FYFE on Feb 7, 2017
These earrings are beautifully sculptured, very stunning, I have worn them proudly. Please keep up your beautiful work
Stacey Fischer on Dec 10, 2016
The ring has beautiful color and fits well as expected. Linda was amazing and answered every question I had to make this purchase become reality. Thank you Linda for your help and for a beautiful ring I will wear often.
Linda Blackbourn Jewelry
Linda Blackbourn Jewelry is really just me, some rocks and a flair for design and fashion. I started creating jewelry nearly 10 years ago -- selling online, and in craft shows ... and it has grown into a wonderful passion. I say that the "gemstones don't need much intervention from me", and it's true. Their beauty on their own is enough -- they just need a little silver or gold, and a little direction.
In 2008, I worked with a group of neighbor/artists to start a local gallery/shop, in Silver Spring, MD, called ArtSpring. Over time I met a lot of the local artist and indie crafters and I loved the coalition we created. I left the organization of ArtSpring in 2011, (which is now in Takoma Park, MD). I am no longer affiliated.
In September of 2012, working with a business partner (another local jeweler) -- we collaborated with some like minded individuals to start GALA Artisan Jewelry and Gifts, in Kensington, MD. (http://www.galaartisans.com). GALA is a store selling hand crafted work of all types (not just jewelry), and is run by the artists who create the work.
My work is available at several brick and mortar shops, I will still do some selected shows in the DC/MD region as well, but nowhere is better than Etsy.
Shop members
Linda Blackbourn
Owner, Maker, Designer
I am a jewelry designer focusing on beaded gemstone jewelry and silver work in .925 Sterling Silver, as well as the co-owner of Gala Artisan Jewelry and Gifts in Kensington, MD.
Shop policies
Have fun browsing, and don't forget to visit again. These fingers are always working.
Wholesale inquiries welcomed.
Accepted payment methods
- Accepts Etsy gift cards
- Money Order
boxes with bows - suitable for gift giving. Shipping Costs: Domestic mail: $2.75 + $1 for each additional item. I will upgrade to priority for $5.00 + $2 for each additional item. Express mail (overnight) is $12.00 + $2 each additional item. Insurance is determined by the P.O. - let me know if you want it - it's usually $2-$4 domestically. Sometimes I add it on to one of a kind items at my discretion but I will cover the costs. International airmail is $6 + $2 for each additional item. Canada is usually less and I will refund anything over a $2 difference. There is generally no insurance offered on International orders.
Refunds and Exchanges
*Customized orders are not returnable.


text:
Determinants of proactive and reactive technology licensing: A contingency perspective
Industrial firms increasingly attempt to license their technologies apart from applying them in their own products. Because of the imperfections in technology markets, an active approach towards technology licensing does not automatically result in licensing transactions. To balance prior research, which has focused on licensing transactions as the outcome of licensing intentions, we take a contingency view to analyze how characteristics of a firm's innovation ecosystem determine different strategic types of licensing. Specifically, we distinguish proactive licensing, which refers to identifying recipients for technology transactions, and reactive licensing, which relates to offering licenses to infringers of a firm's intellectual property. Survey data show that environmental antecedents concerning appropriability, i.e., patent protection and technological turbulence, and determinants regarding technology markets, i.e., transaction frequency and competitive intensity, have different effects on proactive and reactive licensing. On this basis, the article has major implications for research into technology licensing, markets for technology, and open innovation.
If you experience problems downloading a file, check if you have the proper application to view it first. In case of further problems read the IDEAS help page. Note that these files are not on the IDEAS site. Please be patient as the files may be large.
As the access to this document is restricted, you may want to look for a different version under "Related research" (further below) or search for a different version of it.
Volume (Year): 39 (2010)
Issue (Month): 1 (February)
Pages: 55-66
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| Web page: http://www.elsevier.com/locate/respol
References listed on IDEAS
Please report citation or reference errors to , or , if you are the registered author of the cited work, log in to your RePEc Author Service profile, click on "citations" and make appropriate adjustments.:
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Black Net Designer Salwar Kameez
Guide price: £220
Last updated on 2nd May 2015
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Lot 2016: Wen Wenguang (b. 1948)
Watches & Jewellery, Fine Chinese Paintings & Works of Art
by Gianguan Singapore
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Wenguang Wen (1948-) Please Register/Login to access your Invaluable Alerts
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Wen Wenguang (b. 1948)
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What good is success if not shared and paid forward with attitude and deed? And how much envy can we muster for a supremely successful asshole who can't muster a kind word for anyone?
How we treat others should be a choice that reflects our character -- not a reaction to other people's character. So, I choose to be kind because my kindness will define me. Not my parents. Not my relationships. Not my sexuality. Not my work. But my kindness.
In three weeks, I will graduate from UCLA. The greatest advice that I have for incoming and current scholars is simple: be fearless. Face your fears. Don't be afraid. Fear will hold you back. Bravery will push you forward.
By Joan Tupponce
Here are a few of Patience Salgado's stealth-kindness missions which anyone can duplicate in her own neck of the woods.
We got a saint in our family. ... I thought, you know, I could be doing just a little bit better. Be a little nicer. Count to ten. Go out of my way once in a while. What, I wondered, would it be like if I tried to do a good deed -- even something tiny -- for a whole year?
How often have we each been so embroiled in our own petty dramas that we breeze past someone in trouble? My hand is raised. How about yours?
Is it not time to make kindness cool, to make consideration and caring hot topics? We've already proven that war does not work, that fighting and killing never has a happy ending.
I was about to get a promotion. My boss said sternly, "Be polite and be fair. Then you'll do fine." I've always remembered that.
There is only one place to practice compassion: the one you're in. You can never leave this place, but you can turn it inside out.
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Black Jett Jeans
House of Holland have tapped in to the mid-90's skate culture and iconic street wear brands popular at the time. With designer Holland, delving into memories of his adolescence spent in car parks of Northern England, the collection continues the autobiographical slant of the brands debut menswear collection.
Menswear 'Season 2'Jett Jeans
- 100% black cotton
- Denim
- Embroidered patches and vecro strips
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-Oversized to sit on the hip
Model wears a 32.
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Embroidered Floral Denim Shorts
Lee AOP Release Shorts
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Besides being visually strinking, this two-tier bamboo steamer by Ken Hom Wok includes enough space to cook several guests. Recipes leaflet included. This piece is suitable to use in conjunction with any wok.
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What to Expect When You're Expecting LA Premiere
Brooklyn Decker, Cameron Diaz, Jennifer Lopez, and More Light Up What to Expect in LA — Who's Most Fab?
Last night's What to Expect When You're Expecting premiere drew the styled cast out to Grauman's Chinese Theatre in LA, with each of the film's stars showing off her own version of glamour. The film screening was lit up with arrivals from the leading ladies, including Brooklyn Decker in a sunny Giambattista Valli confection, Cameron Diaz showing off her stems in black, and J Lo stepping out in an ultrachic Maria Lucia Hohan gown. Along with the standout cast, Whitney Port joined the festivities in a gold and black patent minidress. Click on for hers and the rest of the night's big arrivals — and be sure to tell us your pick for best dressed in the comments.


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This Lent, take a 40-day devotional journey with Dietrich Bonhoeffer. Click here to sign up.
Paul had received word that in Galatia, where he had preached the Gospel, there were some who were preaching "another gospel," which was unsettling the believers. These other preachers were responsible for "bewitching" (3:1; cf. 1:6-9) them. These perceived troublemakers apparently were not only casting aspersions on Paul's preaching, but also on his person. The issues seem to center on (1) whether non-Jewish believers must enter into Christian fellowship via Judaism and its covenantal mark, circumcision, and (2) whether Paul had legitimate apostolic authority to teach and preach.
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Hotfrog INDIA provides information regarding Sleekworld in Mumbai Maharashtra. Sleekworld is located at Borivali E, Mumbai Maharashtra 400066 and provides kitchens services. Contact them on 022 64527616 or by visiting them on their website http://www.sleekworld.co.in.
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Full pixels attached :-)
Still WIP, so feel free to feedback.
This app overall is very content heavy, some of the screens are super difficult to keep clean but I have tried to stay true to simplicity :-)
Take a look at any drug-related index and you will see how much data will be stored here.
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Magento - How to close an image
This project received 23 bids from talented freelancers with an average bid price of £25 GBP.Get free quotes for a project like this
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We purchased a Magento template from template monster ,Template no.39194.
When you click on a product image it enlarges the image,
to close the image you need to double click.
Can you amend this so that there is a little cross next to the image that needs to be clicked to close the image instead of double clicking.
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♦ product specifications
|Product name
|FIRST OF THE NORTH STAR century battle Apocalypse PVC Hokuto no Ken VOL.3 collection JUDA No.7 Judah
|FIRST OF THE NORTH STAR century battle Apocalypse figure collection
|Height approx. 100 mm
|Title appearance
|Fist of the North Star
|JAN code
|For more product information
|Fist of the fist century battle Apocalypse figure collection series # 3! Judas appeared.
|* This product is [brand new / unread items] is to hike retail package there is slight damage and fading.
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(C) theory of Wu Zun / Hara, husband /NSP 1983
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Tomato-Crab Bites
7 Sep 2009
Tomato-Crab Bites is a simply delicious mouth-watering recipe. Try this amazingly tempting recipe; I am sure you will get a lot of compliments for this Tomato-Crab Bites .
IngredientsSee In Directions
Blend 1/4 cup low calorie mayonnaise-type dressing, 1 teaspoon lemon juice, 1/4 teaspoon salt, and few drops bottled hot pepper sauce.
Stir in 2 tablespoons chopped green onion and one 7 1/2 ounce can crab meat, drained, cartilage removed, and chopped.
Hollow out 1 pint (25 to 30) cherry tomatoes.
Stuff tomatoes with crab mixture.
Recipe Summary
Course:Side Dish
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Tomato-Crab Bites Recipe


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Five advertising women have established Sandvertising, a collective of advertising professionals, working in conjunction with various established relief groups to help the thousands affected by Hurricane Sandy and to organize resources and trips out to devastated areas.
The initiative was launched on November 6th by Rasha Clark, Executive Producer at Goodpenny; Jenny Karakaya, Freelance Producer, Shirley Ramos, Director of Business Development at Pulse Music; Oritte Bendory, Director of Business Development at GARTNER; and Nancy Kagan, Executive Producer at Republic.
All communications, requests for donations, and volunteering opportunities are coordinated via a dedicated Facebook page: http://www.facebook.com/Sandvertising
"The idea came about when a few of us volunteered the first weekend after the storm, and we realized the need for stronger organization for people wanting to help," explain the Sandvertising founders. "We wanted to act as a resource for others and pass on relevant and timely information. As five women in advertising, we felt that mobilizing the ad industry was where we'd have the biggest reach and impact."
Through personal outreach to ad agencies, production companies, vendors and others, Sandvertising has already enlisted help from various entities, including, BBDO, JWT, Razorfish, Grey, Anomaly, McGarry Bowen, MPC, Imagery Lab, D2 Brands, Uproar and the Associated Press, as well as a network of freelance directors, editors, producers, graphics artists, and designers.
Social media has also had a huge impact on Sandvertising's efforts with the organizers scouring other sites, Twitter and Facebook updates to gather information on where their help is most needed, and then sending out a call to action even to those who don't live in New York or surrounding areas.
Relief efforts to date include "missions" to affected neighborhoods, having a constant presence on the ground to see where the greatest needs are on a daily, if not hourly, basis and coordinating with other organized groups.
One Federal Emergency Management Agency (FEMA) rep comments, "In my 15 years in working with FEMA, I've never seen such an organized and concerted effort from the community to help."
"We've applied our same principles of connecting talent and producing work in advertising to Sandvertising," say the founders. "Our goal is to align volunteers with the work that needs to be done. We've raised money, provided food, collected supplies and clothes, assessed needs, and given many hours of manpower and manual labor."
Sandvertising is currently organizing a toy drive, and hopes to sustain their outreach throughout the winter until those areas affected by Sandy are restored to some semblance of normalcy and the residents have safe living conditions.
"As long as there is a need, we will help in whatever capacity we can," concludes Sandvertising.
This section of Creative Planet Network, "The Wire", contains original press releases issued by various companies and industry organizations. The releases are not reviewed or edited by the editorial staff of Creative Planet Network News. For information and access, forward your name and email address to email@example.com.
Sandvertising: Ad Industry Reps Harness the Power of NY Ad Production Community & Social Media for Hurricane Sandy Relief Efforts2012-11-19 11:29:47
Five advertising women have established Sandvertising, a collective of advertising professionals, working in conjunction with various established relief groups to help the thousands affected by Hurricane Sandy and to organize resources and trips out to devastated areas.
- SMPTE® Hollywood Section to Explore Laser Projection at February Meeting
- Technicolor PostWorks' Sam Daley Replicates Black & White Look for Horror Tale "The Eyes of My Mother"
- VRLA Partners with IEEE VR to Present Academic Track at VRLA
- RTI Strengthens Operations With Four Key Promotions
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In Sunday's (August 2) episode of "True Blood," Lorena (played beautifully by Mariana Klaveno) left us forever in a, shall we say, explosive exit.
Sookie (Anna Paquin) told her she would be the girl to take her out and guess what? She did.
It was a fitting end for the woman who brought Bill (Stephen Moyer) into the vampire fold. But, Lorena has definitely provided a great amount of drama while she was around.
In probably the best Postmortem HBO has produced, the network gives fans a montage of Lorena and Bill's love.
Watch the Ode to Lorena and Bill below:
Will you miss Lorena?
Follow Zap2it and TheRealJethro on Twitter and Zap2it on Facebook for the latest TV, movie and celebrity news.
Video credit: HBO


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Dark finish on maple neck, rim and double bound resonator, bound ebony fretboard, floral inlays, 22 frets, 11'' head, 1 piece flange, 24 brackets, arm rest, no hole flat head tone ring, Presto tailpiece, headstock overlay features floral and logo inlays, geared tuners and 5th string peg, 5th string capo installed, OHSC, EC- (SN:041541019555) Item ID 70U-4161
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The Legal Foundation of Washington is a non-profit created by the Washington Supreme Court to build support for civil legal aid across the state.
Last year was full of surprises, to say the least. And while there has been a lot of change in our country and state, we know that one thing remains constant – the civil legal aid providers of Washington continue to work tirelessly to help low...
Stay up-to-date on what's happening in Washington's civil legal aid community by joining our email list. You will receive periodic updates about events and our bi-monthly newsletter 'The Brief'!
Join us on Friday, February 17th from noon - 1:30pm at the 31st Annual Goldmark Luncheon at the Washington State Convention Center. Your continued help and support fuels justice in Washington.
You're invited to the 31st annual Goldmark Award Luncheon on Friday, February 17, 2017 from noon - 1:30pm at the Washington State Convention Center. We will be honoring legal aid champions Lucy Lee Helm, Paula Boggs, and the University of Washington Tribal Court Public Defense Clinic. REGISTER TODAY!


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David Bowie kicks off the Concert for New York benefit at NYC's Madison Square Garden. AP Photo
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|Publication number
|Publication type
|Application number
|Publication date
|Jun 20, 2000
|Filing date
|Sep 29, 1997
|Priority date
|Sep 29, 1997
|Fee status
|Publication number
|Glenn A. Baxter
|Original Assignee
|Xilinx, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Non-Patent Citations (4), Referenced by (19), Classifications (4), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates to the field of circuit design, and in particular to a system and method for converting programmable logic devices to mask programmed integrated circuits.
Programmable logic devices (PLDs) allow a user to program a device to perform the function of a particular circuit. Examples of PLDs include field programmable gate arrays (FPGAs), erasable programmable logic devices (EPLDs), and complex programmable logic devices (CPLDs). A description of illustrative FPGAs, EPLDs, and CPLDs is provided in "The Programmable Logic Data Book", published by Xilinx, Inc. in 1996, pages 4-11 to 4-65, 3-147 to 3-150, and 3-3 to 3-12.
To use a PLD, a user captures a circuit design using any of several design capture tools. The user then uses software tools to convert the captured design into a device specific bitwise representation. This bitwise representation, also known as the bit stream, programs (configures) the PLD to perform the function of the circuit design. Certain PLDs employ random access memory (RAM) to configure the PLD (i.e. the configuration memory).
Some PLDs allow the circuit designer to utilize portions of the configuration memory as addressable storage elements, i.e. an array of Read/Write memory cells. Such memory cells are referred to herein as "operational memory." This operational memory is distinguished frog the configuration memory used for configuration of the PLD. A detailed description of operational memory is provided in U.S. Pat. No. 5,566,123 issued to Freidin et al. on Oct. 15, 1996 and is incorporated by reference herein.
Typically, PLDs initialize the contents of the operational memory to a set of known values using the bit stream. These values are loaded into the operational memory after the power has been applied, but before the PLD has implemented the particular circuit design. More specifically, certain types of PLDs allow the operational memory to be initialized as the configuration process is occurring. In some instances, a system reset can cause the configuration process to begin again, thereby re-initializing the operational memory.
It is highly desirable to convert PLDs into mask programmed integrated circuits (MPICs), because a substantial cost savings is generally realized. U.S. patent application Ser. No. 08/614,113 entitled "Method and Apparatus for Converting a Programmable Logic Device Representation of a Circuit into a Second Representation of the Circuit", now issued U.S. Pat. No. 5,815,405, assigned to the assignee of the present application, describes a method and apparatus which may be used to convert a PLD to a target technology (such as an MPIC) and is incorporated by reference herein. However, prior art MPICs are not configured using the bitstream which include the initialization bits.
Therefore, a need arises for a system and a method to properly initialize an operational memory in a target technology, thereby ensuring compatibility of the target device in the system for which the PLD was designed. Such a system and method should (i) be equipped to handle PLDs which contain operational memories of varying sizes, (ii) allow the designer to specify certain parameters of the initialization of the operational memory to permit variations in the design, (iii) maintain timing relationships implemented by the PLD to ensure proper operation of the target device, (iv) maintain functional relationships implemented by the PLD to ensure proper functional operation of the target device, and (v) ideally require a very small area overhead on the target device.
In accordance with the invention, a bitstream that configures a PLD is used to generate the initialization logic for the operational memory in a target device. In this manner, the operational memory of the target device functions identically to the operational memory of the PLD. One example of the target device is a mask-programmed integrated circuit (MPIC).
In one embodiment of the invention, to initialize the operational memory in the target device, the initialization bits used to initialize the operational memory in the PLD are identified and extracted. Initialization control logic is generated in accordance with these extracted initialization bits and a set of selectable control circuitry options. In another embodiment of the invention, netlist parameters are used instead of the initialization bits to generate the initialization control logic and/or the data initialization logic.
The selectable control circuitry options advantageously allow the user to specify a plurality of parameters that define how the operational memory is initialized. For example, selectable control circuitry options may include specifying the number of locations in operational memory to be initialized, indicating how many times each location should be initialized with a specified value, or identifying the timing relationships of memory control signals. In certain embodiments, selectable control circuitry options may allow specification of initialization values other than those specified for the PLD.
In accordance with the present invention, data initialization logic is also generated in accordance with the extracted initialization bits. Address control logic is typically customized in accordance with user inputs. The present invention also includes operational circuits for testing of the initialization logic, thereby ensuring that each initialization bit is provided to the correct memory location. A pre-compile representation is built for the target device based on the customized logic.
FIG. 1 illustrates a system in which a PLD is replaced with a new integrated circuit that was created using the initialization data of the PLD.
FIG. 2 shows the circuit initialization and illustrative memory cells in the PLD of FIG. 1.
FIG. 3 is a flow diagram illustrating how to generate operational memory initialization functionality in the integrated circuit of FIG. 1.
FIG. 4 is a block diagram of the memory initialization logic in accordance with the present invention.
FIGS. 5A and 5B respectively illustrate one embodiment of a data generator circuit in accordance with the present invention and one initialization bitstream that customizes that data generator circuit.
FIG. 6 shows one embodiment of an address generator circuit in accordance with the present invention.
FIG. 7 illustrates one embodiment of a control logic circuit in accordance with the present invention.
FIG. 8 is a timing diagram showing the timing relationships of the signals generated to initialize an operational memory.
FIGS. 9A and 9B are respectively a block diagram and timing diagram showing an embodiment of a structure in the control logic circuit that ensures correct mode switching.
FIGS. 9C and 9D are respectively a block diagram and timing diagram showing yet another embodiment of a structure in the control logic circuit that ensures correct mode switching.
FIG. 10 illustrates a line twisting problem which the present invention solves.
FIG. 11 illustrates the combination of two bit streams in light of the line twisting problem shown in FIG. 10.
FIG. 12 illustrates an alternative example of the memory initialization logic.
FIG. 1 illustrates a system 100 in which a PLD 107 is replaced with an integrated circuit (hereinafter IC) 190 designed in accordance with the present invention. IC 190 is described in detail below and particularly in reference to FIGS. 4, 5A, 5B, 6, 7, 9A, and 9C. Both PLD 107 and IC 190 implement a circuit design 106. In the following discussion, PLD 107 refers to the general class of PLDs and is not specifically restricted to a particular type or family of PLDs. Circuit design 106 refers to an actual user design as well as any additional elements necessary to properly implement the function provided by the user's design including, for example, boundary scan and oscillators. System 100 includes a programming circuit 101 which communicates with a device, such as PLD 107, mounted in a programmable logic device site 102. To configure PLD 107 to implement circuit design 106, programming circuit 101 generates and downloads a bit stream 116 to PLD 107 when it is mounted in programmable logic device site 102.
Bit stream 116 includes configuration data that configures a plurality of configurable elements 108. Configurable elements 108 include, for example, function generators, multiplexers, flip-flops, and programmable interconnect points (PIPs). Memory cells 111 store the configuration data on PLD 107. In this embodiment of PLD 107, memory cells 111 include an operational memory 109 which is initialized by circuit initialization 110 in accordance with the bits of bit stream 116. Specifically, in one PLD 107, the memory look-up tables in some of the function generators are used as an array of Read/Write memory cells, i.e. operational memory 109. The "1996 Programmable Logic Data Book" published by Xilinx, Inc. of San Jose, pages 4-14 to 4-20 describes 16�2, 32�1, and 16�1 bit arrays.
FIG. 2 illustrates circuit initialization 110 and memory cells 111 of PLD 107 in greater detail. Specifically, circuit initialization 110 includes an address generator 257 and a data shifter 255. In this example, 12 bits of memory are organized in 2 frames 259 and 260 (Rank 0 and Rank 1, respectively), each frame being 6 bits wide. Typical PLDs employ much larger numbers of memory cells. For example, the Xilinx XC4028EX PLD contains 1567 frames, each frame being 421 bits wide.
Memory cells 111, labeled 111.1-111.12, may be used as configuration memory. Certain of memory cells 111 may be used as operational memory 104. Each of memory cells 111 in the same frame is loaded concurrently. Thus, the memory cells in Rank 0 (frame 259) are loaded in parallel, and then the memory cells in Rank 1 (frame 260) are loaded in parallel. Bitstream 116 is shifted through data shifter 255 until six bits are positioned at data lines D0-D5. Address generator 257, in response to the signal ADDR-- EN, generates an address signal A0 which causes the bits at data lines D0-D5 to be written into the memory cells of frame 259. Bitstream 116 is then shifted through data shifter 255 until the next six bits are positioned at data lines D0-D5. Address generator 257 then generates address signals A1 which causes the bits at data lines D0-D5 to be written into the memory cells of frame 260. Note that the DATA-- EN and the ADDR-- EN signals are generated by PLD 107 by circuit initialization 110 (FIG. 1). The generation of these signals is well known in the art and therefore is not explained in detail herein.
IC 190 includes design implementation logic 103 that also implements circuit design 106. In accordance with the present invention, bitstream 116 is used to design IC 190, i.e. specifically to generate memory initialization logic 105, thereby ensuring that IC 190 implements the functions of circuit design 106 exactly as those functions are implemented in PLD 107. In this manner, because of the high degree of compatibility between IC 190 and PLD 107, the end user need not redesign system 100 when IC 190 is substituted for PLD 107.
Typically, bitstream 116 includes three conceptual parts: a header, data, and a postamble. The header includes a preamble, indicating that the configuration process is beginning, followed by a predetermined bit length count representing the total number of configuration clocks need to complete loading of the data. The data includes the bits which will be loaded into memory cells 111. Finally, the postamble signals the end of the configuration process. The 1991 "Xilinx User Guide", published by Xilinx, Inc., pages 515-543, describes the generation and use of bitstream 116 in the configuration process in further detail.
In accordance with the present invention, bits that initialize operational memory 109 are extracted from bitstream 116 and used to ensure that an operational memory 104 of IC 190 implements the functions of operational memory 109 in PLD 107. Specifically, the extracted bitstream information is used to customize memory initialization logic 105 in IC 190. FIG. 4 illustrates, at a block diagram level, memory initialization logic 105 which includes in part a data generator circuit 420, an address generator circuit 430, and a control logic circuit 440.
FIG. 3 illustrates the steps in customizing memory initialization logic 105. First, the bits that initialize operational memory 109 are identified and extracted in step 310. In a first embodiment, the initialization bits are identified automatically from netlist 301, an example of which is an XNF file generated by a Foundation software package provided by Xilinx, Inc. Specifically, in the XNF file, for example, an initialization parameter INIT precedes the bits to be loaded into operational memory 109, thereby facilitating the extraction of those bits. Note that to optimize layout, operational memory 104 is localized on IC 190. Thus, in this embodiment, all the bits from each XNF block are read out bit by bit. In a second embodiment, the initialization bits are identified from their order in bit stream 116. Because of the complexity of a PLD and thus the corresponding complexity of deriving information from its bitstream, this level of knowledge is for all practical purposes limited to the manufacturer of that PLD. In yet another embodiment, a textual description of the logic in PLD 107 is utilized which contains parameters of the memory initialization. Examples of such descriptions (also called netlists) are the Xilinx proprietary description format for a logic design (XNF file) and an industry standard for specifying logic design in text (ASCII) form (an electronic data interchange format (EDIF) file).
In accordance with the present invention, memory cells are grouped together in width and depth to dramatically improve silicon space utilization. For example, a 32�8 array is three to four times more space efficient than sixteen 16�1 arrays. Therefore, in one embodiment, operational memory cells are grouped together in width and depth. This consolidation may, however, introduce data ordering issues. Specifically, in some situations, one or more address lines in PLD 107 are twisted due to routing. In these situations, the address bits provided on those lines must be reordered to provide the correct initialization order.
For example, referring to FIGS. 10 and 11, assume that a 32�1 RAM is implemented with two 16�1 RAMs, i.e. RAM 1 and RAM 2 (having address bits A0-A3 indicated on the instances of the RAM) and a multiplexer 1000 receiving input signals from the data output terminals DO of RAMs 1 and 2 and providing an output signal DATAOUT. Assume that RAM 1 and RAM 2 are to be loaded with identical bits. However, as noted in FIG. 10, RAM 1 has the address bits logically provided to the corresponding address terminal (i.e. A3 to A3, etc.), whereas RAM 2 has the address bits provided to different address terminals (i.e. A0 to A3, A1 to A2, A2 to A1, and A3 to A0). In other words, a complete swap of address bits would occur in RAM 2.
In typical PLD applications, only a few address bits are swapped, generally to improve routability in the PLD. In these applications, the PLD software that generates the configuration bitstream automatically corrects the bit stream for this address line twisting to ensure that all data bits are provided to their corresponding addresses. Because the present invention consolidates operational memory together, the bit streams for this operational memory must also be consolidated, thereby posing significant challenges if address line twisting is present. Address line twisting can also occur at multiplexer 1000. In this case, which RAM (i.e. RAM 1 or RAM 2) will be used as least significant address may be swapped when combining RAM depth.
Referring specifically to FIG. 11 in which bit streams for RAMs 1 and RAM 2 are combined, right bitstream RB indicates that the bits for RAM 2 are swapped to correct for the address line twisting shown in FIG. 10 (the bitstream for RAM 1 needs no correction because the address bits are provided to the corresponding terminals as previously indicated). The wrong bit steam WB does no bit swapping to compensate for the line twisting, and therefore provides an incorrect combined bitstream. Note that the selection of the signals from output terminals DO of RAMs 1 and 2 may also be swapped by multiplexer 1000. Although FIG. 10 illustrates primarily a depth issue, i.e. the configuration of RAMs 1 and 2 as well as the address bit A4 controlling multiplexer 1000, the line twisting problem applies equally to width issues in the PLD. The present invention swaps bits in the extracted initialization bitstream to compensate for address line twisting, thereby ensuring that each initialization bit is provided to the correct memory location.
Memory initialization control logic is generated in step 330 based on (1) the initialization bits identified in step 310 and (2) control circuitry options provided in step 320. Selectable control circuitry options advantageously allow a user to specify the manner in which operational memory 104 is initialized. For example, the selectable control circuitry options may include:
(a) terminating initialization of operational memory 104 after every location of the memory has been initialized,
(b) initializing each location of operational memory 104 a predetermined number of times,
(c) initializing only selected locations of operational memory 104,
(d) changing the event which causes the operational memory 104 to be initialized, i.e. upon power-on, during a configuration cycle of IC 190, or after a reset has been applied (note that similar to PLD 107, IC 190 needs re-initialization to recover to a known state after power is lost),
(e) writing initialization data to operational memory 104 for a predetermined amount of time,
(f) initiating normal operation of IC 190 upon termination of initialization of operational memory 104, or alternatively, a predetermined amount of time after termination of initialization of operational memory 104,
(g) specifying whether address generator circuit 430 (FIG. 4) which generates addresses for operational memory 104 during initialization is inside or external to IC 190,
(h) specifying whether data generator circuit 420 which generates data values for operational memory 104 is inside or external to IC 190,
(i) specifying the initialization operational values for operational memory 104 to be a read-only-memory (ROM) or combinational logic elements,
(j) specifying the sequence in which address, data and write enable signals are presented to operational memory 104 during initialization (for example, concurrently presenting initialization values to be written to operational memory 104, an address specifying a location to which the initialization bits are to be written, and a write enable signal to enable the writing of the initialization bits to operational memory 104), and
(k) allowing the timing of the address, data, and write enable signals to be presented to operational memory 104 in a different sequence, i.e. defining a timing relationship between the address, data and write enable signals.
As seen from the foregoing description, the selectable control circuitry options advantageously allow a user to specify aspects of the initialization of operational memory 104, thereby further facilitating the replacement of PLD 107 with IC 190. Note that in other embodiments of the present invention, the memory initialization bits are supplemented by netlist parameters provided in step 311 or similar specifications (such as, width and depth of the memory) provided by user directly in step 312.
In step 331, memory initialization data logic is customized based on (1) the initialization bits identified in step 310 or alternatively (2) the initial memory data values for one or more memory locations provided in step 321 (selected by the user in step 312 to initialize specified locations in operational memory 104 of IC 190 with different values than those used in operational memory 109 of PLD 107). Note that in other embodiments of the present invention, the data initialization logic is supplemented by netlist parameters provided in step 311. In step 332, address control logic is customized based on the initial addresses selected in step 332 based on inputs provided by the user in step 312.
Note that steps 320, 321, and 322 specifically allow for direct user-customization of memory initialization logic 105 (FIG. 1). For example, consider a 2�1 memory array, whose bit stream sets the two memory locations to a zero. If a user desires that one of those memory locations be set to one instead, step 310 and/or step 311 would not provide that ability. Therefore, step 321 is advantageously introduced to accommodate setting different data values for the memory. In this manner, step 321 permits the user to customize the data value or values to specific locations within operational memory 104 during the initialization process. Steps 320 and 322 allow for direct user-customization of the initialization control logic and the address control logic in a similar manner. Additionally, step 313 is introduced in accordance with the present invention to provide a means for adding different or additional functionality. This step allows, for example, changing an asynchronous RAM to a synchronous RAM, adding testability logic for system tests, or adding built-in test logic. Note that this logic was not present in PLD 107 and therefore is added by step 313 to IC 190. Steps 312, 313, 320, 321, and 322 are facilitated by a prompt in a computer program or via a file read by a computer program which implements the method of the present invention.
After the memory initialization control logic, memory data initialization logic, and address control logic have been customized, a pre-compile representation for all logic in IC 190 is generated using conventional methods. U.S. patent application, Ser. No. 08/614,113 describes at least one such conventional method.
FIG. 4 illustrates one embodiment of memory initialization logic 105 wherein IC 190 is a mask-programmed integrated circuit (MPIC). In this embodiment, clock generator 410, which forms part of transparent circuits/implementation logic 193 (see FIG. 1), generates a clock signal (CLK) using an oscillator or responding to an external clock (neither shown). In one embodiment, this signal CLK is provided to data generator circuit 420, address generator circuit 430, and control logic circuit 440. Address generator circuit 430 generates initialization addresses (IADDR) in response to signal CLK. Note that in one embodiment the initialization addresses are sequential depending upon the selectable control circuit options specified in step 320 (FIG. 3). In another embodiment, step 320 utilizes a Johnson counter (well known in the art and therefore not described in detail herein) to reduce the number of logic gates required to implement the function. Also in one embodiment, data generator circuit 420 provides initialization data (IDATA) sequentially for each location of operational memory 104 in response to the initialization address (IADDR) generated by address generator circuit 430.
The count enable (CE) signal generated by control logic circuit 440 enables changing of initialization addresses IADDR. In one embodiment described in detail in reference to FIG. 6, address generation circuit 430 generates initialization addresses IADDR by using a binary counter which increments sequentially when enabled by signal CE. In another embodiment (not shown, but also well known), address generator circuit 430 includes a state machine which receives additional inputs to allow non-sequential addressing of operational memory 104.
Control logic circuit 440 generates a memory input selection signal RAMINIT which, in its active state, causes input multiplexer 450 (i.e. data, address, and write enable multiplexers 452, 454, and 456, respectively) to select signals IDATA, IADDR, and IWE to be provided to operational memory 104. The initialization write enable signal (IWE) triggers initialization data signals (IDATA) to be written into operational memory 104. In a preferred embodiment, a comparator 490 compares the data output signals DATAOUT with the data input signals DATAIN to ensure each initialization bit is properly written to operational memory 104. The output signal from comparator 490 is provided to transparent circuits implementation logic 193 to restart the initialization process or to indicate an error in the initialization of operational memory 109. At the completion of initialization, control logic circuit 440 provides the signal RAMINIT which, in its inactive state, causes input multiplexer 450 to select normal memory input signals 470.
Note that additional testing of the signals provided by input multiplexer 450 is provided in one embodiment by operational circuits 199. Because operational circuits 199 are typically implemented with multiplexers, these circuits are preferably placed before input multiplexer 450 as shown in FIG. 4, thereby ensuring optimal speed for the user pathway (i.e. for normal memory input signals 470). However, operational circuits 199 can be placed after input multiplexer 450 in other embodiments. The testing of signals IDATA, IADDR, and IWE in the present invention is extremely important in that known methods of testing the signals associated with operational memory 109 in PLD 107 are unavailable in IC 190. For example, in Xilinx XC4000 series FPGAs, the testing of operational memory 109 is accomplished using the Readback function which is not present in IC 190. This Readback function is described in further detail in the "1996 Xilinx Programmable Logic Data Book", previously referenced.
FIG. 5A shows an embodiment of data generator circuit 420 which generates initialization data signal IDATA on output line 560 based on address input signals A0-A3 (initialization address signal IADDR). Note that in this embodiment, data generator circuit 420 does not receive signal CLK (see FIG. 4) and therefore is asynchronous. Address drivers 530 provide inverted and non-inverted output signals for each address input signal A0, A1, A2, and A3. Additional addresses would result in additional address drivers 530.
AND gates 540 are coupled to certain address drivers 530 in accordance with an illustrative bitstream 116A shown in FIG. 5B. Specifically, AND gates 540 are customized for each IC 190 based on the number of logic 1 bits in initialization bitstream 116A. Thus, because initialization bitstream 116A has nine logic ones, nine AND gates 540 are provided in data generator circuit 420. OR gate 550 receives the terms generated by AND gates 540 and provides initialization data signal IDATA (one bit). Note that this embodiment is for clarity of example only and is not intended to illustrate the possible ways of constructing the logic that one skilled in the art might have at their disposal. In one embodiment, logic 530, 540, and 550 is built by a logic synthesis tool, such as Design Compiler available from Synopsys, Inc. or using the pre-compile representation built in step 340 (FIG. 3). In another embodiment, as selected by selectable control circuitry options 324, signal IDATA may be generated from signals IADDR (A0-A3) by way of a Read-Only Memory which contains initialization bitstream 116A and which is addressed by signals IADDR. Note that in yet another embodiment, signal IDATA may be generated by Boolean logic equations.
FIG. 6 shows an embodiment of address generator circuit 430 which generates a four-bit address A0-A3 (IADDR), thereby allowing addressing an operational memory having up to eight memory locations. Note that address A0 is used to generate operational memory 104 WRITE ENABLE while A1-A3 are used to control operational memory 104 ADDRESS. Address generator circuit 430 implements a conventional four-bit binary counter, which counts when count enable signal CE selects input B of multiplexers 608, and which stops counting and maintains a count when signal CE selects input A of multiplexers 608. D-type flip-flops 602, that can be set or reset by a synchronous or asynchronous S/R input signal, receive input signals from multiplexers 608 and provide those signals as addresses A0-A3 based on signal CLK. If additional initialization bits are identified in bitstream 116, additional logic and flip-flops 602 are provided, thereby increasing the number of addresses. Therefore, address generator circuit 430 is also customized in accordance with the present invention.
FIG. 7 illustrates control logic circuit 440 which receives initialization address IADDR (i.e. signals A0-A4) and generates signals IWE, CE, and RAMINIT. Control logic circuit 440 is customized by providing a wider AND gate 702 for additional addresses (generated by address generator circuit 430). The operation of control logic circuit 440 is explained with reference to the timing diagram of FIG. 8 which shows the relationship of the signals used to initialize operational memory 104. Signal IWE, an active low signal, causes the data at data input terminals DATAIN (FIG. 4) of operational memory 104 to be written to the location indicated on address lines ADDRESS of operational memory 104. Write enable signal IWE is generated at one-half the frequency of clock signal CLK beginning when signal POWER-ON-RESET is active. At power-up of IC 190, signal POWER-ON-RESET is asserted for a predetermined period of time. Signal POWER-ON-RESET feeds a synchronous set input of a flip-flop 704, thereby causing signal CE and RAMINIT to be asserted in the following clock cycle. Initialization address IADDR changes after each positive edge of CLK. Signal RAMINIT, which is generated by flip-flop 710, is a one-half clock cycle delay from the CE signal. Signal IWE is generated by flip-flop 708 whose data input is ANDed by gate 706 which receives signals CE and A0.
Note that the generation of signal CE and RAMINIT must occur in the correct sequence of events to ensure no extra writes are performed on operational memory 104 during the transition of signal RAMINIT from initialization to user mode. In one embodiment, initialization signal RAMINIT DELAY is a delayed RAMINIT signal. FIG. 9A illustrates a delay module 902 which generates initialization signal RAMINIT. FIG. 9B shows a timing diagram of the signals associated with the circuitry of FIG. 9A. Referring to both figures, delay module 902 delays signal RAMINIT being provided to multiplexers 452 and 454, but not to multiplexer 456. To prevent unwanted write operations to operational memory 104, multiplexers 452, 454, and 456 must continue to select initialization data and addresses during the final pulse of signal IWE. Thus, the delay generated by delay module 902 must be sufficient to prevent selection by data and address multiplexers 452 and 454 of user input signals 470 until after occurrence of the final pulse of signal IWE.
FIG. 9C shows another embodiment of the present invention in which unwanted writes to operational memory 104 are prevented by direct control of write enable signal IWE. Specifically, control logic circuit 440 generates a hold signal WE-- HOLD-- OFF which is provided to OR gate 902. OR gate 902 receives the signal from the output of control logic 456 at its other input terminal. During memory initialization, the RAMINIT signal chooses the IWE input of control logic multiplexer 456. Thus, the output signal of gate 902 is disabling, i.e. logic one, if either signal IWE or signal WE-- HOLD-- OFF is high. As shown in the timing diagram of FIG. 9D, hold signal WE-- HOLD-- OFF is asserted high before initialization signal RAMINIT switches multiplexer 456 to select user inputs 470, but only after the final pulse of signal IWE. Signal WE-- HOLD-- OFF is held asserted high to prevent write cycles until the initialization sequence is completed and operational memory 104 is available for operation, at which time WE-- HOLD-- OFF is released (set low).
FIG. 12 illustrates another embodiment of memory initialization logic 105. In this embodiment, circuit initialization 110 is mostly reproduced. FIG. 2 shows the logical organization of memory cells 111. FIG. 12 shows address generator 257 and data shifter 255 from FIG. 2. Address generator 257 generates a decoded address signal such that each address within the frame (e.g. frame 260) is individually decoded. Similarly, data shifter 255 shifts the data from the data portion of bit stream 116 until it contains a full frame of data. Frame counter 1210 and frame decoder 1220 provide additional decode such that each frame is uniquely identified. This embodiment allows the exact decode for any bit in the data section of bit stream 116. The exact decode allows for the building of a sum-of-products logic generation for the IDATA path. Note that FIG. 12 does not show the control logic required to address and control operational memory 104. This circuitry will be similar to that shown in FIG. 4 and is therefore not described in detail.
It is to be understood that the specific mechanisms and techniques which have been described are merely illustrative of one application of the principles of the invention. Numerous modifications may be made to the methods and apparatus described herein without departing from the true spirit and scope of the invention.
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|Partial reconfiguration of a programmable logic device using an on-chip processor
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|Reconfiguration of a programmable logic device using internal control
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|Altera Corporation
|Method of creating a mask-programmed logic device from a pre-existing circuit design
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|Sedna Patent Services, Llc
|Method and apparatus providing remote reprogramming of programmable logic devices using embedded JTAG physical layer and protocol
|Apr 7, 2005
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|Reconfiguration of a programmable logic device using internal control
|Nov 16, 2004
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|Routing with derivative frame awareness to minimize device programming time and test cost
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|Lsi Logic Corporation
|Verification of RRAM tiling netlist
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|Dec 5, 2005
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|Altera Corporation
|Method and apparatus for compiling programmable logic device configurations
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|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Sep 29, 1997
Owner name: XILINX, INC., CALIFORNIA
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text:
the subject they dont want us to talk about
source: http://www.dailymail.co.uk/news/article-2896986/Prince-Andrew-s-sex-slave-nightmare-deepens-Duke-faces-fresh-wave-lurid-claims-sex-underage-girl-Virginia-Roberts-plans-tell-memoir-alleged-
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Jack Nicholson sinks teeth into acting role
behind the scenes potatocam footage from the making of Wolf
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Illuminati Bloodline Relations (Organized Crime Family Ties The Video) Truthtrekker
The 1% are all related, all doing the incest and all getting you to follow them into death. The Keys to Eternal Life in this World Are Simple: NO WORSHIP, NO SLAVES! The Book of Life, Transcrib
By: nature_4_life | Comments: 4 | Views: 990 | Votes: 0 | Shared: 0
Location: New Jersey, United States | Leaked: Feb-14-2014 in Conspiracy
A King's Welcome Home
Muchos smooches on the tarmac for Moroccan King Mohammed VI
By: TheSanityInspector | Comments: 26 | Views: 1176 | Votes: 1 | Shared: 0
Location: Fes, Fes-Boulemane, Morocco | Leaked: Sep-25-2013 in Other Middle East, Other Entertainment, Propaganda
Muslim Brotherhood created by British Intelligence
Muslim Brotherhood created by British Intelligence Dr. John Coleman, a former British Intelligence agent...states in his report on Iran's Islamic Revolution that the Muslim Brotherhood was crea
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Location: United Kingdom (UK/GB) | Leaked: Aug-21-2013 in Conspiracy
Obama Princesses now headed to the Bahamas
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Leaked: Mar-26-2013 in Other News, Politics
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Prince Harry RUNS for Ice-Cream Truck in Afghanistan!
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British Rulers Sue Over Pictures Of Kates Saggy, Floppy, Terrible, Lopsided, Titties...France Surrenders.
http://www.guardian.co.uk/uk/2012/sep/18/kate-william-win-battle-topless-photos Kate and William win first round in battle over topless photos French magazine Closer banned from further use o
By: VikingRapeSquad | Comments: 69 | Views: 17177 | Votes: 0 | Shared: 276
Location: United Kingdom (UK/GB) | Leaked: Sep-18-2012 in Other News, Sexy
Rightful Heir' to British Throne Dies
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PEASANT LOVING INBRED SCUM (FKN Newz)
The monarchy is an "ignoble affront to equality and humanity". You monarchists are "Steaming dullards". You are "the pillars upon which the monarchy rests. Without you they'd stand naked
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Leaked: Jun-3-2012 in Other
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This Sigma lens case is fully fitted, padded, and designed specifically to house the Sigma 15mm Fisheye EX, Sigma 15mm Fisheye EX DG, Sigma 4.5mm EX DC and Sigma 10mm EX DC lenses. It is an identical replacement for the pouch originally supplied with the lens.
Wex Photographic is a trading name of Warehouse Express Limited (registered as company no. 03366976).
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text:
Uneasy lies the head that wears the crown, and all that.
And all the more so if that head is travelling on Ryanair, as David Cameron did last week, we can safely assume. It's the budget airline that makes you pay extra for breathing space, let alone a padded headrest to drift off on. In fact, the only head that seems to be resting easily right now is that of Ed Miliband, whose aides were caught removing the first class paraphernalia from his train seat shortly before he gave a TV interview from its cosy embrace.
What fools they both take us for. Of course politicians travel first class; we in steerage know this better than anyone else. It's not like you ever spot any of them crammed in there among the screaming children and crates of chickens. It's as if, with the close of the swishy doors and the rumble of the complimentary drinks trolley, there comes a certain childlike naivety – like the conviction that no one will know if you stick your finger in the immaculate chocolate icing of a freshly made cake and then vigorously deny it. We know, Ed – but you're the one making a fuss about it.
And likewise, we know that the Camerons fly Ryanair only to redirect their nosediving popularity ratings. Their visceral distaste once installed in their seats must have been quite the thing to behold: David trying to avoid putting his Church's loafers in the sticky patch on the floor, Samantha trying to decide whether a Twix or a tub of Pringles was more worth the £4 they ask for them.
Bring back the good old days, when the pretending was half-hearted, to say the least. Remember when Tony and Cherie announced they were staying at a pal's house for the summer? The pal turned out to be Cliff Richard and the house was a mansion in Barbados. And when Mandy went out on a pedalo for the day? It was a yacht owned by Lord Rothschild, followed by a stay in his secluded hilltop villa.
But Ed's removal of his controversial antimacassar is indicative of the piety that has overwhelmed the political sphere now that the good old days have turned sour. And, like most piety, it's as empty and resonant as the public coffers. It's the ultimate embodiment of "Do as I say, not as I do".
With those in Westminster decrying our spending and our reliance on debt, there is a general movement toward Lutheran thriftiness of the sort that involves a hair shirt and sleeping on a stone floor. (Needless to say, they're all wrapped in silk and eiderdowns.) We must suffer, they imply, before it all gets better again; we must forgo our creature comforts and the extra log on the fire, because this is the time for belt-tightening.
Which is why it sticks in the craw. Not, as you would first assume, to see George Osborne and family jetting off to Klosters – oh no! At least Gideon knows we wouldn't be fooled by the sight of him in the Ryanair queue; we'd assume he was heading to the Silverjet parked behind it. No, what is more galling beyond expression is when we see politicians politely sidestepping the penury they impose on us while pretending they're not. Cameron's self-imposed budget flight is a drop in the ocean, while Miliband's egregious self-editing is simply annoying. They should just admit to being in a position fortunate enough to be able to live well and travel in luxury. Why pretend? If the country really is going to hell, at least it's in a plush handcart. And, of course, all these first class tickets are doubtless being claimed on expenses anyway.
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text:
Panda Security Announces Panda Adaptive Defense
Security professionals responsible for enterprises around the world can view the status of hundreds, even thousands of endpoints in real-time.Panda Security announced the launch of Adaptive Defense, a cloud-based solution that provides endpoint protection against Advanced Persistent Threats (APTs), the ransomware Trojan CryptoLocker, and targeted attacks in enterprise environments. APTs are next generation malware that use sophisticated strategies, such as multiple simultaneous attacks over an extended period of time with the primary objectives of industrial espionage or data theft. Adaptive Defense's remediation services and ability to incorporate into the customer's existing security infrastructure offer an enterprise solution against nearly all types of malware. "Traditional anti-malware is still necessary but it is increasingly ineffective. Companies must assume that they are already compromised," Josu Franco, vice president of business development at Panda Security, told eWEEK. "Many new security companies are addressing this problem with investigation tools, which need skilled personnel to run the investigations and remediate incidents. With Adaptive Defense, we are providing a solution, which reduces the impact on IT and the requirement for skilled personnel. Adaptive Defense uncovers threats that are missed by the incumbent anti-malware product, transparently for the admin, with integrated remediation and without the need to perform manual investigations."
Security professionals responsible for enterprises around the world can view the status of hundreds, even thousands of endpoints in real-time, as well as manage all settings from a single Web console.
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