text:
Optimal leverage from non-ergodicity
In modern portfolio theory, the balancing of expected returns on investments against uncertainties in those returns is aided by the use of utility functions. The Kelly criterion offers another approach, rooted in information theory, that always implies logarithmic utility. The two approaches seem incompatible, too loosely or too tightly constraining investors' risk preferences, from their respective perspectives. The conflict can be understood on the basis that the multiplicative models used in both approaches are non-ergodic which leads to ensemble-average returns differing from time-average returns in single realizations. The classic treatments, from the very beginning of probability theory, use ensemble-averages, whereas the Kelly-result is obtained by considering time-averages. Maximizing the time-average growth rates for an investment defines an optimal leverage, whereas growth rates derived from ensemble-average returns depend linearly on leverage. The latter measure can thus incentivize investors to maximize leverage, which is detrimental to time-average growth and overall market stability. The Sharpe ratio is insensitive to leverage. Its relation to optimal leverage is discussed. A better understanding of the significance of time-irreversibility and non-ergodicity and the resulting bounds on leverage may help policy makers in reshaping financial risk controls.
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|Date of creation:
|Feb 2009
|Date of revision:
|Aug 2010
|Publication status:
|Published in Quant. Fin., Vol. 11, Issue 11, 1593--1602, 2011 (open access)
|Contact details of provider:
| Web page: http://arxiv.org/
References listed on IDEAS
Please report citation or reference errors to , or , if you are the registered author of the cited work, log in to your RePEc Author Service profile, click on "citations" and make appropriate adjustments.:
- J. Tobin, 1958.
"Liquidity Preference as Behavior Towards Risk,"
Review of Economic Studies,
Oxford University Press, vol. 25(2), pages 65-86.
- James Tobin, 1956. "Liquidity Preference as Behavior Towards Risk," Cowles Foundation Discussion Papers 14, Cowles Foundation for Research in Economics, Yale University.
- Merton, Robert C. & Samuelson, Paul A., 1974. "Fallacy of the log-normal approximation to optimal portfolio decision-making over many periods," Journal of Financial Economics, Elsevier, vol. 1(1), pages 67-94, May.
- Markowitz, Harry M, 1976. "Investment for the Long Run: New Evidence for an Old Rule," Journal of Finance, American Finance Association, vol. 31(5), pages 1273-1286, December.
- Allan G. Timmermann, 1993. "How Learning in Financial Markets Generates Excess Volatility and Predictability in Stock Prices," The Quarterly Journal of Economics, Oxford University Press, vol. 108(4), pages 1135-1145.
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text:
|Publication number
|Publication type
|Application number
|Publication date
|Sep 15, 2009
|Filing date
|Jun 30, 2005
|Priority date
|Sep 13, 2004
|Fee status
|Also published as
|Publication number
|James Aweya, Delfin Y. Montuno, Michel Ouellette, Kent Felske
|Original Assignee
|Nortel Networks Limited
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (13), Non-Patent Citations (1), Referenced by (10), Classifications (6), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to and claims the benefit of U.S. Provisional Application No. 60/609,477, filed Sep. 13, 2004; U.S. Provisional Application No. 60/609,478, filed Sep. 13, 2004; U.S. Provisional application No. 60/630,550, filed Nov. 23, 2004; and U.S. Provisional Application No. 60/674,231, filed Apr. 23, 2004, and is also related to U.S. Patent Application entitled Method And Apparatus For Synchronizing Clock Timing Between Network Elements, filed on even date herewith. The content of each of these provisional and utility applications is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to communication networks and, more particularly, to a method and apparatus for synchronizing the internal state of frequency generators on a communications network.
2. Description of the Related Art
Data communication networks may include various computers, servers, nodes, routers, switches, hubs, proxies, and other devices coupled to and configured to pass data to one another. These devices will be referred to herein as "network elements." Data is communicated through the data communication network by passing data over an established circuit or by packetizing the data and routing the data packets between a series of network elements over the network.
There are two basic types of networks—Time Division Multiplexed (TDM) networks and packet networks. These two networks differ in how signals are separated on the physical medium. In a TDM network, the network elements rely on time to determine which signals belong to which connection, whereas in a packet network the packets are individually addressed in a manner that is able to be understood by the network elements. Since TDM networks rely on time to divide signals between multiple logical channels, timing requirements of TDM networks are relatively stringent. In a packet network, by contrast, timing is less important since each packet of data is self-contained and is able to specify to the network its size and other associated parameters. Since timing is not as important on a packet network, the network elements on a packet network are generally not synchronized. Hence, packet networks are generally implemented as asynchronous networks.
TDM networks are synchronous in nature. Consequently, the equipment connected to a TDM network has to be synchronized to it in some manner. In a TDM network, a timing distribution network typically will link the TDM nodes to provide a synchronization signal that is traceable to a Primary Reference Source (PRS). Networking synchronization is derived from the PRS and distributed through a hierarchy of network nodes with lesser stratum clocks. An alternative timing solution is to maintain a distributed PRS architecture, where for example, each TDM node is timed from an accurate timing source, such as a PRS/Stratum 1 clock, Global Positioning System (GPS) based clock, or a standalone accurate clock (e.g., H Maser, Cesium, Rubidium, etc.). The particular timing requirements on a service interface depend on the services (T1, E1, T3, E3, etc.) carried over the network, which are typically specified in a standard promulgated for that particular service type.
Timing signals in a synchronous network are used by the physical interfaces of the network elements to put data on the transmission media, and to extract data from the media. In other words, clocking at the physical interface of a network element controls the speed at which data is transmitted on the physical connection. Typically, to accommodate minor transmission jitter, a de-jittering or elastic buffer is implemented at the receiver. The arrival rate and the departure rate from the buffer are controlled, respectively, by the transmitter clock and the receiver clock. If the physical interfaces on a connection are not synchronized (not driven by a clocking signal of identical frequency), data can be lost due to buffer overflow or underflow, resulting in periodic line errors.
As packet technology has increased in reliability and sophistication, the cost of deploying packet-based networks such as Ethernet networks and Internet Protocol (IP) networks has dropped to the point where it is often cheaper to deploy a packet network than to deploy a TDM network. To take advantage of the lower costs of packet network technology, service providers have sought to implement a packet-based core network intermediate existing TDM networks. To allow a packet network to carry TDM traffic, the packet network must essentially behave as a transparent "link" in the end-to-end connection. The transparent inclusion of a packet network in an end-to-end path of a connection that carries circuit-switched time sensitive traffic is commonly referred to as "circuit emulation" on the packet network.
The non-synchronous nature of the packet network and the packetizing and depacketizing processes used to format the data for transmission over the packet network all contribute to increased jitter and delay in the transmission of traffic, which makes synchronization of the different TDM networks and network elements on these TDM networks difficult. Additionally, while packet networks are able to carry traffic between the end TDM networks, they do not naturally carry clock information due to their asynchronous nature. Thus, to enable TDM traffic to be carried over a packet network, it is necessary to have the end systems directly exchange clock information to allow the data ports on the network elements to be synchronized and to allow the different networks to be synchronized.
To overcome the inherent non-synchronous nature of a packet network, a network element or a downstream terminal mode may use an adaptive timing technique to reconstruct the timing signal of the upstream TDM terminal. In an adaptive clocking technique, the TDM receiver derives an estimate of the transmitter clock from the received data stream. This is commonly done using a phase-locked loop (PLL) that slaves the receiver clock to a transmitter clock. The slave PLL is able to process transmitted clock samples encoded within the data stream, or process data arrival patterns, to generate timing signals for the receiver. The purpose of the slave PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock.
Several adaptive timing techniques have been developed, including extracting clock information from arrival patterns over the network, observing the rate at which the buffers are being filled, and using encoded timing signals transmitted from the upstream terminal to the downstream terminal across the packet network. One example of the use of encode timing signals (timestamps) is described in U.S. patent application Ser. No. 10/076,415, entitled "Technique for Synchronizing Clocks in a Network", the content of which is hereby incorporated by reference. Although several of the developed techniques are relatively good at transmitting clock signals on the network, it would still be advantageous to find a way to transmit better clock information across the network, and to find a way to use a less complicated circuit than a PLL to implement the slave clocks.
The present invention overcomes these and other drawbacks by providing a method and apparatus for synchronizing network elements. According to an embodiment of the invention, a master clock is implemented as an all digital phase locked loop. The loop filter output is used to control a Digitally Controlled Frequency Selector (DCFS). The output of the loop filter is also sampled and periodically transmitted to slave clocks to allow the slave clocks to emulate the state of the master clock. The slave clocks, in this embodiment, use the transmitted information as an input to directly control their output frequency to match the output frequency of the master DCFS. The DCFS may be implemented as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).
Where the master clock is implemented using a DCO as the DCFS, the slave clocks will also be implemented using DCOs. In the master clock, error signals are generated by a Phase Frequency Detector (PFD) and then processed by a loop filter to form a filtered error signal that is combined with a nominal control word to form a DCO control word. The DCO control word is in turn used to control the local DCO and the remote DCOs. Where the master clock is implemented using a DDS as the DCFS, the slave clocks will also be implemented using DDSs. The control word that is used to set the frequency of the master DDS is also transmitted to the slave DDSs, and used by the slave DDSs to cause the slave DDSs to generate the same frequency as the master DDS.
According to another embodiment of the invention, to ensure that the local oscillators in the slave DCFSs are oscillating at the same frequency as the master local oscillator, the slave local oscillators are formed as voltage controlled oscillators and a feedback loop is used to synchronize the slave local oscillators with the master local oscillator. In one embodiment, time stamps are used to transmit state information from the master local oscillator to the slave local oscillators so that the slave local oscillators may replicate the frequency of the master local oscillator to eliminate any long term drift of the slave local oscillator relative to the master local oscillator.
Aspects of the present invention are pointed out with particularity in the appended claims. The present invention is illustrated by way of example in the following drawings in which like references indicate similar elements. The following drawings disclose various embodiments of the present invention for purposes of illustration only and are not intended to limit the scope of the invention. For purposes of clarity, not every component may be labeled in every figure. In the figures:
The following detailed description sets forth numerous specific details to provide a thorough understanding of the invention. However, those skilled in the art will appreciate that the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, protocols, algorithms, and circuits have not been described in detail so as not to obscure the invention.
First Level Control—Exchange of Control Words
In operation, the master clock PLL locks onto an external reference clock 24 by adjusting a control word input to the DCFS. The control word that is used by the master DCFS is transmitted via packets 12 across the network 10 to the slave clocks 18. The slave clocks extract the control word via processor 26 and use that as the new input to the slave DCFS 22. In this way, the same control word that has been derived from the master clock DCFS may be used to replicate the output frequency in the DCFSs forming the slave clocks. By periodically transmitting the control words from the master clock to the slave clocks, the slave clocks can be made to track operation of the master without requiring the slave clocks to be implemented as phase locked loops.
Communication between the master clock and the slave clocks over the packet network can be done in-band, for example by transmitting clock state samples with or without user data, or out-of-band, for example by using a separate physical or logical communication channel, for example, using Real Time Control Protocol (RTCP). The invention is not limited to the particular manner in which the DCFS control word is transmitted from the master clock 16 to the slave clocks 18 or the particular protocols or other technologies involved in the transportation of the control word from the master clock to the slave clocks. Additionally, although only one master and a plurality of slaves have been shown, in a practical embodiment multiple network elements would take place in the clock synchronization scheme, and the invention is not limited to the example network architectures shown in
Two examples of a DCFS that may be used in connection with embodiments of the invention will be described in greater detail below. The first example will describe an embodiment in which the DCFS is formed as a digitally controlled oscillator (DCO), and the second example will describe an embodiment in which the DCFS is formed as a Direct Digital Synthesizer (DDS). The invention is not limited to these two particular structures as other types of digitally controlled frequency selectors may also be used to enable synchronization between the master and slave clocks to occur by transmission of a control word to specify an operating frequency of the slave clocks.
Master Clock
A Phase Locked Loop (PLL) is one of the basic building blocks commonly used in frequency synthesis. A PLL can be constructed using analog technology, using a combination of analog and digital technology, and using only digital technology. As used herein, the term all-digital PLL (ADPLL) will be used to describe a PLL in which all of the signals within the system are digital values; no analog voltage signal is used anywhere in the system. Since analog PLLs are susceptible to temperature variations, DC drift, and numerous other factors, it is preferable to implement the master clock as an ADPLL.
A PLL receives as an input a reference signal (reference clock 24 in
As shown in
The master clock 16 may also include a clock selector 74 to allow the input reference frequency to be obtained from a plurality of different available sources. For example, the master clock may have access to a clock signal generated by a GPS clock, a BITS, line-timed clock signal, or a free-running oscillator.
The comparator 32, 42, compares the input reference clock 24 with the current output (the synthesized clock signal) of the master clock 44 (also referred to as the synthesized clock) and generates an error signal 46. The error signal 46 represents the difference between the reference clock 24 and the synthesized clock 44 signals. The error signal 46 is filtered by a loop filter 34 and combined with a nominal control word 48 to form an input 50 to the Master local DCFS (or DCO 52 or DDS 54). The nominal control word 48 allows the frequency of the DCFS to be set to a frequency close to the input reference frequency 24 and the error signal 46 adjusts the output 44 of the DCFS 36 to lock the synthesized clock 44 onto the reference clock 24.
To enable the slave clocks to operate at the same frequency as the master, the slave clocks are provided with the same input 50 as is provided to the master DCFS 36. This may be done by transmitting the nominal control word 48 to each of the slave clocks 18 and periodically transmitting a control word formed from the filtered error signal 56 to the slave clocks, or by transmitting the control word 50 formed from combining the filtered error signal 56 with the nominal control word 48 to the slave clocks.
To allow the master clock 16 to interwork with slave clocks that configured to implement a timestamp based scheme, rather than the clock synchronization scheme described herein, the master clock may also include a counter to allow the master clock to generate explicit time indications or timestamps that can then be transmitted to the slave clocks to allow the slave clocks to synchronize their local clocks to the master clock.
A digitally controlled oscillator (DCO) is a frequency synthesizer that takes a digital control word 50 as input and generates a corresponding frequency 44. According to one embodiment of the invention, the DCFS may be formed as a DCO. An example of this embodiment is illustrated in
The PFD 42 samples and compares the input reference signal fref 24 with the reconstructed reference (or synthesized clock) fT 44 to produce digitized error samples 46 which are proportional to their phase and frequency differences. The samples are filtered by a digital filter (loop filter 34) and corresponding output samples 56 are used to control the period of the DCO. The output of the loop filter is used to correct the phase and frequency of the DCO by changing the frequency of the DCO for the next clock period in an appropriate direction. If the loop is designed properly, the reconstructed reference fT will be forced to resemble the input reference signal fref. The PFD is described in more detail below in connection with
The PLL control section 58 generated the DCO input from the error signal 46 generated by the PFD 42 and the nominal DCO control word 48, which may be set depending by the network operator depending on the desired output frequency from the DCO. At sampling instant n, the error signal e(n) 46 produced by the PFD 42 is processed by the loop filter 34 F(z) to obtain the correction factor Ncorr(n) 56 (which could be positive or negative quantity). This correction factor is then subtracted at subtractor 60 from the nominal DCO control input Nnom 48 (which corresponds to the nominal system frequency fnom) to obtain a DCO control word NDCO(n) 50. A detail model of the DCO and the loop filter design is given below. Note that the nominal control word Nnom 48 can be set to any desired value depending on system requirements.
The loop filter output Ncorr 56 (or alternatively, the DCO input, NDCO 50) is sampled periodically, for example between about 1 and 20 times per second, and the sampled value is then transmitted to the slave clocks 18 to allow them to emulate the state of the master clock. Transmission of the filtered error signal Ncorr 56 may require fewer bits than transmission of the DCO input 50, since the filtered error signal is likely to be a smaller value than the DCO input which is a combination of the filtered error signal and the nominal DCO control word. Also, since the nominal DCO control word may be known at the slaves, transmission of this component of the input signal may be unnecessary.
Operation of the DCO is illustrated in
If the DCO is operating with a control input Nnom 48, which corresponds to the nominal frequency fDCO=fnom=1/τnom, adding a negative quantity −Ncorr to Nnom results in an increase in the frequency of the output 44 (since the counter has to count fewer pulses from the local oscillator), τDCO=(Nnom−Ncorr)τo, whereas adding a positive quantity +Ncorr to Nnom results in a decrease in the frequency of the output 44, τDCO=(Nnom+Ncorr)τo. Thus, by appropriately controlling the correction factor Ncorr 56 added to Nnom 48, the output frequency of the DCO fDCO=1/τDCO can be controlled accordingly.
Another implementation of the DCO is shown in
Frequency quantization is an important consideration in the design of a digital loop, especially since this quantity can be a limiting factor in the performance of a practical implementation.
For small quantization errors, fo>>fnom, where fnom=1/τnom is the nominal frequency of operation (e.g., 1.544 MHz for a T1 link), the phase error which may occur in the DCO due to frequency quantization is
For small quantization errors, for example, Δφ≦7.2� requires that Nnom≧50.
Between samples, the phase error changes in a linear manner at a rate proportional to the difference between the input frequency and the DCO frequency. Since the loop averages two frequencies, one of which could be qf Hz from the input frequency, a phase change of
Δφ=2πqfTs, (3)
can occur between samples, where Ts is a sampling interval. Given that Δφ/2π=fnomτo, the quantization increment qf can be expressed as
A DCO has an inherent stability equal to that of the input high-speed oscillator. If the high-speed oscillator has a frequency range of fo�Δfo, and normalized error �Δfo/fo (which is usually expressed in parts per million, (ppm)), then for a DCO input word Nnom, the output clock will have a corresponding frequency range
The error range of the output frequency is scaled accordingly by a factor of NDCO and is equal to
but the normalized error range stays the same as that of the high speed oscillator, i.e.,
Thus, the stability of the high-speed oscillator is an important factor to the overall stability of the DCO.
Several advantages of using a DCO for frequency synthesis include numeric frequency tuning, much faster tuning speed, very high tuning range, low phase noise dependent on the frequency ratio Nnom, very high frequency resolution dependent on the frequency ratio Nnom, excellent short and long term stability, highly linear frequency tuning range, and low cost and low complexity. However, the DCO will exhibit relatively high quantization noise if the value of Nnom is too small.
A master (or slave) clock has an inherent stability equal to that of the input high-speed oscillator at the master (or slave) clock. If the high-speed oscillator at the master (or slave) clock has a frequency stability of x ppm, the master (or slave) clock will also have a corresponding frequency stability of x ppm. For the clock synchronization scheme to be stable and accurate, the DCOs will require reasonably stable high-speed oscillators. Thus, the clock accuracy at a slave clock has an inherent stability equal to that of the input high-speed oscillators at the slave and master clock. If the high-speed oscillators at the master and slave clocks have frequency ranges of fo�Δfom and fo�Δfos, respectively, then for a given DCO control word NDCO generated by the master ADPLL, the slave clock will see a corresponding frequency range that embodies the error ranges �Δfom/NDCO and �Δfos/NDCO. For the clock synchronization scheme to be accurate, the DCOs will require reasonably stable high-speed oscillators depending on the application. A method and apparatus for implementing a second level control, in which the local high frequency generators of the master and slave DCOs may be synchronized, is discussed in greater detail below in part two hereof.
As shown in
If fref=fT but there is a phase difference between REF and DCO, as shown in
For example, assume that the PFD is in the {UP=0 and DOWN=0} state initially. If fref=fT and there is zero phase error between REF and DCO as shown in
Since the output signal of the PFD depends on the phase error in the locked state of the DPLL and on the frequency error in the unlocked state, a DPLL which uses a PFD will lock under any condition, irrespective of the type of loop filter used.
Assume now that the reference clock period is quantized (by the high-speed clock with frequency fos=1/τos) into M=Max steps, i.e., Max=τnom/τos. Note that the high-speed clock driving the PFD may be different from that driving the DCO. If the two clocks are equal, i.e., fos=fo, then Max=Nnom. The UP-DOWN counter is a binary counter of certain size whose upper limit can be denoted as Max. The counter operates at the speed (or multiple) of the high-speed DCO. It counts up or down, initially from zero, at every high-speed clock tick until it reaches Max−1, and then it will roll over and start again. The value stored in the counter is latched out by the active rising edge of the reference clock REF. Therefore, when the DCO is frequency locked to the reference clock, the counter value should be a fixed number (see
The D-type flip-flops 80 are triggered by the positive-going edges of inputs, REF and DCO, to the PFD. Initially, both outputs are low. When one of the PFD inputs rises, the corresponding output becomes high. The state of the finite-state machine 90 of
Two important observations may be made from the waveforms shown in
To illustrate this,
The slope of the PFD characteristic curve shown in
When the phase error is restricted to the range −2π<θe<2π, the counter output becomes
To interface with the loop filter, the PFD is implemented as follows (see
Under normal circumstances (typical applications), the DCO and the PFD will be driven by the same high-frequency oscillator fo. In this case, the high-frequency oscillator is selected to have a frequency of fos=fo=Max.fnom=Nnom.fnom. With this, the counter for both PFD and DCO will have the same maximum values.
In a practical implementation, to allow for the loop filter to be implemented in software on a processor, the inputs REF and DCO may be divided down to 8 KHz (or even 4 or 2 KHz) frame rates and fed to the PFD, as shown in
Where the inputs are divided by X before being fed to the PFD, the input REF and DCO frames would not necessarily be aligned initially before entering the PFD. An example of this is illustrated in
According to an embodiment of the invention, values obtained from the PFD are converted into error values meaningful for adjusting the DCO frequency. The error values may be obtained such that the conversion allows the initial misalignment error Coffset shown in
if offset_case == left_of_max/2 if C(n) <= Coffset then e(n) = −(Coffset − C(n)) /* slow down DCO */ else if C(n) > Coffset + Max/2 then e(n) = −(Max − C(n) + Coffset) /* slow down DCO */ else e(n) = C(n) − Coffset /* speed up DCO */ if offset_case == right_of_max/2 if C(n) > Coffset then e(n) = C(n) − Coffset /* speed up DCO */ else if C(n) < Coffset − Max/2 then e(n) = Max − Coffset + C(n) /* speed up DCO */ else e(n) = −(Coffset − C(n)) /* slow down DCO */ if offset_case == on_zero if C(n) > Coffset + Max/2 then e(n) = −(Max − C(n) + Coffset) /* slow down DCO */ else e(n) = C(n) − Coffset /* speed up DCO */ if offset_case == on_max if C(n) < Coffset − Max/2 then e(n) = Max − Coffset + C(n) /* speed up DCO */ else e(n) = −(Coffset − C(n)) /* slow down DCO */
Consolidated Algorithm:
if C(n) < Coffset − Max/2 then e(n) = Max − Coffset + C(n) /* speed up DCO */ else if C(n) <= Coffset then e(n) = −(Coffset − C(n)) /* slow down DCO */ else if C(n) > Coffset + Max/2 then e(n) = −(Max − C(n) + Coffset) /* slow down DCO */ else e(n) = C(n) − Coffset /* speed up DCO */
Further Consolidation for Interpreting C(n) (Lines 2 & 4 Above Consolidated):
if C(n) < Coffset − Max/2 then e(n) = Max − Coffset + C(n) /* speed up DCO */ else if C(n) > Coffset + Max/2 then e(n) = −(Max − C(n) + Coffset) /* slow down DCO */ else e(n) = C(n) − Coffset /* speed up if C(n) > Coffset and slow down if C(n) <= Coffset */
Processing of Phase Count Values to Obtain Error Values:
if C(n) < Coffset − Max/2 then
e(n) = Max − Coffset + C(n) /* speed up DCO */
else if C(n) > Coffset + Max/2 then
e(n) = −(Max − C(n) + Coffset) /* slow down DCO */
else e(n) = C(n) − Coffset /* that is speed up if C(n) >
Coffset and slow down if
C(n) < Coffset */
With this pseudo code, it is possible to generate the error signal e(n) that can be used to control the DCO 52 in the master clock PLL 30 to adjust the output frequency of the DCO 52. As shown in
Depending on the PFD sampling frequency, the low-pass filter can be implemented in software on a processor which controls the DCO. The processor computes the DCO control word NDCO by using the output from the PFD.
The acquisition mode, with faster response, is used to bring the ADPLL into synchronism with the reference. This faster response is necessary initially, and each time after an extended free-run period, whenever the DCO clock frequency 44 differs from the reference frequency 24 by more than the capture range of the tracking mode.
The normal or tracking mode, with very slow response provides the desired frequency stability and low-output jitter of the DCO which is master to a number of other DCOs in the timing hierarchy. It also permits integration and consequent attenuation of short-term (up to one day) phase wander which enables the DCO to free-run at very near the mean reference frequency after it is cut off from its own synchronization source. Other benefits of the slow tracking mode are the ability to detect unusual long-term disturbances (such as excessive frequency drift) by simple inspection of the phase detector output, and the ability to bridge short-term disturbances (phase hits).
To analyze and design a control system, it generally is necessary to obtain a quantitative mathematical description or model of the system. Since a person of ordinary skill in the art would be able to create a mathematical model of the PLL in connection with designing the PLL, additional details of a particular mathematical model have been omitted to avoid obscuring the invention. One example of a mathematical model that may be used to describe an example PLL is set forth in provisional application No. 60/674,231 the content of which is hereby incorporated herein by reference, although other mathematical models may be implemented as well and the invention is not limited to the embodiment(s) disclosed in this provisional application.
Direct Digital Synthesizer
As shown in
As discussed in greater detail below, the master clock 16 of this embodiment shown in
A DDS is able to produce an accurate reference signal whose frequency and phase can be precisely controlled in real time. The term "frequency synthesizer" defines an active electronic device that accepts an input reference frequency and then generates one or more new frequencies as commanded by a control word, whereby the stability, accuracy, and spectral purity of the output correlates with the performance of the input reference.
Direct digital synthesis generates a new output signal 44 based upon an original reference clock signal 112. While this technique essentially mimics traditional phase-locked loop synthesis, all frequencies are generated as digital representations of the desired signal using digital sampling techniques. This approach inherently affords great flexibility to the designer in terms of control and accuracy of the selected frequency. The digital output from the DDS is usually reconstructed with an accurate high-speed Digital-to-Analog Converter (DAC) 106 and then filtered via filter 108 to provide an analog output signal. Since the DDS chip contains all the digital processing to construct and manipulate a frequency, most analog circuitry (apart from the DAC) is eliminated, along with the disadvantages inherent to analog components.
The synthesis of frequencies via direct digital synthesis involves the generation of a waveform from a series of digital numbers which are then converted into analog form by a DAC. The DDS seems architecturally simple, yet provides persuasive advantages that are difficult or expensive to achieve with alternative synthesis methods. These advantages include, among other benefits, very fast switching, fine frequency resolution, excellent phase noise, transient-free (phase continuous) frequency changes, frequency agility and extraordinary flexibility as a modulator, and small size.
The DDS has disadvantages also, of which two may impose serious restrictions. First, the operating range of a DDS is limited by Nyquist sampling theory, which limits the output waveform to be at most half the input reference frequency. For practical reasons, this may be further limited to about one half of the maximum clock rate at which the logic can be operated where the logic operates at a slower clock speed than the input frequency. The second limitation is spectral purity, which is governed by the density/complexity of the logic circuitry that is attainable at the desired operating speed. Spectral purity and operating bandwidth are inversely correlated. When a DDS is to be implemented as part of the master clock, the DDS may be used to generate a Sine wave. Although each of the components of the DDS will be explained in connection with generation of a sine wave, the invention is not limited to use of a DDS to generate a Sine wave, as other waveforms may be used if desired.
The phase accumulator generates the phase component of the output clock. Specifically, the phase accumulator will cycle through 2π radians in increments specified by the change in phase per clock cycle. The change in phase per clock cycle is set by the DDS input control word 50. By changing the amount of phase that is accumulated during each clock cycle, the frequency of the output signal may be adjusted.
The phase accumulator may be implemented using a q-bit adder 114 and a register 116. The q-bit adder 114, in this embodiment, has two inputs, one of which is connected to the DDS input control word φ=Δθ (DDS control word 50) and the other of which is connected to the previous sum 118 stored in the register 116. The range of phase numbers 2q is spread across one cycle of the sine wave, thus 2π=2q. It may be shown that the generated output frequency may be expressed as:
The phase accumulator represents a cyclic phase generator producing a time series of binary integer values (phase sequence) corresponding to the oscillator progression of phase. Stated differently, the phase accumulator generates a phase value of the output waveform for each cycle of the fixed high-frequency oscillator. Since the phase of a Sine wave changes linearly with time, a set value may be added to the accumulator during each clock cycle to cause the output phase of the Sine wave to change a particular amount for the clock cycle. By changing the amount of phase accumulated during a given clock cycle (by changing the DDS input control word 50) the frequency of the output signal 44 may be adjusted.
The phase sequence is generated by a q-bit accumulator clocked at the sample rate, fo=1/δt 120, which accumulates a phase increment, φ, modulo 2q. As shown in
N PA(nδt)=[N PA(nδt−δt)+φ]modulo 2q, (11)
where NPA(nδt) is the content of the phase register (which represents DDS phase in fractional cycles), n is the time index, and δt is the sampling interval. The value of NPA(nδt) is bounded by the width (number of bits) of the input φ and of the accumulator (q number of bits). Note that a cycle is equal to 2q since the counter will overflow once it reaches 2q causing the phase to return to zero. Hence, NPA(nδt) is always modulo 2q. NPA(0) represents the accumulator initial condition at n=0, which can take a value of zero or higher value to produce an initial phase shift. The complete set of discrete states generated by the accumulator may be evenly mapped as phase values around a circle. This would correspond to the discrete output waveform values. The restriction imposed on the phase accumulator by the finite width results in an overflow inherent in the binary adder. This implies a phase zero crossing upon overflow. The frequency of overflow thus dictates the frequency of the output signal. The particular control word required to generate a particular output frequency will thus depend on the length of the register 116 and the speed of the reference clock 120.
From this it follows that the DDS phase output in radians is
which means that the DDS divides the range of the input signal (0,2π) into 2q equal increments. The DDS control word 50 indicates the step size 124 with which the phase will be incremented during each clock cycle. The stored value 116 in the accumulator represents the current phase of a cyclical function.
The input to the phase accumulator is the frequency control word φ 50. Since the control word 50 represents a q-bit digital value, the output frequency of the DDS fout 40 is changed by variation of the input control word. The above phase accumulator arrangement forms a frequency generator at a fixed rate for given values of φ and fo=1/δt.
Whereas the size of the phase increment determines the actual output frequency, the frequency resolution is determined by the number of bits in the phase accumulator register. The frequency increment (or resolution) of a DDS is defined as
As is readily apparent, the frequency resolution of the DDS is a function of the clock frequency fo and the number of bits q employed in the register 116 of the phase accumulator. A longer phase accumulator register, therefore, will allow finer frequency tuning to take place. The phase accumulator must have a sufficient field width to span the desired frequency resolution. For practical applications, a large number of bits are allocated to the phase accumulator in order to satisfy the system frequency resolution requirements. Given the resolution δfout and the clock frequency, the required number of bits is given as
The finite length of the register introduces a source of quantizing noise into the DDS. Commercially available DDSs with register lengths between 24 and 64 bits may be used to implement the DDS, although the invention is not limited to an implementation having a register in this length range as other DDSs may be used as well depending on the particular implementation. A longer register entails some penalty—in power consumption, cost, chip area, spurious outputs, or speed (i.e., a larger q results in a slower accumulator rate of internal addition due to carry propagation)—so there is an incentive to minimize its size. But an excessively short register entails a performance penalty because the quantization noise may become too large. To balance these competing considerations, the phase jitter caused by frequency quantization may be calculated using known techniques so that an informed trade-off can be made.
Once the phase information is generated, it will be converted to a sinusoidal value using the lookup table 104, which stores samples of a sinusoid according to phase. The phase accumulator is used to generate a suitable phase argument that is mapped by the lookup table to obtain the desired output waveform value. Thus, the second component in a DDS is a memory such as a Read Only Memory (ROM) or a Random Access Memory (RAM) or mapping device 104 that performs the nonlinear transformation of ωt
The ROM/RAM lookup table 104 thus acts as a phase-to-amplitude converter. The phase accumulator generates a discrete time phase sequence NPA(nδt), which is then mapped to the amplitude domain using a lookup table 104 containing amplitude values for the sinusoid. Where a different waveform is desired to be created, amplitude values for the different waveform may be stored in the lookup table 104. The digitized phase mapping from the phase accumulator is used to address the ROM/RAM which contains the stored values of the desired output waveforms. The phase-to-amplitude conversion process maps the sequence of instantaneous binary phase values provided by the phase accumulator through corresponding phase values into quantized amplitude time samples of the generated waveform. If the output is to be over a usable bandwidth, the memory must also be fast. Memory is the slowest digital device in the chain (logic gates operate today at 5 GHz, while memory is about an order of magnitude slower).
To convert the phase to amplitude a converter, ideally, would take the q accumulated phase bits as the input. Because lookup tables are mostly used for phase-to-sinusoid amplitude conversion, with linearly increasing q the table size increases exponentially. Due to excessive memory requirements, it may not be practical to use the full precision of the phase accumulator to index into the sine/cosine lookup table. A quantized (or truncated) version of the phase angle therefore may be used to index into the lookup table 104 such that only the p most significant bits are used to obtain the amplitude value of the Sine wave.
A phase quantizer 122 (see
As described above, not all of the bits recorded in the phase accumulator may be input to the sine lookup algorithm. Reducing the number of bits input to the sine lookup function is referred to herein as phase truncation. Phase truncation is an internal operation of DDSs and cannot be externally influenced. The truncation of the Least Significant Bits (LSB) is a loss of phase information and contributes errors. However, in most practical designs, the spurs caused by phase truncation error are low.
The size of the lookup table also can be reduced by taking advantage of the symmetry of the sine wave. First, there is symmetry about the x-axis, indicated by the most-significant bit (MSB) used as a sign bit. Next, there is vertical symmetry about each half sine wave, where the second MSB is used for quadrant information. Thus, due to the symmetry of the Sine wave, only one quadrant of the waveform must be stored in the lookup table 104. The 2 most significant bits from the accumulator, in this embodiment, may be used to identify the quadrant and the next m bits may be used to obtain an amplitude value from the data stored in the lookup table 104. This implementation results in a more area efficient implementation because the memory requirements are minimized: either fewer FPGA block RAM or reduced distributed memory may be implemented to access the requisite information.
Amplitude quantization occurs in the sine lookup process. The lookup takes in a fixed number of bits of phase information and converts it to the equivalent sine amplitude. Since an ideal sine representation would require an infinite number of bits for most values, the value must be truncated. Most DDSs quantize the values and output the 12 MSBs as the sine amplitude representation which is a typical value for practical high-speed DACs. Quantization beyond the value accepted by the DAC would be ignored by the DAC and, hence, is not beneficial.
If an analog output is required, the DDS presents the digital samples from the lookup table to a DAC to obtain an analog waveform with the specific frequency structure. Of course, the samples may also be used directly in the digital domain and the invention is not limited to an embodiment that implements a DAC.
The DAC converts the output values from the ROM/RAM lookup table 104 (i.e., the digital amplitude information) into an analog output Vout(t). A conventional high speed DAC 106 may be used to convert the output values from the lookup table 104 and the invention is not limited to implementation using a particular DAC.
The output of the DAC has the desired sine wave as a major component, but also includes higher frequency image components introduced by the DAC 106 and the other components of the DDS. A Low-Pass Filter (LPF) 108 may be used to reduce these image signals to the desired level, as shown in
Additional degradation of the output waveform signal may also occur due to harmonics of the frequency being generated and the clock rate of the DAC. Non-ideal behavior of the DAC will introduce distortion that shows up as harmonic spurs. Slow edge rates or delay mismatch on the signals switching the current or settling time, over/under shoot, and glitch impulses at the DAC output can lead to this harmonic distortion. When operating well below Nyquist, these harmonics appear directly in the pass band and usually can be handled with appropriate filter at the output. However, when generating frequencies that approach Nyquist, these harmonics can mix with the reference clock and can produce aliasing—spurs that fall onto or near the fundamental frequency.
The spectral quality of a DDS system is dependent upon a number of factors including the phase noise of the clock source, the number of phase bits applied to the sine lookup function (i.e., phase truncation, which is an internal operation of the DDS and cannot be externally influenced), and the number of bits output from the lookup (i.e., amplitude truncation).
The specifications of the DAC, LPF design, and circuit card design also affect the quality of the converted sine wave. The linearity and glitch energy specifications of the DAC are especially important to the generation of pure sine wave signals. Careful attention to layout of the printed circuit design is important to limiting the noise of the synthesizer. Digital switching and power supply noise should be limited from coupling with clock and analog signals.
The reference clock signal 120 input to a DDS system is a major contributor to the phase noise of the system, even though its effect is reduced by the frequency division process of the DDS. The phase noise of the DDS output will show an improvement over phase noise of the clock source itself of
The frequency accuracy of the clock is propagated through the DDS. Therefore, if the sampling frequency is 10 ppm higher than desired, it may be shown that the output frequency will also be higher by 10 ppm. Thus, the stability of the high-speed oscillator is important in determining the overall stability of the DDS. A method and apparatus for synchronizing the local reference clocks of the master and slave Digitally Controlled Frequency Selectors is described in greater detail below.
The frequencies of the discrete spurs and the amplitude of each are dependent on the ratio of the generated frequency fout to the clock frequency fo, as well as the phase relationship of the output waveform to the sample clock. The 12-bit digitized sine output may provide a broadband signal-to-spurious ratio of 72 dB, again depending on the quality of the DAC and the LPF design, as well as the printed circuit characteristics and the phase noise of the clock frequency.
The DDS is able to generate frequencies from 0 Hz to � the frequency of the reference clock. However, limitations on the slope of the roll off of the LPF may reduce the practical upper limit of the output frequency to about 40% of the reference clock frequency.
Phase truncation and amplitude quantization (discussed above) results in periodic noise, which results in undesired spectral line structures. To lower the spurious levels it is possible to spread them over the spectrum. While this will reduce the levels, it also causes the noise floor to rise. One way to lower the spurious levels is to use a phase dithered DDS architecture, an example of which is shown in
As shown in
One advantage of using a dithered DDS such as the one shown in
Controlling the DDS
The DDS is basically a digital frequency divider the incremental resolution of which is determined by the frequency of the reference clock divided by the 2q number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. When the counter overflows it wraps around, making the phase accumulator's output contiguous. The frequency tuning word sets the modulus of the counter that effectively determines the size of the phase increment (φ) that gets added to the value in the phase accumulator during each pulse of the reference clock. The larger the added increment, the faster the accumulator overflows, which results in a higher output frequency.
The output frequency fout of the DDS waveform is a function of the system clock frequency fo, the number of bits q in the phase accumulator and the phase increment value φ. The phase increment value required to generate an output frequency fout Hz is
The phase increment φ is an unsigned value and defines the DDS output frequency.
Assume that the DDS is operating with a control input φnom which corresponds to the nominal frequency fDDS=fnom. Adding a quantity −Δφ to φnom (i.e., φDCO=φnom−Δφ) results in a decrease in the output frequency, fDDS=fnom−Δf, whereas adding a quantity +Δφ to φnom (i.e., φDDS=φnom+Δφ) results in an increase in the output frequency, fDDS=fnom+Δf. Thus, by appropriately controlling the quantity Δφ added to φnom, the output frequency of the DCO fDDS can be controlled accordingly. The size of the phase increment determines the actual output frequency and the fixed binary width q of the accumulator (which overflows) determines the minimum frequency resolution of the DDS. When the DDS is used as a DCFS in a master clock PLL, the value Δφ may be determined from the error signal 56 generated from the filtered phase frequency detector output. Since the details of obtaining an error signal Δφ are set forth in particularity above, a repeated exposition of this topic has been omitted to avoid obscuring the invention.
A DDS may be implemented as a single chip with high clock rates (greater 150 MHz). These devices are competitive in price and power when compared to analog PLLs, while offering high performance, and ease of use and assembly. A DDS can also provide high accuracy and versatile waveform generation. The output frequency of a DDS can be precisely controlled from a digital controller. The frequency can be changed rapidly, each time maintaining phase continuity. A DDS allows frequency resolution control on the order of milli-hertz step size and can likewise allow milli-hertz or even nano-hertz of phase resolution control. In addition, a DDS imposes no settling time constraints for frequency changes other than what is required for digital control. This results in extremely fast frequency switching speeds, on the order of nanoseconds or a few microseconds. In comparison, an analog PLL has a frequency resolution in the 100s of Hz and settling time is a function of the loop filter characteristics, typically about 1 ms. Whereby analog PLL techniques employ feedback and filtering of error signals impeding the time required to change frequencies, a DDS is only constrained by the digital interface control and the settling time requirements of the DAC. DDSs switch frequencies at rates on the order of nanoseconds or a few microseconds, an improvement of at least one or two orders of magnitude faster than conventional PLL switching speeds.
In a DDS, frequency changes are automatically completed in a phase-continuous fashion—a change to a new frequency continues in-phase from the last point in the previous frequency. Since the signal being generated is in the digital domain, it can be manipulated with exceptional accuracy. Optionally, a microprocessor-controlled system can be implemented to store open loop compensation data vs. frequency for a particular device or system parameter. The microprocessor can then simply control the DDS to dynamically correct the frequency as needed. With a suitable frequency detector in a receiver system, a closed-loop system can easily be constructed.
While the DDS offers many design benefits, there are a few drawbacks that should be considered as well. The limitations imposed by the digital sampling process and the digital-to-analog reconstruction affect three primary areas of performance: maximum frequency limitations, spurious signals at output; and power consumption. Additional details associated with DDS design are set forth in Provisional U.S. Patent Application No. 60/674,231, the content of which is hereby incorporated herein by reference. The invention is not limited to the embodiment(s) disclosed in this provisional application, however, as other DDS designs may be utilized as well.
Part II—Second Level Control
In the clock synchronization scheme described above, the master and slave clocks are implemented as Digitally Controlled Frequency Selectors (DCFS), each of which includes a local high frequency oscillator. For example, in the embodiment in which the DCFS is implemented as a Digitally Controlled Oscillator (DCO), illustrated for example in
In each of these embodiments, the local oscillator frequency directly affects the output frequency of the DCFS. For example, a DCO has an inherent stability equal to that of the input high-speed oscillator. If the high-speed oscillator has a frequency range of fo�Δfo, and normalized error �Δfo/fo (which is usually expressed in parts per million, (ppm)), then for a DCO input word Nnom, the output signal will have a corresponding frequency range
The error range of the output frequency is scaled accordingly by a factor of NDCO and is equal to
but the normalized error range stays the same as that of the high speed oscillator, i.e.,
Thus, the stability of the high-speed oscillator is important in determining the overall stability of the DCO.
A DDS similarly is dependent on the stability of the local high-speed oscillator. Specifically, since frequency accuracy of the clock is propagated through the DDS, if the sampling frequency of the DDS is 10 ppm higher than desired (because the input reference clock signal is running 10 ppm too fast) the output frequency will also be higher by 10 ppm. Mathematically, this may be explained as follows. If the high-speed oscillator has a frequency range of fo�Δfo, and normalized error �Δfo/fo, then for a DDS input word φnom (corresponding to the nominal out frequency fnom), the output clock will have a corresponding frequency range
The error range of the output frequency is scaled accordingly and is equal to
but the normalized error range stays the same as that of the high speed oscillator, i.e.,
Thus, the stability of the high-speed oscillator is also important in determining the overall stability of a DDS.
Since the slave and master DCFSs each implement their own local high frequency oscillator, any frequency variation between the high frequency oscillators will result in frequency discrepancies between the master and slave clock outputs. Thus, the inherent clock stability at a master (or slave) clock is dependent on the stability of the local high speed oscillator at that clock. Additionally, since the master clock is implemented as a PLL, any instability at the master will result in the generation of a control word that compensates for the local oscillator drift. This, accordingly, will manifest itself in the slave clock since the control word passed to the slave clock will reflect the master local oscillator drift. Accordingly, the slave clocks will experience drift not only from their own local oscillator, but also that of the master clock local oscillator.
To minimize the amount of drift experienced at the slaves, and for the clock synchronization scheme to be reasonably stable and accurate, DCFSs using free running oscillators would require fairly stable high-speed oscillators. However, even if all of the local oscillators are implemented to be highly stable, the fact that the local oscillators are free-running and are allowed to operate independently ultimately may cause long term drift to occur between the Master and slave DCFSs. According to an embodiment of the invention, operation of the local oscillator at the slave clock may be synchronized with operation of the local oscillator at the master clock, to thereby provide a second level of control to occur that will allow greater synchronization between the clocks to be achieved. For example, a stable local oscillator may be implemented at the master clock and frequency controlled oscillators may be used to implement the local high frequency oscillators at the slave clocks. Operation of the local oscillator of the master clock DCFS may then be monitored, and information associated with its operation may be transmitted to the slave clocks to allow the local oscillators at the slave clocks to mimic the behavior of the master clock local oscillator.
Time stamps may be used, for example, to transmit local oscillator frequency information from the master clock to the slave clocks. In the timestamp-based technique for clock synchronization, a transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. For example, as shown in
The use of timestamps to synchronize two signals is described in greater detail in U.S. patent application Ser. No. 10/076,415, entitled Technique For Synchronizing Clocks In A Network, the content of which is hereby incorporated by reference. In general, timestamps are a construct that allows the number of clock cycles that have occurred at a particular time to be captured and then replicated at another clock source so that the second clock source is able to recreate the operating frequency of the first clock source. If the two clocks are not generating the same number of clock cycles in a given period, the frequency of the tracking clock may be adjusted to more closely approximate the frequency of the master clock.
For example, let the value T(n) denote the time base (e.g., number of clock ticks) of the transmitter at a particular time n, and the value R(n) represent the time base (e.g. number of clock ticks) of the receiver at time n. In the embodiment shown in
The timestamp difference between the nth and (n−1) th timestamp generated at the transmitter 132 is defined as ΔT(n)=T(n)−T(n−1). Similarly, the timestamp difference between the nth and (n−1)th timestamp as measured by the receiver clock is defined as ΔR(n)=R(n)−R(n−1).
When timestamps are transmitted over the packet network, they will arrive at the receiver with variable delay. If d(n) and d(n−1) denote the delay experienced by the nth and (n−1) th timestamp at the receiver, respectively, then the jitter induced by the network is given as j(n)=d(n)−d(n−1). Accordingly, the timestamp difference measured by the receiver includes both the timestamp difference introduced by the transmitter ΔT(n) and the jitter j(n) experienced as the timestamp was transmitted over the network, that is, ΔR(n)=ΔT(n)+j(n).
Ideally, the jitter j(n) should not affect clock recovery at the receiver. To filter out the jitter, the receiver clock frequency {circumflex over (f)}s=1/{circumflex over (τ)}s may be controlled such that the receiver clock measurements ΔR(n) are equal to the transmitter clock timestamp differences ΔT(n). To adjust the receiver clock, an error signal may be formed from the difference between ΔT(n) and ΔR(n): e(n)=ΔT(n)−ΔR(n). Over time, if the transmitter and receiver are operating at the same frequency, the error signal should tend toward zero.
The computed error signal may therefore be filtered and used as feedback in a PLL to adjust the operating frequency of the receiver clock. Specifically, the error signal may be input to a loop filter of a PLL whose output then controls the frequency {circumflex over (f)}s=1/{circumflex over (τ)}s of the oscillator of the receiver clock, where Ko is the gain of the VCO. The function of the PLL is to control the receiver clock frequency {circumflex over (f)}s such that the error e goes to zero at which point the receiver frequency equals the transmitter frequency fs. The loop filter is a simple low-pass filter and may take the form, for example, of the loop filter shown in
In the embodiment shown in
In the example shown in
As shown in
The slave clock, as shown in
The DCFS 22 forming slave clock 18 has a local oscillator 138 configured to generate a local oscillator clock signal 142. Where the DCFS is implemented as a DCO, as shown in
In the second level control, the input timestamp T(n) is compared with a delayed timestamp T(n−1) at a first summing junction 148 to calculate the transmitter clock timestamp difference ΔT(n)=T(n)−T(n−1). At the same time, the oscillator is outputting a signal 142 that is used to run the DCFS which, in the embodiment shown in
The transmitter clock timestamp difference and receiver clock timestamp difference are compared at a third summing junction 154 to generate an error signal e(n)=ΔT(n)−ΔR(n) 156. The error signal 156 is filtered using loop filter 158 to form a filtered error signal u(n) 160. The filtered error signal, over time, should tend toward zero to allow the jitter to be filtered out, so that the reference frequency 142 of the slave local oscillator is able to track the reference frequency 134 of the master local oscillator 132.
The loop filter may be formed to be similar to the loop filter shown in
When the first transmitter timestamp arrives, it will be stored and the receiver counter value will be stored (204). When a subsequent timestamp arrives from the transmitter (206), and for each subsequent timestamp that arrives from the transmitter, the arrival index n will be incremented and the timestamp value of the transmitter and receiver timestamps will be stored. The transmitter clock timestamp difference ΔT(n)=T(n)−T(n−1) and receiver clock timestamp difference ΔR(n)=R(n)−R(n−1) will then be calculated (208) to allow an error signal to be generated. Knowing the two timestamp differences allows the error signal e(n)=ΔT(n)−ΔR(n) to be calculated (210), which may then be filtered by the loop filter to calculate the loop filter output (212).
Using timestamps to allow the slave local oscillators to synchronize with operation of the master local oscillators allows the stability of the high-speed oscillators to be increased by locking the slave clock's high-speed oscillator to the master's high-speed oscillator. Transmission of the control word to cause overall synchronization of the DCOs or DDSs thus provides a first level control, while allowing synchronization of the local oscillators provides a second level control that prevents frequency differences in the local oscillators from affecting the transmission scheme.
Although an embodiment has been described in which timestamps were generated at the master clock and transmitted to the slave clocks, alternatively the slave clocks may generate timestamps from their local oscillators and transmit the timestamps to the master clock. The master clock may use the values from the local oscillators, in this embodiment, to generate slave specific DCFS control words to compensate for the local oscillator drift and unicast those slave specific DCFS control words to the slave clocks. Performing local oscillator processing at the master clock allows the slave clocks to be kept very simple, which may be advantageous in particular environments. Requiring the master clock to process timestamps from each of the slaves, however, will require the master clock to be implemented with additional processing capacity. The invention is not limited, therefore, to an embodiment as shown in the several figures as other ways of synchronizing the state of an internal reference frequency may be implemented as well.
The circuits described herein that may be used to form master and slave clocks may be implemented using discrete components, integrated circuitry, or using a combination of hardware and control logic implemented as a set of program instructions that are stored in a computer readable memory within the network element and executed on a microprocessor. However, it will be apparent to a skilled artisan that all logic described herein can be embodied using discrete components, integrated circuitry, programmable logic used in conjunction with a programmable logic device such as a Field Programmable Gate Array (FPGA) or microprocessor, or any other device including any combination thereof. Programmable logic can be fixed temporarily or permanently in a tangible medium such as a read-only memory chip, a computer memory, a disk, or other storage medium. Programmable logic can also be fixed in a computer data signal embodied in a carrier wave, allowing the programmable logic to be transmitted over an interface such as a computer bus or communication network. All such embodiments are intended to fall within the scope of the present invention.
Although the invention has been described in the context of clock distribution over an asynchronous network the invention is not limited in this manner. For example, embodiments of the invention may also be used as a timing distribution technique for a packet backplane interconnect in a packet switch, router, or TDM switch, as a TDM backplane extension, for example to extend the reach of a TDM bus over a longer distance, and as a TDM backplane expansion, for example to scale up a TDM backplane to handle more cards and devices.
It should be understood that all functional statements made herein describing the functions to be performed by the methods of the invention may be performed by software programs implemented utilizing subroutines and other programming techniques known to those of ordinary skill in the art. It also should be understood that various changes and modifications of the embodiments shown in the drawings and described in the specification may be made within the spirit and scope of the present invention. Accordingly, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted in an illustrative and not in a limiting sense. The invention is limited only as defined in the following claims and the equivalents thereto.
|Cited Patent
|Filing date
|Publication date
|May 24, 1995
|Jun 18, 1996
|Sun Microsystems, Inc.
|Multiple phase shifted clocks generation using a minimal set of signals from a PLL
|Oct 30, 1997
|Feb 22, 2000
|Texas Instruments Incorporated
|Digitally-controlled oscillator with switched-capacitor frequency selection
|Mar 10, 1997
|Aug 14, 2001
|Madge Networks Limited
|Methods and apparatus for synchronizing a clock
|Apr 7, 2000
|Jun 3, 2003
|Omneon Video Networks
|Clock recovery in a packet-based data network
|Feb 7, 2003
|May 2, 2006
|Advanced Micro Devices, Inc.
|Automatic center frequency tuning of a voltage controlled oscillator
|Dec 24, 2001
|Jul 31, 2007
|Agilent Technologies, Inc.
|Distributed system time synchronization including a timing signal path
|Sep 30, 2002
|May 13, 2008
|Lucent Technologies Inc.
|Systems and methods for synchronization in asynchronous transport networks
|Jan 9, 2002
|Jul 10, 2003
|Jones Delon K.
|Method and apparatus for aligning the clock signals of transceivers in a multiple access communication system utilizing programmable, multi-tap phase-locked loops
|Nov 22, 2002
|Jul 17, 2003
|Staszewski Robert B.
|All-digital frequency synthesis with DCO gain calculation
|Dec 12, 2003
|Jun 24, 2004
|Orr Raymond K.
|Digital pulse modulation arrangements
|May 23, 2002
|Sep 9, 2004
|Frank Lillie
|Method and device for producing mobile radio signals
|Aug 13, 2002
|Mar 19, 2003
|Nortel Networks Limited
|Technique for synchronizing clocks in a network
|Feb 17, 2004
|Sep 2, 2004
|Zarlink Semiconductor Inc.
|Method providing distribution means for reference clocks across packetized networks
|International Search Report dated Jan. 3, 2006, from corresponding PCT patent application No. PCT/CA2006/001390.
|Citing Patent
|Filing date
|Publication date
|May 31, 2007
|Aug 16, 2011
|Netlogic Microsystems, Inc.
|Low power serial link
|Jan 27, 2011
|Mar 12, 2013
|Microsemi Semiconductor Ulc
|Feedforward synchronization in asynchronous packet networks
|Jun 30, 2011
|Feb 24, 2015
|Netlogic Microsystems, Inc.
|Low power serial link
|Mar 30, 2010
|Jan 19, 2016
|Nxp, B.V.
|Frequency synthesiser
|Dec 20, 2013
|Nov 29, 2016
|Blackberry Limited
|Method for improving clock accuracy in a wide area positioning pseudolite receiver system architecture
|Jun 19, 2013
|Dec 13, 2016
|Blackberry Limited
|Architecture and method to 4G-mobile positioning
|Sep 28, 2007
|Apr 2, 2009
|Ahmadreza Rofougaran
|Method and system for signal generation via a digitally controlled oscillator
|Aug 26, 2009
|Mar 3, 2011
|Credo Technology Corporation
|Table saw with linkage drop system
|Jan 27, 2011
|Aug 18, 2011
|Zarlink Semiconductor Inc.
|Feedforward Synchronization in Asynchronous Packet Networks
|Mar 30, 2010
|Jun 7, 2012
|Nxp B.V.
|Frequency synthesiser
|U.S. Classification
|375/356, 370/503
|International Classification
|Cooperative Classification
|Jun 30, 2005
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In PARIS story headlined "Toyota poised to boost production in France", please read in fourth paragraph ... . Toyota will unveil its plans about Yaris-II at the Frankfurt Car Show on Sept. 12 ... (deleting reference to four-by-four). A corrected repetition follows. (Adds company comment, industry and market details) PARIS, Aug 25 (Reuters) - Toyota Motor Corp is set to boost output at its north French plant to meet booming European demand for its cars, despite higher wage costs, a media ...
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Results 1 to 5 of 5
- 05-17-2013, 08:28 PM Thread Author #1
Play store says "This item cannot be installed in your device's country." even though Im in U.S.
So I tried to download some new apps on my nexus 7, but when I opened the play store it only shows 14 really weird apps, like radar and a third party translator. Even when I search for apps in the search bar it shows up with no results, even though the app obviously exists.
I have tried clearing the cache and data on the store to no avail. Ive also tried to re-install the program with no results. It seems like the problem is with my gmail account, since when I try to look up apps via the play store on my desktop, it shows the exact same apps and nothing else, even when searched. When I go to an apps store page via a link, it takes me to the page, but then an error message shows up on my devices compatability saying that "This item cannot be installed in your device's country." But I live in the U.S., so I dont see what the problem is.
I tried it on my phone, and it works perfectly on it, so I have no idea what's going on. Help would be greatly appreciated.
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Re: Play store says "This item cannot be installed in your device's country." even though Im in U.S.
Some thoughts, maybe helpful, maybe not:
Are you using a proxy server for your internet connection? If so, then perhaps this server is based in a country with limited Google support. Ditch the proxy so that Google sees you are connected within the United States. After doing so, you'll probably need to clear the cache of your N7 as well as computer browser.
Under Settings > Accounts > Google > Location Settings, make sure you have the switch on to allow Google apps to use your location.
Under Settings > Personal > Location Access, make sure you allow other apps access to your location, and have WiFi and mobile network location checked.
Is your Gmail address based in the USA? Perhaps this makes a difference. And when you set up the N7, I assume you chose the USA as your location.
Finally, call Google support at 855-836-3987.
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Re: Play store says "This item cannot be installed in your device's country." even though Im in U.S.
In my case it was Canada, I'm in Vancouver, BC and the annoying message did not wanted to go away, I tried several things but what worked for me was to look for the app on the phone browser (CBC.ca -> Olympics app) but when link opened instead of selecting the play app (google default), I choose web (stayed on my browser) where it asked me to login, then finaly I was able to see the Install button.
Hopefully this will help some other people to install the apps from their own country.
Re: Play store says "This item cannot be installed in your device's country." even though Im in U.S.
I live in Gibraltar, which is a small country, so small that Google's copyright lawyers probably have not heard about it. But we are an affluent European nation and naturally my credit cards are located here. Virtually any app that I try to install is "incompatible with" my device or "unavailable in" my country. Most good apps are not even displayed in the Play Store. Ironically their add-ons or expansions are usually displayed and can be installed, but what good is that? Wherever possible, I download APKs from developer's site or APK distributor sites and sometimes there is a risk of malware, but what can I do? I don't want to root my phone or do anything illegal, but Google does not give me a chance. This complete geographical isolation is not only gratuitously offensive but stupid (I can pay good money like anyone else, which developers are losing!), but it is a price I pay for Google's ignorance. Not for long, hopefully. After 3 years of sticking to Android (I don't like the Apple ecosystem), I see that the Windows environment is maturing slowly at last and I may switch later this year, giving up Android for good.
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text:
Selection Bias in Web Surveys and the Use of Propensity Scores
Web surveys have several advantages compared to more traditional surveys with in-person interviews, telephone interviews, or mail surveys. Their most obvious potential drawback is that they may not be representative of the population of interest because the sub-population with access to Internet is quite specific. This paper investigates propensity scores as a method for dealing with selection bias in web surveys. The authors' main example has an unusually rich sampling design, where the Internet sample is drawn from an existing much larger probability sample that is representative of the US 50+ population and their spouses (the Health and Retirement Study). They use this to estimate propensity scores and to construct weights based on the propensity scores to correct for selectivity. They investigate whether propensity weights constructed on the basis of a relatively small set of variables are sufficient to correct the distribution of other variables so that these distributions become representative of the population. If this is the case, information about these other variables could be collected over the Internet only. Using a backward stepwise regression they find that at a minimum all demographic variables are needed to construct the weights. The propensity adjustment works well for many but not all variables investigated. For example, they find that correcting on the basis of socio-economic status by using education level and personal income is not enough to get a representative estimate of stock ownership. This casts some doubt on the common procedure to use a few basic variables to blindly correct for selectivity in convenience samples drawn over the Internet. Alternatives include providing non-Internet users with access to the Web or conducting web surveys in the context of mixed mode surveys.
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- Couper, Mick P. & Kapteyn, Arie & Schonlau, Matthias & Winter, Joachim, 2007. "Noncoverage and nonresponse in an Internet survey," Munich Reprints in Economics 20093, University of Munich, Department of Economics.
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mollusque commented on the word wonder-bag
OED2 defines it as "a Negro amulet", obeah. The wonder-bag contained an assortment of materials used in obeah practice.
December 23, 2007
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Whatever happens to The Artist and its 10 nominations at tonight's Oscar ceremony, it has been an extraordinary 12 months for French cinema.
The jury for the "French Oscars", or Césars, in Paris on Friday were spoiled for choice. Should the most glittering prizes go to a French-made, silent, black and white film about Hollywood which has conquered the world and even, er, Hollywood?
Or should they go a heart-warming comedy about physical handicap, Intouchables, which has been shattering box-office records in France?
The French film academy split the spoils, giving six Césars to The Artist, including Best Film and Best Director to Michel Hazanavicius. But the César for Best Actor went not to the star of The Artist, Jean Dujardin, but to Omar Sy, 34, the comedian-turned-actor who plays a minor criminal turned nurse and carer in Intouchables. No black actor had won the prize before.
Even leaving aside The Artist and Intouchables, it has been a remarkable cinematic year in France. Ticket sales in 2011 – €216m (£183m) – were the highest since 1967. Just over two-thirds of all French people went to the movies at least once. More than two-fifths of all seats sold last year were for French-made movies. There was a string of other critical and modest commercial successes, including Polisse, a movie about a police squad investigating child crime which won two Césars. There were also several expensive bides (flops), including big-budget films by supposedly bankable "stars" such as Luc Besson and Mathieu Kassovitz.
Last year was a powerful advertisement for the often-decried, public-and-private French approach to financing film-making – a unique model. Since much of the "public" investment comes from a 12 per cent tax on cinema tickets, success should, in theory, breed success.
The French industry, the third largest in the world, received €1.5bn from the state last year. It should be even more flush with public cash to fund films in 2012/13.
Some important figures in French cinema are, however, unimpressed by what the industry does with its money. Kassovitz, stung by the failure last year of his complex, anti-colonialist movie, L'Ordre et la Morale, posted a tweet last month stating, roughly speaking: "Screw French cinema. Go and fuck yourselves with your shit films."
There is a growing tendency, Kassovitz and other critics say, for French films to ape the worst of American styles and tastes. The Artist, a French movie made without words and about Hollywood, might seem to be the perfect target for their barbs. In fact, Kassovitz and other critics of the French industry, have saluted the wit and "Frenchness" of The Artist – even though the last quality has been disguised by its distributors in the US.
Their complaints are mostly directed at the uninspiring middle ground of French comedies, thrillers and rom-coms. The safety net of public subsidy, critics say, too often makes the film-making lazy and predictable.
Public funding also allows so-called experimental or director's movies (films d'auteur) to see the light of day in France – but not always the light of the cinema screen. Almost half of the 260 French films made each year are scarcely given public showings. A move to "digital" projection will make it even easier in future for a few films to dominate the market.
Other senior figures in the French industry reject the criticism as manifestly unfair or exaggerated. They point out that Hazanavicius cut his teeth on Hollywood-style, crowd-pleasing comedies. They also point out that the defining characteristic of French cinema in recent years has been its lack of defining characteristics, with a mix of successful films that don't conform to formats.
Who would have predicted the runaway popularity in 2008 of a comedy about the fact that people in northern France talk oddly (Bienvenue chez les Ch'tis)? Or the triumph last year of Intouchables, a buddy comedy about a rich man in a wheelchair and a wiseacre from a troubled, multi-racial suburb? Or the global success of a silent movie made in 2011?
At least, unlike Britain, France still has a complete cinema industry, which makes French thrillers, French comedies, French adventure stories, French rom-coms, French silent movies – and French flops.
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