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A new technique developed by Janelia researchers allows scientists to use electron beams to determine protein structure from tiny crystals.
New evidence suggests that aneuploidy patterns of chromosome deletion or amplification that are recurrent among tumors actually represent a driving force during tumor evolution and are very frequent in cancer.
HHMI researchers have discovered that the pool of inactive HIV viruses that lingers silently in a patient's body is larger than expected. The viruses continue to be a threat because they retain the ability to become active even after treatment with the best HIV drugs.
HHMI researchers have developed a mouse model of scleroderma. Their studies have uncovered some of the molecular pathways that go awry to cause the disease.
Neurons deep in the fly's brain tune in to some of the same basic visual features that neurons in bigger animals such as humans pick out in their surroundings. The new research is an important milestone toward understanding how the fly brain extracts relevant information about a visual scene to guide behavior.
HHMI researchers have designed an inhibitor that can reduce the expression of the mutated gene that causes hypertrophic cardiomyopathy, a potentially fatal heart condition.
La Real Academia de las Ciencias Sueca anunció que los investigadores del HHMI, Randy W. Schekman y Thomas C. Südhof, y James E. Rothman de la Universidad de Yale son los ganadores del Premio Nobel de Fisiología o Medicina 2013 por sus descubrimientos sobre la maquinaria que regula el tráfico de vesículas, un importante sistema de transporte de nuestras células.
The Nobel Assembly at the Karolinska Institute announced that HHMI investigators Randy W. Schekman and Thomas C. Südhof, and Yale's James E. Rothman are the recipients of the 2013 Nobel Prize in Physiology or Medicine for their discoveries of machinery regulating vesicle traffic, a major transport system in our cells.
Janelia scientists launch collaboration to develop a new generation of devices to detect neural activity.
Some breast cancer cells have a leg up on survival—the genes they express make them more likely to spread and prosper in bone tissue.
Scientists have discovered that an active ingredient in an over-the-counter skin cream slows or stops the effects of Parkinson's disease on brain cells.
New thinking and technological innovation help Janelia researchers piece together a complex map of the neuronal connections that flies use to detect motion.
By activating a subset of brain cells in mice, researchers changed the way the animals remembered a particular setting.
New research reveals the cellular network that activates temperature-sensitive changes in an infectious fungus.
A new protein engineered by scientists at the Janelia Farm Research Campus fluoresces brightly each time it senses calcium, giving the scientists a way to visualize neuronal activity. The new protein is the most sensitive calcium sensor ever developed and the first to allow the detection of every neural impulse.
New research reveals details of changing DNA methylation patterns as the brain matures.
Proteins engineered to bind enhancer regions of the genome offer researchers a window into how genes are activated.
Scientists have identified a gene that enables wheat crops to fight off stem rust, a dreaded fungus that blights wheat fields with rusty brown lesions and reduces yields.
When injected into mice immediately following a traumatic event, a new drug prevents the animals from developing memory problems and increased anxiety that are indicative of post-traumatic stress disorder.
In one of the first successful attempts at genetically engineering mosquitoes, researchers have altered the way the insects respond to odors, including the smell of humans and the insect repellant DEET.
Identification of a cell signaling pathway that affects the levels of the toxic protein responsible for the neurodegenerative disease SCA1 could lead researchers to new drugs.
Malaria parasites infecting human red blood cells send packets of information between cells to coordinate group activity. When the parasites are under stress, the communication increases their ability to develop into a new stage of the life cycle.
New research shows that about 10 percent of severe cases of congenital heart disease are caused by genetic mutations that are absent in the parents of affected children.
Meet the 2013 HHMI Investigators
Meet the 2013 HHMI Investigators
Meet the 2013 HHMI Investigators
Meet the 2013 HHMI Investigators
Waging an immunological war against a pathogen is not the body's only way to survive an infection. Sometimes learning to live with an invader can be just as important.
A new technique transforms biological tissue into an optically transparent sample that retains its original structure and molecular information.
Stephen Elledge recognized for research on DNA repair.
New research reveals how a localized source of a signaling molecule directs a dividing stem cell to produce two different cells—one identical to its parent, the other a more specialized cell type—and aligns those cells.
Researchers have found that temperatures on the surface of the tropical South Atlantic Ocean in July can predict the severity of malaria outbreaks in northwestern India that begin to peak four months later.
Scientists have a new view of the cellular machinery that assembles directly on DNA and readies it for transcription into RNA, the first step in protein production.
Three HHMI scientists are among 11 honored for excellence in research aimed at curing intractable diseases and extending human life.
Científicos han descubierto que arreglos periódicos de actina en forma de anillos rodean las largas fibras axonales de las células nerviosas, en contraste con las redes lineares que comúnmente le dan forma a las células.
Scientists have discovered that periodic ring-shaped actin arrangements encircle the long axonal fibers of nerve cells, in contrast to the linear meshworks that typically give cells their shapes.
HHMI scientists discover how a single molecule in a living cell can respond differently to different strengths of an external signal.
A new analysis suggests that the regulatory protein MeCP2 works with the modified nucleotide 5hmC to facilitate gene activation in the brain.
Scientists have discovered the molecular pathway responsible for detecting loose bits of DNA outside a cell's nucleus and setting off an immune reaction.
Rather than scrutinizing hours of video, scientists can quickly teach the software how to recognize key behaviors.
AAAS recognizes Ulrike Heberlein and Nelson Spruston for meritorious efforts to advance science.
A new DNA sequencing technique has enabled researchers to map for the first time the influential chemical modifications known as methylation marks throughout the genome of a pathogenic bacterium.
eLife makes first collection of research articles available online.
Robert Lefkowitz de HHMI comparte el premio con Brian Kobilka por estudios sobre los receptores acoplados a proteínas G.
Only a few animals, such as songbirds, whales, and dolphins, are known to be vocal learners, modifying the sequence or pitch of their sounds based on what they hear from other members of their species. New evidence suggests mice can be added to that list.
HHMI's Robert Lefkowitz shares prize with Brian Kobilka for research on G-protein coupled receptors.
HHMI and the University of KwaZulu-Natal open new research institute in Durban, South Africa.
In experiments with rats, researchers found that the rejection of an old belief correlates with abrupt changes in activity in a region of the brain involved in cognitive functions such as reward anticipation and decision-making.
HHMI selects 13 of the world's leading basic science researchers to receive Senior International Research Scholar (SIRS) awards. The awards support outstanding biomedical scientists working outside the United States who have made significant contributions to fundamental research in the biological sciences.


text:
Thank you for posting these, Colleen. I know how busy you are today with the bus
tour groups arriving. The pictures
are beautiful. Unfortunately the
little ones are hard to grow here in the hot desert. They take more work just to keep alive
and often don't bloom. The
TBs give more color for the time spent on them, so I've given up on the
Francelle Edwards Glendale, AZ Zone 9
-----Original Message-----
From: firstname.lastname@example.com
[mailto:email@example.com] On
Behalf Of Colleen Modra
Sent: Wednesday, October 26, 2005
To: firstname.lastname@example.com
Subject: [iris-photos] MB: spring
It hasn't been our best srping for
littlies but hare are some Aussie bred favourites.
Zinglet - Nilsen Nisen 96
Whydidi - Blyth 02
Tickle The Ivories - Blyth 02
Colleen Modra
Adelaide Hills AUST
zone 8/9

subset: commoncrawl


text:
|Publication number
|Publication type
|Publication date
|Jun 28, 1974
|Filing date
|Mar 13, 1973
|Priority date
|Mar 17, 1972
|Publication number
|Vinsani M
|Original Assignee
|Honeywell Inf Systems Italia
|Export Citation
|BiBTeX, EndNote, RefMan
|Referenced by (35), Classifications (11)
|External Links: USPTO, USPTO Assignment, Espacenet
United States Patent [191 Vinsani [11] 3,821,645 June 28, 1974 [75] Inventor: Mario Vinsani, Milan, Italy [73] Assignee: Honeywell Information Systems Italia, Caluso, Italy 22 Filed: Mar. 13,1973
211 App]. No.: 340,798
[30] Foreign Application Priority Data- Mart 17, 1972 Italy .4 21989/72 [52] US. Cl 324/73 R, 235/153' AC [51] Int. Cl G01r 15/12 [58] Field of Search 324/73 R, 73 AT, 73 PC; 235/153 AC [56] References Cited UNITED STATES PATENTS 3,286,175 11/1966 Gerbier 324/73 R 3,311,890 3/1967 Waaben 324/73 R 3,544.777 12/1970 Winkler t v. 235/l53 AC 3.614,608 10/1971 Giedd 324/73 R 5/1973 Maley 324/73 R OTHER PUBLICATIONS Y. Tsuboi Function Tester For Digital Integrated Circuits Electrical Engineering in Japan 89(8)-Aug. 1969 pp. 45 54.
Primary Examiner-Michael J. Lynch Attorney, Agent, or Firm-Fred Jacob [5 7] ABSTRACT A device is provided for testing integrated circuit units, the device including means for connecting the unit under test and comparing the outgoing signal of the unit with the outgoing signal of a reference unit to detect a difference in the logic operation of the unit under test and to determine failures. In order for such comparison to be accomplished, the reference unit is placed in the same state in which the unit under test should be for correct operation. The present device is advantageously employed in testing those units having circuit elements capable of assuring one of two definite states, and remaining in that state for an indefinite length of time.
5 Claims, 9 Drawing Figures PATENTEDJUNZB m4 332L645 SHEU 3 OF 5 REFERENCE MEMORY f? "/B B B B3 PATENIEB JUN 28 I974 SHEEI 4, [IF 5 SUPERVISION CIRCUIT FIGS PATENTEJUNZ am FIG. 6
BACKGROUND OF THE INVENTION This Application relates to a device for testing the operation of integrated circuit units as used in electronic data processing apparatus, and more particularly is an improvement to the copending US. Pat. Application Ser. No. 233,675, filed Oct. 3, I972.
Said copending application describes a device comprising means for connecting the input pins of a reference integrated circuital unit, to the input pins of an integrated unit under test, and for comparing the signals at the output pins of the unit under test to the signals at the output pins of the reference unit, in order to detect any difference in the behaviour of the unit under test from that of the reference unit, and therefore any malfunction of the unit under test.
However the unit to be tested may not be of purely combinatorial type, but may comprise sequential, or memory elements, that is, circuit elements capable of assuming one of two definite states, and remaining in the assumed state for an indefinite length of time, thus storing an information element. In this case, as explained in the cited copending application, it is necessary, both in the unit under test, and in the reference unit, to initially set the sequential elements in the same state, so that they may respond in the same way to the received signals.
Different ways for obtaining this result have been indicated in the cited copending application. In the case where the integrated sequential unit to be tested is provided with a re-set input, that is, an input enabling a reset signal to set all the sequential elements in the same state, the desired result may be obtained by a key or a push button enabling the operator to send this reset signal; or alternatively, this signal may be generated in the test program, or also be emitted automatically by the apparatus at the start of the operation.
If the integrated sequential unit under test is not provided with such reset input, the same result may be obtained by a properly designed test program. The device according to the invention will be provided with an inhibit circuit, for preventing an error signal from being emitted as long as the test program has not yet set all the memory elements contained in the unit, in the same state. When this condition has been reached, the program may signal the operator, for instance by stopping, to disable the inhibit circuit.
The said means for reaching the required result are all feasible, but such arrangements lack generality, because they require a different designing of the test program, and a different behaviour of the operator, according to the type of unit to be tested.
The purpose of the invention is to provide means for automatically inhibiting the emission of the error signal as long as all the memory elements in the unit under test, and in the reference unit, have not been set in the same state, and for removing'the inhibition when this condition has been reached.
Thus, there is no need for using an expressly designed test program, but a usual operating program of the apparatus may be used, provided it fulfills certain requirements. These means will adapt themselves to the type of unit to be tested,'andtherefore the manual operation tobe effected by changing the reference unit will also adapt or change said means according to the type of reference unit.
SUMMARY OF THE INVENTION This objective is attained by providing the testing device with circuit means for inhibiting the error signal, and associating with the reference unit a supervision circuit which, in the initial state, maintains the inhibition, and on receiving the signals applied to at least a part of the inputleads of the reference unit, records these signals in storage elements, in such a way, as to remove said inhibition only in case the received signals have been such as to put each memory element of the reference unit in the same state in which the memory elements of the unit under test should be in case of its correct operation.
In the preferred embodiment, as described in the cited copending application, the supervision circuit is mounted on the same removable pin support which carries the reference unit. Therefore, by changing the support in order to change the reference unit mounted on the same, the supervision circuit is also changed accordingly.
BRIEF DESCRIPTION OF THE DRAWING A preferred embodiment of the invention is now described'in detail, with reference to the attached drawing, in which:
FIG. 1 is a simplified wiring diagram of the device according to the invention, in the case where the sequential unit is provided with clock and reset inputs;
FIG. 1a is a modification of the same wiring diagram in the case where only clock inputs are provided;
FIG. 1b is a modification of the wiring diagram of FIG. 1 in the case where flip-flops of the J-K type with clock input are employed;
FIG. 2 is a simplified wiring diagram of the device in the case using a shift register;
FIG. 3 is a simplified wiring diagram of the device in the case employing a semiconductor storage unit;
FIG. 4 is a wiring diagram of a modified device according to the invention in the case where asequential cyclic unit is not provided with reset input;
FIG. 4a is a variant of the preceding circuit;
FIG. 5 shows a plurality of waveform diagrams at different points of the device of FIG. 4; and
FIG. 6 is a schematic perspective viewshowing the arrangement of the different components according to a preferred embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.- 1 shows an example of the circuit according to the invention, applied to the device for checking the logical operation of an integrated circuit unit as described in the cited copending application.
Reference numeral 1 indicates theintegrated sequen tial unit under test, which, in the example illustrated, comprises four bistable multivibrators with clock latching, usually known as a Flip-flop-latch." Such devices each comprise a data input D, a clock input C, a set input S, and an output O. The binary value applied to the input D is transferred to the output Q when, for instance, the input C is at value ZERO: when C goes from ZERO to ONE, the output value is latched to the input value existing immediately before the moment of this change of the clock value, and is independent of the value at the input D, as long as C remains ONE.
A binary value ONE applied to the set input S sets the flip-flop to a predetermined state, for instance the high" state corresponding to the value ONE at output Q, independently of the values applied to the other inputs.
The integrated sequential unit illustrated in the example comprises four flip-flops of said type all having clock inputs and, respectively, all having set inputs connected to single respective common clock and common set inputs. It has, therefore, a Common Clock input CC, a Common Set input SC, four individual data input l l l 1;, and four individual outputs U U U U Reference numeral 2 indicates the sequential integrated reference unit, identical in construction and operation to the unit under test, and having the six inputs CC, 1' l,, 1' 1' SC parallel connected to the six inputs CC, 1 1,, 1 1 SC of the unit under test, by means of gripper contacts as described in the copending application.
The outputs U U',, U U;, of the reference unit are each connected to a first input, indicated respectively by 4, 6, 8, of one of the logic test channels 11, 12, 13, 14, and the second inputs of these, respectively 3, 5, 7, 9 are connected, by means of the gripper contacts, to the outputs U U U U of the unit under test. Each one of the test channels comprises a comparing circuit CP and a delay circuit CR. As explained in more detail by the cited copending application, the comparing circuit gives at its output a signal of a given binary value, for instance ZERO, each time its two inputs are at a different binary value. The delay circuit OR may be formed by a delay line and an associated logic circuit, and at the output of the channel (respectively 15, 16, l7, 18) gives a signal of a given binary value, for instance ZERO, if, and only if, the length of the signal ZERO applied at its input by the comparing circuit is greater than a given interval. The presence of a binary value ZERO at the output of a logic test channel indicates therefore that there is a difference in binary values between the outputs U and U of the corresponding pair of associated outputs of the unit under test and of the reference unit, and that such difference is not due to an allowed small difference in the propagation time of the signals within said units, but to a defective unit, and is therefore an error signal.
The outputs 15, 16, 17, 18 of the four test channels 11, 12, 13, 14 are connected to the inputs of a NAND gate 20 which therefore gives at its output a binary value ONE if, and only if, at least one of the inputs is a ZERO value, that is, if at least one of the channels emits an error signal.
The output of the NAND gate 20 is connected to a first input of a NAND gate 21, the second input being connected to a supervision circuit 30, associated with the reference unit 2.
The output 31 of this supervision circuit, the operation of which is described later in the description, delivers in the initial condition, a binary value ZERO. .Therefore, the output of NAND gate 21 is ONE for any value of the signal at its first input. When the value of output 31 is ONE, the output of the gate 21 is the inverted value of the signal applied to its first input, connected to the output of gate 20.
In case it gives out a ONE signal, that is an error signal, this causes the output of NAND gate 21 to go to the value ZERO. This signal is applied to an input S of a flip-flop 22 setting the same in the high condition and originating a continuous alarm signal, for instance the lighting of the signalling lamp 24.
This light alarm may be turned off acting on the pushbutton 23 applied to a reset input R of the flip-flop 22. It may therefore be seen that a signal ZERO on output 31 inhibits the alarm signal caused by a difference of logical level between an output of the unit under test and the corresponding output of the reference unit.
Generally, the supervision circuit 30 is so designed, and so connected, as to give out at its output 31, initially, a ZERO value, and to changeover to a value ONE only when both memory elements of each pair of corresponding elements in the unit under test and in the reference unit, have been put in the same state. From this moment on, all pairs of elements will change in the same way in response to the same signals, and therefore the testing of the unit under test may proceed in a fully automatic way, and is able to detect any fault under the condition that the program controlling the unit test be such, as to cause, in a first time, the coincidence of states for all pairs of corresponding memory elements in both units, and subsequently, to apply to the inputs of said units a sequence of signal patterns capable of revealing a faulty operation of the unit under test.
In the example considered, the sequential unit under test is provided with a common set input SC and a common Clock input CC. By applying a signal ONE to the common set input SC, all four flip-flops are brought, for. instance, to the high position. When a signal ONE is applied to the common clock input CC, the four flip-flops of each unit are brought to the state determined by the values of the signals applied to the in-' puts I, which are the same for both units. Therefore, when a Clock signal, or a Set signal is applied to the corresponding inputs, all the corresponding flip-flops in both units are set in the same state, provided that the unit under test is operating correctly.
According to the preferred embodiment, therefore, in this case the supervision circuit 30 has two inputs, 28 and 29, connected to the common clock input CC and to the common set input SC of the reference unit. These inputs are connected to the inputs of an OR gate 27, its output being connected to the set input S of a flip-flop 32 having a direct output U and a reset input R In the initial condition, the output 0 of flip-flop 32 delivers a ZERO value signal to the output 31 of the supervision circuit, and therefore the NAND gate is inhibited, and any alarm signal is prevented. When a signal ONE is present either at the Set input SC, or at the Clock input CC of the reference unit, the flip-flop 32 goes to the high position, and the output U delivers a signal ONE on output 31 enabling the NAN D gate 21, thus allowing, which may be the case, an alarm signal to be delivered.
The Reset input R of flip-flop'32 is connected to an input 33 by means of which a signal for resetting the flip-flop in the low condition may be applied. This,
for instance, may be obtained using the same push button 23 which resets the flip-flop 22.
A light signalling device, preferably a solid-state photoemitter 35, connected to the output 31 of the super vision unit, will light up when this output is at binary value ONE, signalling that the sequential unit under test and the reference unit are in the same conditions.
Consider now the case wherein the integrated units 1 and 2 are not provided with common set and clock inputs, each one of the four flip-flops having, instead, a single data input D and a single clock input C. In this case the supervision circuit 40, indicated at FIG. 1a, comprises four flip-flops 41, 42, 43, 44 having their set inputs S connected, through the input leads 45, 46, 47 and 48, to the four individual clock inputs of the reference unit C',,, C,, C C not shown in the Figure, which are assumed to be connected to the so indicated lead. The outputs U of the four flip-flops are connected to the inputs of an AND gate 50 having the output connected to the output 49 of the supervision circuit, and therefore connected to the second input of the NAND gate 21 as indicated by arrow (21). A common reset input, connected by the lead X to the push button 23 of FIG. 1 may reset all the flip-flops to the low position.
In the initial conditions the four flip-flops are in the low condition, and deliver a ZERO value at all their outputs. Therefore, output 49 is also at ZERO value, and the error alarm is inhibited. Any time a pair of corresponding flip-flops in the unit under test and in the reference unit are put in the same state in response to a ONE signal on a clock input,the corresponding one ofthe four flip-flops 41 to 44 is set in the high" condition, and one of the inputs of the AND gate 50 goes over from ZERO to ONE. When each one of the clock inputs has received at least one clock signal, all flipflops 41 to 44 have been put in the high condition, all the inputs of the AND gate 50 are ONE, and the output 49 is ONE. On the other hand, when this condition is fulfilled, the pattern of the states of the flip-flops in the refernece unit and in the unit under test is the same, provided the unit under test is operating faultlessly.
. Thus, the inhibition of the alarm signal is removed, and
the test may go on. In case the unit under test is faulty, and does not respond as required to the clock and data signals, so that some one of the flip-flops of a pair is not in the same state, as the other one, an alarm will be given as soon as the inhibition is removed.
From the above example it is easily understood how to design the supervision circuit according to the number, type and control means of the flip-flops contained in the unit under test.
Thus, if the flip-flops contained in the sequential units are of the Set-Reset type, in which a ONE signal applied to either one or to the other of the two inputs, sets the flip-flop either in the high or in the low condition, the supervisor circuit will comprise, for each pair of Set and Reset inputs of the sequential unit, an OR gate with two inputs connected to said Set and Reset inputs, the output of the gate controlling a flipflop, as the flip-flop 32 of FIG. 1.
If the flip-flops of the sequential unit are of the J-K clocked type, they are set in a definite position only when, for instance, a- ONE signal is applied to one of said inputs, and a ONE signal is applied to the clock input. If a signal ONE is applied to both I and K inputs, the flipflop is not put in any definite position, because, in'this condition, as known, the flip-flop change position at each clock signal. Therefore the logical threeinput network, which controls a flip-flop corresponding to flip-flop 32 of FIG. I, should have the following truth-table:
JKCU JKCU 0000 I000 0010 1011 0100 1100 011] I110 which corresponds to the logical function U JKC JKC. The supervision circuit (shown in FIG. 1b) therefore comprises this logical network, including two inverters 35 and 36, two AND gates 37 and 38, and the OR gate 39, having the output connected to the SET input of flip-flop 55, having the output connected to output lead 54 and the reset input connected to input 58.
FIG. 2 illustrates thecase wherein the reference sequential unit comprises a shift register, formed by four flip-flops F F F E of the master-slavetype. As known, each flip-flop is provided with an informa tion input D, a clock input C, and an output O which is connected with the data input D of the following one. The four outputs Q are also connected to four external terminals U U Each master-slave flip-flop consists substantially of two flip-flops: a masterland a slave, of which the first one is controlled by the rising front of the clock signal, and the second one by the falling front of the same.
The binary value applied to the input D is stored in the first master flip-flop in response to the rising front of theclock pulse, the second slave flip-flop remaining in the former state. In response to the following falling front of the clock pulse the said binary value is stored in the slave flip-flop, and therefore appears at the output Q of the first master-slave, and is applied to the input D of the second one. At this time, a new information value may be applied to the input I, that is, to the data input D of the first master-slave. In response to the following clock rising front, the information applied in D is recorded in the first master, and the one applied to D is recorded in the second master. At the following second falling front of the clock signal, the information proceeds from the first master into the first slave, appears at O and is applied to D the one recorded in the second master goes into the second slave, appears at Q, and is applied to D It is clear that after four subsequent complete alternations of the clock signal the information value pres ent at input I at the moments of the four subsequent rising fronts have been recorded into the four masters and that, at the moment of the fourth falling front these values are now recorded in the four slaves, and appear to the outputs U to U As, during this operation, the'values applied to the input I of the reference unit have been the same as .the ones applied to the input I of the unit under test,'and if this. unit operates correctly, all previous difference possibly existing between the values recorded in the register has been erased, and the pattern of the binary values existing at the outputs U, to U, is the same for both units.
The supervision circuit therefore only has the task of checking whether, from the beginning of the test, there have been at least as many complete alternations of the clock signal as are the master-slave flip-flops contained in the unit under test. In the example considered, (FIG.
2) the supervision circuit is indicated by 101, and comprises an input 102 connected parallel to the clock input CC of the reference unit. It is connected to the first input of an AND gate 103 having its second input connected to the input of an inverter 107, having the input connected to the output 108 of the supervision circuit. The circuit comprises a counter 104 having an output U delivering initially a ZERO value, and on which a value ONE appears when four complete clock signals have been applied to the input I. When this happens, the output of inverter 107 inhibits the AND gate 103 and the counter remains in the caught up state until it is reset to Zero by a signal applied to the reset input R connected to input terminal 109. Therefore this supervision circuit will remove the inhibition of the alarm signal when the register under test and the reference register have been loaded with the same data.
FIG. 3 considers the more complex case of a semiconductor memory contained in an integrated unit, indicated as a whole by reference numeral 60, and represents only the reference unit. It contains 16 words P to P having four bits B0 to B3 each, and is provided with the following inputs:
a memory enabling input AM, four address inputs A to A a write enable input AS, four data inputs D to D and four outputs U, to U When input AM is at the value ONE, the memory is enabled, and an address of four bits may be applied to the four address inputs A to A for selecting one out of 16 Words. If the write-enable input AS is ZERO, the values recorded in the four storage cells of the selected word appear at the outputs U to U;,.
When the writing is enabled (AS to ONE) the four data bits applied to the inputs D to D are written in the four storage cells of the selected word. The description of other devices and operations proper to semiconductor memories is omitted as they are not relevant for an understanding of the present invention. When the reference memory unit is connected by the gripper to the unit under test, each time a pattern of four bits is applied to the address inputs of the two units, while the memory enabling input and the write-enable input are at value ONE, the bits applied to the four data inputs are recorded in the selected word, both in the unit under test as in the reference unit, if the former operates correctly: and from this moment on the four storage cells of this word in both units will record the same bits, being subject to the same signals.
To be sure that the unit under test andthe reference unit are in the same state, it is required that all 16 bit patterns, which address all 16 words, have been applied at least one time to the four address inputs, the enabling inputs being both at level one.
In FIG. 3 the supervision circuit is indicated, as a whole, by reference numeral 61. It comprises four inputs 62, 63, 64, and 65 connected in parallel to the address inputs A A A A and two inputs 66 and 67 connected respectively to the memory enable input AM and to the write-enable input AS. Each one of the inputs 62 to 65 is connected to the first input of four AND gates 70, 71, 72, 73, having their second inputs parallel connected to the output of an AND'gate 74 v having its two inputs connected to the inputs 66 and 67 of the supervision circuit, that is, to the AM and AS enabling inputs. 1
When AM and AS are both at the value ONE, that is, the memory and the writing are enabled, the output of AND gate 74 enables the AND gates 70 to 73 to transmit the signalsapplied to their first inputs. The output of these AND gates are applied to the inputs of a four-input, l6-outputs decoder 76. Each output is applied to a Set input of one of 16 flip-flops to 95, of which only the first and last are shown in the figure, having their output U connected to the inputs of a 16- input AND gate 97. The output of this gate 97 is connected to the outputs 98 of the supervision circuit 90, and this output, as already explained, may enable the test circuit to deliver the alarm signal, if its output is at level ONE. This happens when all flip-flops 80 to 95 have been set in the high" condition, that is when they have received at least one ONE value at their set input. This happens only when all the 16 possible patterns of addressing bits have been applied at least one time to the four inputs 62 to 65, with inputs 66 and 67 at value ONE.
The 16 flip-flops 80 to may be reset in the low position by a reset signal applied to input 96, which controls all the reset inputs of the flip-flops.
It may happen that some of the 16 words of the storage units are not used, and therefore, the running program, during the test operation, may not apply the corresponding address to the address inputs. In this case, according to the conditions, a ONE signal may be applied by suitable means to the inputs of AND gate 97, which are not used, or either, the program used must be designed for delivering the addresses even of the words not in use. These examples quickly consider all the types and modes of application of integrated sequential circuital units. There is, however, a peculiar case, rather uncommon, in which no one of the above mentioned circuits and modes of operation may be suitable, and in this case the supervision circuit must be based on a rather different principle.
This is the case of a cyclical sequential circuit not provided with a reset input. A circuit of this type, when driven by a series of clock pulses, goes through the different states forming a closed loop, and therefore delivers at its outputs a sequence of patterns of binary values which is repeated after a definite number of clock pulses. It may happen that, during the test of a circuit of this type, the reference unit connected in parallel to its terminals is not in the same state as the unit under test, and therefore delivers at its outputs, at the same steps, a pattern of binary values different from the ones delivered by the unit under test. If the unit is provided with a reset input, the difficulty is easily overcome, as the supervision unit will enable the alarm signal only after a reset signal has been received by both units.
In the case which is practically not common, that no reset input is available, the unit under test and the reference unit will go on along the same cycle in response to the same clock pulses, but if they are initially out-0fstep, there is no means of setting them in step, that is, at the same state of the cycle, and, even if they operate correctly, there will be differences in binary values at the corresponding outputs, and therefore an alarm signal will take place. FIG. 4 shows how it is possible to solve this difficulty.
The sequential cyclical reference unit is indicated by 110, and is provided with a clock'input C and four outputs U,,, U,, U U' connected to the four second inputs of the logical test channels 11, 12, 13, 14, having connected at their first inputs, the outputs U U U U, of the unit under test, not shown.
The outputs l5, l6, l7, 18 of the test channels are connected to the inputs of the NAND gate 20; as in FIG. I, the same reference numbers indicate the NAND gate 21 for inhibiting the alarm signal, the flipflop 22, the signalling lamp 24 and the reset push button 23. It must be remembered that, in the preferred embodiment of the invention, as described in the cited copending application, and as assumed to be embodied in the examined example, the output of the NAND gate 20 delivers a binary ONE in case of discordance between the values of the two inputs of at least a test channel having a duration higher than a predetermined value.
The supervision circuit 120 is provided with a clock input 119 connected to the wire leading, by means of the known gripper device, to the input C of the unit under test, and comprises an AND gate 122 having a first input connected to this clock input 119, the output connected to a clock output 123, leading in turn to the input C of the reference unit. Therefore the reception of the clock pulses by the reference unit may be inhibited by the AND gate 122 by means of its second input connected, through the inverter 124 and terminal 127 to the output of NAND gate 20. The supervision circuit comprises in addition a one-shot circuit 125, which is set in the high" position at the beginning of the test, by a signal applied to input terminal 126, and sent by the reset push button 23. In the high position the inverted output U of the one shot 125 delivers a ZERO value to the output terminal 121, inhibiting the alarm signal.
FIG. shows the diagrams of the binary values at different points of the circuit. It is assumed, for instance, that the cyclical unit is such as to let a ONE value appear at each pulse, and for the interval separating two subsequent pulses, at each one on the output U U U U in orderly succession.
The diagram shows the sequent of the clock pulses C C C C repeated three times. The diagrams U U U U show the sequence of the binary values at the outputs of the unit under test. Diagram C shows the sequence of the clock pulses effectively applied to the input C of the reference unit, and the diagrams U U U U' show, in solid line the effective sequences of the binary values at the corresponding outputs of the reference unit. The diagram N shows the succession of binary values at the output of the NAND gate 20.
It is assumed that initially the reference unit is out-ofstep with respect to the unit under test, by two steps: that is, that, while for the latter the first clock pulse is C (which causes the output U to go to ONE, and the output U to go to ZERO), the other outputs remaining at ZERO for the reference unit this pulse acts as pulse C (which brings to ONE output U and to ZERO output U the other outputs remaining at ZERO). The dashed lines represent the pulses in case all the clock pulses were received by the reference unit, and the two units would proceed out of step.
As soon as the first clock pulse is received, the outputs assume the values to be read in correspondence with the vertical line P there is discordance of values between U and U and between U and U therefore the output of NAND gate goes to ONE and the gate 122 is inhibited.
At the following clock pulse C 1 the output of NAND gate 20, by effect of the delay introduced by the delay lines of the test channels, is still at ONE, therefore this clock pulse is not received by the reference unit, which remains in the former state, whereas the unit under test goes to the following state.
In this condition, the binary values of the outputs may be read in correspondance of the vertical line P there is discordance between U and U' U and U' Therefore, as the unit under test receives the clock pulse C the reference unit does not receive any pulse, and remains in the former state. In this condition, as may be seen along the line P there is agreement of values on all outputs. The output of NAND gate 20 returns to ZERO, the AND gate 122 is enabled, and the subsequent pulse C is received also by the reference unit as pulse C' because it follows C' The two units are now in step and may proceed so along the cycle. Thus, by preventing the reception of clock pulses by the reference unit, and letting it lose some steps, the difference in steps is removed, and the two units are brought in step.
During this process, the alarm signal is inhibited, because the one-shot is in the high position.
It is not suitable to enable the alarm signal immediately after the first agreement between all corresponding outputs of the cyclic units, because the simple agreement at one or two steps is not enough to guarantee that both units are in step.
A defective operation of the unit under test may cause a perturbation of the cycle of the unit under test, thus preventing the falling in step of the units, and causing the periodical or erratical appearance of discordances. However, even if the unit. goes along the correct cycle, a faulty output may periodically deliver a wrong value and cause a discordance to appear. This causes an error signal to be delivered by NAND gate 20, which disturbs the stepping of the reference unit.
In any case, it is self-evident that every fault will prevent the falling in step of the two units, whereas, by the operation on the described supervision circuit, two correctly operating units will fall in step after a certain time. Therefore, the one-shot I22 may return to the low position after a reasonable length of time, delivering a ONE value to output 127 and enabling the alarm signal. If the unit under test is operating correctly, by this time both units will be in step, the corresponding outputs will be in agreement, and no alarm signal will be generated. In the contrary case, the emission of an alarm signal will reveal, with practical certainty, that the unit under test is faulty.
It has been found that, even in the most unfavorable case, both units, if they operate correctly, will fall into step after a number of cycles of the tested unit not greater than the number of steps per cycle. The time after which the one shot may return to the low condition may be thus established substantially as the time corresponding to a number of pulses equal to the square of the number of steps per cycle. For instance, in the case where the cycle comprises 128 steps, each step during two microseconds,.the time corresponding to 128 X 2 cycles is approximately 32 ms, which is clearly admissible.
In special cases, when the interval between subsequent clocks is considerable, and the number of steps is very high, this rule could lead to a return time of the one shot which is too long for practical requirements.
However, it is usually possible, by analyzing the cycle of the sequence of signals at the outputs of the cyclical unit, to establish the maximum number of clock pulses which are required to put both units in step. It has been found that, on the average, this does not exceed the number of clock pulses equal to twice the number of steps per cycle.
In this case, as shown by FIG. 4a, the suprvision circuit may comprise, in place of the one-shot, a counter 129 driven by the clock input 119. This counter will give the value ONE at the output 121 only after receiving the predetermined number of clock pulses, thus enabling the alarm signal, and will be maintained in this condition by an inhibiting input 1 controlled by the ONE signal on the output 121. The counter may be reset to zero by a reset pulse applied to input 128.
It may happen that a cyclical sequential circuit goes along a cycle which does not comprise all possible states of the circuit: in this case the unit under test, and the reference unit, even if identical, may, in case of an accidental difference between their respective starting position, go along different cycles and therefore never fall in step. In this case, the test device will signal this condition as a fault, emitting the alarm signal. However, it is evident that, if this is the case, the apparatus including such cyclical sequential unit could not operate correctly if the unit is not provided with a reset input to establish without doubt the starting position and the cycle to follow.
A particularly simple case of cyclical sequential until is the switching flip-flop, that is, a flip-flop which changes state at each clock pulse, as a J-K flip-flop having both inputs at ONE. In this case the one-shot 125 should have a return time not lower than two clock intervals.
FIG. 6 shows schematically a possible embodiment of the invention corresponding substantially to FIG. 6 of the cited copending application. It shows the testing apparatus comprising a gripper 142 which may be applied to the circuit unit 152 to contact its pins, and the wires of the flexible cord 141. Reference number 44 indicates the container of the test channels, which is provided, in addition to other components which are irrelevant to this description, with a reset push button 151, an alarm lamp 150 for signalling a fault, and a lamp 155 for signalling the enabling of the alarm signal.
There is, in addition, a socket 145 provided with plugs 146, 161 and 162, wherein a pin support 147 may be plugged. The pin support 147 carries, in addition to the reference sequential unit 149, also the supervision circuit 160 associated with this unit, which will be conveniently obtained in form of an integrated unit, and contained in a package of the same standard type as the reference unit. When the type of sequential unit under test is changed, and therefore the pin support carrying the reference unit is also changed, the supervision circuit suitable for such sequential unit type is at the same time also automatically provided.
It may be seen that, in the great majority of cases of sequential units, two additional pins, and two additional plugs 16] as those needed for purely combinatorial units must be used: that is the pin and plug and the plug for the output of the supervision circuit and the pin and plug for the input of the reset signal. Only in the case of cyclical units, as considered in FIGS. 4 and 4a, a third pin and plug connection is required, for the input of the error signal delivered by the NAND gate 21.
What is claimed is:
1. An improved test device for electronic circuit units, having a plurality of input and output leads, and mounted on digital electronic apparatus, comprising a reference circuit unit similar to the circuit unit under test, at least a comparator circuit having two input and one output leads, means for temporarily and singularly connecting each input lead of a circuit unit under test to the corresponding lead of the reference circuit unit, and for connecting at least one output lead of said circuit unit under test to a first input lead of said comparator circuit; means for connecting the corresponding output lead of the reference circuit unit to the second input lead of said comparator circuit, the comparator circuit delivering a discordance signal whenever two signals of different binary level are applied to the input leads of said comparator circuit; timing means for transmitting only the discordance signals exceeding a predetermined time interval; means for memorizing the transmitted discordance signal, and means controlled by said memorizing means, for emitting an alarm signal,
the improvement comprising a supervision circuit having input leads for receiving at least part of the signals applied to the input leads of the unit under test, and means for inhibiting the memorizing of said dicordance signal under control of signals delivered by said supervision circuit,
said supervision circuit disabling said inhibiting means when the reference unit has received all signals needed for setting all memory elements comprised therein in the same state as the memory elements comprised in the unit under test in case of correct operation of the unit under test in response to the received signals.
2. An improved test device as claimed in claim 1 wherein said signals received by said supervision circuit are at least part of the signals applied to the circuit unit under test for controlling the memory elements comprised therein.
3. An improved test device as claimed in claim 2, wherein said supervision circuit comprises memory elements controlled by at least part of said signals applied to the circuit unit under test for controlling the memory elements comprised therein.
4. An improved test device as claimed in claim 2, wherein the signals applied to the reference unit for controlling the memory elements comprised therein are under the control of said supervision unit, said supervision unit being able to inhibit the receiving of at least part of said signals under control of the discordance signal, for modifying the progression of the set of memory elements of the reference unit along a succession of state combinations, for reaching a condition whereby the set of memory elements contained in the unit under test and the set of memory elements contained in the reference unit are in the same combination of states.
5. An improved signal device as claimed in claim 4, wherein the inhibiting of the memorizing of the discordance signal is disabled by the supervision unit after a predetermined time interval from the beginning of the test of the unit under test.
|Citing Patent
|Filing date
|Publication date
|Oct 3, 1974
|Mar 23, 1976
|Fluke Trendar Corporation
|Logic test unit
|Sep 3, 1974
|Aug 24, 1976
|Hewlett-Packard Company
|Apparatus and method for testing digital circuits
|Apr 22, 1974
|Oct 19, 1976
|Stewart-Warner Corporation
|Bulb outage warning system
|Oct 29, 1976
|Jul 11, 1978
|Westinghouse Electric Corp.
|Monitoring circuit
|Aug 2, 1977
|Oct 31, 1978
|Burroughs Corporation
|Asynchronous digital circuit testing system
|Sep 2, 1977
|Feb 13, 1979
|Burroughs Corporation
|Asynchronous digital circuit testing and diagnosing system
|Apr 6, 1979
|Jan 6, 1981
|General Instrument Corporation
|Microelectronic device and method for testing same
|Mar 23, 1979
|Jun 2, 1981
|John Fluke Mfg. Co., Inc.
|Universal analog and digital tester
|Oct 19, 1979
|Feb 23, 1982
|Vlsi Technology Research Association
|Method and device for testing a sequential circuit divided into a plurality of partitions
|May 12, 1980
|Mar 1, 1983
|Tektronix, Inc.
|Signal measurement apparatus
|Jan 2, 1985
|Mar 31, 1987
|Rodrigues John M
|Tri-state in-circuit logic comparator with automatic input/output terminal discrimination
|Oct 1, 1984
|Sep 20, 1988
|Tektronix, Inc.
|Method and apparatus for improved monitoring and detection of improper device operation
|Sep 18, 1989
|Jan 22, 1991
|International Business Machines Corporation
|High level clamp driver for wire-or buses
|Jan 18, 1996
|Apr 25, 2000
|Luk; Fong
|System configuration and methods for on-the-fly testing of integrated circuits
|Mar 1, 1999
|Sep 17, 2002
|Formfactor, Inc.
|Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
|Dec 31, 1998
|Sep 24, 2002
|Formfactor, Inc.
|Special contact points for accessing internal circuitry of an integrated circuit
|Mar 1, 1999
|Nov 12, 2002
|Formfactor, Inc.
|Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
|Mar 1, 1999
|Dec 24, 2002
|Formfactor, Inc.
|Distributed interface for parallel testing of multiple devices using a single tester channel
|Jul 29, 2002
|May 6, 2003
|Formfactor, Inc.
|Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
|Dec 29, 2000
|Jul 22, 2003
|Formfactor, Inc.
|Special contact points for accessing internal circuitry of an integrated circuit
|Jul 10, 2000
|Aug 5, 2003
|Formfactor, Inc.
|Closed-grid bus architecture for wafer interconnect structure
|Dec 29, 2000
|Aug 5, 2003
|Formfactor, Inc.
|Special contact points for accessing internal circuitry of an integrated circuit
|Nov 6, 2002
|Jan 13, 2004
|Formfactor, Inc.
|Distributed interface for parallel testing of multiple devices using a single tester channel
|Dec 29, 2000
|Sep 6, 2005
|Formfactor, Inc.
|Special contact points for accessing internal circuitry of an integrated circuit
|Apr 27, 2004
|Oct 2, 2007
|Formfactor, Inc.
|Closed-grid bus architecture for wafer interconnect structure
|Oct 2, 2007
|Mar 24, 2009
|Formfactor, Inc.
|Closed-grid bus architecture for wafer interconnect structure
|Apr 20, 2010
|Jun 14, 2011
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|Closed-grid bus architecture for wafer interconnect structure
|Dec 29, 2000
|Sep 13, 2001
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|Special contact points for accessing internal circuitry of an integrated circuit
|Apr 27, 2004
|Jan 6, 2005
|Formfactor, Inc.
|Closed-grid bus architecture for wafer interconnect structure
|Oct 2, 2007
|Jan 31, 2008
|Formfactor, Inc.
|Closed-grid bus architecture for wafer interconnect structure
|Apr 20, 2010
|Oct 21, 2010
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|Closed-grid bus architecture for wafer interconnect structure
|Aug 2, 2012
|Jun 20, 2013
|Hon Hai Precision Industry Co., Ltd.
|Testing system and method for testing electronic device
|Feb 7, 1996
|Aug 14, 1997
|Martin Kuboschek
|Evaluation of test responses from digital integrated circuits
|Feb 7, 1996
|Apr 29, 1999
|Martin Kuboschek
|Verfahren zur Auswertung von Testantworten zu pr�fender digitaler Schaltungen und Schaltungsanordnung zur Durchf�hrung des Verfahrens
|May 22, 1989
|Dec 6, 1989
|Philips Electronics N.V.
|Electronic module comprising substrate elements
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification


text:
Defense focus of Boise State recruiting efforts
Associated Press | Last updated February 06, 2013
For the second straight year, Boise State coach Chris Petersen has focused recruiting efforts on defense. Defensive players account for 16 of the 21 new recruits who signed letters of intent Wednesday to play for the Broncos this fall. The Broncos are coming off an 11-2 season and were supposed to join the Big East this year. But the school backed out of those plans, opting instead to remain in the Mountain West Conference. The 2013 recruiting class includes five cornerbacks, four linebackers, six linemen and a safety. Some of those players signed on last year and are now enrolled in school. On the other side of the ball, Petersen signed quarterback Ryan Finley from Phoenix, along with two wide receivers, two tight ends, two linemen and a running back.
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text:
Port 68 Fleur De Lis Ornament in Gold-Set of 5
Port 68 Fleur De Lis Ornament in Gold-Set of 5
Free Shipping!
Product ID: 15850
The fleur de lis is the iconic symbol of Louisville, New Orleans, Florence, Italy and France. A wonderful antique inspired object for your wall, or nest in a bowl for a French tableau.
The back side of the fleur de Lis has a hidden ring which allows you to use this as curtain hardware. Simply move your curtain hook to the front of the fabric, hook and hang as a curtain panel.
Sold as a set/5
Materials: Polystone
|Product ID
|6H x 5 W x 2D
|Port 68
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text:
A pantomime of feelings to preform,
without a cast or crew,
the thunder's closing quickly now,
but soon it will be through
A sea of broken bones to cross
with out a rowing boat
We fear to plunge in mindlessly
in case our heavy hopes don't float
A vanity encased in a worn out silver box,
Locked away beside it too, is a mind degrading pox
A fierce and bitter envy,
starved to death it seems,
without a single trace of what friendship really means
A whisper in the courtyard,
as the hangman does his deed,
A strained and awful tear,
for the knight that lost his steed
A single dance of pity
for the maid without a lord
And a lonely drawn out symphony,
for the injured in the wards.
Our cries for help left unanswered,
by those in mortal shells,
with only cries of vengeance from those that promise hell.
A single purple rose
upon a shattered frozen tomb,
does bring about the honesty that healing comes,
© Copyright 2017 EwanMac. All rights reserved.
Status: Finished
Genre: Other
Oh my god, this is craaazy good :O seriously... because parts of it are really sad but it's optimistic too? I think, especially considering the last line
Just.. everything about it is so nice! I'm going to read it again after this comment, maaaany times........
Gah I've missed your writing :P such a nice name too, clap clap EwanMac
Beautiful written EwanMac.10/10 smiles Chiqui
Book / Romance
Book / Romance
Book / Fantasy
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text: Patton Oswalt's 8-minute Episode VII pitch is delightfully insaneRob Bricken4/17/13 12:20pmFiled to: this is awesomepatton oswaltstar warsparks & recepisode viitelevision10913EditPromoteShare to KinjaToggle Conversation toolsGo to permalink Patton Oswalt makes an appearance in this Thursday's episode of Parks & Rec. But here's what you won't see — an 8-minute deleted scene of him filibustering a Pawnee town meeting by describing his plan for Star Wars: Episode VII, which involve not only involve Boba Fett and Lando hooking up with Leia, but the Avengers. Advertisement It's pure improv, and it's completely amazing. Honestly, Disney and Abrams could do a lot worse.Reply109 repliesLeave a reply


text:
Time to do a total overhaul of my branding and website, because my current site is two years old, which is about 200 in Internet Years.
(The background image is part of a potential header, in case you were wondering!)
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Reviewed by: George G, October 2016
Our guide was excellent. Extremely knowledgeable and very personable. A great day.
Reviewed by: Pamela F, June 2016
It was great. Kate was a very knowledgable guide and provided excellent service. Her passion in her profession and about the area in which she specializes was second to none.
Reviewed by: Alison H, United Kingdom, December 2015
This was quite the most amazing trip I have ever done..so pleased a that I booked it. We took our American friends to Normandy as a 50th wedding anniversary treat..and I booked this day as the highlight of the 4 day trip. It could not have been better..we were picked up from our hotel by our guide Phillip who was the best..very comfortable people mover and he worked so hard to give us a day to remember..he planned our day round places and things we asked to see and added so much more into the mix . I hadn't realised just how big the area was to cover but he did it and kept us enthralled all day with the history and stories. One of our group had mobility issues and Phillip was so respectful and helpful..finding the best places to park and knowing how much of a particular activity that he would be able to manage...excellent. Point du Hoc was probably the most moving and difficult to traverse..the German battery was in redible to see and hear about and the weather joined in to give us a real feel for what it might have been like for our brave troops..Phillip had a wealth of knowledge and a good British sense of humour which went down well with us all..he was good company and excellent at his job..but it didn't seem like a job..he was delightful and took us to a restaurant for lunch that we would never have found ourselves...so many things we did that day we wouldn't have seen or even thought of seeing if we hadn't been on this trip. The German cemetery was one of them..we wouldn't give but for Phillip and I am so glad that we did..a very sombre place but essential to look at the other side too....very moving.
We wanted to find some personal graves too and Phillip sourced those for us making the whole thing much easier...I seriously would have booked another day if I had known just how good this would be...don't hesitate..it is excellent value to have such a personal experience and it is one the 4 of us will ever forget...thank you
Reviewed by: Nancy M, November 2015
Our guide was wonderful. His english was perfect and his knowledge of the events leading up to and during the Normandy Invasion was superb! We were out site seeing all day and it wasn't enough. We could easily have had another day or two with him. Thank you!
Reviewed by: Judy H, October 2015
Our private tour of the Normancy Landing Beaches was an incredibly special day. We truly appreciated Ann-Sophia researching information pertaining to our family about D-Day and incorporating that into our tour. She was incredibly knowledgeable and brought the WWII history to life for us. Her itinerary for the day could not have been better planned out. Truly an emotional and special day that we will always have in our memories. Booking the tour and connecting with Ann-Sophia the morning of our tour could not have been easier. Thank-you for a memorable day Ann-Sophia!!
Reviewed by: Charles F, September 2015
This was amazing. Kate was our guide for the day. She is passionate about history! Her great grandmother's personal story about the German soldiers who lived with her for 4 years is inspirational to what the French endured during the war. It is humbling to have walked where so many young men lost their lives to make the world a better place. Kate made the whole trip. She is super sweet and better than any history book or movie. Outstanding Trip!
Reviewed by: wfjulavits, June 2015
Well organized, efficient and informed representative for one day tour for us two couples.


text:
magento site replication
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- Budget $30 - $250 USD
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I have bought a magento theme and site installed and i would like the site to look and have similarities to this website
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item properties as well as a similar look, don't want it to look exactly but very similar and with a different color scheme.
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The system is broke - we need to fix it. Open Government has the opportunity to re-build the trust needed between politicians and citizens to make their communities better than they are. An open gov framework focusing on principles of transparency, accountability and citizen participation allows strategic directions to be set and innovative initiatives to address the goals of the framework.


text:
Abu Simbel Profanation
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DescriptionThe protagonist, Johny Jones, have been mutated by the curse of Abu Simbel, becoming a strange creature that only conserves his enormous nose of his old appearance.
In order to get rid of the curse he is forced to travel to Egypt to the pyramid where is the tomb of Abu Simbel, and where it must arrive after discovered the keys that will lead him to this place. If he obtains it, he will recover his normal appearance.
As logical, the pyramid is filled of traps and strange creatures who will suppose a serious obstacle for our pretensions, and the only weapon is our skill to be jump from a side to another one without falling in the claws of our enemies, or the traps that are in all places. He can do long or short jumps, according to the situation in which one is.
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|Modern games are too easy? Try Abu Simbel!
|ZX Spectrum
|666gonzo666 (56150)
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|Computer Emuzone
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|Dec 07, 2000
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CompetitionKnown for its legendary difficulty level, the developers awarded a prize of 50,000 pesetas to the first player who completed the game and was able to read the sentence Nos veremos en el Polo.
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In a memorandum opinion issued in Principal Life Insurance Company v. Lawrence Rucker 2007 Insurance Trust on June 26, 2012, a federal district court applied the Delaware Supreme Court's holding in PHL Variable Life Insurance Co. v. Price Dawe 2006 Insurance Trust ("Price Dawe") to reverse an earlier order voiding a policy for lack of insurable interest. The Rucker opinion, which concerned a beneficial interest transfer transaction, recognizes that under Price Dawe, a policy is not void either because the insured intended to sell it on the secondary market or because the insured obtained the policy through premium financing. Ultimately, in undoing the prior order granting summary judgment in favor of the insurer, the court found that there was conflicting evidence surrounding the procurement of the policy that would have to be resolved by a jury.
The implications of Rucker are, for the most part, positive for investors. Most importantly, the case interprets Price Dawe as permitting insureds to use premium financing to procure policies without violating insurable Delaware's interest laws. This is significant because the Price Dawe opinion contains broad and ambiguous language possibly putting the validity of premium financed policies in question. Specifically, the Delaware Supreme Court noted that "if a third party funds the premium payments by providing the insured with the financial means to purchase the policy then the insured does not procure or affect the policy." While that language might have been construed to cover premium finance transactions, the Rucker court held that under Price Dawe, "an insured's ability to procure a policy is not limited to paying the premiums with his own funds; borrowing money with an obligation to repay would also qualify as an insured procuring a policy." Rucker is, of course, a trial court opinion with limited precedential value; but its express limitation of Price Dawe's sweeping language is nevertheless important. On a less positive note, the Rucker court's decision highlights the fact-intensive nature of the inquiry needed to ascertain the existence of an insurable interest. This may prevent investors from quickly (and cheaply) prosecuting or defending suits to enforce their contract rights.
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Pharmacists reminded of need to be vigilant in preparation of dose administration aids
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June 20, 2014
Pharmacists have been reminded of the need to follow correct standards and procedures in the preparation of dose administration aids (DAAs) following a warning from the Pharmacy Board of Australia over a medication incident involving the drug methotrexate.
The Board said this resulted in a death and while the medication was dispensed correctly, the resultant packaging of the drug into a dose administration aid by a pharmacy technician was incorrect and the packing error was not detected by the pharmacist.
National President of the Pharmaceutical Society of Australia (PSA), Grant Kardachi, said DAAs were extremely effective in assisting in compliance and adherence to medication regimens but pharmacists needed to be robust in their procedures.
"PSA has in place guidelines and standards for DAAs and these were developed to help ensure a DAA service meets the safety and quality requirements of professional practice," Mr Kardachi said.
"These standards and guidelines stipulate that a pharmacist should introduce procedures for quality control, quality assurance and monitoring of DAA provision.
"They also say audits should be carried out before starting a DAA service and at six-monthly intervals. The performance and results of these activities should be recorded together with any action taken, or outcome."
Mr Kardachi said millions of DAAs were prepared annually in Australia and were proven to be highly effective in improving the nation's health, with non-compliance of medicines still a major factor in adding significant costs to the health system.
"Pharmacists every year actually prevent thousands of medication mishaps through DAAs and the case highlighted by the Pharmacy Board is a rare, but unacceptable, incident," Mr Kardachi said.
"I would also remind pharmacists involved in DAAs to have a separate area of the pharmacy dedicated to this work so that all those involved in the preparation and checking of DAAs are able to work in an environment that allows the standards and guidelines to be met.
"As detailed in PSA's Code of Ethics, patient wellbeing and their health outcomes are paramount for everything that pharmacists do and DAAs are no exception."
Mr Kardachi said PSA had also developed four checklists in its guidelines to assist pharmacists with:
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April 17, 2015 4:13 pm
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Today's guests on the Federal News Countdown:
– Alan Chvotkin, executive vice president and counsel, Professional Services Council – Bob Suda, president and senior consultant, Suda and Associates
Alan Chvotkin's stories #3 White House testing approach called for in draft cyber order From Federal News Radio:
The White House is trying to prove the theory behind its draft cyber executive order. The Obama administration is using two pilot programs to show how cyber information sharing with the private sector could work. The latest test case is with the owners and operators of the electricity critical infrastructure. Michael Daniel, the White House's cyber coordinator, said the Energy and Homeland Security departments are working with companies in the electricity sector to come up with a baseline set of cybersecurity standards.
#2 White House to government contractors: Stop human trafficking From GovExec:
President Obama has issued an executive order to increase oversight that prevents human trafficking resulting from government contracts, the White House announced Tuesday. The policy will seek to strengthen existing laws against government contracts going to companies involved in human trafficking by requiring contractors to provide more information about their foreign employees. It requires a compliance plan from any contractor or subcontractor whose foreign services exceed $500,000.
Sponsored content: Agency managers surveyed, many unsure about data storage or how to improve it. Learn more in our next generation data center survey.
Sponsored content: Agency managers surveyed, many unsure about data storage or how to improve it. Learn more in our next generation data center survey.
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#1 Senate conservatives may block sequester solution From Politico:
Not everyone in Washington is so desperate to avoid sequestration. A handful of Senate conservatives have been gaming out ways to block a deal, if they consider it a bad one – even if it means letting billions in across-the-board cuts go through, according to GOP sources on Capitol Hill. The issue: Republican budget hard-liners fear that the White House, congressional Democrats and their own party leaders will try to replace or forestall the cuts with budget gimmickry or new taxes. They worry that "fake" cuts – savings that would have happened anyway or other accounting tricks – will become increasingly popular, even for moderate Republicans, as the zero hour approaches for the Defense Department.
Bob Suda's stories #3 What would you do if you were in charge of RFP-EZ? From GovLoop:
Project RFP-EZ is one of five initiatives that are part of the Obama administration's Digital Government Initiative. The initiatives are led by Presidential Innovation Fellows — these are small teams that were being called in for a six-month stint to provide outside the box thinking to vexing problems. And the initiatives range from MyGov, which is tasked to reimagining the relationship between the federal government and its citizens through by essentially creating an online portal for the government.
#2 The long-awaited 'retirement tsunami' has begun From Federal Computer Week:
Remember the expected mass exodus of retiring government employees that was going to leave the government without its most knowledgeable, experienced hands? It's here.Recent data from FedScope shows that retirements have spiked recently, with a 45 percent increase governmentwide in the last quarter of 2011 compared to the same quarter of 2010.
#1 The mobile revolution could transform the next-generation federal workforce From Federal Computer Week:
It was one of the most popular — and endearing — YouTube videos of 2011: a baby trying to use a magazine the same way as an iPad. But to Jeri Buchholz, assistant administrator for human capital management at NASA, the video captured a glimpse of the future workforce, a tech-savvy generation never bound by office space or rigid work schedules.
Photos of the amazing, moving, important and amusing things happening in the federal community.
A daily update of important moments in the history of the U.S. government.


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Regional North America United States Texas Localities A Abilene Society and Culture
Subcategories 6
Related categories 1
Sites 21
Abilene Masons
Information about the three Masonic Lodges in Abilene.
Abilene Rotary Club
Include list of officers, membership, contact information, programs, calendar and announcements.
Abilene Southwest Rotary Club
Includes officers, announcements, calendar, and meeting information.
Alliance for Women and Children
Includes programs, history, contacts, and breast cancer awareness information.
Ben Richey Boys Ranch
Private, nonprofit basic child care facility. Includes history, mission, education, and activities.
Cactus Lions Club
Contacts, club history, membership, current events and fund raisers.
Camp Courage
Camp for children, first grade through 12 grade, who are dealing with loss due to a death, divorce, or other painful transition. Includes photographs, schedule, and applications.
Christian Homes of Abilene
Maternity Care, adoption services and foster care. Includes visual tour of the facilities.
Christian Women's Job Corps of Abilene
Helps women in need develop the personal, academic, career, and spiritual skills they need to become self-sufficient.
The Community Foundation of Abilene
Establishes permanent charitable endowments and provides a vehicle for donors' varied interests. Promotes local philanthropy and provides leadership and resources in addressing local challenges and opportunities. Scholarships and grants available.
Connecting Caring Communities
Exists to build meaningful relationships that foster safe, caring, whole communities. Provides history, mission, programs, and events.
Day Nursery of Abilene
State subsidized day care facility for newborns through age ten. Services and contact information.
Disability Resources Inc
A non-profit organization for developmentally disabled individuals, is a planned community designed to enhance the lives of the residents, develop their life skills, and provide the required medical care and a variety of therapies.
Elmwood West Lions Club
Includes meeting dates and times, charities supported, and list of officers.
Food Bank of West Central Texas
Frequently asked questions, volunteer opportunities, map of their service area, tour, and the history of the organization.
Global Samaritan Resources
International relief organization. Includes relief efforts, history, staff, and videos.
Hendrick Home for Children
Licensed 24 hour basic child care facility for children. For children who are drug free and do not possess severe emotional or behavioral problems. History, services, exes association and special events.
Junior League of Abilene
Includes contact information, projects, and information on the Junior League cookbook.
Texas Trails Council, Boy Scouts of America
Boy Scouting in the Abilene and Brownwood area. Council calendar and contact information. Camping at Camp Tonkawa.
United Way of Abilene
The largest non-governmental funder of health and human services in the community. Includes Helplines - a resource directory of human services in the area.
The YMCA of Abilene
Contact information. Lists of programs and services.
Last update:October 26, 2016 at 12:50:34 UTC
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St Peter Mancroft: east window interactive!
St Peter Mancroft, Norwich
Clickable notes are back! Hover over the photograph to read what the panel is. Click on the caption to go to an enlargement of it.
For more, see the Norfolk Churches Site.
St Peter Mancroft, in the heart of the city of Norwich, has one of the best collections of 15th century glass in England. It is collected together in the east window, above.
12,565 views
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Taken on April 13, 2007


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Louis Garneau Hat Cover
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From the streets to the rooftops
An all-Neapolitan debut for the new Milanese director Paola Randi
"Two years ago I visited a friend in Naples. One evening, I was
struck by a curious scene in Piazza Dante. On one side of the
square, a rabble of local boys were kicking a tennis ball around;
on the other side, a bunch of Sri Lankan kids were playing cricket.
This was the image I'd been looking for: I took it as a starting
point and built my film around it". So says Paola Randi
(40), a new Milanese director whose passionate directorial debut
Into paradiso comes out in February. The film is
described as a "story set in the Neapolitan areas of Quartieri
Spagnoli and Rione Sanità, where the city's Sri Lankan population
Zoraide Cremonini, Vogue Italia, December 2010 (n. 724), p. 52
English translation: Soget
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Vittoria Mentasti's Dead Sea takes us to a place where the sky and the sea are one
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A chat with Kristin Prim, the founder of The Provocateur, the site that publishes letters written expressely by leading women addressing the whole female world. Vogue.it presents you an exclusive preview of the letter written by Dresden Dolls' Amanda Palmer
Fashion shows are changing: Burberry and all that's new on the runways
Menswear and womenswear collections will walk together and will be on sale right after the show. These are the news from Burberry but the evolution is generalized: runway shows are changing


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Henley Manor
No prices found through our partners. Please contact the business directly or check some of our recommended alternatives.
TripAdvisor Reviews Henley Manor Cedar City
Travel Blogs from Cedar City
Day 78 - Zion is Spectacular!
... followed UT-9W on to UT-17W until we ran into I-15 again. About 12 miles up on I-15, we exited to the Kolob Canyon Visitors Center. It was about 4:30, and we were just going to stop and get our passports stamped. But the ranger said it was only a 5-mile scenic ride and it looked best in the late afternoon anyway. So we took the scenic ride to the overlook and it was beautiful. Where Zion was all about being in the valley and looking up ...
The Narrows
... we should probably just ride back down and go the the museum. Once at the top, at least the sun came out. We started down the Riverside Walk path along with a couple thousand other "hikers".
I was still nervous about what to expect having never been on this hike before. Looking at all the other people traveling this same route, it didn't look like they were any more prepared than we were. In the end, the trail dead ends into the ...
Yeeha Utah
We have spent a couple of days in Cedar City which is a small town in Utah. Firstly because its a good base to explore some great national parks and secondly because poor Darren was sick and I was sick of his driving. LOL Actually for an Aussie he does ok but it does get a bit scary when your hugging a cliff side and he tends to vere to the right all the time, he kinda has trouble keeping in the right lane for some reason. Theres been a few moments when ...
Canyons and camping
... the mountains curving around and opposite the top of the trail. As we approached, we saw the feature that gives this place its name. A thin layer of water was trickling over the edge of the rocks, reflecting the sunshine onto the wall behind. The heat of the day was searing, and standing under the droplets of water was the refreshing break we had craved since entering the park.
After our refreshing mini shower, we climbed back abroad and headed for the last stop ...
... vegetation was lush and the deer were out grazing. Siena of course got as close as she could to them.
Tomorrow before we head out to California we are going to rent inner tubes and float down the Zion river (creek) which meanders through the vast canyon. Its a 2.5 hour float and should be a nice activity before we pile into the Pilot once again.
The gift of Zion brings perspective and appreciation for nature and it's greatness.


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Gain access to discount* on volume orders of Surface Pro 3 (Available in the UK on 31st August 2014)
Retail pricing starts at £639**, however, there are volume discounts to be had in the commercial sector. If you want to revamp your hardware estate, manage your portfolio securely or simply improve the flexibility of your workforce get in contact with a Microsoft Authorised Device Reseller (ADR) who can provide a quote.
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Surface Pro 3 is pretty perfect if your a Mobile Professional. It has a very nice 12" display in a sleek magnesium frame with all the power and performance of a laptop, but in an incredibly thin, lightweight, versatile form. It features a pen experience which works seamlessly with One Note and all your favourite Office applications. It delivers the fast, fluid touch experience of a tablet but with a built-in, multi-angle Kickstand and optional click-in keyboard, it can also become the ultimate laptop in a snap. A 4th generation Intel® Core™ processor, full-size USB 3.0 port, microSD card reader, and Mini DisplayPort enable it to do anything your laptop can do and more.
*Size of discount goes up according to quantity bought, Please ask your ADR for quote. Minimum order for discount is 5 units
*Please speak with your ADR for commercial pricing. Please note that retail pricing includes pen but NOT keyboard.


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More information about this newspaper title may be available on the source website.
Source: Chronicling America [US Library of Congress]
Country: United States
State: South Carolina
City: Sumterville, S.C.
Issues of this title available in Elephind: 103
Items (articles and/or pages) from this title available in Elephind: 428
Earliest Date: 5 January 1870
Latest Date: 25 December 1872
The weekly Sumter Watchman and Southron (1881-1930) served the residents of Sumter County, located in the Midlands region of South Carolina, for half a century. Whereas the title of the Columbia-based Daily Phoenix conjured images of a community reborn, the Watchman and Southron alluded to the politically divisive years leading up to the Civil War. The word "watchman" recalled the partisan spirit of newspapers like the Greenville Southern Patriot and the Anderson Southern Rights Advocate, published in 1851 and 1852, respectively. "Southron," a Scottish dialect variant for "Southern," was an expression of identity used by Confederates.
The Watchman and Southron began as two weekly newspapers, the Sumter Watchman and the True Southron. Allen A. Gilbert and Horatio Lincoln Darr started the Sumter Watchman in 1855, merging the Sumter Banner and Sumterville Black River Watchman. The Sumter Banner had held the distinction of being one of Sumter's earliest and longest-running newspapers; several prominent citizens, including William Francis Baker Haynsworth, John Smythe Richardson, Jr., and James Sanders Guignard Richardson, had at times acted as editors and publishers. Gilbert and Darr also launched the SumterTri-weekly Watchman and the Sumter Semi-weekly Watchman. In April 1865, soldiers of the 25th Ohio Infantry Regiment briefly seized control of the Watchman and printed a single-issue newspaper called the Banner of Freedom before destroying its offices.
In 1866, Darr and Gilbert ended their partnership. Soon Darr launched a competing newspaper, the Sumter News in tandem with his former apprentice, Noah Graham Osteen. In 1873, Darr and Osteen changed the paper's name to the True Southron. Osteen and the Reverend Clinton Caper Brown bought out the Sumter Watchman which they merged with the True Southron to create the Watchman and Southron on August 2, 1881. The new owners borrowed a line from Henry VIII by William Shakespeare for the paper's motto--"Be just and fear not: let all the ends thou aim'st at be thy country's, Thy God's, and truth's." Editor Julius Andrew Mood stayed on for only two years, but his editorials proved popular with readers throughout South Carolina. Reverend Brown contributed columns on morals and religion. The Watchman and Southron bore witness to major events such as: the crop failures of the 1880s; the introduction of mills, manufacturing, and even a cocoonery in the local economy; and the creation of Lee County from Sumter County in 1902. The paper steered a reliably conservative, if unregimented, course, challenging Democrat Governor "Pitchfork" Ben Tillman's administration in the 1890s as doggedly as its predecessor, the True Southron, had criticized Reconstruction-era Republican reformers in the 1870s.
In 1909, the Watchman and Southron became a semiweekly paper. It was later absorbed by the Sumter Daily Item founded by Noah Osteen's son, Hubert Graham. The last issue of the Watchman and Southron appeared on January 1, 1930.
Provided by: University of South Carolina; Columbia, SC