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David Moyle Photographer
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About Me
Experience... I have dealt with the best and the worst... I love my job, and take it with a grain of salt... but there are some limitations to what I am willing to do... please do not inundate me with messages asking me to do nudes, porn, fetish... or any of the alike... I am secure enough with myself to be able to let you know that I'm not willing to show off what I have to world to make my mark... you either love me for me, or not at all...
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Haymish (Homemade) Challah
READY IN: 1hr 55mins
Recipe by unclemoishy613
This is an easy recipe that I adapted from a cookbook. I added more sugar, adjusted some of the other ingredients and made a few procedural updates and shrunk the recipe to fit in a 5-quart mixer. This is a recipe that I really love, and I try to have my own homemade challah (almost) every Shabbos. Tinker with the recipe yourself; I like very sweet, doughy challah, while you might prefer a more-baked, less-sweet version.
Ingredients Nutrition
- 8 cups all-purpose flour
- 1 3⁄4 cups water
- 1 1⁄8 cups sugar
- 1 1⁄2 tablespoons dry yeast
- 1⁄2 cup canola oil
- 1⁄2 tablespoon salt
Directions See How It's Made
- Put 3/4 cups of very warm water in a bowl. Add 1/8 cups of sugar and then the 1.5 T of dry yeast. Cover the bowl and set aside for 8-10 minutes to allow the yeast to proof.
- In an electric mixer (5-quart) mix the following ingredients: 1/2 cup of canola oil, 1 cup of sugar, 1 cup of warm water, 1/2 T of salt, and 4 cups of flour. Mix until a thin mixture forms.
- When the yeast mixture bubbles, add it to the other ingredients and mix. Then, begin to add the remaining 4 cups of flour in 1/2-1 cup increments. Add water in 1/4 cup intervals until the dough is smooth and only slightly sticky.
- Scrape the sides of the bowl with a greased spatula and make sure that all of the ingredients are mixed inches.
- Cover the bowl with a towel and allow the dough to rise for 10 minutes.
- If you are going to shape and bake your challahs immediately, cover loosely with plastic wrap and allow it to rise for 1 hour. If you are going to shape later (or the next day), place the dough into Zip-Loc bags lined with a little canola oil and refrigerate. (Remember that the dough will double in size, so leave enough room!) Remove the dough from the refrigerator 45 minutes prior to shaping.
- When you are ready to shape, grease your hands and the workspace with a little canola oil. Stack two baking trays on top of eachother and line the top with parchment paper (doubling up the baking trays prevents the bottom of the challahs from burning). Then, shape the challahs (be careful not to overwork the challah). If the dough is too sticky, use oil (don't use flour). Place the finished challahs on the baking sheet.
- Cover the challahs loosely with plastic wrap and allow to rest. Mix an egg glaze (mix 1 egg and some canola oil together). Preheat the oven to 350. When the oven reaches the temperature, brush the challahs gently with the egg glaze as evenly as possible. Place the challahs in the oven to bake.
- After about 20 minutes, begin to check on the challahs. Take them out as soon as they are golden brown.
- Remove them from the oven and allow them to cool. When they are cool, pack them in plastic bags. You can also freeze them, by placing them in Zip-Loc bags.
- Enjoy your challahs and have a beautiful Shabbos!

subset: commoncrawl


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The Boston based record label Run For Cover Records have announced they will be releasing the debut EP from the Long Island indie rockers Coasta. The label plans to release the bands five song EP on vinyl later this summer.
Coasta is described by their new label as a band that "craft brooding, atmospheric pop-rock songs akin to Nada Surf", a comparison I'm sure the band does not mind. Take a listen to the bands track "Young Blood" past the jump and comment with your thoughts on the new signing. Be sure to keep an eye on this band, as they are sure to have a busy and exciting few months ahead of them.
Latest posts by Matthew Dondiego (see all)
- Music Video: Turnover – "Most Of The Time" - March 21, 2013
- Music Video: Daylight – "In On It" - March 21, 2013
- Johnny Craig Announces UK Tour, New Songs - February 6, 2013


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Each month, Rated People connects over 50,000 homeowners with quality tradesmen - simply enter your job details in the form above to get started.
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Frequently Asked
"I like to help others," L. Ron Hubbard once wrote, "and count it as my greatest pleasure in life to see a person free himself of the shadows which darken his days."
That purpose was the reason for more than half a century of research into methods to improve the human condition.
Most important to Mr. Hubbard throughout his research was to achieve a workable solution to the problems of ethics, always searching for a methodology that would produce consistent and uniform results.
From the start, Mr. Hubbard had seen the effects of criminal behavior from the top down and from the bottom up. After witnessing the execution of a prisoner, he realized that killing a man was not justice, but merely a type of revenge. It was not a solution. Nor did locking a person away for life solve the problem. In his own words, "All one learns in a cage is that he has indeed become an animal."
Continuing to search for the one common denominator that marked anyone's start of a career in crime, Mr. Hubbard found that the loss of self-respect is what brought about any life of lawlessness and criminality.
To remedy this, Mr. Hubbard developed the workable methodology which is available today in the Criminon program.
"I have gotten so much out of this course, I have better learned to communicate with my family and friends and have learned to defuse potentially hostile situations with both convicts and guards that I come into contact with every day...
"Thanks to Criminon's The Way to Happiness course I am well on my way to being able to be a productive part of society upon my release."
The Criminon Program Evaluation: Phase I — The Urban Institute
Utah Juvenile Court Case Study — FASE
Criminon is licensed by the Association for Better Living and Education International.


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Mid-cap stocks are often ignored by investors -- at their own detriment. Retirement investors should connect with mid-caps via one or more of these three holdings. More
Mid-cap Stocks
Mid-cap stocks are perhaps the most intriguing investments, as they offer the best of both worlds: the potential for growth of small-cap stocks and the stability of large-cap stocks. Technically speaking, mid-cap stocks are stock of any company whose market cap falls between $2 and $10 billion. Due to the stability of mid-cap stocks, the plays on the stocks are plentiful. Some of the best mid-cap stocks include Dick's Sporting Goods (NYSE:DKS) and Old Republic International (NYSE:ORI). A few of the best mid-cap funds are T. Rowe Price Mid-Cap Growth (MUTF:RPMGX) and Vanguard Mid-Cap ETF (NYSEARCA:VO).
Recent Articles
The One Best Mutual Fund to Hold Forever
If you had to pick just one mutual fund for the long term, which one would it be? Here's what we picked. More
3 Best Mid-Cap Growth Mutual Funds to Buy Now
Mid-cap growth stock funds may be the sweet spot of investment class that leads other fund types in 2015. These three funds are all seeing rapid growth. More
Stay Far Away From Small and Mid Caps
Sellers are overcoming almost every attempt at a rally. More
Why You Should Ignore Mutual Funds' Five-Year Returns Right Now
If you think analyzing five-year returns is a good way to find a fund right now, think again. These mutual funds show that certain time periods can be deceiving. More
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Investors in midcap energy stocks get the dual benefit of stability AND growth. Here are five of the best picks for midcap energy stocks. More
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Midcap stocks beat small caps and large caps over long periods, but get too little attention. Here are five stocks to buy to get in on the upside. More
5 Midcap Energy Stocks Powering Up for 2014
Midcap energy stocks are in the market's sweet spot, which could mean huge returns for investors in these five midcap stocks. More
3 Best Funds to Play Midcap Growth Stocks
Midcap growth stocks can reward investors in a big way, without the risks of small-cap stocks. Here are the best mutual funds and best ETFs in the space. More
Mosey Into Midcaps: ETF Alternatives for Hot Stock Picks
This week, we look at ways to bundle midcaps, doublers, energy stocks and other equities into diversified ETFs. More


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Washington Redskins CB DeAngelo Hall said Wednesday that he saw no evidence that teammate LaRon Landry spit on any Philadelphia Eagles players during Monday night's game.
Eagles C Mike McGlynn alleged that Landry spit on him during the team's 59-28 win at Washington. The NFL said Tuesday that it would look into the allegation.
Landry denied the allegation. And Hall added support to that defense.
"I never saw it, and I don't think nobody else saw it," Hall said, via the Washington Post.
"That's the crazy part. I'm asking cats out there, like, 'Did you see it?' They were like, 'No, but that's what they said.' But they didn't see it. Nobody saw it."
-- Sean Leahy
Nate Davis is a reporter, blogger and editor who's been at USA TODAY since 2000. He has covered the NFL since 2005. No, he did not play quarterback for Ball State. Davis' succession of our esteemed colleague Sean Leahy at The Huddle is considered a Brady-for-Bledsoe swap by most "insiders."More about Nate


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Home > Product Categories > Pro-Audio > Studio Tools & Problem Solvers > Audio Hum & Noise Eliminators > IL-19-6RM
Item #: IL-19-6RM MFG #: IL-19-6RM
List Price:$299.95Our Price:$269.95Quantity Pricing
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The Only Product that Removes All Types of Hum in Live Sound & Pro-Audio Gear!
Designed as 3 products in-one, the Sescom® IL-19® is the industry standard for instantly reducing audio hum problems in live sound & broadcast applications providing quick fix line isolation to stop noise at the source. This 6 channel version features 1/4" or XLR combination balanced inputs and male XLR outputs. Removes ground loop hum, mode noise & differentially induced hum without the need for multiple transformers, ground lifters or phase inverters. Other in-line problem solvers solve only one problem at a time.
Sescom transformers are specifically engineered for flatter and broader frequency response allowing a hotter signal throughput without saturation. Sescom transformers also provide superior protection against radiated noise thus reducing pickup of hum and interference from outside sources such as power supplies. The IL-19-6RM keeps unwanted signals out of the circuit, but also reduces induced noise providing high-quality line level isolation to eliminate hum and buzz from interacting gear.
Provides Instant Relief For:- Has Combination Inputs Jacks which accept Both 1/4" TRS plugs -OR- XLR connectors!- Live Sound Equipment- Radio & Broadcast Audio- Line Level Equipment Interface- Decoupling Lines to Reduce Hum- Isolating Drive Lines to On-Stage Power Amps- Long Line Cable Runs
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Connie Scott
Sandy (Luke Halpin), the son of a Florida fisherman (Chuck Connors, of TV's "Rifleman" fame), rescues and nurses an injured dolphin, whom he calls Flipper, and in due course, forges a deep bond with the friendly animal. But the boy is crestfallen when, after Flipper regains his health, he must return the dolphin to the ocean. This charming family film is the basis for the hit television show of the early 1960's.


text:
MINA NIGHT 5 - 9 pm Sat 19th March 2016
Posted by CIBI CIBI on
MINA NIGHT "Minanoie Boutique Saturday Night Market"
Mina Saturday night market was started in 2013 as an experimental Retail and Food night on a Saturday evening. Our simple idea was "let's open up our Mina space and share it with the public on an evening occasion".
Do we call it a market, or do we call it something else? It's a kind of a market but perhaps it's just an evening where everyone can call it "home". Instead of just going out to a restaurant or bar, why not stop in at Mina night on a Saturday evening and enjoy the moment with beautiful products and special Mina food. Sharing our space will be various products from other brands and makers in Melbourne who have a similar vision to us, and are absolutely passionate about what they do!
Mina Night! at Minanoie (everyone's home) - we look forward to having you all over at our place to enjoy the evening, a place to be inspired and re-energise with all the goodies that are available.
This time at Mina Night, featured friends include Kloke, Tokyobike, Spacecraft, Tarlo & Graham, Honey Fingers, and Mac Forbes Wines – all amazing people we are very excited to see and spend an evening with.
MINA NIGHT "Minanoie Boutique Saturday Night Market"
5-9pm, Saturday 19th March 2016 @ Minanoie (33 Peel St Collingwood)


text:
|Publication number
|Publication type
|Application number
|Publication date
|Aug 19, 1980
|Filing date
|Jun 30, 1978
|Priority date
|Jun 30, 1978
|Also published as
|Publication number
|James E. Carlton, Werner J. Schaeuble
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Referenced by (5), Classifications (10)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Technical Field
This invention relates in general to systems for controlling the transfer of data between two units of a data processing system which are interconnected by cables whose length may vary in different installations and wherein the difference in signal propagation time between pairs of units interconnected with different cable lengths becomes significant in controlling the transfer of data. The invention relates more specifically to the control of the transfer of data to a disk file so as to provide a minimum of data buffering hardware at the disk file and permit accurate checking of the data transfer hardware.
2. Background Art
Various arrangements have been disclosed in the prior art to control the transfer of information between units of the data processing system. Since data is generally transferred between these units on a serial by byte basis, the interface cabling generally includes either one bidirectional data bus or two unidirectional data buses where information is to be transferred in both directions between the units. These buses generally extend between the output of a register in one unit and the input of a register in the other unit. The output of the sending register is usually gated in response to a suitable control signal which forms one of the interface lines from the receiving unit to the sending unit. The function of this control signal can be characterized as notifying the sending unit that the receiving unit is in a position to accept another character of data. A similar control line extends from the sending unit to the receiving unit to indicate to the receiving unit that a character has been sent.
Where the receiving unit is a magnetic storage device such as a disk file, the problem of initiating the transfer of data from the sending unit involves timing considerations which can be affected by the propagation delays caused by interface cables of different lengths. When data is transferred to a disk file it must be stored at some predetermined address. This address is usually specified at the track level and a location along the track relation to some predetermined reference point generally referred to as index. The data to be recorded must be supplied to the magnetic transducer at a time when the addressed portion of the record appears under the magnetic transducer. In order to insure that the first character of the data to be recorded is sent to the file in time for it to be serialized, encoded and supplied to the write drivers of the magnetic transducer, the data must be requested a predetermined amount of time before it is actually recorded. Since this time period involves the propagation time of the control signal requesting the data and the propagation time of the data itself, plus the delays in the sending unit, a variation in anyone of these factors could result in an erroneous data transfer operation. As the time required for the disk file to serialize the character from the sending unit, encode the serial data stream and supply it to the magnetic transducer decreases as a result of improvements in high speed circuit technology, the propagation time becomes more significant and variations caused by different cable lengths become more critical to the design and installation of these units.
One solution to the problem caused by different cable lengths is to provide a suitable size buffer in the disk file so that characters can be transferred early enough to be stored in the buffer until needed. Another solution is to avoid the problem by not permitting units to be interconnected by cables whose lengths vary significantly. The present invention overcomes the above noted problems.
FIG. 1 is a block diagram illustrating a simple data processing system wherein the control unit-controller interface involves a variable length cable.
FIG. 1A illustrates in detail the control unit-controller interface shown in FIG. 1.
FIG. 2 is a diagram of the circuits (shown in block form) for generating the "Sync In" pulse applied to the "Sync In" interface line shown in FIG. 1A.
FIG. 3 is a diagram of circuits (shown in block form) for receiving the "Sync Out" pulse applied to the "Sync Out" line shown in FIG. 1A.
FIG. 4 is a timing diagram for the circuits shown in FIGS. 3 and 4 for three different cable lengths or propagation times.
FIGS. 5A-5E illustrate a block diagram of the circuits for detecting a "Sync Out" timing error.
FIG. 6 shows another embodiment of the invention shown in FIGS. 2 and 3 in which prewired hardware circuits are employed in place of the microprocessor.
The present invention overcomes the problems discussed above by calculating the propagation time for the control signal in the particular installation on a regularly scheduled basis. The control signal to the sending unit is then issued at a time which reflects this calculation to insure that the first byte of data to be recorded is received at the file when it is needed regardless of the propagation time of the interface cables. The calculation is achieved in the preferred embodiment by measuring the number of bit and byte times that occur between the time the control pulse is sent to the sending unit and when the control pulse is received at the receiving unit. The control pulse, requesting the first byte of data to be recorded from the external device, is then issued the appropriate number of byte and bit times prior to when the first byte is to be recorded.
An added feature of the invention is the provision of a series of circuits that can be used to distinguish between the correct return pulse and a spurious noise pulse since the exact bit time for the return pulse to arrive is known.
FIG. 1 shows a simple data processing system comprising a central processing unit 10, a control unit 11, a disk file controller 13 and a string of disk drives 14. As shown, the interface cable 16 interconnecting the control unit 11 and the controller 13 may vary in length in different installations. In the system shown in FIG. 1, data is stored on disk drives 14 in the form of predefined records, each of which is assigned a unique address. The address generally comprises a designation of a disk, a track on the disk, and a location on the track which may be referenced to some arbitrary starting point referred to as index.
Information is transferred between the disk file and the CPU under the control of the CPU program. The function of the control unit is to interpret commands issued by the CPU (or channel). These commands, referred to as channel command works (CCWs) in one well-known system, are interpreted by the control unit which, in turn, issues its own series of orders to the controller. The commands can generally be divided into two groups: those that involve an actual reading or writing operation by the disk files, and those that involve other control operations such as selecting the appropriate controller and disk drive, positioning the head to the correct track, and obtaining status information about a particular drive or controller.
The transfer of this invention between the control unit and the controller occurs via the interface shown in FIG. 1A which comprises a number of different buses and lines for data and control signals.
As shown in FIG. 1A, the interface comprises the following lines from the control unit to the controller:
CTL Bus Out--The CTL bus out consists of 9 lines for one byte of data and parity. Bus out transmits command information and tag modifiers when Tag Gate is present and information to be recorded on a disk drive when "Sync Out" is present.
CTL Tag Bus--The CTL Tag Bus consists of 6 lines for five bits and a parity bit of control information.
CTL Select Hold--CTL Select Hold is a single line which is made active and remains active when a drive selected. It remains active until an End Signal is received from a drive after the last operation on the drive is performed and the End Signal is acknowledged.
"Sync Out"--"Sync Out" is a single line which validates and gates data on Bus Out during a data transfer operation.
End Response--End Response is a single line used by the Control Unit to acknowledge to the controller the receipt of a Normal End or Check End signal from the controller.
The signal lines from the controller 13 to the storage control unit 11 are as follows:
CTL Bus In--The CTL Bus In consists of 9 lines for one byte of data and parity. Bus In transmits data from a disk to the Storage Control Unit during read operations with the use of "Sync In" for gating. Bus In is also used to transfer information to the Storage Control Unit when Normal End, Check In, or Tag Valid are active.
CTL "Sync In"--"Sync In" is a single line which is used during transfer of data to the Control Unit to validate and gate Bus In. "Sync In" is used to request a byte of data from the Control Unit.
Select Active--Select Active is a single line which becomes active after a successful selection sequence and remains active to indicate proper selection as long as Select Hold is active.
CTL Tag Valid--CTL Tag Valid is a single line which rises in response to Tag Gate from the Control Unit to indicate reception of the Tag Decode by the Controller.
Normal End--Normal End is a single line used to indicate to the Control Unit that the normal ending point of an operation has been reached.
Check End--Check End is a single line used to indicate that an abnormal ending condition exists. The abnormal condition is defined by the byte of data that exists on Bus In.
Alert Lines--Alert Lines is a series of three lines, two selected and one unselected. Select Alert 1 is used to indicate an error condition in the selected controller or drive. Select Alert 2 is used to indicate a busy condition. Unselected Alert 1 is used to indicate to the Control Unit that a polling sequence is required by the Control Unit.
Transfer of a byte of data between the Control Unit and the Controller is synchronized by the action of the "Sync In" and "Sync Out" lines. Assuming that a given drive has been selected, the actual transfer of data from the Control Unit, where the data is buffered, is initiated by the Controller issuing a "Sync In" signal to the Control Unit. On receiving the "Sync In" signal, the Control Unit placed a byte of data on the Data Out bus and simultaneously issues a "Sync Out" signal. The "Sync Out" signal is used by the Controller to gate the data on Bus Out into a register at the Controller. The "Sync In" pulse sent to the Control Unit is repeated until the last byte of data is transferred. Meanwhile, the first byte of data is transferred to the serializer unit where it is serialized and encoded and supplied to the write drivers of the magnetic transducers. Since the Controller is synchronized to the disk drive, the first byte of serialized data will be stored beginning at the location along the track which is under the magnetic transducer. If the length of cable 16 is allowed to vary between installations, the total time between the issuance of a "Sync In" signal and the return of a "Sync Out" signal, referred to as propagation time, will vary accordingly. In the system shown in FIG. 1, the length of the cable measured in terms of byte times, is allowed to vary between one-half byte time and three byte times. This is approximately from 5 meters to 136 meters, assuming a data transfer rate of 1.9 bytes per second. The variation in length may be greater and, in practice, is limited only by the line driver and not the control system.
In the embodiment of the invention shown in FIGS. 2 and 3, this difference is accommodated for by first calculating the propagation delay in two steps and then issuing the "Sync In" pulse at a predetermined time selected in accordance with the results of the calculation so that the first byte of data to be recorded on the selected disk drive arrives at the Controller at the appropriate time.
FIG. 2 shows an arrangement for issuing a "Sync In" pulse selectively during any one of eight bit times, 0-7, which correspond to the bit times of the serial data being transferred to the file. The arrangement shown in FIG. 2 comprises a control register 21, a second control register 22, selection decode logic 23, selector 24, AND/OR logic unit 25, and AND GATE 26.
As shown in FIG. 2, control register 21 has its input connected to a data bus 28 which is adapted to be supplied with an 8 bit control byte from the microcontroller 29. The function of the microcontroller is to load control register 21 with an appropriate byte of control data at the correct time to generate the "Enable Sync In" signal for AND GATE 26 and the "read and write" op signals for AND/OR logic unit 25.
Control register 22 also has its input connected to bus 28 and receives an 8 bit byte of control data from the microcontroller 29. Three output lines designated 4, 2, 1 from control register 22 are connected to a decoder 23 whose function is to convert the input values of lines 4, 2 and 1 to one of eight output signals designated 0-7.
The eight line output of decoder 23 is supplied to selector 24 which is also supplied with bit ring signals 0-7 from a bit ring counter (not shown). The output of selector 24 is connected to one input of AND GATE 31. The other input to AND GATE 31 is from control register 21 and is designated "write op." The function of the control register 22, select decoder 23, selector 24 and AND GATE 31 is to provide a signal to AND GATE 26 during a write operation at any of the bit times 0-7 selected by the control register 22. The function of control register 21 is to provide an enable signal to AND GATE 26 which permits the "Sync In" signal to be issued at a predetermined bit time determined by control register 22.
While two separate control registers are shown in FIG. 2, it will be apparent to those skilled in the art that one control register could provide the desired control signals. Likewise, the input to the control register is shown as a microcontroller, but other devices known in the art for loading a control register with a predetermined byte of control information could be used.
FIG. 3 shows an arrangement for determining at what bit time the "Sync Out" pulse is received at the controller. As shown in FIG. 3, the arrangement comprises control register 36 and logic unit 32. The control register 36 is supplied with an output from logic unit 32 which comprises a series of AND GATES, each of which is supplied with the "Sync Out" signal and one of eight timing signals B0-B7. The output of control register 36 is connected to the microprocessor through bus 28. FIG. 3 also shows the data buffer 40 which is part of the controller 13 to which the bus out lines from the control unit are connected. As shown, the "Sync Out" pulse gates or clocks the data on bus out into the data buffer 40. During the next byte time, the byte of data in data buffer 40, if it is to be recorded on the disk drive, is transferred to the Serdes unit 50 through bus 28A where it is encoded and sent to the selected drive.
The operation of the arrangement shown in FIGS. 2 and 3 will now be described relative to the function of calculating the actual propagation delay of cable 16 for the particular installation. The first function to be performed is to issue a "Sync In" pulse at some preselected time. In this instance, the "Sync In" pulse is issued at T7 time by placing in control register 22 a signal pattern which causes the 4, 2 and 1 lines to be active. The select decoder converts the 4, 2, 1 signals to a select B7 signal supplied to selector 24. The output supplied to AND GATE 31, therefore, occurs at bit 7 time. The other input to the AND GATE 31 "write op" has previously been enabled by placing in control register 21 a signal pattern which makes "write op" and "Enable Sync In" active. As a result, the bit 7 signal is supplied to AND GATE 26 and the "Sync In" signal is issued at T7 time.
The arrangement of FIG. 3 first functions to determine the bit displacement relative to T7 independent of the byte displacement. The "Sync Out" pulse returned from the control unit is clocked into control register 36 by logic unit 32. The microprocessor examines the control register 36 during each subsequent byte time for a non-zero pattern until the "Sync Out" pulse is received. On detecting that the "Sync Out" signal has been received, the bit time displacement required to receive the "Sync Out" signal at T3 time is calculated by the microprocessor in accordance with Table 1 below.
Table 1______________________________________If Issued At T7 Displacement Is To Receive At T3and Received At Bytes Bits Issue At______________________________________T7 1-2 0 T3T0 1-2 1 T2T1 1-2 2 T1T2 1-2 3 T0T3 0-1-2 4 T7T4 0-1-2 5 T6T5 0-1-2 6 T5T6 0-1-2 7 T4______________________________________
Table 1 above relates the value clocked into the control register 36 representing the arrival time of the "Sync Out" pulse when the "Sync In" pulse is issued at T7. The table is constructed on the premise that the minimum cable length is sufficiently long so that the "Sync Out" pulse will not return within 4 bit times after the "Sync In" pulse is issued and the maximum cable length will insure a "Sync Out" pulse being returned within 3 complete byte times. The middle column shows the displacement in terms of possible byte times and actual bit times for each arrival time in column 1.
Since the first step in the process of determining actual propagation time is to determine the bit displacement, the actual number of bytes in the displacement is immaterial at this point. This bit displacement may be stored by the microprocessor for use after the next step.
The second step of the displacement measurement involves determining the number of byte times (independent of the number of bit times) consumed by the propagation delay. The microprocessor converts the arrival time of the "Sync Out" signal in column 1 to the bit time that a "Sync In" pulse should be issued to have an arrival time of T3. That information is then supplied to control register 22 so that the next "Sync In" pulse is issued at a time which should cause the "Sync Out" pulse to arrive at T3. During the propagation delay, the microprocessor will keep track of the number of byte times. The byte measurement and the bit measurement are then added together to determine the total propagation delay and can be used in subsequent operations.
With reference to FIG. 2, the second phase of the operation begins by loading control register 22 with a bit pattern to cause decoder 23 and selector 24 to provide a pulse to AND GATE 31 at the bit time which corresponds to the bit time in column 3 of Table 1 for the bit displacement determined during the first phase of the operation. Assuming, for example, that the "Sync Out" pulse was received at T4, the bit displacement from Table 1 is 5 bits and either 0, 1 or 2 bytes. The next "Sync In" pulse is issued at T6 time so that the "Sync Out" pulse should return at T3 time of one of the next three byte times.
Pattern 110 is therefore placed in control register 22. Control register 21 is supplied with a pattern which renders the "Enable Sync In" line to AND GATE 26 and the "write op" line to AND GATE 31 active.
A single "Sync In" signal is then sent at T6. The "Sync Out" pulse will be returned at T3 of the next byte time, the second byte time, or the third byte time so that the microprocessor examines the contents of control register 36 each of the next three succeeding byte times until a non-zero pattern is detected. If a non-zero pattern is detected at the first succeeding byte, the byte displacement under the previous assumption would be zero. If the non-zero pattern is detected during the second sequential byte time, the displacement is one byte and if the non-zero pattern is detected on the third successive byte time, the displacement is two bytes. The microprocessor now adds the byte displacement and bit displacement and stores this value for use in issuing the "Sync In" signal for the start of each subsequent write operation.
FIG. 4 is a timing diagram illustrating the time a "Sync In" signal will be issued for three different displacements of 0 bytes 4 bits, 1 byte 5 bits, and 2 bytes 6 bits. As shown in FIG. 4, one bit time, namely bit time 4, is reserved for changing the status of the control registers. Any action which would occur during bit time 4 may therefore be advanced or delayed one bit time.
FIGS. 5A through 5E illustrate the system for generating a "Sync Out" timing error. Since the exact bit time that the "Sync Out" pulse should be received is known, the system is designed to check five possible errors. These errors are as follows:
1. Two "Sync Out" pulses occurring in a single byte time period.
2. Two consecutive "Sync In" pulses occurring with no intervening "Sync Out" pulse.
3. A "Sync Out" pulse present when not expected.
4. A "Sync Out" pulse occurring at "Sync In" time.
5. A "Sync Out" pulse present before the first "Sync In" pulse is generated.
The manner in which the errors are detected will now be explained with reference to FIGS. 5A through 5E:
The circuit shown in FIG. 5A for detecting an error resulting from two "Sync Out" pulses in one byte time comprises SO1 Latch 50, SO2 Latch 51 and AND GATE 52 and the logic 53 for generating the "pseudo Sync In signal" and the "pseudo Sync In gated signal" applied to the reset terminal of Latch 50 and used in subsequent test circuits.
The output of SO1 Latch 50 is made active when it receives the first "Sync Out" pulse applied to the set terminal. Latch 51 is set by the leading edge of the "Sync Out" pulse provided the output of Latch 50 is active. Latch 50 is reset at bit 7 time during a write op and in the presence of an "Expect Sync Out" signal which generates a signal referred to as "pseudo Sync In gated" represented by PSIG in FIG. 5A. If a "Sync Out" pulse is active, goes inactive and returns to the active state again before T7 time, Latch 51 will be set and indicate an error condition referred to as Type Error 1 in FIG. 5A.
The circuit shown in FIG. 5B for detecting two consecutive "Sync In" pulses with no intervening "Sync Out" pulse comprises SI 1 Latch 60, SI 2 Latch 61, AND GATE 63, and the Invertor 64. The "pseudo Sync In" signal and the "pseudo Sync In gated" signal described in connection with FIG. 5A are employed as inputs to the Invertor 64 and the "Sync In" 1 Latch 60. The "Sync In" 1 Latch 60 is set by the "pseudo Sync In gated" signal at T7 time. The SI 2 Latch 61 is set by the leading edge of the "not pseudo Sync In" signal which is the output of the Invertor 64. No error condition is signalled since AND GATE 63 is not enabled by "Sync In" 2 Latch. However, if Latches 60 and 61 are not reset by the next bit 7 time, the "pseudo Sync In gated" signal supplied by the enable AND GATE 63 signifies an error condition.
The circuits for detecting the receipt of the "Sync Out" pulse at the wrong byte time are shown in FIG. 5C. The "Expect Sync Out" signal is the byte time signal which was calculated by the system shown in FIGS. 2 and 3. This signal is inverted and applied to AND GATE 70 which also receives a "Sync Out" signal. AND GATE 70 is disabled except for the byte time when the "Sync Out" signal is expected. As a result, should a "Sync Out" signal occur, an error condition is indicated by an active output of AND GATE 70.
The AND GATE shown in FIG. 5D checks against the "Sync Out" pulse and a "pseudo Sync In" pulse occurring at T7 time. Should this occur, an error condition is indicated at the output of AND GATE 75. This prevents the data buffer from receiving a byte of data from Bus Out at the time it is being put into Serdes.
The circuits for detecting a "Sync Out" pulse occurring before the first "Sync In" pulse are shown in FIG. 5E. The circuits comprise Latch 80 which is set by a "Sync Out" pulse occurring before the signal from the "Sync In" 1 Latch goes active. This signal is generated from the "Sync In" 1 Latch 60 of FIG. 5B. Once the "Sync In" 1 Latch 60 goes active, the "Sync Out" pulse is degated and the Latch 80 cannot be set, and hence, no error condition can be indicated. However, if the "Sync Out" pulse is received while the "Sync In" 1 Latch is inactive, an error condition is indicated since Latch 80 would be set.
FIG. 6 shows another embodiment of the invention shown in FIGS. 2 and 3 using prewired logical circuits for determining the displacement and/or propagation delay instead of using the microprocessor shown in FIGS. 2 and 3. The system shown in FIG. 6 comprises a bit counter 90, a byte counter 91, a counter control latch 92, and AND GATES 93 and 94 connected to the set and reset input, respectively. of latch 92. The system further includes a convertor 96 whose function is to convert the actual propagation delay measured in bit and byte times by the counters to a suitable control signal for register 22 shown in FIG. 3.
The system of FIG. 6 operates as follows. Counter control latch 92 is set by application of the "Sync In" signal and a calibrate signal to AND GATE 93. The calibrate signal may originate from control register 22 or any other suitable source. The output of latch 92, when set, opens the input to AND GATE 95 and allows the bit clock signal to advance the bit counter 90. Bit counter 90 provides one input signal to byte counter 91 for each cycle of eight bits. The AND GATE 95 is disabled to stop the counter from advancing when the counter control latch 92 is reset by the signal from AND GATE 94. This signal is, in effect, the "Sync Out" signal received from the control unit.
Counters 90 and 91, therefore, measure the actual propagation delay of the interface cable, since counter 90 is started when the "Sync In" signal is issued and stopped when the "Sync Out" signal is received. The convertor 96 supplied with the measured propagation delay from counters 90 and 91 converts the count figure to a control byte to be supplied to control register 22 so that the "Sync In" signal requesting the first byte of data to be recorded will be issued early enough to insure that the byte of data is returned at a predetermined time relative to when it is actually to be recorded.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in the form and details may be made therein without departing from the spirit and scope of the invention.
|Cited Patent
|Filing date
|Publication date
|Mar 26, 1970
|Feb 15, 1972
|Rca Corp
|Synchronization of serial memory
|Mar 8, 1971
|Apr 3, 1973
|Searle Medidata Inc
|Data communication system
|Nov 26, 1971
|Nov 20, 1973
|Method of and arrangement for the distribution of timing pulses in an electronic data processor
|Apr 4, 1973
|Aug 13, 1974
|Bell Telephone Labor Inc
|Readout circuitry for elastic data bit stores
|Dec 26, 1973
|Nov 11, 1975
|Asynchronous clocking apparatus
|May 19, 1976
|Jul 5, 1977
|Bell Telephone Laboratories, Incorporated
|Overlap PCM coder/decoder with reaction time compensation
|Jun 27, 1975
|Dec 13, 1977
|International Business Machines Corporation
|Automatic clock tuning and measuring system for LSI computers
|Citing Patent
|Filing date
|Publication date
|Jul 20, 1990
|Aug 25, 1992
|Canon Kabushiki Kaisha
|Image data communication control system
|Jun 21, 1994
|Oct 1, 1996
|Hitachi, Ltd.
|Storage system and method of remotely controlling the same
|Jun 26, 1995
|Mar 3, 1998
|Siemens Business Communication Systems, Inc.
|Automatic path delay compensation system
|Jun 21, 2000
|Dec 27, 2000
|Nec Corporation
|Circuit and method for reliably performing bus reset regardless of cable length
|Jun 21, 2000
|Apr 26, 2006
|Nec Corporation
|Circuit and method for reliably performing bus reset regardless of cable length
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification


text:
Project RISK is a Spokane Valley Fire Department initiative to reduce fire and medical emergencies in our community through proactive, targeted outreach and education. Project RISK focuses on:
We analyze of our fire and medical emergency call data to identify the most frequent causes of fire and Emergency Medical Service (EMS) calls. We then focus our educational efforts and resources to address these identified 'community risks'.
Project RISK is led by our Community Risk Reduction Specialist, Elysia Spencer.
Community Risk Reduction (CRR) is a term used by the National Fire Prevention Association (NFPA) and is defined as "programs, actions and services used by a community, which prevent or mitigate the loss of life, property and resources associated with life safety, fire and other disasters within a community."
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text:
Breaking News: COMEDY OF ERRORS & LOVE LABOUR'S LOST Set for SHAKESPEARE IN THE PARK 2013! Ferguson & Linklater to Star
The Public's 2013 free Shakespeare in the Park season will begin on Tuesday, May 28 with THE COMEDY OF ERRORS, featuring Shakespeare in the Park alumni Jesse Tyler Ferguson ("Modern Family") as Dromio and Hamish Linklater ("The New Adventures of Old Christine") as Antipholus. Ferguson and Linklater last performed together in The Winter's Tale and The Merchant of Venice in 2010 for The Public's Shakespeare in the Park. Directed by Daniel Sullivan, THE COMEDY OF ERRORS will run for five weeks through Sunday, June 30.
The second show of The Public's free Shakespeare in the Park season will be a new musical adaptation of Shakespeare's LOVE'S LABOUR'S LOST, directed by Alex Timbers with songs by Michael Friedman, and book adaptation by Alex Timbers. Timbers and Friedman last collaborated on the award-winning musical Bloody Bloody Andrew Jackson at The Public and Timbers will direct the new David Byrne musicalHere Lies Love this spring at The Public's downtown home at Astor Place. LOVE'S LABOUR'S LOST, A NEW MUSICAL will begin performances on Tuesday, July 23 and run through Sunday, August 18.
"This summer will be a joyous and light-hearted celebration of Shakespeare's comic side - from the wild slapstick of The Comedy of Errors to the hip beauty of Alex Timbers and Michael Friedman's musical adaptation of Love's Labour's Lost," said Artistic Director Oskar Eustis. "TheComedy of Errors will let our beloved Dan Sullivan explore his antic side, and Love's Labour's Lost will be the first original musical adaptation of Shakespeare's work at the Delacorte since the storied Two Gentlemen of Verona in 1971. The summer will be filled with universal laughter!"


text:
|Roslin Frey
General Information
|TV Show
|Game of Thrones
|Alexandra Dowling
Daughter of Walder Frey. She is wed to Edmure Tully.
Roslin Frey is one of the many daughters of Walder Frey. In season 2 of the series, Walder Frey had received word from Robb Stark that he would marry Roslin in exchange for the use of Walder Frey's bridge and his men to help win the Stark's war against the Lannisters. However, Robb had gone back on his word by marrying another woman named Talisa. Later, Robb would turn to Walder Frey after he is losing the war. After receiving assurances from Tywin Lannister, Walder Frey agrees to kill Robb and his mother. Walder Frey then falsely agrees to reform Robb's agreement with him if Roslin weds Edmure Tully.
Major Plots
Season 3
Roslin appears for the first time at her wedding. Before her marriage to Edmure, he was very nervous that he was going to marry an ugly bride. To his relief, Roslin was very beautiful and his fears subsided. He married her without a second thought. Then at the wedding reception, she and Edmure are carried off into another room for the bedding ceremony. While she is with Edmure, Walder Frey has his men kill Robb, his mother and the Stark bannermen.
Personality and Traits
Unlike many of her siblings, Roslin is considered very beautiful and many who saw her were surprised at how beautiful she was compared to Walder Frey's other children. Not much is known about Roslin Frey's personality since she does not speak much in the series. However, it can be said that she is an obedient daughter since she agreed to be married to Edmure for her father.


text:
How do you search messages in your inbox on facebook?
open your messages page, and there is a search box at the top of the left column
Using my iPad how do I delete my inbox messages on facebook?
Hold your finger down on the message (When its in your inbox) it should come up with Archive or something.
Facebook inbox won't load + can't send messages?
You know, I have same problems since today morning, so I suppose their server is down at the moment. All we can do now is waiting (I've reported btw).I'll add an "edit" here if mine's working again...
Read More »
Is there a limit to the number of messages your tumblr inbox can hold?
How to Hide Messages on Your Facebook Profile?
When you hire the services of a personal trainer, you expect that he or she will provide you with a high value for your hard earned money. You expect instruction on how to safely and effectively us...
Read More »


text:
William Henry Morgan & Harriet May Chalmers
(Click on image to enlarge)
Morgan, William Henry (Rev.)
Birth: 18 JAN 1861, Wilton Park, Durham, England
Gender: Male
Parents:Father: Morgan, John, Jr. (Rev.)
Birth: AUG 1839, Fredthvin, Monmouthshire, Wales
Death: 21 NOV 1901, Newark, Essex County, New Jersey, United States
Mother: Williams, Mary
Birth: MAY 1841, Blana, Monmouthshire, Wales
Marriage: February 25, 1860, Witton le Wear, Durham, England
Spouse:Chalmers, Harriet MayMarriage: ABT 1904
Birth: 01 FEB 1868, Galway, Saratoga County, New YorkGalway, Saratoga County, New York
Death: 03 JAN 1941
Gender: Female
Parents:Father: Chalmers, William Kerr
Birth: 08 JUL 1828, New York, United States
Death: 16 DEC 1910
Gender: Male
Mother: Elizabeth
Birth: ABT 1836, Galway, Saratoga County, New York, United States
Death: 1924
Gender: Female
Spouse:Minnie B.
Birth: ABT 1869, Pennsylvania, United States
Marriage: ABT 1889
Spouse:White, Carrie LunettaChildren:
Birth: JUN 1841, Columbiana, Mahoning County, Ohio, United States
Death: ABT 1910, Ohio, United States
Parents:Father: White, Charles Lewis
Birth: 29 OCT 1840, Barboursville, Cabell County, West Virginia, United States
Death: 27 JUN 1920, McArthur, Vinton County, Ohio, United States
Mother: Bussard, Eliza Newell
Birth: 29 OCT 1840, Barboursville, Cabell County, West Virginia, United States
Death: 27 JUN 1902, McCarthur, Vinton County, Ohio, United States
Morgan, William Edgar
Birth: 07 AUG 1890, Bayfield, Bayfield County, Wisconsin, United States
Death: ABT 1950, Texas, United States
Gender: Male
Morgan, John Lewis
Birth: 19 DEC 1891, Port Morris, Roxbury Township, Morris County, New Jersey, United States
Gender: Male
Morgan, Carrie L.
Birth: 19 OCT 1893, Mend, Morris County, New Jersey, United States
Gender: Female
This page was produced by GED2WWW version 0.31 compiled on Sep 27 1999 at 13:23:34. GED2WWW © 1996-1999 Leslie Howard. GED2WWW is free software, distributed under the terms of the GNU General Public License. For more information about GED2WWW or the GNU General Public License visit the GED2WWW webpage at http://www.lesandchris.com/ged2www .
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text:
Each month, Rated People connects over 50,000 homeowners with quality tradesmen - simply enter your job details in the form above to get started.
We'll match your job to the relevant tradesmen in your area - those interested will pay to see your contact details and call you to quote.
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Moving to house and no patio keys Need new lock
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text:
That is a lie. They want affirmation and acceptance for their nihilistic, destructive behavior. They want to promote it as good (as they do in all media where they hide all negative references like the Duke homosexual who married in Mass and adopted a black baby and molested him and pimped him to other homosexuals.) It is a sexual identity disorder and never natural. It was a crime to take it off the APA list of disorders and was forced off--not by scientific research--but by the gay movement so they could proceed to normalize it through brainwashing.
There is no homosexual gene. It has been conclusively proven in several scientific reports. They try to compare a behavior to skin color....it is why they lie about the genetic angle--to gain sympathy for a lifestyle.
If there is a sexual orientation gene, then there has to be a baby raping gene or a bestiality gene. It is utterly stupid to pursue the "gene" theory.
Sexual decadence is learned--you find lots of it where it is not condemned....Gramsci and Marcuse understood the need to corrupt societies by using sexual perversion and Freudian Marxism is behind the homosexual movement.
Research the intent of this movement....it is to destroy Western Civilization.....not change it....to destroy it. Get educated before you make such ignorant posts!
False Compassion is what you have for homosexuality. Yes, Christians need to be compassionate to all sinners, because we all are....but you do not affirm the sins and advocate the continual sinning PLUS tell your kids (cognitive dissonance) that homosexual behavior is good. That is like telling them doing crack is good too. Both behaviors are nihilistic and are demeaning to a culture of life. Healthy societies can not promote destructive lifestyles to their children. It is suicidal for a culture to do that....but with the Cultural Marxists in control of media, schools and government, we are destroying ourselves....We need to CHANGE NOW!
My friend you're beyond salvage on this issue.
People are born with a myriad of gene deficiencies every day. Never said anything about a homosexual gene. Please cite the so-called scientific evidence proving that homosexuality is a chosen lifestyle?
As to your example of bad homosexual behavior: You seem to be saying that because some homesexuals do bad things all homosexuals do bad things. Your logic is specious and juvenile. Because, if your logic is logical, then the same can be said for heterosexuals. In other words, because some heteros do bad things all heteros do bad things.


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Torra Brilliant in 6-2 Aces Win
August 6, 2010 9:40 PM ET
Reno has now won three-straight games, with a series sweep on the line Saturday night.
The Aces took an early 6-0 lead through three innings, and Torra (8-6) took care of the rest. The right-hander took a shutout into the ninth and finished with eight hits and two runs-one earned-scattered over 8.1 frames. Torra walked one and punched out two in a 106-pitch effort. Jose Marte came on with one out in the ninth and recorded the final two outs of the ballgame.
At the dish for Reno, Ryan Roberts led the way with three hits, a run and an RBI. Tony Abreu singled and doubled, while driving in three runs. Brandon Allen and Cole Gillespie added two hits apiece, while Jeff Bailey drew a walk to extend his home on-base streak to a franchise-high 34-straight games.
Sounds starter Marty McLeary (5-7) took the loss Friday, surrendering six runs-five earned-on 10 hits over five innings of work.
Defensively, the Aces flipped four double plays on the night.
The Aces look for the series sweep over Nashville on Saturday night at Aces Ballpark. LHP Zach Kroenke (3-3, 4.15 ERA) gets the nod for Reno, while LHP Sam Narron (7-4, 3.50 ERA) counters for the Sounds. First pitch is set for 7:05 p.m. PT
Tickets for all Aces games start at just $7, and are available by calling the Reno Aces box office at (775) 334-7000 or by visiting RenoAces.com. The brand-new Freight House District, located just outside Aces Ballpark, is open seven days a week, on both game days and non-game days.
This story was not subject to the approval of the National Association of Professional Baseball Leagues or its clubs.View More


text:
Toy Care & Cleaning Guide
Paddle Care Beautiful wood requires this easy care and storage.
Cane Care Some easy tips for keeping your canes healthy!
Silicone Care What to use and what not to use.
Rubber Care Easy to clean and care for...find out how.
Leather Care Find tips on keeping your leather goods in tip top shape!
Metal Care Learn how to best care for your solid metal toys, including cleaning, storage and sterilization tips.
Tail Care Learn how to best care for your real fur, faux or pony tail butt plugs including cleaning and storage tips.
Electronic Devices It may seem obvious, but see our tips for care and storage.
And remember, if you've broken or damaged your toy, We Do Repairs!
Check out our return and warranty information for additional help.


text:
Audi Introduces R18 e-tron Quattro in Video
If there's an age old adage in motorsports, then it has got to be "racing improves the breed." This idea is particularly close to Audi's heart, as the German automaker has participated in decades of racing and development for its Quattro all-wheel-drive technology.
This year, Audi will field a pair of R18 e-tron Quattro cars which will compete in a series of endurance races including the iconic 24 Hours of Le Mans. The added e-tron designation on the new R18 refers to an all-new hybrid system for Audi's LMP1 racer. Featuring a V6 TDI diesel powerplant sending 510-hp to the rear wheels and an additional pair of electric motors to motivate the front, the R18 e-tron Quattro is, without a doubt, one of the most technologically advanced racing cars in the world.
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Assassins and Victims(1969)
A novel by Campbell Black
In the darkness outside a seedy English boardinghouse, a dog whines and barks, night after night, and the lives of three people begin to crack. Writing with diabolical skill and a fiendish eye for detail, Campbell Black has created around the gothic trio a memorable comedy of grotesque.
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Used availability for Campbell Black's Assassins and Victims
See all available used copies of this book at Abebooks UK or Abebooks US
Hardback Editions
1969 : UK Hardback
|Title: Assassins and victims
Author(s): Campbell Black
ISBN: 0-333-10102-2 / 978-0-333-10102-5 (UK edition)
Publisher: Macmillan
Availability: Amazon UK Amazon CA
Paperback Editions
June 1972 : UK Paperback
|Title: Assassins and Victims
Author(s): Campbell Black
ISBN: 0-586-03573-7 / 978-0-586-03573-3 (UK edition)
Publisher: HarperCollins Distribution Services
Availability: Amazon Amazon UK Amazon CA
Kindle Editions
April 2015 : USA, Canada, UK Kindle edition
|Title: Assassins and Victims
Author(s): Campbell Armstrong
Publisher: Open Road Media Mystery & Thriller
Availability: Amazon Amazon UK Amazon CA
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