text:
|Publication number
|Publication type
|Application number
|Publication date
|Dec 7, 2004
|Filing date
|Apr 26, 2001
|Priority date
|Apr 26, 2001
|Fee status
|Also published as
|Publication number
|Toshiaki Kirihata, Sang Hoo Dhong, Hwa-Joon Oh, Matthew Wordeman
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (18), Non-Patent Citations (3), Referenced by (18), Classifications (18), Legal Events (8)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates generally to integrated circuit memory devices and, more particularly, to improving access cycle time for Dynamic Random Access Memories (DRAMs).
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the application thereof. Accordingly, there is an increasing demand for larger Dynamic Random Access Memories (DRAMs) with higher density and performance.
DRAM architectures have evolved over the years, being driven by system requirements that necessitate larger memory capacity. However, the speed of a DRAM, characterized by its random access time (tRAC) and its random access cycle time (tRC), has not improved in a similar fashion. As a result, there is a widening speed gap between the DRAMs and the CPU, since the clock speed of the CPU steadily improves over time.
The random access cycle time (tRC) of a DRAM array is generally determined by the array time constant, which represents the amount of time to complete all of the random access operations. Such operations include: wordline activation, signal development on the bitlines, bitline sensing, signal write back, wordline deactivation and bitline precharging. Because these operations are performed sequentially in a conventional DRAM architecture, increasing the transfer speed, or bandwidth, of the DRAM becomes problematic.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
In a preferred embodiment, enabling a destructive read mode includes developing a differential signal on a pair of precharged complementary bit lines, one of the bit lines being coupled to the addressed DRAM memory cell. The differential signal is then transferred the pair of bit lines to a pair of sense lines, with the sense lines being isolated from the bit lines immediately thereafter. Then, the pair of bit lines is precharged.
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
FIG. 1 is a schematic and associated timing diagram of an existing single DRAM structure, illustrating the sequential processing steps associated therewith;
FIG. 2 is a schematic and associated timing diagram of an exemplary DRAM structure having a destructive read/delayed write feature, in accordance with an embodiment of the invention;
FIG. 3 is block diagram of a DRAM control architecture using a destructive read/delayed write feature, in accordance with an embodiment of the invention;
FIG. 4 is a data flow diagram illustrating an example of one embodiment a method for controlling the operation of the DRAM system in FIG. 3;
FIG. 5 is a flowchart illustrating an alternative embodiment of the method illustrated in FIG. 4;
FIGS. 6A-6C are command pipeline diagrams for the embodiment of FIG. 5;
FIG. 7 is a timing diagram comparing internal and external operations for the method in FIG. 5; and
FIG. 8 is a schematic of a exemplary DRAM cell structure embodying the method illustrated in FIGS. 5-7.
Referring initially to FIG. 1, a conventional DRAM array architecture is shown employing a CMOS cross-coupled sense amplifier (SA). The DRAM array 100 includes a plurality of DRAM cells 102 arranged in a matrix pattern. Each DRAM cell 102 comprises one field effect transistor (FET) 104 and one capacitor 106, functioning as a data bit storage element. The operation of the conventional array 100 is best understood with an explanation of the following sequential signal processing steps:
(A) signal development on the bitlines (BL and BL bar);
(B) bitline (BL) sensing;
(C) signal write back; and
(D) a bitline (BL) precharging operation.
(A) signal development on the bitlines (BL and BL bar): The gate of the FET 104 is coupled to a wordline (WL). As long as WL is low, the capacitor 106 holds a data bit as a charge. The capacitor 106 holds 0 volts for a "data 0" bit, and a predetermined voltage (VDD) for a "data 1" bit, respectively. The bitline pairs (BL and BL bar) are already precharged at a � VDD level by bitline equalizing devices 120 (when ΦEQ=high). The precharging operation is described in step (D). When WL goes high, the capacitor 106 is coupled to the corresponding bitline (BL) through FET 104. However, prior to the wordline (WL) activation, the bitline (BL) equalizing devices 120 are turned off (when ΦEQ=low). Thus, it is possible to change the bitline voltage by transferring whatever charge is stored in capacitor 106.
(B) bitline (BL) sensing: The CMOS cross-coupled sense amplifier (SA) 130 amplifies the differential voltage between BL and BL bar by driving clock signals ΦN and ΦP low and high, respectively. The operation of the CMOS cross-coupled sense amplifier is well known in the art, and is not discussed further detail hereinafter.
(C) signal write back: After the BL signal is sufficiently amplified, a column select line (CSL) activates column switch devices 140. This couples the BL pair to the VDD precharged data line pair (DL and DL bar). During a data read mode, a differential voltage is therefore generated on the DL pair, which differential voltage is then sensed by a second sense amplifier (not shown). During a write mode operation, the BL pair may be "flipped", depending upon the data pattern driven from the DL pair. It should be pointed out that a write mode should not be enabled prior to the BL sensing operation, since the BL swing in a write mode (WRITE) causes a coupling noise on an adjacent BL (READ) during signal development, thereby destroying the sensing signal. The bitline voltages are then stored on capacitor 106 through FET 104.
(D) a bitline (BL) precharging operation: Finally, the wordline (WL) is deactivated, thereby isolating the data cell 102 from the bitline pair. The data bit is therefore maintained in the capacitor 106. The CMOS cross-coupled SA 130 is thereafter deactivated, and equalizer devices 120 equalize the BLs so that they are once again precharged at the � VDD level.
The timing diagram in FIG. 1 illustrates an example of a conventional "1" bit read and then a "0" bit write operation. During the signal development step (A), the voltage on WL goes from low to high. Initially, bitline pairs BL and BL bar are both at 1.5 volts from a previous precharging (for illustrative purposes, it will be assumed that VDD=3 volts). Once WL goes high, the gate of FET 104 is turned on, thereby coupling capacitor 106 (with its stored 3 volt/"1" bit charge) to BL. The voltage on BL begins to increase from 1.5 volts while the voltage on BL bar remains at 1.5 volts. When the sense amplifier SA 130 connected to BL and BL bar is enabled during step (B), a differential voltage across BL and BL bar is sensed and thereafter amplified. Thus, BL is driven up to 3 volts, while BL bar is driven down to 0 volts. This then enables a writeback of data to cell 102. Without SA 130, the data in cell 102 would be lost upon coupling capacitor 106 to BL.
Because a "0" bit write is called for in this example, the values of BL and BL bar are "flipped" during step (C) such that BL is driven to 0 volts and BL bar is driven to 3 volts by driving DL to a low level while keeping DL bar high. Thus, the capacitor 106 will then be pulled to 0 volts, still being coupled to BL as WL is still high. Finally, in step (D), WL is deactivated, a "0" bit is written to cell 102, and BL and BL bar are once again precharged to 1.5 volts.
The existing architecture 100, thus configured, makes it difficult to improve the overall random access cycle time (tRC) due to the sequential execution of all the operations (A), (B), (C), and (D) discussed above. Therefore, in accordance with one embodiment of the present invention, there is shown in FIG. 2 a DRAM array 200, and an associated timing diagram illustrating the operation thereof, featuring a "destructive read" architecture. For purposes of illustration only, similar or like components described hereinafter have the same reference numeral designations as previously described components.
In addition to the previously described elements, array 200 further includes switching devices 150 connected between bitlines (BL) and sense lines (SL). Again, when the WL goes high, the capacitor 106 is coupled to the corresponding bitline (BL) through FET 104. Prior to the WL activation, the BL equalizing devices 120 are turned off (ΦEQ=low), and making it possible to change the BL voltage by transferring the charge from the storage capacitor 106. Switching devices 150 are then temporarily turned on to transfer the signal developed on the BL pair over to the SL pair. The switching devices 150 are then turned off and SLs are decoupled from the BLs before the precharge operation is executed thereon. This allows the WL, the BL and BL bar to be precharged immediately and simultaneously after a sensing signal has been developed on the BLs and SLs.
Accordingly, the sense amplifier SA 130 amplifies the differential voltage between SL and SL bar in a "pipeline" manner. Unlike the conventional architecture shown in FIG. 1, the SA 130 is used only for transferring a data bit to the data line (DL). Due to the isolation of the BLs from the DLs, the signal on the capacitor 106 of cell 102 is destroyed after the signal has been read (thus, comprising a destructive read architecture). The data bit transferred to the DLs is then copied to a static random access memory (SRAM). During a write mode, the data bits are directly written to the corresponding DRAM cell as a "write though". Alternatively, the written bit may be read and stored in the SRAM for a future delayed write back, similar to the read mode. Some of the read bits may be overwritten with the input data bits and stored in the SRAM for future delayed write back. Such an option would allow a chip to support a bit or byte mask mode.
Regardless of the write-through and delayed write options implemented, all of the data bits accessed by a wordline (WL) are simultaneously written back to the corresponding DRAM cells. The write mode may commence prior to signal development, thereby avoiding the tRC penalty normally incurred during a write mode. A destructive read architecture, therefore, eliminates the time components of the overall tRC represented by the operational steps of (B) bitline sensing and (C) signal write back, regardless of whether the system is in a read or write mode. As a result, the overall speed improvement of the random access cycle time (tRC), using the architecture shown in FIG. 2, is as much twice that of the conventional DRAM architecture.
The timing diagram in FIG. 2 further illustrates the elimination of steps (B) and (C). Once WL is enabled and a bitline signal differential is developed, the bitlines are immediately precharged and returned to 1.5 volts. The amplification used to rewrite or flip the data bit occurs on the isolated SL and SL bar lines, which bit is then stored in SRAM for future use. Thus, the cycle is completed after steps (A) and (D), since the data read (and destroyed from the cell) is temporarily saved into SRAM and rewritten back into the cell at a later time if need be.
Referring now to FIG. 3, an architecture 300, in accordance with an embodiment of the invention, is shown. Architecture 300 includes a plurality of DRAM arrays 302 (individually designated by Array <0> through Array <255>), and at least one SRAM 304 array within a given chip. While the size of each DRAM array 302 may be different, the total number of data bits for the SRAM array 304 should be larger than the largest individual DRAM array size. Optionally, a plurality of DRAM arrays 302 may be grouped as a bank. In this case, the density of the SRAM array should be equal to or larger than the DRAM bank size containing a plurality of DRAM arrays. For purposes of illustration only, the following description assumes a total of 256 DRAM arrays, each consisting of 32K cells. The 32K cells are each accessed by 256 wordlines (WLs) and 128 bitline (BL) pairs. The SRAM array 304 is organized similar to each DRAM array 302 (having 32 K cells accessed by 256 WLs and 128 BL pairs).
As discussed previously, a DRAM read command reads out all data bits (128 b) sensed in a 32K DRAM array 302 to the SRAM array 304. A scheduler 306 controls and keeps track of the DRAM arrays 302 and the SRAM array 304 so that the data bits stored in the SRAM array 304 will be correctly written back to the corresponding DRAM array 302 as a delayed write back. Scheduler 306 receives a command signal (CMD) along with a 16-bit address vector (designated by ADD <0:15>) from a controlling entity such as a CPU (not shown). Bits 8 through 15 of the address vector (ADD <8:15>) are used for decoding a selected array, representing one of the 256 DRAM arrays 302. Bits 0 through 7 of the address vector (designated by ADD <0:7>) are used for decoding an individual WL within the selected DRAM array 302. The command signal (CMD) is a signal corresponding to either a read or a write mode.
In one embodiment of the architecture 300 shown in FIG. 3, a direct mapping scheduling method for scheduling DRAM and SRAM access is contemplated. In a direct mapping scheduling method, a write back operation from the SRAM to a corresponding DRAM array is enabled only when new data to be copied to the SRAM from a different DRAM array comes from the same wordline. For example, if a read operation were to be executed for the data in wordline 0 of array <1>, but the SRAM already had data stored for wordline 0 from any one of the other arrays, then that previously stored data in wordline 0 would have to be written back to whichever array it came from before the SRAM could then store the new data contained in wordline 0 of array <1>.
For exemplary purposes only, scheduler 306 further supports 128 data inputs and outputs (corresponding to the maximum number bits obtained from a DRAM array 302) without a byte or bit masking function. When the scheduler 306 supports a smaller number of bits (e.g., 64), byte or bit masks, a different scheduling method is used. A data input pin (DI) and a data output pin (DO) are preferably not shared, although it will be appreciated the present embodiments are not limited in this manner.
The scheduler 306 further includes a TAG memory 308, which comprises 256 wordlines (WL), similar to the DRAM 302 and SRAM 304 arrays. The individual TAG memory 308 cells are accessed through ADD <0:7> in order to activate the corresponding WL. In turn, the TAG memory 308 cells activated by the corresponding WL store 8 array address bits (AB), identifying one out of 256 DRAM arrays, as well as a valid bit (VB) verifying the availability of the SRAM. More specifically, if the VB in a TAG memory is "1", the SRAM 304 contains the data bits for the corresponding DRAM array as identified by the bits AB.
A 3-phase pipeline stage scheme, preferably including: (1) TAG access and DATA input, (2) DRAM access, and (3) Data Output is used for the direct mapping scheduling method. Other pipeline schemes, however, are contemplated.
The operation of the DRAM architecture 300, using the direct mapping scheduling method will be understood with the following description. It is first assumed, initially, that a read mode is detected by a predetermined read command (CMD). Once a read mode is detected, the following pipeline scheme is enabled:
Phase I: The SRAM 304 immediately starts to check the data bits from the particular WL therein, as identified by the address vector ADD <0:7>. More particularly, the corresponding WL in the TAG memory 308 is accessed, also according to the input address vector (ADD <0:7>). The valid bit (VB) and the address bits AB are simultaneously read out from the TAG memory 308. The TAG memory 308 updates the bits AB (by setting AB=ADD <8:15>) and VB (by setting VB=1) for future access. A controller 310 located within the scheduler 306 checks the state of the valid bit (VB).
Phase II: If VB=0, then the SRAM 304 does not contain any data bits therein (Read MISS/NO Write Back). This enables a DRAM array read access mode. The controller 310 then activates the corresponding DRAM array read operation through ADD <0:15>, followed by an SRAM array write operation through ADD <0:7>. All data bits coupled to the activated WL in the addressed DRAM array are therefore copied to the SRAM 304 during this second pipeline phase. The data bits are also copied to a read buffer 312. If VB=1, then the SRAM 304 contains data bits from a previously accessed DRAM array 302. The controller 310 detects whether or not the address bits AB are same as in ADD <8:15>. It should be noted that this detection is done in the first pipeline phase. If the address bits are matched (Read HIT), the controller 310 will not enable a DRAM array read operation in this second pipeline phase. The data bits read from the SRAM 304 in the first pipeline stage are then copied to the read buffer 312.
However, if the address bits are not matched (Read MISS/Write Back), the controller 310 enables a DRAM read access mode for the corresponding DRAM array 302 identified with the address vector ADD <0:15>. The data bits from the corresponding DRAM array 302 are copied to the SRAM 304 and the read buffer 312. Simultaneously, the controller 310 enables a DRAM write back from the SRAM 304 to the corresponding DRAM array 302 identified by the address bits AB. The data bits read from the SRAM 304 in the first pipeline stage are then written back to the corresponding DRAM array 302 identified by the address bits AB and the address vector ADD <0:7>. A dual port SRAM is preferably used for this simultaneous read and write operation.
Phase III: Data bits are read out from the read buffer 312 to the data output pins (DO).
It is now assumed that a write mode is detected by a predetermined write command. When a write mode is detected, another pipeline scheme is enabled:
Phase I: The write data bits on the data input pins (DI) are placed in a write buffer 314. Simultaneously, the corresponding WL in the TAG memory 308 is accessed according to the input address vector (ADD <0:7>). The TAG memory 308 updates the address bits AB (by setting AB=ADD<7:15>) and VB (by setting VB=1) for future access. Beforehand, the controller 310 checks the state of valid bit (VB). Phase II: If VB=0, the SRAM 304 does not contain any data bits therein (Write MISS/no Write Back). The controller 310 therefore allows the SRAM 304 to store the data bits placed in write buffer 314 during the first pipeline phase. If VB=1, the SRAM 304 contains some data bits. The controller 310 detects whether or not the bits in AB are the same as the bits in ADD <7:15>. Similar to the read mode, the write mode detection is also done in the first pipeline stage. If the address bits are matched (Write HIT), the corresponding data bits in the SRAM 304 are overwritten.
However, if the address bits are not matched (Write MISS/Write Back), the data bits in the write buffer 314 are written to the SRAM 304, while transferring the previously stored data bits back to the corresponding DRAM array 302 (referred to hereinafter as Delayed Write Back). The TAG memory 308 should be updated for storing new data in the SRAM 304. Alternatively, without writing to the SRAM 304 and without updating the TAG memory 308, the data bits in the write buffer 314 may be directly written back to the DRAM core as a write through (referred to hereinafter as Write Through). VB in the TAG memory should then be overwritten to 0 if the SRAM contains the old data bits for the corresponding DRAM core prior to the write through. However, if the SRAM contains the data bits for another DRAM core not related to the write through, then the data bits and the valid bit VB should be kept as they are.
Phase III: No Operation
FIG. 4 is a data flow diagram illustrating an example of the DRAM and SRAM array operation using the direct mapping scheduling method described above. By way of example, only two of the DRAM arrays 302 (array <0> and array <1>) are used to illustrate the following commands received during eight sequential clock cycles:
1. write to DRAM array 0, wordline 0 (W 0, 0);
2. write to DRAM array 1, wordline 0 (W 1, 0);
3. write to DRAM array 0 wordline 1 (W 0, 1);
4. write to DRAM array 1 wordline 1 (W 1, 1);
5. read from DRAM array 0, wordline 0 (R 0, 0);
6. read from DRAM array 1, wordline 0 (R 1, 0);
7. read from DRAM array 0, wordline 1 (R 0, 1); and
8. read from DRAM array 1, wordline 1 (R 1, 1).
In the illustrated example, the preferred embodiment "Delayed Write Back" embodiment is used for the write mode.
During the first clock cycle, a command to write data into DRAM array 0 at wordline 0 is received. The data for (W 0, 0) transmitted on input pins DI is initially stored in the write buffer 314, as indicated by the thin solid arrow. It will be initially assumed that the SRAM 304 previously contained no data bits, and therefore the (W 0, 0) data may be stored in the SRAM 304 during the next pipeline phase (clock cycle). At the second clock cycle, write command is received for DRAM array 1, wordline 0. The (W 0, 0) data is shifted from the write buffer 314 and written into SRAM 304. At the same time, the (W 1, 0) data is stored in write buffer 314, as indicated by the thin dashed arrow.
During the third clock cycle, a write command is received for DRAM array 0, wordline 1. Again, the (W 0, 1) data is moved into write buffer 314, as indicated by the thick dotted arrow. However, since wordline 0 in the SRAM 304 already contains data therein (from (W 0, 0)), the SRAM must immediately write the (W 0, 0) data into the corresponding DRAM array so that it can store the (W 1, 0) data previously inputted into the write buffer 314 during the second clock cycle. Thus, at the end of the third clock cycle, DRAM array 0 contains the (W 0, 0) data, SRAM 304 contains the (W 1, 0) data, and write buffer 314 contains the (W 0, 1) data.
During the fourth clock cycle, a write command is received for DRAM array 1, wordline 1. Once again, this data is first stored into write buffer 314, as indicated by the thick solid arrow. However, it will be noted this time that since wordline 1 in SRAM 304 is clear, no immediate write back into DRAM takes place in this clock cycle. Instead, the (W 0, 1) data is now stored in SRAM 304, as well as the (W 1, 0) data stored during the third clock cycle.
Referring now to the fifth clock cycle, a read command is received for DRAM array 0, wordline 0. (It will be recalled that the (W 0, 0) data, inputted initially at the first clock cycle, was written into DRAM array 0 during the third clock cycle). Continuing along with the above described pipeline scheme, then, the (W 0, 1) data in SRAM 304 is written in DRAM array 0, wordline 1. This is because wordline 1 in SRAM 304 is now needed to store the (W 1, 1) data taken from the write buffer 312.
During the sixth clock cycle, a read command is now received for DRAM array 1, wordline 0. Because wordline 0 in SRAM is needed to store the (R 0, 0) data requested during the previous clock cycle, the (W 1, 0) data which has just been requested is finally written into DRAM array 1, wordline 0. Then, the data contained in DRAM array 0, wordline 0 is read therefrom and stored in both SRAM 304 and read buffer 312. Again, due to the destructive read architecture, the SRAM also stores the (W 0, 0) data because, at some point, it must be re-written back to DRAM array 0, wordline 0.
Referring now to the seventh clock cycle, a read command is received for DRAM array 0, wordline 1. Recalling that the previous read command was for the data in DRAM array 1, wordline 0, the SRAM wordline 0 is now needed. Thus, the (W 0, 0) data is immediately re-written back to DRAM array 0, wordline 0 to make room. At the same time, the data in DRAM array 1, wordline 0 is read therefrom into both SRAM 304 and the read buffer 312. The data read from DRAM array 0, wordline 0, which has just been written back thereto, but also previously stored in read buffer 312, is sent out through data output pins DO.
Finally, during the eighth clock cycle, a read command is received for DRAM array 1, wordline 1. Since wordline 1 of SRAM is needed to hold the data from the previous (R 0, 1) command, the (W 1, 1) data which has just been requested is finally written into DRAM array 1, wordline 1. Then, the data requested from DRAM array 0, wordline 1 is read into SRAM 304 and read buffer 312, while the previously stored data in read buffer 312 is outputted through data output pins DO.
From the foregoing, it will be seen that a total write back operation in a destructive read is realized using a direct map scheduling. Furthermore, because the SRAM array size is equal or larger than the largest DRAM array size, no SRAM overflowing occurs, even if the same array is continuously accessed. Once again, the data input pin (DI) and data output pin (DO) are preferably not shared in this example; however, other configurations are contemplated.
Referring now to FIG. 5, an embodiment of an alternative scheduling method 500 is illustrated by the flowchart therein. Method 500 begins with decision block 502 and determines whether a read command is detected, a write command is detected or no command is detected. If, for example, a read command is detected, method 500 proceeds to decision block 504 where it is then determined whether there is a "hit" or a "miss" in the SRAM. A "hit" means that the data to be read out is already contained within one of the SRAM addresses, while a "miss" means that the data is not in the SRAM. In the event of a "miss", the data to be read out is accessed from the corresponding DRAM array and copied into the lowest available SRAM address at block 506. Then, at block 508, the data from SRAM is read. On the other hand, in the event of a "hit", the data is already in SRAM and method 500 goes directly to block 508.
If at decision block 502, a write command is detected, then method 500 proceeds to decision block 512. Here, it is again determined whether there is an SRAM "hit" or "miss". After a "miss", (and in addition to proceeding to write back node 510) method proceeds to both blocks 514 and 516. At block 514, any data bits present are read from the corresponding DRAM. At the same time, the new data to be written is sent to the write buffer at block 516. Then the read data from the DRAM and the written data from the write buffer are merged and stored in the lowest available SRAM address at block 518. It will be noted that the merged data is not immediately written to the corresponding DRAM array, but instead is stored in the SRAM 518.
Regardless of whether a read, write or no command (NP) is detected, method 500 eventually proceeds to write back node 510, where a write back determination is made at decision block 520. The write back determination at decision block 520 determines whether there is any data in the SRAM at all (to be written back to the DRAM available for write-back). If there is no data which can be written back to a corresponding DRAM, then there is no further operation at that point. On the other hand, if there are data bits available for write-back, the oldest data stored therein (whether from a read operation or a write operation) is written back/written into the proper DRAM array at block 522.
FIGS. 6(a)-(c) illustrate a preferred pipeline diagram for the embodiment of the method described in FIG. 5. As shown in FIG. 6(a), the DRAM array read access operation is divided into four pipeline stages: command detection and address decoding (COM-DEC) 602 for the address vector ADD <0:15>; WL activation and signal development (WL-SIGDEV) 604; SA activation and SRAM data copy (SA-SRAM) 606, for sensing and transferring the data bits to the SRAM and the data read buffer; and a DQ read from SRAM (SRAM-DO) 608. A series of commands (numbered 0 through 4) are shown as they progress through the pipelines at each successive clock pulse (indicated by the vertical dashed lines).
In contrast to the embodiment of the direct mapping method discussed hereinbefore, the SRAM array 304 stores data bits in the lowest address data cells which do not contain any previously stored data bits. It should be noted that a DRAM array starts a BL and WL precharging operation at the third pipeline stage. In the fourth pipeline stage, the data bits are sent from the read data buffer to the data output pin, thereby resulting in a read latency of 4 (clock cycles).
In FIG. 6(b), a DRAM array write mode further includes a data input pipeline stage from data input pin (DI) with a write latency of 1 from the initial command detection thereof. Again, the first pipeline stage of the DRAM array write mode is the command detection and address decoding (COM-DEC) 602, as is the case with the DRAM array read access mode in FIG. 6(a). The second pipeline stage is WL activation and signal development (WL-SIGDEV) 604, which is also similar to the DRAM array read access mode. The second pipeline stage, however, includes a data input stage (DI) 610 from the data input pin to the write buffer, having a write latency of 1. Optionally, data bits may be fetched to the write buffer at the first pipeline stage, and may be digitally delayed to support a write latency of 0. In a third pipeline stage, the data bits are transferred from the sense amplifier to SRAM (SA-SRAM) 612; however, some data bits are overwritten by the data bits fetched in data write buffer (DI-SRAM) 614. For example, assuming that the DRAM array transfers 128 bits while having 64 data input pins, then 64 out of 128 bits are overwritten. Optionally, the overwrite function for some bits (e.g., 8 out of 64 bits) may be prohibited by utilizing a byte or bit mask command. These data bit handlings are enabled prior to the SRAM write mode. The SRAM therefore stores the data bits that have been handled for data inputs and/or byte or bit mask function. Similar to the DRAM array read access mode, the SRAM array stores data bits in the lowest address data cells which do not contain previously stored data bits for the write back.
Referring now to FIG. 6(c), a delayed write-back pipeline may be enabled when the corresponding DRAM array is available for writing back previously stored data bits in the SRAM. The first pipeline stage is a command and address decoding stage (COM-DEC) 602, which is again similar the other two pipelines. During this first pipeline stage, the scheduler determines whether or not the corresponding DRAM array is available for the second pipeline stage. It should be noted that, at most, only one DRAM array is unavailable at a given time for the DRAM data read at the second pipeline stage. If no command is given, then all the DRAM arrays are available for the DRAM write back. The scheduler first determines the data bits in the lowest address data cells which contain previously stored data bits for the write back. The scheduler then detects whether or not the DRAM array is available for the write back in the second pipeline stage. If it detects that the DRAM array is not available, the scheduler then chooses the next lowest address data cells which contain previously stored data bits a the write back operation. These detections and scheduling are done in the first pipeline stage. An actual write back operation (WL-Write Back) 616 will be enabled in the second pipeline stage according to this scheduling.
FIG. 7 is a timing diagram comparing internal and external operations for the to method in FIG. 5, in view of the pipeline schemes shown in FIG. 6. In FIG. 7, the "xyz" in the "Axyz" designations represent: the DRAM array (0 or 1), the command (R=read, W=write: B=Write Back), and the address. For example, the designation A0R0 means that a read mode command is detected for address 0 in the array 0, while the designation A0W7 means that a write mode command is detected for address 7 in the array 0. Further, the designation A1B9 means that a write back mode is detected for address 9 in the array 1.
The DRAM commands are detected by the address strobe (ADS) and write enable (WE), synchronized with a clock (CLK), and the array status. More specifically, if the ADS is high, a no operation command (NP) is detected. If the ADS is low, the DRAM accepts the address (ADD) shown in the pipeline. If the WE is high, the read mode is enabled, and the data bits are outputted to the data output pin (DO) with a read latency of 4. If the WE is low, the write mode is enabled, and the data bits from the data input pin (DI) with a write latency of 1. However, as discussed in the previous scheduling embodiment, a write mode latency of 0 could be used by adding an additional data input pipeline stage.
A write back operation in the corresponding array is scheduled when one of the following conditions is detected: (1) NP, (2) SRAM HIT, or (3) activation of other arrays. For example, the A0R0 command detected at clock cycle-1 triggers a write back operation for array 1 (A1B9). The A1R3 command detected at clock cycle 1 triggers the write back operation for array 0 (A0B0). The NP command detected at clock cycle 2 also triggers a write back operation for array 0 (A0B7). Then, the A0R5 command detected at clock cycle 3 triggers the write back operation for the array 1 (A1B3).
Finally, FIG. 8 illustrates a schematic of a exemplary DRAM cell structure 800 embodying the method illustrated in FIGS. 5-7. The structure 800 includes a cell 802, a BL equalizer (EQ) 804, a sense amplifier (SA) 806, and write drivers (WD) 808. NMOS multiplexers (MUX) 810 are also used for coupling between a BL pair to an SL pair for the destructive read pipeline operation. When a read or write mode is detected, the wordline (WL) goes high. This, again, results in the development of a signal on the BL pair. The WL is then deactivated, and equalizer (EQ) turns on simultaneously and immediately after the signal has been developed on the BL pair to recharge the bitlines. In this signal development phase, a pulsed signal RE periodically turns on the MUXs, coupling the BL pair to the SL pair. The signal transfer between BL pair to SL pair is fast, as the SL capacitance is very small. When the pulsed signal RE goes low, the SA 806 starts the SL sensing. A direct sensing scheme is preferably used; however, other sensing schemes are contemplated. (Additional information on sensing schemes may be found in "A 17 ns, 4 Mb CMOS DRAM", Takeshi Nagai, et. al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, pp. 1538-1543, November 1991, incorporated herein by reference.)
The sensing results are transferred to SRAM through a hierarchical data line (MDQ) 812, preferably arranged over the DRAM arrays. (Additional information on hierarchical data lines may be found in "Fault-Tolerant Designs for 256 Mb DRAM", Toshiaki Kirihata, et. al., IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, pp. 558-566, April 1996, incorporated herein by reference.) For a signal write back operation, the WL goes high. Simultaneously, the signal write back (WRTBACK) goes high, forcing the BL and BL bar go high and low, respectively, (or low and high) depending on the MDQ data pattern. Because all the BLs in a page are forced by the write drivers 808 avoiding a data bit destruction due to the BL-BL bar coupling effect, there is no late write penalty. The BL swing is halved from the conventional write full BL voltage swing, further improving the write back speed. The WL is deactivated, and equalizer (EQ) turns on immediately after the signal has been written back to the cell. The embodiment of FIG. 8 assumes a single data rate synchronous DQ interface, but the invention is not limited in this configuration. The protocol may also include a double data rate protocol for the interface, or may include a burst read and write operation.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
|Cited Patent
|Filing date
|Publication date
|Jul 13, 1995
|Nov 25, 1997
|Douglass; Barry G.
|Memory cell and method of operation thereof
|Jul 2, 1996
|Nov 25, 1997
|Douglass; Barry G.
|Memory element and method of operation thereof
|Jul 15, 1996
|Jul 21, 1998
|Mosys, Incorporated
|Method and structure for performing pipeline burst accesses in a semiconductor memory
|Nov 22, 1996
|Jul 20, 1999
|International Business Machines Corporation
|Method and apparatus of burst read and pipelined dynamic random access memory having multiple pipelined stages with DRAM controller and buffers integrated on a single chip
|Sep 11, 1997
|Sep 7, 1999
|International Business Machines Corporation
|Method of structuring a multi-bank DRAM into a hierarchical column select line architecture
|May 2, 1997
|Nov 23, 1999
|Enhanced Memory Systems, Inc.
|Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
|Jun 30, 1998
|Dec 21, 1999
|Lsi Logic Corporation
|Inherently compensated clocking circuit for dynamic random access memory
|Nov 4, 1997
|Apr 4, 2000
|The United States Of America As Represented By The Secretary Of The Navy
|Predictive read cache memories for reducing primary cache miss latency in embedded microprocessor systems
|May 12, 1998
|Jun 20, 2000
|Mosys, Inc.
|Method and structure for controlling operation of a DRAM array
|Sep 19, 1997
|Jul 4, 2000
|International Business Machines Corporation
|DRAM system with simultaneous burst read and write
|Mar 26, 1998
|Sep 5, 2000
|Compaq Computer Corporation
|Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control
|Feb 22, 1999
|Jan 23, 2001
|Nband Communications
|Cycle-skipping DRAM for power saving
|Oct 29, 1999
|Feb 13, 2001
|Hewlett-Packard Company
|MRAM device including digital sense amplifiers
|Aug 13, 1999
|Feb 13, 2001
|International Business Machines Corporation
|Method and system for improving DRAM subsystem performance using burst refresh control
|Jul 22, 1999
|Feb 20, 2001
|International Business Machines Corporation
|Floating bitline timer allowing a shared equalizer DRAM sense amplifier
|Feb 22, 1999
|Oct 30, 2001
|Nband Communications
|Low-power memory system with incorporated vector processing
|Nov 19, 1998
|May 14, 2002
|International Business Machines Corporation
|Restore tracking system for DRAM
|Aug 14, 2001
|Sep 10, 2002
|International Business Machines Corporation
|DRAM direct sensing scheme
|Takeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Simizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada and Syuso Fujii, "A 17-ns 4-Mb CMOS DRAM", IEEE Journal of Solid-State Circuits, vol. 26, pp. 1538-1543, Nov. 11, 1991.
|Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida ,Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke and Yoshiaki Asao, "Fault-Tolerant Designes for 256 Mb DRAM", IEEE Journal of Solid State Circuits, vol. 31, pp. 558-566, Apr. 4, 1996.
|Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida ,Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke and Yoshiaki Asao, "Fault—Tolerant Designes for 256 Mb DRAM", IEEE Journal of Solid State Circuits, vol. 31, pp. 558-566, Apr. 4, 1996.
|Citing Patent
|Filing date
|Publication date
|Oct 8, 2003
|Jul 12, 2005
|Infineon Technologies Ag
|Integrated memory
|Aug 26, 2004
|Sep 19, 2006
|Altera Corporation
|Dual port memory array using shared write drivers and read sense amplifiers
|Oct 14, 2004
|Jan 2, 2007
|Memocom Corp.
|Method of operating dynamic random access memory
|Aug 31, 2001
|Sep 25, 2007
|Intel Corporation
|Hardware updated metadata for non-volatile mass storage cache
|Aug 11, 2006
|Oct 30, 2007
|Altera Corporation
|Dual-port memory array using shared write drivers and read sense amplifiers
|Dec 31, 2001
|Jun 17, 2008
|Intel Corporation
|Distributed memory module cache writeback
|Dec 10, 2007
|Jul 12, 2011
|Foundry Network, LLC
|Techniques for detecting non-receipt of fault detection protocol packets
|Apr 2, 2007
|Sep 27, 2011
|Kristopher Chad Breen
|Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit
|May 14, 2009
|Jan 3, 2012
|Brocade Communications Systems, Inc.
|TCAM management approach that minimize movements
|Mar 13, 2009
|Apr 23, 2013
|International Business Machines Corporation
|Method and mechanism for delaying writing updates to a data cache
|Apr 8, 2011
|Dec 31, 2013
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|Aug 7, 2002
|Jan 23, 2003
|Daniel Litaize
|Multiple-mode memory system
|Dec 31, 2001
|Jul 3, 2003
|David Howard S.
|Distributed memory module cache writeback
|Oct 8, 2003
|Jun 10, 2004
|Reidar Lindstedt
|Integrated memory
|Oct 14, 2004
|Feb 2, 2006
|Hong-Gee Fang
|Method of operating dynamic random access memory
|Apr 2, 2007
|Sep 11, 2008
|Kristopher Chad Breen
|Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit
|Jul 18, 2007
|Nov 12, 2009
|Foundry Networks, Inc.
|Segmented crc design in high speed networks
|Mar 13, 2009
|Sep 16, 2010
|International Business Machines Corporation
|Method and mechanism for delaying writing updates to a data cache
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Apr 26, 2001
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
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text:
We're back, and excited to teach you a little bit about recycling metals! Most of us were taught the overall importance of recycling and the positive impact it has on our planet, but through this education, we weren't necessarily taught about metals in specific. This includes our metal soda cans, but it can also include other items such as cell phones.
Since many metal items are made up of precious metals worth conserving, it's best to recycle. This not only allows them to be reused instead of wasted, it protects our environment and our people. When placed in the garbage and sent to landfills, they are not broken down properly and may release harmful toxins, as well as contribute to global warming. This is especially true for electronics.
Recycling metals also helps with energy consumption. It takes less energy to process recycled metal, and we can save a substantial amount of time and energy by doing less mining, purifying and shaping. A large amount of this energy goes into aluminum, copper and steel.
The price of metal items has the potential to drop. Since there would be less time and money spent on making the products, the overall cost amount would decrease.
You may have noticed the rise in scrap metal recycling, but you can also use search engines available online for finding the right one for your specific metal or other recyclable item. Most of them are as easy as typing in what it is/what it's made of and a location. Other than these types of companies, there are ones specific to electronics. GoodCellas encourages consumers to recycle mobile phones for cash instead of throwing them away or letting them go to waste.
While we can't go back in time and fix what has already been done, we can make sure that we start doing our part as soon as possible. Recycle your metals!
The process of recycling a can is pretty interesting! Check it out:

subset: commoncrawl


text:
War On A RackFavorites [+]
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You can now enjoy this movie on your iPhone®, iPad®, or compatible Smart TV & Android devices.
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Available MP4 sizes:SD 480p (2.12 GB)
DRM-free downloads offer content that is not limited by standard Digital Rights Management (DRM) access technologies. These technologies allow hardware manufacturers, publishers, copyright holders and individuals to limit the usage of digital content.
When you purchase DRM-free downloadable content, that content is available for you to download on any computer and save to a disk whenever you like. You can also download to multiple computers. There is no timeframe associated with your purchase and the content will not expire.
Running Time: 146 minutes
Released: 07/2009
Studio Name: Zero Tolerance
Categories: Big Tits All Sex Award Winning Movies High Definition
Description: Prepare yourself for an all out assault on the largest lactoids in XXX! you'll be ready to "open fire" As our sluts take a pouncing, and their huge howitzers are bouncing. Whatever you call them, Tata's, Knockers, Milkers- You'll love our world class collection of colossal cans! Bottom Line... If you're a fan of huge hootered hotties getting fucked, sucked, prodded and rode, then we can proudly boast. "Mission Accomplished!"
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text:
The Fukui Astronomical Institute is a scientific and educational institute based on Earth. Some of the Federation's most brilliant minds work at the Fukui Institute, most notably Seven of Nine.
In early 2381, the F.A.I. discovered an unusual spatial anomaly in the Mutara sector nicknamed the "Fountain of Possibilities."
This anomaly turned out to be the most significant find in the Institute's 200-year history, as the anomaly's trans-temporal effects yielded not only the remains of the original USS Enterprise but a temporally-dislocated Klingon commander named Kruge. (Harry Potter and the Fountain of Possibilities)
Background InformationEdit
Just like the astronomical designation for the Guardian's World in Harry Potter and the Return of James T. Kirk, the Fukui Institute is a reference to the Japanese television series Iron Chef and more specifically the show's chief commentator, Kenji Fukui.


text:
This alternate history related article is a stub. You can help by expanding it.The Hon. Margret Rose Mayson (b. 14 October 1931) was the forty-first President-General of the United Provinces of America.
Mayson became the first female President-General in June, 1980.
| Preceded by:
Harrold Darling
President-General of the UPA
| Succeeded by:
Stanley Walker


text:
Take a look through my pics on here and explain which piercing you think would be the hottest.
I'm thinking of getting an ear done with a stud in it, but I definitely haven't dedicated to that choice yet.
I'm not an attention whore, I don't want you to say that I'm hot/cute whatever please just take this question for what it is.
If you can find a pic on the internet and can post a link that would be great by the way! :)
Most Helpful Girl
. . Do you actually need anything? You look fine, manly enough, so I'm sort of thinking if you had an earring, some of your . . . "fresh" appeal might be taken away from. But if you're going to go for the ears, try ear cuffs first. One, because they're sort of punkish without being. . overdone? Which could suit you if you wanted an entire style. And two, they come off- for the style chameleons, who go from a boy next door look to a motorcyclist, it's great but it also works when you're trying things out. No commitment. You ARE tall, wow, that's nice. . but I wouldn't want to look up and see a diamond in your ear. Call me old fashioned, but you have other assets that are actually part of you that could make much more of a . . statement, I guess you'd say, or define your personality more.
If you want actual physical change I'd go for maybe a smallish tattoo on a shoulder blade.10|10|0
I have a tattoo that I'm designing, I just need to finish it and then it's gonna go on my upper chest. It's big, but It will be positioned so that if I wear a loose shirt you could see it, but not if I wear a dress shirt. And I'm not limiting it to ears, that's just the first thing that came to mind. I like the other girl's idea of an eye piercing. Also, I'm gonna dye my hair black in the next few days, maybe I'll put a pic after I do that and you can have a better idea of what I look like now.
- Show AllShow Less
Remember to post a picture of the end result!
oh, scrap that- looks good!


text:
The Treasure of Verdauga Greeneyes was buried by the great wildcat somewhere in Kotir. After Kotir sunk into the lake, and Redwall Abbey was built over it, the treasure was located underneath the south wall.
The treasure was later discovered by Abbess Tansy, Friar Butty, Shad the Gatekeeper, Foremole Diggum, and Craklyn. Its location was indicated by a riddle carved by Verdauga in the walls of the northwest tower. It had been placed in a recess in a wall behind the carving of a wildcat biting a raven. However, when Tansy and her friends attempted to remove the carved stone covering, part of the wall collapsed and some of the treasure was buried among the rubble. As the five creatures tried to find their way back to the surface, they often used part of the treasure as tools.
The rescued treasure was eventually melted into medals of solid gold for the survivors of the Battle of the Ridge of a Thousand, wherein each medal was set with a gem. Redwallers received a ruby, waterhogs and otters a pearl, shrews a peridot and hares a bluejohn. Craklyn was appointed official keeper of the medals.
Known items in the treasure
- A silver spearhead studded with peridots with a silk tunic
- A gold platter
- A dagger with a hilt crusted with pearl and bluejohn stones and a golden blade
The Treasure of Verdauga Greeneyes appears in The Long Patrol.


text:
Everton winger Kevin Mirallas has revealed the revolutionary treatment that has got him off the sick list and back in David Moyes' team.
The £5.3million Toffees forward has been under the supervision of Dr Hans Muller-Wohlfhart – a German sports specialist nicknamed 'Healing Hans' – in a bid to cure the hamstring problem that had put his Goodison career on hold.
Dr Muller-Wohlfahrt injects his patients with the extract from a cockerel's crest and has also used calves blood in his treatment of top athletes like Olympic sprint champion Usain Bolt.
Mirallas got the recomendation from Belgian buddy Daniel van Buyten, the Bayern Munich defender. And he revealed: "I decided to turn to Hans after talking with my best mate in football, Daniel.
"If he's on the staff of Bayern Munich then he's obviously there for a reason. He's proved that he's a competent guy at what he does. He certainly did a good job for me. And so far so good. Things have gone well. It's worked for me. I just had this problem and as an option I decided to turn to him to try and cure it.
"We tried a certain method here at the club with the doctors and the physios and had a setback.
"So I chatted to Daniel and he said: 'Why don't you come and try here. He's very good. It might work out for you'. So I consulted with the club and with their blessing I travelled over to Germany. I went there with the club doctor and it was explained exactly what he was going to do.
"From the very first injection I started to feel a slight improvement in things. It was incredible.
"Let's hope the injuries are behind me now and that I can start to get a run of games together again."
Meanwhile, David Moyes is emerging as a shock target for Manchester City – if Roberto Mancini gets the sack.


text:
"Very many thanks for a quiet, clean and VERY warm holiday cottage"
Ross, Alnwick
Please click here to see our special Discount offers on the main attractions
Self Catering Holiday Cottage in Killin, Perthshire, Scotland
A recent European Union report highlighted that Scotland is actually one
of the quietest destinations across the whole of the continent
Bridge Park is a self catering holiday cottage which has a welcoming, friendly atmosphere where you can relax and feel completely 'at home'. It can sleep up to 5 in comfort. We know this because we stay in the cottage for a week or more each year.
It is situated in Glen Lochay, just half a mile outside the village of Killin in Perthshire, Scotland.
The cottage stands in the middle of a large sunny garden laid mainly to lawn and well stocked with shrubs and trees that offer complete seclusion and tranquility with glorious views up the glen and across the field to the river Lochay.
If you would like to have a close up look please click here then drop the Explore 'person' onto the road outside the cottage and have a look round.
Though situated in Glen Lochay it is in easy reach of the local shops, restaurants and amenities in the bustling village of Killin and is an ideal central base for exploring Scotland.
We look forward to hearing from you soon,
Peter and Victoria Jones.
Please go the Calendar page, for prices and availability, also try the Surrounding Countryside and Things to Do pages for more local information.
It is with regret that we find it necessary to require a £200 deposit in addition to the tariff.
This will be returned in full providing that no damage has been sustained.
We apologise to our regular clientele that we need to do this.


text:
Overview Edit
The NATO Intelligence Fusion Centre is a military led, U.S.-sponsored MOU organisation chartered by NATO's Military Committee. Located in the United Kingdom, the NATO IFC became fully operational in December 2007. The NIFC comprises over 200 multinational military and civilian intelligence and support professionals from 26 of 28 NATO nations and one North Atlantic Council (NAC) approved non-NATO nation.
The NIFC is directed by the Military Committee to significantly contribute to, but not replace, NATO Allied Command Operations (ACO) key intelligence activities. The NIFC remains outside national chains of command and NATO's permanent and crisis manning structures. The NATO IFC falls under the operational command of SACEUR through his Deputy Chief of Staff for Operations and Intelligence at SHAPE.


text:
We are celebrating Thanksgiving with friends this year, but are doing a family Thanksgiving the next day at home. Back in my teaching days, we always had the kids make woven paper pattern placemats for Thanksgiving. I had totally forgotten about that until this week when I saw that my daughter's preschool class was making placemats. I thought it would be great to make these with the kids at home because it reinforces fine motor skills while creating a beautiful pattern. It's super easy to make and only requires a few things you probably already have. Be sure to check out these Free Kindergarten Worksheets for Thanksgiving.
This post contains affiliate links. If you click one of them and make a purchase, Mess for Less will receive a small percentage of the sale, at no extra cost to you. These proceeds help keep the blog running. Thanks for your support
You will need:
- 9 x 12 Construction paper in Fall colors.
- Scissors
- Tape
Next, you will cut some strips out of the remaining colors of construction paper. Try to get these strips roughly the same size as the lines you cut on the larger piece of construction paper. It doesn't need to be exact though, so you can just eyeball it. You will want to make sure you don't cut any strips in the same color as your mat will be. We used 9 x 12 construction paper and found that 6 strips were enough to weave the entire paper.
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text:
environment not language
What I would love to see is a IDE that allows the functionality of VB, with the following additions
- pluggable language support
- pluggable toolkit support
Want to design a new app? Just fire up the IDE, select the language most appropriate for the desired task, and select the toolkit that you prefer. Python & GTk, no problem. C++ & QT, no problem.
A tool for securing DNS communications between a client and a DNS resolver.
A polyhedral extraction tool (PET).


text:
Providing You With The Steady Legal Guidance You Need
Contemplating filing for divorce? Let Attorney Dannie Boswell Botros put her aggressiveness, experience and trust to help you through this difficult time for you and your family. When you retain Attorney Dannie Boswell Botros, you will have the benefit of one-on-one contact with her. She has 30 years experience in family law and is an experienced litigator.
Contact Attorney Dannie Boswell Botros today if you need legal assistance with any of the following:
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Call Attorney Dannie Boswell Botros today at 806-340-7910 to arrange your free initial consultation.
Attorney Profile
Attorney Dannie Boswell Botros
- Texas, 1982
- Texas Tech University School of Law, Lubbock, Texas


text:
Lace Trim Leather Shorts
Lace trim leather shorts with lace hemline , hidden zipper closure in the back super cute for any time of the day, pair it up with a plain blouse, stack of jewelry, and ankle booties.
Faux leather
Hidden zipper closure in the back
Lace hemline
Measurments on size small approx. 11" long, waist approx. 13"


text:
This item is temporarily unavailable from the supplier though we still may have stock. Add to cart to check availability and for more information.
This comprehensive collection is a must for the wedding pianist! The music ranges in style from classical to contemporary and contains service music for preludes, processionals, bridal marches, unity candle
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Hosting Trek, a provider of hosting services, recently announced the 'Helping Hand Hosting' plan which gives non profit organizations and community focused businesses all the tools needed to get on the web.
The hosting plans are available in Windows or Linux and cost $8.25 a month. The Helping Hand hosting accounts come with a website builder tool – Easy Site Studio, two hundred email addresses for volunteers, free anti virus, and other services.
A company spokesperson stated; "This new advantage that we're offering to community based organizations isn't all about features, virtual storage, or anything like that. It's about lending a helping hand to groups that do so much for their communities. Most of them don't have the funding to have an online presence nor do they understand how valuable one can be. It is our goal to help these groups succeed further in their causes by using the benefits made possible through the internet."


text:
In a bid to take stringent action against those who submit bogus caste certificates for personal gain, the city-based Dr Babasaheb Ambedkar Research and Training Institute (BARTI) has organised a special four-day training programme for caste scrutiny officers across the state.
The aim behind conducting the training, which began in Mumbai on Saturday, is to introduce a system under which records of bogus certificates will be maintained so that strict action can be would be taken against those who submit bogus certificates to get caste-based benefits. No such system exists currently.
"The Maharashtra Judicial Academy has taken the responsibility to train these officers. As many as 132 caste scrutiny officers and police officers attached to caste scrutiny committees are attending the training.
The training is focused on how to follow the principles of natural justice and deal with bogus claims firmly," said Director of BARTI, D R Parihar.
He added that, in light of the increasing number of bogus caste certificates being submitted, steps are being taken to sensitise the officers who are handling these cases.
"It was clearly mentioned in the Caste Certificate Issuance And Verification Act, 2001, that anyone who submits a bogus certificate will be liable to be imprisoned for a term of 6 months-2 years and/or to pay a penalty of up to Rs 20,000," Parihar said.
"Taking a serious note of this provision, I had already given the order to all caste scrutiny committees across the state to take strict action against those who violate the Caste Verification Act," he said.
Number of officers attending the training in Mumbai


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Hotel City: Cheats, Tricks, and Tips
Welcome to Hotel City!
Hotel City is the newest, free, Facebook game from Playfish, the makers of Pet Society and Restaurant City.
In Hotel City, you and your friends can become hotel moguls, building and customizing your very own hotels to gain the coveted 5-star ranking!
Once you play it this new Facebook game, you'll be hooked! That's why I've compiled a list of cheats, tricks and tips to help you conquer Hotel City!
Naming Your Hotel
First things' first, You need to name your hotel. Don't stress about it,
you can change it later. Your hotel's name will show at the top of the game-play screen and all your friends on Hotel City will be able to see it.
Having trouble figuring out a name? Here are some ideas to help you get started:
- Use words like "Hotel, Motel, Chateau, Resort, Grand."
- If you're planning a theme for your hotel, put it in your hotel's name. Ex. If you want a beach themed hotel, try the "Seashell Resort."
- Keep your hotel's name short, avoid names over 5 words long.
Tutorials: Gotta Love 'em
When you first move into Hotel City, you'll be introduced to the game through the tutorial. This will show how to get started and where all the buttons are.
You're given $50,000 to get started and only 1 room, your reception lobby. To begin getting customers into your hotel, you'll need to build guestrooms, a cleaning closet, and a gym. But don't worry, the Hotel City game tutorial will show you how to do all of these!
Hiring Staff
Your hotel can't run by itself! You're going to need a whole crew to keep it up and running.
When you first start your hotel, you'll need to hire temporary staff, also known as "Temps" to run your reception desk, cleaning closet, and gym. The wages for temps are determined by 2 things.
- How long you want their shifts to be (the longer the shift, the more expensive they are)
- How many facilities you have that require workers (Ex: cleaning closets, gyms, restaurants)
An alternative to hiring temps is to hire permanent staff.
Hiring permanent staff reduces the cost of wages. To hire permanent staff, you'll send out a feed to your Facebook friends asking for people to work at your hotel. The more friends you have who will work for you, the lower the wages you'll have to pay!
Your Grand Opening!
Congratulations! Your hotel is ready for it's big debut! Time to make some money!
You make money whenever a guest visits your hotel. How much money depends what they're doing when they come. They could be checking into a room or working out at the gym. Here is a Price Guide so you know where you'll earn money!
- Budget Room: 1 Coin per 2 minute stay
- Small Room: 3 Coins per 3 minute stay
- Large Room: 7 Coins per 4 minute stay
- High Ceilinged Room: 10 Coins per 4 minute stay
Commercial Rooms:
- Gym: 2 Coins per 5 minute stay (up to 3 guests)
- Posh Restaurant: 3 Coins per 5 minute stay (up to 3 guests)
- Bar: 1 Coin per 4 minute stay (up to 6 guests)
- Small Cinema: 2 Coins per 6 minute stay (up to 5 guests)
- Swimming Pool: 6 Coins per 5 minute stay (up to 3 guests)
- Arcade: 1 Coin per 2.5 minute stay (up to 3 guests)
Other Ways To Make Money In Hotel City
Earn Money by Visiting Other Hotels:
Every day, you can visit other local hotels (your friends' hotels) to earn a special bonus! When you visit them, you'll find a money bag located in their reception lobby. To claim your bonus, click on all the money bags you find while visiting friends!
Earn Money by Poking Sleeping Guests:
You can also earn coins by clicking on the guests who are staying in guestrooms. When they lay down on the bed, you can click them once to see if you got the bonus of 400 Coins! Not all guests will give you the bonus, so cross your fingers that you'll get lucky!
Send Your Friends A Free Gift
Who doesn't love free stuff?
Now you can send your friends a completely free gift! Facebook Game Gift requests for Hotel City get sent to their "Requests" page. Once they've accepted the gift, it'll show up in their storage in the actual game! Odds are, the more gifts you send out to your friends, the more you'll also get back in return!
Reception Desk Emergency Calls
A newly added feature of Hotel City is the reception desk phone! When guests have complaints or emergencies, it's your job as hotel manager to resolve these problems. Each time you resolve a situation, you'll earn coins!
Your guests will call the reception desk when they're too cold, burning up, or even being haunted by a scary ghost. Once you notice the green phone at the bottom of the screen, you'll have to find the room that's making the phone call.
Don't worry, if you don't see the phone or miss the call, nothing bad will happen. There are no penalties for not answering the reception desk phone.
Selling and Gifting Items
Playfish is currently working on giving you the ability to sell and gift the items you own!
Selling Items:
Selling items you don't want anymore is a great way to earn back a little extra cash from a previous purchase. As your hotel grows, you may want to replace some of the plain standard beds that come in every guestroom. Selling things like these extra beds will give you more money to buy newer and nicer items.
Gifting Items:
Gifting items is also an awesome feature which allows you to send particular items you own as gifts to your friends. This is great when you're trying to help out a fellow hotel friend who is just starting up and could use a little motivation!
Hotel Giant 2
Enjoy Your Stay!
Hotel City is a fun, new game, unlike most of the other Facebook games! Can't wait to see what Playfish comes up with next!
~ Laura
Sim Games
Tycoon Games
More Game Hubs from Lauralolita
- Treasure Isle: Cheats, Tips, and Tricks
Welcome to Treasure Isle! Let's get right down to business. If you have played any other Zynga game, you'll know that there are two currencies in all their games, including Yoville and Petville.
- Facebook Games: How to Earn Money on Petville
Petville, one of the more recent additions to the Zynga family, has two different pet-currencies, or forms of money, like most other Zynga games.
- Yoville on Facebook: Cheats, Tricks, and Tips
Yoville uses two forms of currency, Yocoins and Yocash. Yocoins can purchase anything from food for energy to clothing and furniture. However, not all things can be bought with Yocoins.
Thank You for putting this up, after reading your blog on Hotel City, I made the decision to Join it....Now just to invite my friends to play it along with me. Again Thanks for the Info....You gave some Great advice!
Wow, my wife loves this game, I know because she floods me with all of those posts on facebook! Thanks for all of the GREAT TIPS AND TRICKS! I'll be sure to tell her about this hub!
So, when I had 8 temp staff it was costing me 12000-13000 for 24 hour shift.
NOW with only 4 temp staff, and 4 friends it's costing me 15000! for a 24 hour shift! THIS MAKES NO SENSE!!!!!!! It just keeps going up no matter how many temp staff I have. Are they going to be charging me 25000$ If i have no temp staff?
I have 5 friends working for me but it only gave 3 of them jobs. the other 2 friends names are just up there. But I have 3 temps and its telling me to hire more friends. but when my friends reapply its saying the position has already been filled.SMH!!!!! Does anyone know how to fix this problem? Because im ready to erase my hotel and start over. But im trying to hold off on that cuz im at level 15 and i want a cinema.
I ordered 520,000 coins through Moneybookers back on April 4th... my card was charged... but I never received the 520,000 coins.... So I hope Playfish comes through on this!
Sounds great! I don't have the playing experience but seems it would be wonderful! Thanks for the great hub!
Hey, how come no one will go into my gym? Before it worked, now it's not! I have people working there.
I need help! I have started my hotel but I hate the order I put my rooms in, is there anyway to start the game over completely?
Hey, how come everyone that visits my hotel always leaves are two minutes sleeping and they wake up and they have like a fork and a knife above there head what does that mean I really need help and I have no money to buy a resturant and everything I have enough I can't find the resturants, help me please.
iv sent out the hire friends request but i wont put them on my temp staff just as neighbors!!! and also hotel city is giving me more temp staff than i have! i only hve 2 cleaners but it say i have three??
Does anyone know how to make the URL for hiring staff? I have seen it on the hotel city fan page on facebook. It enables you to just click on the link and then you work for that person. Any help would be appreciated :) Also do you know if this adds the person just to your hotel or to your facebook page as well?
Can I send purchased gifts to other friends? I am a new for this game, just want to know badly. Thank you :")
well i all ready new all of these stuff .... but thanks any way i am sure that it will come in good handy for other people..thanks agai and good luck with ur hotel
do you get more money if you have different decorations in every room?
too make more money..
visit your friend that show "new" words,
save the game.
reload your page.
do the same thing again..
but not to rich, or u'll b leg on the page..hehe..
this game is so much fun and i love it so..so..so much..
and it's a cute game too. thanks to the programmers that made this game. BTw My Hotel help my stress to cool down too. =)
I play it 18 hrs every days to make my hotel look cute and i arrange the room every time if i like.. hehehe
How do you make a link for a job?!?
Please help!
I love this hotel city, but the server always error and stuck in the page, .. please make it more faster and no error.
i wondered why almost all people visiting my hotel leave with a shopping cart above their heads...any ideas?
I already got a gift shop, but people are still leaving my hotel with shopping carts above their heads! I dont know whats going on? do i need to buy another one? please help!
thank you!! even though i dont want to buy one.... ^_^
oh well thanks anyway!
What the heck does the Grocery Cart Mean??
Please Help(:
okay, can you get more than one location on hotel city?? can you have the san fransico room while on the beach with the beach shack?
best way to increase the number of neighbours and hire permanent staff is to create your own fake accounts on facebook.......i have 5 of them....and the rest my friends have taken place in the job........so create some fake ones if you are experiencing problems with staff salary!!!!
How to change hotel city locations ???
hotel city gave me free money!! i went from having like 100 000 and now i have about 1 000 000! i dont know how this worked but i like it :D maybe it rewards its awesome hotel city players :P
i think to make a lot of money on the hotel you need to make more bussines and less rooms. and get the ones that are for 5 people its better.
This game is so much fun.. Thanks for the Info....
how can we get playfish cash & coins
How do I place rooms? I can't seem to put them!
why can't i find luxuries in my hotel and my friends hotel
I named by hotel differently and with your tips i'm gonna fix some terms. cheers
I don't have money so I need many money for shifting.
I have a question, I invested in a friend (paid 1000$) and it said that if this friend reaches level 10, I get 100,000$ as return on investment. This friend is currently at level 11, and when I look at my portfolio it says "investment unavailable" ... how can I get my return on my investment ? thank you !
I like
I'm sad that its closed I wish it wasnt


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Hello, fellow humans!
Guess who's officially broken up for Christmas? Oh, yeah – that would be me. I spent my first day of freedom watching Christmas movies and pigging out and- it. Was. Awesome. (The last one was Love Actually – am I the only one who wanted the widow dad and the cheated on wife to get together? And what happened to Carl and Alan Rickman's employee whose name I cannot remember? For that matter – what happened to Alan Rickman and his seductress assistant? Yeah; he's tempted to cheat on his frankly awesome wife with a young, hot, foreign assistant. Nobody blew any brain cells there. I now need to do a Christmas Movies review post. It shall be done.)
Also, I may have possibly bought myself a little Nightmare Before Christmas necklace because I love Jack Skellington so much. Seriously – I sympathise with Sally's swooning. She's only . . . okay, well, I guess she's not human. Whatever.
Back to the point!
So, I've actually completed pretty much all of my Christmas shopping! I know – I managed to do it before Christmas Eve; I'm growing up. Now, I would love to show you all what I bought everybody . . . but I wrapped it. And not very well either; all those dreams of beautiful packages sitting under a glittering tree are just that – dreams.
We don't even have a tree up yet.
So, as I clearly cannot bring you all the brilliant Christmas presents I went and bought everyone, what am I showing you? Why, all the brilliant presents I bought myself.
First off, can we just talk about something that I've wanted since all the way back here in August – my dragon print trainers!
Yes – the first thing I bought were a pair of trainers. And they're beautiful.
I bought these as the last pair from a stockist on Ebay, so unfortunately I cannot link them – which is why I bought them now, rather than waiting until after Christmas, like everything else; when they're gone, they're gone. They're from Rita Ora x Adidas SS 15 collection (My obsession with dragons cannot be curbed – back in summer, I bought a dress with the same print from the same collection. And it's beautiful and I recieve compliments for it whenever I wear it. You need a picture now, don't you?)
It seemed a bit like a big buy considering I was soon to be Christmas shopping, but my Amazon cheque finally cleared (international banks do not communicate as if it's the 21st century.) and I figured that . . . well, if I want to blog more about fashion, this purchase was more an investment. (BTW – if you want to know how I earned that cheque – check the post out here!)
Next up – well, some more things from the wishlist. This is actually a tip of mine to get the most out of your money – create a wishlist (I personally use Padlet.com . . . let me hit you up with a screenshot) of things you want and need and, when you get the urge to shop, pick things off there. Trust me on this – you will automatically refine and change your wishlist until the only things left on it are things you actually want. It's like magic.
Besides, a good general rule of thumb is that if you can sit and pine over a product for over three months – you actually want it. Next up, though . . .
Forever 21
So, as I have cried over not only here but in all of my gift guides, I actually bought myself a hand chain and matching ring set from Forever 21.
Now, these I can link for you!
If you don't think these are gorgeous, I'm sorry but you're wrong and possibly blind. It is my sincere recommendation that you head straight out to a doctors. Please – it's for your sake, not mine.
Next up was this "Make Your Own" necklace set; I'd been eyeing this for a while, but wondered if it was actually worth it. And then. And then. I realised, in a white hot flash of epiphany, that another thing I wanted but didn't know if it was worth it would go perfectly with this.
And that, folks, is what you call a happy ending.
Link, link, link – okay, I think this is out of stock, because I cannot find it, but it was £9.
Why would they even care about that if they can't get it for themselves? Sorry. God, girl, get your act together.
Now, these rings are a possible gift idea for one of my friends and are adorable.
Babe rings – £2 . . . and these are also not in stock. However, there are a lot of really cute alternatives.
We have kittens. That is all I can say to excuse Blackie's tail in my photograph. If there is paper, rustling, sound, movement, breathing, air, or just a human being they know they can get affection off of (namely me because I'm the one that's a: home most and b: nocturnal and willing to play with them when they're hyper at 3am) they will be there.
These two final cute bits were more to tip me over the £21 mark; if you spend £21, you get free shipping – so I thought why not grab a few little essentials?
Okay, so that's the Forever 21 section of my shopping all did. Now, time for a brief but necessary kitten interruption as I show you how fucking hard they made taking these pictures.
Now – enough of Blackie and Whitey (no, that is not their "official" names. Yes, that is what they are called.) Back to pretty things.
New Look
As tempted as I was to buy a watch, all I bought from New Look was a bottle.
Yes, you read right – a bottle. Just wait for it; you'll see.
This year's production of "The Mermaid Milkshake Bottle" is proudly presented to you by the white kitten. Yep. It's a really cute bottle that says mermaid milkshake on it. And it has a candy cane straw. I'm a happy human.
And, last but not least . . .
Word to the wise – if you're looking for some really fantastic deals on gifts this Christmas, look no further than BHS. I got both my mum and grandma some really great sets for just over a tenner.
How much was this gorgeous palette? About £2.50. Live Love London is having a brand launch at BHS, so all their make-up palettes and sets and whatever else is all majorly reduced. I like to think I restrained myself by only getting this one, because this was actually bought while I was out shopping for other people.
But it's so gorgeous and perfect for Christmas party make-up.
Thanks for reading you little rascals – I'm half surprised you made it this far, but you never disappoint, so the other half of me is just slowly applauding your dedication. That's my pre-Christmas shopping haul done – what were your favourite things I picked up? And have any of you picked up any . . . "blog investments" for yourself?
Merry Christmas!


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New England Patriots 2009 PreviewJuly 13, 2009
But that all came crashing down in Super Bowl XLII, when the New York Giants pulled off one of the biggest upsets in modern day sports history. Led by a tenacious pass rush that disrupted the aerial circus all evening and a strangely poised Eli Manning, the Giants ended the Patriots quest at perfection with a 17-14 victory that will go down in the annals of history as one of the best games ever.
Entering the 2008 regular season, many believed the Patriots would end the string of teams that seemingly couldn't shake the heartbreaking championship loss just months prior. Fans called this the so-called "Super Bowl Loser Curse" and unlike many superstitions, this one seemed to hold water.
Only the 2006 Seahawks had been able to make the playoffs following a loss in the Super Bowl this decade, but when you looked at the level of competition in the Patriots division and a roster that was loaded from top to bottom, the Patriots return to the playoffs seemed like a foregone conclusion.
Then, relatively unknown Kansas City Chiefs safety Bernard Pollard changed that a mere seven minutes and change into the first quarter of the opening day game when an unfinished block by the usually reliable Kevin Faulk led to an unfortunate low hit on Tom Brady's knee.
Brady's knee was ripped to shreds, the Patriots season suddenly took a new look. The Super Bowl loser curse appeared to have struck yet again.
But the Patriots would not go down without a fight, as should be expected from a team coached by Bill Belichick. Untested quarterback Matt Cassel would become the starter the rest of the season, which became a new role for him.
Cassel hadn't started a game since his senior year of high school, but as the weeks passed by and as Cassel became more and more comfortable with Josh McDaniels offense, the longtime backup to Tom Brady started to look the part of an NFL starting quarterback.
After doing just enough to get by the Brett Favre led Jets, the Patriots hosted the Dolphins and were ripped to shreds by a new offense that no one had seen before. The 'wildcat' outsmarted Belichick's defense all afternoon as Ronnie Brown ran for four touchdowns and threw another during Miami's 38-13 pounding of New England.
The loss sent shockwaves all throughout the NFL. The Patriots from last year appeared to be dead and gone. Writers and pundits from all over were ready to christen New England's season as an afterthought and began looking at other teams in football as the new favorites.
Maybe that's what fueled New England long enough for them to stay alive in 2008. Because following the loss to Miami the Patriots would win four of their next six contests and were tied at the top of the AFC East with the New York Jets at 6-3.
And as fate would have it, the Patriots would just so happen to have a game scheduled with those New York 'Bretts' in Week 11 of the season. At the time, it seemed like the game would determine who would be in the drivers seat the rest of the way.
Matt Cassel put together the game of his career, and outgunned the legendary Favre by throwing for 400 yards and 3 touchdowns including a touchdown pass to Randy Moss that would send the game into overtime with one second left in regulation. The Patriots erased a 24-6 deficit and tied the game at 31.
However, the Patriots defense would not be able to hold the Jets again, and a Jay Feely field goal in overtime would send the Jets to the victory and put the Patriots a game out of first place.
Cassel and the Patriots would get their revenge over the Dolphins a week later with a 48-28 beat down at Dolphins stadium. Cassel became the fifth quarterback since the merger to throw for over 400 yards in back to back games, and the Patriots were sitting at 7-4 in the division, still a game behind the Jets. The Dolphins were 6-5 and an afterthought in the division.
But that afterthought wouldn't lose another game for the rest of the regular season, and the Jets would begin to free fall. The Patriots were in the unfortunate situation where winning out wouldn't even guarantee them a playoff spot due to the strength of the AFC as a whole.
A date with the Pittsburgh Steelers loomed on the horizon, and the Steelers were looking for blood after being torn to pieces a season ago. Matt Cassel had not yet experienced a defense as tenacious and relentless as the Steel Curtain, and after posting back to back 400 yard, 3 touchdown performances he was grounded with only 169 yards and two interceptions.
The Steelers went on to win 33-10, leaving the Patriots with a huge loss down the stretch.
Cassel and the Pats would go on to post a perfect 4-0 mark in December, but it wouldn't be enough. The Colts would finish 12-4, with one of those wins being a late game victory over the Patriots back in Week 9, and the Ravens would also finish 11-5 but held tiebreakers over New England which assured them of the final playoff spot in 2008.
And so the Super Bowl losers curse took it's batting average to 8 of 9 this decade, and the Brady-less Patriots were left watching the postseason from the comfort of their own homes despite finishing 2008 with three more victories than the AFC West champion Chargers.
2009 Free Agency Additions:
CB Shawn Springs (Washington)
TE Chris Baker (New York Jets)
RB Fred Taylor (Jacksonville)
LB Paris Lenon (Detroit)
S Brandon McGowan (Chicago)
C Al Johnson (Miami)
DE/LB Tully Banta-Cain (San Francisco)
WR Joey Galloway (Tampa Bay)
LB Vinny Ciurciu (Minnesota)
WR Greg Lewis (Philadelphia)
LB Mike Vrabel (Traded to Kansas City)
CB Ellis Hobbs (Traded to Philadelphia)
S Rodney Harrison (Retired)
FB Heath Evans (New Orleans)
RB Lamont Jordan (Denver)
WR Jabar Gaffney (Denver)
ST Larry Izzo (New York Jets)
WR Kelley Washington (Baltimore)
DE Darrell Robertson (Kansas City)
LB Bo Ruud (Cleveland)
2-34. Patrick Chung, SS, Oregon
2-40. Ron Brace, NT, Boston College
2-41. Darius Butler, CB, Connecticut
2-58. Sebastian Vollmer, OT, Houston
3-83. Brandon Tate, WR, North Carolina
3-97. Tyrone McKenzie, LB, South Florida
4-123. Rich Ohrnberger, G, Penn State
5-170. George Bussey, G, Louisville
6-198. Jake Ingram, LS, Hawaii
6-207. Myron Pryor, NT, Kentucky
7-232. Julian Edelman, WR, Kent State
7-234. Darryl Richard, DE/DT, Georgia Tech
Brady will once again inherit an offense with a ridiculous amount of talent at wide receiver. Randy Moss may once again claim the title of best receiver in football with Brady's return and Wes Welker is without question the most dangerous slot receiver in football.
While the Patriots again appear to be the team that spreads it out via the pass, they would like to assimilate some sort of a running game and will deploy a running back by committee approach in 2009 led by Laurence Maroney and free agent acquisition Fred Taylor.
The Patriots offensive line returns in tact from the team that went 18-1 in 2007 with Matt Light and Nick Kaczur starting at tackle, Logan Mankins and Stephen Neal starting at guard, and Dan Koppen starting at center.
Defensively, the Patriots lost veterans Rodney Harrison (retirement) and Mike Vrabel (traded with Matt Cassel to Kansas City) in the offseason, but replenished their roster with young talent in the draft.
The linebacking corps will be headlined by 2008 Defensive Rookie of the Year Jerod Mayo and longtime vet Tedy Bruschi. The Patriots will also see the return of Adalius Thomas, who missed a large part of last season with a broken forearm.
The Patriots secondary will be without Ellis Hobbs after he was traded to Philadelphia, and the aforementioned Rodney Harrison, but they added Leigh Bodden and Shawn Springs to a relatively young defensive backfield.
|Mon 9/14
|Sun 9/20
|at NY Jets
|Sun 9/27
|Sun 10/4
|Sun 10/11
|at Denver
|Sun 10/18
|Sun 10/25
|at Tampa Bay
|Sun 11/8
|Sun 11/15
|at Indianapolis
|Sun 11/22
|NY Jets
|Mon 11/30
|at New Orleans
|Sun 12/6
|at Miami
|Sun 12/13
|Sun 12/20
|at Buffalo
|Sun 12/27
|Sun 1/3
|at Houston
As is usually almost always the case, Bill Belichick and company continued to add key cogs to an already explosive team and will once again be a force to be reckoned with this season.
Of course all of this is with the assumption that Brady's knee is indeed healthy and that he will be able to start all 16 games in 2009. If Brady were to miss any extensive period of time again this year, the Patriots will not be as lucky as they were with Matt Cassel stepping in to keep the Patriots in the thick of the AFC Playoff Picture.
I'll go out on a limb and say Brady will return to form, and that this Patriots team can very well be better than the one we saw two seasons ago - although they won't run the table, which in the long run will probably be better for them anyway.
The run to Miami will go through Gillette Stadium in the AFC. And whether you love them or hate them, the New England Patriots are back.
Predicted Finish: 13-3, 1st place AFC East


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DNC or file transfer between computer and CNC Control.
Use this security logo:
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Upgraded Help File
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In accordance with copyright laws, the purchase price entitles the purchaser to the use of one copy of this software package on one computer.
Since CNC Consulting has no control over the configuration of the user's computer, nor the way in which the software is used, we accept no responsibility whatsoever for any loss or damage caused by the use of this software.
Questions regarding error messages, or bugs in the software can be emailed to email@example.com, and we will attend to your needs as soon as possible, usually by the next business day.
Note regarding registration of ConnectCNC:
All versions of this software, except the thirty-day demo version, must be paid for and registered.
Registration of the software, with its update privileges, is not complete until invoiced amounts are paid in full.
Invoiced amounts unpaid after thirty days will accrue interest at the rate of 2% per month until CNC Consulting receives payment.


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Average Price: $30.00
This is my favorite moisturizer of all time. Its light and not greasy and absorbs very fast. I have normal to dry skin so it really helps me out. Its nice because it is SPF 30.
After searching through the aisles at Shoppers Drug Mart, searching for a new face mositurizer I decided upon the Biore Dual Fusion Moisturizer SPF 30. I've tried Biore products and have been pleasantly surprised so when I saw this one, I thought why not. It was a little pricey at $30 dollars but ones face is not something to mess around with. I also liked the fact that it has a spf of 30. I'm fair and freckle very easily so sun protection is extremely important. Don't let the small bottle fool you either. Even though it's only 50ML, all you'll need is one pump. Half the bottle is full of a white substance, the other half with a green substance. One moisturizer, one SPF. It goes on incredibly matte as well. I have combination skin so a moisturizer that doesn't go on oily is important. The SPF is perfect. Can't say enough good things about this moisturizer.
These reviews are the subjective opinions of ChickAdvisor members and not of ChickAdvisor Inc.


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Research Engineer
Deadline to apply: Wednesday, November 30
Submit resume to: [email protected] and write Research Engineer (Newtown) in the subject.
Job Title: Research Engineer
Education: Bachelor, Master, or Ph.D. degree in Electrical engineering or Physics
Experience Level: > 2 Years (Exceptional fresh graduates are encouraged to apply)
Salary Range: Depends on qualification
Location: Newtown, PA, USA
We're looking for a talented Research Engineer who is creative and highly driven. The position requires working in a fast-paced environment where engineers, physicists, and technicians work closely together. The candidate is expected to conduct research, invent new ideas and concepts, and assist in product development. Strong team spirit and a positive attitude are essential.
- Excellent understanding and experience with artificial intelligence algorithms and tools for pattern recognition and machine learning.
- Thrives on solving challenging and open-ended problems in physics and engineering through research, careful experimentation, and often thinking out of box.
- Exceptional mathematical and modeling skills, and inquisitiveness to understand the fundamentals of any technology.
- Highly motivated, a team person, and willingness to learn and improve on a daily basis.
Primary Responsibilities
- Conduct research and develop of new technologies and algorithms to facilitate Senstar's technological edge in the market place.
- Support product development and meet project and customer-driven deliverables and deadlines.
- Program in Matlab and LabVIEW for solving problems.
- Assist other engineers in solving challenging technological problems.
- Support Technical Support, Operations and Sales when assigned by Manager.
- Document all work in a professional manner so that similarly qualified engineers can understand and reproduce.
Contact us today to speak with a Senstar representative about your security needs.