text:
Module Introduction. CONTENT: - 31 pages - 6 questions. LEARNING TIME: - 60 minutes
- Joshua Kelley
- 2 years ago
- Views:
1 Module Introduction PURPOSE: The intent of this module is to present all CPU12 instructions to better prepare you to write short routines in assembly language. OBJECTIVES: - Discuss all CPU12 instruction sets. - Describe data handling instructions. - Identify arithmetic instructions. - Describe logic instructions. - Identify data test instructions. - Describe branch instructions. - Discuss jump and subroutine calls. - Identify the HCS12 CPU features that support high-level language programs. CONTENT: - 31 pages - 6 questions LEARNING TIME: - 60 minutes The intent of this module is to present all CPU12 instructions to better prepare you to write short routines in assembly language. You will become more familiar with Data Handling, Arithmetic, Logic, Data Test, Branch, and finally, Jump and Subroutine Calls. You will learn about the HCS12 CPU features that support high-level language programs and you will be better prepared to write these programs.
2 HCS12 Instruction set Superset of the M68HC11 instruction set CPU12 implementations: - the original M68HC12 - and the newer HCS12 All memory and I/O are mapped in a common 64-Kbyte address space Full set of 8-bit and 16-bit mathematical instructions Let s start with the HCS12 instruction set. CPU12 instructions are a superset of the M68HC11 instruction set. Code written for an M68HC11 can be reassembled and runs on a CPU12 with no changes. The CPU12 provides expanded functionality and increased code efficiency. There are two implementations of the CPU12, the original M68HC12 and the newer HCS12. Both implementations have the same instruction set, although there are small differences in cycle-by-cycle access details. For example: the order of some bus cycles changed to accommodate differences in the way the instruction queue was implemented. These minor differences are transparent for most users. In the M68HC12 and HCS12 architecture, all memory and input/output (I/O) are mapped in a common 64-Kbyte address space (memory-mapped I/O). This allows the same set of instructions to be used to access memory, I/O, and control registers. General-purpose load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory and peripherals. The CPU12 has a full set of 8-bit and 16-bit mathematical instructions. There are instructions for signed and unsigned arithmetic, division, and multiplication with 8-bit, 16-bit, and some larger operands. Special arithmetic and logic instructions aid stacking operations, indexing, binary-coded decimal (BCD) calculation, and condition code register manipulation. There is also dedicated instruction for multiply and accumulate operation, table interpolation, and specialized fuzzy logic operations that involve mathematical calculations.
3 Instruction Set Data Handling Arithmetic Logic Data Test Branch Jump & Subroutine Calls To reference the information in the CPU12 Users Manual, see the document CPU12RM/AD or go to Most instructions are standard 68xx, but some new and efficient opcodes have been added. Here, we will briefly cover the CPU12 instruction set to help you better understand the program examples during this module. Let s look at the various instruction types that the CPU12 supports. The data handling instruction type includes Loads, Stores, Pulls, Push, Transfers, INC, DEC, Rotates, and Shifts. The arithmetic instructions include ADD, SUB, and MULT. The logic instructions include AND, OR, and EOR. The data test instructions include Bit Test and Compare. The branch instructions include conditional branches such as Branch if not equal,(bne), Branch if higher, (BHI) and many more conditional branches. The HCS12 allows the program to jump to any memory address during program execution, and the jump to subroutine instruction may be used to call a routine that needs to be executed on periodic bases. To reference the information in the CPU12 Users Manual, see the document CPU12RM/AD or go to the web site listed here.
4 Load and Store Instructions Load instructions copy memory content into an accumulator or register. The memory content is not changed by the operation. Load instructions (excluding LEA_ instructions) affect condition code bits. As a result, no separate test instructions are needed to check the loaded values for negative or 0 conditions. The LEA instruction calculates an effective address and puts it into a destination register. For example: LEAX B and Y adds register B to register Y and puts the sum into register X. Neither register B or Y contents are affected by this operation. If register Y equals $1000 and register B equals $25, the resulting value in register X will be $1025. Store instructions copy the content of a CPU register to memory. Register and accumulator content is not changed by the operation. Store instructions automatically update the N and Z condition code bits, which can eliminate the need for a separate test instruction in some programs.
5 Data Move Instructions Moves the content of one memory location to another memory location. The content of the source memory location is not changed. EXAMPLE: MOVW 2,X+, 2,-Y MOVB 1,Y+, 1,X+ MOVB 2,X+, 2,Y- MOVW 2,X+, 2,-SP MOVW 2,X+, 2,Y+ The function of the data move instructions is to move the content of one memory location to another memory location. As a result, the content of the source memory location is not changed. Move instructions use separate addressing modes to access the source and destination of a move operation. The following combinations of addressing modes are supported: IMM EXT, IMM IDX, EXT EXT, EXT IDX,IDX EXT, and IDX IDX. IDX operands allow indexed addressing mode specifications that fit in a single post byte including 5-bit constant, accumulator offsets, and auto increment/decrement modes. Nine-bit and 16-bit constant offsets would require additional extension bytes and are not allowed. The Move instructions support Auto increment, Pre-Decrement, Post Increment and post Decrement addressing modes as shown in the example above
6 Data Movement Data Handling Instructions Now, let s look at Push and Pull instructions. Push instructions save the content of a register onto the stack area. The Stack Pointer (SP) is decremented by one or two depending on whether the size of the register is 8 or 16 bits, respectively. The content of the register is then stored at the address where the SP points. Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine. The Push operation does not affect the Condition Code Register (CCR). Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before the subroutine execution. The Pull instructions do not affect the CCR unless it is pulled.
7 EXAMPLE: PSHX BEFORE MEM INCREASING ADDRESSES Stack Operation B7 B0 EXAMPLE: PSHX AFTER B7 MEM B0 INCREASING ADDRESSES SP $4000 TOP OF STACK SP $3FFE SP $3FFF SP $4000 XH XL TOP OF STACK EXAMPLE: PULD BEFORE B7 MEM B0 INCREASING ADDRESSES EXAMPLE: PULD AFTER B7 MEM B0 INCREASING ADDRESSES SP SP SP $3FFE $3FFF $4000 DH DL TOP OF STACK SP $4000 TOP OF STACK Here, you can see the Push operation depicted. Note that the SP is decremented by two and then the X register is pushed onto the stack. The Pull operation works exactly the opposite of Push. On the HCS12DP256, the RAM ends at location $3FFF. Putting the SP to $4000 is usually a good choice since the stack grows toward lower memory addresses.
8 Question What type of addressing should you use with PSHA? Select the correct response and then click Done. a. Extended Addressing b. Inherent Addressing c. Indexed Addressing You have just learned about push and pull instructions. See what you remember by answering this question. The type of addressing you should you use with PSHA is (SP) 1 => SP; (A) => SP M(SP).
9 Question When are Pull instructions commonly used? Select the correct response and then click Done. a. Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution. b. Pull instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. c. Pull instructions are commonly used to move the contents of one or more CPU registers at the start of a subroutine. d. Pull instructions are commonly used at the beginning of a subroutine to restore the contents of CPU registers that were pulled onto the stack before subroutine execution. Here is another question to check your understanding of the Push and Pull instructions. Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution. The Pull instructions do not affect the Condition Code Register unless the CCR is pulled.
10 Transfer and Exchange Data Handling Instructions FUNCTION MNEMONIC OPERATION TRANSFER DATA TBA TAB B A A B TXS TYS R SP TSY TSX SP R TRANSFER REG TO REG TFR A, B, CCR, D, X, Y, SP A, B, CCR, D, X, Y, SP EXCHANGE EXG A, B, CCR, D, X, Y, SP A, B, CCR, D, X, Y, SP EXCHANGE DATA XGDX XGDY D D X Y EXAMPLE 1: TFR X,A EXAMPLE 2: EXG Y,B Now, let s examine transfer and exchange instructions. Transfer instructions copy the content of a register or accumulator into another register or accumulator. The source content is not changed by this operation. Transfer register to register (TFR) is a universal transfer instruction, but other mnemonics are accepted for compatibility with the M68HC11. The transfer A to B (TAB) and transfer B to A (TBA) instructions affect the N, Z, and V condition code bits in the same way as M68HC11 instructions. The TFR instruction does not affect the condition code bits. The sign extend 8-bit operand (SEX) instruction is a special case of the universal transfer instruction. It is used to sign extend 8-bit 2 s complement numbers so that they can be used in 16-bit operations. The 8- bit number is copied from accumulator A, accumulator B, or the condition code register to accumulator D, the X index register, the Y index register, or the SP. All the bits in the upper byte of the 16-bit result are given the value of the Most-significant Bit (MSB) of the 8-bit number. Exchange (EXG) instructions exchange the contents of pairs of registers or accumulators. When the first operand in an EXG instruction is 8-bits and the second operand is 16-bits, a zero-extend operation is performed on the 8-bit register as it is copied into the 16-bit register.
11 Alter Data Data Handling Instructions FUNCTION MNEMONIC OPERATION DECREMENT DEC DECA DECB DEX DEY DES (M)-1 (M) A-1 A B-1 B X-1 X Y-1 Y S-1 S INCREMENT INC INCA INCB (M)+1 (M) A+1 A B+1 B INX INY INS X+1 X Y+1 Y S+1 S The increment and decrement instructions are optimized 8- and 16-bit addition and subtraction operations. They are generally used to implement loop counters. These instructions add one or subtract one respectively to the content of the memory location or a register. The N, Z and V status bits are set or cleared according to the results of the operation. The C status bit is not affected by the operation. This allows the INC and DEC instructions to be used as a loop counter in multiple-precision computations. When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. When operating on 2 s complement values, all signed branches are available.
12 Clear, Complement, and Negate Data Handling Instructions FUNCTION MNEMONIC OPERATION COMPLEMENT, 2'S (NEGATE) NEG NEGA NEGB 0-(M) (M) 0-A A 0-B B COMPLEMENT, 1'S COM COMA COMB (M) A B (M) A B CLEAR CLR CLRA CLRB 0 (M) 0 A 0 B BIT(S) CLEAR BCLR (M) MASK (M) BIT(S) SET BSET (M) + MASK (M) Bit Manipulation Example: BSET OFFSET,X, #MASK Now let s examine Clear, Complement and Negate instructions. Each of these instructions performs a specific binary operation on a value in an accumulator or in memory. Clear operations (CLR) clear the value to 0 and complement operations replace the value with its 1 s complement. Negate operations (NEG) replace the value with its 2 s complement. NEG affects N, Z, V, and C. It replaces the contents of Accx or Memory (M) with its 2 s complement. However, the value $80 is left unchanged. Complement (COM) affects only N and Z. It clears V and sets C. It replaces the contents of Accx or Memory (M) with its 1 s complement. CLR (write 0 s to operand) clears N, V, C, and sets Z. The contents of Accx or M are replaced with 0 s. Bits Clear (BCLR) and Bits Set (BSET) are used so SET and CLEAR memory operand bits given by 1 s that are set in the instruction s operand mask. For BCLR (clear multiple bits in location M). The bits to be cleared are specified by 1 s in the mask byte. For BSET (set multiple bits in location M). The bits to be set are specified by 1 s in the mask byte. The BSET and BCLR instructions affect N and Z, clears V, and leaves C unaffected. Users are tempted to use bit manipulation to clear timer system status flags. Note that timer flags are cleared by writing a 1 to the flag after having read it while it was a 1. If you use BSET instruction, you may clear more flags than intended. This is because you would clear any flag in the register that happened to be set during the operand read cycle of the BSET instruction, and not just the bits that were set in the mask of the BSET instruction. You could use BCLR with a mask that has 1 s in bits to be cleared. BCLR instruction ANDs operand with the inverse of the mask.
13 MAX and MIN Instructions Data Handling Instructions The maximum (MAX) and minimum (MIN) instructions are used to make comparisons between an accumulator and a memory location. These instructions can be used for linear programming operations, such as simplex-method optimization, or for fuzzification. MAX and MIN instructions use accumulator A to perform 8-bit comparisons, while EMAX and EMIN instructions use accumulator D to perform 16-bit comparisons. The result, which is a maximum or minimum value, can be stored in the accumulator (EMAXD, EMIND, MAXA, MINA) or the memory address (EMAXM, EMINM, MAXM, MINM). Click Example A to see a comparison between register A and memory locations pointed by X register. When an operand is found in memory lower than the value in A register, the loop ends and the lower value is loaded from memory to A register. The MIN and MAX instructions assume that the operands are unsigned. N, Z, V and C flags of CCR are updated according to the result of the operation.
14 Example A Example: LOOP MINA 1,X+ BHS LOOP This example compares register A and memory locations pointed by X register. [The content on this page is the Example A ]
15 Shift and Rotate DATA HANDLING INSTRUCTIONS FUNCTION MNEMONIC OPERATION ROTATE LEFT ROL ROLA ROLB M A B C b7 b0 ROTATE RIGHT ROR RORA RORB M A B C b7 b0 SHIFT LEFT, ARITHMETIC (LOGICAL) ASL(LSL) ASLA(LSLA) ASLB(LSLB) ASLD(LSLD) M A B D C b7 b0 A B C b15 b0 0 0 SHIFT RIGHT, ARITHMETIC ASR ASRA ASRB M A B b7 b0 C SHIFT RIGHT, LOGICAL LSR LSRA LSRB LSRD M A B D 0 0 b7 b15 A B b0 b0 C C Now let s look at shift and rotate instructions. There are shifts and rotates for all accumulators and for memory bytes. They all pass the shifted-out bit through the C status bit to facilitate multiple-byte operations. Because logical and arithmetic left shifts are identical, there are no separate logical left shift operations. Logic shift left (LSL) mnemonics are assembled as arithmetic shift left memory (ASL) operations. Rotate Left (ROL) and Rotate Right (ROR) instructions rotate the operand in a register or a memory location through carry bit. ROL shifts all bits of Accx or M one place to the left. ROR shifts all bits of Accx or M one place to the right. There is no 16-bit rotate for ACCD. Logical and arithmetic Shifts all affect condition code register bits N, Z, V, and C. LSL and ASL are identical in operation and use same opcode. ASL shifts all bits in Accx or M one place to the left. Note that Left Shifts is an efficient way to multiply by powers of two. Arithmetic Shift Right (ASR) shifts all of Accx or M one bit to the right. BIT 7 is shifted into bit 6 but bit 7 is held constant since this is the operand sign bit. Likewise bit 6 is shifted into bit 5 and so on, and finally bit 0 is shifted into the Carry bit (C-Bit). Right Shifts is an efficient way to divide by powers of two.
16 Question Match each instruction type to the statement that describes it by dragging the letters on the left to their corresponding items on the right. Click Done when you are finished. A Transfer instructions B Are optimized 8- and 16-bit addition and subtraction operations B Increment and decrement instructions D Are used to make comparisons between an accumulator and a memory location C Clear, complement, and negate instructions A Copy the content of a register or accumulator into another register or accumulator D MAX and MIN instructions C Perform a specific binary operation on a value in an accumulator or in memory E Shift and rotate instructions E Pass the shifted-out bit into the C Flag bit allowing the software to test each shifted bit, if necessary Done Reset Show Solution Let s review some characteristics of the data handling instructions we have just looked at. Transfer instructions copy the content of a register or accumulator into another register or accumulator. The Increment and decrement instructions are optimized 8- and 16-bit addition and subtraction operations. The clear, complement, and negate instructions perform a specific binary operation on a value in an accumulator or in memory. The MAX and MIN instructions are used to make comparisons between an accumulator and a memory location. Finally, all shift and rotate instructions pass the shifted-out bit into the C Flag bit allowing the software to test each shifted bit, if necessary.
17 Data Test Instructions FUNCTION MNEMONIC TEST BIT TEST BITA BITB A B (M) (M) COMPARE CBA CMPA CMPB A-B A-(M) B-(M) TEST, ZERO OR MINUS CPD CPX CPY TST TSTA TSTB R L-(M+1) R H-(M)-C COMPARE STACK CPS SP - ( M :M +1) (M)-0 A-0 B-0 Compare and test instructions perform subtraction between a pair of registers or between a register and memory. The result is not stored, but condition codes are set by the operation. These instructions are generally used to establish conditions for branch instructions. In this architecture, most instructions update condition code bits automatically, so it is often unnecessary to include separate test or compare instructions.
18 Conditional Branch Instructions MNEMONIC CONDITION CCR TEST INDICATION (L) BMI MINUS N=1 r=negative (L) BPL PLUS N=0 r=positive *(L) BVS OVERFLOW V=1 r=sign ERROR *(L) BVC NO OVERFLOW V=0 r=sign OK *(L) BLT LESS [N V]=1 *(L) BGE GREATER OR EQUAL [N V]=0 A < M A >= M *Use for signed arithmetic only *(L) BLE LESS OR EQUAL [Z+(N V)]=1 A <= M *(L) BGT GREATER [Z+(N V)]=0 A > M (L) BEQ EQUAL Z=1 A=M (L) BNE NOT EQUAL Z=0 A <> M (L) BHI HIGHER [C+Z]=0 A > M (L) BLS LOWER OR SAME [C+Z]=1 A <= M (L) BCC (BHS) CARRY CLEAR C=0 A >= M (L) BCS (BLO) CARRY SET C=1 A < M Indication refers to the use of a CMPA M instruction immediately before the branch Branch instructions cause a program sequence to change when specific conditions are met. The CPU12 uses three kinds of branch instructions. These are short branches, long branches, and bit condition branches. Branch instructions can also be classified by the type of condition that must be satisfied in order for a branch to be taken. Some branch instructions belong to more than one classification. The list of branch instructions above support algebraic and non-algebraic comparison operations. For example, a non-algebraic 8-bit operand can be in the range of hex 0 to hex FF, which can represent a value between 0 to 255 decimal. For algebraic 8-bit operand, the maximum positive value that can be represented is from 0 to hex 7F, which is equal to plus 127 decimal. Where as the value of hex 80 hex FF represent the values of minus128 to minus 1 decimal. Click Example B to see an example that compares register A with memory locations pointed by X register. CPU12 supports two type of branches, short and long. Short branches use an 8-bit signed offset which is added to the value of the Program Counter (PC) when the condition is met. The branch ranges from +127 to -128 locations. Long branches use 16-bit signed offset allowing the CPU to branch anywhere in the 64K memory map.
19 Example B Example: Next: CMP A,X+ ; Compare A to memory location pointed to by (X) BNE Next: If not equal, loop back to next The example above compares register A with memory locations pointed by X register. The program will loop until a value in memory found that compares to register A. Note: Register x increment with every iteration. [The content on this page is the Example B ]
20 Conditional Branch Instructions FUNCTION MNEMONIC OPERATION DECREMENT & BRANCH DBEQ COUNTER - $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC DBNE COUNTER - $01, COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC INCREMENT & BRANCH IBEQ COUNTER + $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL IBNE COUNTER + $01 COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC PC TEST & BRANCH TBEQ IF COUNTER = 0, THEN PC+$ REL PC TBNE IF COUNTER <>0, THEN PC+$ REL PC With loop primitive instructions, the loop primitives can also be thought of as counter branches. The instructions test a counter value in a register or accumulator (A, B, D, X, Y, or SP) for zero or non-zero value as a branch condition. There are pre-decrement, pre-increment, and test-only versions of these instructions. The numeric range of 8-bit offset values is $80 or ( 128) to $7F (+127) from the address of the next memory location after the offset value. Click Example C to see an example that moves a block of data from memory location pointed by Y register to memory location pointed by X register. The BDNE instruction subtracts a 1 from the loop counter register D and if the loop counter has not yet decremented to $0000, the program will continues to loop.
21 Example C EXAMPLE: LOOP - MOVW 2,Y+, 2,X+ DBNE D,LOOP - The example above moves a block of data from memory location pointed by Y register to memory location pointed by X register. The X and Y registers are incremented by two to point to the next word in memory. [The content on this page is the Example C ]
22 Branch if Bits Set or Clear BRSET BRCLR (M) MASK SERVICE OCL OP CODE OPERAND MASK BRANCH DISP. The Mask value is used to test bit or bits in the memory operand. Example: A value of $80 in the mask, tests bit 7 of the operand in memory. A value of $61 in the mask, tests bits 6 and 1. Addressing modes allowed are: DIR, EXT, IDX, IDX1 & IDX2. Let s look at bit condition branch instructions. The bit condition branches are taken when a bit or bits in a memory location are in a specific state. A mask operand is used to test the byte location. If all bits in the location that corresponds to the ones in the mask are set using the BRSET instruction, the branch is taken. The numeric range of 8-bit offset values is $80 ( 128) to $7F (127) from the address of the next memory location after the offset value. The Branch if bit or bits cleared, BRCLR instruction test for zero or zeros in the memory location specified, depending on the value in the mask field. Bit condition branch instructions are useful for polling interrupt status flags and for making program decisions based on bit values. Each branch is taken from the next instruction address (OCL +4, 5, OR 6 ). Addressing modes that are allowed include DIR, EXT, IDX, IDX1, and IDX2. Click Example D to see an example of Port D bit 7 instruction tested.
23 Example D EXAMPLE: WAIT BRCLR PORTD,X $80 WAIT The example above instruction tests Port D bit 7 and stays in this short loop until the bit is set. This instruction is useful for polling the status of a port pin or even an I/O device flag. [The content on this page is the Example D ]
24 Question Which of following statements about condition branch instructions are true? Select all options that apply. Branch instructions cause a program sequence to change when specific conditions are met. All instructions belong to more than one classification. Branch instructions can be classified by the type of condition that must be satisfied in order for a branch to be taken. Some instructions belong to more than one classification. Consider this question regarding condition branch instructions. The CPU12 uses three kinds of branch instructions; short branches, long branches, and bit condition branches. Branch instructions can be classified by the type of condition that must be satisfied in order for a branch to be taken. Only some instructions belong to more than one classification.
25 Add/Decimal Adjust Instructions FUNCTION MNEMONIC OPERATION ADD ADDA A + (M) A ADDB B + (M) B ADDD D + (M+1) D ; D + M + C D L H H L ADD ACCUMULATORS ABA ABX ABY A + B X + B Y + B A X Y ADD WITH CARRY ADCA ADCB A + M + C B + M + C A B DECIMAL ADJUST DAA CONVERTS BINARY ADDITION OF BCD CHARS INTO BCD FORMAT Next, we will examine add and decimal adjust instructions. First, let s look at ABY. This is one of the rare places the instruction set isn t entirely general. You can add B to X or Y but you can t add A to X or Y. ABY is useful for calculating offsetts into multi-dimensional arrays. If you want to do 16-bit arithmetic on X or Y, just do XGDX then 16-bit arithmetic such as ADDD, then XGDX again. Note that X acts as temp for D in this sequence. All Add instructions update Condition code register bits N, Z, C, H and V. ABX and ABY (adds ACCB to index register X or Y) and it does not affect condition code, CCR register field. ABX and ABY are useful for pointing index register to a new (calculated) address. Add with Carry,ADDC instruction includes the carry bit in the addition operation to support multiprecision addition. DAA is only of use immediately after executing ADDA to transform the accumulator s hexadecimal results to decimal, using the half carry bit.
26 Subtract & Multiply Instructions FUNCTION MNEMONIC OPERATION SUBTRACT SUBA A (M) A SUBB B (M) B SUBD D (M+1) D ; D (M) C D L L H H SUBTRACT ACCUMULATORS SBA A B A SUBTRACT WITH CARRY SBCA SBCB A (M) C B (M) C A B MULTIPLY MUL A * B D EXTENDED MULTIPLY EMUL D * Y Y : D EXTENDED MULTIPLY EMULS D * Y Y : D SIGNED Now, let s discuss subtract and multiply instructions. SUBA instruction Subtracts Memory location specified from A and places the difference in accumulator A. SBA instruction Subtracts B from A and places the difference in accumulator A. SUBD instruction Subtracts 16-bits from memory location specified and places the difference in accumulator D. All other instruction that includes C in the operation, will subtract with Carry. The subtract operation always affect N, Z, V, and C. MUL is 8x8 unsigned multiply giving a 16-bit result. MUL takes 3 clocks & affects C bit according to bit 7 (ACCB bit 7) of 16-bit result.
27 Divide Instructions INTGER DIVIDE 16/16 UNSIGNED OR SIGNED (IDIV/IDIVS) OPERATION RESULT INTEGER DIVIDE D REG / X REG QUOTIENT IS IN X REMAINDER IS IN D IDIV/IDIVS RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB EXTENDED DIVIDE 32-BIT BY 16-BIT UNSIGNED OR SIGNED (EDIV/EDIVS) OPERATION (Y:D)/ (X)! Y; REMAINDER! D V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000 V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000 C = 1, IF DIVISOR WAS $0000 Let s look at the description of Integer Divide (IDIV) 16/16 Unsigned or Signed. This divides an unsigned/signed 16-bit dividend in double accumulator D by an unsigned/signed 16-bit divisor in index register X. This produces an unsigned/signed 16-bit quotient in X, and an unsigned/signed 16-bit remainder in D. The signed 16-bit dividend depends on whether the IDIV or IDIVS is used. If both the divisor and the dividend are assumed to have radix points in the same positions, the radix point of the quotient is to the right of bit 0. In the case of division by zero, C is set, the quotient is set to $FFFF, and the remainder is indeterminate. The condition codes for IDIV are: Z equals 1 if the quotient equals 0; C equals 1 if the divisor equals 0. The condition codes for Fractional Divide (FDIV) are: Z equals 1 if the quotient equals 0; V equals 1 if the dividend is greater than the divisor; C equals 1 if the divisor equals 0. Now let s examine extend divide 32/16 unsigned or signed. This divides a 32-bit unsigned/signed dividend by a 16-bit divisor, depending on whether the EDIV or EDIVS is used. This produces a 16-bit unsigned/signed quotient and an unsigned/signed 16-bit remainder. All operands and results are located in CPU registers. If an attempt to divide by zero is made, the contents of double accumulator D and index register Y do not change. C is set and the states of the N, Z, and V bits in the CCR are undefined. EDIV/EDIVS are useful for A/D and D/A calculations. Their result values can be compared to ratiometric A/D results. Also, the results are in correct form to drive a weighted D/A. Examine the condition codes in the grey box to see how.
28 Fractional Divide Instruction Fractional Divide (FDIV) The radix point of the result is to the left of the MSB If the numerator is greater than or equal to the denominator, then V Flag is set. Result Examples: A result of 1 is 1/$10000 which is.0001 A result of $C000 is $C000/$10000 which is.75 A result of $FFFF IS $FFFF/$10000 which is.9999 Here are the Fractional Divide (FDIV) instructions. FDIV may be executed after IDIV to resolve the remainder. In fact, FDIV can follow another FDIV to resolve more bits past the radix point. If the numerator is greater than or equal to the denominator, then V Flag is set which indicates an overflow condition is generated by this operation. Ratiometric A/D and D/A values are also weighted binary fractions. These express the analog value as a fractional portion of the analog reference. For example $C000 means 3/4 or 0.75 (base 10) of the reference value. This idea also extends to percentage calculations. FDIV is intended for use when the dividend is less than the divisor allowing for fractional results to be obtained. If the FDIV is successful, then the quotient (in X register) equals 0 and the remainder is a 16 bit fractional value in ACCD. If FDIV fails, when the dividend is greater than the divisor, then the quotient (in X register) equals $FFFF and the remainder is undefined.
Lecture 3 Addressing Modes, Instruction Samples, Machine Code, Instruction Execution Cycle
Lecture 3 Addressing Modes, Instruction Samples, Machine Code, Instruction Execution Cycle Contents 3.1. Register Transfer Notation... 2 3.2. HCS12 Addressing Modes... 2 1. Inherent Mode (INH)... 2 2.More information
M6800. Assembly Language Programming
M6800 Assembly Language Programming 1 3. MC6802 MICROPROCESSOR MC6802 microprocessor runs in 1MHz clock cycle. It has 64 Kbyte memory address capacity using 16-bit addressing path (A0-A15). The 8-bit dataMore information
Programming the Motorola MC68HC11 Microcontroller
Programming the Motorola MC68HC11 Microcontroller CONTENTS: COMMON PROGRAM INSTRUCTIONS WITH EXAMPLES MEMORY LOCATIONS PORTS SUBROUTINE LIBRARIES PARALLEL I/O CONTROL REGISTER (PIOC) COMMON PROGRAM INSTRUCTIONSMore information
HC12 Assembly Language Programming
HC12 Assembly Language Programming Programming Model Addressing Modes Assembler Directives HC12 Instructions Flow Charts 1 Assembler Directives In order to write an assembly language program it is necessaryMore information
Microcontroller Basics A microcontroller is a small, low-cost computer-on-a-chip which usually includes:
Microcontroller Basics A microcontroller is a small, low-cost computer-on-a-chip which usually includes: An 8 or 16 bit microprocessor (CPU). A small amount of RAM. Programmable ROM and/or flash memory.More information
THUMB Instruction Set
5 THUMB Instruction Set This chapter describes the THUMB instruction set. Format Summary 5-2 Opcode Summary 5-3 5. Format : move shifted register 5-5 5.2 Format 2: add/subtract 5-7 5.3 Format 3: move/compare/add/subtractMore information
CPU08 Central Processor Unit
CPU08 Central Processor Unit Reference Manual M68HC08 Microcontrollers CPU08RM Rev. 02/2006 freescale.com CPU08 Central Processor Unit Reference Manual To provide the most up-to-date information, theMore information
6800 Basics. By Ruben Gonzalez
6800 Basics By Ruben Gonzalez 6800 Processor Uses 8 bit words Has addressable main memory of 64k Has Memory Mapped I/O and interrupts The 6800 has the following main registers: 8- bit Accumulator A (AccA)More information
Introduction to Microcontrollers
Introduction to Microcontrollers Motorola M68HC11 Specs Assembly Programming Language BUFFALO Topics of Discussion Microcontrollers M68HC11 Package & Pinouts Accumulators Index Registers Special RegistersMore information
The stack and the stack pointer
The stack and the stack pointer If you google the word stack, one of the definitions you will get is: A reserved area of memory used to keep track of a program's internal operations, including functions,More information
Programming Model, Address Mode, HC12 Hardware Introduction
EEL 4744C: Microprocessor Applications Lecture 2 Programming Model, Address Mode, HC12 Hardware Introduction Dr. Tao Li 1 Reading Assignment Microcontrollers and Microcomputers: Chapter 3, Chapter 4 SoftwareMore information
Decimal, Hexadecimal and Binary Numbers Writing an assembly language program
Decimal, Hexadecimal and Binary Numbers Writing an assembly language program o Disassembly of MC9S12 op codes o Use flow charts to lay out structure of program o Use common flow structures if-then if-then-elseMore information
U:\montages\dominique\servo\moteur_AV_AR\program\moteur_AV_AR.asm jeudi 28 avril 2011 10:32
Norton Junior Moteur PWM AV - AR pour SLE BRESSUIRE PORTA ------------------------------------------------------- 0 = Entrée Servo 1 = PWM moteur 2 = Strap mode 3 = 4 = 5 = Relay AV - AR $Include 'C:\pemicro\ics08qtqyz\qtqy_registers.inc'More information
How It All Works. Other M68000 Updates. Basic Control Signals. Basic Control Signals
CPU Architectures Motorola 68000 Several CPU architectures exist currently: Motorola Intel AMD (Advanced Micro Devices) PowerPC Pick one to study; others will be variations on this. Arbitrary pick: MotorolaMore information
The 68000's Instruction Set
The 68000's Instruction Set We have included this appendix to save you the task of having to turn to secondary material when writing 68000 assembly language programs. Since most programmers are not interestedMore information
Sample Problem Set #1 - SOLUTIONS
Sample Problem Set #1 - SOLUTIONS Notes: These problems are typical exam problems; most are drawn from previous homeworks and exams. This exam is open book, open notes. It may help to have a calculator.More information
DATA TRANSFER INSTRUCTIONS Opcode Operand Description 8085 INSTRUCTION SET INSTRUCTION DETAILS Copy from source to destination OV Rd, Rs This instruction copies the contents of the source, Rs registerMore information
Representation of Floating Point Numbers in
Representation of Floating Point Numbers in Single Precision IEEE 754 Standard Value = N = (-1) S X 2 E-127 X (1.M) 0 < E < 255 Actual exponent is: e = E - 127 sign 1 8 23 S E M exponent: excess 127 binaryMore information
Z80 Instruction Set. Z80 Assembly Language
75 Z80 Assembly Language The assembly language allows the user to write a program without concern for memory addresses or machine instruction formats. It uses symbolic addresses to identify memory locationsMore information
Programmer s Model = model of µc useful to view hardware during execution of software instructions
HC12/S12 Programmer s Model Programmer s Model = model of µc useful to view hardware during execution of software instructions Recall: General Microcontroller/Computer Architecture note: Control Unit &More information
1 Classical Universal Computer 3
Chapter 6: Machine Language and Assembler Christian Jacob 1 Classical Universal Computer 3 1.1 Von Neumann Architecture 3 1.2 CPU and RAM 5 1.3 Arithmetic Logical Unit (ALU) 6 1.4 Arithmetic Logical UnitMore information
MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmableMore information
Binary. ! You are probably familiar with decimal
Arithmetic operations in assembly language Prof. Gustavo Alonso Computer Science Department ETH Zürich email@example.com http://www.inf.ethz.ch/department/is/iks/ Binary! You are probably familiar withMore information
Feature of 8086 Microprocessor
8086 Microprocessor Introduction 8086 is the first 16 bit microprocessor which has 40 pin IC and operate on 5volt power supply. which has twenty address limes and works on two modes minimum mode and maximum.More information
Interrupts and the Timer Overflow Interrupts Huang Sections 6.1-6.4. What Happens When You Reset the HCS12?
Interrupts and the Timer Overflow Interrupts Huang Sections 6.1-6.4 o Using the Timer Overflow Flag to interrupt a delay o Introduction to Interrupts o How to generate an interrupt when the timer overflowsMore information
Microprocessor/Microcontroller. Introduction
Microprocessor/Microcontroller Introduction Microprocessor/Microcontroller microprocessor - also known as a CU or central processing unit - is a complete computation engine that is fabricated on a singleMore information
PROBLEMS (Cap. 4 - Istruzioni macchina)
98 CHAPTER 2 MACHINE INSTRUCTIONS AND PROGRAMS PROBLEMS (Cap. 4 - Istruzioni macchina) 2.1 Represent the decimal values 5, 2, 14, 10, 26, 19, 51, and 43, as signed, 7-bit numbers in the following binaryMore information
Call Subroutine (PC<15:0>) TOS, (W15)+2 W15 (PC<23:16>) TOS, Process data. Write to PC NOP NOP NOP NOP
Section 3. Descriptions CALL Call Subroutine Syntax: {label:} CALL lit23 CALL.S Operands: lit23 [0... 8388606] (PC)+4 PC, (PC) TOS, (W15)+2 W15 (PC) TOS, (W15)+2 W15 lit23 PC, NOP Register.More information
in the name of God the compassionate, the merciful notes on MACHINE ARCHITECTURE & LANGUAGE compiled by Jumong Chap. 9 Microprocessor Fundamentals A system designer should consider a microprocessor-basedMore information
Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2
Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy ofMore information
Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated CircuitMore information
Modbus RTU Communications RX/WX and MRX/MWX
15 Modbus RTU Communications RX/WX and MRX/MWX In This Chapter.... Network Slave Operation Network Master Operation: RX / WX Network Master Operation: DL06 MRX / MWX 5 2 D0 Modbus Network Slave OperationMore information
PART B QUESTIONS AND ANSWERS UNIT I 1. Explain the architecture of 8085 microprocessor? Logic pin out of 8085 microprocessor Address bus: unidirectional bus, used as high order bus Data bus: bi-directionalMore information
Freescale Semiconductor, I
nc. Reference Guide CU12RG/D Rev. 2, 11/2001 CU12 Reference Guide (for HCS12 and original M68HC12) 7 15 15 15 15 15 A 0 D X Y S C 7 B S X H I N Z V C 0 0 0 0 0 0 8-BIT ACCUMULATRS A AND B R 16-BIT DUBLEMore information
Instruction Set. Instruction Set Nomenclature: Status Register (SREG) Registers and Operands
Nomenclature: Status Register (SREG) SREG: Status register C: Carry flag in status register Z: Zero flag in status register N: Negative flag in status register V: Two s complement overflow indicator S:More information
The string of digits 101101 in the binary number system represents the quantity
Data Representation Section 3.1 Data Types Registers contain either data or control information Control information is a bit or group of bits used to specify the sequence of command signals needed forMore information
Oct: 50 8 = 6 (r = 2) 6 8 = 0 (r = 6) Writing the remainders in reverse order we get: (50) 10 = (62) 8
ECE Department Summer LECTURE #5: Number Systems EEL : Digital Logic and Computer Systems Based on lecture notes by Dr. Eric M. Schwartz Decimal Number System: -Our standard number system is base, alsoMore information
Building A RISC Microcontroller in an FPGA
Building A RISC Microcontroller in an FPGA Name : Yap Zi He Course : 4 SEL Supervisor : PM Muhammad Mun im Ahmad Zabidi Introduction Reduce Instruction Set Computer (RISC) is a new trend on computer design.More information
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 1. Introduction 6.004 Computation Structures β Documentation This handout isMore information
Computer Organization and Architecture
Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goalMore information
CS 16: Assembly Language Programming for the IBM PC and Compatibles
CS 16: Assembly Language Programming for the IBM PC and Compatibles First, a little about you Your name Have you ever worked with/used/played with assembly language? If so, talk about it Why are you takingMore information
Section 44. CPU with Extended Data Space (EDS)
Section 44. CPU with Extended Data Space (EDS) HIGHLIGHTS This section of the manual contains the following topics: 44.1 Introduction... 44-2 44.2 Programmer s Model... 44-5 44.3 Software Stack Pointer...More information
Traditional IBM Mainframe Operating Principles
C H A P T E R 1 7 Traditional IBM Mainframe Operating Principles WHEN YOU FINISH READING THIS CHAPTER YOU SHOULD BE ABLE TO: Distinguish between an absolute address and a relative address. Briefly explainMore information
Comp 255Q - 1M: Computer Organization Lab #3 - Machine Language Programs for the PDP-8
Comp 255Q - 1M: Computer Organization Lab #3 - Machine Language Programs for the PDP-8 January 22, 2013 Name: Grade /10 Introduction: In this lab you will write, test, and execute a number of simple PDP-8More information
Divide: Paper & Pencil. Computer Architecture ALU Design : Division and Floating Point. Divide algorithm. DIVIDE HARDWARE Version 1
Divide: Paper & Pencil Computer Architecture ALU Design : Division and Floating Point 1001 Quotient Divisor 1000 1001010 Dividend 1000 10 101 1010 1000 10 (or Modulo result) See how big a number can beMore information
Typy danych. Data types: Literals:
Lab 10 MIPS32 Typy danych Data types: Instructions are all 32 bits byte(8 bits), halfword (2 bytes), word (4 bytes) a character requires 1 byte of storage an integer requires 1 word (4 bytes) of storageMore information
LABORATORY MANUAL EE0310 MICROPROCESSOR & MICROCONTROLLER LAB DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING FACULTY OF ENGINEERING & TECHNOLOGY SRM UNIVERSITY, Kattankulathur 603 203 1 LIST OF EXEPRIMENTSMore information
Chapter 7D The Java Virtual Machine
This sub chapter discusses another architecture, that of the JVM (Java Virtual Machine). In general, a VM (Virtual Machine) is a hypothetical machine (implemented in either hardware or software) that directlyMore information
==== ==== ================================================================ DR 6502 AER 201S Engineering Design 6502 Execution Simulator ================================================================More information
8085 Assembly Language Programs & Explanations
8085 Assembly Language Programs & Explanations 1. Statement: Store the data byte 32H into memory location 4000H. Program 1: MVI A, 32H STA 4000H : Store 32H in the accumulator : Copy accumulator contentsMore information
Local workspace of a subroutine: Recursion and recursive subroutines:
Local workspace of a subroutine: A number of temporary memory locations required by the subroutine for temporary private variables used in addition to available data registers. Recursion and recursiveMore information
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA) * Instruction set architecture of a machine fills the semantic gap between the user and the machine. * ISA serves as the starting point for the design of a new machineMore information
Assembly Language Programming: Subroutines
Assembly Language Programming: Subroutines by Alex Milenkovich, email@example.com Objectives: Introduce subroutines, subroutine nesting, processor stack, and passing the parameters to subroutines.More information
CPU Organization and Assembly Language
COS 140 Foundations of Computer Science School of Computing and Information Science University of Maine October 2, 2015 Outline 1 2 3 4 5 6 7 8 Homework and announcements Reading: Chapter 12 Homework:More information
2 Programs: Instructions in the Computer
2 2 Programs: Instructions in the Computer Figure 2. illustrates the first few processing steps taken as a simple CPU executes a program. The CPU for this example is assumed to have a program counter (PC),More information
Flash Microcontroller. Architectural Overview. Features. Block Diagram. Figure 1. Block Diagram of the AT89C core
Features 8-Bit CPU Optimized for Control Applications Extensive Boolean Processing Capabilities (Single-Bit Logic) On-Chip Flash Program Memory On-Chip Data RAM Bidirectional and Individually AddressableMore information
Z80 Microprocessors Z80 CPU. User Manual UM008006-0714. Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com
Z80 Microprocessors Z80 CPU UM008006-0714 Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTSMore information
University of Toronto Faculty of Applied Science and Engineering
Print : First Name :............................. Last Name :............................. Student Number:............................................... University of Toronto Faculty of Applied ScienceMore information
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,More information
Multiplication and Division Instructions
Multiplication and Division Instructions MUL Instruction IMUL Instruction DIV Instruction Signed Integer Division Implementing Arithmetic Expressions Irvine, Kip R. Assembly Language for Intel-Based Computers,More information
Instruction Set Architecture. or How to talk to computers if you aren t in Star Trek
Instruction Set Architecture or How to talk to computers if you aren t in Star Trek The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set ArchitectureMore information
Overview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX
Overview CISC Developments Over Twenty Years Classic CISC design: Digital VAX VAXÕs RISC successor: PRISM/Alpha IntelÕs ubiquitous 80x86 architecture Ð 8086 through the Pentium Pro (P6) RJS 2/3/97 PhilosophyMore information
Basic Concepts of Microprocessors
MICROPROCESSOR 8085 Reference Book: Ramesh S. Goankar, Microprocessor Architecture, Programming and Applications with 8085, 5 th Edition, Prentice Hall Week 1 Basic Concept and Ideas about Microprocessor.More information
C What Happens INTRODUCTION PIC MICROCONTROLLER PRODUCT OVERVIEW SELECTING A DEVICE FOR EXPERIMENTS PIC16F818
C What Happens INTRODUCTION PIC MICROCONTROLLER PRODUCT OVERVIEW SELECTING A DEVICE FOR EXPERIMENTS PIC16F818 Pins and functions Package Clock oscillator Reset Ports Special Features PIC microcontrollerMore information
Instruction Set Design
Instruction Set Design Instruction Set Architecture: to what purpose? ISA provides the level of abstraction between the software and the hardware One of the most important abstraction in CS It s narrow,More information
Informatica e Sistemi in Tempo Reale
Informatica e Sistemi in Tempo Reale Introduction to C programming Giuseppe Lipari http://retis.sssup.it/~lipari Scuola Superiore Sant Anna Pisa October 25, 2010 G. Lipari (Scuola Superiore Sant Anna)More information
Programmable Logic Controllers
Programmable Logic Controllers Data Handling and Program Control Flow Instructions Dr. D. J. Jackson Lecture 8-1 Move (MOV) This output instruction moves the source value to the destination location. AsMore information
A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc
Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into accMore information
CHAPTER 7: The CPU and Memory
CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slidesMore information
Chapter 5, The Instruction Set Architecture Level
Chapter 5, The Instruction Set Architecture Level 5.1 Overview Of The ISA Level 5.2 Data Types 5.3 Instruction Formats 5.4 Addressing 5.5 Instruction Types 5.6 Flow Of Control 5.7 A Detailed Example: TheMore information
Quiz for Chapter 3 Arithmetic for Computers 3.10
Date: Quiz for Chapter 3 Arithmetic for Computers 3.10 Not all questions are of equal difficulty. Please review the entire quiz first and then budget your time carefully. Name: Course: Solutions in REDMore information
COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 1 - INTRODUCTION JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ Unit 1.MaNoTaS 1 Definitions (I) Description A computer is: AMore information
Lecture 8: Binary Multiplication & Division
Lecture 8: Binary Multiplication & Division Today s topics: Addition/Subtraction Multiplication Division Reminder: get started early on assignment 3 1 2 s Complement Signed Numbers two = 0 ten 0001 twoMore information
Computer Science 281 Binary and Hexadecimal Review
Computer Science 281 Binary and Hexadecimal Review 1 The Binary Number System Computers store everything, both instructions and data, by using many, many transistors, each of which can be in one of twoMore information
Lab 4 Large Number Arithmetic. ECE 375 Oregon State University Page 29
Lab 4 Large Number Arithmetic ECE 375 Oregon State University Page 29 Objectives Understand and use arithmetic and ALU operations Manipulate and handle large numbers Create and handle functions and subroutinesMore information
AN617. Fixed Point Routines FIXED POINT ARITHMETIC INTRODUCTION. Thi d t t d ith F M k 4 0 4. Design Consultant
Thi d t t d ith F M k 4 0 4 Fixed Point Routines AN617 Author: INTRODUCTION Frank J. Testa Design Consultant This application note presents an implementation of the following fixed point math routinesMore information
RISC PROCESSOR ISA FOR EECS 427 PROCESSOR ImmHi/ ImmLo/ OP Code Rdest OP Code Ext Rsrc Mnemonic Operands 15-12 11-8 7-4 3-0 Notes (* is Baseline) ADD Rsrc, Rdest 0000 Rdest 0101 Rsrc * ADDI Imm, RdestMore information
Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360
1 Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 Computer Science and Artificial Intelligence Laboratory M.I.T. Based on the material prepared by and Krste AsanovicMore information
Instruction Set Architecture
Instruction Set Architecture Consider x := y+z. (x, y, z are memory variables) 1-address instructions 2-address instructions LOAD y (r :=y) ADD y,z (y := y+z) ADD z (r:=r+z) MOVE x,y (x := y) STORE x (x:=r)More information
EE 261 Introduction to Logic Circuits. Module #2 Number Systems
EE 261 Introduction to Logic Circuits Module #2 Number Systems Topics A. Number System Formation B. Base Conversions C. Binary Arithmetic D. Signed Numbers E. Signed Arithmetic F. Binary Codes TextbookMore information
MAPware-7000 Ladder Logic Guide
APware-7000 Ladder Logic Guide aple ystems Inc. 808 134 th treet, uite 120 Everett, A 98204-7333 Phone: (425) 745-3229 Email: email@example.com eb: www.maplesystems.com 2011 aple ystems Inc. All rightsMore information
68HC11 Programmer s Reference Manual
8HC11 Programmer s Reference Manual Phillip Musumeci firstname.lastname@example.com November 1999 Version 1. Credits Engineer proofreading: Dr. Barbara La Scala; Cross Assembler for 8HC11: Motorola; University ofMore information
PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 TUTORIAL OUTCOME 2 Part 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 TUTORIAL OUTCOME 2 Part 1 This work covers part of outcome 2 of the Edexcel standard module. The material isMore information
150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs anMore information
Atmel AVR 8-bit Instruction Set
Atmel AVR 8-bit Instruction Set Instruction Set Nomenclature Status Register (SREG) SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two s complement overflow indicator S: N V, ForMore information
Chapter 6 Digital Arithmetic: Operations & Circuits
Chapter 6 Digital Arithmetic: Operations & Circuits Chapter 6 Objectives Selected areas covered in this chapter: Binary addition, subtraction, multiplication, division. Differences between binary additionMore information
Central Processing Unit (CPU)
Central Processing Unit (CPU) CPU is the heart and brain It interprets and executes machine level instructions Controls data transfer from/to Main Memory (MM) and CPU Detects any errors In the followingMore information
EC 362 Problem Set #2
EC 362 Problem Set #2 1) Using Single Precision IEEE 754, what is FF28 0000? 2) Suppose the fraction enhanced of a processor is 40% and the speedup of the enhancement was tenfold. What is the overall speedup?More information
Number Systems, Base Conversions, and Computer Data Representation
, Base Conversions, and Computer Data Representation Decimal and Binary Numbers When we write decimal (base 10) numbers, we use a positional notation system. Each digit is multiplied by an appropriateMore information
A Utility for Programming Single FLASH Array HCS12 MCUs, with Minimum RAM Overhead
Freescale Semiconductor Application Note AN2720 Rev. 2, 04/2008 A Utility for Programming Single FLASH Array HCS12 MCUs, with Minimum RAM Overhead By Jim Williams 8/16-Bit Applications Engineering Austin,More information
CHAPTER 2 MACHINE INSTRUCTIONS AND PROGRAMS CHAPTER OBJECTIVES In this chapter you will learn about: Machine instructions and program execution, including branching and subroutine call and return operationsMore information
8-bit RISC Microcontroller. Application Note. AVR236: CRC Check of Program Memory
AVR236: CRC Check of Program Memory Features CRC Generation and Checking of Program Memory Supports all AVR Controllers with LPM Instruction Compact Code Size, 44 Words (CRC Generation and CRC Checking)More information
CPU Organisation and Operation
CPU Organisation and Operation The Fetch-Execute Cycle The operation of the CPU 1 is usually described in terms of the Fetch-Execute cycle. 2 Fetch-Execute Cycle Fetch the Instruction Increment the ProgramMore information
Instruction Set. Instruction Set Nomenclature. Status Register (SREG) Registers and Operands
Instruction Set Nomenclature Status Register (SREG) SREG: Status register C: Carry flag Z: Zero flag N: Negative flag V: Two s complement overflow indicator S: N V, For signed tests H: Half Carry flagMore information
An Overview of Stack Architecture and the PSC 1000 Microprocessor
An Overview of Stack Architecture and the PSC 1000 Microprocessor Introduction A stack is an important data handling structure used in computing. Specifically, a stack is a dynamic set of elements in whichMore information
Goals. Unary Numbers. Decimal Numbers. 3,148 is. 1000 s 100 s 10 s 1 s. Number Bases 1/12/2009. COMP370 Intro to Computer Architecture 1
Number Bases //9 Goals Numbers Understand binary and hexadecimal numbers Be able to convert between number bases Understand binary fractions COMP37 Introduction to Computer Architecture Unary Numbers DecimalMore information
X86-64 Architecture Guide
X86-64 Architecture Guide For the code-generation project, we shall expose you to a simplified version of the x86-64 platform. Example Consider the following Decaf program: class Program { int foo(intMore information
The University of Nottingham
The University of Nottingham School of Computer Science A Level 1 Module, Autumn Semester 2007-2008 Computer Systems Architecture (G51CSA) Time Allowed: TWO Hours Candidates must NOT start writing theirMore information
MOS T ic H N O LO O Y, INC. V A LLEY FORGE CORPORATE CENTER (216) 666 7950 950 RITTENHOUSE ROAD, NORRISTOWN, PA 19401
PR ELIM IN A R Y DATA SHEET MOS T ic H N O LO O Y, INC. V A LLEY FORGE CORPORATE CENTER (216) 666 7950 950 RITTENHOUSE ROAD, NORRISTOWN, PA 19401 M A Y, 1976 M C S6 5 0 0 M IC R O P R O C E S S O R S TheMore information
AN2183. Using FLASH as EEPROM on the MC68HC908GP32. Introduction. Semiconductor Products Sector Application Note
Order this document by /D Semiconductor Products Sector Application Note Using FLASH as EEPROM on the MC68HC908GP32 By Derrick H.J. Klotz Field Applications Engineer Toronto, Canada Introduction This applicationMore information


text:
No fewer than eight persons were killed on Monday in Talata-Mafara community in Zamfara following violence that erupted over alleged blasphemy by a student of Abdu Gusau Polytechnic, Talata-Mafara.
The deceased were said to have all been killed when an angry mob set fire on the house of a man who tried to rescue the student.
Nigerians some of who blamed the killings on the state governor have frowned on the incident.
READ: FLASHBACK: We 'Will Deal Decisively' With Qur'an Desecrators – Gov.Yari
See tweets below:
Make Money Online in Nigeria... Click HERE To Start Now!

subset: commoncrawl


text:
16900 N. 88th Drive
Directions Peoria, AZ 85382
Field boasts a state-of-the-art LED ribbon display which runs 1199 feet - the
largest of its kind in Major League Baseball. From one innovator in its field
to another, Audi is proud to partner with the Arizona Diamondbacks this season.
Audi Club
The D-backs
exclusive Audi Club allows fans to enjoy a luxurious club experience without
ever leaving the action. Located just off the main entrance of the Insight
Diamond Level, adjacent to the Chase Field parking garage, the Audi Club is
accessible to guests with a suite ticket or premium lower level seating.
Overlooking the 3rd base side, the Audi Club offers an unparalleled view of the
game action with floor to ceiling windows and outdoor patio seating. Our guests
can also enjoy eight 60" flat screen televisions and a private bar, making it
an ideal gathering place for D-backs fans.
Audi quattro
Located behind
home plate, the Audi quattro Lounge is an exclusive, upscale dining and bar
experience. Because it is on the Field Level of Chase Field, it is only
accessible to those guests with a ticket in the Clubhouse Box or 1st/3rd Base
Box sections. The Audi quattro Lounge offers fans a chef table with a variety
of items to choose from. The Audi quattro Lounge menu varies each homestand and also
includes an Ala Carte menu with items ranging from sandwiches, wraps to gourmet salads and pastas.
16900 N. 88th Drive
Directions Peoria, AZ 85382
We were unable to locate the page you requested. Please take a look at our most popular pages, listed below. If you still cannot find what you are looking for, feel free to contact us directly.' }


text:
I like comedy (I run a couple of comedy nights), I like singing (I help run a choir), I like technology (it's my job). And apparently I really like parentheses (({{[[]]}}))
I'm not looking to be monogamous right now. That doesn't mean I just want to bang loads of random people though, I want to get to know you. And also bang. Bang is a horrible word.
I am happy and sarcastic and I'm looking for people to be happy and sarcastic with. I find it really attractive when someone is passionate about their hobby, job or interests. Do you know about a thing? Tell me about that thing.
***Message me if you've got something to say other than, "Hi" or similar. If you could copy and paste your message to more than one person, then you're doing this site wrong.***
Doing that awkward thing where I hold the door open for someone, but they're too far away, so then I let go of the door, but by that time they've made it to the door, so essentially I end up slamming the door in their face. It's not the superpower I'd hoped for, if I'm honest.
Nope. No idea. Probably that I'm a stylish, tall, fat woman. I'm often wearing red lipstick, so maybe it's that. Or my necklace that says 'why?'. It's a band, not a philosophical question, by the way.
Books... Orwell, F. Scott Fitzgerald, Iain Banks, Douglas Coupland, Chuck Palahniuk, Chuck Klosterman, Augusten Burroughs, Jonathan Franzen.
Graphic novels: Saga, Bitch Planet, Sex Criminals
Food: I'm a vegetarian, but not one who really cares what anyone else eats.
If your friends have nicknamed you Sasquatch/Viking, or you look like you could be in Game Of Thrones.
If you are able to talk about something you love. Quantum physics, otters, cooking, knitting, whatever.
Basically if you're a good person and you've got something to say other than, "Hi" or similar. Like I said earlier, if you could copy and paste your message to more than one person, then you're doing this site wrong.


text:
"The ICL is not recognised by the International Cricket Council or its member boards so there is no question of our players going to play there," Ashraf told reporters.
Sources close to some of the players said Shoaib Akhtar, Shahid Afridi and Shoaib Malik had received offers days after former captain Inzamam-ul-Haq confirmed he had been approached by the organisers.
The ICL has signed former West Indies captain Brian Lara for the Twenty20 series to be played over 45 days starting in October.
Ashraf said any player who decided to play in the league would not be selected again for Pakistan.
"We have clauses in our central contracts clearly outlining the board decides where the players can play," he said.
"Even where former players are concerned if they are not holding any position with the board we can't stop them. But those who are working for us will not be given permission to play in the Indian league."
India's cricket board has also refused to endorse the league.


text:
Acon Digital Media Releases AudioLava – Vinyl Restoration Software
Acon Digital Media has released AudioLava, a utility to prepare vinyl and cassette recordings for digital transfer. Acon Digital Media claims AudioLava can automatically remove noise such as tape hiss or clicks and crackle on LP records and contains filters and effects that are otherwise only found in expensive audio editing software for making optimum recordings.
Even users new to audio editing can easily and in short time record and clean up old recordings. The user friendly Cleaning Wizard helps to find the best way to bring old recordings back to life and guides the user through all the steps from recording and
track splitting to restoration and CD burning.
The digital emulation of phono preamplifiers makes it possible to connect ordinary record players directly to the sound card input.
AudioLava automatically splits recordings into separate tracks, which can also be edited manually. A large set of effects and filters are included, ranging from reverb and equalizer to synthesis of missing high frequency content (treble). Plug-ins in the
DirectX or VST format are supported. The real time processing of the filters and effects simplifies the fine tuning of the filters and enhances the workflow. The restored recordings can be burned directly on CDs or saved as audio files on the computer in a
variety of formats, including WAV and MP3.
Acon Digital Media's AudioLava is available for $24.90 via the company's website. A free 30-day trial is also available. More information on Acon Digital Media AudioLava.


text:
Citrix Desktop Virtualization and Mobility
" Citrix has been around for a long time. Many of us first knew them with their MetaFrame product which was an add-on to Terminal Server. Back then Citrix was a one-product company (and we just called the servers, ""Citrix servers."") But now.. wow! MetaFrame has evolved to Presentation Server which evolved to XenApp. After a decade of dominating the server-based computing industry, Citrix entered the desktop virtualization space with the first products that ultimately evolved into XenDesktop. And let's not forget server virtualization! In 2007 Citrix bought XenSource which led to the creation of Citrix XenServer. But it didn't end there. In early 2009 Citrix announced ""Project Independence,"" a bare-metal client hypervisor that's now called Citrix XenClient. So clearly now Citrix has moved beyond being a one-product company. They have NetScalers and Branch Repeaters and Citrix Receivers and HDX and GoToMyPC... it's crazy now! And we've been here all along, writing about Citrix since 2001. Here's a list of the hundreds and hundreds of stories we've written about Citrix -- both the company and their products. "
Articles : Citrix Desktop Virtualization and Mobility
Citrix on Google Cloud, Glass returns, & Group Policy via MDM - Friday Notebook for July 21
Also: GeekOut 365, dinCloud, Windows 10 S, Google Play Protect, Check Point, Jide, and why forced iOS updates and a good thing. Continue Reading
Friday Notebook, July 14, 2017: Citrix CEO shuffle, Skycure and RES acquisitions, Windows 10 SPLA
Also: Fireglass, Microsoft 365, RDS modern infrastructure, Parallels RAS 16, FSLogix, and more on mobile threat defense. Continue Reading
Kirill Tatarinov out as Citrix CEO, CFO David Henshall takes over as CEO. Here's our full analysis:
Kirill Tatarinov and Citrix have parted ways after just 18 months as CEO. With CFO David Henshall taking the helm, here's our take on the situation. Continue Reading
Podcasts : Citrix Desktop Virtualization and Mobility
BrianMadden.com Podcast #128: Citrix Synergy 2017
Gabe and Jack sit down after the show to hash out their opinions. Continue Reading
BrianMadden.com Podcast #126: Dane Young joins us to talk about Citrix Summit
Citrix Summit was last week, and between the acquisition of Unidesk, the future of Windows management, and Citrix's relationship with Microsoft, there was a lot to talk about. Continue Reading
BrianMadden.com Podcast #124: Gabe and Jack talk VMware, Citrix, Identity, and Macs
Also: Windows 10 Mobile, BlackBerry, what's going on around the site, and our upcoming events. Continue Reading
Videos : Citrix Desktop Virtualization and Mobility
Thoughts on Citrix's Linux VDA, plus a video demo from Citrix Synergy 2015
One of the more surprising things in a relatively unsurprising Citrix Synergy was the round of applause created by the announcement of the Linux VDA Tech Preview. I think it's great, but it's not the kind of announcement you'd think would garner much more than a murmur, let alone get a larger reaction from the audience than the iBand's rendition of "Hey Ya!
Citrix's Chris Fleck demoing their "Workspace Hub" Android-on-a-stick prototype
One of the things that got a lot of buzz at Citrix Synergy a few weeks ago was something called "Citrix Workspace Hub," a prototype Android-on-a-stick you can use to convert any HDMI or VGA display to a full screen extension for your Android or iOS device. You can plug this thing into a display and then wirelessly connect to it via your mobile device.
Panzura explains their Global File System and how they can help you deploy XenDesktop from AWS
I stopped by the Panzura booth at Citrix Synergy to learn more about what they mean when they say "Deploy XenDesktop completely in the cloud." Prior to the show I'd heard from several people that I needed to check them out, and when Panzura was announced as a finalist in the Best New Technology category of the Best of Synergy awards, I had to check them out.


text:
Online video-based learning platform
Budget min $5000 USD
This project is for a small business that offers online video courses to paying customers. We are looking to upgrade/revamp the entire system from the ground up.
Currently, users log in and click on courses sorted by topic. They can then click on the chapter they'd like to start with and begin watching the video. This largely covers the extent of the existing end-user functionality.
We would like to re-design the system in several ways, implementing many features of other excellent learning platforms such as Khan Academy ([url removed, login to view]). Key elements include:
1. More social network-oriented user profiles (profile pictures, contact info, file upload, social network integration, etc.)
2. More streamlined course management (videos progress along a "track", with very easy previous/next navigation)
3. Q&A/help section for each video (view, ask, and answer questions directly underneath a video that's playing)
4. Technical updates (modern HTML5 player integration, reliable DRM-supported video delivery)
*Note that point 4 above is not expected to be developed from scratch--instead, we would like a professional recommendation regarding the best solution (e.g., play videos through JW Player, host them on Amazon Web Services/deliver them via ...)
A dedicated backend is also necessary so administrators can easily:
- manage all users (add users by batch/CSV, sort users by join date, add/remove video course access, view usage logs, email/message users)
- manage actual videos (manage courses, packages, "tracks")
Note that our current video backend system is also integrated with the actual order/e-commerce process, so when a visitor places an order on our website for a specific course, she receives an email with her login info and can begin viewing courses immediately. All incoming orders are tracked/recorded by this same backend. Ideally this e-commerce integration would be retained in the new revamped system, though this may be discussed further.
Our ideal candidate is a firm/team with substantial experience building similar platforms who communicates well and can share a clear vision of what we're looking for. We are looking specifically for a team who knows the industry and is willing to help build a vital part of a business that extends beyond the lifetime of this project. We are not seeking someone who can only offer proficient coding skills.
An added bonus would be if you are open to working on smaller, related projects in the near-term as well.


text:
Lookbook: Romper9:00 AM
So, I know when I last mentioned rompers I said I wasn't going to wear heels with them but I found this little romper that wasn't too short and decided that heels would be acceptable to be worn with it.
Romper: Forever 21
Shoes: Cynthia Vincent (from Gilt)
I woke up early one Saturday morning and checked my e-mail to see a Gilt sale. I was like "What? Gilt sale on a Saturday?" and lucky for me it was a shoe sale! I got 3 pairs of Cynthia Vincent shoes and these were one of them. The platform in front gives just the right amount of height and I love the pleats in front.
Each photo session usually ends with a ridiculously goofy picture of me as my husband always likes to say at least one comment to get this reaction.
p.s. if you are looking for a Gilt invite, click here!
52 comments
LOVE THAT ROMPER!!!!!!!!!ReplyDelete
i love this look. that romper doesn't look like something from Forever21. what a great find!ReplyDelete
you are quickly becoming one of my favourite stylish ladies...and that's a very elite & small circle to enter if i do say so myself...ReplyDelete
it includes halle berry, cameron diaz and jennifer lopez.
You look lovely, darling ~ better than Blake! The romper and pumps are both divine!ReplyDelete
Love the print.ReplyDelete
Love it! The print, the shoes, you look stinkin' adorable!ReplyDelete
Ohhhhhhhh, those shoes are delicious!!ReplyDelete
I gotta admit, I'm not a fan of the romper look. But you may have pulled me over because you certainly pull it off!! :)ReplyDelete
cute romper! i'd totally wear a jacket or cardi over it if it weren't for the heat right now.ReplyDelete
you look adorable.....the whole outfit is so so cute...n the romper is from forever 21, boy thats one great find.ReplyDelete
you look so adorable in this! love it!!! :)ReplyDelete
Wow that is a great F21 find. I think I'm going to stop by F21 today to see if I can find any rompers that don't make me look like an oompa loompa.ReplyDelete
This romper looks SO CUTE on you! Omg, you inspire me to grab a few now! I love the print on it too. I worry that I'll look squat in it, but you look great. And it's from F21? Well I know where I'm going this weekend!ReplyDelete
love the outfit! rompers are one of my favorite summer time duds...right up there with sundresses!ReplyDelete
omg i love that romper! infact i have it in my closet too! ive been wearing it with flats & flip flops, but now im going to try it with heels.ReplyDelete
WOW. ..i mean WOW ...FOREVER 21 rocked this so hard! You look amazing ...and it totally works with heels. LOVE IT....happy weekend!ReplyDelete
I think rompers are cute, just not on me. Maybe I haven't found one that I think works on my body. Your entire outfit looks cute!ReplyDelete
I wish my husband would take pictures for me without any grunts. :)
omg!! uber cute! i love jumpers/rompers/onsies..whatever they're called.ReplyDelete
for my wedding, my girls and i got ready in rompers...from F21! woot! =)
Oh my! That is so adorable I just rocked a jumper last week and got all stared down. lolReplyDelete
I must definitely hit F21 and grab a pair!!!
Totally inspirational!
Tiff WOW! I am really inspired with this one lady! I'm a shortie too and I was afraid a romper + flats would make me look like a blob, so seeing it with heels is AMAZING! And forever 21?! If I only wear it once around the house, it's paid for itself.ReplyDelete
I'm totally going tomorrow!!!
The last pics are always my fave...so adorable! :)
so adorable...you totally made the romper look work for you!!! One of the benefits of being short like us is that we can wear things like this and not look the least bit tart-y:)ReplyDelete
You have inspired me to go romper shopping this weekend!
totally adorable. i am still trying to find the romper for me...ReplyDelete
This romper looks so comfortable - and you look adorable!!!ReplyDelete
I am in LOVE with that romper!! I think I'm going to the forever 21 website right now....ReplyDelete
I love it!! I'm still searching for my perfect romper for summer :)ReplyDelete
i give the romper an A PLUS!ReplyDelete
you are TOO cute - love the romper!ReplyDelete
ADORABELLA!!! I love this look. you can seriously wear anything. I would look like a moron in a romper and you look FAB. I love it. And those shoes are to DIE for. loves!ReplyDelete
LOVE THE ROMPER!!! This one is totally amazing & you took it to the next level...dog, you in the doghouse (I hope you watch American Idol or you might take offense to that!)ReplyDelete
Seriously, awesome outfit, you worked it out!!
oh.. great ! :)) you look really good :))ReplyDelete
I've always been a bit apprehensive about rompers but this look book is fantastic! Perhaps I'll have to give rompers a second chance.ReplyDelete
Beautiful rompers,u look great! I find ur blog very informative n interesting, truly enjoy!ReplyDelete
You look divine, darling! So perfect! Have a great weekend,ReplyDelete
Definitely a fashion DO! You look positively adorable as usual, and that romper looks so stylish without being overly trendy. And don't you love Gilt? It's my kryptonite! I'm still celebrating over a pair of snakeskin loeffler randall flats that i got for like 60% off!ReplyDelete
what a gorgeous print, so chic!!ReplyDelete
you look so adorable! i love it. I could never pull off a romper ...its just me! but you look absolutely fab. (alllmost making me want to go out and try it) thanks girl! xoReplyDelete
This comment has been removed by the author.ReplyDelete
Awesome romper and heels!ReplyDelete
I love your outfit! I would so wear that, it's gorge!ReplyDelete
can I borrow your legs? no? okay, I'd settle for those Cynthia shoes! Gorgeous :-)ReplyDelete
you are so beautiful (this is my first visit!) and you wear this look so well. :)ReplyDelete
This is my first visit to your blog and now I'm a follower! I love your style and I'm a Gilt lover as well :)ReplyDelete
such a cute look! i love the heels - and the romper is great. i bought one and havent found the right way to wear it yet, this is good inspiration :)ReplyDelete
looove the romper! looks great on you!!ReplyDelete
i love Ur romber/jumpsuits...so fashionable!ReplyDelete
Hi :)ReplyDelete
You look absolutely gorge! You can pull it off :D
cute romper..looks cuteReplyDelete
this romper is SO cute! Can't believe its from Forever!ReplyDelete
you look so cute! love the addition of the cardigan =)ReplyDelete
Thanks for the Gilt invite! I'm excited to check it out!!ReplyDelete
omg i love the outfit!!ReplyDelete
Have that same romper!ReplyDelete


text:
ALL >> Fashion-Costume >> View Article
And Talentsdubai Modelingmodel Managementdubaimanagementfashion Show
Total Articles: 153
FLC Models is looking for a fresh male universal look models for an upcoming Photo shoot in Kuwait this July. (The models will be travelling in the morning and coming back same day after the show). FLC Events can organize all your event requirements, whether it is booking an act or creating an entire show extravaganza for you. FLC Marketing provides you all your roadshow, tradeshow and marketing promotion requirements, from concept to execution.FLC Models, an UAE based Talent Agency in association with Lutece Holding/Elite Middle East, the ELITE MODEL LOOK 2013's licensee for United Arab Emirates and Qatar, are pleased to announce their collaboration in the organization of the world largest and renowned model search "ELITE MODEL LOOKâ€.A Worldwide Contest
Created in 1983, the ELITE MODEL LOOK competition is organized in more than 60 countries to discover the most promising young talents in modeling from among the winners of the national competitions organized in each of the participating countries.
ELITE MODEL LOOK is the most famous model search contest offering the opportunity to upcoming models from all nationalities to enter the world of fashion, to become a model and to begin a modeling career in the best conditions, in one of Elite Model agencies.
Organizers, especially selected by Elite Group, handle the organization of more than 800 live castings events throughout the world with the participation of more than 370,000 contestants wishing to enter the national contests. The winners of every national final then go to the international final where they will get the opportunity to represent their country along with other national winners. A great first step in the Middle East Region
For the 30th consecutive year, Elite is organizing the most prestigious modeling contest in the world offering thousands of girls and boys between the age of 14 and 22, the opportunity to achieve their dream and to follow in the footsteps of top models such as Cindy Crawford, Stephanie Seymour, Gisele Bundchen, Sigrid Agren and Constance Jablonski.
In 2013 and for the first time in the Middle East region, FLC Models with Elite Middle East bring together their expertise and know-how to organize the ELITE MODEL LOOK UAE & QATAR.
Talking to the press, Adriana USVAT, Managing Partner, FLC MODELS said, "The World -Renowned Elite Model Look competition has offered many young girls a chance to be discovered and to literally take over the fashion world. We are proud to bring the first Elite Model Look to UAE & Qatar and offer an international platform to the amazing talents in the region. We would love to see the next World Winner coming from our region. Let's make history together!â€
Ganesh IYER, Managing Partner, FLC MODELS also added that "Our region has seen many of world's biggest & highest, we are now proud to bring the 'The World's BEST Model Look Contest' to the region. Exciting days are ahead for the fashion industry in 2013â€. FLC\Models and Talents provide you with a range of local and according to your needs Film, TVC Fashion Shows and more. You can view them category wise - ageethnicity capabilities to bring you the right talent specifications. With a wealth of experience in above clients strives to be the partner of choice for all fashion related , photographic and communication
Fashion/Costume Articles1. Designer Purses For Women: Models To Look Out For
Author: Suhana Scott
2. Wear T Shirt For A Classy And Sassy Look
Author: Denesh Yadav
3. More Than A Century Old Legacy!
Author: Bespocut
4. Beach Party Ideas From Beatbox Beverages - The Coolest Party Planners
Author: Brad
5. Guide To Select Perfect Swimwear In Uk
Author: uswimwear
6. The Changing Face Of Indian Fashion Industry
Author: Amaya Sharma
7. Your Love For Animals Now Revealed Through Trendy Jewelry
Author: Hugo McCoy
8. Versace, Roberto Cavalli & Missoni - A Luxury Fashion Brands For Men & Women Clothing In Delhi India
Author: Infinite Luxury
9. 3 Engagement Rings You Haven't Considered
Author: David Smith
10. Top 10 Bridal Lehenga Trends For 2017-2018
Author: Sonali Lad
11. Beach Holiday Checklist
Author: Brad
12. Beach Vacation Must- Haves For Men
Author: Brad
13. Made In Usa Jeans – Right Compliment To Your Look
Author: Jeff Harmon
14. Process Of Making Cotton Clothes
Author: Cotton Source
15. Are Briefs Ideal For Summer?
Author: Andrew Joel


text:
In the article by Doctorow he attempts to show how complex our current copyright problems are. He talks about far wages for artist paid by government and how this would never work. With this I agree because as much as I would love to be guaranteed an income to many people would jump at this opportunity to quite their jobs and write music and paint.
He also talked about the "Berne Convention" and how the nations that used this where breaking their own laws by allowing blanketed licensing for music to radio stations, karaoke bars, and hairdressers. Then Doctorow went on to talk about the old trying to stifle the new from TV going after the cable companies, then the cable companies going after the VCR and how they always seem to use the defense of no one will buy what they can get for free.
Then he talked about the industries of fashion and architecture having very few copyright protections yet they still seem to be attracting new people into the fields. This to me means that a lack of copyright protection does not stop creative people for creating.
Doctorow suggest the possibility of charging an annual fee in exchange for unlimited downloads when purchasing a MP3 player and rationing out the money to the artists by how many songs of their were downloaded that year. Though I am glad to see that someone is trying to think of way to fix the problem I do not believe this is a viable solution. The reason that I don't like this idea is because the money will go through the labels before getting to the artist and who to say that it will ever fairly reach the hands of the artists.
In conclusion I think Doctorow is trying to give possible solutions to an impossible problem. The biggest problem is that there are just no good answers. Yes artist should have the right to protect the art and have an incentive to continue creating new art but they shouldn't have the right to get in the way of others that are attempting to do the same. This is the problem. Both sides are right and wrong.
It is just to complicated a problem to fix without starting over and rewrite the laws. But this leads to another set of problems. As long as we have a system that is set up where the ones with the money and power are the ones who get to right the laws, we the people will never get the true freedom of expression we deserve.


text:
This is another presidential election year in the United States, and plenty of expats here have opinions on who should win.
The choice is between the incumbent, Barack Obama, and the Republican hopeful Mitt Romney, although a reader wrote Wednesday to say that Ron Paul still has a chance. There also is Gary Johnson, the Libertarian candidate.
The main force behind the First Amendment to the U.S. Constitution is political speech. Readers are encouraged to express their views, tightly and clearly. A.M. Costa Rica is not a discussion list, so readers have just one chance to express themselves on this topic.
Discussion is good. Personal attacks are bad. Readers should try to focus on facts to support their argument.
The election is Nov.6, but most expats here will have filed their absentee ballots long before that date. So A.M. Costa Rica will cut off discussion of the candidates and their positions Oct. 15.
Shortly thereafter, this newspaper will publish its opinion and endorsement.
This is the same rule that applied in 2008, but some readers, miffed at the newspaper endorsement, became enraged when told their letters would not be published.
So if readers have something to say on the presidential or congressional elections, they should say it before Oct. 15.
Of course if someone wishes to insert political advertising promoting one candidate or another, the newspaper will happily accept money at the printed rates. The ad must contain a line of type saying who paid for the message.
This message will be repeated as the election draws near.


text:
Christifideles Laici is the name of a post-synodal apostolic exhortation of Pope John Paul II, signed in Rome on December 30, 1988. It is summary of the teaching that arose from the 1987 synod of bishops on the vocation and mission of the laity in the Church and the World.
The goal of the document is to indicate the road of lay participation in human society. "This Exhortation intends to stir and promote a deeper awareness among all the faithful of the gift and responsibility they share, both as a group and as individuals, in the communion and mission of the Church."
|This Roman Catholicism-related article is a stub. You can help by expanding it.