text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 27, 2007
|Filing date
|Aug 7, 2006
|Priority date
|Dec 14, 2004
|Fee status
|Also published as
|Publication number
|Sergey Anatolievich Gorobets, Yan Li
|Original Assignee
|Sandisk Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (60), Non-Patent Citations (7), Referenced by (36), Classifications (18), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of U.S. patent application Ser. No. 11/013,125, entitled, "Pipelined Programming of Non-Volatile Memories Using Early Data," filed on Dec. 14, 2004 now U.S. Pat. No. 7,120,051, which is incorporated herein by this reference.
This invention relates generally to a non-volatile memory and its operation, and, more specifically, to techniques for improving the programming speed of multi-state memories when complete data is not initially present at the time programming is initiated.
The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates, as exemplary.
It is common in current commercial products for each floating gate storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate storage element) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the floating gate storage elements decreases. Since the ranges of charge designated for each storage state must necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced. Actual shifts in the charge stored in one cell can be disturbed when reading, programming and erasing other cells that have some degree of electrical coupling with that cell, such as those in the same column or row, and those sharing a line or node.
Apparent shifts in the stored charge occur because of field coupling between storage elements. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased and as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to their floating gates that corresponds to one set of data. After the second set of cells is programmed with a second set of data, the charge levels read from the floating gates of the first set of cells often appear to be different than programmed because of the effect of the charge on the second set of floating gates being coupled with the first. This is described in U.S. Pat. Nos. 5,867,429 and 5,930,167, which patents are incorporated herein in their entirety by this reference. These patents describe either physically isolating the two sets of floating gates from each other, or taking into account the effect of the charge on the second set of floating gates when reading that of the first. Further, U.S. Patent No. 5,930,167 describes methods of selectively programming portions of a multi-state memory as cache memory, in only two states or with a reduced margin, in order to shorten the time necessary to initially program the data. This data is later read and re-programmed into the memory in more than two states, or with an increased margin.
This effect is present in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. No. 09/505,555, filed Feb. 17, 2000, and Ser. No. 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935. Briefly, two bits of data, often from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, re-programming that cell into another one of its states according to the second bit of incoming data.
As described in these patents, a common technique for encoding the data stored in these multi-state (or MLC) memories is to both store an upper page of data and a lower page of data in the same set of multi-level cells. This arrangement has the shortcoming that if a physical page of MLC flash memory is being programmed with the lower page data, the user (controller) has to wait until the programming is finished to be able to start programming the upper page data, when, in fact, both the lower and upper page data are going to be programmed into the same physical page. It is also common in these designs to write data in a page containing an amount of data corresponding to multiple units of data transfer. This results in the shortcoming that if a flash memory is being partially programmed, as when a multi-sector or multi-plane page is programmed with, say, only a single sector of data, the user (controller) has to wait until programming is finished to be able to start another partial program of the same page. The performance of non-volatile memory systems could be improved if these shortcomings could be reduced or eliminated.
Briefly and generally, the present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. If additional data assigned to the group arrives while programming is in progress, the programming is interrupted and the current state of the memory cells is determined. The additional data is then incorporated into the data being programmed and programming resumes, until completion or until even more additional data assigned to the group arrives on the memory. This allows performance to be increased since programming of the additional data can begin as it arrives, rather than waiting until the partial content programming in process completes.
In a sub-aspect of the present invention, the present invention allows overlapped programming of upper and lower data pages. In a multi-state system using multi-pass programming, the lower logical data page assigned to physical page of the memory begins programming. Once the upper logical data page assigned to the same physical page is transferred to the memory, the programming of the lower page is interrupted and the status of the lower page programming is established. The memory than converts to a multi-state programming mode to write the upper and lower page data concurrently. This allows the lower page data to start programming as soon as it is available, without having to wait for an associated upper page. It also allows the upper page to begin programming as soon as it is available, without waiting for the first programming pass to finish writing in the lower page.
In another sub-aspect of the present invention, programming to a physical page can start once data that has been assigned to a given physical page has been transferred, even if corresponds to less than the full complement of planes that make up the page. For example, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received. Once the partial page programming begins, should additional data (e.g. additional sectors) assigned to the page being programmed be transferred to the memory, the partial page programming is interrupted and the status of the partial page is established. The memory then adds the additional data to the write and restarts programming. This allows the first transferred data to start programming as soon as it is available, without having to wait for any additional data needed to complete the page. It also allows the additional data to begin programming once it is transferred, without waiting for the partial page programming of the initially transferred portion of the page to finish writing, resulting in a pipelined partial page programming process. Additionally, the physical page can be distributed across multiple planes of the memory.
A specific embodiment of these aspects uses a staircase programming waveform. When the additional data is received, the level of the staircase and other associated parameters may need to be reset depending upon the progression of programming to that point.
Additional aspects, features, advantages and applications of the present invention are included in the following description of exemplary embodiments, which description should be taken in conjunction with the accompanying drawings.
Example Non-Volatile Memory System
With reference to
The data stored in the memory cells (M) are read out by the column control circuit 2 and are output to external I/O lines via an I/O line and a data input/output buffer 6. Program data to be stored in the memory cells are input to the data input/output buffer 6 via the external I/O lines, and transferred to the column control circuit 2. The external I/O lines are connected to a controller 20.
Command data for controlling the flash memory device are input to a command interface) connected to external control lines that are connected with the controller 20. The command data informs the flash memory of what operation is requested. The input command is transferred to a state machine 8 that controls the column control circuit 2, the row control circuit 3, the c-source control circuit 4, the c-p-well control circuit 5 and the data input/output buffer 6. The state machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
The controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, or a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from the memory array 1, and provides or receives such data, respectively. The controller converts such commands into command signals that can be interpreted and executed by the command circuits 7. The controller also typically contains buffer memory for the user data being written to or read from the memory array. A typical memory system includes one integrated circuit chip 21 that includes the controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
With reference to
During a user data read and programming operation, 4,256 cells (M) are simultaneously selected, in this example. The cells (M) selected have the same word line (WL), for example WL2, and the same kind of bit line (BL), for example the even bit lines BLe0 to BLe4255. Therefore, 532 bytes of data can be read or programmed simultaneously and this unit of data is referred to as a page. Since in this example each NAND string contains 4 cells and there are two bit lines per sense amp, one block can store at least eight pages. When each memory cell (M) stores two bits of data, namely a multi-level cell, one block stores 16 pages. In this embodiment, the storage element of each of the memory cells, in this case the floating gate of each of the memory cells, stores two bits of user data.
Each memory cell has a floating gate (FG) that stores an amount of charge corresponding to the data being stored in the cell, the word line (WL) forming the gate electrode, and drain and source electrodes made of the n-type diffusion layer 12. The floating gate (FG) is formed on the surface of the c-p-well via a tunnel oxide film (14). The word line (WL) is stacked on the floating gate (FG) via an insulator film (15). The source electrode is connected to the common source line (c-source) made of the first metal (M0) via the second select transistor (S) and the first contact hole (CB). The common source line is connected to the c-source control circuit (4). The drain electrode is connected to the bit line (BL) made of a second metal (M1) via the first select transistor (S), the first contact hole (CB), an intermediate wiring of the first metal (MO) and a second contact hole (V1). The bit line is connected to the column control circuit (2).
Table I of
In order to store electrons in the floating gate (FG) during a programming operation, the selected word line WL2 is connected to a program pulse Vpgm and the selected bit lines BLe are grounded. On the other hand, in order to inhibit the program on the memory cells (M) in which programming is not to take place, the corresponding bit lines BLe are connected to a positive voltage Vdd, for example 3V, as well as all of the unselected bit lines BLo. The unselected word lines WL0, WL1 and WL3 are connected to 10V, the first select gate (SGD) is connected to Vdd, and the second select gate (SGS) is grounded. As a result, a channel potential of the memory cell (M) that is being programmed is set at 0V. The channel potential of a cell that is being inhibited is raised to around 6V as a result of the channel potential being pulled up by the capacitive coupling with the word lines (WL). As explained above, a strong electric field is applied to only the tunnel oxide films 14 of the memory cells (M) during programming, and the tunnel current flows across the tunnel oxide film 14 in the reverse direction compared to the erase, and then the logical state is changed from "11" to one of the other states "10", "01, or "00". Various other coding schemes may be selected to represent these states so that the designation E (erase), A (lowest threshold program state), B (threshold higher than A), and C (highest threshold program state) will be used in the subsequent discussion.
In the read and verify operations, the select gates (SGD and SGS) and the unselected word lines (WL0, WL1 and WL3) are raised to a read pass voltage of 4.5V to insure that current between the bit line and common source line can pass through them. The selected word line (WL2) is connected to a voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. For example, in a READ 10 operation (state A), the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than 0V. In this read case, it can be said that a read level is 0V. In a VERIFY01 operation (state C), the selected word line WL2 is connected to 2.4V, so that it is verified that whether the threshold voltage has reached 2.4V. In this verify case, it can be said that a verify level is 2.4V.
The selected bit lines (BLe) are pre-charged to a high level, for example 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the concerned bit line (BLe) maintains the high level, because of the non-conductive memory cell (M). On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell (M). Further details of the read and verify operations are explained below.
Operation of the Memory System with More than Two States per Storage Element
Each of the two bits stored in a single memory cell (M), in this example, is from a different logical page. That is, each bit of the two bits stored in each memory cell carries a different logical page address from the other. The lower page bit shown in
In order to provide improved reliability, it is better for the individual distributions to be tightened (the threshold distribution narrowed), because the tighter distribution results in a wider read margin (distance between them). According to the present invention, the distribution width remains tighter without a conspicuous degradation in the programming speed.
According to the article "Fast and Accurate Programming Method for Multi-level NAND EEPROMs", Digest of 1995 Symposium on VLSI Technology, pp 129-130, which article is incorporated herein by this reference, in principle, limiting a distribution to a 0.2V-width requires that the usual repetitive programming pulses be incremented 0.2V between steps.
In periods between the pluses, the verify (read) operations are carried out. That is, the programmed level of each cell being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than the verify level to which it is being programmed. If it is determined that the threshold voltage of a given memory cell has exceeded the verify level, programming is stopped or inhibited for that bit by raising the voltage of the bit line to which the series cell unit of the given cell is connected from 0V to Vdd. Programming of others of the cells being programmed in parallel on the same page continues until they in turn reach their verify levels. When the threshold voltage moves from below the verify level to above it during the cell's last programming pulse, the shift of the threshold voltage is equal to the Vpgm step size of 0.2V. Therefore, the threshold voltages are controlled within a 0.2V-width.
In a second programming pass, the cell's threshold level is set according to the bit being stored in the cell from the upper logical page. If a "1", no programming occurs since the cell is in one of the states 33 or 34, depending upon the programming of the lower page bit, both of which carry an upper page bit of "1". If the upper page bit is a "0", however, the cell is programmed a second time. If the first pass resulted in the cell remaining in the erased or E state 33, the cell is programmed from that state to the highest threshold state 36 (state C), as shown by the upper arrow
Of course, if the memory is operated with more than four states, there will be a number of distributions within the defined voltage threshold window of the memory cells that is equal to the number of states. Further, although specific bit patterns have been assigned to each of the distributions, different bit patterns may be so assigned, in which case the states between which programming occurs can be different than those shown in
The voltages VRA, VRB and VRC, positioned roughly halfway between adjacent ones of the distributions 33-36, are used to read data from the memory cell array. These are the threshold voltages with which the threshold voltage state of each cell being read is compared. This is accomplished by comparing a current or voltage measured from the cell with reference currents or voltages, respectively. Margins exist between these read voltages and the programmed threshold voltage distributions, thus allowing some spreading of the distributions from disturbs and the like, as discussed above, so long as the distributions do not overlap any of the read voltages VRA, VRB and VRC. As the number of storage state distributions increases, however, this margin is reduced and the programming is then preferably carried out with more precision in order to prevent such spreading.
The previous description assumes that two logical pages reside in one physical page and that only the lower logical page or the upper logical page but not both are programmed during a given programming cycle. U.S. patent application publication US 2003/0112663 titled "Method and System for Programming and Inhibiting Multi-Level Non-Volatile Memory Cells", hereby incorporated by reference, describes programming all of the physical states of the page during one programming operation. In the case of four states per cell as shown in
Although specific programming scheme has been described using
Overlapped Programming of Data Portions in the Same Page
As described above, a unit of programming or "physical page" is composed of the cells that can be programmed concurrently. In the case of a multi-state memory, each physical page can store more than one logical page; the exemplary embodiment stores an upper logical page and a lower logical page in each physical page. In the two pass programming process of the prior art, once the lower page data assigned to a given physical page begins a programming operation, the process must be carried through to completion for a successful programming operation. Although the upper page data assigned to the same physical page may be present in the memory registers, the prior art does not allow the first programming pass to be interrupted and later restarted to include all of the data content for the physical page. Thus, although all of the data to be programmed into a given physical page may be present on the memory, the programming process cannot transition to a full programming sequence and the upper page data must wait until the lower page completes the programming process of the first pass.
In the prior art, it is also known that programming can be performed concurrently in multiple semi-autonomous memory arrays, know as planes (or quads), distributed across one or more memory chips, as is described in more detail in U.S. Pat. Nos. 5,890,192 and 6,426,893, which are hereby incorporated by reference. The memory may be either binary or multi-state. In this case, the physical page will consist of several planes and a programming operation will concurrently program a sector (or other amount of data) into each of these planes. If the data for some, but less than all, of the arrays has transferred to the memory, to program the full page the memory must wait for data for the rest of the page. Alternately, the memory can program the data it has in a partial page programming operation, where the missing portion is either not programmed or treated as if the data is all the erased state. Should additional data belonging to the page arrive during the partial page programming, the prior art does not allow the programming operation to be interrupted and restarted incorporating the additional data.
Both of these cases are similar in that a programming operation is started with less than the full amount of data that the physical page can contain. The situation can be conceptualized as subdividing the physical page in either the horizontal direction (into planes) or the vertical direction (upper and lower pages). When data is provided for less than all of the subdivisions, a partial programming based upon the available data can be started; but as the physical page forms a unit of programming, without provisions for interrupting and restarting programming, additional data cannot be incorporated except by using an additional, subsequent programming operation. A principal aspect of the present invention provides this capability.
In the upper page/lower page arrangement, this results in the overlapped programming of upper and lower multi-state memory pages. In the multi-plane case, this results in pipelined partial page programming. In exemplary embodiments of these two sub-aspects, the programming process uses a staircase programming waveform, such as shown in
Overlapped Programming of Upper and Lower MLC Pages
As described in the Background, when a physical page of MLC flash memory is being programmed with the lower page data, the user (controller) has to wait until the programming is finished to be able to start programming the upper page data, when in fact, both the lower and upper page data will eventually be programmed into the same physical page. This is shown in
After the lower page data has been transferred from the controller to the memory, the upper page data is transferred to the controller and then on to the flash memory. The transfer occurs during the programming of the lower page and is completed at time t2. Although the upper page data is on the chip at time t2, as the prior art does not allow the lower page programming to be terminated before completion and then subsequently resumed, the upper page data cannot be programmed until time t3 when the lower page programming is complete. Beginning at time t3, the upper page data are then programmed as shown in
According to a first aspect of the present invention, once the upper page data is present on the memory the lower page programming is interrupted at time t2. The process is then resumed, programming both the lower and the upper page data at the same time. This eliminates the programming time between time t2 and time t3 that was devoted to the lower page data alone, and essentially reduces the programming time by this amount.
In a first aspect of the present invention, the time between t2 and t3 (when the upper page data has been transferred to the memory but is not being programmed) in
Under the prior art arrangement, the limitations of
In this aspect of the invention, the method begins by starting the programming of the lower page before the upper page data is available. The programming operation can be stopped before the lower page programming is complete when upper page data is available. If the new data should be written to another physical page, then the controller only needs to wait for the end of the on-going lower page program operation; however, if the new data is the upper page data corresponding to the same physical page as the current lower page date being programmed, the status of the memory cells being programmed is verified and the memory's physical page can then be programmed with both the lower and the upper pages data in parallel. As a result, the controller can start lower page programming as soon as it can without possible performance penalty in the case where it needs to wait for the upper page's data. The method is illustrated schematically in
As in
Once the second set of data is received, it needs to be checked that it is for the upper page corresponding to the same physical cells of the memory as the lower page being programmed. More generally, it is checked to see that it corresponds to an additional set of data states stored in the same set of cells as those currently being programmed; for example, if three pages are stored on a physical page, it could be the middle page corresponding to the lower page going programming. When it is determined that the new upper page data is appropriate to be added to the currently programming lower page, a change to a "full sequence programming" is initiated. Full sequence programming means that two binary bits are being programmed simultaneously. While this increases the programming speed, it may require one or more additional verify steps after each programming pulse to determine when programming for each bit should be terminated. Initiating a change from lower page programming to full sequence programming requires that several conditions be examined. First, it must be determined if lower page programming is in fact complete or nearly complete. If so, the change to full sequence programming will not occur; lower page programming will complete in the normal fashion and programming will continue with upper page programming using the standard programming algorithms. Secondly, a change to full sequence programming will only occur at the completion of the current program verify cycle. For an embodiment using a staircase programming voltage waveform, such as that shown in
If event t2 occurs prior to pulse 101, the lower page to full sequence conversion will occur before the pulse amplitude reaches the full sequence starting value of 105. In this case, the staircase can continue to rise by constant step levels until it reaches this level, with pulses between 101 and 105 removed and these two pulses basically coalescing and forming a single staircase such as that shown in
While only the lower page is being programmed, only the A state needs to be verified, as indicated by pvfyA. Once the upper page data is loaded, the B state is also verified, as indicated by pvfyA/B. After the number of pulses allotted for the A state, programming can stop for any cells having the A state as their target state that have not verified and these can be dealt with by error correction methods. Sometime after the verification of the A state is discontinued, verification of the C state is added to the verification of the B state, as indicated by pvfyB/C. Once the allotted number of pulses for the B state have been used, only the C state continues to be verified as indicated by pvfyC. Line 41 indicates that when all cells are verified in state B and only programming of state C remains, new data for the next page can be received and occur while programming continues for state C. This is another embodiment of the invention to further improve programming time. Assuming the state coding referenced earlier in
Pipelined Partial Page Programming
As described in the Background, when a page in a flash or other memory is being partially programmed, for example a multi-sector or multi-plane page is programmed with only a single sector of data, the user (controller) has to wait until programming is finished to be able to start another partial program of the same page. This process is shown in
The first two lines of
The bottom four lines of
While the partial page of sectors 0 and 1 is being programmed, the rest of the data corresponding to this page arrives, and sector 2 and sector 3 data are transferred to the memory at times t2 and t3, respectively. As the prior art does not allow for interrupting and later resuming programming before the programming is complete, the memory must wait until sectors 0 and 1 finish programming at time t4 before sector 2 and 3 data can be programmed into planes 2 and 3 in a second partial programming operation. While programming sectors 2 and 3, sectors 4-7 are transferred and can be programmed together as a whole page, starting at time t5 when the partial page programming of sectors 2 and 3 finishes. It should be noted that this sequence is just an example of the timing for when the different sectors are transferred; more generally, these considerations would apply any time there is a gap so that less all of the sectors that make up a complete page show up one right after another and, subsequently, additional sectors belonging to the page arrive while the partial page is still programming.
Although the data for sector 2 is present at time t2 and the data for sector 3 is present at time t3, according to the prior art the partial page of sectors 0 and 1 cannot be interrupted and then resumed in mid-course to include these additional portions of the page, but must finish at time t4 followed by a second partial page programming. A aspect of the present invention is a method allowing pipelining partial programming of memory pages in flash memory so that the memory can be programmed at its highest programming bandwidth under any circumstances. A particular strategy is to start programming as soon as possible, based on this method, can significantly increase system performance in applications where the host writes in small clusters or non-contiguously.
To deal with these problems in the prior art, there are different methods where the main idea is to collect as much data as possible for page programming. In this case the data for different sectors is cached in the controller buffer or memory data register until all the data for the page is collected for full page programming, so that for the transfers shown in
A first partial page programming begins with a first data portion, leaving some sectors blank. This first partial page programming begins before the next host command is received and when it is unknown whether the next command is a contiguous sector write. The first partial page programming operation can be stopped before completion if a subsequent command relates to data for the blank sectors of the page as soon as this new data portion is received. If the new data corresponds to another page, then the controller only needs to wait for the end of the on-going program operation. The status of the memory cells is then verified and the page can then be programmed with both the original and the new data in parallel. The memory can indicate a status for every sector/plane of the page being programmed, so that the controller can free up the buffer, which contains data for those sectors already programmed. The controller can start programming of the next sector in a plane independently from the on-going activity in the other planes and the multi-plane memory can start programming in those planes where programming is complete ahead of other planes.
According to these various sub-aspects, the controller can start first partial page programming operation as soon as it can without possible performance penalty in the case that it later wants to program more data to the same page. This also allows the controller to free up data buffers, which contained the data for the first portion, before the second portion data programming is finished. Further, if memory architecture allows, the controller can start another program operation in the inactive planes.
A first embodiment of a pipelined partial page programming operation is illustrated in the diagram of
Prior to time t1 in
At time t2, data for sector 2 are received by a new command (as in the other examples this can be any sector, which is going to be written subsequently to the sectors 0 and 1 as part of the same page). The controller reports successful command execution and sector 2 is transferred to the flash memory. The physical page programming is stopped and the physical page's state is verified so that the correct programming mode (for example, coarse or fine) can be chosen later for every cell. Partial page programming then resumes, where planes 0, 1 and 2 will be programmed with sector 0, 1 and 2 data, correspondingly, and plane 3 will either be programmed with blank data (FF's) or will not be programmed at all. One implementation of a coarse/fine programming mode is disclosed in U.S. Pat. No. 6,643,188, hereby incorporated by reference.
At time t3, data for sector 3 is received by a new command. The controller does not report a successful command execution, as no data buffers are available. Sector 3 is transferred to the flash memory. The physical page programming is again stopped and the physical page's state is verified so that the correct programming mode can be chosen later for every cell. Full page programming can then start, where planes 0, 1, 2 and 3 will be programmed with sector 0, 1, 2 and 3 data correspondingly.
In this embodiment, at time t4, the programming of sector data 0 and 1 into planes 0 and 1 finishes, the controller frees up the buffers which contained data for sectors 0 and 1, and the controller reports successful execution of the last command. After time t4 and prior to time t5, data for sectors 4 and 5 are received by the controller and are transferred to the 4-plane flash memory. If the memory allows independent plane programming, then programming of planes 0 and 1 can start, where planes 0 and 1 will be programmed with data for sectors 4 and 5 correspondingly, and planes 2 and 3 will still be programmed with blank data (FF's) or will not be programmed at all. If memory planes cannot be programmed independently, then physical page programming can be stopped, the physical page's state verified so that the correct programming mode can be chosen later for every cell, and the programming for all planes started with data for sectors 2, 3, 4 and 5.
Prior to the time t6, the programming of plane 2 finishes, the controller frees up the buffer which contained data for sector 2 and the controller reports a successful execution of the last command. Data for sector 6 is subsequently received by the controller. The controller does not report a successful command execution as no the data buffers are available. Sector 6 is transferred to the flash memory. If memory allows independent plane programming, then plane 2 programming starts with sector 6 data, and planes 0, 1 and 3 will restart programming with sectors 4, 5, and 3 data respectively. If memory planes cannot be programmed independently, then physical page programming should be stopped, the physical page's state verified so that the correct programming mode can be chosen later for every cell, and the programming for all planes started with data for sectors 3,4,5 and 6.
At time t7, programming of plane 3 finishes and the controller can free up the buffer with data for sector 3. If programming of sectors 4, 5, and 6 has not been started yet, then partial page programming can start, where planes 0, 1, and 2 will be programmed with sector 4, 5, and 6 data correspondingly, and plane 3 will either be programmed with blank data (FF's) or will not be programmed at all. At time t8, sector 7 data is received by a new command. The controller does not report successful command execution as no data buffers are available. Sector 7 is transferred to the flash memory. Physical page programming is stopped and its state is verified so that the correct programming mode can be chosen later for every cell. Full programming starts, where planes 0, 1, 2 and 3 will be programmed with sector 4, 5, 6 and 7 data, correspondingly.
Until time t2, the process of
In the example, however, sector 3 data arrives and is transferred at time t3. Programming of the partial page of planes 0-2 is interrupted, the programming process is again reset as at time t2, and programming resumes with the full page. Due to the resetting, the full page finishes at time t7. This allows the programming of each sector to begin in a pipelined, partial page process as soon as the data is available. Rather than both of sectors 2 and 3 waiting until time t4 to begin programming, they can respectively start at t2 and t3.
While sectors 0-3 are programming, sectors 4 and 5 are transferred by time t5, with sector 6 transferred by time t6. Once the first page finishes at time t7, partial page programming of planes 0-2 with respective sector data 4-6 begins, following the same process as the first page. This assumes buffer space is available before sectors 0-3 finish programming. If not, as soon as the programming of this first page finishes, sectors 4-6 are then transferred subsequent to event time t4. Once they are on the memory, the programming of the partial page of sectors 4-6 into planes 0-2 begins. When sector 7 data arrives, the partial page programming of planes 0-2 is interrupted, the process reset, and full page programming resumes at event time t8.
In all of the forgoing embodiments, both for pipelined partial page programming and for overlapped programming of upper and lower MLC pages (that is, for both the "horizontal" and "vertical" implementations of overlapped programming of data portions in the same page), it should be noted that the usage of "current programming operations" or, more briefly, "concurrently programming" does not necessarily imply that all programming pulses for all the data within a page are absolutely simultaneous. This also applies to the case when a page spans multiple planes (a "meta-page"). For example, in the case where a meta-page spans multiple chips, the programming pulses of the programming operation in the first chips maybe started first, followed by those for the same programming operation in the second chip. Such wide-meta-pages are used in some multi-chip parallel configurations for convenience. Among the areas where these may provide advantages are: address translation; in minimizing overhead if the programming parts of a meta-page is not simultaneous, but the program pulses can be started one after another in a shorter time if enough data is collected for multiple programs (in an extreme case, data may be programmed bit by bit inside the memory chip); and/or minimize power consumption.
Alternate Use of Dielectric Storage Elements
The forgoing examples of flash EEPROM memory cells have been described with respect to the type of cell that utilizes conductive floating gates as charge storage elements. However, the various aspects of the present invention can be used in conjunction with the various memory technologies described in U.S. patent application Ser. No. 10/841,379 filed May 7, 2004, which is hereby incorporated by reference. For example, the invention may also be implemented in a system that uses a charge trapping dielectric as the storage elements in individual memory cells in place of floating gates. The dielectric storage element is sandwiched between a conductive control gate and the substrate within the cell's channel region. Although the dielectric can be separated into individual elements with the same sizes and positions as the floating gates, it is usually not necessary to do so since charge is trapped locally by such a dielectric. The charge trapping dielectric can extend over the entire array except in areas occupied by the select transistors or the like.
Dielectric storage element memory cells are generally described in the following technical articles and patent, which articles and patent are incorporated herein in their entirety by this reference: Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95; Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501; Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, and U.S. Pat. No. 5,851,881.
There are two specific charge trapping dielectric materials and configurations that are practical for use. One is a three-layer dielectric with silicon dioxide initially grown on the substrate, a layer of silicon nitride deposited thereover and another layer of silicon oxide, grown and/or deposited, over the silicon nitride layer ("ONO"). A second alternative is a single layer of silicon rich silicon dioxide sandwiched between the gate and the semiconductor substrate surface. This later material is described in the following two articles, which articles are incorporated herein in their entirety by this reference: DiMaria et al., "Electrically-alterable read-only-memory using Si-rich SI02 injectors and a floating polycrystalline silicon storage layer," J. Appl. Phys. 52(7), July 1981, pp. 4825-4842; Hori et al., "A MOSFET with Si-implanted Gate-Si02 Insulator for Nonvolatile Memory Applications," IEDM 92, April 1992, pp. 469-472. Dielectric storage elements are also discussed further in the U.S. patent application Ser. No. US 10/280,352, filed Oct. 25, 2002, which is hereby incorporated by this reference.
Although the present invention has been described in terms of specific examples and variations thereof, it is understood that the invention is to be protected within the full scope of the appended claims.
|Cited Patent
|Filing date
|Publication date
|Apr 17, 1991
|Dec 28, 1993
|International Business Machines Corporation
|Excessive error correction control
|Aug 30, 1994
|Nov 7, 1995
|Kabushiki Kaisha Toshiba
|Non-volatile memory device with a sense amplifier capable of copying back
|Feb 19, 1993
|Dec 17, 1996
|Intel Corporation
|Method and circuitry for increasing reserve memory in a solid state memory disk
|Mar 10, 1994
|Mar 31, 1998
|International Business Machines Corporation
|Nonvolatile memory with flash erase capability
|Mar 26, 1997
|Oct 13, 1998
|Atmel Corporation
|Dual buffer flash memory architecture with multiple operating modes
|Sep 29, 1997
|Jan 19, 1999
|Integrated Silicon Solution, Inc.
|Non-volatile programmable memory having a buffering capability and method of operation thereof
|Nov 5, 1996
|Mar 30, 1999
|Sandisk Corporation
|Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM
|Dec 27, 1995
|Apr 6, 1999
|Intel Corporation
|Flash memory array with two interfaces for responding to RAS and CAS signals
|Jun 23, 1998
|Oct 19, 1999
|Invox Technology
|High-bandwidth read and write architectures for non-volatile memories
|Sep 2, 1997
|Feb 1, 2000
|International Business Machines Corporation
|Method and means for efficiently managing update writes and fault tolerance in redundancy groups of addressable ECC-coded sectors in a DASD storage subsystem
|Jun 2, 1997
|Feb 22, 2000
|Bull, S.A.
|Circuit for moving data between remote memories and computer comprising such a circuit
|Mar 25, 1998
|Mar 21, 2000
|Lexar Media, Inc.
|Flash memory leveling architecture having no external latch
|Aug 21, 2000
|Jul 24, 2001
|Sandisk Corporation
|Method and structure for reliable data copy operation for non-volatile memories
|Nov 12, 1998
|Aug 28, 2001
|Seiko Epson Corporation
|Non-volatile memory apparatus including first and second address conversion tables stored in volatile and nonvolatile memories for improved access at power up
|Nov 24, 1998
|Sep 25, 2001
|Intel Corporation
|Method and apparatus for error management in a solid state disk drive
|Apr 4, 2001
|Nov 13, 2001
|Hitachi, Ltd.
|Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory
|Jan 23, 2001
|Dec 11, 2001
|Multi Level Memory Technology
|High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream
|Nov 16, 1999
|Apr 16, 2002
|Lexar Media, Inc.
|Data pipelining method and apparatus for memory control circuit
|Jun 22, 2001
|May 14, 2002
|Hitachi, Ltd.
|Semiconductor memory device having faulty cells
|Aug 13, 2001
|Jul 16, 2002
|Hitachi, Ltd.
|Flash memory control method and apparatus processing system therewith
|Feb 17, 2000
|Jul 30, 2002
|Sandisk Corporation
|Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
|Apr 20, 1999
|Sep 10, 2002
|Lucent Technologies Inc.
|Use of a two-way stack approach to optimize flash memory management for embedded database systems
|Sep 17, 2001
|Sep 24, 2002
|Sandisk Corporation
|Selective operation of a multi-state non-volatile memory system in a binary mode
|Feb 28, 2002
|Dec 3, 2002
|Lexar Media, Inc.
|Memory device
|Mar 26, 2002
|Feb 18, 2003
|Multi Level Memory Technology
|Dynamic refresh that changes the physical storage locations of data in flash memory
|Apr 8, 2002
|Feb 25, 2003
|Sony Corporation
|Recording system, data recording apparatus, memory apparatus, and data recording method
|Dec 28, 2001
|May 6, 2003
|Sandisk Corporation
|Method and structure for efficient data verification operation for non-volatile memories
|Sep 1, 2000
|Jun 17, 2003
|International Business Machines Corporation
|Computer program product and method for partial paging and eviction of microprocessor instructions in an embedded computer
|Jun 14, 2004
|Feb 7, 2006
|Sandisk Corporation
|Operating techniques for reducing program and read disturbs of a non-volatile memory
|Dec 14, 2004
|Oct 10, 2006
|Sandisk Corporation
|Pipelined programming of non-volatile memories using early data
|Jun 19, 2001
|Nov 15, 2001
|Micron Technology, Inc.
|Method and apparatus for programming multi-state cells in a memory device
|Dec 28, 2001
|Sep 12, 2002
|Sandisk Corporation
|Novel method and structure for efficient data verification operation for non-volatile memories
|Sep 27, 2002
|Apr 3, 2003
|Gorobets Sergey Anatolievich
|Memory system sectors
|Sep 27, 2002
|Apr 10, 2003
|Gorobets Sergey Anatolievich
|Memory system for data storage and retrieval
|Nov 18, 2002
|May 29, 2003
|M-Systems Flash Disk Pioneers, Ltd.
|Detecting partially erased units in flash devices
|Jan 3, 2002
|Jul 3, 2003
|Elmhurst Daniel R.
|Programming non-volatile memory devices
|Feb 3, 2003
|Jul 24, 2003
|Jian Chen
|Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells
|Feb 22, 2002
|Aug 28, 2003
|Conley Kevin M.
|Pipelined parallel programming operation in a non-volatile memory system
|Feb 6, 2003
|Sep 11, 2003
|Kabushiki Kaisha Toshiba
|Non-volatile semiconductor memory device
|Feb 7, 2003
|Sep 18, 2003
|Sandisk Corporation
|Novel method and structure for efficient data verification operation for non-volatile memories
|Jun 12, 2003
|Jan 1, 2004
|Fujitsu Limited
|Semiconductor memory
|Mar 27, 2003
|Feb 12, 2004
|Mitsubishi Denki Kabushiki Kaisha
|Nonvolatile semiconductor memory device allowing high speed data transfer
|Feb 12, 2004
|Aug 19, 2004
|Tetsuya Tsujikawa
|Semiconductor, memory card, and data processing system
|Jun 7, 2002
|Oct 21, 2004
|Renesas Technology Corp.
|Nonvolatile memory
|May 8, 2003
|Nov 25, 2004
|Micron Technology, Inc.
|Program failure recovery
|Dec 14, 2005
|Jun 15, 2006
|Yan Li
|Data recovery methods in multi-state memory after program fail
|Dec 14, 2005
|Jun 15, 2006
|Yan Li
|Multi-state memory having data recovery after program fail
|Dec 21, 2004
|Jul 13, 2006
|Andrew Tomlin
|Method for copying data in reprogrammable non-volatile memory
|Mar 9, 1994
|Sep 14, 1994
|International Business Machines Corporation
|Nonvolatile memory
|Apr 26, 2002
|Jan 29, 2003
|Samsung Electronics Co., Ltd.
|Memory devices with page buffer having dual registers and methods of using the same
|Title not available
|Title not available
|Title not available
|Mar 31, 1998
|Oct 8, 1998
|Lexar Media, Inc.
|Moving sectors within a block in a flash memory
|Feb 17, 2000
|Aug 24, 2000
|Memory Corporation Plc
|Memory system
|Apr 25, 2000
|Nov 9, 2000
|Koninklijke Philips Electronics N.V.
|Device for use as stand-alone device and as slave device in a data bus system
|Nov 13, 2001
|Jun 20, 2002
|Sandisk Corporation
|Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory
|Jan 7, 2002
|Jul 25, 2002
|Sandisk Corporation
|Partial block data programming and reading operations in a non-volatile memory
|Sep 27, 2002
|Apr 10, 2003
|Lexar Media, Inc.
|Non-volatile memory control
|Feb 5, 2003
|Aug 21, 2003
|Advanced Micro Devices, Inc.
|Partial page programming of multi level flash semiconductor memory
|Imamiya et al., "A 125-mm<SUP>2 </SUP>1-Gb NAND Flash Memory with 10/Mbyte/s Program Speed," IEEE Journal of Solid State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1493-1501.
|Lee et al., "High-Performance 1-Gb NAND Flash Memory with 0.12-mum Technology," Journal of Solid-State Circuits, Nov. 2002, vol. 37, No. 11, pp. 1502-1509.
|Listing of Pending Claims for International Application No. PCT/US2005/043020, 7 pages.
|Nakamura et al., "A Novel Sense Amplifier for Flexible Voltage Operation NAND Flash Memories," 1995 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 8-10, 1995, pp. 71-72.
|Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration for International Application No. PCT/US2005/016341 mailed Oct. 19, 2005, 12 pages.
|Notification of Transmittral of the International Search Report and the Written Opinion of the International Searching Authority, or the Delcaration for International Application No. PCT/US2005/043020 mailed May 10, 2006, 9 pages.
|Srisa-an et al., "Performance Enhancements to the Active Memory System," 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sep. 16-18, 2002, pp. 249-256.
|Citing Patent
|Filing date
|Publication date
|May 5, 2006
|Nov 4, 2008
|Sandisk Corporation
|Method for non-volatile memory with background data latch caching during read operations
|May 5, 2006
|Dec 9, 2008
|Sandisk Corporation
|Method for non-volatile memory with managed execution of cached data
|May 5, 2006
|Jan 20, 2009
|Sandisk Corporation
|Non-volatile memory with background data latch caching during read operations
|May 5, 2006
|Feb 3, 2009
|Sandisk Corporation
|Non-volatile memory with managed execution of cached data
|May 5, 2006
|Mar 10, 2009
|Sandisk Corporation
|Method for non-volatile memory with background data latch caching during program operations
|May 5, 2006
|Mar 17, 2009
|Sandisk Corporation
|Non-volatile memory with background data latch caching during program operations
|Dec 4, 2006
|Mar 24, 2009
|Sandisk Corporation
|Use of data latches in multi-phase programming of non-volatile memories
|May 5, 2006
|Oct 27, 2009
|Sandisk Corporation
|Non-volatile memory with background data latch caching during erase operations
|May 5, 2006
|Nov 17, 2009
|Sandisk Corporation
|Method for non-volatile memory with background data latch caching during erase operations
|Nov 3, 2008
|Jun 8, 2010
|Sandisk Corporation
|Method for non-volatile memory with background data latch caching during read operations
|Jun 30, 2009
|May 3, 2011
|Sandisk Corporation
|Use of data latches in cache operations of non-volatile memories
|Oct 27, 2009
|May 31, 2011
|Micron Technology, Inc.
|Program-verify method
|Mar 19, 2008
|Jul 26, 2011
|Sandisk Technologies Inc.
|Different combinations of wordline order and look-ahead read to improve non-volatile memory performance
|May 18, 2010
|Oct 11, 2011
|Sandisk Technologies Inc.
|Method for non-volatile memory with background data latch caching during read operations
|Dec 28, 2009
|May 8, 2012
|Hynix Semiconductor Inc.
|Nonvolatile memory device and method of operating the same
|Jun 29, 2010
|Oct 16, 2012
|SK Hynix Inc.
|Method of programming nonvolatile memory device
|Dec 10, 2008
|Dec 11, 2012
|Sandisk Technologies Inc.
|Program control of a non-volatile memory
|Oct 6, 2011
|Jan 8, 2013
|SanDisk Technologies, Inc.
|Method for non-volatile memory with background data latch caching during read operations
|Dec 21, 2010
|Jun 25, 2013
|Sandisk Technologies Inc.
|Alternate page by page programming scheme
|May 1, 2012
|Jul 9, 2013
|Fusion-Io, Inc.
|Apparatus, system, and method for managing data in a solid-state storage device
|Jun 29, 2009
|Apr 22, 2014
|Marvell World Trade Ltd.
|Selectively accessing faster or slower multi-level cell memory
|Jun 15, 2009
|Jun 24, 2014
|Marvell International Ltd.
|Selectively scheduling memory accesses in parallel based on access speeds of memory
|Mar 15, 2013
|Jun 2, 2015
|SanDisk Technologies, Inc.
|Managing data reliability
|Mar 18, 2013
|Nov 8, 2016
|SK Hynix Inc.
|Nonvolatile memory apparatus, operating method thereof, and data processing system having the same
|Apr 21, 2014
|Jan 10, 2017
|Marvell World Trade Ltd.
|Selectively programming data in multi-level cell memory
|Jun 23, 2014
|Jan 17, 2017
|Marvell International Ltd.
|Selectively scheduling memory accesses in parallel based on access speeds of memory
|May 5, 2006
|Oct 19, 2006
|Yan Li
|Non-Volatile Memory with Background Data Latch Caching During Read Operations
|May 5, 2006
|Oct 26, 2006
|Yan Li
|Method for Non-Volatile Memory with Managed Execution of Cached Data
|May 5, 2006
|Jan 4, 2007
|Yan Li
|Non-Volatile Memory with Managed Execution of Cached Data
|Mar 19, 2008
|Sep 24, 2009
|Yan Li
|Different Combinations of Wordline Order and Look-Ahead Read to Improve Non-Volatile Memory Performance
|Jun 29, 2009
|Jan 21, 2010
|Xueshi Yang
|Selectively accessing memory
|Oct 27, 2009
|Feb 25, 2010
|Micron Technology, Inc.
|Program-verify method
|Dec 10, 2008
|Jun 10, 2010
|Shai Traister
|Program Control of a non-volatile memory
|Dec 28, 2009
|Aug 5, 2010
|Kyu Hee Lim
|Nonvolatile memory device and method of operating the same
|Jun 29, 2010
|Dec 30, 2010
|Hynix Semiconductor Inc.
|Method of programming nonvolatile memory device
|Mar 18, 2013
|Jun 12, 2014
|SK Hynix Inc.
|Nonvolatile memory apparatus, operating method thereof, and data processing system having the same
|U.S. Classification
|365/185.02, 365/185.03, 365/185.12, 365/185.17, 365/185.22
|International Classification
|Cooperative Classification
|European Classification
|Apr 27, 2011
|Fee payment
Year of fee payment: 4
|May 25, 2011
Owner name: SANDISK TECHNOLOGIES INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026339/0127
Effective date: 20110404
|May 20, 2015
|Fee payment
Year of fee payment: 8
|May 25, 2016
Owner name: SANDISK TECHNOLOGIES LLC, TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038809/0472
Effective date: 20160516


text:
- Doctors
- North Carolina
- Stoney Creek
- Family Doctors
- Dr. Graham S. Duncan
Ratings for Dr. Graham S. Duncan
There aren't enough superlatives to adequately describe Dr. Duncan. Unlike most primary care physicians who seem programmed for a 7-10 minute assembly line patient appointment, Dr. Duncan puts the patient first. He will spend as much time with his patients as necessary. He treats the whole person, not just your malady, complaint, or disease: Dr. Duncan is as concerned with his patient's emotional/relational/psychological well-being as their physical well-being. LaBauer Healthcare is very fortunate to have a doctor of his character and caliber on their staff!! He is down to earth, approachable, personable, attentive, caring, sincere, and, above all, genuine. Contrary to an earlier negative rating I read, Dr. Duncan is very responsive to patient needs and concerns; in fact, he has actually sent me several "hand written" letters in the past, and I have never experienced any difficulty whatsoever speaking with him directly. Five gold stars! Thank You, Dr. Duncan!!!
Dr. Graham Shaw Duncan is the "Best" Doctor I have seen in 30 years. He is The Ultimate and Complete Health Care Provider. Intelligent, Personable, Patient, Compassionate, Empathetic, and every other Positive Superlative you can name. I am a Professional Educator who grades, rates, and judges individual performances on a daily basis...Dr. Graham Shaw Duncan is at the Head of His Profession. Please disregard any Prank Negative Ratings of this Doctor. Please show your whole family you Love them and Seek this Doctor out!!! I give RateMDs.com permission to release my private contact information. Dr. Graham Shaw Duncan Heals the Whole Person in Mind, Body, and Spirit. Thank You Dr. Duncan!!! Our whole family Loves and Appreciates You!!!
Dr. Duncan is very attentive, patient and caring. He takes the time to answer any and all questions. The previous negative comment was most likely by a prank teeny-bopper. I can not believe, based on my personal experience , that he would ever ignore a concern from a patient. In addition, all practices use nurses to address initial issues from patients in follow-up, there is nothing wrong with that to weed out the minor issues from the more important. Dr. Duncan is now my family physician because I was so impressed with my visits with him.
Dr Duncan is extremely patient; he does not rush you and listens to what you say. I get very nervous when I do for a check-up and he put me at ease. He did not try to get me to run a million tests like many doctors do. I asked for a blood profile and received results by mail within a few days. I will definitely go back.
I have been dealing with symptoms of bipolar disorder for years and have never had a doctor want to help me as much as Dr. Duncan. He cares about helping people and is very willing to listen to your problems so he can help. We have had difficulties with meds and dosages but he kept at it until we finally found a combination that works so wonderfully. He never gave up hope that we would get to the spot I'm at now. He even has called to check up on me a few times which I think is incredibly awesome of him. I highly recommend Dr. Duncan!
Went to see him for a swimmer's ear infection. He prescribed a medication that irritated my ears- they felt like they were burning. I called 4 times to ask him to switch the medicine and he refused. He would not speak to me on the phone- instead had nurses do it. My ears hurt so bad I finally went to an urgent care facility where they told me my ear canals were bleeding they were so irritated. Dr. Duncan's advice was to "tough it out". Don't see him. He is very cold and dismissive. I'm lucky, my reaction could have been much worse. When I informed the office of my reaction- no response. Big suprise! Now I'm looking for a new doctor. Aviod at all costs!
Dr. Graham S. Duncan's Credentials
Facility Affiliations
Accepting New Patients
- North Carolina Medical School (Grad. 2005)
Other Specialties
Areas of Expertise
Awards & Recognitions
Publications & Research
Insurance accepted by this Doctor
Find a Doctor by Specialty
Featured News
Top Family Doctors / G.P.s
#1 of 1

subset: commoncrawl


text:
On December 15, 2004, Vneshtorgbank held an extraordinary general meeting of its shareholders.
Accepting motions made by shareholders, the General meeting elected a Supervisory Board and Auditing Commission of Vneshtorgbank.
The newly elected Supervisory Board now includes 9 members, namely:
|Aratsky Dmitry Borisovitch
|- Deputy Head of the Federal Agency for Management of Federal Property
|Dvorkovitch Arkady Vladimirovitch
|- Head of Experts` Directorate of the President of the Russian Federation
|Drozdov Anton Viktorovitch
|- Head of Economy and Finance Department of the Government of the Russian Federation
|Kostin Andrey Leonidovitch
|- Chairman of the Board and Chief Executive Officer of Vneshtorgbank
|Kudrin Alexei Leonidovitch
|- Minister of Finance of the Russian Federation
|Siluanov Anton Germanovitch
|- Head of Department of Inter-budgetary Relations
|Stortchak Sergey Anatolyevitch
|- Head of Department of International Financial Relations, Sovereign Debt and State Financial Assets of the Ministry of Finance of the Russian Federation
|Ulyukaev Alexei Valentinovitch
|- First Deputy Minister of Finance of the Russian Federation
|Sharonov Andrey Vladimirovitch
|- Deputy Minister of Economic Development and Trade of the Russian Federation
The Auditing Commission includes:
|Avdeeva Olga Anatolyevna
|- Chief Accountant
|Lukov Vladimir Valentinovitch
|- Deputy Director of Department of Fiscal Policy of the Ministry of Finance of the Russian Federation
|Rusakov Viktor Anatolyevitch
|- Deputy Head of Division of Financial Markets and Institutions Development of Corporate Governance Department of the Ministry of Economic Development and Trade of the Russian Federation
Also, a number of organizational issues were discussed at the extraordinary general meeting of Vneshtorgbank`s shareholders, as well as a number ofendments were approved to be made to the Bank`s Articles of Association reflecting a change in the registered address of the Bank, and to the Bank`s By-laws "On the Supervisory Board of Vneshtorgbank JSC" and "On the Management Board of Vneshtorgbank JSC".


text:
C.J. Wilson Leaves Packers to Sign with Oakland Raiders
Although the news is not going to qualify as earth shattering to Packer fans, it has been confirmed that that former Green Bay defensive lineman C.J. Wilson has come to terms with Oakland Raiders according to Tyler Dunne of the Milwaukee Journal-Sentinel.
Wilson, who was selected in the seventh round by the Packers in the 2010 NFL Draft, earned a spot on the team as a rotational player along the defensive line, where he was known specifically for his ability to stop the run.
The former East Carolina product saw the field right away as a rookie, playing in 15 games and starting two. In all, he totaled 12 tackles and one sack that season, the one sack coming against Brett Favre and the Vikings, when Favre made his second trip to Lambeau Field.
Wilson's best season came in 2012, when he started seven games, notched 15 tackles and two and a half sacks. In 2013, his role was greatly reduced and he ended up being active for only eight games and registered just five tackles.
The chances of the defensive end returning to Green Bay was always unlikely but became even less so when the Packers re-signed B.J. Raji and then signed former Vikings defensive tackle Letroy Guion, who was brought on because is his run-stopping capabilities.
However, Wilson has found a home with the Raiders and if can keep holding up well against the run, he should be able to find gainful employment in the league for years to come, it just won't be with in Green Bay where he was a part of a Super Bowl Championship team as well as three division championships.


text:
House Speaker Majority Leader D.J. Bettencourt (R-Salem) today released the following statement with regard to the passage of CACR 6, a constitutional amendment that would require that any tax increase or bonding would need to receive a vote of 3/5ths of both the House and Senate. This legislation will now move to the Senate, where, if it passes there, will appear on the November 2012 ballot.
"Today the NH House made it clear that any future decision on raising taxes and fees should rest with the voters of this state. This amendment is important to the future financial stability of New Hampshire. We have seen first hand over the last four years the damage that can been done to state, county and local governments when the legislature is allowed to tax and spend at will. This will insure that any increase in taxes and additional bonding will no longer be done by a simple majority. It is important that we give our citizens the opportunity to decide this issue at the polls in November of 2012."


text:
Bring Hayao Miyazaki's Castle in the Sky into your home with this hanging planter. The planter features features the details of the castle itself, but the top of the castle is yours to create.
It's also designed to hang instead of sitting somewhere in a garden or on a counter. This castle, like the one from the film, is made to live in the air.
The planter will sell for 4,000¥ (approx. $33 USD) in Japan later this month.
(via Rocket News)


text:
Cuttack: Deccan Chargers show its strength by beating Delhi Daredevils at Barabati Stadium of Orissa on Sunday.
A fine all-round display from Andrew Symonds inspired the Deccan Chargers to a 10-run victory over the Delhi Daredevils in Cuttack.
Deccan Chargers, electing to bat, scored 171 for six with significant contributions from the top order. Rohit Sharma was the highest scorer with 45 while Adam Gilchrist (24), Andrew Symonds (35), Herscehlle Gibbs (31) and Tirumalasetti Suman (29 not out) did their bit with the bat.
Deccan vs Delhi, 15th Match - Scorecard
After an explosive start from opener David Warner (57 off 33 balls), stand-in skipper Karthik slammed (46 off 27 balls) but failed to carry the team to win. Daredevils lost AB de Villiers (27) and David Warner (57) in quick succession after going smoothly in their run chase as they scored only 161 using the full quota of 20 overs.
Catch IPL on Set Max on TV, Youtube on net
Andrew Symonds adjudged as Man of the Match for his 3 wickets and a 24 ball 35 runs in this match.
IPL 2010: Fixture - Teams - Points - Orange-Purple


text:
by clicking the arrows at the side of the page, or by using the toolbar.
by clicking anywhere on the page.
by dragging the page around when zoomed in.
by clicking anywhere on the page when zoomed in.
web sites or send emails by clicking on hyperlinks.
Print Page
Email this page to a friend
Search this issue
Index - jump to page or section
Archive - view past issues
FLEXO Magazine : January 2008
. . . . BEGINNER FLEXOGRAPHER . Making Superior Plates Every Time By Malcolm G. Keif F lexo plates are a critical component of the printing system. Printing is a system-viewing platemaking in isolation doesn't address the total print process. A sys- tem has multiple components that interact with each other and influence the performance of each. Great plates with the wrong anilox rolls offer nothing to improve quality. Likewise, great plates made from a poorly prepared file help little to produce an outstanding final product. So, looking upstream and down- stream is necessary to ensure your plates are supporting the total printing system. Superior printing plates... · have sufficient resolution for the graphics to be repro- duced on the substrate for the job (paper, film, foil, etc). · are produced to optimize press and ink performance. · are made in a controlled and repeatable manner. Let's look at several important factors to making great plates. PLATE ROOM Quality in the plate room starts with the design of the plate room. If solvent processing is used, it is im- portant to exchange the air in the plate room several times per hour. This ensures a safe work- ing environment for the operators. Additionally, reducing dust is critical, which means having a filtration system and ideally a positive air sys- tem-air blows out of the plate room when the door is opened. Many plate rooms have tacky mats that are stepped on when entering the room to remove dust from shoes. The goal is to minimize dust as much as possible. Basic housecleaning is essen- tial to ensure pinhole-free plates. - PLATE MATERIAL A number of companies manufacture plate materials. Plate material generally comes in three forms: . Liquid for forming, then imaging, then mounting. . Sheet for imaging, then mounting. . Sleeve for imaging. Obviously, the more processing you perform in-house, the cheaper you can acquire the base polymer. However, forming plates or sleeves in a "clean-room" factory provides better re- sults than forming in a typical printing company. If starting from scratch, one of the first decisions in buy- ing sheet plates is which thickness to purchase. Plates come in various thicknesses and a balance is reached between buying extra polymer (thicker the plate, higher the cost) and having enough polymer for the various plate "reliefs" you may want to use. Plate relief is the difference between the plate surface and the floor that remains (film backing plus support polymer) after processing. Narrow-web printers usually use O.067-in. plates in the u.S. However, European narrow-web printers often - . ""' ,. JANUARY 2008 www.f I exog ra p hy.o rg FLEXO
December 2007
February 2008
Previous Page
Next Page


text:
Living With The Ache…
I've been waiting for the right time to come in which I would write an eloquent blog post about how I had figured out how to kick "the ache" in the dust and… Continue reading
I've been waiting for the right time to come in which I would write an eloquent blog post about how I had figured out how to kick "the ache" in the dust and… Continue reading
Story is what makes up our lives. Stories can be fascinating, thrilling, intriguing, dull, beautiful, inspiring, scary, invigorating, soothing. The difference between my story and the world's story is that mine is eternal.… Continue reading
A month ago, for the very last time, we walked down the very familiar three flights of stairs from the apartment building we lived in as a family of six for eighteen months. It… Continue reading
Nearly every night as I tuck my children into bed, I place my hands on theirs and pray that they would know how great God's love is for them. It is a… Continue reading
Friendship is, indeed, a precious gift to behold. It is also something that, to many, can hold memories of pain, scars and failed expectations. I can think back to my childhood and… Continue reading
Several months ago I heard a sermon that the Spirit used to stir within me in a most beautiful way. Through a deep humility and passion, the pastor spoke of the power… Continue reading
Hi! My name is Ashtyn Figgins and I'm twelve years old. My mom asked me if I would like to write a guest post on her blog, so here it is!… Continue reading
This past year has been one of beauty and challenge for us as we've lived as a family of 6 in a 3rd story, 1,200 square foot apartment. As we prepare to move… Continue reading
"The land that you are to take possession of is a land of mountains and valleys that drinks rain from heaven. It is a land your God cares for; the eyes of the… Continue reading
One great thing about where we live is that we are 2 hours from the beach and 2 hours from the mountains. It was such a joy to get up to the cooler… Continue reading


text: Woolen Mittens Showing 1 - 3 of Total 3 Manufacturers/ Suppliers Newwestern Handicraft Industrie Send Trade Enquiry BUSINESS PROFILE Nature of Business: ExporterProducts Offered: Exporter of all types of woollen items such as jackets, fleece, gloves, mittens, shawl, puncho etc. CONTACT DETAILS Street Address: Sorakhutte-16, Ktmnepal City: Kathmandu PIN: 97701 Country: NepalPhone: +(977)-(1)-9851027169 Send Trade Enquiry Now Kanodia Hosiery Mills (P) Ltd. Send Trade Enquiry BUSINESS PROFILE Nature of Business: ManufacturerProducts Offered: Manufacturers and exporters of knitted products like knitted garments, knitted home furnishings, knitted accessories, knitted pet products, knitted pullovers, sweaters, knitted tops, cushion covers, stoles, shawls, dog coats, dog shoes. CONTACT DETAILS Street Address: B-14/2 Okhla Industrial Area, Phase - II City: New Delhi PIN: 110 020 State: Delhi Country: IndiaPhone: +(91)-(11)-41709732/33/34/41705020/21/22 Fax: +(91)-(11)-26385754 Send Trade Enquiry Now Perko Trading Co. Send Trade Enquiry BUSINESS PROFILE Nature of Business: ManufacturerProducts Offered: Manufacturers and exporters of different types of hats, caps, scarves and mittens for ladies, men and children. CONTACT DETAILS Street Address: Rm 840, Nan Fung Commercial Centre, 264 Castle Peak Road, Ts uen Wan, N.T. City: Hong Kong Country: China (Hong Kong S.A.R.)Phone: +(852)-(852)-24111621 Fax: +(852)-(852)-24136158 Send Trade Enquiry Now


text:
Results 1 - 7 of 7 matches
Rids your system of unwanted hum safely .
It displays the exact wiring of any cable or adapter " even allows testing of installed cables inside walls.
Quick and easy hum elimination.
A quick and easy way to eliminate AC hum and noise.
Our product catalog varies by country due to manufacturer restrictions. If you change the Ship-To country, some or all of the items in your cart may not ship to the new destination.


text:
Saturday, March 5, 2011
Out in the Wild
Posted by Tracey at 8:13 AM
6 comments:
- Shirley said...
Have a wonderful day!
- March 5, 2011 at 10:45 AM
- Paint Girl said...
I wish I could be out there too! One of these days!
- March 5, 2011 at 11:21 AM
- Donna Gunn said...
What a great way to spend the day.
- March 5, 2011 at 1:23 PM
- Cheyenne said...
Standin` watchin`, no particular place to be. Thats cool.
- March 5, 2011 at 10:15 PM
- Jessie Walling said...
Oh. Yes. So would I! I was down on the Yakama reservation yesterday checking out their horses. I want to go back, not sit here in my apartment studying!!
- March 6, 2011 at 9:20 AM
- Rising Rainbow said...
Comicon, really?? So glad it was you and not me. LOL I do sympathize, however, I end up places I would rather not be too.
- March 7, 2011 at 4:36 PM
Subscribe to: Post Comments (Atom)


text:
Young Monalisa Houseboat
Call us 1800-300-2400-1 (Toll Free) and Get additional Discount upto 50% for this Hotel.
Per Room Per Night
Lowest Price Guarantee
You are getting lowest possible rate for this hotel
- About Hotel
- Reviews
Select Room
About Young Monalisa Houseboat
Plan your stay at Young Monalisa Houseboat in Srinagar and set your mood for a pleasant vacation trip. Experience the picturesque beauty of the lakes reclining in the well-furnished rooms. The houseboat offers amenities like room service, boating, housekeeping and many more. There are 7 clean and spacious rooms.
No of floors: 0 | No of rooms: 7
Checkin Time: 1200 pm
Checkout Time: 1200 pm
Hotel Information and Amenities
Read More....
Hotel Amenities
- Housekeeping
- Suitable For Children
- Room Service
- Boating
- H/C Running Water
- Reading Lamps
- Television-Room
- Attached Bathroom
- "Bottle Opener
- Makeup Mirror
- Refrigerator-Room
- Sofabed
- Cooking Facilities (stove Etc.)
Hotel Location


text:
Malankara Orthodox - Wedding Songs MP3
Malankara Orthodox Wedding Songs.
Malankara Wedding Songs MP3
Best New Ethiopian Orthodox mezmur 2016 Nonstop VoL 1 MP3
Best New Ethiopian Orthodox mezmur 2016 Nonstop VoL 1 Best New Ethiopian Orthodox tewahedo mezmur 2016.
Aadima neethinjare orthodox christian wedding song malayalam MP3
Vivahakoodasha ganangal sruthi school of music well,i knw the vid is nt upto scratch,and trans is lousy..bt however good i translate,it wont have the original ...
Pathivrathayam malayalam christian beautiful wedding song download link MP3
download link http://www.mediafire.com/?6a9sg44knhha5gr please join at https://www.facebook.com/yesuvinnamam.
Orthodox Christian Wedding Song- Malayalam MP3
Jesus says in Mark 10 "It was because your hearts were hard that Moses wrote you this law," Jesus replied. "But at the beginning of creation God made them ...
Bangalore Days || Maangalyam Wedding Song DQ,Nivin&Nazriya MP3
Subscribe us http://goo.gl/qdQIPG Like Us On facebook https://www.facebook.com/MC.MovieChannel Follow us on Twitter https://twitter.com/mcmoviechannel ...
Indian Orthodox Church Wedding Song,Dhanyan Vin M MP3
jacobite malayalam wedding songs MP3
malayalam jacobite wedding song.
Magnificent russian orthodox song MP3
Russian chant.
Vaneennudayon Kaiyyal വാനീന്നുടയോന് കൈയ്യാല് MP3
Vaneennudayon Kaiyyal വാനീന്നുടയോന് കൈയ്യാല് സുറിയാനി സഭയുടെ വിവാഹ കൂദാശ By Fr. M P George &...
Malankara Orthodox Qurbana Songs - SRUTHI MP3
Malankara Orthodox Qurbana Songs - SRUTHI.
Original Big surprise for Bride and Groom...Chris and Leah Wedding 5 April 2014 MP3
Original A big surprise for newly married couple Chris and Leah O'Kane... To use this video in a commercial player, advertising or in broadcasts, please email ...
Malankara Orthodox Qurbana Prayers and songs MP3
Please visit my blog : http://endedhaivam.blogspot.in/ for more videos and posts Vist my channel : https://www.youtube.com/Endedhaivam for more christian ...
New Ethiopian Orthodox wedding mezmur_ Hamelmal ሐመልማል ወርቅ MP3
Angelic voices russian orthodox song MP3
Russian chant.
Malankara Orthodox - Morning Prayer / Prabhatha Namaskaram MP3
Full Malankara Orthodox Morning Prayer.
Malankara Orthodox Morning Prayer Songs - Sleeba Namaskaram MP3
Malankara Orthodox Morning Prayer Songs - Sleeba Namaskaram.
Shira Choir Sings New Song At Bar Mitzvah - מקהלת שירה מבצעת את השיר החדש ׳אם השם לא יבנה בית MP3
To use this video in a commercial player or in broadcasts, please email [email protected] for more info Shira Choir Sings New Song "Im Hashem Lo ...
Orthodox Kurbana Song Yachikandum Samayamitha Suriyani Song MP3
Holy Qurbono (Holy Qurbana) The word "Qurbana" has different meanings like offering, gift, oblation, sacrifice, presents etc. The word took its origin from the ...


text:
Kiwanis of Cape May Court House
Cape May Winery is located at 711 Town Bank Rd. Cape May, NJ 08204.
Kiwanis International was founded in 1915 to assist local children in having a richer and fuller life. Currently, Kiwanis clubs are located in many countries benefiting children everywhere. The Kiwanis Club of Cape May Court House chapter has been raising money and donating to local children since 1945. Last year, we started a Wine Gala as a main fundraiser and with continuing efforts have increased our scholarship awards, sent a terminally ill child to Florida, donated funds to children throughout Cape May County, assisted our Key Club financially in their endeavours to give back to the community and participated in Kiwanis One Day by completing light renovations to two families in need. All of this was possible because of the Wine Gala. We are asking if you would be willing to buy a ticket for $65.00 or make a donation to our silent auction table. We really appreciate your help!


text:
USF Art In Health
In partnership with USF Health, USF Contemporary Art Museum's Art In Health program explores intersections between the arts and healthcare. Among initiatives are two ongoing projects: The Art of Attending, a series of observation training workshops for health students taught by arts instructors, and Arts at the Clinic, a weekly art-making group for aphasia patients, caregivers and therapists facilitated by an artist/faculty and art student interns.
The Art of Attending
Museum Workshop
Movement Workshop
Studio Art Workshop
Listening Workshop
Research shows that training health practitioners in arts skills improves visual awareness. Practice observation, communication and critical thinking skills with other USF students in health disciplines at the USF Contemporary Art Museum and campus arts studios. Each workshop includes a series of arts based activities and a concluding discussion with a USF Health faculty member. Visiting faculty members include Dr. David Ecker, Morsani College of Medicine, Dr. Cheryl Zambroski, College of Nursing, and Dr. Aurora Sanchez-Anguiano, College of Public Health.
Additional participation in a research study on learning outcomes from the workshops is optional and entails the completion of two online or paper surveys. The purpose of the research is to assess the impact of the workshops on students' observation skills. IRB study #16778.
Shannon Annis (Museum) is Exhibitions Manager/Registrar at the USF Contemporary Art Museum. In addition to caring for the USF art collection and traveling exhibitions, she has co-curated exhibitions and developed associated programs and events. She has experience in art museum and health care settings and holds an MA in Art History from USF, an MS in Speech-Language Pathology from the University of North Carolina at Chapel Hill and an MA in Medical/Clinical Psychology from UAB.
Dolores Coe (Studio Art) is an artist, educator and former Professor of Art and Program Director at Ringling College of Art and Design. Her paintings and mixed media works are exhibited regionally and nationally in museums and galleries and included in a number of public, private and corporate collections. She was awarded a resident fellowship at the Rijksakademie in Amsterdam and a 2010 State of Florida Individual Artist Fellowship in Painting. She earned the MFA in Painting and an MA in Counseling. For more information, go to http://dolorescoe.com.
Bruce Marsh (Studio Art) is a Professor Emeritus with the USF School of Art and Art History and a painter pursuing a career involving representational painting. He has exhibited widely and produced a number of large-scale public art projects. During the past three years, he has been deeply involved in the development and operation of the new Firehouse Cultural Center in Ruskin, Florida. His painting, teaching, and community activities have been motivated by his interest in perception, communication and representation, and by his faith in the unlimited possibilities of the human mind and spirit. Visit http://brucemarsh.wordpress.com to view recent paintings by Bruce Marsh.
Merry Lynn Morris (Movement) holds an MFA in dance performance and choreography from Florida State University. She seeks out interdisciplinary teaching and research opportunities in which her movement background and expertise can be utilized and expanded. Her dance/mobility chair project [http://rdc.arts.usf.edu] involves approaching wheelchair design from a dance performance perspective to increase options for differently-abled individuals and expand perceptions regarding human mobility. She frequently collaborates across disciplines including art and video, architecture, music, engineering and physical therapy, and is pursuing a doctoral degree in dance and disability studies at Texas Womans University.
Paul Reller (Listening), Associate Professor of Music, is a part of the Composition Department and serves as Director of USF's SYCOM (Systems Complex for the Recording and Performing Arts) Electronic Music Studio. Reller teaches electronic music, acoustic composition, and the History of Blues and Rock Music. Reller helped create the Bonk Festival of New Music, and his work has been performed at the Festival by Margaret Lancaster, Conrad Harris, Hilton Jones, and the USF Percussion Ensemble. Reller received a BM from the University of Minnesota and a Masters at the Eastman School of Music.
Art In Health @ USF was established in Fall 2012 as a partnership between the USF Contemporary Art Museum and USF Health to develop arts-based observation training for USF Health graduate students. The program drew inspiration from existing arts-and-medicine initiatives at Harvard University, Yale University, the University of Miami and other institutions and has developed into a multi-modal series that integrates arts based components in museum, visual studio, movement and listening.
Art in Health Internships
Art In Health expanded in 2013 to include a project that engages students from the School of Art and Art History to work as artist practitioners in a healthcare environment in cooperation with the USF Department of Communication Sciences and Disorders. For more information on Arts@the Clinic Programming and to apply for internships or graduate projects, contact Dolores Coe, USF Art In Health Program Curator, at email@example.com.
Art in Health Blog
Art in Health on Facebook
Student Feedback
What did you learn?
(Spring 2014)
I learned to be more perceptive of my surroundings. I became more aware of my own thoughts, movements and emotional response to different stimuli. I believe I will be more pensive and think more critically when approaching new situations and observing others. I will be more conscientious in how I carry myself, how others carry themselves and appropriate situations to adapt my energy and perspective.
In the art studio, I learned to look at things from different perspectives and assimilate whole things from pieces. In the [museum] workshop, I learned to interpret things objectively and express feelings associated with observation. In the movement workshop, I learned to use the control of my body to regulate my behavior or emotion.
The most important skills relate to leadership, especially the role of moderating in the art workshop. Other skills include abstract thinking, teamwork, appreciating the thoughts and views of other people."
Increased observation skillsreally looking for visual clues and details, not just big picture stuff. Not to rush in judging a situation/scene/person, careful deliberation, observation of verbal and non-verbal messages. Facilitation skillsparticularly important when I enter an unknown culture and community with the goal of helping to promote their health. Feeling comfortable with being uncomfortable in some situations.
Copyright and Reproduction
The electronic images available on this site are subject to copyright and may be covered by other restrictions as well. The images are made available to the general public for the sole purpose of representing the USF Contemporary Art Museums programs and collection. Copying or redistribution of the images in any manner without the express written permission of the University of South Florida Institute for Research in Art is strictly prohibited.


text:
Regional Events
Regional Events
The Alumni Association hosts alumni gatherings in cities throughout the United States each year. These events are a great way to meet other St. Bede alumni in your area and catch up on the latest news from Saint Bede Academy, not able to make it back to St. Bede for a visit or to attend Homecoming? St. Bede will be hitting the road to bring alumni, parents, and friends together at regional gatherings throughout the year. Keep checking back for the schedule and invitations.
To find out where the Alumni Association is headed next, see the regional events listed below.
Interested in hosting an event at a restaurant or space near you or at your home? Contact Julia Yaklich or call 815-250-0359
Click here to see pictures from some of our recent regional events.
Upcoming Events
St. Bede will continue to travel across the country. We hope you can stop by and join us to meet Abbot Philip and other representatives from the School, hear what's happening on campus, meet others in the Saint Bede family, and share what's been happening with you. Come to one, or come to several. We'd love to see you.
Some venues have been set, while others are still in the planning stages. Nonetheless, we wanted you to know what's on deck. If you are able to host or help coordinate any of these events, please contact Julia Yaklich or call at 815-250-0359. We look forward to seeing you soon.
Houston, Texas
Description: Check back for more details soon
Date: Saturday, October 29, 2016, 3:00 p.m.- 6:00 p.m.
Location: The Bayne Residence
14423 Tivoli Drive
Houston, TX 77077
Host: Kenneth Bayne '76
Contact: Julia Yaklich
Dallas, Texas:
Description: Check back for more details soon
Date: Sunday, October 30, 2016, 3:00 p.m. - 5:00 p.m.
Location: Las Colinas Country Club
4400 North O'Connor Road
Irving, TX 75062-2796
Contact: Julia Yaklich
Recent Regional Events
Denver, Colorado
Description: John Levisay '85 and CEO of Craftsy hosted our Regional Event at his company in Denver, Colorado. Over 40 of our St. Bede family got together to hear more about John's company www.craftsy.com chat about their time at St. Bede and catch up on all the news at St. Bede Thank you John for hosting this event.
Date: Friday, August 5, 2016
Location: Craftsy www.craftsy.com
Host: John Levisay '85, CEO of Craftsy


text:
In a video segment done on the O'Reilly Factor, New Jersey voters were asked by correspondent Jesse Watters along the Jersey boardwalk who they were voting for. Many said Donald Trump, with humorous explanations. Those who said Bernie Sanders tended to give muddled or contradicting explanations. There were relatively no voters who said Hillary Clinton.
You can watch the great video clip right here:


text:
autumn, blogger, blogging, landscape, landscapephotography, nature, photo, photographer, photography, photography blog, photographyblogger, scenery, summer, sunset, toronto, torontophotographer, travelling, wordpress, yyz
Hi everyone,
I'm back again with another photography post! I've been working very hard, studying photography to improve my art. I've put together this post to show some of my recent work. I hope you all enjoy these photos!
I hope you all enjoyed these photos, let me know which one stood out to you.
Thanks for reading and see you soon!


text:
Programming note: Catch Raiders RB Darren McFadden and WR Denarius Moore on Chronicle Live tonight at 9:30 p.m. on Comcast SportsNet Bay Area!
NAPA -- The legal cases of receiver Darrius Heyward-Bey, who pleaded no contest to a DUI charge on the Bay Bridge this offseason, and middle linebacker Rolando McClain, who was convicted on counts of third-degree assault, menacing, discharging a handgun in city limits and reckless endangerment, may be settled in courts of law, but their immediate playing future in the NFL is still fuzzy.
RELATED: No contest DUI plea for Heyward-Bey
NFL spokesman Greg Aiello said the two are still "under review." Reading into that, suspensions handed down by commissioner Roger Goodell could potentially still be coming for the two Raiders players, even as McClain's case is under appeal in Alabama.Raiders general manager Reggie McKenzie, meanwhile, said in June that McClain was essentially given a clean slate by the team.


text:
A Better Camera Unlocked v3.45 APK Available !
A Better Camera Unlocked
Forget about having dozens of camera apps. A Better Camera does everything you need.
- All-purpose, full featured camera for Android:
- HDR+ photo and video
- Panorama
- Multishot: Group portrait, Sequence shot, unwanted moving objects removal
- Night mode
- Video recording + pause
- Time lapse (video and photo)
- Pre-shot: negative shutter lag
- Burst and Expo-bracketing
- Self timer
- RAW capture (depends on device)
- Timestamps
- Manual controls (focus and shutter speed priority)
- full access to all Camera features
What's New
- Sony Xperia Z5 max resolution added
- thumbnail update when saving to sd card fixed
- DRO and Super modes improved
- many stability fixes


text:
Discovery Communications, Inc., DISCA is in the exchange NASDAQ and its industry is CATV Systems in the sector of Services. Based in USA, Discovery Communications, Inc., DISCA has a market cap of 10630.93. Since its IPO date on the 7/8/2005, Discovery Communications, Inc., DISCA performance year to date is 2.70%. Today Discovery Communications, Inc., DISCA has gained 0.04%, with a current price of 27.4.
Ownership of the company is 0.50% for insider ownership while institutional ownership is *TBA. The management of the company have seen the company have a payout ratio of 0.00%. Return of assets are at 4.90%, with return on investment at 11.20%.
In terms of debt levels and profit levels, Discovery Communications, Inc., DISCA is seeing a long-term debt/equity of 1.46. While Total debt/equity is 1.49. With a profit margin of 11.90%, this is combined with a gross margin of 62.80%, and operating margin of 31.20%. Discovery Communications, Inc. ability to meet debt levels, with a current ratio of 1.8, while the quick ratio is 1.8.
For the last year Discovery Communications, Inc., DISCA has seen a EPS growth of -4.80%. A performance for the year of 1.93%. The 52-week high is -13.84%, and the 52-week low is 15.81%. The average volume for Discovery Communications, Inc., DISCA is 3368100.
With a target price of 29.09, can Discovery Communications, Inc., DISCA reach this target? Looking at the value indicators of Discovery Communications, Inc., DISCA. Discovery Communications, Inc. has a P/E of 14.86 and a forward P/E of 12.32. Perhaps the more useful indicator than P/E, is PEG which has a value of 0.95. Discovery Communications, Inc. also has a P/S and a P/B of 1.64 and 2.07 respectively. For P/cash, Discovery Communications, Inc. has a value of 57.46, while it is 9.01 for P/free cash flow.
At the current price of 27.4, Discovery Communications, Inc. has a dividend yield of *TBA. We see a return on equity of 14.20%.
Looking more long-term Discovery Communications, Inc., is projected to get an EPS growth for the next five years of 15.70%. In the short-term an EPS growth of 12.78% in the next year is forecasted. This is after a EPS growth of -4.80% for this year and for the last five years a 1.00% growth has been seen.


text:
History of the club part Two:
The maddness continues
Minsk Madness 4 Gatherning #028
25 May 2002
Minsk Madness 5 Wave Rave Gathering #031
17 May 2003
The party was a massive success. More than 700 people made it down to the Wave Club for the biggest Minsk Club party to date. Many thanks to the bands (Irriflexible, Halley, West Lake Boyz, Kaboos, Bu-Mu-Light, The Offensive). An excellent live set was followed up by sound tunes from DJ Kong Anh and DJK.
A little punk rock anyone?
Thac Da Rally Minsk Olympics#1 gathering #032
14/15 June 2003
This summer's ultimate back-to-nature cruise brought to you by the Minsk Club Vietnam.
The weekend was great fun and all who compeated in the Oylmpics were rewarded with lots of cold beer. The first Prizewent to Mr VTV Vinh who completed the course in the slowest time.
Khau Vai H'mong Love Market Gathering #033
17 May 2004
For those of you who missed it, Club Gathering #00033 was at the Khau Vai Love Market, near Meo Vac in Ha Giang District; an annual market which takes place on the 27th of the third lunar month. Some 25 riders made the long trek to Vietnam's northernmost province and drove down the skid-pan track to Khau Vai where we were greeted with flammable corn liquors. see below!!!!
Thac Da rally Minsk Olympics 2 Gathering #035
10/11 July 2004
Minsk Olympics Piston Cup 2004
Produced by DigbyMinsk
Minsk Club Olympics Comrade Challenge 2004
Produced by DigbyMinsk


text:
What is it?
- My project is an animation
- I made something that explains what cohort Im in
Why did you make it?
- I made it because I've always wanted to see how to make an animation on scratch
- I wanted to see if I could make one
What challenges did you face?
- I had a really hard time with making things pop up
- Moving through the project, I found that i needed a lot of help
How did you overcome any problems?
- The solution was to work a lot harder
- I was able to find a workaround by changing a lot of things
What did you like/dislike about the project?
- I really liked how it turned out
- I didn't like that how short it is
What would you do differently?
- If I did this again, I would make it lounger
- Next project, I would add more detail