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Multi-state Flash EEprom system on a card that includes defective cell substitution
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
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This invention relates generally to semiconductor electrically erasable programmable read only memories (EEprom), and specifically to a system of integrated circuit Flash EEprom chips.
Computer systems typically use magnetic disk drives for mass storage of data. However, disk drives are disadvantageous in that they are bulky and in their requirement for high precision moving mechanical parts. Consequently they are not rugged and are prone to reliability problems, as well as consuming significant amounts of power. Solid state memory devices such as DRAM's and SRAM's do not suffer from these disadvantages. However, they are much more expensive, and require constant power to maintain their memory (volatile) Consequently, they are typically used as temporary storage.
EEprom's and Flash EEprom's are also solid state memory devices. Moreover, they are non-volatile, and retain their memory even after power is shut down. However, conventional Flash EEprom's have a limited lifetime in terms of the number of write (or program)/erase cycles they can endure. Typically the devices are rendered- unreliable after 10.sup.2 to 10.sup.3 write/erase cycles. Traditionally, they are typically used in applications where semi-permanent storage of data or program is required but with a limited need for reprogramming.
Accordingly, it is an object of the present invention to provide a Flash EEprom memory system with enhanced performance and which remains reliable after enduring a large number of write/erase cycles.
It is another object of the present invention to provide an improved Flash EEprom system which can serve as non-volatile memory in a computer system.
It is another object of the present invention to provide an improved Flash EEprom system that can replace magnetic disk storage devices -in computer systems.
It is another object of the present invention to provide a Flash EEprom system with improved erase operation.
It is another object of the present invention to provide a Flash EEprom system with improved error correction.
It is yet another object of the present invention to provide a Flash EEprom with improved write operation that minimizes stress to the Flash EEprom device.
It is still another object of the present invention to provide a Flash EEprom system with enhanced write operation.SUMMARY OF THE INVENTION
These and additional objects are accomplished by improvements in the architecture of a system of EEprom chips, and the circuits and techniques therein.
According to one aspect of the present invention, an array of Flash EEprom cells on a chip is organized into sectors such that all cells within each sector are erasable at once. A Flash EEprom memory system comprises one or more Flash EEprom chips under the control of a controller. The invention allows any combination of sectors among the chips to be selected and then erased simultaneously. This is faster and more efficient than prior art schemes where all the sectors must be erased every time or only one sector at a time can be erased. The invention further allows any combination of sectors selected for erase to be deselected and prevented from further erasing during the erase operation. This feature is important for stopping those sectors that are first to be erased correctly to the "erased" state from over erasing, thereby preventing unnecessary stress to the Flash EEprom device. The invention also allows a global de-select of all sectors in the system so that no sectors are selected for erase. This global reset can quickly put the system back to its initial state ready for selecting the next combination of sectors for erase. Another feature of the invention is that the selection is independent of the chip select signal which enables a particular chip for read or write operation. Therefore it is possible to perform an erase operation on some of the Flash EEprom chips and write operations may be performed on other chips not involved in the erase operation.
According to another aspect of the invention, improved error correction circuits and techniques are used to correct for errors arising from defective Flash EEprom memory cells. One feature of the invention allows defect mapping at cell level in which a defective cell is replaced by a substitute cell from the same sector. The defect pointer which connects the address of the defective cell to that of the substitute cell is stored in a defect map. Every time the defective cell is accessed, its bad data is replaced by the good data from the substitute cell.
Another feature of the invention allows defect mapping at the sector level. When the number of defective cells in a sector exceeds a predetermined number, the sector containing the defective cells is replaced by a substitute sector.
An important feature of the invention allows defective cells or defective sectors to be remapped as soon as they are detected thereby enabling error correction codes to adequately rectify the relatively few errors that may crop up in the system.
According to yet another aspect of the present invention, a write cache is used to minimize the number of writes to the Flash EEprom memory. In this way the Flash EEprom memory will be subject to fewer stress inducing write/erase cycles, thereby retarding its aging. The most active data files are written to the cache memory instead of the Flash EEprom memory. Only when the activity levels have reduced to a predetermined level are the data files written from the cache memory to the Flash EEprom memory. Another advantage of the invention is the increase in write throughput by virtue of the faster cache memory.
According to yet another aspect of the present invention, one or more printed circuit cards are provided which contain controller and EEprom circuit chips for use in a computer system memory for long term, non-volatile storage, in place of a hard disk system, and which incorporate various of the other aspects of this invention alone and in combination.
Additional objects, features, and advantages of the present invention will be understood from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a general micrprocessor system including the Flash EEprom memory system of the present invention;
FIG. 1B is schematic block diagram illustrating a system including a number of Flash EEprom memory chips and a controller chip;
FIG. 2 is a schematic illustration of a system of Flash EEprom chips, among which memory sectors are selected to be erased;
FIG. 3A is a block diagram circuit on a Flask EEprom chip for implementing selective multiple sector erase according to the preferred embodiment;
FIG. 3B shows details of a typical register used to select a sector for erase as shown in FIG. 2A;
FIGS. 4(1)-4(11) is a flow diagram illustrating the erase sequence of selective multiple sector erase;
FIG. 5 is a schematic illustration showing the partitioning of a Flash EEprom sector into-a data area and a spare redundant area;
FIG. 6 is a circuit block diagram illustrating the data path control during read operation using the defect mapping scheme of the preferred embodiment;
FIG. 7 is a circuit block diagram illustrating the data path control during the write operation using the defect mapping scheme of the preferred embodiment;
FIG. 8 is a block diagram illustrating the write cache circuit inside the controller.DESCRIPTION OF THE PREFERRED EMBODIMENTS
EEprom System
A computer system in which the various aspects of the present invention are incorporated is illustrated generally in FIG. 1A. A typical computer system architecture includes a microprocessor 21 connected to a system bus 23, along with random access, main system memory 25, and at least one or more input-output devices 27, such as a keyboard, monitor, modem, and the like. Another main-computer system component that is connected to a typical computer system bus 23 is a large amount of long-term, non-volatile memory 29. Typically, such a memory is a disk drive with a capacity of tens of megabytes of data storage. This data is retrieved into the system volatile memory 25 for use in current processing, and can be easily supplemented, changed or altered.
One aspect of the present invention is the substitution of a specific type of semiconductor memory systems for the disk drive but without having to sacrifice non-volatility, ease of erasing and rewriting data into the memory, speed of access, low cost and reliability. This is accomplished by employing an array of electrically erasable programmable read only memories (EEprom's) integrated circuit chips. This type of memory has additional advantages of requiring less power to operate, and of being lighter in weight than a hard disk drive magnetic media memory, thereby being especially suited for battery operated portable computers.
The bulk storage memory 29 is constructed of a memory controller 31, connected to the computer system bus 23, and an array 33 of EEprom integrated circuit chips. Data and instructions are communicated from the controller 31 to the EEprom array 33 primarily over a serial data line 35. Similarly, data and status signals are communicated from the EEprom 33 to the controller 31 over serial data lines 37. Other control and status circuits between the controller 31 and the EEprom array 33 are not shown in FIG. 1A.
Referring to FIG. 1B, the controller 31 is preferably formed primarily on a single integrated circuit chip. It is connected to the system address and data bus 39, part of the system bus 33, as well as being connected to system control lines 41, which include interrupt, read, write and other usual computer system control lines.
The EEprom array 33 includes a number of EEprom integrated circuit chips 43, 45, 47, etc. Each includes a respective chip select and enable line 49, 51 and 53 from interface circuits 40. The interface circuits 40 also act to interface between the serial data lines 35, 37 and a circuit 55. Memory location addresses and data being written into or read from the EEprom chips 43, 45, 47, etc. are communicated from a bus 55, through logic and register circuits 57 and by another bus 59 to each of the memory chips 43, 45, 47 etc.
The bulk storage memory 29 of FIGS. 1A and 1B can be implemented on a single printed circuit card for moderate memory sizes. The various lines of the system buses 39 and 41 of FIG. 1B are terminated in connecting pins of such a card for connection with the rest of the computer system through a connector. Also connected to the card and its components are various standard power supply voltages (not shown).
For large amounts of memory, that which is conveniently provided by a single array 33 may not be enough. In such a case, additional EEprom arrays can be connected to the serial data lines 35 and 37 of the controller chip 31, as indicated in FIG. 1B. This is preferably all done on a single printed circuit card but if space is not sufficient to do this, then one or more EEprom arrays may be implemented on a second printed circuit card that is physically mounted onto the first and connected to a common controller chip 31.
Erase of Memory Structures
In system designs that store data in files or blocks the data will need to be periodically updated with revised or new information. It may also be desirable to overwrite some no longer needed information, in order to accommodate additional information. In a Flash EEprom memory, the memory cells must first be erased before information is placed in 7 them. That is, a write (or program) operation is always preceded by an erase operation.
In conventional Flash erase memory devices, the erase operation is done in one of several ways. For example, in some devices such as the Intel corporation's model-27F-256 CMOS Flash EEprom, the entire chip is erased at one time. If not all the information in the chip is to be erased, the information must first be temporarily saved, and is usually written into another memory (typically RAM). The information is then restored into the nonvolatile Flash erase memory by programming back into the device. This is very slow and requires extra memory as holding space.
In other devices such as Seeq Technology Incorporated's model 48512 Flash EEprom chip, the memory is divided into blocks (or sectors) that are each separately erasable, but only one at a time. By selecting the desired sector and going through the erase sequence the designated area is erased. While, the need for temporary memory is reduced, erase in various areas of the memory still requires a time consuming sequential approach.
In the present invention, the Flash EEprom memory is divided into sectors where all cells within each sector are erasable together. Each sector can be addressed separately and selected for erase. One important feature is the ability to select any combination of sectors for erase together. This will allow for a much faster system erase than by doing each one independently as in prior art.
FIG. 2 illustrates schematically selected multiple sectors for erase. A Flash EEprom system includes one or more Flash EEprom chips such as 201, 203, 205. They are in communication with a controller 31 through lines 209. Typically, the controller 31 is itself in communication with a microprocessor system (not shown). The memory in each Flash EEprom chip is partitioned into sectors where all memory cells within a sector are erasable together. For example, each sector may have 512 byte (i.e. 512.times.8 cells) available to the user, and a chip may have 1024 sectors. Each sector is individually addressable, and may be selected, such as sectors 211, 213, 215, 217 in a multiple sector erase. As illustrated in FIG. 2, the selected sectors may be confined to one EEprom chip or be distributed among several chips in a system. The sectors that were selected will all be erased together. This capability will allow the memory and system of the present invention to operate much faster than the prior art architectures.
FIG. 3A illustrates a block diagram circuit 220 on a Flash EEprom chip (such as the chip 201 of FIG. 2) with which one or more sectors such as 211, 213 are selected (or deselected) for erase. Essentially, each sector such as 211, 213 is selected or tagged by setting the state of an erase enable register such as 221, 223 associated with the respective sectors. The selection and subsequent erase operations are performed under the control of the controller 31 (see FIG. 2). The circuit 220 is in communication with the controller 31 through lines 209. Command information from the controller is captured in the circuit 220 by a command register 225 through a serial interface 227. It is then decoded by a command decoder 229 which outputs various control signals. Similarly, address information is captured by an address register 231 and is decoded by an address decoder 233.
For example, in order to select the sector 211 for erase, the controller sends the address of the sector 211 to the circuit 220. The address is decoded in line 235 and is used in combination with a set erase enable signal in bus 237 to set an output 239 of the register 221 to HIGH. This enables the sector 211 in a subsequent erase operation. Similarly, if the sector 213 is also desired to be erased, its associated register 223 may be set HIGH.
FIG. 3B shows the structure of the register such as 221, 223 in more detail. The erase enable register 221 is a SET/RESET latch. Its set input 241 is obtained from the set erase enable signal in bus 237 gated by the address decode in line 235. Similarly, the reset input 243 is obtained from the clear erase enable signal in bus 237 gated by the address decode in line 235. In this way, when the set erase enable signal or the clear erase enable signal is issued to all the sectors, the signal is effective only on the sector that is being addressed.
After all sectors intended for erase have been selected, the controller then issues to the circuit 220, as well as all other chips in the system a global erase command in line 251 along with the high voltage for erasing in line 209. The device will then erase all the sectors that have been selected (i.e. the sectors 211 and 213) at one time. In addition to erasing the desired sectors within a chip, the architecture of the present system permits selection of sectors across various chips for simultaneous erase.
FIGS. 4(1)-4(11) illustrate the algorithm used in conjunction with the circuit 220 of FIG. 3A. In FIG. 4(1), the controller will shift the address into the circuit 220 which is decoded in the line to the erase enable register associated with the sector that is to be erased. In FIG. 4(2), the controller shifts in a command that is decoded to a set erase enable command which is used to latch the address decode signal onto the erase enable register for the addressed sector. This tags the sector for subsequent erase. In FIG. 4(3), if more sectors are to be tagged, the operations described relative to FIGS. 4(1)-4(2) are repeated until all sectors intended for erase have been tagged. After all sectors intended for erase have been tagged, the controller initiates an erase cycle as illustrated in FIG. 4(4).
Optimized erase implementations have been disclosed in two copending U.S. patent applications. They are copending U.S. patent applications, Ser. No. 204,175, filed Jun. 8, 1988, by Dr. Eliyahou Harari, now U.S. Pat. No. 5,095,344, and one entitled "Multi-State EEprom Read and Write Circuits and Techniques," Ser. No. 07/337,579, filed Apr. 13, 1989, now abandoned, by Sanjay Mehrotra and Dr. Eliyahou Harari. The disclosures of the two applications are hereby incorporate by reference. The Flash EEprom cells are erased by applying a pulse of erasing voltage followed by a read to verify if the cells are erased to the "erased" state. If not, further pulsing and verifying are repeated until the cells are verified to be erased. By erasing in this controlled manner, the cells are not subject to over-erasure which tends to age the EEprom device prematurely as well as make the cells harder to program.
As the group of selected sectors is going through the erase cycle, some sectors will reach the "erase" state earlier than others. Another important feature of the present invention is the ability to remove those sectors that have been verified to be erased from the group of selected sectors thereby preventing them from over-erasing.
Returning to FIG. 4(4), after all sectors intended for erase have been tagged, the controller initiates an erase cycle to erase the group of tagged sectors. In FIG. 4(5), the controller shifts in a global command called Enable Erase into each Flash EEprom chip that is to perform an erase. This is followed in FIG. 4(5) by the controller raising of the erase voltage line (Ve) to a specified value for a specified duration. The controller will lower this voltage at the end of the erase duration time. In FIG. 4(6), the controller will then do a read verify sequence on the sectors selected for erase. In FIG. 4(7), if none of the sectors are verified, the sequences illustrated in FIGS. 4(5)-4(7) are repeated. In FIGS. 4(8) and 3(9), if one or more sectors are verified to be erased, they are taken out of the sequence. Referring also to FIG. 3A, this is achieved by having the controller address each of the verified sectors and clear the associated erase enable registers back to a LOW with a clear enable command in bus 237. The sequences illustrated in FIGS. 4(5)-4(10) are repeated until all the sectors in the group are verified to be erased in FIG. 4(11). At the completion of the erase cycle, the controller will shift in a No Operation (NOP) command and the global Enable Erase command will be withdrawn as a protection against a false erasure.
The ability to select which sectors to erase and which ones not to, as well as which ones to stop erasing is advantageous. It will allow sectors that have erased before the slower erased sectors to be removed from the erase sequence so no further stress on the device will occur. This will increase the reliability of the system. Additional advantage is that if a sector is bad or is not used for some reason, that sector can be skipped over with no erase occurring within that sector. For example, if a sector is defective and have shorts in it, it may consume much power. A significant system advantage is gained by the present invention which allows it to be skipped on erase cycles so that it may greatly reduce the power required to erase the chip.
Another consideration in having the ability to pick the sectors to be erased within a device is the power savings to the system. The flexibility in erase configuration of the present invention enables the adaptation of the erase needs to the power capability of the system. This can be done by configuring the systems to be erased differently by software on a fixed basis between different systems. It also will allow the controller to adaptively change the amount of erasing being done by monitoring the voltage level in a system, such as a laptop computer.
An additional performance capability of the system in the present invention is the ability to issue a reset command to a Flash EEprom chip which will clear all erase enable latches and will prevent any further erase cycles from occurring. This is illustrated in FIGS. 2A and 2B by the reset signal in the line 261. By doing this in a global way to all the chips, less time will be taken to reset all the erase enable registers.
An additional performance capability is to have the ability to do erase operations without regard to chip select. Once an erase is started in some of the memory chips, the controller in the system can access other memory chips and do read and write operations on them. In addition, the device(s) doing the erase can be selected and have an address loaded for the next command following the erase.
Defect Mapping
Physical defects in memory devices give rise to hard errors. Data becomes corrupted whenever it is stored in the defective cells. In conventional memory devices such as RAM's and Disks, any physical defects arising from the manufacturing process are corrected at the factory. In RAM's, spare redundant memory cells on chip may be patched on, in place of the defective cells. In the traditional disk drive, the medium is imperfect and susceptible to defects. To overcome this problem manufacturers have devised various methods of operating with these defects present, the most usual being defect mapping of sectors. In a normal disk system the media is divided into cylinders and sectors. The sector being the basic unit in which data is stored. When a system is partitioned into the various sectors the sectors containing the defects are identified and are marked as bad and not to be used by the system. This is done in several ways. A defect map table is stored on a particular portion of the disk to be used by the interfacing controller. In addition, the bad sectors are marked as bad by special ID and flag markers. When the defect is addressed, the data that would normally be stored there is placed in an alternative location. The requirement for alternative sectors makes the system assign spare sectors at some specific interval or location. This reduces the amount of memory capacity and is a performance issue in how the alternative sectors are located.
One important application of the present invention is to replace a conventional disk storage device with a system incorporating an array of Flash EEprom memory chips. The EEprom system is preferably set up to emulate a conventional disk, and may be regarded as a "solid-state disk".
In a "disk" system made from such solid-state memory devices, low cost considerations necessitate efficient handling of defects. Another important feature of the invention enables the error correction scheme to conserve as much memory as possible. Essentially, it calls for the defective cells to be remapped cell by cell rather than by throwing away the whole sector (512 bytes typically) whenever a defect occurs in it. This scheme is especially suited to the Flash EEprom medium since the majority of errors will be bit errors rather than a long stream of adjacent defects as is typical in traditional disk medium.
In both cases of the prior art RAM and magnetic disk, once the device is shipped from the factory, there is little or no provision for replacing hard errors resulting from physical defects that appear later during normal operation. Error corrections then mainly rely on schemes using error correction codes (ECC).
The nature of the Flash EEprom device predicates a higher rate of cell failure especially with increasing program/erase cycling. The hard errors that accumulate with use would eventually overwhelm the ECC and render the device unusable. One important feature of the present invention is the ability for the system to correct for hard errors whenever they occur. Defective cells are detected by their failure to program or erase correctly. Also during read operation, defective cells are detected and located by the ECC. As soon as a defective cell is identified, the controller will apply defect mapping to replace the defective cell with a space cell located usually within the same sector. This dynamic correction of hard errors, in addition to conventional error correction schemes, significantly prolongs the life of the device.
Another feature of the present invention is an adaptive approach to error correction. Error correction code (ECC) is employed at all times to correct for soft errors as well as any hard errors that may arise. As soon as a hard error is detected, defect mapping is used to replace the defective cell with a spare cell in the same sector block. Only when the number of defective cells in a sector exceeds the defect mapping's capacity for that specific sector will the whole sector be replaced as in a conventional disk system. This scheme minimized wastage without compromising reliability.
FIG. 5 illustrates the memory architecture for the cell remapping scheme. As described before, the Flash EEprom memory is organized into sectors where the cells in each sector are erasable together. The memory architecture has a typical sector 401 organized into a data portion 403 and a spare (or shadow) portion 405. The data portion 403 is memory space available to the user. The spare portion 405 is further organized into an alternative defects data area 407, a defect map area 409, a header area 411 and an ECC and others area 413. These areas contain information that could be used by the controller to handle the defects and other overhead information such as headers and ECC.
Whenever a defective cell is detected in the sector, a good cell in the alternative defects data area 407 is assigned to backup the data designated for the defective cell. Thus even if the defective cell stores the data incorrectly, an error-free copy is stored in the backup cell. The addresses of the defective cell and the backup cell are stored as defect pointers in the defect map 409.
It is to be understood that the partitioning between the user data portion 403 and the spare portion 405 need not be rigid. The relative size of the various partitioned areas may be logically reassigned. Also the grouping of the various areas is largely for the purpose of discussion and not necessarily physically so. For example, the alternative defects data area 407 has been schematically grouped under the spare portion 405 to express the point that the space it occupies is no longer available to the user.
In a read operation, the controller first reads the header, the defect map and the alternative defects data. It then reads the actual data. It keeps track of defective cells and the location of the substitute data by means of the defect map. Whenever a defective cell is encountered, the controller substitutes its bad data with the good data from the alternative defects.
FIG. 6 illustrates the read data path control in the preferred embodiment. A memory device 33 which may include a plurality of Flash EEprom chips is under the control of the controller 31. The controller 31 is itself part of a microcomputer system under the control of a microprocessor (not shown). To initiate the reading of a sector, the microprocessor loads a memory address generator 503 in the controller with a memory address for starting the read operation. This information is loaded through a microprocessor interface port 505. Then the microprocessor loads a DMA controller 507 with the starting location in buffer memory or bus address that the data read should be sent. Then the microprocessor loads the header information (Head, Cylinder and sector) into a holding register file 509. Finally, the microprocessor loads a command sequencer 511 with a read command before passing control to the controller 31.
After assuming control, the controller 31 first addresses the header of the sector and verifies that the memory is accessed at the address that the user had specified. This is achieved by the following sequence. The controller selects a memory chip (chip select) among the memory device 33 and shifts the address for the header area from the address generator 503 out to the selected memory chip in the memory device 33. The controller then switches the multiplexer 513 and shifts also the read command out to the memory device 33. Then the memory device reads the address sent it and begins sending serial data from the addressed sector back to the controller. A receiver 515 in the controller receives this data and puts it in parallel format. In one embodiment, once a byte (8 bits) is compiled, the controller compares the received data against the header data previously stored by the microprocessor in the holding register file 509. If the compare is correct, the proper location is verified and the sequence continues.
Next the controller 31 reads the defect pointers and loads these bad address locations into the holding register file 509. This is followed by the controller reading the alternative defects data that were written to replace the bad bits as they were written. The alternative bits are stored in an alternative defects data file 517 that will be accessed as the data bits are read.
Once the Header has been determined to be a match and the defect pointers and alternative bits have been loaded, the controller begins to shift out the address of the lowest address of the desired sector to be read. The data from the sector in the memory device 33 is then shifted into the controller chip 31. The receiver 515 converts the data to a parallel format and transfers each byte into a temporary holding FIFO 519 to be shipped out of the controller.
A pipeline architecture is employed to provide efficient throughput as the data is gated through the controller from the receiver 515 to the FIFO 519. As each data bit is received from memory the controller is comparing the address of the data being sent (stored in the address generator 507) against the defect pointer map (stored in the register file 509). If the address is determined to be a bad location, by a match at the output of the comparator 521, the bad bit from the memory received by the receiver 515 is replaced by the good bit for that location. The good bit is obtained from the alternative defects data file 517. This is done by switching the multiplexer 523 to receive the good bit from the alternative defects data file instead of the bad bit from the receiver 515, as the data is sent to the FIFO 519. Once the corrected data is in the FIFO it is ready to be sent to buffer memory or system memory (not shown). The data is sent from the controller's FIFO 519 to the system memory by the controller's DMA controller 507. This controller 507 then requests and gets access to the system bus and puts out an address and gates the data via an output interface 525 out to the system bus. This is done as each byte gets loaded into the FIFO 519. As the corrected data is loaded into the FIFO it will also be gated into an ECC hardware 527 where the data file will be acted on by the ECC.
Thus in the manner described, the data read from the memory device 33 is gated through the controller 31 to be sent to the system. This process continues until the last bit of addressed data has been transferred.
In spite of defect mapping of previously detected defective cells, new hard errors might occur since the last mapping. As the dynamic defect mapping constantly "puts away" new defective cells, the latest hard error that may arise between defect mapping would be adequately handled by the ECC. As the data is gated through the controller 31, the controller is gating the ECC bits into the ECC hardware 527 to determine if the stored value matched the just calculated remainder value. If it matches then the data transferred out to the system memory was good and the read operation was completed. However, if the ECC registers an error then a correction calculation on the data sent to system memory is performed and the corrected data retransmitted. The method for calculating the error can be done in hardware or software by conventional methods. The ECC is also able to calculate and locate the defective cell causing the error. This may be used by the controller 31 to update the defect map associated with the sector in which the defective cell is detected. In this manner, hard errors are constantly removed from the Flash EEprom system.
FIG. 7 illustrates the write data path control in the preferred embodiment. The first portion of a write sequence is similar to a read sequence described previously. The microprocessor first loads the Address pointers for the memory device 33 and the DMA as in the read sequence. It also loads the header desired into the address generator 503 and the command queue into the command sequencer 511. The command queue is loaded with a read header command first. Thereafter, control is passed over to the controller 31. The controller then gates the address and command to the memory device 33, as in the read sequence. The memory device returns header data through controller's receiver 515. The controller compares the received header data to the expected value (stored in the holding register file 509). If the compare is correct, the proper location is verified and the sequence continues. Then the controller loads the defective address pointers from the memory device 33 into the holding register file 509 and the alternative data into the alternative defects data file 517.
Next, the controller begins to fetch the write data from system memory (not shown). It does this by getting access to the system bus, outputs the memory or bus address and does the read cycle. It pulls the data into a FIFO 601 through an input interface 603. The controller then shifts the starting sector address (lowest byte address) from the address generator 503 to the selected memory device 33. This is followed by data from the FIFO 601. These data are rotted through multiplexers 605 and 513 and converted to serial format before being sent to the memory device 33. This sequence continues until all bytes for a write cycle have been loaded into the selected memory.
A pipeline architecture is employed to provide efficient throughput as the data is gated from the FIFO 601 to the selected memory 33. The data gated out of the FIFO 601 is sent to the ECC hardware 527 where a remainder value will be calculated within the ECC. In the next stage, as the data is being sent to the memory device through multiplexers 605 and 513, the comparator 521 is comparing its address from the address generator 503 to the defect pointer address values in the holding register file 509. When a match occurs, indicating that a defective location is about to be written, the controller saves this bit into the alternative defect data file 517. At the same time, all bad bits sent to memory will be sent as zeroes.
After the bytes for a write cycle have been loaded into the selected memory device, the controller issues a program command to the memory device and initiate a write cycle. Optimized implementations of write operation for Flash EEprom device have been disclosed in two previously cited co-pending U.S. patent applications, Ser. No. 204,175, now U.S. Pat. No. 5,095,344, and one entitled "Multi-State EEprom Read and Write Circuits and Techniques, Ser. No. 07/337,579, filed Apr. 13, 1989, now abandoned. Relevant portions of the disclosures are hereby incorporated by reference. Briefly, during the write cycle, the controller applies a pulse of programming (or writing) voltages. This is followed by a verify read to determine if all the bits have been programmed properly. If the bits did not verify, the controller repeats the program/verify cycle until all bits are correctly programmed.
If a bit fails to verify after prolonged program/verify cycling, the controller will designate that bit as defective and update the defect map accordingly. The updating is done dynamically, as soon as the defective cell is detected. Similar actions are taken in the case of failure in erase verify.
After all the bits have been programmed and verified, the controller loads the next data bits from the FIFO 601 and addresses the next location in the addressed sector. It then performs another program/verify sequence on the next set of bytes. The sequence continues until the end of the data for that sector. Once this has occurred, the controller addresses the shadow memory (header area) associated with the sector (see FIG. 5) and writes the contents of the ECC registers into this area.
In addition, the collection of bits that was flagged as defective and were saved in the alternative defects data file 516 is then written in memory at the alternative defects data locations (see FIG. 5), thereby saving the good bit values to be used on a subsequent read. Once these data groups are written and verified, the sector write is considered completed.
The present invention also has provision for defect mapping of the whole sector, but only after the number of defective cells in the sector has exceeded the cell defect mapping's capacity for that specific sector. A count is kept of the number of defective cells in each sector. When the number in a sector exceeds a predetermined value, the controller marks that sector as defective and maps it to another sector. The defect pointer for the linked sectors may be stored in a sector defect map. The sector defect map may be located in the orginal defective sector if its spare area is sufficiently defect-free. However, when the data area of the sector has accumulated a large number of defects, it is quite likely that the spare area will also be full of defects.
Thus, it is preferable in another embodiment to locate the sector map in another memory maintained by the controller. The memory may be located in the controller hardware or be part of the Flash EEprom memory. When the controller is given an address to access data, the controller compares this address against the sector defect map. If a match occurs then access to the defective sector is denied and the substitute address present in the defect map is entered, and the corresponding substitute sector is accessed instead.
In yet another embodiment, the sector remapping is performed by the microprocessor. The microprocessor looks at the incoming address and compares it against the sector defect map. If a match occurs, it does not issue the command to the controller but instead substitute the alternative location as the new command.
Apart from the much higher speed of the solid-state disk, another advantage is the lack of mechanical parts. The long seek times, rotational latency inherent in disk drives are not present. In addition, the long synchronization times, sync mark detects and write gaps are not required. Thus the overhead needed for accessing the location where data is to be read or written is much less. All of these simplifications and lack of constraints result in a much faster system with much reduced overheads. In addition, the files can be arranged in memory in any address order desired, only requiring the controller to know how to get at the data as needed.
Another feature of the invention is that defect mapping is implemented without the need to interrupt the data stream transferred to or from the sector. The data in a block which may contain errors are transferred regardless, and is corrected afterwards. Preserving the sequential addressing will result in higher speed by itself. Further, it allows the implementation of an efficient pipeline architecture in the read and write data paths.
Write Cache System
Cache memory is generally used to speed up the performance of systems having slower access devices For example in a computer system, access of data from disk storage is slow and the speed would be greatly improved if the data could be obtained from the much faster RAM. Typically a part of system RAM is used as a cache for temporarily holding the most recently accessed data from disk. The next time the data is needed, it may be obtained from the fast cache instead of the slow disk. The scheme works well in situations where the same data is repeatedly operated on. This is the case in most structures and programs since the computer tends to work within a small area of memory at a time in running a program. Another example of caching is the using of faster SRAM cache to speed up access of data normally stored in cheaper but slower DRAM.
Most of the conventional cache designs are read caches for speeding up reads from memory. In some cases, write caches are used for speeding up writes to memory. However in the case of writes to system memory (e.g. disks), data is still being written to system memory directly every time they occur, while being written into cache at the same time. This is done because of concern for loss of updated data files in case of power loss. If the write data is only stored in the cache memory (volatile) a loss of power will result in the new updated files being lost from cache before having the old data updated in system memory (non-volatile). The system will then be operating on the old data when these files are used in further processing. The need to write to main memory every time defeats the caching mechanism for writes. Read caching does not have this concern since the data that could be lost from cache has a backup on disk.
In the present invention, a system of Flash EEprom is used to provide non-volatile memory in place of traditional system memories such as disk storage. However, Flash EEprom memory is subject to wearing out by excessive program/erase cycles. Even with the improved Flash EEprom memory device as disclosed in copending U.S. patent applications, Ser. No. 204,175 now U.S. Pat. No. 5,095,344, and Harari, Ser. No. 07/337,579, filed Apr. 13, 1989, now abandoned, and Techniques," by Sanjay Mehrotra and Dr. Eliyahou Harari filed on the same day as the present application, the endurance limit is approximately 10.sup.6 program/erase cycles. In a ten-year projected life time of the device, this translates to a limit of one program/erase cycle per 5 minutes. This may be marginal in normal computer usage.
To overcome this problem, a cache memory is used in a novel way to insulate the Flash EEprom memory device from enduring too many program/erase cycles. The primary function of the cache is to act on writes to the Flash EEprom memory and not on reads of the Flash EEprom memory, unlike the case with traditional caches. Instead of writing to the Flash EEprom memory every time the data is updated, the data may be operated on several times in the cache before- being committed to the Flash EEprom memory. This reduces the number of writes to the Flash EEprom memory. Also, by writing mostly into the faster cache memory and reducing the number of writes to the slower Flash EEprom, an additional benefit is the increase in system write throughput.
A relatively small size cache memory is quite effective to implement the present invention. This helps to overcome the problem of data loss in the volatile cache memory during a power loss. In that event, it is relatively easy to have sufficient power reserve to maintain the cache memory long enough and have the data dumped into a non-volatile memory such as a specially reserved space in the Flash EEprom memory. In the event of a power down or and power loss to the system, the write cache system may be isolated from the system and a dedicated rechargeable power supply may be switch in only to power the cache system and the reserved space in the Flash EEprom memory.
FIG. 8 illustrates schematically a cache system 701 as part of the controller, according to the present invention. On one hand the cache system 701 is connected to the Flash EEprom memory array 33. On the other hand it is connected to the microprocessor system (not shown) through a host interface 703. The cache system 701 has two memories. One is a cache memory 705 for temporarily holding write data files. The other is a tag memory 709 for storing relevant information about the data files held in the cache memory 705. A memory timing/control circuit 713 controls the writing of data files from the cache memory 705 to the Flash EEprom memory 33. The memory control circuit 713 is responsive to the information stored in the tag memory as well as a power sensing input 715 with is connected through the host interface 703 via a line 717 to the power supply of the microprocessor system. A power loss in the microprocessor system will be sensed by the memory control circuit 713 which will then down load all the data files in the volatile cache memory 705 to the non-volatile Flash EEprom memory 33.
In the present invention, the Flash EEprom memory array 33 is organized into sectors (typically 512 byte size) such that all memory cells within each sector are erasable together. Thus each sector may be considered to store a data file and a write operation on the memory array acts on one or more such files.
During read of a new sector in the Flash EEprom memory 33, the data file is read out and sent directly to the host through the controller. This file is not used to fill the cache memory 705 as is done in the traditional cache systems.
After the host system has processed the data within a file and wishes to write it back to the Flash EEprom memory 33, it accesses the cache system 701 with a write cycle request. The controller then intercepts this request and acts on the cycle.
In one embodiment of the invention, the data file is written to the cache memory 705. At the same time, two other pieces of information about the data file are written to a tag memory 709. The first is a file pointer which identifies the file present in the cache memory 705. The second is a time stamp that tells what time the file was last written into the cache memory. In this way, each time the host wishes to write to the Flash EEprom memory 33, the data file is actually first stored in the cache memory 705 along with pointers and time stamps in the tag memory 709.
In another embodiment of the invention, when a write from the host occurs, the controller first checks to see if that file already existed in the cache memory 705 or has been tagged in the tag memory 709. If it has not been tagged, the file is written to the Flash memory 33, while its identifier and time stamp are written to the tag memory 709. If the file already is present in the cache memory or has been tagged, it is updated in the cache memory and not written to the Flash memory. In this way only infrequently used data files are written into the Flash memory while frequently used data files are trapped in the cache memory.
In yet another embodiment of the invention, when a write from the host occurs, the controller first checks to see if that data file has been last written anywhere within a predetermined period of time (for example, 5 minutes). If it has not, the data file is written to the Flash memory 33, while its identifier and time stamp are written to the tag memory 709. If the data file has been last written within the predetermined period of time, it is written into the cache memory 705 and not written to the Flash memory. At the same time, its identifier and time stamp are written to the tag memory 709 as in the other embodiments. In this way also, only infrequently used data files are written into the Flash memory while frequently used data files are trapped in the cache memory.
In all embodiments, over time the cache memory 705 will start to fill up. When the controller has detected that some predetermined state of fullness has been reached, it begins to archive preferentially some files over others in the cache memory 705 by writing them to the Flash memory 33.
In either embodiments, over time the cache memory 705 will start to fill up. When the controller has detected that some predetermined state of fullness has been reached, it begins to archive preferentially some files over others in the cache memory 705 by writing them to the Flash memory 33. The file identifier tag bits for these files are then reset, indicating that these files may be written over. This makes room for new data files entering the cache memory.
The controller is responsible for first moving the least active files back into the Flash memory 33 to make room for new active files. To keep track of each file's activity level, the time stamp for each file is incremented by the controller at every time step unless reset by a new activity of the file. The timing is provided by timers 711. At every time step (count), the controller systematically accesses each data file in the cache memory and reads the last time stamp written for this data file. The controller then increments the time stamp by another time step (i.e. increments the count by one).
Two things can happen to a file's time stamp, depending on the activity of the file. One possibility is for the time stamp to be reset in the event of a new activity occurring. The other possibility is that no new activity occurs for the file and the time stamp continues to increment until the file is removed from the cache. In practice a maximum limit may be reached if the time stamp is allowed to increase indefinitely. For example, the system may allow the time stamp to increment to a maximum period of inactivity of 5 minutes. Thus, when a data file is written in the cache memory, the time stamp for the file is set at its initial value. Then the time stamp will start to age, incrementing at every time step unless reset to its initial value again by another write update. After say, 5 minutes of inactivity, the time stamp has incremented to a maximum terminal count.
In one embodiment of keeping count, a bit can be shifted one place in a shift register each time a count increment for a file occurs. If the file is updated (a new activity has occurred) the bit's location will be reset to the initial location of the shift register. On the other hand, if the file remains inactive the bit will eventually be shifted to the terminal shift position. In another embodiment, a count value for each file is stored and incremented at each time step. After each increment, the count value is compared to a master counter, the difference being the time delay in question.
Thus, if a file is active its incremented time stamp is reset back to the initial value each time the data file is rewritten. In this manner, files that are constantly updated will have low time stamp identifiers and will be kept in cache until their activity decreases. After a period of inactivity has expired, they acquire the maximum time stamp identifiers. The inactive files are eventually archived to the Flash memory freeing space in the cache memory for new, more active files space is also freed up in the tag memory when these inactive files are moved to the Flash memory.
At any time -when room must be made available for new data files coming into the cache memory, the controller removes some of the older files and archives them to the Flash memory 33. Scheduling is done by a memory timing/control circuit 713 in the controller. The decision to archive the file is based on several criteria. The controller looks at the frequency of writes occurring in the system and looks at how full the cache is. If there is still room in the cache, no archiving need to be done. If more room is needed, the files with the earliest time stamps are first removed and archived to the Flash memory.
Although the invention has been described with implementation in hardware in the controller, it is to be understood that other implementations are possible. For example, the cache system may be located elsewhere in the system, or be implemented by software using the existing microprocessor system. Such variations are within the scope of protection for the present invention.
The Profile of how often data is written back to the Flash memory is determined by several factors It depends on the size of the cache memory and the frequency of writes occurring in the system. With a small cache memory system, only the highest frequency files will be cached. Less frequently accessed files will also be cached with increasing cache memory size. In the present invention, a relatively cheap and small amount of cache memory, preferably about 1 Mbyte, may be used to good advantage. By not constantly writing the most active files (the top 5%), the write frequency of the Flash EEprom may be reduced from the usual one every millisecond to one every 5 minutes. In this way the wear-out time for the memory can be extended almost indefinitely. This improvement is also accompanied by increased system performance during write.
Incorporating time tag into the write cache concept has the advantage that the size of the write cache buffer memory can be relatively small, since it is used only to store frequently written data files, with all other files written directly into the Flash EEprom memory. A second advantage is that the management of moving data files in and out of the write cache buffer can be automated since it does not require advanced knowledge of which data files are to be called next.
The various aspects of the present invention that have been described co-operate in a system of Flash EEprom memory array to make the Flash EEprom memory a viable alternative to conventional non-volatile mass storage devices.
While the embodiments of the various aspects of the present invention that have been described are the preferred implementation, those skilled in the art will understand that variations thereof may also be possible. Therefore, the invention is entitled to protection within the full scope of the appended claims.
1. A memory card connectable to a computer system, comprising:
- an array of Electrically Erasable and Programmable Read Only Memory ("EEPROM") cells partitioned into a plurality of flash sectors, the cells of the array being individually programmable into more than two states in order to store more than one bit of data per cell;
- each flash sector being a group of cells that are erasable together as a unit, and having a portion thereof reserved as redundant cells; and
- a memory controller for controlling operations of the EEPROM cells;
- error detection means within said memory controller for detecting any defective cells within the array;
- defect pointers, each generated by said memory controller for linking a detected defective cell's address to that of a corresponding redundant cell substituting for the defective cell, said defect pointers being stored within the array; and
- defective cell substituting means within said memory controller and responsive to said defect pointers for substituting said detected defective cell with said corresponding redundant cells.
2. The memory card as in claim 1, wherein said plurality of sectors have a portion thereof reserved as redundant sectors, and said EEPROM controller, upon detecting more than a predetermined number of defective cells in a sector, substitutes said sector with one of said redundant sectors.
3. The memory card as in claim 2, wherein said EEPROM controller including a circuit for implementing error correction codes for detecting and correcting errors in the operations of the EEPROM cells.
4. The memory card as in claim 1, wherein said memory card is compatible with a magnetic disk drive storage system and capable of substituting therefor in said computer system.
5. A memory card connectable to a computer system, said memory card comprising:
- an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, the individual sectors including a user data portion and a spare portion of the group of memory cells, the cells of the array being individually programmable into more than two states in order to store more than one bit of data per cell,
- a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system,
- means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors, and
- means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors.
6. The memory card of claim 5, which additionally comprises means within said memory controller for, upon detecting a defective sector having more than a predetermined number of defective cells therein, substituting another of said plurality of sectors for the defective sector.
7. The memory card of claim 5, which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data stored in the user data portions of the same sectors.
8. The memory card of claim 5, wherein said memory card is compatible with a magnetic disk drive storage system and capable of being substituted therefor in said computer system.
9. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:
- providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,
- programming the individual cells of the array into one of more than two programmable states in order to store more than one bit of data per cell,
- reserving a portion of the memory cells within the individual sectors as spare cells, remaining cells of the individual sectors being designated for storing data,
- enabling the controller to detect when a cell within the data portion of a sector becomes defective,
- causing the controller to store an address of such a detected defective cell, and
- thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected.
10. The method according to claim 9, wherein the storage of an address of a detected defective cell includes storing the address of the detected defective cell within the spare cells of the sector in which the defective cell exists.
11. The method according to claim 10, wherein detecting the address of a defective cell includes maintaining a defect map which links addresses of defective cells to substitute redundant cells.
12. The method according to claim 11, wherein detecting the address of a defective cell includes storing the defect map in the memory array.
13. The method according to claim 9, additionally comprising:
- reserving a number of the sectors as redundant sectors,
- in response to a number of occurrences of a defective cell being detected within a single sector exceeding a predetermined number, marking such a single sector as a defective sector, and
- thereafter remapping the defective sector into one of the redundant sectors as a substitute for the defective sector.
14. The method according to claim 13, wherein the marking of a sector as the defective sector includes placing an address of the defective sector into a defect map that includes an address of the substitute redundant sector, thereby causing the redundant sector to be accessed in response to a request to access the defective sector.
15. The method according to claim 13, wherein a defect map is stored in the memory cell array.
16. The method according to claim 13, wherein the marking and remapping operations are under the control of said memory controller.
17. The method according to claim 9, additionally comprising storing addresses of the sectors in the spare cells of the sectors to which the address pertains.
18. The method according to claim 9, additionally comprising storing in the spare cells of the individual sectors an error correction code for data stored in corresponding ones of the sectors.
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Type: Grant
Filed: Dec 29, 1997
Date of Patent: Mar 2, 1999
Assignee: SanDisk Corporation (Sunnyvale, CA)
Inventors: Eliyahou Harari (Los Gatos, CA), Robert D. Norman (San Jose, CA), Sanjay Mehrotra (Milpitas, CA)
Primary Examiner: David Nelms
Assistant Examiner: Trong Phan
Law Firm: Majestic, Parsons, Siebert & Hsue
Application Number: 8/999,472
International Classification: G11C 1604;


text:
By Deirdre Macnab
Being invited to write a column to oppose tax breaks for disabled veterans, low-income seniors and spouses of veterans and first responders (our EMTs, firefighters, etc.) killed in the line of duty is like being asked to throw torpedoes at the Easter Bunny or Santa Claus.
But do it I will. That's because this November, Florida voters will see 11 of the most confusing, complex and sometimes misleading state ballot amendments ever proposed, and voters will need to decide: Do I want this in our state constitution?
Our Florida Constitution was crafted as a document that is intended to be difficult to change, and kept sacred for the purpose of identifying the structure of our government. These proposed amendments, however, would insert specific tax exemptions into that sacred document.
As beneficial an idea as tax breaks may be for disabled veterans, low-income seniors and surviving spouses of first responders and veterans, is the constitution the right place to enact them?
The League of Women Voters of Florida, after years of studying and evaluating changes to our state constitution, says no, and urges Florida voters to give these amendments — 2, 9 and 11 (as well as all the other state amendments) — a firm thumbs down.
Of course our disabled veterans and surviving spouses of first responders and veterans deserve our highest respect, and we should do everything we can reasonably do to thank them and recognize them. Low-income seniors deserve a helping hand as well, which is why the League supports getting the Medicaid funds that were refused by Gov. Rick Scott restored to Florida.
The League's concern is twofold:
First, is the state constitution the appropriate place for tax breaks … for anyone? With the constitution intentionally hard to change, a better place for such tax provisions is regular statutory law, where changing conditions make modification easier. The constitution is a governing document, and should be left sacred to that purpose. We urge legislators to use their law-making powers, and not weigh down citizens with complicated amendments that do not belong in our state's constitution.
Second, should Florida have a level playing field for taxes? Imagine a giant hunk of Swiss cheese. That is our state tax policy. Loopholes everywhere for private plane owners, yacht owners and ostrich-feed owners.
These loopholes, breaks and exemptions mean one thing: You pay more. The League says close the loopholes, level the playing field, and lower the amount on everyone, not just a designated few.
The total cost of these three tax breaks for local governments over three years would amount to about $45 million. It's not going to break the bank.
The other amendments on the ballot — which, unbelievably, propose among other things to let those who live out of state and have second homes here get the residents' property-tax break — will in total mean more than $1 billion less for our public schools, health care, roads, bridges, sidewalks, police and more. The League says just say no to the state amendments.
Many Floridians feel their property taxes are too high, but forget we have no income tax, and are surprised to hear that when we count all our taxes together, we pay less than citizens in most other states. We have one of the lowest corporate taxes as well, and only 2 percent of Florida corporations pay corporate income tax.
So let's thank our veterans, our first responders and our low-income seniors not by opening more exemptions just for them, but by leveling the playing field, providing a fair tax rate for all Floridians and adequately funding our public schools and universities, so that we can compete with the rest of America — perhaps one day bringing higher-paying jobs and new businesses to our state.
Deirdre Macnab is state president of the League of Women Voters of Florida.

subset: commoncrawl


text:
Shooting Skills for Hunters (.30-30 Drill)
The effective range of the .30-30 is about 150-170 yards. Some of the wizzy new Magnums can outperform this by roughly 300 percent, at least on paper. But can the hunter outperform the .30-30? Can you?
The .30-30 WCF (Winchester Center Fire) was a hot little number when first debuted in 1895 but today's hunters complain about this "obsolete" antique. Standard wisdom states this cartridge is best contained within a range of 100-175 yards. A.30-30 will push a 150-170 grain bullet out at approximately 2200 fps or so. With a 150 yard zero, the bullet will be about two inches above line of sight at 100 yards and around five inches low at 200.
Few hunters possess enough shooting skill that warrants better performance than this. Are you one of them? Find out with the .30-30 Drill.
Begin by getting a good 150 yard zero for that anemic.30-30 (or whatever your favorite hunting rifle is chambered in.) Set up a Y-ring steel target at 150 yards. If you don't have a quality, self-resetting steel target that is about 8-10 inches in diameter, a paper dinner plate at 150 yards makes an ersatz substitute. Get a shooting timer, or a buddy with a whistle and stop watch, to record the time.
Start from standing up. On the start signal adopt a sitting position and fire one aimed shot at the plate. Stand back up and repeat the drill for a total of three shots. After completing this three string/three round sequence from the sitting position, do it again adopting and shooting from prone.
We are shooting at the distance we zeroed giving point-of-impact at point-of-aim on a nice, level playing field with no intervening brush, trees, etc. All the shooting is done from the two most stable positions available in the field. Furthermore, the target is presented whole, as opposed to a large animal with the vital zone hidden somewhere inside, thus eliminating the need to estimate target angle. Just hold center and let 'er rip!
Regardless of elapsed time, a hunter claiming to need something better than a .30-30 should get at least 5 hits out of 6 shots (83% hits) or better on this six MOA target every time. If so, our hero can actually make use of the ballistic capability provided by a .30-30 or equivalent for field shooting. If not, their maximum effective range in field shooting is shorter than 150 yards and the capability of a .30-30 rifle exceeds their present level of skill.
A more competent hunter-shooter who can get those same hits in ten seconds per shot or less just might benefit from a "better" rifle. They possess sufficient skill to warrant extended range.
We can repeat this drill out even further. Use the same target and set at 200, 225, 250, 300, or out as far as you dare. Give the shooter an extra three seconds or so for every 50 yards beyond 150. Sight in appropriately and shoot. For example, .308/ .30-06 and cartridges of similar ballistics can set their zero to 200-250 yards. Churchill shooting


text:
In the last several years Google has become quick to respond to complaints of copyright infringement. Unfortunately, its record in dealing with unfounded claims (specifically on YouTube) is a bit mixed. In particular the process for appealing a Content ID takedown has left many users frustrated and with little recourse in the event of a rejected dispute. And its the content owners themselves who make that decision. Starting today, even if a dispute is rejected, users can file an appeal that leaves a content owner with one of two choices — recind the complaint or file a proper DMCA takedown notice. To minimize the amount of appeals and disputes Google is also launching an improved Content ID algorithm that identifies potentially invalid claims and places them in a queue to be reviewed manually before takedowns are issued. For more, check out the source.
Filed under: Internet, Google
YouTube scales back automatic Content ID takedowns, improves appeals process originally appeared on Engadget on Wed, 03 Oct 2012 19:43:00 EDT. Please see our terms for use of feeds.
Permalink | YouTube Creator Blog | Email this | Comments


text:
Banner frames are an amazing marketing tool for use at events, exhibitions and conferences, as well as simply outside of your premises to promote your business. Perfectly suited to long-term outdoor or indoor use, they do not suffer from the twisting and buckling problems suffered by their aluminium counterparts.
- Includes bespoke-printed graphic(s) to fit the frame
- 35mm diameter steel tube construction
- Banner included in price
- Single or double-sided
- Includes bungee ties
- Built to last


text:
- Inside Athletics
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WILMINGTON, N.C. (Sept. 8, 2007) - The ETSU women's tennis team put the pedal to the metal early and cruised by its competition on day two of the UNC Wilmington Country Club of Landfall Collegiate Tennis Invitational Saturday afternoon. The trio of Olya Batsula (
"The girls played well today and I am very happy with the way they are competing," said head ETSU women's tennis coach Steve Brooks. "They are all representing ETSU well, and it's a great way to start the season."
ETSU's morning began with the partners of Batsula/Stupak running through doubles competition. First, the Bucs pair defeated UNC Greensboro's team of Valerie Behr and Jessica Eblen, 9-7, and then earned a spot into Sunday's finals by knocking off Maggie Yahner and Cathy Nimitz from the
The set of Buccaneer stars remained perfect in singles play as Batsula, Stupak and Voinea all won their matches respectively. For second time on Saturday, Batsula faced
The Bucs are guaranteed at least one final win tomorrow, as Voinea and Batsula face off against each other in the Navy Flight finals, while Stupak will represent ETSU in the championship match of the Teal Flight.
Competition has been moved up to 8 a.m. Sunday, due to the scheduled landfall of subtropical storm Gabrielle, which is on path to hit the
Please visit www.ETSUBucs.com for more information on Buccaneer women's tennis and all other ETSU athletic events.


text: China | October 7, 2016 Written by Raffaello Pantucci. Back in the late 1990s, then-PRC President and Communist Party leader Jiang Zemin noticed that the country was facing an imbalance. Deng Xiaoping's economic reforms had opened up the coastal cities, transforming them into beacons of international industry and development. Cities like Shanghai, Shenzhen and Guangzhou were on their way to becoming international hubs. And yet looking inland, the difference was stark, with parts of the centre or border regions with neighbouring Southeast, South and Central Asia remaining poor and underdeveloped. Seeking to rectify this, and in part to help Chinese companies go out, Jiang Zemin instigated a 'Develop the West' or 'Great Western Development' strategies. Academics like Zheng Xinli came back from their travels along China's borderlands with southeast Asia with ideas of developing multilateral institutions that would help address one of the key problems in the region, a lack of infrastructure to help accelerate trade between parts of the world that were already deeply economically interdependent. To China's west, the problems were political and had a security bent to them thanks to the proximity of Afghanistan, historical conflicts with Russia and an angry resident Uighur population. As the Soviet Union fell apart, China accelerated a process of border demarcation going on between itself, Russia, Kazakhstan, Kyrgyzstan and Tajikistan into a process called the 'Shanghai Five' – named after the city in which they met. The priority was largely to define what China's borders were, with a later attempt to move the discussion towards other economic and political goals. To China's south, the scenario looked different. In the absence of a collapsing superpower with which China had fought conflicts, Beijing instead found itself confronted by a series of underdeveloped nations (including ones with which it had fought conflicts in some cases) that nonetheless had deep economic and ethnic links back and forth across China's equally underdeveloped borderlands. In August 1999, over one hundred academics and experts from China, India, Burma and Bangladesh gathered together in Kunming for a conference at the Yunnan Academy of Social Sciences (YASS). The outline for the conference was laid out as: Practical and strategically significance for the regional cooperation among China, India, Bangladesh and Burma; Feasibility of cooperation in the economic, trade and technological cooperation among China (Yunnan), India, Bangladesh and Burma (including industry, agriculture, tourism and finance); Study on the construction of communication channels and networks among China, India, Bangladesh and Burma (including the opening and reconstructing roads, air lines, water routes and railways); Prospect and basis for the economic cooperation among China, India, Bangladesh and Burma; Open-door policies and trade and investment environment for China, India, Bangladesh and Burma; Construct the framework for regional cooperation in China, India, Bangladesh and Burma. Its conclusions were similar and thus was laid out the framework for the Bangladesh-China-India-Myanmar Economic Corridor (BCIM), or the 'Kunming Initiative'. Focusing on improving infrastructure and opening markets, the BCIM was dreamed up as a way of developing China through opening of markets, building infrastructure, and enhancing cooperation between China and its border nations. The vision was one that was actually suggested a few months earlier in March 1999 at the 9th National Party Congress in Beijing by President Jiang Zemin. Crystallized in speeches delivered later in the year and put on the front page of the People's Daily on June 19 1999, the 'Great Western Development Strategy' was a vision that suggested the 'time was ripe' to speed up the development of the central and western regions' and that this 'should become a major strategic task for the party.' In other words, the Chinese Communist Party was to throw itself into working to develop the left behind 'western' (put in parentheses as the logic of 'west' was substantially stretched to anything not on China's coast), and the 'Kunming Initiative' was to push this concept out as a trade and economic corridor that swept through Myanmar and Bangladesh to India. All of which sounds a lot like the current vision that is being advanced for the 'Belt and Road', where we see Beijing pushing out trade and economic corridors in every direction as a way of helping not only China's companies go out into the world, but also to help develop China's under-developed 'western regions', be this in central China, Xinjiang, Tibet or Yunnan. Given the problems in Xinjiang, it is maybe unsurprising that the Central Asian strand of the 'Belt and Road' – the 'Silk Road Economic Belt' that Xi Jinping christened when he visited Astana in September 2013 – has found itself front and center, but it is also the one which is building on a well-established political track which Beijing had been laying since the collapse of the Soviet Union. There is an additional problem with the BCIM which is that it ends with a power, India, with which Beijing continues to have tense relations that are complicated by China's intimate embrace through another strand of the 'Belt and Road' with India's persistent enemy Pakistan (the $46 billion China-Pakistan Economic Corridor). This tension alongside the persistent problems of development, governance and criminality that are encountered in Myanmar and Bangladesh, all serve to illustrate why China has had a harder time of things in Southeast Asia. But the BCIM and its history do serve to illustrate that the 'Belt and Road' vision that is on its way to becoming the signature foreign policy initiative of the Xi Jinping administration is not in fact as new as it may sound. Rather, it is a case of an old model being re-attempted in a new cast. And as the 'Belt and Road' continues to remain a nebulous vision rather than a specific project, its conceptual embrace becomes ever tighter and it drags in historical projects like the BCIM into its all-encompassing horizon. During their July 2015 meeting on the fringes of the joint SCO and BRICS meeting Russia hosted in Ufa, Presidents Narendra Modi and Xi Jinping confirmed the proximity of the two visions. As reported in the official Chinese read-out of the meeting: 'Both countries should also join efforts to promote the construction of Asian Infrastructure Investment Bank (AIIB), New Development Bank (NDB) of BRICS nations and the Bangladesh-China-India-Myanmar Economic Corridor (BCIM), and discuss on effectively connecting China's initiative of the "Belt and Road" with related initiatives of India, so as to achieve mutually beneficial cooperation and common development.' The BCIM has therefore been brought into the broader 'Belt and Road' vision, highlighting the degree to which its goals are interchangeable with the approach being practiced by Beijing in the modern 'march west' strategy as laid out by Xi Jinping. Thus bringing in full circle the repetition that is inherent within the current vision and the historical one, and showing how this approach is in fact one that China has attempted before. Whether this one will succeed where previous have not is unclear at this point, but when one considers the vast sums that Beijing is able to muster and deploy under the auspices of the current approach, it seems that the current 'Belt and Road' will leave an indelible impression. One that may even help imprint the BCIM onto Southeast Asia in its wake. Raffaello Pantucci is Director of International Security Studies at the Royal United Services Institute (RUSI). He is also the co-creator of http://www.chinaincentralasia.com and is currently working on a number of projects looking at the Belt and Road through a number of different lenses. Image credit: CC by World Economic Forum/flickr. Are Chinese-style gardens built outside China a form of 'soft power'? Hukou Reform and China's Migrant Workers.


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Podcast: Play in new window | Download (Duration: 1:37:18 — 89.2MB)
Discussing Camus's "An Absurd Reasoning" and "The Myth of Sisyphus" (1942).
Does our eventual death mean that life has no meaning and we might as well end it all? Camus starts to address this question, then gets distracted and talks about a bunch of phenomenologists until he dies unreconciled. Also, let's all push a rock up a hill and like it, okay? Plus, the fellas dwell on genius and throw down re. the Beatles, the beloved Robert C. Solomon and Malcom Gladwell's Outliers.
An abridged version of the reading covered with most of the good stuff in it is here. An unabridged version of "An Absurd Reasoning" is here.
Also, Wes said something wrong on the episode.
End song: "My Friends" by Mark Lint and the Simulacra (2000).
If you enjoy the episode, please donate at least $1:


text:
|image source
Richard Wilcox, Contributor
Activist Post
Were it not for certain nuclear whistle blowers and outside, independent experts, the public would have to rely on the glib and technically inaccessible reports from Tokyo Electric Power Company (Tepco) or the Japanese government.
Not that those reports are entirely without substance, but due to the incomprehensible technical jargon most people simply throw up their hands and hope for the best.
Luckily, in this day of the Internet we can learn a lot about what is going on thanks to independent researchers and writers.
To the extent that mainstream newspapers have covered the issue responsibly, and there has been substantive coverage, web sites like "enenews.com"; "fukushima-diary.com" and "rense.com" have served as information clearinghouses for mainstream news, academic studies and independent sources of journalism about the nuclear crisis in Japan.
Given this wide perspective, it is hard to see how any meaningful progress is being made at the Fukushima Nuclear Power Plant (FNPP). This is the conclusion I drew, or anyone with reasonable skills of observation would have drawn, in April of 2011. The Japanese government kept telling us that "everything is under control" and there is "no immediate danger," all the while, lying through their teeth about the reactor meltdowns.
Any intelligent layperson who considers the technical aspects of the disaster will be at a loss as to how the plant operators will be able to restore the cooling system, which may be badly damaged, to reactors that themselves may be unrepairable or in various states of melt-down. If the nuclear fuel in the reactors has melted through to the floor, what would be the point of setting up a cooling system to a dysfunctional reactor and a pool of melted fuel? No one in the government clearly answers these questions nor has the international community come forth with a possible solution. (1).
Credit must be given to the hard work of engineers and makeshift cooling systems were installed, but the state of the reactors is precarious–highly radioactive–and things have not gone smoothly for plant operators, Tepco. As for long term solutions, none are presented. We are supposed to believe that out of this gigantic mess of strewn rubble and constantly leaking pipes and cooling systems, progress is being made. At some level there is: as long as the melted fuel keeps cooling and there are no other major earthquakes, the level of radioactivity will naturally decrease. But this is a hypothetical, best-case scenario.
The fuel pools of Units three or four could collapse in another large earthquake and the highly radioactive fuel rods will not be removed until 2013 at the earliest– putting the entire world in grave peril every second that ticks by.
Nuclear expert, Arnie Gundersen, recently stated regarding units 1 – 3 that they will "get to the point where they throw some concrete down on the top of it and come back in 300 years." Gundersen thinks this may not even be cleaned up in "500 years!" (2) This bears repetition:
It's no wonder nuclear watchdogs have created a special rating system for Fukushima– putting it in a new category, above Chernobyl, as a no. 8 level nuclear disaster. Fukushima is a "[m]ulti-source major nuclear accident requiring international assistance and monitoring" (3).
A Few Quadrillion Becquerals Here, A Few Quadrillion There…
Meanwhile in Tokyo the Japanese government admits that the incineration of radioactive debris shipped from the tsunami disaster zone, from 2011 to 2013, will emit at least 2 billion becquerals of radiation into the air (according to my calculations) (4; 5). Yes, you read that correctly: TWO BILLION. Compared to the FNPP disaster that is not much at all, that number could end up being lower, or even much higher, depending on how much debris is burned, how radioactive it is, whether the equipment malfunctions, and so on. The curious point is that the Japanese government admits they are intentionally emitting radiation into densely populated urban environments.
Nominally, this policy is "to help the people in the Northeast" (or more likely to help their buddies in the incineration business). This is sheer insanity, but these are the times we live in, when even Japanese school children are being given pamphlets "full of misleading information and half-truths" about the safety of burning radioactive debris (6).
The government's heartfelt concern for the inhabitants of the northeast is touching. But after 17 months there are still evacuees living in classrooms partitioned with cardboard (7) and rumors of many people dying from cancer due to radioactive fallout. This has gone unreported in the establishment press (8).
Meanwhile, the situation at the FNPP is still unstable. Tepco has admitted that,
a total of about 10 million becquerals per hour of radioactive cesium was being emitted from the No. 1 to No. 3 reactors as of June. That is about one-80 millionths of the level that was being spewed immediately after the accident (9).
This is down from a peak of thousands of trillions of becquerals at the time of the reactor explosions (10; 11). Measured as quadrillions or as petabecquerals (10 to the 15th power) (12), the radiation emitted was comparable to Chernobyl, being well over half if not roughly equivalent in volume (13). While the worst Chernobyl had to offer was pretty much over once it had blown its lid, Fukushima could still release vastly greater amounts of harmful radiation due to the nuclear fuel at the site.
The Unimaginably Unimaginable Danger Of Being (Nuked)
Although the government continues to dismiss the idea that the quakes themselves were the main cause of the nuclear meltdowns, while attributing the entire crisis to the "unforeseen" natural phenomenon of the tidal wave, they admit the quake caused "a 3-square-centimeter rupture in the piping of the emergency cooling system for the No. 1 reactor." In addition, they note "the possibility that tremors from the earthquake created a tiny rupture of 0.3 square centimeter or less, which later grew larger when the reactor temperature and pressure rose and radioactive substances leaked from there" (14).
This is controversial given that independent scientists are not allowed to inspect the facilities and that witnesses saw the Unit 1 building collapsing before the tsunami arrived.
One worker, a maintenance engineer in his late twenties who was at the Fukushima complex on March 11, recalls hissing and leaking pipes. 'I personally saw pipes that came apart and I assume that there were many more that had been broken throughout the plant. There's no doubt that the earthquake did a lot of damage inside the plant,' he said. 'There were definitely leaking pipes, but we don't know which pipes – that has to be investigated. I also saw that part of the wall of the turbine building for Unit 1 had come away. That crack might have affected the reactor' (15).
In addition to the accumulation of evidence that the earthquake itself was a primary cause of the meltdowns (16; 17) — something the industry does not want to admit — there are other inherent flaws in the way nuclear power plants are built and operate. Gundersen points out that the service pumps failed because they were flooded by the tidal wave on 311.
These pumps send water from the ocean to cool the back up diesel generators (18). Gundersen (at 19:00 mark in audio): "There could have been 14 meltdowns and not three. If you look at the data, there were six units at Fukushima Daiichi [power station no. 1], there are four at Fukushima Daini [station no. 2], three at Onagawa and one at Tokai. The net affect is that there were 37 diesel generators between those plants. 24 of those diesels were knocked out by the tsunami. You need the diesels to cool the plant."
This occurred because at FNPP no. 1 the tsunami flooded the actual diesel generators, but at the other plants the "tsunami knocked out the cooling water to the diesels, something called service water. So, Japan narrowly missed 14 meltdowns and not three because the cooling water to 24 of the 37 diesels was destroyed."
This bears repetition: JAPAN NARROWLY MISSED 14 NUCLEAR MELTDOWNS
Furthermore, it was sheer luck that there were not eight meltdowns, for another totally different, random, reason:
The plant manager at Fukushima Daini, which is six miles away from Daiichi, is quoted as saying that if the tidal wave happened on a Saturday his four units would have melted down too. He had a thousand people on site because it was a Friday, but if it happened on a weekend there would have been a skeleton crew there. The roads had been destroyed so nobody could have gotten in to help, and we would have had Fukushima Daiichi and Daini in meltdown conditions. What happened was almost unimaginably unimaginable.
To repeat: had the earthquake happened on a Saturday or Sunday there would have been eight instead of merely three meltdowns– you can't make this stuff up, folks.
The FNPP site is fraught with danger, with constant reports of highly toxic water leaking from this pipe or that, or this reactor or that. For example, water in Unit 2 turbine basement was found to have 47 million becquerals per liter (19). These sorts of conditions are common. Many engineers are "highly suspicious" of government assurances that things are going well. For example,
"Takahashi Kei, a former cooling system worker at the plant now working as a radiation survey volunteer, said the utility company's executives are portraying the situation in the best possible light. 'There are leaks everywhere, wreckage too. It's not as simple as they portray,' he said."
Japanese nuclear expert, Hiroaki Koide, recently said that "The state of the reactors is still deteriorating" (20). Let's repeat that for the audience at home:
This hardly sounds like a successful "cold shutdown" and tends to support Gundersen's idea that the units 1 – 3 will have to be entombed in concrete (if not with Japanese parliament member's tempura, leftover from their extravagant taxpayer funded banquets). Recently there is talk from engineers who have intimate knowledge of the FNPP situation, and even from the government, that Japan needs to recruit help from the international community of scientists and engineers (21; 22; 23). Hey! Good idea, let's hope they don't wait too long. After all, this disaster is not only Japan's fault, but an international issue from start to finish.
The lesson yet to be learned is that nuclear power is inherently dangerous and that the consequences for humanity and the environment continue to be "unimaginably, unimaginable" in their size.
You can support this information by voting on Reddit HERE
Richard Wilcox has a Ph.D. in Environmental Studies from a social science, holistic perspective. He teaches at a number of universities in the Tokyo, Japan area. His articles on the Fukushima nuclear disaster have been published at Counterpunch, Global Research, Dissident Voice, Activist Post, Zen-Haven, and Rense.com. His most recent interview with Jeff Rense is available at the website www.rense.com. Many of his environmental articles are archived at:
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