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Lists sites offering historical information related to or about this locality. Sites specifically for Historical Buildings would be listed in Arts_and_Entertainment/Architecture/Historic_Buildings if available.
Subcategories 2
Related categories 1
Sites 15
Archives Association of British Columbia
Provides information on the Archives Association of British Columbia. Listing of online historical resources about the province including vintage photographs and virtual exhibits.
British Columbia History
A directory of Internet resources detailing the history of this province. Almost all historical disciplines are represented.
Cassiar... Do You Remember?
A virtual community of the now-closed asbestos mining town of Cassiar. Includes history, photo archives, search page, newsletter and related information.
Chinese Canadian Historical Society of BC
Founded in 2004, aims to encourage research, documentation and promotion of Chinese Canadian history in the province. Offers membership information, scholarships, event listings, articles and photos.
Heritage BC
Aims to conserve historic buildings and other heritage resources. Offers on-line guide to BC heritage sites and services, activities, advice on maintenance and conservation of historic buildings.
The Jewish Museum and Archives of BC
Archives and resources which include study guides, news and publications lists and a pictorial time line of Jewish settlement from 1858 to the present.
Kootenay, an Exploration of Historic Prejudice and Intolerance
Provides a look behind the peaceful facades of Kootenay towns in the late nineteenth and early twentieth centuries, when the forces of prejudice and intolerance were an everyday occurrence.
Marine History of the Comox Valley, British Columbia
Highlights a timeline of events, photos and a bibliography.
Mennonite Historical Society of British Columbia
Provides information about membership, events, family histories and genealogical resources.
North Shuswap Historical Society
Has been documenting and publishing the human and natural history of the Shuswap Lake area of the southern interior of British Columbia in its journal "Shuswap Chronicles" since 1985.
Okanagan Archive Trust Society
Historical and vintage photos from all around Canada, with a special focus on British Columbia and the Okanagan region. Offers profile, gift shop, photo archives and quarterly newsletter.
Okanagan Historical Society
Has been documenting and publishing the human and natural history of the Okanagan Valley of British Columbia, for over 70 years.
Rolf Knight
Rolf Knight regional history books available for free download. Writer was recipient of a Canadian Historical Association's award.
Time Travel BC
Showcases heritage attractions around the province. Offers news, event calendar and links.
Town of Kitsault
Photographs and history of a ghost town that was structured around a molybdenum mine, built in 1979 and abandoned in 1983.
Last update:April 9, 2016 at 4:33:39 UTC
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CLG knocked Gambit Esports out of StarSeries S3
The next team coupled with MVP.Project, who were eliminated from SL i-League CS:GO StarSeries S3 at the 12-14th place, is Gambit Esports. The team was defeated by the Americans from CLG in an elimination-match.
Zeus' team leaves SL i-League StarSeries S3
The game passed on Cobblestone. Gambit Esports made a good start and quickly started to earn the round-advantage, but CLG saved themselves from a devastating loss in the first half by a well-timed tactical pause, after which the NA-team played back to 6-9.
Switching to the T-side, Counter Logic Gaming continued their win-streak and earned six match-points shortly. Only the last one of them was gotten by CLG, and as a result, Gambit lost this match.
Gambit Esports finishes at the 12-14th place and takes home $4,000. In turn of CLG, they will continue to fight for the spot in the Playoffs of SL i-League StarSeries S3.
The match between Virtus.pro and fnatic is the next one to be played. You can watch this game on starladder_cs_en.

subset: commoncrawl


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04 Nov Debt and Investing
Debt and Investing go hand in hand, if you are in debt you really shouldn't invest and if your investing successfully then you probably are not in debt.
At Cansliming we do not believe in debt. As an investor we look for stocks with little to no debt so why should our personal affairs be any different? When you are in debt you are holding risk, if you lose your source of income your debt is a massive risk. If you lose your house, car or other assets you are going to have to work doubly hard to get those items back, and in many cases you will need to get those items back. So trying to keep a level head while investing, if you have money to do so, will be nearly impossible.
I have seen investors that have debt and lose a job or are wiped out for some reason and they take a long time to recover because of their house payment, 5 car payments and the like. I have also see people with no debt take a hardship in relative stride. If you are trading stocks you should make a definite effort to relieve yourself of your debts including your house!
Now I know as a trader you think you can earn your way out of your debt, habits and shortcomings. However the only thing that can get you out of debt is your mindset, and once you get your mindset right then the rest will come easy. Its amazing what can happen when you finally get focused on a goal and achieve it, or even if you havent achieved it yet the discipline that you will gain from working towards a personal goal will effect you in other aspects of your life. As you get more disciplined you will automatically be a more disciplined person, and you brain will find ways to keep you on the disciplined path. You may lose weight, sleep more and be on time to more things just because you started to work on a great personal habit.
Well what does this have to do with Canslim you ask! Well EVERYTHING.
If you know of William Oneil then you know that good personal habits are part of his trading style, it isnt spelled out in his books however he is known for looking down on traders that have large ego's and for people that cant stand back and look past themselves. It is known that his traders would be looked down upon if they drove a Ferrari to work, not just because its bad for resale value but because it implies something about that person, that they probably have a tendency to be selfish. That same mindset to not have a large ego, not show off is the same personality traits that you need to have to not get into trouble with debt. It doesnt matter if you make $50k per year or $500k per year you can get buried or become free depending on your debt level.
When you have debt, in the back of your mind you know that you NEED to make money, that thought process skews your judgement and can change your trading style. If you have bills to pay then you will always want to trade, sometimes even forcing trades with little risk reward just because you have a house payment coming up. When you are relieved of that pressure you can open up your mind and trade clearly, because as traders we are training ourselves to look logically, clear emotion and view objectively and these are hard to do when your wife is wondering if your next trade is going to be profitable.
So do the right thing, grow a little slower, take some of that capital and pay off that debt that is a risk line on YOUR balance sheet, make yourself look like a company that you would want to invest with.


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improve upon the first table.
For reasons out of my control, both tables include maple in the species mix, even though the client specified deep, dark colors in a striped table, "like a Wine Wing, but random". Rather than use stain to darken the maple, I chose to use Trans-Tint water borne dye.
This time around, I used American Black Walnut, the same beautiful quilted cherry I used in the original table, and some nice hard white maple. I darkened the whole table with a fairly strong mix of Golden Brown dye, which darkened the maple, but really just changed the tint of the walnut and cherry. Once this had dried, I was confronted with the same problem as last time: the cherry and maple were similar in color. So I masked off the maple, added a shake of "cherry" powder dye to the Golden Brown mixture, and applied it lightly to the cherry plank.
The resulting color is intense, for sure. If I were looking at this table top a year ago, I would have sanded off the dye and started again, because the cherry color is so vibrant as to not look completely natural. But I think that when people see this table, they won't see walnut, maple, and cherry. They'll see chocolate, umber, and wheat colors. And because the dye isn't covering any of the beautiful wood grain, it does look natural.
This table top is making me love dye all the more. And it's also making me love making table tops!
Here's the top being glued up. I used the X31's 12 inch jointer to dress the wide boards for glue up. This is my first time gluing up boards wider than 6 inches! This gives the table a great look that you just can't get with a narrow jointer.
Here's the top, planed and sanded smooth, with wood putty filling in around the knots in the walnut board.
Here it is with the knots filled in, ready to be dyed
And here it is, dyed and with a coat of 100% wax-free clear shellac
This table really shows off the striking figure of the walnut and cherry pieces. As for the maple: slight imperfections that expose end grain suck up dye in maple, and can cause speckling. Also, invisible figure springs forth when dye is applied to maple. Star patterns, whorls, and the like, will all emerge from hard maple. It changes the appearance of hard white maple from pure, bone white, to a more rustic, varied, almost wild (but still sparse) figure. I like it, especially juxtaposed under the hard clear topcoat these restaurant tables require.


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Bristol Jewelers
|B Delicious - Beaded Jeweler in Bristol
|0117 929 1789
|B Delicious beads offers an exceptional and fascinating shopping experience for lovers of beaded jewellery. Our array of beads, findings, feathers and trims ensures you'll find what you need to make your own jewellery, or commission us to make up your design. Tutoring in basic and advanced techniques is available and we can provide free helpful advice. Parties for adults or kids can be booked and we provide workshops to clubs and schools.www.bdeliciousbeads.co.uk
South West England › Bristol › Bristol › BS8 1EY 2 Triangle S
|Shopping › Jewelers
|Nailsea Jewellers - Gold Jeweler in Bristol
|01275 810383
|Nailsea Jewellers is an independent family business set up in 1995. The shop is run and run on the basis that individual friendly service is the key to success by attracting regular clients time and time again. The huge multiples have central buyers for all of their branches. This matters that the only goods you can purchase are what is in the shop.www.nailseajewellers.co.uk
South West England › Bristol › Bristol › BS48 1AW 67-69 High Street
|Shopping › Jewelers


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Exhibit & Sponsor
Interested in exhibiting or sponsorship opportunities at the 2019 show?
Following a hugely successful launch of The Telegraph Travel Show in January 2016, we returned stronger than ever with an increased turn out of 29,294 visitors and an exciting range of features such as our Destinations Theatre and Travel Genius Bar.
With 4.6 million monthly unique users on The Telegraph Travel website and a UK audience that spent more than £15.5 billion on travel last year (more than any of its quality competitors), The Telegraph Events is ideally placed to bring readers and advertisers together in a live environment with an aim to produce the UK's biggest travel show.
- 29,294 visitors (15% growth YOY)
- Average age 58
- 45% female, 55% male
- £66,000 average household income
- Visitors spent on average £3,410 per person per holiday at the show
- Average dwell time of 3 hours 30 minutes
- 85% visit the show to meet travel brands
- 48% are seasoned cruisers
- 2/3 do not visit any other cruise shows
- 56% were first time visitors to the show
The TELEGRAPH TRAVEL READER STATISTICS**
- Largest travel section of any national newspaper
- UK audience spent £15.5 billion on holidays last year
- Take 8+ holidays a year
- 4.6 million unique users to the website per month
- 79% of The Telegraph audience are brand loyal and exclusive
Speak to our team about stand space options and sponsorship opportunities.
Neil Worrall
Group Sales Manager
Tel: 020 7931 3965
Email: firstname.lastname@example.com
Lucy Stott
Sponsorship Manager
Tel: 020 7931 3035
Email: email@example.com
James Bishton
Senior Sales Executive
Tel: 020 7931 3964
Email: firstname.lastname@example.com
Jeff Blackmore
Senior Sales Executive
Tel: 020 7931 3283
Email: email@example.com
Helen Bowden
Senior Sales Executive
Tel: 020 7931 3990
Email: firstname.lastname@example.com
We've really enjoyed the Show this year, the setup is excellent and there's a nice flow. Silversea will certainly be back next year.Christian Walter, Expedition Expert - Silversea Expeditions
We chose The Telegraph Travel Show as we wanted to showcase our company at what we think is one of the best travel events. We were not wrong, we have had an amazing response to us being there and therefore chose to come back for 2018.Audrey O'Donnell, Sales Marketing Executive – Sealand Villas


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Status: Open
Know more about this business than we do? Cool! Please submit any corrections or missing details you may have.Help us make it right
Be the first NOLA.com user to add photos or videos of Storybook Florist
I have used Storybook for almost 15 years. They always deliver on time, and make beautiful arrangements. If you are looking for a totally ...
Storybook Florist can be found at Jewella Ave 8035. The following is offered: Florists. The entry is present with us since Sep 9, 2010 and was last updated on Nov 14, 2013. In Shreveport there are 27 other Florists. An overview can be found here.
Storybook Florist is located at 8035 Jewella Ave, Shreveport, LA. This location is in the Jenkins Subdiv., Pinecroft Subdiv. neighborhood. This business specializes in Gifts and Florists.


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The issue of what to do about the 11 million illegal immigrants living in the United States has taken center stage with President Obama and Congress firing the opening salvo in their efforts to overhaul the nation's immigration laws. The discussion has focused on making efforts to better secure the country's border with Mexico a priority.
But many Latino leaders say the time has come to finally place illegal immigrants, many of whom are Latinos, on a path that would make them lawful citizens. As Mr. Obama said, the debate over the immigration plan will promise to be an emotional one. It also shines a spotlight on the changing face of America and what that means for the country, a theme that has persisted throughout history.
City Room was reminded that more than 100 years ago one of America's greatest poets, Walt Whitman, offered his own reflection of the nation's shifting population and in particular the role of people of Hispanic origin. In 1883, Whitman had been asked to participate in ceremonies marking the 333rd anniversary of the founding of Santa Fe. He could not attend, but instead sent a letter — published in The New York Times on August 7 of that year — to the organizers in which he discussed his views of what he called the "American identity" and the "Spanish stock" of the Southwest.
"It is certain to me that we do not begin to appreciate the splendor and sterling value of its race element," Whitman wrote of the Spanish-speaking population. "Who knows but that element, like the course of some subterranean river, dipping invisibly for a hundred or two years, is now to emerge in broadest flow and permanent action?"
Below is the full text of the letter.


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0 Flares 0 Flares ×
There, I said it and it's the honest to God's truth.
So many folks, especially those in the online marketing space, proclaim how awesome their lives are and how terrible it would be if they were to have a regular job.
I'm not sure if they do this because they have amazingly strong mindsets and they know it's better to think positively than to be negative or if they're just doing it to lull themselves into a false sense of inner peace. As if it will lessen the pain of the struggle by putting on a smile and pretending everything is awesome.
One thing I know for sure is that being an entrepreneur is NOT easy for anyone and it does require struggle.
Lately, I've noticed a lot of my peers admitting the struggle and saying they're tempted to quit.
Having just returned from 12 glorious days at the happy place on earth, Walt Disney World, I woke up this morning with the question burning in my mind "What if Walt Disney had quit?"
He certainly had many chances to quit. Walt had put heart and soul into each of his companies and wound going bankrupt something like 10 times. He "failed" to get funding for Disneyland numerous times. There are dozens of books written about the man and all the ones I've read so far shine a light on his struggles.
Walt learned some things the hard way, just like you and I. He created a character called Oswald the Lucky Rabbit but due to the fact that he didn't fully understand copyright law at the time, he lost the rights to the character to the studio he was working for at the time. That might have been enough to cause a lot of people to just throw in the towel right then.
If Walt hadn't persisted, there would be no $207.8 billion Disney empire. More importantly, there would be no Disneyland, no Walt Disney World, and none of the the wonderful Disney movies, records or animations would exist.
If Walt Disney had quit, the world would never have know how brilliant he truly was. If you quit, the world will never come to learn how brilliant YOU are.
Do you feel stuck and discouraged?
Maybe you just haven't found your "thing" yet. Maybe the current challenge you face is just there to push you to ask better questions or to learn something you might have just skipped over.
When Walt created Oswald The Lucky Rabbit but failed to protect his intellectual property rights, it taught him to learn how to do just that. It also pushed him to create even better characters with unique personalities. You know like Mortimer Mouse…maybe you know him as Mickey Mouse.
I'm not exactly why these struggles and challenges have to put in front of entrepreneurs so frequently and readily, but I honestly do believe it happens for a reason. It happens because we're not "done" yet and heroes don't quit until they're "done".
You have no limits except those you choose to place on yourself. You may experience more struggles the harder you push and the bigger your dreams. Please don't back away from it. Rather, embrace it and see where it takes you.
I believe our struggles are put before us to test the size of our dreams. If Walt Disney had dreamed to become a cartoonist, he would have achieved that dream way back in 1919 when he worked at the Posman-Rubin art studio for $50 a month.
Thankfully Walt dreamed bigger dreams and faced bigger challenges so he could create far more amazing things that he was creating at that studio.
Whatever you're facing now will pass.Think…where do you want to go next? What do you really want to achieve?
Don't lose hope and don't quit…you might be a lot closer than you think and the world needs to know your brilliance.


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Genre(s): Puzzle Games, Added by : soruman, Feb 21 2010 10:24,
Tags : puzzle
Tags : puzzle
EmotiPleX is a strategic puzzle game consisting of sliding emoticons(/smileys) in a varying assortment of different puzzles. The goal of each puzzle is to eliminate all emoticons by grouping them into rows or columns of 3 or more. Most of the puzzles advance in difficulty as you progress between levels. There is an option to submit your score located directly after the last listed puzzle in the puzzles-list.
Good luck & have fun!
Play EmotiPleX (External Link)Feeling lucky? Play a random game
Please rate this game!
Rated 0.0 out of 10 based on 0 votes
Thanks for your interest!
Thanks for your interest!


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For 30 years, FACTS has helped schools maintain financial stability and affordability by offering the best payment plan solutions in the nation. Our commitment to Pre-K–12 private and faith-based education guides us in everything we do. For more information, preview our brochure.
The FACTS Dashboard lets you manage your financials at-a-glance
Match financial aid awards to families' payment plans through our integrated systems
Place multiple students on one agreement
Bill parents for tuition and all incidental fees
Create online forms for event registrations, permissions, field trips, athletics, and more
Track student expenses and credits in a single system
We remit funds to your school weekly on the day of your choosing
Full custom reporting and delinquency prevention included at no cost
Easy payment-plan signup (online or paper)
Multiple payment options (automatic debit, credit card, mailed payments, mobile payments, web payments, 24/7 phone; families can also pay monthly, quarterly, or by semester)
Dynamic web chat and 24/7 live-agent customer service—not an outside call center
FlyWire (PeerTransfer) integration to accept international payments with ease
Intuitive online account maintenance
View account status and make payments from any mobile device
FACTS has partnered with CathoNet—the leading provider of QuickBooks® cloud-based accounting—to change the way accounting is managed at your school. FACTS and CathoNet give you a complete view of your school's revenue stream in one system. The more families you have on the FACTS system, the easier accounting is for your business office.


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Thanks for helping us sort this video!
Thanks for helping us associate the correct Pornstars to this video!
Aidez-nous : ces acteurs/actrices porno apparaissent-ils/elles dans cette vidéo ?
Pornstar Name:
Who is the girl at 7:07? Anybody have any info?
I know her real name but I want her name as an actress
Who is girl no. 2?
whos 1st girl?
The girl at 28 seconds... I MUST have this scene. PLEEEEEEASE!
who wants a facial? msg me.
i want cum everywhere
Please find out the scene of the cumshot at 0.28!!! PLEASE!
who's the 3rd girl? seriously holy hell MORE!
scene at the end is one of my favorites
Second girl´s name please.
i want a facial
whos the girl at 2:45?
nunca habia visto tantos finales felices
2:05 Very funny.
Vannesa Lyn is the girl.
whose the 2nd girl?
whats the name of the girl at 4:00?
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₹ 1870.00
Inclusive of all Taxes FREE Shipping* 0 - 3 Days Delivery Cash on Delivery Available Easy Return & Refund
About Blue & Orange Jacket & Shirt For Boys ( 2-3 Years)
OKS BOYS presents this blue & orange colored combo that will be a perfect pick for your little boy. Fashioned from cotton blend, this regular-fit combo includes a shirt and sleeveless jacket. Team this combo with jeans or trouser to lend him a smart look. Material : Cotton Blend Wash care : Mild Wash, Do not Bleach Age Range : 3-4 Years


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My admiration is boundless to the vast, nay, I'd say, encyclopedic knowledge of the readers and commenters to this blog. Yet again Speeedicus triplicatum leads when he says in comment to THIS blog article,
I've never found much online about the 4 Barrows next to the Red Road …..
He continues to add this wonderful piece of history about the bowl barrow site,
… The [Surrey Wildlife Trust information board] by the barrows always makes me smile when it waxes lyrical about the 'tool marks' on a nearby Sarsen allegedly made by Bronze age masons … actually, the Stone was trundled down from the A322 Roundabout construction in the 1970s by a JCB with sharp teeth in its Bucket !
Couldn't resist Speedicus's implied challenge. After some time googling, here's what I've discovered about the burial mounds,
- The Chobham website has some information on burial mounds in our local area
- The Makers of the Heath by Iain Wakeford has a cracking photo, though focus is on Woking, useful none the less
- Surrey barrows 1934-1986: a reappraisal by Leslie Grinsell, who surveyed the barrows in 1932, is the authoritative source, though a somewhat dry academic description. [Note: Click on Accept to download the PDF file]. Oh, and his report says there are 12 such barrows in Surrey Heath. But where? More work for me to do methinks.
Below are photos of [click to expand], of the barrows, the information board, the sarsen stone, an aerial photo from the 1930's [my, how things have changed], and a contour survey 1930's survey,


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Mr. Diaw is a specialist on PPPs, with 10 years work experience in creating, financing, implementing and monitoring public infrastructure projects, combined with experience in the implementation of institutional and legal frameworks for PPPs and investment promotion.
From 2008 to 2012, he was responsible for a new toll highway PPP in Senegal. He followed the financial agreements between public and private partners, prepared the annual budget for the project, monitored the progress of the construction company, and wrote texts to improve the legal framework for PPPs.
He holds an MBA from the University of Leeds in England and public management certificates from Georgia State University, in the USA.


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generic setup
Apr 09, 2013
How to enable User Folders in Plone
User Folders are an option in Plone. You can turn them on In the Security settings area of Site Setup (Plone Control Panel). Here's how I enabled User Folders in Plone from within my product.
I needed to enable the User Folders feature of Plone from within my product. My first thought was to use a Generic Setup profile, but the solution was setuphandlers.py.
I inspected the Enable User Folders button on the Security settings page of Site Setup, and saw the attribute was named enable_user_folders. I tried to find a generic setup profile I could edit.
The closest I got was adding enable_user_folders to properties.xml. This turned the attribute on in the ZMI, but not in Site Setup and User Folders were not enabled.
Then I found a reference to
in a setuphandlers.py file from the Rhaptos git repo.So, I added these lines to setupVarious in my setuphandlers.py.
from plone.app.controlpanel.security import ISecuritySchema site = context.getSite() security = ISecuritySchema(site) security.enable_user_folders = True
Now, when I install my product, User Folders are enabled automatically.
Note that you need to make sure setupVarious is turned on in configure.zcml.
<genericsetup:importStep name="your.package" title="your.package special import handlers" description="" handler="your.package.setuphandlers.setupVarious" />
Hope this helps someone.
Jun 22, 2010
Injecting Plone variables into javascript
Step 1: Create a class to output the javascript
Step 2: Create a browser view pointing to the class
In src/my.product/my/product/browser/configure.zcml, I added a browser view pointing to GlobalJS, gave it a name, and added a permission. Note that the name of the file containing GlobalJS is CommonUtils.py
<browser:view for="*" name="global_js.js" class=".CommonUtils.GlobalJS" permission="zope2.View" />
Step 3: Register the view in javascript registry
Here, I register the browser view in src/my.product/my/product/profiles/default/jsregistry.xml. I needed access to portal_url before jquery was loaded, so I added the insert-before property. Note that the id is the same as the name registered in the browser view.
Now, global_js.js is loaded on every page and I have access to portal_url from within javascript.
Hope this helps someone.


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America Ferrera still learning comedy
America Ferrera may be a part of comedy TV series "Superstore" but she says she does not consider herself as a comedic actress and it is watching her co-stars in the sitcom that helps her with the performance. The Justin Spitzer-created series is about a group of employees working at a big-box store. Besides Ferrera, the show also stars "Saturday Night Live" performer Ben Feldman, Canadian comic actress Lauren Ash and comedian Colton Dunn among others. "Comedy is really great. Our cast has many true blue comic actors. I don't really consider myself as a comedic actor. I feel like the space is enriching for me, to work with all these actors who come from the world of comedy. I have learnt a lot about the realm of comedy by watching them," Ferrera said.
The 33-year-old actress, who rose to fame after starring in "Ugly Betty" TV series, has been a part of dramas like "The Sisterhood of the Traveling Pants 1 and 2", "The Dry Land" crime drama "End of Watch" and romantic comedy "Our Family Wedding". "I personally don't see myself as a comedic or dramatic actress. My background has always been pretty diverse in terms of tone and the type of things I have been involved in."
The actress says she does not find it difficult to handle both her producing duties and acting as she is blessed to have a collaborative team, who enjoy the creative process. "It wasn't challenging at all. Ours is a very integrated collaborative cast. We are always talking and collaborating. The direction is good, the characters are interesting. "It is a collaborative process. I enjoy it very much to be part of the creative process before shooting the episodes in front of the camera," she says.


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The Young Women's and Teenage Mothers Project was launched in November 2009 and is funded through BBC, Children in Need. The project delivers a variety of
personal development programmes and workshops (accredited and non accredited) to young women between 13 to 18 years old in a community environment.
It helps young women to explore any issues that they face in their life today and tries to meet the need of each individual through an in house and outreach service.
• Guide and support young women from all backgrounds through difficult challenges they face throughout their life. It offers them the chance to try new
activities, meet new friends and build on their personal development and team building.
• Offer young women the chance to participate in a range of high quality training programmes, covering all areas of health (mental, physical, sexual
and emotional).
• Supports young women to take ownership of the programmes, encouraging them to voice their opinions on what they would like to achieve.
• Encourages Teenage Mothers to increase their personal development and give them the confidents to seek guidance and support through their pregnancy/parenthood.


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Gone are the days when businesses simply rely on a plain old telephone system (POTS) to communicate with their workers and customer base. With the advent of digital transformation, updates and...
Blue vs Paragon VoIP
Compare Blue vs Paragon VoIP. Find out whether Blue or Paragon VoIP is better for your VoIP business or home needs. The experts at VoipReview have analyzed the strengths and weaknesses of Blue and Paragon VoIP and detailed analysis of the comparison can be found below.
User Ratings & Reviews
Paragon VoIP could be a paragon of VoIP quality - but they're new, so we're not sure. Their website also looks like it's under construction - which isn't a bad thing either. It does mean that it is hard to find information on them.
Provider Info
- Website:
- Headquater Country:
- Founder Year: 2003
- Website:
- Headquater Country:
- Founder Year: 2009
Plans Available*


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Doctor Who (1963)
1 question in season 8
Starring: Colin Baker, Jon Pertwee, Patrick Troughton, Peter Davison, Sylvester McCoy, Tom Baker, William Hartnell
Question: Why does this serial only survive in black and white. If it was made in colour, why did the BBC have black and white copies in the first place?Josman
Chosen answer: The reason this serial only exsists in black and white when it was recorded in colour is because in the 60's and 70's the BBC wiped and reused video tapes, some of which were Doctor Who. Luckily copies were made and sent to other countries, most of which didnt have colour TV's. These copies were later found and returned to the BBC archive.
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text:
Today was "Fat Tuesday" and the whole town shut down! Lincoln was sick and the pharmacy across the street was shut down and we couldn't get his antibiotics. Finally, Nick and John found one and all was well. Hopefully Lincoln will be back on his on his toes.
The schools let out early and we walked downtown to the parade...minus Nick and Lincoln!
As you can see, we had a great time. We got front row spots and the kiddos had a great time...and so did the adults! These germans sure like to have a good time!
Little Pebbles was at the parade!
A walk over to the parade!
Go Vikings! This guy was from Germany and had a Vikings jersey on so of course I HAD to get a picture!
Andrea and I at the parade!
Adults can have fun at parades too!
Our friend, Henry!
Lucy got to dress up for a party at school today and wanted to be a fairy!
Stats 2017 edition
1 year ago


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Contact Us
Browse by:
Dual gated power electronic switching devices
Dual gated power electronic switching devices
Patent Drawings:
(16 images)
Date Issued:
November 9, 1999
April 28, 1997
Driscoll; John Cuervo
(Raleigh, NC)
Primary Examiner:
Dutton; Brian
Assistant Examiner:
Attorney Or Agent:
Burns, Doane, Swecker & Mathis, L.L.P.
U.S. Class:
Field Of Search:
International Class:
U.S Patent Documents:
Foreign Patent Documents:
Other References:
Charles Belove, Handbook of Modern Electronics and Electrical Engineering, 1986, pp. 339-344..
A novel semiconductor switching device is disclosed. The switching device is designed and constructed to include, for example, a highly interdigitated cathode/gate structure on both anode and cathode sides. The semiconductor switching device can be multi-loaded on both anode and cathode sides which provides a great deal of flexibility in operation.
What is claimed is:
1. A semiconductor device comprising:
a first layer doped with an n-type dopant and electrically connected as a cathode;
a second layer, bordering said first layer, doped with a p-type dopant and electrically connected as a gate, wherein portions of said first and said second layers are etched away to expose a junction between said first and second layers;
a third layer, bordering said second layer, doped with an n-type dopant, and electrically connected as an anode gate, and
a fourth layer, bordering said third layer, doped with a p-type dopant and electrically connected as an anode, wherein edges between said second and third layer are rounded.
2. The semiconductor device of claim 1, wherein said first and second layers are etched so that said semiconductor device is optically triggerable by light incident on at least one of the anode and cathode.
3. A semiconductor device comprising:
a first layer doped with an n-type dopant and electrically connected as a cathode;
a second layer, bordering said first layer, doped with a p-type dopant and electrically connected as a gate, wherein portions of said first and said second layers are etched away to expose a junction between said first and second layers;
a third layer, bordering said second layer, doped with an n-type dopant, and electrically connected as an anode gate, and
a fourth layer, bordering said third layer, doped with a p-type dopant and electrically connected as an anode, wherein outer edges of said third and fourth layers slope inwardly toward a central portion of said semiconductor device.
4. A semiconductor device comprising:
a first layer doped with an n-type dopant and electrically connected as a cathode;
a second layer, bordering said first layer, doped with a p-type dopant and electrically connected as a gate;
a third layer doped with an n-type dopant;
a fourth layer, bordering said third layer, doped with a p-type dopant and electrically connected as an anode; and
a first switch for selectively opening said electrical connection to said cathode;
a second switch for selectively opening said electrical connection to said anode.
5. A semiconductor device comprising:
a first layer doped with an n-type dopant and electrically connected as a cathode;
a second layer, bordering said first layer, doped with a p-type dopant and electrically connected as a cathode gate;
a third layer doped with an n-type dopant and electrically connected as an anode gate;
a fourth layer, bordering said third layer, doped with a p-type dopant and electrically connected as an anode;
a first connection for shorting said cathode and said cathode gate; and
a second connection for shorting said anode and said anode gate.
6. The semiconductor device of claim 5 further comprising:
a switch in said first connection between said cathode and said cathode gate for selectively closing and opening said connection.
7. The semiconductor device of claim 6, wherein said switch is opened and further comprising:
a resistance connected between said anode and said anode gate.
8. The semiconductor device of claim 7, wherein said resistance is variable.
9. The semiconductor device of claim 5 further comprising:
a switch in said second connection between said anode and said anode gate for selectively closing and opening said connection.
10. The semiconductor device of claim 9, wherein said switch is opened and further comprising:
a resistance connected between said cathode and said cathode gate.
11. The semiconductor device of claim 5, wherein when said first and second connections short said cathode and said cathode gate, and said anode and said anode gate, respectively, leakage current is reduced within said semiconductor device suchthat said semiconductor device blocks voltage as a diode.
12. The semiconductor device of claim 5, further comprising:
a variable voltage disposed between said anode and said anode gate.
13. The semiconductor device of claim 5, further comprising:
a diode disposed between said cathode and said cathode gate.
14. The semiconductor device of claim 5, wherein said cathode is disposed on one said of a semiconductor wafer and said anode is disposed on another side of said semiconductor wafer.
15. The semiconductor device of claim 5, wherein at least one of said cathode and said anode have a continuous metallization pattern which is serpentine in shape.
16. The semiconductor device of claim 5, wherein at least one of said cathode and said anode have an emitter center line which is less than a single diffusion length from a gate portion of said semiconductor device.
17. A semiconductor device comprising:
a multilayer semiconductor doping structure;
a first switch for selectively opening a first emitter;
a second switch for selectively opening a second emitter;
a third switch for selectively connecting said first emitter to a first gate; and
a fourth switch for selectively connecting said second emitter to said second gate.
18. The semiconductor device of claim 17, wherein at least one of said first, second, third and fourth switches is fabricated as a transistor within said semiconductor device.
19. The semiconductor device of claim 17, wherein at least one of said first, second, third and fourth switches is external to said semiconductor device.
20. The semiconductor device of claim 17, wherein when said first, second, third and fourth switches are closed, leakage current is reduced within said semiconductor device such that said semiconductor device blocks voltage as a diode.
21. The semiconductor device of claim 17, wherein when said first and second switches are closed, and said third and fourth switches are open, said semiconductor device operates as a thyristor.
22. The semiconductor device of claim 17, wherein when said first and second switches are open, and said third and fourth switches are closed, said semiconductor device operates as a PIN diode.
23. The semiconductor device of claim 17, wherein said third and fourth switches can be closed to transition said semiconductor device from operation in a thyristor mode to operation in PIN diode mode.
24. The semiconductor device of claim 17, further comprising:
a fifth switch for selectively shorting said first and second gates together.
25. The semiconductor device of claim 24, wherein said third and fourth switches are DMOS FETs and said fifth switch is an IGBT.
26. The semiconductor device of claim 24, further comprising a voltage applied across the first and second emitters, wherein when said fifth switch is closed charge injection occurs from both said first and second emitters.
27. The semiconductor device of claim 17, further comprising:
a variable voltage disposed between said second emitter and said second gate.
28. The semiconductor device of claim 17, further comprising:
a diode disposed between said first emitter and said first gate.
29. The semiconductor device of claim 17, wherein said third switch is closed, said fourth switch is open and further comprising:
a resistance connected between said first emitter and said first gate.
30. The semiconductor device of claim 17, wherein said third switch is open, said fourth switch is closed and further comprising:
a resistance connected between said second emitter and said second gate.
31. The semiconductor device of claim 30, wherein said resistance is variable.
32. The semiconductor device of claim 17, wherein said first emitter is disposed on one said of a semiconductor wafer and said second emitter is disposed on another side of said semiconductor wafer.
33. The semiconductor device of claim 17, wherein at least one of said first and second emitters have a continuous metallization pattern which is serpentine in shape.
34. The semiconductor device of claim 17, wherein at least one of said first and second emitters have an emitter center line which is less than a single diffusion length from a gate portion of said semiconductor device.
The present invention relates generally to power circuits and systems and, more specifically, to power electronic switching devices.
Power electronic systems have many applications in today's technologies, such as motor drives and pulse power systems. As an example, consider the systems used to ignite turbine engines on aircraft, which systems are commonly referred to asexciters. Turbine engine ignition exciters have evolved considerably since their inception in the 1950's. First generation ignition exciters incorporated vacuum tube spark gap switching devices and vibrator type chopper, or DC-DC converter circuits. Given the severe operating environment of a turbine engine, i.e., high vibration, temperature extremes and widely varying input voltage and load impedance conditions, considerable effort was expended by the industry to develop highly reliable firstgeneration components and circuit configurations.
Second generation ignition exciters were typically characterized by replacement of spark gap switching technology with a semiconductor switching device. These exciters commonly utilized three terminal (thyristor) switching devices to accomplishswitching. This technology offered more precise spark timing and communication with an electronic engine control computer since feedback information could be effectively processed by the exciter charge pump (DC-DC converter) section. This provided asignificant improvement over first generation devices, affording aviators considerably more control over the engine ignition process.
Conventional solid state ignition exciter circuits generally fall into one of two distinct categories. The first category being characterized by a series stack of switching devices to evenly distribute or divide the high (approximately 2-4 kV)tank capacitor voltage across each device. Such exciters incorporate elaborate voltage divider networks to protect and trigger the series ganged semiconductor switching devices from electrical imbalances generated during both the capacitor charge anddischarge cycles. During the capacitor charge cycle, voltage must be evenly distributed across each device to prevent catastrophic failure of the entire series ganged semiconductor switching network. Likewise, during the discharge cycle, a seriesganged back bias diode network is required to protect the switching devices from ring back which results during igniter plug firing. Circuits using this type of circuitry require careful screening and matching of thyristor leakage current and similarcharacteristics to ensure proper operation at elevated ambient temperatures. Moreover, this technology is electrically inefficient since the combined losses of several individual switching elements (during turn on and on-state) are very high.
By contrast, a second current circuit design philosophy incorporates a single thyristor switching device operated at a comparatively lower (0.4-1 kV) tank voltage. This approach offers considerably higher efficiency than the first designphilosophy since only a single (VI) loss is incurred rather than multiple losses experienced with the aforementioned series ganged approach. However, this benefit is quickly offset since the tank capacitor voltage must be significantly lower than theseries ganged approach to avoid using "hockey puck" type switching devices. While "hockey puck" type switches would offer adequate voltage ratings, their considerable bulk, weight and limited di/dt capability preclude their use in pulse discharge typecircuitry. Therefore, current designs tend to utilize roughly 1,500 volt rated (phase control type) thyristors with correspondingly lower tank voltage.
To date, both types of solid state semiconductor switch exciter circuits have incorporated off-the-shelf, commercially available, phase control type thyristors. These devices, while readily available in commercial markets, are designed primarilyfor 60 Hz power control applications. Consequently, the dv/dt and di/dt ratings of these devices is limited with respect to requirements of a pulse power discharge application. The following summary provides a background of various thyristortechnologies conventionally available for switch exciter circuits, as well as other power electronic applications.
Phase-Control Thyristors are designed to maximize the silicon for use as active emitter area at 60 Hz AC. The devices have large, shorted emitters (for high dv/dt) with single-point center gates, and depend on the relatively slow plasmaspreading to turn on emitter areas remote from the point center gate. Researchers have extensively examined the spreading velocity by viewing radiative recombination of the plasma. Despite comprehensive research, spreading resistance of conventionaldevices necessitates low (e.g., less than 200 A/.mu.S) di/dt performance.
Inverter Thyristors have distributed or interdigitated gates (for high di/dt), similar to transistor emitter patterns, to turn on and utilize larger initial areas of the emitter for faster turn-on. For faster turn-off, heavy gold or platinumdiffusion and/or electron radiation reduce carrier lifetime, thereby reducing thyristor turn-off times (tq). Unlike transistors, inverter thyristors have heavily shorted emitters to prevent latch-up when dv/dt is being applied. These inverter designfeatures allow thyristors to be used at high (up to 10 kHz) repetition rates, but at the expense of high forward voltage drop. High forward drop severely limits performance of these devices in turbine ignition applications since increased (VI) powerloss accelerates onset of thermal runaway, limiting upper temperature performance.
Gate Assist (GATO) and Gate Turn-Off (GTO) Thyristors have npn regions which are designed like high-speed transistors, where the gate (or base) is used for charge-control functions. In GATO closing switches, the gate is used to extract chargefrom the gate emitter junction during the tq and dv/dt switching interval. This allows high rep-rate performance without the adverse on-state voltage trade-off of lifetime-controlled inverter SCR's. The disadvantage of GATO's is the requirement fornegative gate bias and current during the off-state and commutation interval, which considerably increases the complexity of exciter (thyristor) triggering circuitry. Gate Turn-Off Thyristors (GTO's) are similar to GATO's but must be lifetime controlledto act as opening switches. GTO's are made with both symmetric and asymmetric structures. Asymmetric GTO's are made both with and without anode shorts. The best turn-off gains for GTO's are obtained with shorted anode, asymmetric structures. So far,some of the highest di/dt pulse power closing switches have been GTO-type structures. These GTO emitter structures are ideally suited to receive and distribute high turn-on gating currents. If opening is not required, the highest possible hole-electronlifetimes will lead to the lowest possible on-state voltage. Therefore, GATO is perhaps the best conventional semiconductor switch structure for pulse-power applications such as turbine engine ignition systems.
MOS-Controlled Thyristors (MCT's) are integrated arrays of paralleled GTO cells (on the order of 20 micron spacing), with complementary FET's connected from anode to gate and gate to cathode. All of the cells have turn-off FET's that act as gatecathode shunts during turnoff and during the off-state. Some of the MCT cells have turn-on FET's connected from anode to gate. For those turn-on cells having their own anode-gate FET, the upper-base spreading resistance under the emitter is low, andgood gate emitter injection is assured for good di/dt. However, not all cells have turn-on FET's and area utilization (60%) is not as good as with GATO's (>85%), precluding use of devices in volumetric/weight sensitive aviation turbine engineapplications. Furthermore, MCT gate-yield considerations limit the active area to about 1 cm.sup.2. High-current high-voltage applications are therefore better served by GATO-type designs, even though the turn-off function is not required.
As can be seen from the foregoing, thyristors have not yet been optimized to serve as both closing and opening switches for "square" reverse bias safe operating area (RBSOA) performance, i.e., turn-off to full current and voltage withoutsnubbers. As a result designers have sought circuit solutions such as forced commutation for turn-off, resonant topologies (soft switching for low RBSOA switches), saturable reactors to limit di/dt, snubbers to limit reapplied dV/dt, and expensive gatedrives to accommodate GTOs with low turn off gain and long turnoff "tail currents" due to open base recovery of the wide base pnp. The MCT has addressed many of these difficulties but also suffers from open base recovery (low RBSOA), is difficult toscale up to large areas with good yield, has a low active to total area ratio and a relatively small number of turn-on cells. Moreover, turn-on FETs associated with MCTs must block the full device voltage and must be sized based on the relationshipblocking voltage to the 2.5 power, i.e., (blocking voltage).sup.2.5.
Thus, it would be desirable to provide the industry with power electronic switching devices which can serve as both closing and opening switches at unlimited di/dt's and without snubbers or saturable reactors.
Accordingly, it is an object of the present invention to provide an alternative to conventional power electronic devices which alternative has increased operational flexibility and improved operational characteristics. The present inventionachieves these objects in the novel dual gated MOS-controlled thyristors (DMCT) and dual gate turn-off thyristors (DGTO) described in detail below.
Semiconductor switching devices according to the present invention are constructed to be capable of nearly unlimited di/dt by virtue of, for example, simultaneous electron-hole injection, reduced spreading resistance under the emitter and acontinuous and narrow solder bumped gate/cathode structure. High di/dt has many desirable ramifications in power applications, such as the turbine ignition exciter application described above. For example, by offering extremely high di/dt, at elevatedtemperature, while reliably blocking nominal 2-5 kV tank voltage, the PPT allows solid state exciters to utilize bona fide high voltage, e.g., greater than 10 kV, PFN's.
It is a further object of the present invention to offer semiconductor devices having improved ambient temperature performance. Existing thyristor junction temperatures (T.sub.j) are limited to approximately 125.degree. C. By utilizing novelthyristor processing technology according to exemplary embodiments of the present invention, asymmetric semiconductor structure and edge-bevel area gain reduction techniques such as positive beveling and electron beam irradiation, significantly higherjunction temperatures on the order of, for example, 175.degree. C. can be achieved. By maximizing junction temperature capability, the probability of thermal runaway is minimized.
It is still a further object of the present invention to provide a four leaded semiconductor device having an anode, anode gate, cathode and cathode gate. By selectively connecting the anode and anode gate leads and/or the cathode and cathodegate leads, (or by opening the emitter leads) semiconductor switching devices according to the present invention can be operated or transitioned in a number of different modes. For example, the DGTO can transition from a pnpn transistor to a pin diode,operate as a semiconductor controlled switch (SCS), operate as a reversibly triggered/conducting thyristor, operate as an anode gated GTO, operate as a cathode gated GTO, operate as an anode/cathode gated SCR or operate as an MCT that is controlled fromboth anode and cathode sides.
Inner and outer gates of continuous cathode designs according to the present invention can be used as a symmetric source and drains of an n-channel JFET, with the solder-bumped serpentine used as a gate, and with the anode and anode gate open. Both the npn and pnp portions of the DGTO can be used as efficient bipolar junction transistors.
Access to all four thyristor layers allows much better device control, higher hole/electron lifetimes and results in better turn-off performance because open base recovery with the attendant hole/electron recombination "tail" of the wide base pnpand npn is avoided. With contacts to all four layers and a narrow and continuous emitter, the conducting pnpn structure can transition to a recovering (reverse biased) pin diode by connecting both gates to their respective emitters. Thus, the externalcircuit will sweep charge from the relatively large area control junction, rather than depending on open base hole-electron recombination as in convention IGBTs, MCTs and three-leaded GTOs. Open base recovery is associated with low RBSOA, the need forsnubbers, high on-state and turn-off dissipation, low rep rate and low controllable current density, all of which are avoided by the present invention.
The foregoing, and other, objects, features and advantages of the present invention will be more readily understood upon reading the following detailed description in conjunction with the drawings in which:
FIGS. 1A-1B compare cathode/gate metalization area of a standard 1.5 kV phase control thyristor with a continuous emitter associated with exemplary switching devices according to the present invention;
FIG. 1C is a detailed plan view of a portion of the emitter of FIG. 1B;
FIG. 1D is a cross-sectional view of the solder bumped emitter of FIG. 1C;
FIG. 2 illustrates a one-sided emitter/base region geometric relationship, which allows immediate conduction of high (di/dt) current following a gate trigger pulse or photon pulse;
FIG. 3 is a cross-sectional diagram illustrating an edge bevel region where peak field is minimized on both sides of the junction;
FIGS. 4A-4B illustrate different edge bevel (sand blasting) techniques and methods according to exemplary embodiments of the present invention;
FIG. 5 illustrates a conventional hockey puck thyristor edge beveling technique;
FIG. 6A is a schematic representation used to illustrate device variations/transitions according to exemplary embodiments of the present invention;
FIG. 6B illustrates an exemplary configuration for the four leaded DGTO of FIG. 6A wherein the DGTO operates as a PIN diode;
FIG. 6C illustrates a second exemplary configuration for the four leaded DGTO of FIG. 6A wherein the device operates as a silicon controlled switch;
FIG. 6D illustrates a third exemplary configuration for the four leaded DGTO of FIG. 6A wherein the device operates as a reversibly triggered/conducting thyristor;
FIG. 6E illustrates a fourth exemplary configuration for the four leaded DGTO of FIG. 6A wherein the device operates as an anode gated GTO;
FIG. 6F illustrates a fifth exemplary configuration for the four leaded DGTO of FIG. 6A wherein the device operates as a cathode gated GTO;
FIG. 6G illustrates a sixth exemplary configuration for the four leaded DGTO of FIG. 6A wherein the device operates as a four leaded gate voltage controlled GTO or DMCT;
FIG. 7 is an isometric rendering of a DMCT processed on both sides of an asymmetric pn+n-pn+ wafer;
FIG. 8 provides a cross-sectional illustration of asymmetric and integral back bias edge shorting geometries enabling anode and cathode shorting of symmetric or asymmetric structures according to an exemplary embodiment of the present invention;
FIG. 9 is a pictorial representation of a four leaded DGTO according to the present invention wherein both emitters can be turned on with a single switch;
FIG. 10 graphically depicts an exemplary (anode) P region carrier following ion implantation and diffusion of Al, Ga and B;
FIG. 11 illustrates an exemplary cathode carrier concentration for devices according to exemplary embodiments of the present invention;
FIG. 12 is a continuation of the cathode carrier concentration profile of FIG. 11;
FIG. 13 provides a summary of an exemplary manufacturing process according to the present invention;
FIG. 14 illustrates (in sheet rho versus etch time) an exemplary process used to form the emitter structure according to exemplary embodiments of the present invention;
FIG. 15 illustrates an exemplary double-sided chip, solder bump packaging configuration for a four leaded device according to the present invention; and
FIG. 16 illustrates an application of a four leaded DGTO device operating as a five leaded DMCT.
FIGS. 1A and 1B illustrate exemplary differences in structure between traditional phase control thyristor structures and the novel DGTO device. It will be noted that conventional phase control devices, generically illustrated in FIG. 1A, havesilicon structures which limit blocking voltage to .ltoreq.1.5 kV and also have essentially point contact gate regions 14 surrounded by the cathode region 15. Conversely, devices according to exemplary embodiments of the present invention (exemplifiedin FIG. 1B) utilize interdigitated gate/cathode geometries 16 and 17. Note the relatively long gate/cathode periphery in FIG. 1B as compared with that of FIG. 1A. Interdigitation of the gate 16 and cathode 17 structures provides several importantadvantages relative to pulse discharge (di/dt) conduction. For example, when the device is triggered, gate charge is immediately distributed over the entire emitter, thus eliminating plasma spreading time delay. Likewise, long and ballasted emitterstructure 17 more efficiently collects current during conduction, thereby eliminating excess current density at "hot" spots during high di/dt periods. Hence, this extremely compact device, e.g., 1 in..times.1 in..times.1/8 in., high voltage, e.g., 5 kV,high current, e.g., >1.2 kA, is well suited for the high rise time, di/dt waveforms associated with pulse power applications, e.g., turbine engine ignition exciters, motor drivers and Pulse Power Switches.
FIG. 1C illustrates in more detail a portion of the serpentine emitter shown in FIG. 1B wherein the various metal layers can be seen.
Therein the continuous and narrow (e..g., 5 mil.) serpentine emitter is accessed everywhere and on both sides by the inner and outer gate metal by virtue of a continuous solder bar/bump (FIG. 1D). Cathode current can be extracted vertically fromthe entire length via a solid emitter metal plate 18 soldered to solder bumps 19. Holes (not shown) are provided in the solid emitter plate through which the inner and outer gates can be accessed. Accordingly, an insulating layer of polyimide or DuPontPyralux covers the gate metal everywhere except where gate and emitter contact windows are opened.
Referring to FIG. 2, unlike conventional thyristors, the emitter and gate geometries are such that the emitter center line is everywhere equidistant from the gate region, and less than a single diffusion length L from the gating region 400. Theemitter region width Y is maintained at, for example, less than or equal to about 1 to 5 times the gate (P base) region which, in this example, means that the emitter width Y is less than or equal to 0.005 inches. This ensures maximum use of the entireemitter area during initial triggering and turn-off. That is, during application of a gate trigger pulse, the entire emitter region is activated preventing concentration of charge in proximity of the gate connection G which occurs in conventional pointcontact thyristor designs, i.e., gate 14 in FIG. 1A. This feature allows the entire device to modulate and conduct full anode current coincidental with the application of a (gate) trigger pulse or a photon trigger pulse. Note that, controllable currentIc times spreading resistance Rs is below 0.6 V for turn off in this exemplary embodiment.
FIG. 3 illustrates a structure according to a first exemplary embodiment of the present invention. By positively beveling the die at edge 23 so as to "spread out" electric field lines on both sides of the high voltage junction when the device isforward biased, rather than the traditional negative bevels (which tend to concentrate E field lines under a forward bias) utilized by most hockey puck type phase control devices, a number of advantages are realized. For example, this unique positivebeveling ensures bulk field breakdown since the surface electric field is spread out over a longer distance 26 than the bulk electric field 24, thereby promoting maximum theoretical (bulk) breakdown. To further reduce leakage current, all edge regions27 outside of lines AA can be treated with electron radiation, further reducing pnp gain and associated leakage current. This unique design enables small, high voltage chips in small packages.
At the edge of the chip, a unique pnp structure 240 is created by etching off the outer n+ region. Note that accordingly the N+ (cathode) region is not embedded in p-doped material nor p+ in n-doped material. Since the (equivalent) npn and pnptransistor has been eliminated from the outermost regions, edge leakage current involves only the np structure as seen, for example, if FIG. 8. Additional etching, to the n-region, further reduces edge leakage to np diode levels by avoiding both npn andpnp gains, see also FIG. 8. Since leakage current in the vicinity of the bevel edge area 23 is higher than in other areas, design according to this exemplary embodiment ensures that this surface leakage current will not be amplified by npn/pnp thyristoror transistor action.
The emitter n+p junction and pn- regions 300 can also be made light sensitive by etching close to the pn- depletion regions. Triggering photons generate hole-electron pairs within these depletion regions effectively shorting the blockingjunction and resulting in simultaneous injection from both p+ and n+ emitting regions 28 and 29. The device can thus be made sensitive to light radiation 30 by a unique etch which is pervasive over the entire gate-emitter length on both sides of thechip (see, e.g., FIG. 7) and provides exposure of n+p junction 300. This allows optional optoelectronic triggering as an alternative to current triggering via the gates. The gate-emitter length is relatively great and base spreading resistance low ascompared to standard phase control thyristors because the serpentine length to area ratio (aspect ratio) is high, this being possible due to the unique cathode soldering techniques described herein. Due to considerably higher isolation achieved withoptoelectronic coupling, exciter circuitry and "up stream" supply electronics are further protected from thyristor failure modes and effects.
Referring to FIGS. 4A and 4B, edge beveling techniques according to the present invention are illustrated. The rounded region 31 of FIG. 4B is desirable since cracks and fractures 32 of FIG. 4A caused during processing and handling are minimizedby elimination of sharp edge 33. Cracks and chips contribute significantly to, and can cause failure of, semiconductors since high leakage current and low breakdown voltage result therefrom. FIG. 4A illustrates a sand blast method of die edge bevelingwherein sand 34 is blasted from the bottom of chip (die) toward the top. FIG. 4B illustrates a second method of forming the bevel where the sharp edges 33 are replaced by rounded edges 31. By changing the direction of the sand blast, or by squarecutting the die using a saw, a blunt edge, less prone to cracking is created. The sand blast profile 34 shown in FIG. 4B eliminates sharp edges since the distribution of the profile is such that some of the sand contacts the edge to round it off. Thesand blast can be directed against the substrate at an angle .crclbar. having a range of from, for example, 0-45 degrees inclusive.
FIG. 5, by contrast, illustrates the conventional bevels for large, e.g., .apprxeq.3 kV hockey puck type thyristors. Current thyristor structures use a double bevel angle, one negative 35, and one positive 36. Negative (Vbo) bevel 35 tends toconcentrate E field lines when the device is forward biased (anode positive WRT cathode; forward blocking condition). This promotes dielectric breakdown at device surface rather than through (bulk) Si. Conversely, phase control devices (which typicallymust block voltage reliably bi-directionally (60 Hz sinusoid)) require a second "positive" bevel to protect the device during reverse (Prv) bias condition. That is, when sinusoidal stress reversed polarity occurs, positive bevel 36 (which would normallytend to spread (surface) E field concentration) actually concentrates the field near the interface with negative bevel 35, thereby protecting the device from same bulk breakdown phenomenon.
In contrast, a dual positive bevel 23 (FIG. 4B) using sand blast and etching allows the device to realize (bulk) Si breakdown equal to theoretical Si breakdown. In comparison, traditional hockey puck devices, such as that illustrated in FIG. 5,can only achieve, for example, 80% of theoretical (bulk Si) breakdown voltage and must utilize considerably more Si and wafer "real estate".
These conventional devices have blocking voltages on the order of 3 kV and require 2.times.0.2" or about 10 mm (linear, over entire dimeteral surface) of Si be used for beveling. The novel beveling methods described above in conjunction withFIG. 4B according to the present invention require only about 2.times.0.032", or 1.6 mm Si for the bevel area for a greater than 5 kV device. This feature provides economic fabrication of devices with diameters on the order of, for example, about 4-25mm, which are capable of reliably blocking, for example, 2 to 6 kV. In contrast, existing MCT's require about 30% of the non-active chip area for passivation.
Referring to FIG. 6A, a DGTO according to another exemplary embodiment having four leads, i.e., cathode (K), anode (A), cathode gate (Kg) and anode gate (Ag) leads is illustrated. If both emitting injectors 37 and 38 of the thyristor structureare shorted, the device blocks voltage like a diode. That is, by effectively shorting the p+n 37 and n+p 38 injecting junctions of the thyristor, npn and pnp gains are eliminated thereby reducing leakage current levels to those associated with diodestructures and permitting high temperature (T.sub.j .gtoreq.175.degree. C.) operation. Selective shorting of the injecting junctions, and other selective connections, is accomplished by the provision of switches 89a-89d in the lead connections. Theswitches can, for example, be implemented as transistors fabricated within the DGTO itself or externally thereto. For example, if switches 89a and 89c are open and switches 89b and 89d are closed, the device is in its thyristor mode. If switches 89aand 89c are closed and switches 89b and 89d are open, the device is in its PIN diode mode. Transitions among these modes can be effected by switches 89a to e in any combination.
FIGS. 6B-6G illustrate other exemplary ways in which a four leaded PPT according to this exemplary embodiment of the present invention can be connected. For the first time, exemplary transitions between these modes can be effected by appropriateconnections of the DGTO leads. For example, if the anode gate is connected to the anode and the cathode gate is connected to the cathode, then the DGTO device transitions from thyristor to PIN diode mode (FIG. 6B). In this way, the DGTO can dynamicallytransition from operating as a conducting thyristor to operating as a reversed biased and clearing PIN diode, thus serving as a current interrupter having the best reverse biased safe operating area (RBSOA) known.
A silicon controlled switch (SCS) is one in which the voltage between the anode and the anode gate is variable, which results in a device which breaks over at an adjustable voltage, e.g., a relaxation oscillator. This exemplary configuration isillustrated in FIG. 6C. Thus, a new category of vertically versus horizontally conducting SCS switches capable of high current and high voltage, unlike existing planar SCS switches which are limited to low current/low voltage operation.
FIG. 6D illustrates the novel four leaded DGTO connected to operate as a reversibly triggered/conducting thyristor. In this device, current will flow through the cathode to the cathode gate (through a diode inserted into the connection andbypass the cathode emitter and out the anode gate or shorted anode.) Reverse conducting will eliminate the need for a separate inverse parallel diode in many applications as well as keep the device reliably turned-on when current undergoes multiplereversals, e.g., in exciter circuitry.
An anode gated GTO can be created by configuring the four leaded DGTO in the manner illustrated in FIG. 6E. Since conventional semiconductor devices do not provide anode gate leads, this type of device has no counterpart among semiconductordevices. However, the anode gated GTO will perform in a manner superior to that of conventional cathode gated GTOs by virtue of its higher turn-off gain and better ballasted nn-base.
A cathode gated GTO can be created by configuring the four leaded PPT as shown in FIG. 6F. While cathode gated GTOs per se are known, these conventional devices do not include anode gate leads, i.e., conventionally the anode and anode gate areseparated by a junction without the possibility of introducing a discrete resistance therebetween. As seen in FIG. 6F, however, cathode gated DGTOs according to the present invention can include a discrete resistor R since electrically separated leadsare available for the anode and anode gate. By varying the value of R, users of cathode gated DGTOs which are created by configuring the device as shown in FIG. 6F can adjust the performance of the device between maximum on-state and maximum off-stateperformance.
FIG. 6G illustrates the four leaded DGTO configured as a DMCT. Specifically, a DMOS FET is connected between each of the anode and anode gate, and the cathode and cathode gate. An IGBT 64 interfaces these two circuits. FIG. 9 (described below)illustrates the turn-on action served by IGBT 64. FIG. 16 illustrates the turn-off action served by the two DMOS FETS 62, as well as the advantages of being able to refer the FETS 62 to the low side of both loads (i.e., to reverse bias and clear bothemitter junctions prior to recovery of the internal pin diode).
To achieve a four leaded DGTO including an anode gate, devices according to this exemplary embodiment are processed on both sides of the wafer. FIG. 7 provides an isometric rendering of a DGTO processed on both sides of an asymmetric pn+n-pn+wafer which, in conjunction with FIG. 8, also illustrates the emitter shorting technique. Both the cathode and anode emitters have been etch defined and metalized in a manner that allows gating on both sides of the pellet using the above-describedsolder bump technique. This double sided gating capability provides the following operational advantages:
Better turn-on performance by enabling forward injection (gating) of electrons and holes from both cathode and anode emitters (injectors) simultaneously.
Better off-state performance at high temperature (125 to 250.degree. C.) by shorting both anode and cathode gates to their respective emitters. Leakage current is forced to bypass the injecting junctions for diode-like blocking performance.
Better turn-off performance is achieved by forcing on-state current to bypass both anode and cathode injecting junctions (FIG. 6A) via gate-injector shorts, 89a and 89c, and/or emitter switch opens, 89b and 89d, or by the reverse bias of one orboth injecting junctions (FIG. 16) to ensure quench of transistor action. The DGTO will then turn off and recover like a diode to full rated current and voltage without snubbers (i.e., "square RBSOA").
Cathode gate contact is accomplished by an etch down, e.g., at regions 90 and 92 of FIG. 7. One method of providing anode gate contact, similar to the technique used for the cathode side, involves building etched "holes" 92 in the anode p+region which penetrate to adjacent n+ material. These processes permit effective shorting of the cathode and/or anode emitters at low level (blocking current levels) such as those experienced during the energy storage device charge cycle, yet permitshigh current triggering and conduction at high conduction levels, such as those experienced during exciter discharge. Effective low level shorting and high level triggering is illustrated in the novel double sided etch down structure illustrated in FIG.7.
FIG. 8 illustrates a method and structure according to an exemplary embodiment of the present invention for shorting both anode and cathode regions of both symmetric and asymmetric structures to achieve high blocking temperature capability and/orintrinsic inverse parallel diode. Anode shorting reduces leakage current associated with npn gain and imperfect passivation of the bevel area. Leakage current contributes considerably to power losses and high junction temperature while blockingvoltages. Likewise, since leakage current increases with temperature, exciter top-end operational temperature performance is limited. At high temperatures, thyristor leakage causes die (chip) heating which, if unchecked, will continue untilcatastrophic thermal runaway occurs. Anode shorting for either asymmetric or symmetric structures is accomplished by removing (either by grit blast or etch method, for example) the outer region 39 of the (P+) anode.
This procedure provides at least two significant advantages. First, a shorting metal such as Au-As 40 can be alloyed into the n- region making an efficient inverse diode 41. Second, by limiting application of anode metal to the outer peripheryetch region, defined by zone 39, an efficient blocking diode structure is created at the outer periphery of the pnpn device. Thus, eliminating npn and pnp gain at the beveled surface (i.e., low leakage current), and providing reverse blocking voltagecapability (asymmetric or symmetric case). Cathode shorting can be accomplished by introducing internal shorts 43 over the entire emitter area or by providing external resistors 44 connected between cathode and gate terminals. This feature eliminates aproblem associated with high temperature pnpn thyristor blocking voltage, i.e. pnpn leakage current is highest in vicinity of bevel area 45. Accordingly, FIG. 8 illustrates how the outer bevel area can be modified to eliminate pnp and npn gain due toleakage current along surface of bevel for both symmetric and asymmetric thyristor structures. It will be appreciated by those familiar with semiconductor processing, that an asymmetric thyristor device would contain an additional n+ layer 46, allowinggood ohmic contact using Al or similar metalization, as well as a lower on-state voltage and fast turn-on times.
FIG. 9 illustrates a technique for turning on both emitters in four leaded DGTOs according to the present invention using a single switch S, e.g., an SCR, a high voltage IGBT or another DGTO, e.g., a light-triggerable thyristor. The functionserved by switch S can also be served by direct photon triggering, thereby effectively shorting the blocking junction and enabling double injection from both emitters. Switch S can be provided on the same wafer as the DGTO or may be provided as anexternal component. By applying a voltage V across the anode and cathode as shown in FIG. 9, simultaneous injection from both the p+ and n+ emitter junctions occurs when switch S closes or shorts 89e are applied (FIG. 6A). High di/dt performance isrealized by the simultaneous turn-on of both npn and pnp transistors along the peripheries of both the cathode and anode serpentine emitters, followed thereafter by pnpn latch on. For turn-off in resonant circuit topologies, reverse ring thru currenteffectively clears both injecting junctions via switch S to turn off the DGTO very quickly. This stands in stark contrast to conventional thyristors, MCTs and IGBTs which require lifetime killing via electron radiation or gold or platinum diffusion toprovide a low T.sub.q (turn-off time). Lifetime killing has the associated disadvantage that the turn-on voltage for a given device is significantly higher than it would be absent e.g., electron radiation. For example, 3.5 kV devices made according tothe present invention might have an on-state voltage on the order of 1.5 volts at about 800 A/cm.sup.2 while conventional, electron radiated devices, such as IGBTs, would need on the order of 3 volts to provide the same turn-off time.
Having described various exemplary structures for DGTO/DMCT semiconductor devices according to the present invention, the focus now turns to exemplary techniques for fabricating such devices. FIGS. 10-14 illustrate an exemplary manufacturingtechnique for a single-sided DGTO according to the present invention that can also be helpful to both sides. Therein, the devices are currently at the metalizing step. FIG. 10 illustrates the p region resulting from a diffusion of Al, Ga and B intoboth sides of a 37 mil thick Float Zoned Si wafer which was NTD (Nutron Transutated Doped) to approximately 1.5 E13 (cm.sup.3). The novel diffusion technique involves ion implanting and driving Al, Ga and B into the wafer with an approximately 16 hour1275.degree. C. diffusion cycle. To prevent device contamination, and associated excess leakage current, the Si is "capped" with layers of SiO.sub.2 --Si.sub.3 --N.sub.4 --SiO.sub.2 thus preventing entrance of contaminants and out diffusion. Thecapping/oxide layer materials and order of application were developed to provide a complete "cocoon" around the Si wafer, preventing entrance of contaminants or out diffusion.
Likewise, the oxide layers have been optimized to prevent cracking of the capping layer. It will be appreciated that the invention utilizes an ion implantation technique whereby Al, Ga and B are ion implanted through the oxide layer. Al is usedto achieve a deep (approximately 4 mil) junction for high voltage capability, with a reasonable (approximately 16 hour 1275.degree. C.) diffusion. Due to the poor (approximately 4%) electrical affectivity of Al, Ga and B are introduced to increaseconcentration of active electrical acceptors for good ohmic contact and injection efficiency. By way of contrast, conventional technology requires very long, high temperature diffusions, for example, about 135 hours at 1275.degree. C., which areconsequently prone to contamination from impurities, e.g. Na, which diffuses through (quartz) diffusion tubes increasing leakage current. HCL is used to tie up the Na ions.
To expand on this three element doping procedure, Al is used since it is a fast diffusing (P type) dopant which will dope an Si lattice properly with 16 hr. 1250.degree. C. diffusion, as opposed to traditional B 135 hr. 1275.degree. C.diffusion. Al is a good fit in the Si crystal, yielding low crystal stress. Unfortunately, Al tends to bond with oxides creating oxide complexes lowering the effective doping to roughly 4%. Ga is used next to achieve higher doping concentration. Since Ga does not tend to form oxide complexes, it is a more efficient dopant. Again, diffusion time is short. Finally, B is used as a getter to "lift" impurities to the surface where they can be removed (etched off). Boron also provides improvedohmic contact. Ion implantation through oxide layer prevents out-diffusion and prevents contamination by, for example, Na, which would reduce carrier lifetime and increase leakage current through space charge generation in the depletion layer.
Exemplary embodiments of the present invention can perform diffusion using, for example, either resistive heaters or microwave oven heating. The microwave technique can be implemented, for example, by replacing a standard fixed frequencymagnetron with a variable frequency variable frequency TWT (Traveling Wave Tube). This technique is favored since the TWT allows uniform RF heating of the Si, without heating the surrounding environment, thereby significantly reducing probability ofcontamination. This is a considerable advancement over current diffusion oven techniques since diffusion temperature can now approach Si melting temperature. Diffusion oven techniques are notably limited since quartz holding tubes used during thediffusion process are prone to sagging and devitrification at temperatures above 1200.degree. C. The resulting pnp structure is then one side lapped to a p concentration on the order of 10E17. The wafer is then diffused with phosphorous, on both sides,to a depth of about, for example, 6.5 microns to form a npnpn structure. The anode n side is then removed forming the raw blanket npnp wafer. FIGS. 10-12 illustrate the complete profile which is capable of blocking, for example, >5 kV.
FIG. 13 illustrates an exemplary method of forming the Si surface, i.e., defining the emitter, through the metalization process. The starting Si substrate is made by the sequential diffusion of Al, Ga and B into a, for example, 450 Ohm-cm, 37mil NTD doped n- wafer thereby forming a pnp. One side of the wafer is lapped, etched and n+ phosphorus (POCL3) is predeposited on both sides and annealed to form a n+ pnp n+ wafer. The emitter mask is used to selectively remove n+ from the cathodeside of the wafer and the blanket n+ from the anode side to achieve the n+pn-p+ structure.
FIG. 13 depicts a process that enables construction of a high voltage type device that replaces planar diffusion fabrication methods, thus eliminating carrier lifetime reducing oxide mask/etch processes. That is, this process allows thethyristor to be etched, defined and metalized without any carrier lifetime reducing process steps, translating into lower on-state (forward conduction) voltage. Although the FIG. 13 process depicts only one sided processing, double-sided exemplaryembodiments of the present invention can be realized by applying the teachings of FIG. 13 to both sides of the wafer in conjunction with other packaging related steps described below.
First, a low pressure chemical vapor deposited (LPCVD) nitride is deposited and patterned through use of standard photolithography masking techniques. The etch process described in FIG. 13 can be accomplished by utilizing the selective etchprocess depicted in FIG. 14, and results in an emitter step height on the order of, for example, about 7.5 microns. The N+ etch down procedure illustrated in FIG. 14 renders the P base region fully exposed. This significantly increases optoelectronicqualities of device, while also improving carrier lifetime. Since the N+ etch is a unique, selective etch, N+ material is removed, exposing underlying P material. This provides excellent uniformity and control which in turn allow the fine geometriesand uniform electrical performance. The oxide layer used in fabrication of standard devices reduces carrier lifetime, increasing on-state (forward conduction) voltage. Also shown in FIG. 14 is the increase in sheet resistance as the NP junction isapproached.
FIG. 14 involves a non-selective Si etch that removes the remaining n material to allow reliable contact to the p gate region; followed by the removal of the nitride mask. FIG. 13 involves the metalization process which is also used to alloydope the gate regions for good ohmic contacts to the lightly doped gate regions. Al, Ti, and Ni are evaporated and sputtered onto the emitter side and etch separated to obtain the gate-emitter lateral diode. Step 20 involves anode metalization usingblanket Al--Ti--Ni. A result achieved using this process is to obtain good ohmic contacts to both lightly doped p Si (the gate region), the heavily doped P anode and the n+ cathode. Good on-state voltage is then achieved by alloying the Al into the Siwith 500.degree. C. sinter step 21.
FIG. 15 illustrates exemplary packaging for a device processed on both sides, i.e., a four leaded DGTO. The wafer (Chip) 1500 is manufactured in accordance with the foregoing principles and includes an insulative surface layer 1502, which can,for example, be formed as a photo-definable polyimide or Pyralux solder mask. The insulative surface layer 1502 surrounds and separates the metallic emitter bars 1504 (only one of which is numbered in the figure for clarity). Also seen on the topsurface of PPT wafer 1500 are a plurality of solder bumps or bars 1506. The solder bumps 1506 can, for example, be formed of an alloy which is 95% Pb and 5% Sn. Most of the solder bumps 1506 are disposed on the emitter bars 1504, although several(seven in this example) are provided outside of the emitter bars for gate contacts. These seven solder bumps are gate connection nodes which provide electrical connection to the anode gate area 1508 of the top ceramic plate 1510. Similarly, the solderbumps 1506 disposed within the emitter bars 1504 contact a mating anode area surface whose outline is seen on top plate 1510. Ceramic thru-holes 1528-1530 provide the necessary access to the direct band copper on the bottom of the top plate.
The patterning on the underside of top plate 1510 is essentially mirrored by that seen on the top side of the bottom ceramic plate 1514. The bottom plate, however, provides connections to the cathode and cathode gate whereas the top plateprovides connections to the anode and anode gate. Thus, bottom plate 1514 includes a cathode area 1516 including a plurality of solder bumps 1506. These solder bumps 1506 intermesh with corresponding solder bumps on the underside of wafer 1500 (notshown) to provide electrical contact with the cathode. Like the emitter bars 1504 on the topside of wafer 1500, the solder bumps on the underside of wafer 1500 are aligned in rows. Analogously to anode gate area 1508, cathode gate area 1518 has solderbumps 1506 which intermesh with corresponding solder bumps on the underside of wafer 1500. Cathode contact area 1520 and cathode gate contact area 1522 are externally connected through leads (not shown) which extend upwardly toward top plate 1510. Metallized vias 1528 and 1530 provide external connection to the anode gate 1508 and anode 1512, respectively. This allows all four leads to emanate from the same side of the package even though both sides of the wafer are processed and contacted. Although the exemplary embodiment illustrated in FIG. 15 uses solder bumps (i.e., dot-like structures), those skilled in the art will appreciate that the bumps could also be elongated to be shaped as bars or to provide continuous coverage over the entireserpentine emitter.
Power electronic switching devices according to the foregoing exemplary embodiments and other embodiments not specifically discussed herein provide many advantages over conventional SCR technology. The following table summarizes exemplarydifferences between the conventional thyristor (hockey puck) and the inventive PPT.
__________________________________________________________________________ CONVENTIONAL THYRISTOR SUBJECT DEVICE FEATURE (Hockey Puck) (DGTO, DMCT) __________________________________________________________________________ dI/dt <200A/.mu.sUnlimited (like transistor). dv/dt good due to internal Integrated resistor will enable high shorts (<200A/.mu.s) dv/dt. On State Good for DC conditions, Good for fast turn-in -dV/dt, but but worst for high Di/dt. at the cost of higher DCon-state voltage. Reverse triggering can be used to offset high DC on-state voltage. Reverse Blocking Symmetric blocking Asymmetric blocking permitted normally required. thereby enabling more efficient forward drop. Maximum 125.degree. C. maximumdue to Both emitter junctions can be Operating leakage current causing effectively shorted, leading to Junction unwanted gate turn-on diode like blocking performance at Temperature temperature >200.degree. C. Reverse Not possible In the inversedirection, the Triggering subject device can act as a forward biased diode and can be reverse triggered for complete turn-on prior to forward conduction for the lowest possible turn-on losses and highest operating current density. Emitter DesignMassive area turned on Distributed gate-emitter area by a plasma spreading turning on instantly along the gate- from a point-like gate. emitter length; similar to high speed transistors. The distributed gate emitter turn on can be achieved fromboth sides of both anode and cathode emitters thereby eliminating delay time for regeneration. Bevel, Junction A negative forward Positive forward blocking bevel Termination blocking level (VBO) achieves 100% of theoretical and a positive reverseblocking voltage. blocking bevel (PRV). This compromise is required for symmetric blocking but only yields 80% of theoretical breakdown. Metalization Low current spring A thick metal lead frame can be Design loaded gate, dry soldered to theentire length of pressure emitter spring both anode and cathode emitters. loaded. As an alternative, a thick metal film can be applied by thick film metallurgy or evaporation. High gate current for inner and outer gates allows high dI/dt. GateLocation The gate region is The distributed emitter region is a normally at the center of central island surrounde d by an the chip surrounded by inner and outer gate region. This the emitter causing dI/dt design permits the gate to supply problems.current on both sides of the serpentine emitter for high dI/dt. Product SCR's above 2.5 kV are The proposed devices will initially Limitations only available in large be available up to 8 kV in chip size hockey pucks sizes from 8 mm dia to <100mm because the typical 3.degree. and can be packaged in small T03 negative bevels require type packages, but with long strike 0.6" of inactive bevel and creep distance, thus filling a space. hole in the industry's offering. Opening Switch The bestGTO`s have The subject devices, e.g., a double Potential poor turn off gain (5), sided GTO, can have both anode poor SOA, need large and cathode emitter shunts to snubbers, and operate at enable diode like recovery for the typical BJT current bestSOA known and could replace densities at turn-off. IGBT's, BJT's, GTO's and MCT's The MCT's also have as a more cost effective switch. poor SOA performance. __________________________________________________________________________
The above-described exemplary embodiments are intended to be illustrative in all respects, rather than restrictive, of the present invention. While it is apparent from the foregoing discussion that the output parameters of devices according tothe present invention can vary based on various design considerations, exemplary output parameters include:
0.5" diameter die, I.sub.RMS =70 A, I.sub.PK =700 A, di/dt=10,000 A/.mu.s
0.3" diameter die, I.sub.RMS =25 A, I.sub.PK =250 A, di/dt=1,500 A/.mu.s
FIG. 16 illustrates the diode-like turn off performance that can be obtained from the four leaded DGTO 1556 driving a series wound DC motor (represented by loads RL). During the ON state of the DGTO 1556, current flows through the main junctionof DGTO 1556 along the solid arrow denoted "ON PATH". The split loads RL charge capacitors 1604 and 1606, respectively. Two discrete switches (e.g., FETs or IGBTs) 1600 and 1602 are used to control the anode and cathode gates, which are referred toherein as the high and low sides of the split load, respectively. When both switches are turned on, both emitters are reverse biased by the load voltage (stored on the capacitors 1604 and 1606). That is, a biasing current flows in the directionsindicated by the "OFF" arrows. The current through the DGTO 1556 is diverted away from both back biased emitters, i.e., along the "ON-OFF TRANSITION PATH", through the two switches and back to supply 1608 for a diode-like turn off recovery. The fourleaded device enables both gates to be referred to the high/low side of the load thereby back biasing both emitters. Those skilled in the art will appreciate that this is not possible with MCT type devices, which can only zero bias one of the twoemitters and must depend on open base recovery, internal recombination and lifetime control for turn off. The MCT does not let the source be referenced to a low side. As a result, the four leaded DGTO has the potential for high controllable currentratings and to turn-off like a PIN diode which has the best RBSOA known.
For high voltage applications (e.g., greater than 3 kV), IGBTs rather than DMOS FETs can be used as pilot switches (e.g., switch S of FIG. 9) for turn-on of both emitters which is a major advantage over the current thyristors. Simultaneousturn-on of both anode and cathode emitters, as shown in FIG. 9, has the following advantages:
Instant latch-on over the entire emitter without delay or di/dt failure.
The pilot switch S (FIG. 9) can be a small inexpensive IGBT (@ $1-2) or SCR or opto device to control a>1000 A, >6 kV device.
The fastest possible turn-in di/dt and turn off for >20 kHz switching vs. the 2 kHz limit for the current state of the art IGBT.
Unlimited di/dt performance.
The highest turn-on gain, that is a few microwatt seconds of photon or electrical energy can trigger a>6 kV DGTO on to >1,000 A in less than 100 ns. That is, only mircro watts of power are needed to latch on >6 mega watt controldevices.
Thus the present invention is capable of many variations in detailed implementation that can be derived from the description contained herein by a person skilled in the art. All such variations and modifications are considered to be within thescope and spirit of the present invention as defined by the following claims.
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