text:
|1. Apr. 2014
|30. M�rz 2012
|21. Nov. 2011
|Auch ver�ffentlicht unter
|Chris Avila, Jianmin Huang, Dana Lee
|Urspr�nglich Bevollm�chtigter
|Sandisk Technologies Inc.
|Zitat exportieren
|BiBTeX, EndNote, RefMan
|Patentzitate (149), Nichtpatentzitate (2), Referenziert von (9), Klassifizierungen (10), Juristische Ereignisse (3)
|Externe Links: USPTO, USPTO-Zuordnung, Espacenet
This application claims priority from U.S. Provisional Patent Application No. 61/562,080 filed Nov. 21, 2011 and is incorporated herein in its entirety by this reference.
This invention relates generally to the operation of non-volatile flash memory systems, and, more specifically, to techniques of refreshing and correcting data stored therein, particularly in memory systems having very large memory cell blocks.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is removably connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. Besides the memory card implementation, this type of memory can alternatively be embedded into various types of host systems.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 6,522,580.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements and are described in United States published patent application no. 2003/0109093.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned U.S. application Ser. No. 10/280,352. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each block, and each page stores one or just a few host sectors of data.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, physical blocks may be logically linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in international patent application publication no. WO 02/058074. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page.
Data stored in a metablock are often updated, the likelihood of updates as the data capacity of the metablock increases. Updated sectors of one logical metablock are normally written to another physical metablock. The unchanged sectors are usually also copied from the original to the new physical metablock, as part of the same programming operation, to consolidate the data. Alternatively, the unchanged data may remain in the original metablock until later consolidation with the updated data into a single metablock.
It is common to operate large block or metablock systems with some extra blocks maintained in an erased block pool. When one or more pages of data less than the capacity of a block are being updated, it is typical to write the updated pages to an erased block from the pool and then copy data of the unchanged pages from the original block to the erase pool block. Variations of this technique are described in aforementioned published international application no. WO 02/058074. Over time, as a result of host data files being re-written and updated, many blocks can end up with a relatively small number of its pages containing valid data and remaining pages containing data that is no longer current. In order to be able to efficiently use the data storage capacity of the array, logically related data pages of valid data are from time-to-time gathered together from fragments among multiple blocks and consolidated together into a fewer number of blocks. This process is commonly termed "garbage collection."
Individual flash EEPROM cells store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as VT) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window is commonly divided into a number of ranges, one for each of the two or more storage states of the memory cell. These ranges are separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels do shift as a result of charge disturbing programming, reading or erasing operations performed in neighboring or other related memory cells, pages or blocks. For example, programming of one set of memory cells sharing a line or circuit with a second set of memory cells can disturb the charge levels of the second set. The end result of this parasitic disturb is that if no corrective action is taken on the part of the storage system controller, data in exposed areas not being operated on may be corrupted, and in an extreme case, beyond the corrective capabilities of any error correcting codes (ECCs) stored along with the data. Such data corruption would then result in loss of data to the user, thus rendering the storage system unreliable. The extent and nature of such disturbs in a particular memory cell array depends upon its specific architecture, structure and operation.
Therefore, it is beneficial to restore shifting charge levels back to the centers of their state ranges from time-to-time, before disturbing operations cause them to shift completely out of their defined ranges, in which case erroneous data are then read. Such a process, termed data refresh or scrub, is described in U.S. Pat. Nos. 5,532,962 and 5,909,449. As a further aspect of this, in memory systems that use error correction codes (ECCs), some number of erroneous data bits read from the memory may be corrected by use of the ECC and the corrected data is then re-written to a previously erased portion of the memory. Re-writing the data causes each of the written memory cell threshold levels to be within its designated state range since data programming usually involves alternately adjusting the stored charge and read-verifying the resulting memory cell threshold level until it reaches the desired range that represents the data being stored in the cell.
A method of operating a non-volatile memory system is presented. The memory maintains a set of read parameters for a default read case and a plurality of distinct shifted read cases. For each physical division of one or more blocks of the memory, the memory also maintaining a correspondence between the physical unit and a read case to use when reading the physical unit. The memory performs a read operation for a page of data using the corresponding read case for the physical unit to which page belongs, determines whether the read operation was successful or yielded a fail result, and, in response to a read operation yielding a fail result, selects a shifted read case at which the page can be read. Based on the shifted read case selected, the memory determines whether to refresh the block to which the page belongs.
The foregoing features may be implemented individually or together in various combinations, depending upon the specific application. Additional aspects, advantages and features of the scrubbing system herein are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles and other publications referenced herein are hereby incorporated herein by this reference in their entirety for all purposes.
Referring initially to
A typical controller 19 includes a microprocessor 21, a read-only-memory (ROM) 23 primarily to store firmware and a buffer memory (RAM) 25 primarily for the temporary storage of user data either being written to or read from the memory chips 11 and 13. Circuits 27 interface with the memory array chip(s) and circuits 29 interface with a host though connections 31. The integrity of data is in this example determined by calculating an ECC with circuits 33 dedicated to calculating the code. As user data is being transferred from the host to the flash memory array for storage, the circuit calculates an ECC from the data and the code is stored in the memory. When that user data are later read from the memory, they are again passed through the circuit 33 which calculates the ECC by the same algorithm and compares that code with the one calculated and stored with the data. If they compare, the integrity of the data is confirmed. If they differ, depending upon the specific ECC algorithm utilized, those bits in error, up to a number supported by the algorithm, can be identified and corrected.
The connections 31 memory of
The memory of
Certain terms used in this description can benefit from some explanation. A "sector" refers to independently addressable units of data accessed during host read and write operations. One sector of data is typically 512 bytes in size.
The "memory system" as used herein is a system consisting of one or more non-volatile memory devices and the hardware and/or software required to store and retrieve data to and from the memory. Varying portions of the overall memory system functionality may be implemented either on a subsystem completely dedicated to data storage, or on the host system itself. The memory system may be embedded in a host system or may be removable, such as in the form of a very small card. Portions of a removable memory system may themselves be removable, as for example if the storage media is removable from the controller portion. Any portion of a host system dedicated specifically to data storage in a memory system is also considered a part of the memory system. Such host functionality may include specialized software libraries, drivers, or applications in addition to any hardware residing on the host system.
For the purposes used herein, a "host system" is a system that generally has a functionality other than data storage, but which also either connects to the memory system, or has a memory system embedded in it. There can be host systems whose sole purpose is data storage.
The various techniques for refreshing and scrubbing data stored in flash memory described herein may be implemented in systems having various specific configurations, examples of which are given in
The size of the individual memory cell blocks of
The parameters 55 may also include an indication of the bit values assigned to each of the storage states of the memory cells, commonly referred to as their "rotation". That is, logical states of the data are mapped to different physical storage states. This also has a beneficial effect in wear leveling. One or more flags may also be included in the parameters 55 that indicate status or states. Indications of voltage levels to be used for programming and/or erasing the block can also be stored within the parameters 55, these voltages being updated as the number of cycles experienced by the block and other factors change. Other examples of the overhead parameters 55 include an identification of any defective cells within the block, the logical address of the data block that is mapped into this physical block and the address of any substitute physical block in case the primary block is defective. The particular combination of parameters 55 that are used in any memory system will vary in accordance with the design. Also, some or all of the overhead data can be stored in physical blocks dedicated to such a function, rather than in the block containing the user data or to which the overhead data relates.
Different from the single data sector block of
A further multi-sector physical block arrangement is illustrated in
Yet another memory cell arrangement is illustrated in
There are many different memory array architectures, configurations and specific cell structures that may be employed to implement the memories described above with respect to
Each row of charge storage transistors (memory cells) of the block forms a page that is programmed and read together. An appropriate voltage is applied to the word line (WL) of such a page for programming or reading its data while voltages applied to the remaining word lines are selected to render their respective storage transistors conductive. In the course of programming or reading one row (page) of storage transistors, previously stored charge levels on unselected rows can be disturbed because of voltages applied across all the strings and to their word lines.
Various Aspects of the Scrub Process
There are two primary phases of scrub, the read phase and the corrective action phase. The scrub read is distinguished from other system reads in that it generally involves the selection and reading of data in areas of the memory system not directly related to the completion of a particular host operation, nor to any of a number of other system operations, such as wear leveling. Another distinguishing feature of the scrub read is that no useful information is gathered by the system from the data read, but instead, the result of the data integrity check is the objective of the operation. Subsequent action on the part of the system is guided by the result of the integrity check, and not particularly by the data itself. The system may subsequently require the use of some information from the data read, such as overhead data, if the data fails the integrity check and corrective action is required. These features of not completing a particular host operation and not obtaining any useful data from the memory are fundamental differences between scrub reads and other data reads performed by the system.
The selection of the particular areas to scrub read is generally guided by the location and number of read, write and erase operations performed in the normal course of system operation in the context of the physical characteristics of the memory device. Generally, the scrub reads will be performed on areas of the memory array that have been exposed to voltages, currents or cross talk as a result of operations in other areas. Alternatively, the scrub read locations may be decoupled from other memory operations, and made to follow a deterministic or random sequence. However, this can result in a loss of system performance, as more reads would have to be performed to get the same amount of coverage of the more disturbed areas.
An additional aspect of the scrub reads is the selection of when to perform the scrub read operation. In general, the scrub operation can be initiated in response to any number of factors, such as a number of host operations, a number of physical read, write and/or erase operations, a time period, usage characteristics of the host, or some random or pseudo-random sequence, the generating and checking of which may be tied to any of the above.
The scrub write is distinguished from other system writes in that it is performed generally as a result of a failed integrity check of the data read during a scrub read. A scrub write is only unique in the context of the scrub read. Other write operations may be performed that have similar mechanisms to scrub writes but which are not carried out for that specific purpose. In one example, write operations may result from failed integrity checks after read or write operations performed in the course of normal memory system operation. In another example, data may be read and rewritten for refresh purposes in the absence of scrub reads, with the decision to write not based on the data integrity check, but instead on some other factor. One such factor can be the existence of an area of the array having high use or exposure, in which case data within the area may be re-written or moved. A continuous moving or refreshing of data may be done in a deterministic or random manner. Data may be read and rewritten with the intended purpose of wear leveling, but have an unintended benefit of refreshing the data in a manner that overcomes disturb issues.
Indeed, the relative freshness of a unit of data can be used to determine whether to initiate scrub of that data unit when it meets other criteria for doing so. That is, if a unit of data has recently been re-programmed as part of a wear leveling, data consolidation (garbage collection), prior scrub or other operation, the current scrub can be skipped since those data have recently been refreshed. The relative freshness of various units of data may be maintained, for example, with experience counts ("hot counts") or time stamps stored with the units of data, such as in part of overhead data of the blocks. Alternatively, the physical blocks may be grouped according to the freshness of the data stored in them, with the group to which a block belongs being stored as overhead data of the block. The relative freshness of blocks which otherwise become candidates for scrub can then be used as a factor in selecting those that are actually scrubbed. System performance is then improved by limiting scrub operations to those units of data that have been stored long enough so that their stored charge levels have likely been disturbed sufficiently to require attention.
In order to monitor the relative freshness of the stored data, either logical or physical blocks may effectively be grouped into sets based upon how recently the blocks have been re-programmed. All blocks within the entire memory array, or, alternatively, blocks within a plane, zone or other portion of the array, may be given an initial relative hot count value, and each time a block is reprogrammed, the relative hot count may be updated to the value of the most recently moved set or group. Once a certain number of blocks are in the most recently reprogrammed group, the most recently reprogrammed group value may be incremented, and any blocks subsequently reprogrammed may be updated to the new group value. As a result, distinct groups may be created with a relatively clear distinction between most recently reprogrammed and least recently reprogrammed blocks. In general, the relative hot count value of a block is allowed to roll over to permit the use of a relatively small number fields.
When relative hot counts are utilized, substantially all blocks may start at a base value of '0' when there are eight possible values, in a specific example, e.g., values of '0' through '7.' Seven out of the eight values may be used while one value is reserved to provide a gap between the value representing the blocks most recently programmed from the value identifying the blocks containing the oldest data. In this example, blocks that are written receive a new value of '1' to indicate that they are the most recently programmed. Once a certain number of blocks have been updated to the new value of '1,' blocks subsequently programmed may receive a new value of '2.' A value of '3' may eventually be assigned to newly reprogrammed blocks once a certain number of blocks have been assigned the value of '2.' At some point, the count will roll over such that the least recently used blocks have a value of '2,' the most recently programmed blocks have a value of '0' and the value '1' provides a gap between the two so that the values of the blocks with the oldest and newest data are clearly identified. Eventually, all the blocks in the oldest bin will be rewritten, either through a host write, scrubbing, wear-leveling or other mechanism. In the above example, bin '2' will then be empty, and that value can serve as the gap, while bin '1' can be used to identify the most recently written blocks. When a block becomes a candidate for a scrubbing operation on the basis of other criteria, its scrubbing may be skipped if its relative hot count places it in one of the groups of blocks more recently reprogrammed.
Alternatively, absolute hot counts may be maintained for either or both logical and physical blocks, in which case the system may preferably use such hot counts to make scrub decisions. That is, when a block is reprogrammed, its absolute hot count is incremented, decremented or otherwise maintained to provide an indication of the total number of times the block has been reprogrammed. Blocks with absolute hot counts indicating a large number of reprogramming operations typically have been reprogrammed more recently than blocks with absolute hot counts indicating a low number of reprogramming operations. Thus, scrubbing the data stored in blocks with a relatively high number of reprogramming operations may be skipped, since it is unlikely that the data has been significantly disturbed.
There are many specific scrubbing algorithms and related memory operations that may alternately be performed. Scrubbing may be controlled by the memory system controller or, alternatively, on each of the memory cell integrated circuit devices (chips), or even controlled in part or entirely by the host. The memory system may be removeably connectable with the host or, alternatively, can be embedded within the host.
The read phase of a scrub operation may be carried out in a number of different ways. Scrub rates may be tuned to optimize performance while maintaining a specified level of data integrity. Both the rates at which scrub operations are performed and the number of data sectors read at a time may be tuned, for example. Such tuning can take place automatically as part of the scrub algorithm. For instance, the rates and locations of scrubbing may be matched with uneven disturb exposure rates in different areas of the memory. Scrub reads may also be deferred in order to optimize system performance, or to meet specific real-time needs.
There are also various alternatives in the manner in which the scrub read is carried out. For example, a set of data may be read with both nominal reference levels and with margined reference levels. The amount of margin may target specific disturb mechanisms being encountered. If read data cannot be corrected by ECC, for example, then a read with wider margins may be able to recover the data. If data are read normally without any errors, then a read with narrower margins can provide information of the quality of the data.
After a scrub read, a decision is made whether to engage in corrective action. Among factors that are such a decision may be based upon include a level of activity based on a number and/or a pattern of bits in error that have been detected.
Corrective action most commonly includes re-writing the read data in the same or a different location in the memory. Such scrub writes may be deferred in order to optimize system performance, or to meet specific real-time needs. Corrective action can additionally include rotation of the data during a scrub write operation; that is, the memory cell states representing specific stored data is changed from what it was. Corrective action can also include mapping cells, columns or other structures deemed to be susceptible to disturb out of the system.
A majority of host protocols have an abstract interface to the memory system such that the memory is generally addressed by the host by logical block address number (LBA). Alternate equivalent addressing modes exist, such as cylinder-head-sector in the ATA host protocol, but the fundamental concept is that the host has no knowledge of the physical location at which the memory system has stored a given host data sector. The host system has available to it a linearly contiguous set of independently logical block addresses at which to store and retrieve data sectors. These abstracted host protocols generally require the presence of a controller on the memory system in order to control the memory operations, perform the mapping functionality, data management, error recovery, and so on. Memory systems operating with these abstracted host protocols preferably rely on the controller in the memory system to perform scrub operations, as the host generally has no knowledge of the physical aspects of the Memory System.
On the other hand, some host protocols have an interface in which the host itself performs the memory management functions. Memory systems that conform to these protocols typically have minimal controller functionality, if any at all. There may be varying portions of functionality such as, but not limited to ECC generation, ECC checking, or ECC correction, that may be performed by the Memory System rather than the Host System. Memory systems operating in these host memory managed protocols will usually rely on the host to perform the scrub operations, since the memory system typically has insufficient logic to perform scrub operations.
Some memory systems have a dedicated controller whose purpose is to operate the memory device and perform memory management functionality. Other memory systems do not have dedicated memory controllers, but instead rely on portions of the host infrastructure to perform memory management operations. As an example, a non-volatile memory device may be connected directly to a general-purpose microprocessor in the host system, with the memory management functionality being performed by software. In such memory systems without controllers, the same subsystem responsible for memory management operations also preferably performs the scrub functionality.
Of the memory systems that do have a controller, it is possible that the controller functionality is integrated into a non-volatile memory device (integrated circuit chip) itself. In an extreme example, the entire controller may be integrated on a memory device.
The memory system may be embedded in the host system and to varying degrees have functionality integrated into host subsystems that are general purpose or that have other functionality. In such embedded memory systems, the same host protocols are generally followed, though that may not necessarily be the case. As a general rule, however, the same set of functionality is required to operate the memory system.
While the memory system typically performs scrub operations in the case of an abstracted host protocol, it is possible that the host system can initiate scrub operations in such systems through use of a special command or other predefined interface transaction. One reason for implementing this functionality may be that the host system is most aware of periods of time during which the memory system will not be accessed to store or retrieve data, and the host system may take the opportunity to initiate a scrub operation during such periods of time. In this way, the overall reliability of the system may be increased with minimal impact upon performance. The mechanism used to initiate a scrub operation may be specifically for the purpose of scrub, or it may be a general-purpose mechanism for notifying the memory system that time is available for housekeeping operations. In the latter case, scrub operations may be one of several operations performed by the memory system during such periods of time.
The region of exposure due to a given memory operation is generally extensive, such that it is not practical to scrub the entire exposed region every time an operation is performed. Generally, only a portion of the exposed area will be selected for scrub, and the rate of scrub must be set such that the scrub operation will detect the most disturbed areas before the number of bits in error and the level of shifted cells exceeds any recovery schemes available on the memory system.
The rate at which scrub operations are performed is an important parameter affecting both data integrity and memory system performance. The higher the rate of scrub, the higher the likelihood of detecting disturbed cells in a block of data before the number of bits in error and the level of shifted cells exceeds any recovery schemes available on the memory system. However, the higher scrub rate, the greater the degradation in performance of the memory system as increasing amounts of memory and controller time are dedicated to this operation. To the end of guaranteeing a desired level of data integrity while sacrificing as little performance as possible, the scrub rate is optimized to the bare minimum required, with whatever guard band is deemed appropriate. The rate at which scrub operations may be performed may vary in two ways: 1) selection of the time at which to perform a scrub operation, and 2) selection of a number of sectors to scrub read at a time.
It is possible that the rate of scrub required for maintaining data integrity changes over the lifetime of the product. For example, as cells become more cycled, the rate of disturb may increase or decrease. If a fixed rate of scrub were set at the time of production, then in order to maintain memory system integrity over the lifetime of the memory system, the highest rate required over the lifetime of the memory system would have to be used. This would result in a higher rate of scrub when a lower one would suffice, resulting in a higher sacrifice of memory system performance than needed at certain times in the memory system lifetime. There are several approaches to tuning scrub rates over the lifetime of a memory system.
It is possible to set a variable rate of scrub at the time of manufacturing the memory system. One method of doing so is to provide a table of rate values that sets different scrub rate with whatever metric affects disturb rate. An example is a table that contains scrub rates for different program/erase cycle counts experienced by various portions of the memory array. If the memory system maintains cycle counts, then the scrub rate parameter would be selected from the table based on the worst-case or average cycle count of a given region of the array.
Another approach is to allow the memory system to self-adjust the rate of scrub based on the results of previous scrub operations. For example, if the memory system maintains a log of scrub operations and determines that a very low percentage of scrub operations require corrective action, it may adjust down the rate at which it performs scrub reads. On the other hand, if it is determined that a very high percentage of scrub operations require corrective action, it may adjust down the rate at which it performs scrub reads. Another metric by which the memory system may adjust the scrub rate is the amount of shift detected in individual storage elements during previous scrub operations, or the number of bits in error. In any of the above cases, the system may adjust scrub rate parameters adaptively with each new result, or it may log the information for periodic adjustment.
There are several techniques that may be used to select when to perform a scrub operation, some examples of which are: 1) random or pseudo-random, 2) based on number of host operations, 3) based on number of operations on the memory device, 4) based on a time interval. It is possible using any of the above described methods to tune the rate at which scrub operations are performed. The assumption below is that any parameters required for the scrub decision are provided at production time. There may be different rate parameters for read, write and erase operations, as each of these may disturb the memory at different rates.
It is possible to use random numbers (RN) or pseudo-random numbers (PRN) to determine the frequency of scrub operations if they are available to the system, or generated by the system. A number of methods are described below for using an RN or PRN sequence to decide whether or not to perform a scrub operation. All of the below methods assume the RN is being checked at some regular interval, and the decision to perform the scrub or not is based on some test of the RN value.
One method of using a random number to determine scrub rate is to perform a logical AND of a RN or PRN with a mask parameter containing some number of bits set to value one, and the remainder set to zero. The decision to perform a scrub or not would be based on whether the AND operation resulted in a zero or a non-zero value. A mask parameter with more ones results in a zero value less frequently than a mask value with more zeros. The table below shows the approximate rates of scrub with different eight-bit mask values, assuming that a zero AND result causes a scrub operation. Note that with a truly random sequence, only the number of bits with value of one affects the rate, and not the value itself, so the values in the table are only exemplary values.
Mask Value (hex)
Mask Value (bin)
Scrub Rate
0 � 00
0 � 01
0 � 03
0 � 07
Another related method is to count the number of bits in an RN of value 1 to determine whether or not to perform a scrub operation. Again, the number of bits in the RN might be compared with a mask or value indicating a threshold. Yet another method entails comparing the value of an RN with that of a scrub rate parameter. The decision to perform a scrub or not would be based on whether the RN exceeded the threshold value numerically. For example, for a threshold value of 5, the RN would be higher 5/256 of the time.
Alternatively, the rate of scrub may be tied to the number of host operations performed. For example, a scrub operation may be performed every N host read, write and/or erase operations, where N is a rate parameter that sets the rate of scrub. Further, the rate of scrub may be tied to the number of memory operations performed. For example, a scrub operation may be performed every NR reads, NW write and/or NE erase operations, where NR, NW and NE are rate parameters that set the rate of scrub. As a further alternative, where the memory system includes a method of measuring time intervals, then the scrubs may be performed at some regular time interval, T, where T is a parameter provided to set the rate of scrub.
It may be desirable in order to maintain performance of the memory system to defer a scrub read even after the decision to perform a scrub read has been made. The reasons for doing so may include real-time considerations. For example a host may require a certain data transfer, and dedicating resources to scrub at certain times might impact the ability of the memory system to meet the guaranteed data rate. For such a purpose, the memory system may queue the scrub operation parameters for later processing, at a time when performing the scrub would not impact performance to the host. The scrub operations may be deferred until sometime later in the host command processing, sometime after the command processing, or until a later host command. In such a case, the scrub operation parameters that have been decided upon are stored and processed at a later time when it is most convenient to the host.
Since only a portion of an exposed region of the memory array may be scrubbed at a given time, one important aspect of achieving proper coverage is the selection of where to scrub once the decision to perform a scrub has been made. The selection of were to scrub is generally related to the location of read, write and/or erase operations to the memory device. Embedded in the selection is knowledge of the region over which a given memory operation will disturb other storage elements. Relating the area to scrub to the area operated upon allows the scrub operations to be most efficient, in that scrub operations are not performed on areas of the memory that have not likely been disturbed.
One method of selecting the location to scrub entails using an RN or PRN to select a location from within the area of exposure of a given operation. On average, the areas experiencing most exposure will have the most opportunities to be selected for scrub. The rate of scrub would be adjusted to account for the expected worst case random number coverage, given that some areas will be selected more often than others, and only on average will there be even coverage.
Another method of selecting the location to scrub entails moving deterministically through an exposed region. However, this method would require logging of both memory operations and of scrub operations to ensure full coverage.
If activity to the memory is logged, then it is possible to get a measure of the amount of exposure a given area receives to potentially disturbing operations. Given such information, the memory system can search through the log for the areas that have received the highest exposure, and limit the scrub operation to those areas. This method may be used to guide any of the above methods in determining rate and locations to scrub. Generally the program/erase cycles may be tracked through maintenance of cycle count information. However, it is generally impractical to log read activity, so this method is likely not be used to track read exposure.
Alternatively, the locations of corrective actions may be logged and used as a guide to areas that may be more susceptible to disturb than others, or which receive greater exposure than others. The memory system may use this information to weight the choice of areas to scrub, particularly for areas that have required corrective action more frequently than others.
In systems where knowledge of potential regions of disturb exposure is not maintained, either of the random or deterministic methods may be used independent of such knowledge. In this case, the scrubs are performed throughout the memory system regardless of where host activity causes operations in the memory system to occur. However, the rate of scrub is adjusted high enough to ensure sufficient coverage. Generally this is a large waste of resources since some areas of the memory system will experience much more exposure than others, and are preferably the primary areas of focus of scrub operations.
The purpose of a scrub operation is to detect disturbed storage elements before the number of bits in error and the level of shifted cells exceed any recovery schemes available on the memory system. To this end, it is generally desirable to detect disturb as early as possible and before much of the guard band for a given voltage threshold level has been lost to disturb.
As described above in the background, flash memories usually store data at discrete states, or ranges of charge storage levels, each of which is separated from other states by some guard band. There is generally a nominal sensing level of discrimination between each state above which a storage element is deemed to be in one state, and below which it is deemed to be in another state. As a given storage element is disturbed, the level to which it has been programmed or erased may begin to shift. If the level of the storage element approaches the sensing level of discrimination, or crosses over it, it produces data in a state different that that to which it was programmed or erased. The error will generally manifest itself as one or more bits in error in the data, and will generally be detected through the use of ECC covering the data field.
Margining or biasing the read conditions such that the sensing level of discrimination is shifted more toward one state or another will cause disturbed storage elements to be sensed in the wrong state even if the amount of shift would not cause an error under nominal read conditions. This allows the system to detect shift before it approaches the point at which it would cause errors during normal memory system operation.
If disturb mechanisms are known to affect data storage levels in a specific way, it is possible to target detection of those specific disturb mechanisms by margining read conditions toward the expected level shifts. While the ideal situation would be to target the expected disturb mechanisms with a single read operation under a single set of margin conditions, this may not usually be possible. It may be necessary to perform multiple read operations under different conditions. For example, it is possible that different disturb mechanisms present in a memory cause storage elements to become either more programmed or more erased. Storage elements both above and below a discrimination level may be shift toward it, in which case it may be necessary to check first for a shift in the storage levels toward a discrimination level from one state, and then from the other.
There are two individual measures of data quality that can be used as thresholds to determine if corrective action should be taken: 1) the detection of data errors through use of ECC, and 2) even though few or no data errors are detected, a shift in the charge storage levels can be detected before they cause data read errors.
As discussed above, the scrub read conditions may be margined in order to target certain expected disturb mechanisms, or to simply check for sufficient margin in the stored levels. Whether the data was read under nominal or margined conditions, the decision whether or not to take corrective action may be based on the number of bits in error detected during the scrub read operation. For example, if the number of bits in error are below the ECC correction capabilities of the system, the system may decide to defer the corrective action, or to ignore the error altogether.
In addition to using the number of bits in error as a threshold to initiating corrective action, the system may make the decision to correct based on other factors such as the pattern of bits in error. For example, the ECC correction capabilities may be sensitive to bit error pattern, or bit error patterns may be indicative of a particular known disturb mechanism in the nonvolatile memory. There may be other reasons for basing the threshold on bit error patterns. The bit error pattern is generally revealed during the ECC correction operation.
It may be desirable for performance purposes to defer a scrub corrective action even if it has been determined that corrective action is required. The reasons for doing so may include real-time considerations. For example a host may require a certain data transfer, and dedicating resources to scrub corrective action at certain times might impact the ability of the memory system to meet the guaranteed data rate. For such a purpose, the memory system may queue the scrub corrective action operation parameters for later processing, at a time when performing the scrub corrective action would not impact performance to the host. The scrub corrective action operations may be deferred until sometime later in the host command processing, sometime after the command processing, or until a later host command. The main point is that the scrub operation parameters would be stored and processed at a later time when it is most convenient to the host.
There are two significantly distinct extremes of memory architectures, each of which leads to different methods of mapping host data to physical locations on the memory device and of managing and accessing data once programmed. The fundamental difference between the two architectures relates to the size of the minimum unit of erase and its relation to the size of the host protocol data sector.
If the size of the minimum unit of erase approximates that of the host data sector, then it is possible to implement a direct addressing scheme, in which a given host data sector is generally mapped to the same physical location as it written to by the host. In such a scheme, the previous contents are generally erased from the physical location prior to the superceding data being written in its place. This rewriting may entail read-modify-write if the size of the minimum unit of erase is larger than that of a host sector. It is possible in this addressing scheme for host sectors to be remapped to alternate locations within the storage system, but this generally only occurs during sector reassignments as part of a defect management operation, or for some other system reliability purpose. After such mapping, the host sector will generally remain mapped to the new physical location until some other reassign event. In such a direct address mapping scheme, the corrective action due to a disturb generally entails erasing the contents from the physical location determined to have been disturbed, and rewriting them to the same location. Any errors during the rewrite would be handled in a manner consistent with the general exception handling employed by the system, including, but not limited to, re-erase and rewrite, reassign, alteration of erase or write parameters, and so on.
On the other hand, if the size of the minimum unit of erase is much larger than that of host sectors, then it is common to implement an erase-pooling addressing scheme. Such an addressing scheme can also be implemented with memories having a small minimum unit of erase as well. In an erase-pooling scheme, host sectors are normally grouped into logical blocks that are then mapped into physical units of erase. A given host data sector is surrounded by other host data sectors within a unit of erase. When the host writes a given data sector, it would be impractical to read all sectors surrounding the target sector, erase the block, and then write all sectors back to the unit of erase with the one host sector containing the new data. To avoid such excessive overhead operations, an erase-pooling scheme generally maintains some number of units of erase in the erased state for the purpose of holding new versions of data as they are written. Sectors are generally grouped together into logical groups for data management purposes, and in general the system will attempt to maintain physical proximity of sectors in the same logical group. Several units of erase may be combined to form a logical construct called a metablock, or virtual block, normally for the purposes of allowing high write parallelism. Generally, the new data from the host will be written to an erased location. At some point, other sectors from the same logical group that have not been superceded with new data are either copied into the same metablock, or copied along with the newly written data into another metablock. Later, once all data in a given metablock or in a unit of erase has been superceded or copied elsewhere, the metablock or unit of erase will be erased and will be considered part of the pool of erased units of erase. In such an erase-pooling addressing scheme, the corrective action due to a disturb generally entails copying the affected data to another location on the memory system, along with any data consolidation required by the system for normal memory system behavior.
However, it is possible for data requiring corrective action during a scrub operation to be treated differently than write operations due to host activity or general data management. It is possible to write the data to a special location reserved for holding such data for a short amount of time until it is convenient for the system to consolidate them with logically contiguous data, said area either held in reserve, or allocated upon demand. It is also possible under some circumstances that the system would simply erase and re-write the data to the same location. For example, if little or no other data resides in the physical block, the other data could either be moved elsewhere permanently, or stored temporarily elsewhere during erase, possibly in volatile memory, and written back along with the data requiring corrective action. Any errors during the data write would be handled in a manner consistent with the general exception handling employed by the system, including, but not limited to, rewrite, reassign, write to a new location, alteration of erase or write parameters, forced rotation of data polarity, and so on.
Some individual storage elements, groups of storage elements, or other structures may be more susceptible than others to disturb. As an example of possible such structures or groupings, flash memory storage elements may be arranged to share a common drain, source, or gate line, and due to variance in the process it is possible that one such set of connected storage elements experience a stronger exposure to potentially disturbing signals than average. Likewise, individual storage elements may be more susceptible than others due to variance in the process used to form the array. The storage system may be designed to permanently map out or reassign these areas deemed to be susceptible to disturb. In an extreme case, any storage elements or other structures may be remapped upon the first occurrence of a scrub corrective action. For example, those storage elements containing the bits requiring ECC correction may be mapped out if redundant storage elements are available. In other embodiments, the locations of corrective actions may be logged and later analyzed for purposes of re-mapping storage elements or groupings at a later time. The analysis may involve a threshold of number of times a given grouping has required corrective action. In some cases the logged data may need to be analyzed with knowledge of the physical aspects of the memory device in order to detect the presence of expected physical structures, such as connected storage elements. The manner in which storage elements or groupings of storage elements are re-mapped depend on the implementation of the memory system. For example, a physical area containing a logical sector may contain redundant storage elements for the purpose of replacing storage elements that are mapped out. In another example, an entire sector or group of sectors may be mapped out if it has required corrective action.
Scrub operations may be performed in the background of host operations, or in between host operations. It may be desirable to change the behavior of the scrub operation depending on the type of operation the host has requested. For example, it may not be convenient for scrub corrective action to take place during execution of a host read command, in which case the corrective action may be deferred to a time which is more convenient to the memory system.
An alternate approach to disturb avoidance is to move data that has received potentially disturbing exposure without first checking to determine if the data are in error. There are many approaches to selecting the frequency and location of data to move, most of which are described above.
General Embodiment of Scrub
A flow chart of
The overall goal is to institute a scrub operation often enough to detect disturbed data before they become so numerous as to exceed any recovery schemes (ECC and the like) that may be available in the memory system.
Once a scrub trigger event is detected, a next step 93 determines locations within the memory array for performing a scrub operation. Example candidates can be determined as follows:
The identification of memory block(s) or other unit(s) as candidates for scrub is not necessarily followed by the scrub being performed. As indicated by a next step 95, initiation of the scrub operation can be deferred under certain circumstances, examples of which are:
In a next step 97, all or only some of the block(s) or other unit(s) of memory identified in step 93 as candidates for scrub are selected for the scrub operation. The selection criteria include:
Next, as indicated by a step 99, data are read from the selected units (scrub read) according to the following:
A next step 101 evaluates the integrity of the read data. As part of the scrub read, an ECC may be calculated from the user data read from the memory unit(s) and compared with the ECC that was earlier calculated and stored along with the user data during programming. So long as there are no bit errors or a small number of errors that can be corrected by the ECC, the second margined read with relaxed reference levels, as described above, need not be made.
An additional read that may optionally be made is of the levels of tracking cells, if provided in the memory array, to see if their stored values have changed. Tracking memory cells are often included to establish the reference levels used to read the memory cells.
Once the data are read and the number of errors (if any) of the read data are known, a next step 103 determines whether corrective action is both necessary and desirable. Some considerations are as follows:
In a next step 105, it is determined whether to perform the scrub corrective action or to defer it until a later time. One of the considerations in making this decision is the same as in step 95, namely deferral in order to meet specific real-time operating needs of the memory system at this time. Generally, completion of the scrub operation is preferably deferred if its later completion will cause a lesser impact upon system performance than to do so at the current time. It is usually undesirable to interrupt normal processing by the controller to perform a scrub, especially when the scrub operation will take more time than usual because of a large number of errors to be corrected by the ECC, the need to consolidate data, and the like. When deferred, the data read by the scrub read, their addresses, any errors determined by the ECC analysis and other parameters of the scrub operation developed in the preceding steps are temporarily stored. These data and parameters are then later read and the scrub operation is completed at a time when the impact on system performance is less.
When the scrub operation is to be completed, the data are corrected in a next step 107. The data are corrected by use of the ECC in this case. If not performed as part of step 99 above, one or more margin reads (where the reference levels are relaxed to read a wider programmed distribution than used during the prior read) may be required to recover data if a normal or scrub read produces more bits in error than can be corrected by the ECC being used. Then, in a step 109, appropriate corrective action is taken. This can include rewriting the corrected data in the same location from which they were read. This, of course, requires first erasing the block in which the data is rewritten, which may be practical in the memory arrangement of
Alternatively, the corrected data can be rewritten into a different location from where it was read earlier in the scrub operation. When the memory arrangement utilizes large storage blocks like shown in
It may be convenient to utilize a common designated physical block or blocks to temporarily store scrub rewrites of data from pages of many other blocks, and then later consolidate data of the rewritten pages with the data from other pages of their original blocks. For example, scrub rewrites of pages from blocks 1 and 2 are temporarily stored in a temporary block 3. Later, the scrub rewrites of block 1 are copied from block 3 into an erased block 4, and remaining unchanged pages of block 1 are also copied into block 3 to consolidate the data mapped into physical block 1. The same is then done in another erased block 5, in which the scrub rewrite of block 2 stored in block 3 and the unchanged data pages from block 2 are consolidated.
In the system of
The manner in which some memory systems are used causes few disturbs. The scrub process is then carried out infrequently because there are few triggering events to be recognized. In addition, it is practical to permanently store the relatively small amount of rewritten data together in one or more designated physical blocks, regardless of the physical blocks in which the scrubbed data originally resided. In this case, pages of scrubbed data are not recombined into physical blocks with pages of other logically contiguous data as a step in the scrub process. Another element of corrective action is to rewrite the corrected data with a different rotation than they were originally written. For example, the four analog storage state ranges of a four state system can be originally designated to represent 00, 01, 10 and 11, respectively, and upon rewrite designated to represent 11, 10, 01 and 00. The conversion is made by the memory controller when the data are read, using data of the specific rotation that is kept as part of the overhead data or otherwise. Data rotation is beneficially applied to rewrites of both corrected data and data that did not need correction.
A further element of corrective action that may be included is to map out pages or blocks of memory that build up a history of being affected by disturbs much more than on average. This is detected by monitoring the number of data errors in various pages, blocks, planes and/or other defined regions of the array. Of course, care should be taken to prevent mapping out pages or blocks experiencing data errors for reasons other than a higher susceptibility to disturbs, such as because a block is being used more or differently than the average.
The scrubbing algorithm is usually controlled by the memory controller but could, alternatively, be controlled by the host. When controlled by the memory controller, the algorithm is coded into the memory system firmware that is typically executed by the microprocessor 21 (
The specific scrubbing algorithm that is utilized depends upon certain characteristics of the memory system, particularly of the memory devices 11 and 13 (
A more specific embodiment of a scrub algorithm is illustrated in the flowchart of
In the step 115, the memory is monitored for a scrub trigger event, as discussed above for the step 91 of
A next step 125 performs the same function as the step 97 of
After the scrub read of the step 127 with the read margins set in the step 126, a step 131 determines whether there are any data errors, similar to the step 101 of
The decision in step 135 can also be affected by whether the data and their ECC are user data or overhead data. As described with respect to
If the decision in step 135 is that correction of the correctable errors in the data unit of interest should be made, a next step 137 asks whether the correction of the data should be deferred. Scrub is desirably deferred, for example, if there are so many bad bits in the read data that their correction will take more time than is available at this stage. If not deferred, the errors are corrected in a step 139, similar to the step 107 of
So far, a main path of the flowchart of
An example of operating the individual storage elements in a flash memory array in four states is used in
For a normal read, breakpoint levels 159, 160 and 161 in about the middle of the respective guard bands 155, 156 and 157 are used. That is, the threshold levels of the cells being read are compared with these breakpoint levels to determine their storage states. Errors occur when the threshold levels of cells within one state shift through a guard band across a breakpoint level. For example, when the threshold levels of cells in state 1 shift lower until they are below the breakpoint level 159, those cells are then read to be in state 0. Similarly, if the threshold levels of cells in state 1 shift higher until above the breakpoint level 160, a normal read will say that those cells are in state 2. Such read data errors are then identified by the ECC process. But when there are too many such errors for the ECC to correct, a second read with different breakpoint levels between states is made by steps 151 ands 153 (
After so re-reading the data, it is determined in a step 165 by use of the ECC whether any data errors remain. If not, the processing then proceeds to the step 135 of the main processing path, including determining whether data correction and rewriting should be deferred. If data errors are discovered by the step 165 to exist, then a next step 167 determines whether they are correctable by the ECC. If so, the processing then also jumps to the step 135 of the main processing path.
But if the data errors are found by the step 167 to be uncorrectable, then a further read with even different break point levels may be included. In a step 169, it is determined whether there are any remaining untried relaxed read conditions. If so, retry conditions are incremented by a step 170 and the processing returns to the steps 151 and 153 to read the data with such new conditions. But if there are no more different read conditions provided for, then the data in the subject array unit must remain with its uncorrectable errors. The scrub operation on that unit is then determined to have failed. One result of this could be to copy all valid data to a new memory system and then discard the present memory. Another result is to simply mark this unit as bad, by a flag stored in overhead data or otherwise, and then proceed to the step 143 to continue the scrubbing of other array units. The data in that unit is then lost. Since these data were verified as part of the original programming to initially be in their correct threshold level range, this possible result of an accumulation of disturbing operations over time shows the desirability of scrubbing frequently enough to such an adverse consequence.
Returning to the step 135, if it is there determined that correction of the data is neither necessary nor desirable, the processing jumps to the step 143 to continue scrub with any additional of the identified units. Also returning to the steps 137 and 140, if it is determined that correction or re-writing of the data should be deferred, then the read data, their addresses, the ECC and any identification of erroneous bits and other previously determine data are stored in a step 171 and the processing then jumps to the step 143. These data are then read when the deferred actions are reached for completion, as described below.
Returning to the step 131, the next action after determining that there are no data errors could be to do nothing further with the data of the current unit by jumping to the step 143. But it can be desirable to further check and adjust the storage levels of cells from which even valid data are read. This involves re-reading the data with different break point levels than used in the initial read, in order to identify any cells where the stored charge has moved into a guard band between the levels defined for the various states (see
If it is determined in the step 131 that there are no errors in the data read with the more restrictive margins, the processing on the current unit of data is ended. It is then determined by the step 172 whether there are more defined scrub read conditions that have not yet been tried with this unit of data. If so, the data may be read again with even tighter breakpoint levels. That is, the data may be read for the second time with a first set of alternate read conditions available in the step 172 with breakpoint levels shifted only a part of the way along their respective guard bands and then repeated this third time with the breakpoint levels of a second set of alternate read conditions selected by the step 172 moved even further toward the guard band edges for further fine adjustment of the charge storage levels, if necessary. As many such additional scrub read conditions may be provided as is practical.
Returning to the step 135, where it can be determined to accept some level of data errors without correction, it will be noted that this is inconsistent with the preciseness of the adjustments made by the branch of steps 172 and 173 to the stored data that contain no errors that have just been described. Therefore, if this processing branch is utilized, the step 135 most likely will not allow acceptance of erroneous data without correction.
After it is determined in the step 143 that all the data units currently identified for scrub have indeed been scrubbed, any of these data units that has shown an extraordinary propensity for having its data disturbed may optionally be mapped out of the system. A step 185 determines whether there are any such physical memory units that should be removed from the system, and, if so, they are mapped out by a step 187. The scrub operation is then complete.
However, if data corrections and/or re-writes have been deferred, the memory system controller or the host system will have this noted. At an appropriate time, when there are no higher priority memory operations pending, the scrubbing of partially scrubbed units may be completed, beginning with the step 117. The data, ECC and other information stored for one unit by the step 171 is read by a step 191. If the data from that unit needs correction, then that is done in a step 193. In a step 195, the correct data is re-written. If there are no other partially competed scrub operations that need to be competed, then this is determined in a step 197 and the step 185 is either executed or the processing ended. If there are other units to be completed, the processing increments to the next unit, in a step 199, and the steps 191, 193 and 195 are then repeated on the data from those units.
In the case where addresses of candidate memory cell units are stored in the step 123 for a deferred scrub, the processing can automatically return to continue the scrub operation for one of the deferred units at a time when the controller has no higher priority actions to implement. Since the deferral step 121 is so early in the processing of
More detail on above aspects of scrub techniques can be found in U.S. Pat. No. 8,050,095 and also in the related US patent publication number 2006-0039196-A1.
Read Scrub with Dynamic Read
This section considers the use of scrub operations in memory systems that use dynamic read. As described above with respect to
For the following discussion, the exemplary embodiment of dynamic read will have an initial or default set of read parameters and a number of different sets of dynamic read levels that are offset from both each other and the default case. These cases can differ from each other in the bias levels (such as word line or bit line levels) or on comparison points (such as voltage, current, or discharge time). The parameters of different dynamic read cases can be stored in a table kept in non-volatile memory. These parameters could be pre-loaded based upon empirical testing or by methods such as described U.S. Pat. No. 7,876,621. For different physical units of the memory, a table can then be kept of the currently read case being used. Depending on the implementation, this can be done at various levels of resolution in terms of block, plane, die, or other physical division for the memory, where smaller units (such as the block level) provide more accuracy, but at the cost of more overhead. This (physical unit, read case) correspondence can be kept on the controller, with a copy that can be updated as desired kept in non-volatile memory; alternately, at start up the system can start with the default cases and update as the system operates. In other embodiments, all the determination could be done on the memory chip. When a read request comes in, the corresponding read case is determined, and then the read parameters are set for this case.
When, during a normal read process, the amount of error exceeds a threshold, the memory will shift from the set of read parameters to a next set, where the same set of read parameters is used for all of the memory. For example, if, while operating with the default read parameters the amount of error reaches a threshold level, the system could go to a first dynamic read case, which it would then use going forward for all reads. Once the amount of read error for this first dynamic read case reaches the threshold, the system would then switch to the second dynamic read case and use this going forward, and so on. In a variation, which dynamic read case the system switches to could be based on the amount of error, skipping one or more intermediate cases if the amount of error is large enough.
As discussed in the preceding sections, the memory system will often use read scrub to try to refresh data by copying it to new location. Such algorithms usually rely on either randomly or systematically scanning part of the data storage space (housekeeping), or upon an actual host read location (active read). During such read operations, the system will often set a threshold lower than ECC correction level to determine whether a refresh is required for a set of data. Therefore, it is important that the integrity of the read used for this process is reliable. However, when system uses dynamic read and applies the same read case across the whole of an array, the integrity of read result is dependent on how dynamic read is used. For example, due to one or several blocks being idle for an extended period, these blocks will likely have more deterioration in threshold distributions and greater data retention problems, resulting in a particular read case being used; but when this same set of read parameters is then applied to a block that has just been programmed (and, consequently, has little data deterioration), these parameters will not be optimal, resulting is a relatively high ECC failure rate even though the state distributions for this block are still quite well-defined. Because of this, the resultant read scrub copy decision may not be correct.
So that the read scrub is based on accurate read results for systems using dynamic read, these section presents several options. In a first set of embodiments, when performing a read for a scrub, the memory system uses the default read values, rather than the current set of dynamic read values, if these are different. This would be the situation when a memory system that uses dynamic read and, due to the result of some earlier read has shifted it read parameters from the default values. When the memory system performs a read scrub scan for housekeeping, it would disable the dynamic read and instead use the default values. This is similar to the process described above with respect to step 126 of
In a variation, rather than go back from the current dynamic read levels to the baseline value, an intermediate value (or values) could be employed. For example, if the system uses, say, ten dynamic read cases, each progressively further from the default value and reads are currently being executed with the sixth of these values, for example, rather go back to the default case, an intermediate dynamic read case (such as the third) could be used.
According to a second set of embodiments, the scrub process uses aspects of the dynamic read process to determine whether a memory block is continued to be used without being refreshed, is refreshed, or is retired. As before, refresh means that when the data from a block is rewritten (usually) to a new block in the scrub process, the block from which the data came is returned to the system resource for future use. If retired, the source block is instead treated as defective and is not returned to the pool for future use. In these embodiments, the determination of whether a block should be refreshed or retired is based upon which dynamic read case number is being used. This second set of embodiments allows the system to make quick decisions on scrub for a block by targeting the failure type (refresh, retire, or just leave as is; prioritizing) triggered by the specific dynamic read case used to extract the data content of a page of the block.
As noted above, the read parameters for the different dynamic read cases can be stored in a table. As the system shifts to a particular dynamic read case number, the read values can then be looked up in the table. According to aspects of this set of embodiments, the dynamic read table is configured so that each of the case numbers correspond to a type of failure that the system and how it should be handled: continue to use the block as it is, refresh the block, or retire it. Note that this approach is not dependent upon comparison to an ECC threshold; that is, ECC is not used to compute the amount of error that is then compared to some threshold value or values. Instead, when the default read values, or nearby dynamic read cases, are used, the block would not be refreshed and continue to be used as is; but as the shift in values for the dynamic read case number get progressively further from the default, blocks would be refreshed and retired based on which case number is used.
Extending this approach further, the system can prioritize the handling or refreshing and retiring of blocks based on the dynamic read case. For example, even though several dynamic read case numbers would correspond to refresh, these numbers could be used to determine, based on this read case number, which blocks are most in need of refresh. In memory systems, the read scrub queue may be defined to have a certain maximum length, such as 8, for example. The system can use the dynamic read case number to add and prioritize blocks for the queue, placing more urgent cases toward the front of the line, and moving down (or even removing from the queue if the maximum length would be exceeded) lower priority blocks. The retiring of blocks can also be prioritized, if needed; for example, if the number of spare blocks begins to run low as the device ages, blocks whose read case indicates that they are marginal may be retained for use instead of being immediately retired.
In other variations, if it is wanted to make the decision on whether to perform a scrub more precise, the system can apply multiple or even all of the dynamic read cases to find which is the optimal case number (in teens of the lowest correctable ECC threshold, for example) before making the determination on how to treat a block or assign priority. To minimize the overhead time when searching for the optimal dynamic read case, the controller can go about it more intelligently. The system can look at the most recently used cases to determine the next case to check, rather than a simple sequential case order. For example, if the current dynamic read case number is 4, rather than sequentially proceeding to case 5 and on to case 6 and so on, the system can try the current case (4 here), the to the last used case (say 0), then on to the case used previously to that (say case 7), and so on. The overhead time involved can further be improved by making a decision on the number of cases that have been attempted (for example, limiting the number of cases tried to a maximum of, say, 3) and then use the cases used to determine how "different" the block is from others to makes scrub determinations.
Although the various aspects of the present invention have been described with respect to exemplary embodiments thereof, it will be understood that the present invention is entitled to protection within the full scope of the appended claims.
|Zitiertes Patent
|13. M�rz 1978
|13. Febr. 1979
|Westinghouse Electric Corp.
|High speed sense circuit for semiconductor memories
|3. Okt. 1978
|19. Aug. 1980
|Matsushita Electric Industrial Co., Ltd.
|Non-volatile memory refresh control circuit
|14. Mai 1979
|24. Febr. 1981
|Fairchild Camera & Instrument Corp.
|EPROM Reliability test circuit
|20. Mai 1982
|17. Juli 1984
|Intel Corporation
|Intelligent electrically programmable and electrically erasable ROM
|27. Juli 1984
|16. Sept. 1986
|Harris Corporation
|EEPROM margin testing design
|29. Juli 1985
|15. Sept. 1987
|Hitachi, Ltd.
|Dynamic memory diagnosis and error correction apparatus
|8. Aug. 1985
|27. Okt. 1987
|Fujitsu Limited
|High voltage precharging circuit
|15. Febr. 1983
|27. Okt. 1987
|Hitachi, Ltd.
|Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit
|23. Apr. 1986
|22. M�rz 1988
|Deutsche Itt Industries Gmbh
|Electrically programmable semiconductor memory showing redundance
|27. Nov. 1985
|9. Aug. 1988
|Motorola, Inc.
|Intelligent write in an EEPROM with data and erase check
|27. Okt. 1986
|18. Okt. 1988
|Mitsubishi Denki Kabushiki Kaisha
|Testable variable-threshold non-volatile semiconductor memory
|4. M�rz 1988
|17. Jan. 1989
|Kabushiki Kaisha Toshiba
|Semiconductor memory device with a sense amplifier
|12. Nov. 1987
|28. Febr. 1989
|Motorola, Inc.
|Method and apparatus for post-packaging testing of one-time programmable memories
|13. Juli 1988
|2. Mai 1989
|Sgs-Thomson Microelectronics S.A.
|Integrated circuit with memory comprising a fraud-prevention device
|27. Juni 1988
|26. Juni 1990
|Nec Corporation
|Programmable read only memory with means for discharging bit line before program verifying operation
|25. Okt. 1989
|9. Okt. 1990
|Texas Instruments Incorporated
|Nonvolatible capacitor random access memory
|24. Apr. 1989
|16. Okt. 1990
|Sgs-Thomson Microelectronics
|Electrically programmable memory with several information bits per cell
|29. M�rz 1990
|4. Dez. 1990
|Intel Corporation
|Method and apparatus for preventing the erasure and programming of a nonvolatile memory
|7. Apr. 1989
|25. Dez. 1990
|Xicor, Inc.
|NOVRAM cell using two differential decouplable nonvolatile memory elements
|17. Juli 1989
|27. Aug. 1991
|Eliyahou Harari
|Flash EEPROM memory systems having multistate storage cells
|20. Aug. 1990
|24. Sept. 1991
|Oki Electric Industry Co., Ltd.
|Method of detecting and indicating errors in a memory device
|15. Sept. 1989
|12. Nov. 1991
|Intel Corporation
|Apparatus for providing block erasing in a flash EPROM
|15. M�rz 1989
|3. Dez. 1991
|Sundisk Corporation
|Method of making dense flash eeprom semiconductor memory structures
|8. Juni 1988
|10. M�rz 1992
|Eliyahou Harari
|Highly compact eprom and flash eeprom devices
|26. M�rz 1990
|2. Juni 1992
|Oki Electric Industry Co, Ltd.
|Nonvolatile memory system for multiple value storing
|16. Apr. 1990
|16. Juni 1992
|Giovani Santin
|Circuit and method for erasing eeprom memory arrays to prevent over-erased cells
|30. M�rz 1990
|21. Juli 1992
|Mitsubishi Denki Kabushiki Kaisha
|Divided word line type non-volatile semiconductor memory device
|16. Apr. 1990
|21. Juli 1992
|Ashmore Jr Benjamin H
|Erasure of eeprom memory arrays to prevent over-erased cells
|2. Mai 1990
|29. Sept. 1992
|Rohm Co., Ltd.
|Semiconductor memory device having self-correcting function
|10. Apr. 1989
|20. Okt. 1992
|Hitachi, Ltd.
|Selective application of voltages for testing storage cells in semiconductor memory arrangements
|11. Apr. 1990
|15. Dez. 1992
|Sundisk Corporation
|Multi-state EEprom read and write circuits and techniques
|21. Aug. 1990
|15. Dez. 1992
|Mitsubishi Denki Kabushiki Kaisha
|Semiconductor memory device having error checking and correcting circuit and operating method therefor
|24. Okt. 1990
|6. Apr. 1993
|Rao Kameswara K
|Redundancy circuit for high speed EPROM and flash memory devices
|17. Okt. 1989
|6. Apr. 1993
|Sundisk Corporation
|Device and method for defect handling in semi-conductor memory
|28. Dez. 1990
|24. Aug. 1993
|Intel Corporation
|Floating gate non-volatile memory with blocks and memory refresh
|28. Juli 1989
|16. Nov. 1993
|Mitsubishi Denki Kabushiki Kaisha
|Non-volatile memory device capable of storing multi-state data
|27. Juni 1991
|16. Nov. 1993
|Digital Equipment Corporation
|Computer system operation with corrected read data function
|13. Febr. 1991
|14. Dez. 1993
|Hitachi, Ltd.
|Method of and apparatus for protecting electronic circuit against radiation
|15. M�rz 1991
|14. Dez. 1993
|Sundisk Corporation
|Method for optimum erasing of EEPROM
|14. Okt. 1992
|11. Jan. 1994
|Kabushiki Kaisha Toshiba
|NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit
|14. Jan. 1992
|17. Mai 1994
|Sundisk Corporation
|EEPROM with split gate source side injection
|20. Sept. 1991
|17. Mai 1994
|Texas Instruments Incorporated
|EEPROM array with narrow margin of voltage thresholds after erase
|24. Juli 1992
|24. Mai 1994
|Sundisk Corporation
|Segmented column memory array
|24. Aug. 1993
|14. Juni 1994
|Kabushiki Kaisha Toshiba
|Semiconductor memory device
|21. Apr. 1992
|5. Juli 1994
|Intel Corporation
|Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy
|6. Mai 1993
|2. Aug. 1994
|Advanced Micro Devices, Inc.
|Flash EEPROM array with high endurance
|1. Sept. 1993
|23. Aug. 1994
|Kabushiki Kaisha Toshiba
|Level shifter circuit constituted of E and I type transistors and an EEPROM using the same
|18. Dez. 1990
|30. Aug. 1994
|Sundisk Corporation
|Dense vertical programmable read only memory cell structure and processes for making them
|21. Apr. 1992
|13. Sept. 1994
|Intel Corporation
|Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
|16. Dez. 1992
|15. Nov. 1994
|Texas Instruments Incorporated
|Method and circuitry for refreshing a flash electrically erasable, programmable read only memory
|11. Aug. 1993
|27. Dez. 1994
|Intel Corporation
|Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
|14. Sept. 1992
|28. Febr. 1995
|Gemplus Card International
|MOS integrated circuit with adjustable threshold voltage
|8. M�rz 1993
|4. Apr. 1995
|M-Systems Flash Disk Pioneers Ltd.
|Flash file system
|2. Juni 1994
|12. Sept. 1995
|Intel Corporation
|Gray coding for a multilevel cell memory system
|23. Aug. 1994
|7. Nov. 1995
|Kabushiki Kaisha Toshiba
|Nonvolatile semiconductor memory system with a plurality of erase blocks
|27. Dez. 1994
|12. Dez. 1995
|Intel Corporation
|Error management processes for flash EEPROM memory arrays
|8. Nov. 1993
|2. Apr. 1996
|Sandisk Corporation
|Mixed data encoding EEPROM system
|2. Juni 1994
|4. Juni 1996
|Intel Corporation
|Method and apparatus for verifying the programming of multi-level flash EEPROM memory
|8. Febr. 1995
|25. Juni 1996
|International Business Machines Corporation
|Soft error recovery system and method
|21. M�rz 1995
|2. Juli 1996
|Sandisk Corporation
|Soft errors handling in EEPROM devices
|21. Sept. 1994
|29. Okt. 1996
|Kabushiki Kaisha Toshiba
|Multi-state EEPROM having write-verify control circuit
|16. Febr. 1995
|10. Dez. 1996
|Harari; Eliyahou
|Flash EEPROM system cell array with more than two storage states per memory cell
|28. Dez. 1994
|15. Apr. 1997
|Kabushiki Kaisha Toshiba
|Memory system
|5. Febr. 1996
|15. Juli 1997
|Micron Technology, Inc.
|On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
|18. Dez. 1995
|29. Juli 1997
|Sgs-Thomson Microelectronics S.A.
|Electrically programmable memory with improved retention of data and a method of writing data in said memory
|20. M�rz 1995
|12. Aug. 1997
|Sandisk Corporation
|Soft errors handling in EEPROM devices
|25. Mai 1994
|26. Aug. 1997
|Sandisk Corporation
|Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
|22. Aug. 1996
|7. Okt. 1997
|Advanced Micro Devices, Inc.
|Erase method for page mode multiple bits-per-cell flash EEPROM
|26. Aug. 1996
|18. Nov. 1997
|Texas Instruments Incorporated
|Semiconductor memory device and defective memory cell correction circuit
|29. Mai 1996
|16. Dez. 1997
|Kabushiki Kaisha Toshiba
|Method of rewriting data in a microprocessor additionally provided with a flash memory
|26. Dez. 1995
|30. Dez. 1997
|Signal processing method
|22. Apr. 1996
|27. Jan. 1998
|Advanced Micro Devices, Inc.
|Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
|23. Mai 1996
|3. Febr. 1998
|Micron Quantum Devices, Inc.
|Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
|27. Nov. 1996
|10. Febr. 1998
|Advanced Micro Devices, Inc.
|Apparatus and method for multiple-level storage in non-volatile memories
|19. Jan. 1996
|12. Mai 1998
|Kabushiki Kaisha Toshiba
|DRAM having a power supply voltage lowering circuit
|9. Aug. 1995
|2. Juni 1998
|Kabushiki Kaisha Toshiba
|Cell threshold value distribution detection circuit and method of detecting cell threshold value
|10. Sept. 1996
|30. Juni 1998
|Kabushiki Kaisha Toshiba
|Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state
|24. Sept. 1996
|25. Aug. 1998
|Sandisk Corporation
|Plane decode/virtual sector architecture
|20. Dez. 1996
|10. Nov. 1998
|Intel Corporation
|Method for improved data retention in a nonvolatile writeable memory by sensing and reprogramming cell voltage levels
|7. Nov. 1995
|30. M�rz 1999
|Hitachi, Ltd.
|Nonvolatile memory device and refreshing method
|5. Nov. 1996
|30. M�rz 1999
|Sandisk Corporation
|Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM
|2. Juni 1997
|18. Mai 1999
|Agate Semiconductor, Inc.
|Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
|8. Sept. 1997
|1. Juni 1999
|Invox Technology
|Multibit-per-cell non-volatile memory with error detection and correction
|30. Juli 1997
|27. Juli 1999
|Sandisk Corporation
|Multi-state non-volatile flash memory capable of being its own two state write cache
|16. Okt. 1997
|10. Aug. 1999
|M-Systems Flash Disk Pioneers Ltd.
|Flash file system optimized for page-mode flash technologies
|12. Dez. 1997
|5. Okt. 1999
|Micron Technology, Inc.
|Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
|27. Jan. 1999
|4. Apr. 2000
|Kabushiki Kaisha Toshiba
|Semiconductor device and memory system
|8. M�rz 1999
|7. Nov. 2000
|Lexar Media, Inc.
|Moving sectors within a block of information in a flash memory mass storage architecture
|25. Nov. 1998
|21. Nov. 2000
|Sandisk Corporation
|Multi-bit-per-cell flash EEPROM memory with refresh
|27. Jan. 1999
|6. M�rz 2001
|International Business Machines Corporation
|Refresh period control apparatus and method, and computer
|14. Jan. 1999
|10. Apr. 2001
|Macronix International Co., Ltd.
|Multi-level memory cell device and method for self-converged programming
|7. Aug. 1997
|24. Apr. 2001
|Sandisk Corporation
|Multi-state memory
|26. Apr. 2000
|24. Apr. 2001
|Advanced Micro Devices, Inc.
|Auto adjusting window placement scheme for an NROM virtual ground array
|15. Sept. 2000
|15. Jan. 2002
|Hitachi, Ltd.
|Storage device counting error correction
|14. Febr. 2000
|2. Juli 2002
|Sanyo Electric Co., Ltd.
|One-chip microcomputer and method of refreshing its data
|17. Febr. 2000
|30. Juli 2002
|Sandisk Corporation
|Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
|17. Sept. 2001
|24. Sept. 2002
|Sandisk Corporation
|Selective operation of a multi-state non-volatile memory system in a binary mode
|27. Juni 2001
|18. Febr. 2003
|Sandisk Corporation
|Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
|2. Nov. 2001
|6. Mai 2003
|Sandisk Corporation
|Non-volatile memory with temperature-compensated data read
|28. Febr. 2002
|20. Mai 2003
|Lexar Media, Inc.
|Block management for mass storage
|28. Sept. 2001
|13. Jan. 2004
|M-Systems Flash Disk Pioneers Ltd.
|Flash management system using only sequential write
|13. Aug. 2002
|27. Apr. 2004
|Renesas Technology Corp.
|Nonvolatile semiconductor memory device having control circuit
|23. Apr. 2003
|6. Juli 2004
|Sandisk Corporation
|Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
|19. Jan. 2001
|13. Juli 2004
|Sandisk Corporation
|Partial block data programming and reading operations in a non-volatile memory
|13. Sept. 2000
|3. Aug. 2004
|Lexar Media, Inc.
|Flash memory system and method implementing LBA to PBA correlation within flash memory array
|23. Dez. 2002
|19. Okt. 2004
|Renesas Technology Corp.
|Semiconductor memory device
|14. Apr. 2003
|4. Jan. 2005
|Jian Chen
|Read and erase verify methods and circuits suitable for low voltage non-volatile memories
|11. M�rz 2003
|28. Juni 2005
|Fujitsu Limited
|Nonvolatile semiconductor memory device
|25. Okt. 2002
|2. Aug. 2005
|Sandisk Corporation
|Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
|29. Okt. 2003
|8. Nov. 2005
|Aifun Semiconductors Ltd.
|Method circuit and system for determining a reference voltage
|3. Okt. 2003
|14. M�rz 2006
|Sandisk Corporation
|Flash memory data correction and scrub techniques
|9. Sept. 2003
|11. Juli 2006
|Solid State System Co., Ltd.
|Pipeline accessing method to a large block memory
|10. Nov. 2005
|29. Mai 2007
|Sandisk Corporation
|Flash memory data correction and scrub techniques
|1. Juli 2005
|29. Mai 2007
|Sharp Kabushiki Kaisha
|Virtual ground line type memory device with high speed readout circuit
|17. Aug. 2005
|10. Juli 2007
|Saifun Semiconductors Ltd.
|Method for reading non-volatile memory cells
|12. Jan. 2006
|7. Aug. 2007
|Sandisk Corporation
|Flash memory devices with trimmed analog voltages
|9. Dez. 2004
|14. Aug. 2007
|Saifun Semiconductors Ltd
|Method for reading non-volatile memory cells
|9. Mai 2006
|23. Okt. 2007
|Macronix International Co., Ltd.
|Method and apparatus to improve nonvolatile memory data retention
|27. Juli 2006
|12. Febr. 2008
|Macronix International Co., Ltd.
|Method for memory data storage by partition into narrower threshold voltage distribution regions
|30. Aug. 2006
|11. Nov. 2008
|Micron Technology, Inc.
|Non-volatile memory cell read failure reduction
|22. Juni 2006
|10. Febr. 2009
|Sandisk Corporation
|System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
|14. Mai 2007
|14. Apr. 2009
|Sandisk Corporation
|Flash memory data correction and scrub techniques
|30. M�rz 2007
|3. Nov. 2009
|Apple Inc.
|Shifting reference values to account for voltage sag
|23. Jan. 2008
|8. Dez. 2009
|Sandisk Corporation
|Starting program voltage shift with cycling of non-volatile memory
|6. Jan. 2006
|8. Dez. 2009
|Sandisk Il Ltd.
|NAND flash memory controller exporting a NAND interface
|27. Sept. 2006
|11. Mai 2010
|Sandisk Corporation
|Memory with cell population distribution assisted read margining
|28. Dez. 2007
|16. Nov. 2010
|Samsung Electronics Co., Ltd.
|Method and apparatus for controlling reading level of memory cell
|11. Sept. 2008
|30. Nov. 2010
|Samsung Electronics Co., Ltd.
|Memory device and data reading method
|10. Juli 2009
|6. Sept. 2011
|Samsung Electronics Co., Ltd.
|Nonvolatile memory device extracting parameters and nonvolatile memory system including the same
|22. M�rz 2010
|4. Sept. 2012
|Apple Inc.
|Database of memory read thresholds
|17. Okt. 2001
|25. Apr. 2002
|Fujitsu Limited
|Method of managing a defect in a flash memory
|2. Nov. 2001
|8. Mai 2003
|Sandisk Corporation
|Error management for writable tracking storage units
|25. Okt. 2002
|12. Juni 2003
|Eliyahou Harari
|Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
|3. Okt. 2003
|7. Apr. 2005
|Gonzalez Carlos J.
|Flash memory data correction and scrub techniques
|7. Apr. 2005
|20. Okt. 2005
|Sony Corporation
|Data readout circuit and semiconductor device having the same
|18. Okt. 2005
|23. Febr. 2006
|Gorobets Sergey A
|Corrected data storage and handling methods
|10. Nov. 2005
|23. M�rz 2006
|Gonzalez Carlos J
|Flash memory data correction and scrub techniques
|5. Mai 2006
|19. Okt. 2006
|Jason Lin
|Method for Non-Volatile Memory with Background Data Latch Caching During Erase Operations
|14. Sept. 2006
|26. Juli 2007
|Kabushiki Kaisha Toshiba
|Apparatus, method and computer program product for reading information stored in storage medium
|14. Mai 2007
|13. Sept. 2007
|Gonzalez Carlos J
|Flash Memory Data Correction and Scrub Techniques
|6. Juni 2006
|6. Dez. 2007
|Micron Technology, Inc.
|Programming a non-volatile memory device
|7. Mai 2007
|20. M�rz 2008
|Jing-Cheng Lin
|Prediction and control of NBTI of Integrated circuits
|3. Nov. 2006
|29. Mai 2008
|Yigal Brandman
|Nonvolatile Memory With Variable Read Threshold
|29. Dez. 2006
|3. Juli 2008
|Farookh Moogat
|Method of NAND Flash Memory Cell Array With Adaptive Memory State Partitioning
|29. Dez. 2006
|3. Juli 2008
|Farookh Moogat
|NAND Flash Memory Cell Array With Adaptive Memory State Partitioning
|26. Juni 2008
|1. Jan. 2009
|Samsung Electronics Co., Ltd.
|Flash memory device and method for adjusting read voltage of flash memory device
|31. M�rz 2009
|23. Juli 2009
|Gonzalez Carlos J
|Flash Memory Data Correction And Scrub Techniques
|17. Febr. 1997
|9. Juni 1999
|Sgs-Thomson Microelectronics S.A.
|Electrically alterable multilevel nonvolatile memory with autonomous refresh
|Titel nicht verf�gbar
|Lee et al., "Error Correction Technique for Multivalued MOS Memory," Electronic Letters, vol. 27, No. 15, Jul. 18, 1991, pp. 1321-1323.
|Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration for Int'l Application No. PCT/US2012/061617 mailed Mar. 14, 2013, 9 pages.
|Zitiert von Patent
|13. M�rz 2013
|27. Okt. 2015
|Sandisk Technologies Inc.
|Weighted read scrub for nonvolatile memory
|28. Febr. 2014
|29. M�rz 2016
|Kabushiki Kaisha Toshiba
|Memory system and constructing method of logical block
|21. Okt. 2014
|7. Febr. 2017
|International Business Machines Corporation
|Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
|12. Dez. 2014
|2. Mai 2017
|International Business Machines Corporation
|Device for selecting a level for at least one read voltage
|24. Juni 2016
|18. Juli 2017
|Sandisk Technologies Llc
|System solution for first read issue using time dependent read voltages
|15. Juni 2016
|25. Juli 2017
|Sandisk Technologies Llc
|Dynamic tuning of first read countermeasures
|22. Sept. 2015
|12. Sept. 2017
|Sandisk Technologies Llc
|Weighted read scrub for nonvolatile memory including memory holes
|13. M�rz 2013
|29. Mai 2014
|San Disk Technologies Inc.
|Weighted Read Scrub For Nonvolatile Memory
|28. Febr. 2014
|5. M�rz 2015
|Kabushiki Kaisha Toshiba
|Memory system and constructing method of logical block
|365/185.11, 365/185.09, 365/185.02
|Internationale Klassifikation
|20. Apr. 2012
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