text:
|Publication number
|Publication type
|Application number
|Publication date
|Apr 29, 2008
|Filing date
|May 17, 2002
|Priority date
|Mar 29, 2002
|Fee status
|Also published as
|Publication number
|Stephen M. Trimberger
|Original Assignee
|Xilinx, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (99), Non-Patent Citations (29), Referenced by (37), Classifications (23), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
A PLD (programmable logic device) is an integrated circuit that performs digital logic functions selected by a designer. PLDs include logic blocks and interconnect lines, and typically both the logic blocks and interconnect lines are programmable. One common type of PLD is an FPGA (field programmable gate array), in which the logic blocks typically include lookup tables and flip-flops that generate and store any logic function of their input signals. Another type of PLD is the CPLD (complex programmable logic device), in which the logic blocks perform the AND function and the OR function and the selection of input signals is programmable.
Designs implemented in PLDs have become so complex that it often takes months to complete and debug a design to be implemented in a PLD. When the design is going into a system of which the PLD is a part and is to be sold for profit, the designer does not want the result of this design effort to be copied by someone else. The designer often wants to keep the design a trade secret.
Many PLDS, particularly FPGAs, use volatile configuration memory that must be loaded from an external device such as a PROM every time the PLD is powered up. Since configuration data is stored external to the PLD and must be transmitted through a configuration access port, the privacy of the design can easily be violated by an attacker who monitors the data on the configuration access port, e.g. by putting probes on board traces.
Efforts have been made to encrypt designs, but it is difficult to make the design both secure from attackers and easy to use by legitimate users. Finding an appropriate encryption algorithm is not a problem. Several encryption algorithms, for example, the Data Encryption Standard (DES) and the more secure Advanced Encryption Standard (AES) algorithms are known for encrypting blocks of data. Cipher block chaining (CBC), in which each block of data is XORed with the immediately previous block and then encrypted, allows the DES or AES to encrypt a serial stream of data and these are therefore appropriate for encrypting a bitstream for configuring a PLD. A key used for encrypting the design must somehow be communicated in a secure way between the PLD and the structure that decrypts the design, so the design can be decrypted by the PLD before being used to configure the PLD. Then, once the PLD has been configured using the unencrypted design, the design must continue to be protected from unauthorized discovery. And, to make matters still more difficult, a single PLD configuration may include "cores," or subdesigns, from several vendors, and each vendor may use a different key to protect his or her core.
A Nov. 24, 1997, publication by Peter Alfke of Xilinx, Inc., entitled "Configuration Issues: Power-up, Volatility, Security, Battery Back-up" describes several steps that can be taken to protect a design in an existing FPGA device having no particular architectural features within the FPGA to protect the design. Loading design configuration data into the FPGA and then removing the source of the configuration data but using a battery to maintain continuous power to the FPGA while holding the FPGA in a standby non-operational mode is one method. However, power and system cost requirements make this method impractical for many applications.
Nonvolatile configuration memory is another possibility. If the design is loaded at the factory before the device is sold, it is difficult for a purchaser of the configured PLD device to determine what the design is. It is possible, however, to discover the program states of non-volatile memories, and consequently to reverse-engineer proprietary PLD designs. Some memory technologies, such as antifuses, are vulnerable to inspection under a microscope. Memory technologies that rely on stored charge can be attacked by chemically treating memory cells to determine their charge states after removing overlaying metal layers. Also disadvantageous, nonvolatile memory fabrication requires a more complex and more expensive process technology than standard CMOS process technology, and takes longer to bring to market.
It is also known to store a decryption key in nonvolatile memory in a PLD, load an encrypted bitstream into the PLD and decrypt the bitstream using the stored key. This prevents an attacker from reading the bitstream as it is being loaded into the PLD, and does retain the key when power is removed from the PLD. Such arrangements are described by Austin in U.S. Pat. No. 5,388,157 and by Trimberger in U.S. patent application Ser. No. 09/253,401 entitled "Method and Apparatus for Protecting Proprietary Configuration Data for Programmable Logic Devices," both of which are incorporated herein by reference. However, these arrangements do not protect user's designs from all modes of attack.
There is a need for additional design protection methods that are convenient, reliable, and secure.
The present invention is directed to methods and structures for configuring PLDS using encrypted configuration data. PLDs in accordance with the invention are adapted to include a decryptor and one or more non-volatile memory elements, each programmed with a secret decryption key. Encrypted configuration data representing some desired circuit function is presented to the decryptor. The decryptor then decrypts the configuration data, using a secret decryption key, and configures the FPGA with the decrypted configuration data.
Some PLDs offer the option of partial configuration (where several configuration addresses are specified for loading several portions of a design) and partial reconfiguration (where an existing design is not erased before new design data are loaded). If the PLD offers these options, an attacker could partially reconfigure a PLD with his or her own bitstream in a "Trojan Horse" attack to make successive portions of the design visible, and possibly learn the whole design. To avoid such an attack, each entity responsible for contributing a subdesign for a PLD configuration includes a shared password with the bitstream specifying their subdesign. The shared password is then encrypted along with the rest of the configuration data. The PLD will not function with any design not including the shared password to authenticate the design. The shared password can be stored in non-volatile memory prior to configuration, or the first core loaded into the PLD can be adapted to store the shared password in volatile or non-volatile memory.
In another embodiment, a non-volatile memory in the PLD stores a message-authentication code (MAC) for each subdesign (core) to be loaded into the PLD. The MAC might be, for example, a hash function of a bitstream defining a subdesign. The hash function of each subdesign bitstream can then be compared with the appropriated MAC to authenticate the subdesign. The PLD will not function with any design (e.g., a Trojan Horse) that does not produce the appropriate MAC.
PLD configuration memory is typically divided into "frames." One embodiment of the invention reduces the risks associated with Trojan Horse attacks by preventing the overwriting of frames between device resets.
One programmable logic system in accordance with the invention provides improved key security and simplifies the process of upgrading PLDs in the field using proprietary configuration data. A PLD is connected to an external memory that stores one or more decryption keys to be loaded onto the PLD. The system also includes some key-write control circuitry that transfers one or more of the decryption keys from the external memory to the PLD. The key-write control circuitry then clears any keys transferred to the PLD so the keys are no longer accessible from outside the PLD.
Encrypted configuration data cannot be read without the correct key, so it is important to verify the integrity of decryption keys stored in a programmable logic device. However, it is equally important to maintain the secrecy of the keys during key verification. A system in accordance with the invention addresses this issue by allowing users to verify the validity of decryption keys without allowing users access to the keys. A one-way function, such as a cyclic redundancy check (CRC), is performed by the author of the decryption key, and the resulting value is distributed to a user authorized to verify key validity. To verify the key, the user loads the CRC value into a register in the PLD, where the CRC value is compared with a second CRC value generated by an on-chip CRC generator connected to the key memory. The key is deemed valid if the CRC values match.
Another embodiment enables users to verify keys while maintaining secrecy by providing read- and write-protect fields associated with each key field on a PLD. A user can write to any key field not write-protected, and can read from any key field not read-protected. A user can thus write and verify keys, so long as the read- and write-protect fields are not set. Once satisfied, the user can set the read-protect field to prevent future reads.
Setting the read-protect field bars any future read access to the stored key, but does not bar future use of the key field in which the key is stored. For example, the user may overwrite the stored key with the same or a different key. This possibility leaves the PLD exposed to potential "Trojan Horse" attacks. The user therefore has the option of setting the write-protect field for one or more key fields to disallow writing any additional keys.
Another embodiment addresses the possibility of key errors using error correction. In this embodiment, a PLD includes, for each decryption-key field in key memory, an associated correction-code (ECC) field. The PLD additionally includes error-correction circuitry that receives each key and associated ECC and performs an error correction before conveying the resulting error-corrected key to a decryptor. The error correction circuitry can perform, for example, the well-known Hamming error-correction technique.
Another embodiment employs a PLD with a number of internal, "hard-wired" (e.g., mask programmed) decryption keys. In this embodiment, only the manufacturer knows the encryption/decryption keys. Users can nevertheless employ the keys to encrypt configuration data by specifying one of the keys in software. The user may, for example, specify a decryption key embedded in software stored in a conventional computer on e.g. a hard disk or some other form of computer-readable medium. In this embodiment, the keys are never transmitted, so they cannot be probed; instead, only the address of the specified decryption key is conveyed between the computer and the PLD.
Another embodiment further protects decryption keys by encrypting the keys themselves before transferring them to a key memory in the target PLD, thus ensuring the keys will not be compromised in transit. One such embodiment encrypts a decryption key for decrypting configuration data (the "configuration key") using a Public-Key Encryption algorithm (e.g., RSA). The configuration key is encrypted using a public key prior to transfer to the PLD. Once in the PLD, the configuration key is decrypted using a private key previously stored on the PLD. The decryptor used to decrypt the configuration key can be instantiated on the PLD using programmable resources.
Another embodiment includes a PLD in which the key memory can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The PLD supports secure and non-secure modes on a key-by-key basis. Users may therefore write, verify, and erase individual keys without affecting others.
This summary does not define the scope of the invention, which is instead defined by the appended claims.
The FPGA also includes configuration memory 12 for turning on routing transistors, controlling multiplexers, storing lookup tables, and controlling the input/output blocks, all of this for the purpose of configuring the FPGA to perform the function desired by the designer(s). Bus 16 connects configuration memory 12 to programmable logic 11 and is typically a distributed set of control lines located throughout the FPGA. Some Xilinx products (e.g. XC6200) include a bus 17 by which programmable logic 11 causes configuration logic 14 to send programming information to configuration memory 12. Such a structure is described by Kean in U.S. Reissue Pat. RE37,195 E, entitled "Programmable Switch for FPGA Input/Output Signals", which is incorporated herein by reference.
FPGA 10 further includes a JTAG logic block 13 for interfacing with JTAG port 20, especially intended for testing of the board in which the FPGA will be placed. JTAG logic block 13 implements the IEEE standard 1532, which is a superset of the IEEE standard 1149.1. JTAG conventionally allows debugging of a design at the board level.
Finally, FPGA 10 includes configuration logic 14 for responding to a configuration bitstream from external source 15 on configuration access port 21 and for interfacing with JTAG logic block 13. The bitstream on configuration access port 21 is treated as words, in one embodiment 32-bit words. Several of the words, usually at or near the beginning of the bitstream, are used for setting up the configuration process and include, for example, length of a configuration memory frame and a starting address for the configuration data. Bus 19 allows communication between configuration logic 14 and JTAG logic block 13 so that the JTAG port 20 can be used as another configuration access port. Bus 18 allows communication between configuration logic block 14 and configuration memory 12. In particular, bus 18 carries addresses to select configuration frames in memory 12, control signals to perform write and read operations, and data for loading into configuration memory 12 or reading back from configuration memory 12.
Configuration Logic block 14 receives instructions and data, and processes the data according to the instructions. These instructions and data come into configuration logic 14 as a bitstream. An instruction, or header, is usually followed by data to be acted upon.
The Configuration Logic Register address (16 bits) shown in
For readback, a read command is placed in the op code field and the Frame Data Output register is addressed, followed by a Word Count (using Command Header Format 2 if necessary). The specified number of words is read back from configuration memory 12, starting at the address specified in the Frame Address register, and shifted out on either configuration access port 21 or JTAG port 20. (Readback data is returned to the port that issued the readback instruction).
Specifying a word count in a bitstream header or pair of headers (
Configuration logic 14 typically performs a cyclic redundancy check (CRC) on a configuration bitstream coming in (see Erickson, U.S. Pat. No. 5,321,704 incorporated herein by reference, or see pages 39 through 40 of the above-referenced Virtex Configuration Guide), reads header bits indicating the frame length of the part being configured and the word count of the configuration data, reads address instructions identifying where to load configuration data, collects frames of configuration data and loads them into columns of configuration memory 12 indicated in the addresses. Configuration logic 14 also controls readback of configuration data and flip-flop values from configuration memory 12 to an external location. In a Virtex FPGA available from Xilinx, Inc., readback can be done through either JTAG port 20 or through configuration access port 21. Because the act of reading back the bitstream would expose the unencrypted bitstream to view, readback is disabled for configurations that employ decryption keys.
Configuration logic 14 can also receive configuration data from programmable logic 11. More information about prior art FPGA structures in which part of the FPGA configures another part of the FPGA can be found in Kean, U.S. Reissue Pat. RE37,195 E. More information about architectures of FPGAs similar to the Virtex architecture can be found in Young et al., U.S. Pat. No. 5,914,616. Both patents are incorporated herein by reference. The format of a bitstream used with the Virtex product available from Xilinx, Inc., assignee of the present invention, is described in an Application Note, XAPP138, entitled "Virtex FPGA Series Configuration and Readback" available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124 published Oct. 4, 2000, which is also incorporated herein by reference.
Bus 25 carries data, addresses, and control signals to perform write and read operations and allows programming of the decryption keys and configuration passwords from JTAG port 20. An optional bus 26 between configuration logic and memory 23 allows programming of keys and passwords via configuration access port 21. Bus 26 may also carry security data from memory 23 to configuration logic 29. In one embodiment, bus 27 carries encrypted configuration data from configuration logic 29 to decryptor 24 and carries decrypted configuration data back to configuration logic 29. Bus 28 allows decryptor 24 to access the keys for decrypting data. When the structure of
In some embodiments, the bitstream for a design or a subdesign comprises two portions, a data portion representing the user's design that can be encrypted or not, and a control portion controlling loading of the bitstream (for example giving addresses of columns in the PLD into which successive portions of the bitstream are to be loaded, providing a CRC code for checking reliability of the loading operation, and a starter number for cipher block chaining (CBC), a technique that prevents a "dictionary attack" where the decrypted data can be deduced from the frequency of occurrence of the encrypted data). Such embodiments are detailed in U.S. patent application Ser. No. 09/724,652, entitled "PROGRAMMABLE LOGIC DEVICE WITH DECRYPTION ALGORITHM AND DECRYPTION KEY," by Pang et al. In other embodiments, used when the order of addresses in which configuration data is loaded may be useful to an attacker in analyzing the design, the address of the configuration data is also encrypted, but other control information in the configuration bitstream remains unencrypted. This too is detailed in the above-referenced Pang et al. application.
As noted above in the background section, sometimes a single FPGA configuration includes a number of subdesigns, or cores, designed by different entities. For example, a circuit designer may employ an FPGA to create a circuit that includes a standard interface (e.g., the popular PCI interface) and some glue logic specific to the designer's needs. In such a case, the designer might opt to purchase a design for the standard interface from a core vendor to save valuable time. Both the core vendor and the designer, fearing copyists, may want to separately encrypt the data defining their respective designs. One embodiment of the invention thus affords each of several entities responsible for portions of a single PLD design the ability to separately protect their portion of the design. Some FPGAs allow partial reconfiguration of the FPGA or allow different parts of a design to be loaded into different parts of the FPGA using separate starting addresses and separate write instructions. An attacker might attempt to learn the design by partially reconfiguring the FPGA to read contents of a block RAM or flip-flops directly to output ports or by adding a section to an existing design to read out information that can be used to learn the design. For example, the attacker might partially reconfigure the FPGA with an unencrypted design whose only purpose is to extract information about the encrypted design. Such a "Trojan Horse" design could be loaded into the PLD with another bitstream or attached to an existing encrypted bitstream. If the attacker was interested in learning a state machine design loaded into block RAM of an FPGA, for example, the Trojan Horse design could include logic to cycle through the addresses of the block RAM and send the block RAM data contents to device pins for observations. Various embodiments of the invention prevent attackers from gaining access to decrypted configuration data using "Trojan Horse" attacks. (For additional methods and circuits for protecting against Trojan Horse attacks, see co-pending application Ser. No. 10/112,838, filed Mar. 29, 2002 and entitled "Method and Apparatus for Protecting Proprietary Configuration Data for Programmable Logic Devices," by Stephen M. Trimberger, which is incorporated herein by references.)
The bitstream of
Bus 28 connects to input and output ports of decryptor 24, and includes the following:
One potential attack on a design in an encrypted bitstream is to change the frame address register (starting address) in the encrypted bitstream so that when it is decrypted it is loaded into a portion of the FPGA visible when the FPGA is being used. In some designs the content of the block RAM is visible. In all designs the configuration of the input/output ports is visible and therefore the configuration bits can be determined. Thus if successive portions of the design were moved to visible portions of the FPGA, even though the FPGA did not function properly, an attacker could in repeated relocation learn the contents of the unencrypted bitstream.
Configuration logic 29 includes the structures to support optional encryption, to prevent design relocation, and to prevent the incorporation of Trojan-Horse designs. As shown in
A 64-bit shift register 299 receives data from configuration access port 21, which can be a single pin for 1-bit wide data or 8 pins for 8-bit wide data. This data is loaded into 64-bit shift register 299 until register 299 is full. Then these 64 bits are preferably shifted in parallel into 64-bit transfer register 298. From there, multiplexer 296 b alternately selects right and left 32-bit words, and multiplexer 296 a moves the data 32 bits at a time either into holding register 292 or alternately into High and Low portions of assembly register 297 as controlled by control line M. When loading of the bitstream begins, line M and a clock signal (not shown) cause multiplexers 296 a and 296 b to move data from 64-bit transfer register 298 to holding register 292. From there these words are applied to control logic 291. If the word is a header, control logic 291 interprets the word. If the op code indicates the data to follow are to be written unencrypted, control logic 291 places an address on bus G to select a register, places a signal on line L to cause multiplexer 294 to connect bus B to bus D, and applies the following word on bus B. On the next clock signal (clock signals are not shown), the data on bus D are loaded into the addressed register. The init CBC register for loading the initial cipher block chaining value and the password register PWD are each 64-bit registers, and each receive two consecutive 32-bit words. In one embodiment, the password is sent, by convention, as the last word in a given subdesign, though other conventions might also be used.
A modified CBC value formed from (1) the original CBC value stored in the init CBC register and (2) the initial frame address stored in the FAR register is available to decryptor 24. In one embodiment, the initial frame address in the FAR register uses no more than 32 bits while the init CBC value uses 64 bits. In the embodiment of
The decryption process begins when control logic 291 receives an op code command to decrypt a number of words of configuration data. Control line M causes multiplexer 296 a to apply data from transfer register 298 to bus A leading to assembly register 297. Control bus H alternately connects bus A to the High[31:0] and Low[31:0] portions of encrypted data register 297 to form a 64-bit word to be decrypted. Control logic 291 then asserts the Enc_data_rdy signal, which causes decryptor 24 to decrypt the data in register 297.
To perform the decryption, decryptor 24 applies a key address KeyAddr on bus 28 to key memory 303 within memory 23. This causes key memory 303 to return the 56-bit key in that address on the 56-bit Key lines. It also causes key memory 303 to return two additional bits "Order" also stored in the key data at that address. For the first decryption key, these two bits must indicate that this is a first key or an only key. If not, decryptor 24 asserts the Bad_key_set signal, which causes control logic 29 to abort the configuration operation. If these two bits indicate the key is a first or only key, decryptor 24 performs the decryption, using for example the well-known DES algorithm. The DES algorithm is described by Bruce Schneier in "Applied Cryptography Second Edition: protocols, algorithms, and source code in C" copyright 1996 by Bruce Schneier, published by John Wiley & Sons, Inc., at pages 265–278, which is incorporated herein by reference.
If the key isn't an only key, decryptor 24 then gets the key at the next address in key memory 303 and checks to see whether the two Order bits indicate it is a middle or last key. If not, the Bad_key_set signal is asserted and the configuration is aborted. If so, decryption is performed. If it is a middle key, another round of decryption is done. If it is the last key, decryptor 24 forms the XOR function of the decrypted word and the value modCBC. Decryptor 24 then places the resultant value on the 64-bit Decrypted_data bus and asserts the Dec_data_rdy signal. This causes control logic 291 to place signals on control line K to cause multiplexer 295 to break the 64-bit word into two sequential 32-bit words. Control logic 291 places a signal on line L to cause multiplexer 294 to forward the 32-bit words of decrypted data to bus D. Control logic 291 also places address signals on bus G to address frame data input register FDRI. The next clock signal moves the decrypted data to bus E where it is loaded into the frame register and when the frame register is full, eventually shifted into configuration memory 12 at the address indicated in the FAR register.
The modCBC value is used only once in the decryption operation. Subsequent 64-bit words of encrypted data are decrypted and then chained using the previously decrypted data for the XOR operation. (The value stored in the FAR register is also used only once to select a frame address. Subsequently, the frame address is simply incremented every time a frame is filled.) In one embodiment, the last 64-bit block of encrypted data is written to register PWD. When the decryption is complete for a given subdesign, the password in register PWD is compared with a preloaded value in a non-volatile memory location 300 within memory 23. If the password does not match the preloaded value, configuration fails; otherwise, the configuration process moves to the next subdesign, if any.
A second embodiment eliminates the need to preload the shared password into non-volatile memory. In that embodiment, those who contribute to the designs expressed in the configuration bitstream agree upon a password. The bitstream associated with the first-loaded subdesign is then used to store a password address in a password-select register PWS and the password both in register PWD and in a memory location 302, typically SRAM, identified by a value stored in register PWS. Subsequent configuration data associated with other subdesigns then have their decrypted passwords checked against the value stored in memory location 302. (Memory location 302 and password select register PWS are cross-hatched to illustrate their association with the second embodiment.)
In accordance with a third embodiment, a message-authentication code (MAC) for each subdesign is pre-calculated off chip by the author of a subdesign and is subsequently loaded with the subdesign bitstream into NVM 300, before configuration, at an address corresponding to the order that the subdesign is to be loaded into the PLD. (In the present disclosure, a "MAC" is any result of a one-way function used to authenticate a design or subdesign.) A MAC generator 304 then calculates the MAC for each subdesign as the subdesign is loaded and compares the result with the respective MAC in NVM 300. This embodiment does not require the password register PWD, password-select register PWS, or memory 302, but one or more of these may nevertheless be included to support more than one method of protecting proprietary configuration data. An XOR gate 305 graphically depicts the comparison between the MAC from MAC generator 304 and the associated value stored in memory 303. (MAC generator 304 and XOR gate 305 are shaded to illustrate their association with the third embodiment.)
For a more detailed discussion of how one might perform a hash function on a design to develop a MAC for the design, see U.S. application Ser. No. 09/253,401 entitled "Method and Apparatus for Protecting Proprietary Configuration Data for Programmable Logic Device," by Stephen M. Trimberger, which is incorporated herein by reference. Another way to make a MAC is described by Schneier in "Applied Cryptography, Second Edition," (1996) on page 456. Schneier describes a way to make a key-dependent one-way hash function by encrypting a message with a block algorithm in the CBC mode, as specified in ANSI X9.9, a United States national wholesale banking standard for authentication of financial transactions. ANSI X9.9 is incorporated herein by reference.
In another embodiment, the author of one subdesign computes a MAC for his or her subdesign and then shares the MAC with the authors of other subdesigns for incorporation into their respective bitstreams. Upon loading the bitstream of the first subdesign, MAC generator 304 computes and stores the MAC of the first subdesign. The MAC may be calculated from either the encrypted or the decrypted bitstream. Subsequently loaded subdesigns must include the stored MAC.
At step 74, 32 bits (1 word) of configuration data are sent to the addressed frame of configuration memory 12. If step 75 indicates the counter is not finished, then at step 76 the counter is decremented and the next word of configuration data is sent to configuration memory 12. When the counter has finished, configuration logic 29 performs cleanup activities, including reading the final cyclic redundancy check value to compare with a value at the end of the bitstream to determine whether there were any errors in loading the bitstream.
If step 73 indicates the bitstream is encrypted, at step 81 the process loads the initial key address from key address register 293 (
At step 82, two words (64 bits) of encrypted configuration data are loaded into decryptor 24. At step 83 the addressed key is loaded into decryptor 24. In one embodiment, a 64-bit number is loaded into decryptor 24. This 64-bit number includes a 56-bit key and some other bits that may be unused, used for parity, or used for another purpose. For example, an embodiment that supports multiple-key encryption/decryption described in the above-mentioned Pang et al. U.S. patent application Ser. No. 09/724,652 entitled "PROGRAMMABLE LOGIC DEVICE WITH DECRYPTION ALGORITHM AND DECRYPTION KEY" employs two of these bits to indicate whether a given key is the first, middle, last, or only key used with a collection of encrypted data. In another embodiment, extra bits are not present and the key data uses less than 64 bits.
At step 84, decryptor 24 decrypts the 64-bit data with the 56-bit key using, for example, the DES algorithm. The DES algorithm is described in the above-mentioned book by Bruce Schneier at pages 265 to 278. Other encryption algorithms may also be used, for example, the advanced encryption standard AES. Other algorithms may require more key bits and more data bits in each block. For example AES requires a key of 128 to 256 bits.
At step 87, the modified CBC value shown in
At step 88, this decrypted configuration data is sent on bus 27 (
At decision 92, the counter is checked to determine whether there is more data associated with the subdesign bitstream. If not finished, the counter is decremented and the process returns to step 82 where the next 64 bits (2 words) are loaded from the bitstream; otherwise, step 93 sets the value in register PWD to the last word. Finally, at decision 90, a CRC (cyclic redundancy check) value in the bitstream is compared with a CRC value calculated as the bitstream is loaded, and the password within memory 300 is compared with the decrypted password in register PWD. The calculated and stored CRC values must match or the design is assumed to be corrupt; the decrypted and stored passwords must also match to verify the source of the configuration data. A mismatch between the CRCs or between the passwords generates a loading error, and the configuration process aborts. If the CRCs and passwords do match, the process either continues to the next subdesign, if any, (decision 95) or the FPGA is operational.
In the depicted embodiment, each subdesign is encrypted with a single encryption key. Other embodiments employ multi-key encryption and decryption, as discusses in the above-incorporated Pang et al. reference.
After the last word is loaded into register PWD, configuration logic 29 determines whether the subdesign being loaded is the first subdesign (decision 93); if so, then the shared session password in register PWD is stored within memory location 302 identified by a value stored in register PWS (step 94). If the subdesign being loaded is not the first, then the password associated with the subdesign is compared with the password loaded into memory 302 by the first subdesign. Decision 90 and the steps that follow are identical to those discussed in connection with
As noted above, in one embodiment the session password is a MAC calculated on the first subdesign and shared with the authors of other subdesigns. In accordance with that embodiment, the flow of
Beginning at step 96, the MAC associated with a given subdesign is calculated off chip (e.g., by a computer) and inserted into the bitstream header of a subdesign. Configuration logic 29 then begins the configuration process at step 70 (
After step 70, the process continues from step 71 to step 88, via decision 73, as discussed above in connection with
In another embodiment, the MAC of the first of a plurality of subdesigns is calculated and stored as a session password instead of a password sent explicitly as part of the first subdesign. All remaining subdesigns then submit a password that matches the calculated MAC of the first subdesign.
Array 900 conventionally includes a frame address register 905 connected via a number N of address lines A0–AN to a plurality of memory frames 910. Each of frames 910 in turn includes a plurality of memory cells 915, each of which is adapted to store a single configuration bit. As is conventional, array 900 is loaded frame-by-frame with configuration data that defines the functionality of the associated PLD.
In accordance with this embodiment, array 900 also includes a collection of "been written" memory elements 920 that store information indicating which, if any, of frames 910 have been written to. Memory elements 920, collectively termed "frame-access-protection circuitry," prevent the overwriting of any frame in array 900 previously loaded with configuration data, and consequently prevent "Trojan horse" designs from occupying previously configured frames.
The following describes the function of the left-most frame 910 of
Once reset, each frame 910 is prepared to receive configuration data. To write configuration data into the memory cells 915 associated with address line A4, configuration logic 29 (
Deselecting address line A4 produces a falling edge on the clock terminal of flip-flop 935, causing the Q and Q-bar outputs to transition to logic one and logic zero, respectively. Consequently, the complementary output Q-bar presents a logic zero through OR gate 950 to frame-write-enable terminal FWE of the associated AND gate 940. AND gate 940 will consequently block any further address signals on line A4 until flip-flop 935 and the associated frame is reset. Memory element 920 thus bars write access to the associated memory frame 910, leaving the remaining "empty" frames 910 free to receive configuration data. In one embodiment, the frames can only be reset using a command that purges all frames on the PLD. A Trojan Horse design is thus prevented from occupying any frame formerly occupied by a proprietary collection of configuration data when any portion of the proprietary collection of configuration data remains in configuration memory.
AND gates 945 and OR gate 955 are provided, in one embodiment, to generate a frame-error signal FERR in response to an attempt to overwrite a frame. The frame-error signal is generated if a address line is brought high after one of flip-flops 930 is set, indicating an attempted write to an occupied frame. In practice, OR gate 955 would include an input from a memory element 920 for each overwrite-protected frame.
The depicted embodiment includes a register for each frame. Other embodiments might employ fewer memory elements to identify those memory frames storing configuration data. In other embodiments, for example, the PLD can be modified as follows:
In each of the above-described embodiments, decryption keys are loaded into memory 24 via an access port (e.g., the configuration access port or the JTAG access port) of FPGA 31. As the keys are loaded, an attacker who monitors the data on the access port can easily violate the privacy of the keys, e.g. by putting probes on board traces. Such attacks are not normally a problem, as a manufacturer interested in maintaining the secrecy of the design typically loads the keys; however, maintaining key security is more difficult when logic designs are updated in the field, and it would be desirable to relieve the manufacturer of the onus of maintaining key security.
Memory 1005 might be one of the Xilinx XC18V00 Series of In-System Programmable Configuration PROMs; Key-write control circuitry 1010 might be a member of the Xilinx XC9500 In-System Programmable CPLD Family. Key memory 1005 preferably includes an array of non-volatile memory that does not require power to maintain data in the array.
In embodiments in which the key or keys are pre-loaded in memory 1005, the key-bearing memory 1005 is physically added to system 1000 (step 1025). Next, power is applied to system 1000 (step 1030), which conventionally initiates a configuration cycle. Key-write control circuitry 1010 then checks memory 1005 for a key (decision 1035): if there is no key in memory 1005, FPGA 31 configures normally using data from external source 15 (step 1040). If there is a key in memory 1005, key-write control circuitry 1010 retrieves the key from memory 1005 and transmits the key FPGA 31, where the key is stored in key memory 24 (step 1045). Key-write control circuitry 1010 then clears the key from memory 1005 by issuing a clear command on bus 1003 (step 1050) and FPGA 31 configures normally (step 1040).
In an embodiment in which key memory 1005 is a Xilinx ISP ROM, key-write control circuitry 1010 and memory 1005 communicate using the Xilinx serial-PROM protocol, and key-write control circuitry 1010 communicates with JTAG logic 13 using the JTAG standard.
Encrypted configuration data cannot be properly loaded into a PLD without the correct key, so it is important to verify the integrity of decryption keys stored in programmable logic devices. However, due to the secure nature of the keys, it is equally important to maintain the secrecy of the keys during key verification.
The embodiment of
Setting the read-protect field bars any future read access to the stored key, but does not bar future use of the key field in which the key is stored. For example, the user may overwrite the stored key with the same or a different key. This possibility leaves system 1200 exposed to potential "Trojan Horse" attacks. The user therefore has the option of setting a write-protect field for one or all key fields to disallow writing any additional keys (step 1220).
System 1300 additionally includes error-correction circuitry 1315 that receives each key and associated ECC and performs and error correction before conveying the resulting error-corrected key to decryptor 24. Error correction circuitry 1315 can perform, for example, the well-known Hamming error-correction technique.
FPGA 1405 includes a key source 1420, in one embodiment a mask-programmable memory hardwired to include one or more decryption keys 1425. Because keys 1425 are hardwired, the user cannot choose his or her encryption/decryption key. Instead, the user specifies a decryption key in software stored in computer 1415 on e.g. and hard disk or some other form of computer-readable medium. For example, a user may specify in software that a given set of configuration data be encrypted using key #2. "Key #2" is hidden in software and is duplicated in memory 1420 at a key address associated in software with key #2. In this embodiment, the keys are never transmitted, so they cannot be probed; instead, only the key address is conveyed between computer 1415 and memory 1410.
Keys are hidden in software by obscurity. The user will not know where in the compiled code to look for the keys. Further, the keys can be broken up within the code, encrypted with yet another obscure key, etc., to render finding the key(s) more difficult.
Key source 1420 may generate keys instead of—or in addition to—storing keys. In one embodiment, for example, key source 1420 includes a circuit, such as a linear-feedback shift register (LFSR), for generating decryption keys. In such cases, computer 1415 is adapted to generate the appropriate encryption key. For example, computer 1415 might perform the LFSR algorithm for e.g. 100 clock cycles and use the resulting value for encryption; an LFSR in the FPGA receiving the bitstream would then generate the same value using the same algorithm and the same number of clock cycles.
Next, key-write control circuitry 1515 enables FPGA 1510 and sends the encrypted configuration key to FPGA 1510 (step 1550). Configuration logic 29 then retrieves the private counterpart of the public key used to encrypt the configuration key and uses the decryptor instantiated in programmable logic 11 to decrypt the configuration key (step 1555). Configuration logic 29 stores the decrypted configuration key in configuration-key field 1530 (step 1560). Finally, key-write control circuitry 1515 resets FPGA 1510 to allow FPGA 1510 to configure itself using the encrypted configuration data in external source 15 (step 1565). In one embodiment, key-write control circuitry 1515 is a Xilinx CPLD, and memory 1505 is a Xilinx ISP ROM.
U.S. patent application Ser. No. 09/724,652, entitled "PROGRAMMABLE LOGIC DEVICE WITH DECRYPTION ALGORITHM AND DECRYPTION KEY," by Pang et al., and incorporated herein by reference, describes an FPGA with a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. In that embodiment, entering the non-secure mode automatically deletes any stored decryption keys.
FPGA 1600 includes configuration logic 1605 similar to configuration logic 29 of
Configuration logic 29 receives signals from JTAG bus logic 13. JTAG logic 13 conforms to the IEEE 1532 JTAG standard. Before key memory 23 can be accessed through JTAG bus 25, FPGA 1600 is placed in the non-secure mode by resetting (e.g., setting to a logic zero) the secure-key flag in register SKF and loading a key address into address register Addr. The selected address can then be written to or read from, leaving the remaining keys, if any, intact. Key memory 23 is written to and read from (for verification) over JTAG bus 25 using the ISC_PROGRAM and ISC_READ instructions of the IEEE 1532 standard.
Next, at JTAG instruction to JTAG logic 13 loads address register Addr with a desired key address (step 1610). This step automatically clears the contents, if any, of the selected memory location (step 1615), before granting access to the designated key field (step 1620). Clearing the memory before granting access prevents anyone from viewing previously stored keys.
After step 1620, the user can write or read to the designated key field until satisfied that the correct key is stored in memory 23. Next, in step 1625, the user sets the secure key flag in register SKF (e.g., to a logic 1) to return FPGA 1600 to the secure-key mode. Another embodiment eliminates register SKF, instead allowing address register Addr to be set to a secure-key address that does not correspond to any key address. Including register SKF avoids the need for a dummy key address and affords some protection against accidentally erasing an encryption key from memory 23.
As with
In some embodiments, the bitstream for a design or a subdesign comprises two or more portions, each of which may be encrypted using a different key. Prior to loading, the author of each portion calculates the byte count for his or her portion and loads the required decryption key and byte count into key and count memory 1705. The designs are then loaded together as a single bitstream; partial reconfiguration is not allowed.
FPGA 1700 decrypts the first portions using the first password. At the start of the partial bitstream, configuration logic 29 loads the count associated with the decryption key for the first portions into a decrementing counter. The counter then decrements for each byte decrypted, reaching a count of zero when the first portion is fully decrypted. Configuration logic 29 then selects the subsequent key address in key and count memory 1705 to obtain the decryption key and associated count for the next portion of the bitstream.
In another embodiment, the count is not stored in memory 1705, but is instead passed to FPGA 1700 as part of the bitstream. For example, the count may be in the encrypted data, or may be determined by a specific data pattern (a word that decrypts to all zeros, for example).
The configuration bitstream includes a header specifying the address in memory 1705 corresponding to the first key/count pair. In step 1725, configuration logic 29 retrieves the decryption key and the associated count (e.g., "CNT_1"). Configuration logic 29 then employs the key to decrypt the number of bytes specified by the count (step 1730). In one embodiment, configuration logic 29 includes a counter that counts down from CNT_1 to zero. When finished with the first portion of the bitstream, configuration logic 29 retrieves the next decryption key in memory 1705 and the associated count CNT_2 (step 1735). (In another embodiment, each key is separately addressed by the bitstream.) Configuration logic 29 then decrypts the number of bytes specified by CNT_2 (step 1740).
The embodiments of
The above description of the drawings gives detail on a few embodiments. However, many additional embodiments are also possible. By way of example:
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|Secure processor operation using integrated circuit configuration circuitry
|Feb 2, 2009
|May 30, 2017
|Infineon Technologies Ag
|Secure manufacturing of programmable devices
|Feb 17, 2014
|Sep 5, 2017
|Microchip Technology Incorporated
|Programmable device personalization
|May 28, 2004
|Dec 15, 2005
|International Business Machines Corporation
|Method for system level protection of field programmable logic devices
|Jul 9, 2004
|Aug 10, 2006
|Peter Rostin
|Secure seed generation protocol
|Jul 31, 2007
|Feb 5, 2009
|Sabev Anton I
|Asymmetric key wrapping using a symmetric cipher
|Feb 5, 2009
|Sep 24, 2009
|Viasat, Inc.
|System security manager
|Feb 2, 2009
|Apr 1, 2010
|Infineon Technologies North America Corp.
|Secure Manufacturing of Programmable Devices
|Feb 2, 2009
|Apr 1, 2010
|Infineon Technologies North America Corp.
|Secure Partitioning of Programmable Devices
|Feb 2, 2009
|Apr 1, 2010
|Infineon Technologies North America Corp.
|Secure Operation of Programmable Devices
|Dec 31, 2008
|Jul 1, 2010
|Sungwon Moh
|System and method for data recovery in a disabled integrated circuit
|Jun 3, 2011
|Dec 6, 2012
|Callas Jonathan D
|Secure storage of full disk encryption keys
|Dec 15, 2011
|Feb 5, 2015
|Hormuzd M. Khosravi
|Method and device for secure communications over a network using a hardware security engine
|Feb 17, 2014
|Mar 24, 2016
|Michael Simmons
|Programmable Device Personalization
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|May 17, 2002
Owner name: XILINX, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRIMBERGER, STEPHEN M.;REEL/FRAME:012915/0078
Effective date: 20020328
|Oct 31, 2011
|Fee payment
Year of fee payment: 4
|Oct 29, 2015
|Fee payment
Year of fee payment: 8


text:
Good for the price
For the price, these are great headphones. Great clarity and good bass. I expected them to be a bit louder and the bass to be a little bit deeper but thats because i was comparing them to the Beats By Dre Studios that i lost. Couldn't see myself paying $300 for another pair of headphones. The biggest downfall of these headphones for me is the huge 6.3mm jack. These were clearly designed for home use. I am deployed and intended to use these with my Iphone5. they come with a 3.5mm adapter which is good except that it now makes the jack 3/4 the length of my phone and its also thicker in diameter than my phone is. It's very bulky and inconvenient. I wish the original plug was 3.5mm with a 6.3mm adapter. I've been searching for a replacement from the manufacturer but none exist. I've tried to use other 3.5 to 3.5 male cables but they wont fit in the actual headphone. because of the size of the plug and adapter, i cant use these headphones while i walk around or at the gym as i intended because its very uncomfortable to put in your pocket or use with a sports strap. i almost wish i'd paid the extra $ for another pair of Beats.
Pros: great sound for the price
Cons: Cabling and adapters not ideal for mobile devices.

subset: commoncrawl


text:
Image: Western Cleaner Clingfish at Rapid Bay
A Western Cleaner Clingfish at a depth of 6 m, Rapid Bay Jetty, South Australia, 14 May 2010.
- Photographer:
- Phil Mercurio
- Rights:
- © Phil Mercurio
The Western Cleaner Clingfish looks similar to the Eastern Cleaner Clingfish. The latter has less regular blue bars on the back and lacks the bluish colouration on the tail.
Last Updated:
Tags fishes, ichthyology, Cochleoceps orientalis, Western Cleaner Clingfish, Gobiesocidae, pink, red, orange,


text:
White House: Sequestration in Massachusetts to cost 10,000 jobs, affect schools, defense, police
PITTSFIELD -- Fewer teachers and instructional aides, fewer children receiving vaccines for measles, mumps and rubella, and more than 10,000 jobs in Massachusetts are at risk if Congress can't come to a compromise and prevent massive spending cuts that begin Friday, according to the White House.
With just three days before the $85 billion budget slash, President Barack Obama continued to put pressure on Republican legislators to prevent the across-the-board cuts, a process known as sequestration, and released a state-by-state breakdown on the impacts of the 10-year cuts worth $1.2 trillion.
"By not asking the wealthy to pay a little more, Republicans are forcing our children, seniors, troops, military families and the entire middle class to bear the burden of deficit reduction," the White House statement said. "The president is determined to cut spending and reduce the deficit in a balanced way, but he won't stick the middle-class with the bill."
According to the White House report, Massachusetts would lose approximately $13.9 million in funding for primary and secondary education, putting nearly 190 teacher and aide jobs at risk.
The cuts would also put 7,000 civilian Department of Defense employees in the state on furlough, reduce funding for law enforcement by $300,000 and programs that provide services to victims of domestic violence, and meal assistance for seniors by a combined $675,000.
Rob Doolittle, a spokesman for General Dynamics, said it's unclear how, or if, the cuts will affect the company and its contracts with the Department of Defense.
"Until our customers tell us how, or if, to change those contracts and the work we're doing for them, we can't estimate the impact," he told The Eagle.
He said the Pittsfield location, which builds mission systems for the Littoral Combat Ship, hasn't seen any decline in production because of the longer process it takes to build such a component but other offices that build short-term projects, about six months or so, has seen production slow.
Throughout New England and nationally, the cuts could affect everything from commercial flights to food inspections.
In a statement, U.S. Rep. Richard Neal, D-Springfield, said most people in his district have told him the sequestration would do "significant damage" in the region.
"They believe this is just another manufactured crisis, and would rather see Congress work together in a bipartisan manner to cut taxes and reduce the deficit. I agree," Neal said.
"With four legislative days left before the deadline, I hope a common sense, fair and balanced compromise can be reached that will prevent these devastating spending cuts from taking place. The American people are interested in solutions, not gimmicks."
U.S. Sen. Elizabeth Warren, speaking at a meeting in Boston with New England business leaders on Monday, called the automatic spending cuts a "mindless across-the-board approach" the solving the country's budget woes.
"I cannot believe we have gotten to this point once again, that we seem to have a government ... that only waits until the 59th minute of the 11th hour to say, 'OK, maybe we'll do something that isn't catastrophic.'"
Material from the Associated Press was used in this story.
This story will be updated in future editions of The Eagle.
To reach Josh Stilts:
or (413) 496-6243
On Twitter: @JoshStilts
If you'd like to leave a comment (or a tip or a question) about this story with the editors, please email us. We also welcome letters to the editor for publication; you can do that by filling out our letters form and submitting it to the newsroom.


text: Chambrey came to see Voodoo. She was very impatient to meet and fuck him, but in the mean time, she showcased her magnificent curves. She shook her tremendous ass all over the place. Then, we went inside where she finally meet Voodoo and soon after she was stuffing his cock in her mouth. She stuck her huge ass in the air as Voodoo munched on her ass. She hopped on that cock and rode that dick as her enormous booty was bouncing. She got man juice all over that luscious ass. CLICK HERE FOR FULL MOVIE AND PICS


text:
Federal and state protection measures for the Lower Dolores River were sharply criticized by local officials Thursday during a regional water meeting in Cortez.
But public-land agencies and the Colorado Water Conservation board defended the decisions as part of their job to inventory special waterways and ensure adequate flows on the river.
New management plans by the BLM and Forest Service upgrade the status of two native fish, and list new sections of the river as "preliminarily suitable" for a Wild and Scenic designation.
Roy Smith, a BLM water specialist, said the suitability status for the Lower Dolores from the dam to Bedrock has been in place since a 1976, and the special status was reaffirmed in a recently released public-lands management plan.
"It qualifies because below the dam, the lower Dolores is a free-flowing stream that has outstandingly remarkable values," he said. "A common misconception is that suitability means we can wave a wand and make it Wild and Scenic, but that is not true. That takes congressional action."
The 1976 suitability study noted that the Dolores is compatible with a Wild and Scenic designation, and "McPhee dam will enhance and complement such designation."
Oustandingly Remarkable Values, known as ORVs, are obscure and sometimes controversial assessments that identify river-related natural values. They are an indication that a river could qualify as a Wild and Scenic River in the future. In the meantime, their natural values are protected in management plans.
In their recent management plan, the BLM and Forest Service upped the ante, adding the bluehead and flannelmouth suckers to ORV standard list, which already includes the bonytail chub.
The Colorado Water Conservation board also believes native fish on the river deserve additional help. They propose to issue a new in-stream flow requirement for a 34-mile section of the river from the confluence with the San Miguel River to the Gateway community.
Ted Kowalski, a Water Conservation Board water resource specialist, said the new in-stream flow is proposed to improve habitat conditions for native fish.
"In-stream flows are designed to protect the natural hydrographs on the river, and we feel they are better than top-down river management from the federal side," Kowalski said. "The proposed in-stream flows on that section of the Dolores are timed to accommodate spawning needs for native fish."
Required peak flows reach 900 cfs during spring runoff, and then taper off. Most of the water would be provided by the San Miguel River, an upstream tributary.
"If in-stream flows are not being met, it would be investigated to find out why the water is not there, or if it is being improperly diverted elsewhere," said Linda Bassi, section chief for CWCB. "It could result in a call upriver to satisfy downstream in-stream flow requirements."
The Dolores Water Conservation Board and the Southwestern Water Conservation board objected to the changes, fearing the move could force more water to be released downstream. They have filed appeals and protests to stop them.
Even the preliminary Wild and Scenic status on the Dolores is strongly opposed by McPhee Reservoir operators because if officially designated, Wild and Scenic rivers come with a federally reserved water right, which would also force more water to be released from the dam.
Jeff Kane, an attorney representing SWCD, said adding two native fish as ORVs was unexpected and unfair to a local collaborative process working to identify and protect native fish needs.
"They were not in the draft proposal. The eleventh-hour finding struck the community and put them on edge," he said.
Barry Spear, an attorney representing DWCD, said the additional in-stream flow requirements and suitability designations will impede water development.
"We found that in-stream flows you are proposing are not imposed on any other BLM or forest in the state. Is this a new precedent? We feel like Southwest Colorado is being singled out," Spear said.
"Where would the water come from?" asked Dolores County commissioner Doug Stowe. "We are in a drought."
Accusations that federal agencies and the CWCB hijacked a 10-year-long, grass-roots effort to protect the Dolores were expressed at the meeting, which was attended by 80 local and regional officials.
"From a water manager perspective, the changes feel like a full-court press on McPhee reservoir," said Mike Preston, DWCD manager.
A diverse stakeholder group, the Dolores River Working Group, is proposing to make the Lower Dolores River into a National Conservation Area through future legislation. As part of the deal, suitability status for Wild and Scenic on the Lower Dolores River would be dropped.
"It is still worthwhile to get our proposal out there," said Amber Kelley, Dolores River coordinator for the San Juan Citizen's Alliance. "We should continue to move forward in our collaborative effort despite the concerns about the BLM changes."


text:
|June 11, 2005, 04:41 PM
Junior Member
Join Date: June 11, 2005
Posts: 2
Using wc820 for 410
I've just begun using wc820 powder in place of H-110 in my 410 skeet recipe. I seems to work just like H-110. Anyone have any feedback or recommendations?
|June 11, 2005, 07:29 PM
Senior Member
Join Date: June 18, 2004
Location: Minden , Nebraska
Posts: 1,403
to say that a powder seems to work as good or like another powder is taking a lot of risk especially when it is a commercial grade powder
|June 11, 2005, 11:16 PM
Senior Member
Join Date: October 15, 2004
Posts: 934
Tell you how I establish burning rate. I have a Handi that has been rechambered to .357 Max, but a .357 mag would do. The rifle is good to about 55k psi. I loaded a batch of .357 Mag ammo using AA 9 data, and chronied it. Velocity I got was a close match to book velocity. Tried it again with Max cases and Max data, and got another match. Good enough for me.
Had I gotten significantly lower velocity, I would have tried the same process with H 110 data. I've done much the same with other powders in other rifles. Seems to be safe enough as long as you use a rifle(s) a lot stronger than your expected results, cases that are small enough to be nearly full, and work up slowly. Once worked all the way through .38 Special, .357 Max, .223, .308, to .25-06 to establish that a completely unknown lot was close to IMR 4831.
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text:
A BILL to repeal sections one, two, three, four, five, six and seven, article three, chapter twenty-one-a of the code of West Virginia, one thousand nine hundred thirty-one, as amended; to repeal section five-b, article two, chapter twenty-three of said code; to repeal section seven, article four-a of said chapter; to repeal section fourteen, article five of said chapter; to amend and reenact section thirty-three-d, article three, chapter five-a of said code; to amend and reenact sections four and five, article three, chapter five-b of said code; to amend and reenact section one, article two, chapter five-f of said code; to amend and reenact section seven, article twelve, chapter eleven of said code; to amend and reenact section three, article seventeen of said chapter; to amend and reenact section four, article one-a, chapter twelve of said code; to amend and reenact section six, article six of said chapter; to amend and reenact section ten, article two, chapter fifteen of said code; to amend and reenact section fifteen, article one, chapter sixteen of said code; to amend and reenact section three, article twenty-nine-d of said chapter; to amend and reenact section three, article thirty-six of said chapter; to amend and reenact section twenty-six, article nine-a, chapter eighteen of said code; to amend and reenact section twelve-a, article ten-a of said chapter; to amend and reenact section two, article ten-k of said chapter; to amend and reenact section three, article three-a, chapter twenty-one of said code; to amend and reenact section four, article one, chapter twenty-one-a of said code; to amend and reenact sections six, six-c and thirteen, article two of said chapter; to amend and reenact section eleven, article ten of said chapter; to amend and reenact section eight, article three, chapter twenty-two of said code; to amend and reenact sections one, two, three, four, five, six, seven, eight, nine, ten, eleven, twelve, thirteen, fourteen, fifteen, seventeen and eighteen, article one, chapter twenty-three of said code; to further amend said article by adding thereto eight new sections, designated sections one-a, one-b, one-c, one-d, one-e, one-f, four-a and nineteen; to amend and reenact sections one, one-c, one-d, two, three, four, five, five-a, five-c, five-d, six, nine, ten, eleven, twelve, thirteen, fourteen, fifteen, sixteen and seventeen, article two of said chapter; to amend and reenact section one, article two-a of said chapter; to amend and reenact sections one, two and three, article two-b of said chapter; to amend and reenact sections one, one-a, two, three and five, article three of said chapter; to further amend said article by adding thereto one new section, designated section six; to amend and reenact sections one, one-a, one-b, one-c, one-d, one-e, two, three, three-b, three-c, four, five, six, six-a, six-b, six-d, seven, seven-a, seven-b, eight, eight-a, eight-b, eight-c, nine, nine-b, ten, eleven, twelve, fourteen, fifteen, fifteen-a, fifteen-b, sixteen, sixteen-a, seventeen, eighteen, twenty, twenty-two, twenty-three, twenty- four and twenty-five, article four of said chapter; to further amend said article by adding thereto a new section, designated section one-g; to amend and reenact sections one, three, five, six and eight, article four-a of said chapter; to amend and reenact sections two, five, six, and seven, article four-b of said chapter; to further amend said article by adding thereto a new section, designated section eight-b; to amend and reenact sections two, three, four and five, article four-c of said chapter; to amend and reenact sections one, two, three, four, five, six, seven, eight, nine, ten, eleven, twelve, fifteen, seventeen and eighteen, article five of said chapter; that said article be further amended by adding thereto two new sections, designated sections ten-a and fifteen-a; to amend and reenact section two, article eight, chapter twenty-six of said code; to amend and reenact sections one hundred twenty-five and one hundred thirty-one, article eighteen, chapter forty-eight of said code; to amend chapter fifty-one by adding thereto a new article, designated article one-b; and to amend and reenact sections twenty-four-e, twenty-four-f and twenty-four-g, article three, chapter sixty-one of said code, all relating to workers' compensation generally.
§5B-3-4. Commission review of procedural rules, interpretive rules and existing legislative rules.
§11-12-7. Display of registration certificate; injunction; public information, reciprocal exchange of information.
§12-1A-4. Applications for loan priority; loan package; counseling.
§12-6-6. Annual audits; reports and information to constitutional and legislative officers, council of finance and administration, consolidated public retirement board, workers' compensation fund and coal-workers' pneumoconiosis fund; statements and reports open for inspection.
§15-2-10. Uniforms; authorized equipment, weapons and supplies; local headquarters; quarters for members; life insurance; medical and hospital fees for injuries and illnesses of members incurred in line of duty.
§16-1-15. Investigations and hearings; power to administer oaths, subpoena witnesses, etc.; use of information and material acquired.
§16-29D-3. Agencies to cooperate and to provide plan; contents of plan; reports to Legislature; late payments by state agencies and interest thereon.
§18-9A-26. Allowance for workers' compensation for unpaid student work-based learning.
§18-10A-12a. Workers' compensation for clients participating in unpaid work-based training programs.
§21-3A-3. Division of occupational safety and health; coordination of activities with workers' compensation commission.
§21A-1-4. Bureau of employment programs created; division; "bureau" defined.
§21A-10-11. Reporting requirements and required information; use of information; libel and slander actions prohibited.
§22-3-8. Prohibition of surface mining without a permit; permit requirements; successor in interest; duration of permits; proof of insurance; termination of permits; permit fees.
§23-1-1a. Workers' compensation board of managers; appointment; composition; qualifications; terms; chairperson; meetings and quorum; compensation and travel expenses; powers and duties.
§23-1-1b. Executive director; qualifications; oath; seal; removal; powers and duties.
§23-1-1d. Rules of former division of workers' compensation.
§23-1-1f. Continuation.
§23-1-2.Oversight of the workers' compensation commission.
§23-1-3. Payment of salaries and expenses generally; manner; limitation.
§23-1-4. Office hours; records; confidentiality; exceptions.
§23-1-5. Office of executive director; hearings.
§23-1-6. Employment of associate director and other assistants; compensation and travel expenses.
§23-1-7. Associate director to act during executive director's absence or inability to act and in case of vacancy; bond of associate director.
§23-1-8. Authority of executive director and employees as to oaths and evidence.
§23-1-10. Fee of officer serving subpoena; fees and mileage of witnesses.
§23-1-13. Rules of procedure and evidence; persons authorized to appear in proceedings; withholding of psychiatric and psychological reports and providing summaries thereof.
§23-1-17. Annual report by commission and occupational pneumoconiosis board.
§23-1-18. Commission employees not subject to subpoena for workers' compensation hearings.
§23-2-1. Employers subject to chapter; elections not to provide certain coverages; notices; filing of business registration certificates.
§23-2-1c. Extraterritorial coverage; approval and change of agreements.
§23-2-1d. Primary contractor liability; definitions; applications and exceptions; certificates of good standing; reimbursement and indemnification; termination of contracts; effective date; collections efforts.
§23-2-2. Commission to be furnished information by employers, state tax commissioner and division of unemployment compensation; secrecy of information; examination of employers, etc.; violation a misdemeanor.
§23-2-4. Classification of industries; rate of premiums; authority to adopt various systems; accounts.
§23-2-5a. Collection of premiums from defaulting employers; interest and penalties; civil remedies; creation and enforcement of lien against employer and purchaser; duty of secretary of state to register liens; distraint powers; insolvency proceedings; secretary of state to withhold certificates of dissolution; injunctive relief; bond; attorney fees and costs.
§23-2-5c. Statute of limitations; effective date for new payments; previous payments due not affected.
§23-2-9. Election of employer or employers' group to be self-insured and to provide own system of compensation; exceptions; catastrophe coverage; self administration; rules; penalties; regulation of self-insurers.
§23-2-12. Effect of repeal or invalidity of chapter on action for damages.
§23-2-13. Interest on past-due payments; reinstatement agreements.
§23-2-14. Sale or transfer of business; attachment of lien for premium, etc., payments due; criminal penalties for failure to pay; creation and avoidance or elimination of lien; enforcement of lien; successor liability.
§23-2-15. Liabilities of successor employer; waiver of payment by commission; assignment of predecessor employer's premium rate to successor.
§23-2-17. Employer right to hearing; content of petition; appeal.
§23-2B-2. Mandatory programs; safety committees; requirements; rules; exceptions.
§23-2B-3. Premium rate credits; qualified loss management program; loss management firms; penalties; rules.
§23-3-1. Compensation fund; catastrophe and catastrophe payment defined; compensation by employers.
§23-3-1a. Transfer of silicosis fund to workers' compensation fund; claims under former article six.
§23-3-5. Authorization to require the electronic invoices and transfers.
§23-4-1c. Payment of temporary total disability benefits directly to claimant; payment of medical benefits; payments of benefits during protest; right of commission to collect payments improperly made.
§23-4-1e. Temporary total disability benefits not to be paid for periods of correctional center or jail confinement; denial of workers' compensation benefits for injuries or disease incurred while confined.
§23-4-1f. Weighing of evidence.
§23-4-2. Disbursement where injury is self-inflicted or intentionally caused by employer; legislative declarations and findings; "deliberate intention" defined.
§23-4-3. Schedule of maximum disbursements for medical, surgical, dental and hospital treatment; legislative approval; guidelines; preferred provider agreements; charges in excess of scheduled amounts not to be made; required disclosure of financial interest in sale or rental of medically related mechanical appliances or devices; promulgation of rules to enforce requirement; consequences of failure to disclose; contract by employer with hospital, physician, etc., prohibited; criminal penalties for violation; payments to certain providers prohibited; medical cost and care programs; payments; interlocutory orders.
§23-4-4. Funeral expenses; wrongfully seeking payment; criminal penalties.
§23-4-6a. Benefits and mode of payment to employees and dependents for occupational pneumoconiosis; further adjustment of claim for occupational pneumoconiosis.
§23-4-7. Release of medical information to employer; legislative findings; effect of application for benefits; duty of employer.
§23-4-7a. Monitoring of injury claims; legislative findings; review of medical evidence; recommendation of authorized treating physician; independent medical evaluations; temporary total disability benefits and the termination thereof; mandatory action; additional authority; suspension of benefits.
§23-4-8a. Occupational pneumoconiosis board; composition; term of office; duties; quorum; remuneration.
§23-4-8b. Occupational pneumoconiosis board; procedure; autopsy.
§23-4-8c. Occupational pneumoconiosis board; reports and distribution thereof; presumption; findings required of board; objection to findings; procedure thereon; limitations on refilings; consolidation of claims.
§23-4-9b. Preexisting impairments not considered in fixing amount of compensation.
§23-4-15b. Determination of nonmedical questions by commission; claims for occupational pneumoconiosis; hearing.
§23-4-16. Commission's jurisdiction over case continuous; modification of finding or order; time limitation on awards; reimbursement of claimant for expenses; reopening cases involving permanent total disability; promulgation of rules.
§23-4-18. Mode of paying benefits generally; exemptions of compensation from legal process.
§23-4-23. Permanent total disability benefits; reduction of disability benefits; reduction of benefits; application of section; severability.
§23-4-24. Permanent total disability awards; retirement age; limitations on eligibility and the introduction of evidence; effects of other types of awards; procedures; requests for awards; jurisdiction.
§23-4-25. Permanent total disability benefits; reduction of disability benefits for wages earned by claimant.
§23-4A-6. Powers of commission over disabled workers' relief fund.
§23-4A-8. Disabled workers' relief fund; how funded.
§23-5-1. Notice by commission or self-insured of decision; procedures on claims; objections and hearing.
§23-5-2. Application by employee for further adjustment of claim; objection to modification; hearing.
§23-5-4. Application by employer for modification of award; objection to modification; hearing.
§23-5-8. Designation of office of administrative law judges; powers of chief administrative law judge.
§23-5-9. Hearings on objections to commission or self-insured employer decisions; mediation; remand.
Appeal from administrative law judge decision to appeal board.
§23-5-12. Appeal to board; procedure; remand and supplemental hearing.
§23-5-17. Termination of office of judges.
§26-8-2. Patients; expenses; disposition of receipts.
§51-1B-1. Intermediate court of appeals; jurisdiction; initial appointment; salary.
§51-1B-7. Rejection, remand or allowance of appeal.
§51-1B-10. Clerk; deputy; other assistants and employees; compensation; expenses.
Omission to subscribe to the workers' compensation fund; failure to file a premium tax report or pay premium taxes; false testimony or statements; failure to file reports; penalties; asset forfeiture; venue.
§61-3-24g. Workers' compensation health care offenses; fraud; theft or embezzlement; false statements; penalties; notice; prohibition against providing future services; penalties; asset forfeiture; venue.


text:
In a high-profile same-sex marriage case in Moscow that has sparked outrage and protests from people on both sides of the issue, on Wednesday a court held up a Russian lesbian couple's appeal of their being denied the right to marry.
Irina Shipitko and her partner Irina Fedotova-Fet, who have been together for five years, made international headlines in May as they were denied a marriage license on the grounds that the Russian Family Code permits marriage only between a man and a woman. On Wednesday a judge postponed a hearing on their case, saying they failed to appear; the couple, arriving after the hearing ended, said they were delayed by traffic, and they met with the media outside the courtroom.
The couple have brought the movement for marriage equality to light of in their country.
Shipitko told the Associated Press that the authorities "are using any excuse" to deny them any form of recognition.
"There is enough homophobia in this country," she said. "We are no different from any other couple."
The couple plan to fly to Toronto -- where same-sex marriage is legal -- to wed, which puts them in position to take advantage of a loophole in their laws that does not prevent the recognition of same-sex marriages performed abroad.
Homosexuality was legalized in Russia in 1993, and the ban on blood donations by gay men was lifted in April 2008. But the country has no antidiscrimination laws covering LGBT people, and many politicians, including Moscow mayor Yury Luzhkov, oppose marriage equality. Luzhkov once referred to gay people as "satanic," and he has banned any gay parades in the Russian capital.
Toronto-based human rights lawyer El-Farouk Khaki, who specializes on LGBT rights and has worked on Russian cases in the past, says the situation in Russia and Eastern Europe is interesting for a number of reasons.
"The strategy may have changed, but the hate has not," Khaki said from Toronto. "Now there are gay bars in cities like Moscow but you can't leave at night because you face the risk of being attacked by skinheads and gangs while the cops do nothing."
"The 'morality' standards only apply to [LGBT people] and not heterosexuals."