text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 18, 2006
|Filing date
|Mar 10, 2003
|Priority date
|Mar 10, 2003
|Fee status
|Also published as
|Publication number
|Larry L. Byers, Paul B. Ricci, Joseph G. Kriscunas, Joseba M. Desubijana, Gary R. Robeck, Michael R. Spaur, David M. Purdham
|Original Assignee
|Marvell International Ltd.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (106), Non-Patent Citations (12), Referenced by (16), Classifications (12), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to the following U.S. patent applications assigned to the same assignee, filed on even date herewith and incorporated herein by reference in their entirety:
"METHOD AND SYSTEM FOR SUPPORTING MULTIPLE EXTERNAL SERIAL PORT DEVICES USING A SERIAL PORT CONTROLLER IN AN EMBEDDED DISK CONTROLLER", U.S. Ser. No. 10/385,039, with MICHAEL R. SPAUR AND IHN KIM as inventors;
"METHOD AND SYSTEM FOR AUTOMATIC TIME BASE ADJUSTMENT FOR DISK DRIVE SERVO CONTROLLERS", U.S. Ser. No. 10/384,992, WITH MICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors;
"METHOD AND SYSTEM FOR USING AN EXTERNAL BUS CONTROLLER IN EMBEDDED DISK CONTROLLERS" Ser. No. 10/385,046, with GARY R. ROBECK, LARRY L. BYERS, JOSEBA M. DESUBIJANA, And FREDARICO E. DUTTON as inventors.
"METHOD AND SYSTEM FOR USING AN INTERRUPT CONTROLLER IN EMBEDDED DISK CONTROLLERS", Ser. No. 10/384,991, with DAVID M. PURDHAM, LARRY L. BYERS and ANDREW ARTZ as inventors.
"METHOD AND SYSTEM FOR MONITORING EMBEDDED DISK CONTROLLER COMPONENTS", Ser. No. 10,385,042, with LARRY L. BYERS, JOSEBA M. DESUBIJANA, GARY R. ROBECK, and WILLIAM W. DENNIN as inventors.
"METHOD AND SYSTEM FOR COLLECTING SERVO FIELD DATA FROM PROGRAMMABLE DEVICES IN EMBEDDED DISK CONTROLLERS", Ser. No. 10,385,405, with MICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors.
1. Field of the Invention
The present invention relates generally to disk controllers, and more particularly to an embedded disk controller that includes a hard disk controller, a microprocessor, a digital signal processor, and a servo controller.
2. Background
Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output ("I/O") devices, and disk drives. In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
The main memory is typically smaller than disk drives and may be volatile. Programming data is often stored on the disk drive and read into main memory as needed. The disk drives are coupled to the host system via a disk controller that handles complex details of interfacing the disk drives to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces.
Typically, a disk drive includes one or more magnetic disks. Each disk typically has a number of concentric rings or tracks on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding for a read or write operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head.
The disk drive is connected to the disk controller that performs numerous functions, for example, converting digital data to analog head signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. To perform the various functions for transferring data, the disk controller includes numerous components.
Typically, the data buffering function is used to transfer data between the host and the disk. Data buffering is needed because the speed at which the disk drive can supply data or accept data from the host is different than the speed at which the host can correspondingly read or supply data. Conventional systems include a buffer memory that is coupled to the disk controller. The buffer memory temporarily stores data that is being read from or written to the disk drive.
Conventionally, when data is read from the disk drive, a host system sends a read command to the disk controller, which stores the read command into the buffer memory. Data is read from the disk drive and stored in the buffer memory. An ECC module determines the errors that occur in the data and appropriately corrects those errors in the buffer memory. Once it is determined that there are no errors, data is transferred from the buffer memory to the host system.
Conventional disk controllers do not have an embedded processor or specific modules that can efficiently perform the complex functions expected from disk controllers.
Conventional disk controllers cannot access plural external memory having different timing characteristics. In addition, conventional controllers do not easily permit use of different bus data width to which external memory is coupled. In addition, conventional disk controllers do not have a built in module that can track bus activity and hence provide valuable information for de-bugging. In conventional disk controllers, the disk controller must be coupled to an external bus analyzer to debug and/or monitor bus activity. This process is cumbersome and requires additional pins on the disk controller. In addition, conventional monitoring techniques cannot easily isolate components within the disk controller that need to be monitored. Furthermore, conventional disk controllers do not have a dedicated module that controls, prioritizes and generates interrupts.
Therefore, what is desired is an embedded disk controller system that can efficiently function in the fast paced, media storage environment.
The present invention solves the foregoing drawbacks by providing an embedded controller with more than one processor. In one aspect of the present invention, a system for an embedded disk controller is provided. The system includes, a first main (system control) processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; and an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface.
The system also includes an interrupt controller module that can generate a fast interrupt and prioritize interrupt requests to the first main processor.
Also provided is a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
In another aspect of the present invention, the system may be an application specific integrated circuit ("ASIC"). In one aspect of the present invention, because the system has dual embedded processors with dedicated history module, interrupt controller module, servo controller and external bus controller, it can perform various functions independently and in parallel. This also improves communication between a host and external device.
In another aspect, dual processors also provide a real time overlap for processing host commands. For example, one processor may move the actuator while the other processor translates the LBA into physical information and queue host requests. The dual processors also improve overall performance for the host. It also allows data recovery when ECC cannot correct data failures. Using unique data recovery algorithms and error recovery information data may be recovered where ECC module fails to dynamically correct the data.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.
The foregoing features and other features of the present invention will now be described. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:
To facilitate an understanding of the preferred embodiment, the general architecture and operation of a disk controller will be described initially. The specific architecture and operation of the preferred embodiment will then be described.
The disk drive system of
As shown in
As is standard in the industry, data is stored on disk 115 in sectors. Each sector is byte structured and includes various fields, referred to as the sector format. A typical sector format includes a logical block address ("LBA") of about four bytes followed by a data field of about 512 bytes. The LBA contains position information, for example, cylinder, head and sector numbers. A field for a CRC checksum of 4 bytes typically follows the data field. A subsequent field for a number of ECC bytes, for example 40–80 bytes, is located at the end of the sector.
Controller 101 can be an integrated circuit (IC) (or application specific integrated circuit "ASIC") that comprises of various functional modules, which provide for the writing and reading of data stored on disk 115. Microprocessor 100 is coupled to controller 101 via interface 118 to facilitate transfer of data, address, timing and control information. Buffer memory 111 is coupled to controller 101 via ports to facilitate transfer of data, timing and address information.
Data flow controller 116 is connected to microprocessor bus 107 and to buffer controller 108. An ECC module 109 and disk formatter 112 are both connected to microprocessor bus 107. Disk formatter 112 is also coupled to data and control port 113 and to data bus 107.
SCSI controller 105 includes programmable registers and state machine sequencers that interface with SCSI port 102 on one side and to a fast, buffered direct memory access (DMA) channel on the other side.
Sequencer 106 supports customized SCSI sequences, for example, by means of a 256-location instruction memory that allows users to customize command automation features. Sequencer 106 is organized in accordance with the Harvard architecture, which has separate instruction and data memories. Sequencer 106 includes, for example, a 32-byte register file, a multi-level deep stack, an integer algorithmic logic unit (ALU) and other special purpose modules. Sequencer 106 support's firmware and hardware interrupts schemes. The firmware interrupt allows microprocessor 100 to initiate an operation within Sequencer 106 without stopping sequencer operation. Hardware interrupt comes directly from SCSI controller 105.
Disk formatter 112 is a disk interface controller and performs control operations when microprocessor 100 loads all required control information and parameter values into a writable control store (WCS) RAM (not shown) and issues a command. Disk formatter 112 executes the command with no microprocessor 100 intervention.
Buffer controller 108 can be a multi-channel, high speed DMA controller. Buffer controller 108 connects buffer memory 111 to disk formatter 112 and to an ECC channel of ECC module 109, a SCSI channel of SCSI controller 105 and micro-controller bus 107. Buffer controller 108 regulates data movement into and out of buffer memory 111.
To read data from disk 115, a host system sends a read command to disk controller 101, which stores the read commands in buffer memory 111. Microprocessor 100 then read the command out of buffer memory 111 and initializes the various functional blocks of disk controller 101. Data is read from disk 115 and is passed through disk formatter 112 simultaneously to buffer controller 108 and to ECC module 109. Thereafter, ECC module 109 provides the ECC mask for errors, which occurred during the read operation, while data is still in buffer controller 108. The error is corrected and corrected data is sent to buffer memory 111, and then passed to the host system.
System 200 includes a microprocessor ("MP") 240 (which is also the overall system processor) that performs various functions described below. MP 240 may be a Pentium� Class processor designed and developed by Intel Corporation� or an ARM processor (for example, ARM966E-S�) or any other processor. MP 240 is operationally coupled to various system 200 components via buses 236 and 208. Bus 236 may be an Advanced High performance (AHB) bus as specified by ARM Inc. Bus 208 may an Advanced Peripheral Bus ("APB") as specified by ARM Inc. The specifications for AHB and APB are incorporated herein by reference in their entirety. It is noteworthy that the present invention is not limited to any particular bus or bus standard.
Arbiter 245 arbitrates access to AHB bus 236, while APB bridge 235 is used to communicate between buses 236 and 208.
System 200 is also provided with a random access memory (RAM) or static RAM (SRAM) 238 that stores programs and instructions, which allows MP 240 to execute computer instructions. MP 240 may execute code instructions (also referred to as "firmware") out of RAM 238.
System 200 is also provided with read only memory (ROM) 237 that stores invariant instructions, including basic input/output instructions.
MP 240 includes a TAP controller 242 that performs various de-bugging functions.
MP 240 is also coupled to an External Bus Interface Bridge (or Controller) ("EBC" also referred to as "EBI" or "EBI controller") 228 via an external bus interface ("EBI/F") 227. EBC 228 allows system 200 via MP 240 and EBI/F 227 to read and write data using an external bus, for example, a storage device external to system 200, including FLASH memory, read only memory and static RAM. EBC 228 may be used to control external memory (not shown), as discussed in detail below. EBI/F 227 may be programmed to interface with plural external devices.
System 200 includes an interrupt controller ("IC") 207 that can generate regular interrupts (IRQ 207A) or a fast interrupt (FIQ 207B) to MP 240. In one aspect of the present invention, IC 207 is an embedded system that can generate interrupts and arbitrates between plural interrupts. IC 207 is described below in detail.
System 200 includes a serial interface ("UART") 201 that receives information via channel 203 and transmits information via channel 204.
System 200 includes registers 209 that include configuration, system control, clock and power management information.
System 200 also includes an address break point and history module (also referred to as "history module" or "history stack") 234 that monitors activity on busses 236 and 208 and builds a history stack. Such history stack may be used for debugging, and monitoring plural components of system 200. History module 234 is discussed below in detail.
System 200 also includes a timer module 206 that controlled by MP 240 and includes various timers, for example, the "Watchdog timer".
System 200 is provided with a general purpose input/output ("GPIO") module 202 that allows GPIO access to external modules (not shown).
System 200 is also provided with a digital signal processor ("DSP") 229 that controls and monitors various servo functions through DSP interface module ("DSPIM") 210 and servo controller interface 212 operationally coupled to a servo controller 216.
DSPIM 109 interfaces DSP 229 with MP 240 and updates a tightly coupled memory module (TCM) 212 (also referred to as "memory module" 212) with servo related information. MP 240 can access TCM 212 via DSPIM 210.
Servo controller interface ("SCI") 211 includes an APB interface 214 that allows SCI 211 to interface with APB bus 208 and allows SC 216 to interface with MP 240 and DSP 229. SCI 211 also includes DSPAHB interface 215 that allows access to DSPAHB bus 233. SCI 211 is provided with a digital to analog/analog to digital converter 213 that converts data from analog to digital domain and vice-versa. Analog data 223 enters module 213 and leaves as data 222 to a servo drive 221.
SC 212 has a read channel device (RDC) interface 217, a spindle motor control ("SVC") interface 219, a head integrated circuit (HDIC) interface 218 and servo data ("SVD") interface 219A.
System 200 also includes a hard disk controller 101A that is similar to the HDC 101 and includes a code cache 101B.
In one aspect of the present invention, because system 200 includes, dual embedded processors (MP 240 and DSP 229) with dedicated history module 234, IC module 207, servo controller and EBC 228, it can perform various functions independently. This not only saves the resources of MP 240 but also improves communication between a host and an external device.
In another aspect, embedded processors (MP 240 and DSP 229) provide independent real time control, with one processor as the system control processor (MP 240) and the second processor (DSP 229) as a slave to the first for real time control of the disk servo mechanism. DSP 229 as a slave also provides real time control for positioning a disk actuator. This includes analyzing error positioning data and outputting error correction data.
Dual processors also provide a real time overlap for processing host commands. For example, one processor may move the actuator while the other processor translates the LBA into physical information and queue host requests.
The dual processors also improve overall performance for the host. It also allows data recovery when ECC cannot correct data failures. Using unique data recovery algorithms and error recovery information data may be recovered if the ECC module 109 fails to dynamically correct the data.
The following describes the various components of system 200 in detail, according to various aspects of the present invention.
EBC 228 is a slave on AHB bus 236 and adapts the high performance of AHB bus 236 to a slower external bus (not shown) that can support external memory (including without limitation, flash memory, ROM, and static memory (not shown)).
In one aspect of the present invention, MP 240 via EBC 228 may access multiple devices with different timing characteristics or data width. At least a Segment Descriptor register is provided, which specifies the timing characteristic of each external device. Also provided is at least a device range register, which specifies the size of the external device address space. Depending on the external bus data width, EBC 228 may convert AHB bus 236 transactions into multiple external bus transactions.
Each device segment descriptor register 601 may be formatted the same way with the same fields. Segment descriptor registers 601 allow firmware to program timing characteristics for an external memory device on an external memory bus. For example, as shown in the table of
DW 601E specifies the data width of an external bus device (not shown). A state machine may be used by EBC 228 to use the various register 601 values, as shown by the state machine diagram in
System 1400 includes a set of registers, for example, HaddrReg 1408, HwriteReg 1411 and HsizeReg 1412 register and their usage is described below.
State S0: This is an idle state, until a valid operation on the bus is received.
State S1: This is a first stage for decoding an address in HaddreReg 1408 to determine which external device if any, is the target for a read or write cycle. After determining the target external device, various counter values, as shown in
State S2: This is a second state during which state machine 1402 remains in this stage until the SW1 601D and TRW 601B values expire to avoid data contention on the external bus.
State S3: The state machine stays in this state for at least one clock cycle with all external bus controls as being inactive. This state is only used for sequential write operations.
State S4: During this state the appropriate chip select signal (XCS 317) is asserted while the write enable (XWEn 319) or output enable (XOEn 318) are deasserted, until SW2 601C expires.
State S5: The state machine logic 1402 stays in this state until a current read or write operation is completed. During this state the chip select, write enable or out enable signals are asserted. For write commands, EBC 228 writes data and for read operation, EBC 228 reads data.
State S6: This state is entered only during write operations and is used to provide write data hold time. During this state, EBC 228 continues to drive the write data on the external bus while it keeps the write enable signal de-asserted.
State S7: During this state, registers within EBC 228 are read or written.
The relationship between the various states is shown in
Interrupt Controller ("IC") 207:
IC 207 synchronizes and prioritizes interrupt signals as a slave on the APB bus 208. IC 207 handles two types of interrupts, Fast Interrupt Request ("FIQ") and Interrupt Request ("IRQ"). The interrupts are sent to MP 240. The FIQ 207B is used for critical interrupts as defined by a user or firmware. IRQs 207A are provided for routine interrupts. IC 207 provides the interrupts to MP 240 that interrogates IC 207 to retrieve a particular interrupt with an interrupt vector, as described below. MP 240 may clear the interrupt after retrieving the interrupt information.
In one aspect of the present invention, IC module 207, provides FIQ 207B for critical interrupts, scans interrupts for priority, prevents interrupt source lockout (interlock) in the interrupt service and allows a user to change various interrupt options using firmware.
IC module 207 uses plural registers for controlling interrupts. The base address of IC module 207 is specified in APB Bridge 235. When signal PSELIC 1604 from APB bridge 235 is sent to IC module 207, the base address of IC module 207 is detected by APB bridge 235 and IC module 207 decodes signals PADDR 1605 and PWRITE 1606 to select the appropriate register address. IC module 207 examines signal PADDR 1605 for exceptions. An access to an undefined or reserved register address results in IC module 207 asserting the PADREXCPT signal 1610 to APB Bridge 235. It is noteworthy that this does not change the state of IC module 207. Also, access to an undefined "read" address results in PADREXCPT signal 1610 to APB Bridge 235.
Interrupt Request Pending ("IRP")-Read Only field 1904C is set when a corresponding interrupt source is asserted. When IRS 1904B is set, IRP 1904C is cleared. In addition, when the source interrupt is masked, IRP 1904C may be cleared. Polarity ("PLR") 1904D is used to specify the polarity of an interrupt source.
Register 1904 also includes a trigger mode TM value 1904E that specifies the mode of an interrupt source signal. Field 1904E specifies whether the interrupt signal is edge triggered or level sensitive. Use of TM 1904E in register 1904 is discussed below in detail.
Fields 1901F and 1901L contain interrupt vector addresses assigned by MP 240 to a corresponding interrupt source. This field specifies a vector address to firmware and specifies the priority of the interrupt with the interrupt source. The vector field in 1905B is updated when an entry in the interrupt control register array (described below) that corresponds to an active interrupt is seen as having a higher priority while the register array is being scanned.
FIQ Interrupts:
Input signal 1608 from a FIQ source is sent to module 2005. Module 2005 selects either the FIQ source signal, or a TestSource signal depending on the state of ICIntTestControl 2017. If the FIQ source signal is selected, then it is synchronized by raw interrupt synchronization module 2006. The synchronized signal is sent for FIQ registration to FIQ registration module 2007. Module 2007 includes registers 1904, and 1902.
Signal 1607 is sent to mask module 2004 (that includes register 1903) and to FIQ IC module 2008. Mask module 2004 sends the mask (1903A) to FIQ IC module 2008, which then sends a signal to interrupt generation module 2009. Interrupt generation module 2009 also receives input from IRQ Scanner 2011 and based upon the priority of the request, an interrupt is generated, for example FIQn 1611, SysInt 1614 and IRQn 1613.
When FIQIRP 1904C is set, then a fast interrupt is asserted. The interrupt request signal remains asserted until MP 240 reads register 1902. When register 1902 is read, FIQn signal 1611 is de-asserted by setting FIQIRS 1904B and clearing FIQIRP 1904C.
In one aspect, another interrupt request cannot be made until FIQIRS 1904B is cleared as follows:
(a) If FIQ interrupt source as defined by TM 1904E is level sensitive then the firmware ensures that the FIQ interrupt source is de-asserted and then an end of interrupt ("EOI") is sent to IC 207 to clear the FIQIRS 1904B state; or
(b) If the FIQ interrupt source as defined by TM 1904E is edge triggered, the firmware need only read register 1902, FIQIRP 1904C is cleared and FIQIRS 1904B is set. In edge triggered mode, FIQIRS clears when the interrupt source de-asserts. The next interrupt does not occur until the interrupt source signal de-asserts, and asserts again.
IRQ Interrupts:
Incoming IRQESOURCE signals 1609 is received by module 2002. Module 2002 selects either the IRQESOURCE signal, or TestSource signals depending on the state of ICTestControl 2015. If the IRQESOURCE signals are selected, then they are synchronized by raw interrupt synchronization module 2003. The synchronized signals are sent for IRQ registration to IRQ registration module 2013. IRQ interrupt registration module 2013 sets the field 1906B in register 1906. Signal 1607 is sent to mask module 2004 (that includes register 1903) and to IRQ Interrupt Registration Module 2013. Mask module 2004 sends the mask (1903A) to IRQ Interrupt Registration module 2013, which then sends signals to the IRQ Priority Evaluation And Scanner module 2011 (also referred herein as "IRQ Scanner 2011"). It is noteworthy that firmware may mask an interrupt before it is sent to MP 240. This de-registers the interrupt by clearing field 1906B.
For each possible interrupt input, information regarding that interrupt is stored in IRQ register control array 1901. Register control array 1901 includes vector values (1901F and 1901L), TM values (1901E and 1901K) and PLR values (1901D and 1901J) for each interrupt source, i.e. even and odd source. MP 240 may write the foregoing values in register control array 1901. Vector values 1901F and 1901L provide the offset for firmware to access the interrupt handler (Not shown) and establish the priority of the interrupt within plural interrupt sources, for example, 16 IRQ sources. It is noteworthy that the invention is not limited to 16 IRQ sources. In one aspect, the highest vector value is given the highest priority. When one of the registers in register control array 1901 is read then, the mask, IRS, IRP, Vector, TM and PLR values are also read at the same time. Output 2012 from register control array 1901 is sent to IRQ scanner 2011 that scans the vector values, as described below. IRQ scanner 2011 provides an input 2011A to interrupt generator 2009 that generates IRQn 1613.
When MP 240 retrieves the IRQ interrupt from IC module 207 it reads register 1905 which sets the IRQIRS bit (1901B or 1901I) associated with the interrupt source in register 1905, which prevents the same interrupt source from generating another interrupt until the IRQIRS bit is cleared.
In one aspect, another interrupt from the same source cannot be made until IRQIRS (1901B or 1901I) is cleared as follows:
In step S2800, an IRQ signal 1609 is received from an interrupt source.
In step S2801, IRQ signal 1609 is selected by logic 2002.
In step S2802, valid IRQ signal 1609A is synchronized by synchronization module 2003.
In step S2803, synchronized IRQ signal 1609B is registered by IRQ interrupt registration module 2013.
In step S2804, registers in register control array 1901 are read.
In step S2805, vector values are scanned (discussed below with respect to
In step S2806, based on the vector values, output interrupt signal 1613 is sent to MP 240.
In step S2900, IRQ scanner 2011 receives register values 2012 from register control array 1901 and IRQESOURCE 2013A from IRQ interrupt registration module 2013. IRQ scanner 2011 receives vector values from register control array 1901. IRQ scanner 2011 examines each interrupt during every interrupt cycle
In step S2901, the process determines if an interrupt is being sent (sent as used here includes "pending" interrupts). If an interrupt is being sent (or pending), then in step S2902, IRQ scanner 2011 compares the vector values of the interrupt being sent (or pending) with the scanned vector values of every other active interrupt input in a given interrupt cycle.
In step S2903, IRQ scanner 2011 replaces the previous vector values if the most current vector values have higher priority.
If an interrupt is not being sent (or pending) in step S2901, then in step S2904, IRQ scanner 2011 loads the current vector values from an active interrupt input from S2901 and the process moves to step S2902.
In one aspect of the present invention, a fast interrupt scheme is provided so that for critical interrupts, MP 240 does not have to wait.
In another aspect of the present invention, interrupt priority is established efficiently by a scanning process.
In yet another aspect of the present invention, firmware can change priority and mask interrupts from any source, providing flexibility to a user and also optimizes MP 240 usage.
In another aspect of the present invention, use of TM values prevents interlocking of interrupt service by MP 240.
History Module 234:
History module 234 is a peripheral on APB Bus 208 that records transaction information over either AHB Bus 236 and/or APB Bus 208. The recorded information may be used for debugging and analyzing firmware and hardware problems. History module 234 is set up and initiated through APB Bridge 235 and information from History module 234 is extracted through APB Bridge 235. History module 234 includes a buffer(s) (not shown) for reading and writing recorded information.
Field 3300J defines break point conditions for History Module 234. Break point conditions are those, which stop recording/monitoring by History Module 234. Field 3300I enables break points, while break point testing stops after a break point is detected, if field 3300E is set.
Trigger mode field 3300G specifies the number of entries made in a History Module 234 buffer after a break point condition is detected.
HSP 3501 may be zero at the beginning of a recording session. Firmware has the flexibility to change HSP 3501 values. In one aspect, firmware may set this value to zero. HSP 3501 allows the firmware to recover a recording regardless of the reason why a recording session stopped. HSP 3501 is incremented each time an entry is accessed from the history stack buffer.
To start history module 234, field 4300A of register 4300 is set, that allows recording when signals HREADY 307 or PENABLE 1607 are asserted. In one aspect of the present invention, history module 234 may record data simultaneously for buses 236 and 208. This allows history module 234 to write in buffers 4313, 4314 and 4315. Although
History module 234 continues to make entries until a break point (or event) is reached as defined by fields 3300I and 3330J in register 3300 or field 4300A is cleared by firmware, as discussed below in detail.
Valid Recorded Entry: Before recording, buffers 4313, 4314 and 4315 are cleared by firmware issuing a "clear History stack Buffer Access 4201 command. All valid entries in buffer 4314 are cleared. When recording, field 4201 is toggled each time an entry is made in buffers 4313–4315.
Break Point and Break Point Interrupt: Firmware can set field 3300I to enable a break point defined by break point condition field 3300J. Event control module 4336 generates field 4300A value that is sent to flip-flop module 4323. Firmware can set field 4300A value that enables flip-flop module 4323. History module 234 tests for break point condition 3300J in every clock cycle as defined by firmware.
When history module 234 detects the defined break point condition then it stops recording bus transactions based on TM value 3300G and an interrupt may be generated, as discussed below. After a break point is detected, history module 234 stops recording and based on field 3300E setting either continues to test for the break condition or stops testing for the break point condition.
An interrupt is generated based on the detection of the break point condition and if field 3300F is set, after the interrupt source is enabled in IC module 207.
Break points may be set for address and/or data or address range based on fields 3601 and 3602. Firmware may also send a "Clear Enable Record status" field 4300A to trigger a firmware break point, if a firmware break point condition is set in 3300J.
Clock Slam: When a break point condition is detected, and if field 3300D is enabled (Enable clock Slam), history module 234 asserts signal ClkSlam 4343 to clock control via flip-flop module 4340. Break point condition 3300J′, which indicates that a break point condition has occurred, is sent to event control module 4336 with trigger mode value 3300G. This stops all the clocks in system 200. This signal remains asserted until system 200 is reset. This allows system 200 component information to be scanned out for analysis and diagnosis using standard debugging tools.
Filter Control: History module 234 can selectively filter out system 200 components based on filter control command 4324. Filter control command 4324 is based on select mask field 3300A in register 3300. If field 3300A is set then transactions related to, a specific peripheral(s) or slave (depending on the bus) is not recorded.
Trigger Mode:
Trigger mode field 3300G specifies the number of entries that are made in buffers 4313–4315 after a break point condition has been detected. In one aspect, field 3300G may be set so that history module 207 stops recording within a single clock cycle, or may continue to record a pre-defined amount of data before stopping.
Starting and Stopping Recording:
History module 234 starts and stops recording based on register 4300 fields. Field 4300A when set to "EnableRcrdReg", allows history module 234 to record. Setting "Clear Enable Record and Status" bit in field 4300A stops history module 234 from recording and break point testing, unless specified otherwise by firmware.
Bus (208 and 236) transactions are recorded when EnableRcrdReg is set. Mux 4324 samples signals HREADY 307 and PENABLE 1603. The signals indicate that a valid transaction is on the bus that may be recorded unless masked by field 3300A.
History Stack Pointer:
History stack pointer 3500, as shown in
Extracting Recorded History Information:
As stated above, when recording stops, history stack pointer 3501 points to the "oldest recorded entry". MP 240 bus master (not shown) reads the history address buffer 4313 and history module 234 places the recorded entry into register 4300 (
Turning in detail to
In step S4501, the process determines if field 3300E is set to enable any break point testing. Field 3300J in register 3300 may be used to specify break point conditions.
In step S4502, transactions are recorded. Bus (208 and 236) transactions are recorded when EnableRcrdReg field 4300 is set. Signals HREADY 307 and PENABLE 1603 are sampled by Mux 4324. The signals indicate that a valid transaction is on the bus that may be recorded unless masked by field 3300A. When an entry is made in buffers 4313–4315, pointer 3501 is updated. When history module 234 stops making entries in buffers 4313–4315, the value of 3501 points to the last entry plus one.
In step S4503, based on whether break point condition testing is enabled, history module 234 tests for break point conditions. Based on the setting of EnBPStp 3300E, history module 234 may continue or stop break point condition testing after a particular break point is encountered.
In step S4504, the process determines the value of TM field 3300G. This sets the amount of data that is to be recorded after a break point condition is detected. It is noteworthy that steps S4502–4504 may occur simultaneously.
In step S4505, recording is stopped and field 4300A is cleared.
In step S4506, recorded information is extracted. MP 240 bus master (not shown) reads the history address buffer 4313 and history module 234 places the recorded entry into register 4327 (
In one aspect of the present invention, history module 234 provides visibility to transactions on the internal AHB Bus 236 or APB Bus 208.
In one aspect of the present invention, history module 234 selects specific slave or peripheral transactions for recording based on a slave or peripheral mask. This allows selective monitoring of system 200 components.
In yet another aspect of the present invention, the process described above provides break point conditions for stopping History module 234 recording. However, external break point signal may be continually provided after recording stops. In addition, break point conditions may be provided for an Address/Data break point and an Address Range break point.
In another aspect of the present invention, an external analyzer is not required to record bus transactions. This saves pins and the effort required connecting system 200 to an external device so that its components can be monitored.
Firmware Synchronization:
DSPIM 210 provides an interface for communication between MP 240 and DSP 229 as a bridge between APB bus 208 and DSPAHB bus 233. DSPIM 210 provides an IN/OUT register file for passing command and status parameters between MP 240 and DSP 229.
MP 240 writes in register 4600 and interrupt is sent to DSP 229. MP 240 sets field 4900C in status register 4900, which generates an interrupt to DSP 229.
In step S5000, MP 240 send information to DSP 229.
In step S5001, MP240 writes the information (or address of the information) in register 4600.
In step S5002, MP 240 sets field 4900C and generates an interrupt for DSP 229.
In step S5003, DSP 229 services the interrupt by reading register 4600 and clears field 4900C.
In step S5004, register 4600 is again available for MP 240 to write into register 4600.
DSPIM 210 is operationally coupled to memory module 212 via interface 230. MP240 and DSP 229 for storing firmware control instructions and any other information may use memory module 212. Interface 230 allows APB bus 208 to access memory module 212 while DSPIM 210 executes firmware instructions.
Memory module 212 is shared using registers 4600, 4700 and semaphore register 5100 shown in
Memory module 212 uses an indirect access register 5200 that facilitates communication between DSP 229 and MP 240 without using any counters. Memory module 212 uses at least a FIFO buffer from where data may be read and/or written. Memory module 212 uses register 5300 (
An indirect read transaction may be initiated by setting up field 5200A and 5200C. Each time register 5300 is accessed, the address in field 5200F is updated. If field 5200C is set then it indicates that the read access is a sequence of continual read accesses that keeps memory module 212 FIFO (not shown) full.
An indirect write access may be initiated by setting field 5200A and 5200B. After the indirect access, register 5300 is updated with data that is written into memory module 212. Each time data is written into register 5300, DSPIM 210 writes data into memory module 212.
One advantage of providing the mail-box" concept is that no write conflict occurs between MP 240 and DSP 229.
In one aspect, MP 240 and/or DSP 229 do not have to gain ownership and then relinquish ownership (clear) of any registers to communicate with each other. This saves performance time and improves overall efficiency, because the registers are dedicated.
In another aspect of the present invention, indirect access is available to access memory module 212.
In another aspect of the present invention, the IN/Out mailbox environment may be used to efficiently run test cases. MP 240 using Assembler or any other language may run test cases. A sub-set of test instructions may be executed by DSP 229. The mailboxes have a buffer (not shown) that keeps a real-time picture of a test case. When the test is complete, mail-boxes are unloaded and a report may be generated that can be used for bug fixing and analysis.
Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.
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|International Classification
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|Mar 10, 2003
Owner name: QLOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BYERS, LARRY L.;RICCI, PAUL B.;KRISCUNAS, JOESEPH G.;ANDOTHERS;REEL/FRAME:013861/0735;SIGNING DATES FROM 20030306 TO 20030307
|Nov 14, 2005
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QLOGIC CORPORATION.;REEL/FRAME:017017/0145
Effective date: 20051104
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|Certificate of correction
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|Jan 20, 2014
|Fee payment
Year of fee payment: 8


text:
Airflow's Impact on Thermographic Readings of Horse Legs
- May 29, 2013
- Topics:
Thermal images of the front legs of a horse. Left without a draft, right-cooled drafts two and a half minutes with the speed from 1.3 to 2.6 meters per second right leg significantly.
Photo: University of Veterinary Medicine Vienna/Dr. Simone Westermann
Considering thermography to evaluate a horse's legs? Better move that patient inside and shut the doors. Austrian researchers recently learned that wind and air drafts can affect themographic readings of horses' front legs—very quickly, in fact—potentially leading to false positive or negative results.
"I was surprised at how fast the temperature decreased after the onset of airflow," said Simone Westermann, DrMedVet, a researcher in the Units of Large Animal Surgery and Orthopaedics at the University of Veterinary Medicine in Vienna. Westermann and her fellow University of Veterinary Medicine researchers studied the effects of air, angles, distances, and natural temperature differences on multiple thermographic readings of 16 healthy adult horses.
Slight drafts of air—what Westermann called "barely noticeable wind velocities"—caused a reduction in the temperature of horses' forelimbs, compared to the temperature recorded without drafts, she said. A gentle breeze of only two meters per second could make leg temperatures drop as much as 1.5°C (2.7°F) in as few as one to three minutes.
Temperature can also naturally vary slightly from one forelimb to the other in a healthy horse, according to Westermann's research, so those evaluating thermographic readings should take into consideration the possibility of natural differences between legs.
Angles and distances of the position of the thermography reader compared to the limb can also cause some variations in reading, but fortunately these parameters do not have to be precisely consistent every time, Westermann said. Slight changes in angle (up to 20°) and distance (up to 50 centimeters, or 19 inches) caused no significant differences in thermographic results from one reading to the next.
"We can tolerate certain variations in camera angle and distance," Westermann said. "But airflow can be a problem that you should keep in mind. It's necessary to perform thermography in a place without airflow to avoid false negative or positive results."
The average barn can probably qualify as a draft-free room, she said—"but certainly it depends on the kind of barn." She said she would not recommend performing thermography outdoors. Even so, this extra effort should not dissuade practitioners from benefiting from this unique diagnostic tool.
"Many veterinarians argue that thermography is too complicated to perform," she said. "But it's not more complicated than many other kinds of diagnostic techniques such as (radiography), scintigraphy, and ultrasound. Certainly, it must be used in combination with a clinical examination, and it can only give a hint to the reason for lameness. But with thermography, it's possible to make physiology visible."
Additional research in the field is needed, Westermann added.
About the Author
Christa Lesté-Lasserre, MA
Christa Lesté-Lasserre is a freelance writer based in France. A native of Dallas, Texas, Lesté-Lasserre grew up riding Quarter Horses, Appaloosas, and Shetland Ponies. She holds a master's degree in English, specializing in creative writing, from the University of Mississippi in Oxford and earned a bachelor's in journalism and creative writing with a minor in sciences from Baylor University in Waco, Texas. She currently keeps her two Trakehners at home near Paris. Follow Lesté-Lasserre on Twitter @christalestelas.
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subset: commoncrawl


text:
LAPD chief criticizes officers' conduct during deadly struggle
Chief Beck concluded that a veteran female officer violated department policies by her actions during the arrest
By Joel Rubin
Los Angeles Times
LOS ANGELES — Los Angeles Police Chief Charlie Beck was sharply critical of how several officers acted during an arrest last year in which a woman died during a prolonged struggle with police, department records released this week show.
In a report to the Police Commission, the civilian board that oversees the LAPD, Beck concluded that a veteran female officer violated department policies when she repeatedly kicked and shoved 35-year-old Alesia Thomas in her genitals and midsection.
The same officer, the chief and commission found, showed "apparent indifference" toward Thomas during the messy effort to restrain her and put her into the back of a police cruiser.
Beck raised concerns as well over the actions of three additional officers and a supervisor during the July 22 confrontation in South L.A. Two of the officers disregarded Thomas' request for medical help, while the third cop may have lied to investigators about the incident, Beck wrote in his report. A sergeant who responded to the scene may have failed to properly supervise the officers, according to the report.
Following the chief's findings, the department opened formal internal investigations, which could result in discipline of the officers and sergeant. The district attorney's office, meanwhile, is reviewing the case for possible criminal charges, said Cmdr. Andy Smith, a spokesman for Beck.
The officers and sergeant have been reassigned to other stations, and all but one have been taken out of the field during the investigations, Smith said. The officers' names have not been released because state law keeps issues related to police misconduct confidential.
In a unanimous vote during a closed-door meeting this week, the five-member commission agreed with the chief's finding that the female officer's forceful use of her feet was "ineffective and inappropriate," according to a commission report.
An autopsy by the Los Angeles County coroner determined that cocaine intoxication probably was "a major factor" in Thomas' death. It was impossible to determine what role, if any, the struggle with the officers played. Because of that uncertainty, the official cause of death was listed as "undetermined."
Last summer, The Times reported on the alleged kicks by the female officer and Thomas' decision to abandon her children outside the LAPD's Southeast area station, which led to the fatal confrontation with police. The chief's report provided details to how events unfolded.
About 1:30 a.m., Thomas, who suffered from bipolar disorder, schizophrenia and drug addiction, according to the autopsy report, left her 3-year-old and 12-year-old children outside the station, according to Beck's report. The children walked into the station lobby carrying a basket of clothing and told the officer at the front desk that their grandmother was supposed to pick them up. One of the children handed the officer a piece of paper with a telephone number and the name "Sandra" written on it, the report said.
In earlier accounts, police officials and relatives of Thomas said she was attempting to surrender the children to police custody because she thought she could no longer care for them.
Officers were dispatched to Thomas' home and were instructed to arrest Thomas on suspicion of child endangerment, according to Beck's account.
Thomas resisted as officers tried to place her in handcuffs, and the officers tackled her to the floor to restrain her. Once she was in handcuffs, Thomas asked for an ambulance, but when one of the officers asked her why, she appeared incoherent and asked only for a glass of water, Beck said.
With the sergeant now looking on, the officers carried Thomas down a flight of stairs to the street. The female officer and her partner arrived to assist and the four officers began trying to push and pull Thomas into the back of a patrol car as she continued to struggle.
When Thomas was partially in the back of the patrol car, the female officer on three separate instances delivered a series of kicks or shoves to Thomas in her groin and thighs. She repeatedly swore at Thomas and threatened to kick her if she did not "knock it off," the commission report said. The force from the officer's feet caused Thomas at one point to fall back and scream. When the female officer ordered Thomas to sit up, she stated repeatedly, "I can't," and the officer applied her foot again, according to the report.
Although a video camera in the car captured much of the incident, Beck and the commission said it could not be determined whether the officer maliciously kicked Thomas or was trying to move her further into the car, as the officer said.
Minutes after being in the car with the doors closed, the video shows Thomas losing consciousness. The officers quickly noticed she was unresponsive and called an ambulance. Thomas was dead by the time paramedics brought her to a hospital.
The LAPD has refused requests from The Times for a copy of the video, citing the ongoing investigations.
Copyright 2013 the Los Angeles Times


text:
Sitegrab is a URL grabber that parses IRC logs for data and then inserts it into a database that can be searched through a web interface using a combination of announcer name, date, partial url, and type of url. Also supported is an administration mode whereby urls can be edited and deleted through the web interface.
Wing IDE is a software development environment for Python. It provides powerful editing, code intelligence, refactoring, testing, debugging, and search capabilities that reduce development and debugging time, cut down on coding errors, and make it easier to understand and navigate Python code.
ADODB is a set of advanced PHP database abstraction classes. It supports MySQL, PostgreSQL, Interbase/Firebird, Informix, Sybase SQL Anywhere, Oracle, MS SQL 7 and 2000, SAP DB, Sybase, DB2, FrontBase, Foxpro, Access, Netezza, LDAP, ODBTP, ADO, and generic ODBC. A metatype system is built in, making it possible to figure out that types such as CHAR, TEXT, and STRING are equivalent in different databases. It also features portable database creation, database-backed session support (with encryption), SQL performance monitoring, and database health checks.
XaoS is a fast, portable, real-time, and interactive fractal zoomer. It displays the Mandelbrot set (among other escape time fractals) and allows you zoom smoothly into the fractal. Various coloring modes are provided for both the points inside and outside the selected set. In addition, switching between Julia and Mandelbrot fractal types and on-the-fly plane switching is provided.
Greenstone is a complete digital library creation, management, and distribution package for Unix, Windows, and Mac OS X. Users create collections by gathering a set of input documents, specifying a configuration file, and running the build script. It provides full-text and fielded searching, browsable indexes, customised formatting, metadata extraction (acronyms, languages, etc), a Z39.50 client, and many other features. It supports many input formats, the interface is configurable and multi-lingual, and collections can be distributed on the Web or on CD-ROM.
Mckoi SQL Database is a full featured SQL-92 relational database management system written in Java. The software can operate as either a dedicated multi-client, multi-threaded database server, or can be used as an embedded database inside a Java application. The engine is designed to be easy to use and maintain and versatile for sophisticated database development tasks. The software provides a JDBC 2.0 driver.
You are captain of the cargo ship Chromium B.S.U., responsible for delivering supplies to our troops on the front line. Your ship has a small fleet of robotic fighters which you control from the relative safety of the Chromium vessel. Chromium B.S.U. is a fast paced, arcade-style, top-scrolling shooter. It uses OpenGL for graphics, OpenAL/SDL_mixer for sound effects, GLC/FTGL for text rendering, and glpng/SDL_image for texture loading.
Gyach is a GTK+-based Yahoo! Chat client which can use your existing Yahoo! logins for chatting in Yahoo! Chat. It supports colors, emotes/aliases, PMs, set status, remote user status display, ignore lists (local, non-Yahoo! based), a regex list of triggers to cause users to be automatically ignored, command-line recall via arrow keys, and tab completion of usernames.
A window manager for X.
Tiny, portable general Unix utilities.


text:
While the SPEW Review Award has always been in place to reward those whose reviews are deemed the most excellent for any given month, there has never been a mechanism to honour those whose mastery of the art of fabulous reviewing is the most consistent throughout the year. That is, of course, until now. As your SPEW Queen, I am all about giving credit where it is due, and that is what SPEW Reviewer of the Year is all about.
The Criteria:
~Complete participation in six or more review periods in the calendar year 2011.
~Has not been subject to disciplinary action save for single-review late penalties.
The Numbers:
~Combined scores of all reviews are added together and divided by the number of reviews.
~Reviews scored under the previous scoring system were multiplied by 3 each so that they were on the same scale.
~The highest average score per review was the winner.
~If you'd like a breakdown of your scores, please PM me.
And, without further ado, with the highest average review score of 16.1 is...
Hannah / h_vic!!!!!
Gorgeous banner provided by Minna/minnabird.
Hannah's wonderful reviews are an inspiration to all of us, and it is no mistake that, when I was in need of a modly power for the RAC, I chose the expert. I've been lucky enough to know her since her return to MNFF, and it elicits no end of awe that one person could so consistently review with such a golden standard.
With her award and shiny banner, Hannah will carry with her 25 points to the Badger's Set, as well as the honour of being the very first SPEW Reviewer of the Year. Please, everyone, take a moment to congratulate Hannah, but not only that, please visit her author page, peruse some of her reviews, and show appreciation for her excellent work.
And from me, Hannah, thank you for being an excellent member of the group, a great author, and a wonderful friend. ♥♥♥♥♥♥♥♥♥♥♥♥♥♥♥


text:
XTS stands for Extraterrestrial and it pretty much explains the style. Our updated design has better fit, better looks and better coverage. XTS was one of our best selling models, already before these upgrades. Elvex XTS safety glasses comply with ANSI Z87.1-2010 (Z87+) requirements and have CE approval to EN-166, for safety eyewear. All lenses provide 99.9% against UV-A, UV-B and UV-C, in wavelength range 180-380 nm. Dual lens construction allows excellent peripheral vision. Anti-fog lenses available in clear and gray lens models. Anti slip rubber temple tips for added comfort, Universal non-slip rubber nose bridge for the most comfortable fit. Special purpose lenses available, such as Polarized and Infrared.
SPECIFICATIONS:Mfg Item Num: RSG24B Category: EYE & HEARING PROTECTION Type :Safety GlassesColor :BlueNRR :Quantity :1 PairStyle :Men And WomensAFT Circuit :Battery :Compression Circuit :Ultraviolet Rating :Temple Sleeves :Anti Slip Rubber


text:
The Denon DNHC4500 Pro Media Player and Controller is a USB MIDI/Audio interface designed exclusively for computer performance club and mobile DJs worldwide.
Ever since the needle hit vinyl, DJ's have been setting the standard for what's hot. Denon comes from that same philosophy and passion, leading the way and creating the path for DJ evolution. The DNHC4500 is the next step.
The feature-packed, professional, PC/MAC compatible Denon DNHC4500 controller combines unmatched hardware performance with internal high quality audio processing offering low latency ASIO/OSX Core Audio support. The DNHC4500 does more than talk MIDI, it offers the exclusive flexibility to control Denon's optional BU4500 dual CD/MP3 player for simultaneous 4-player configuration. The controller is bundled and complimented with an LE trial version of PCDJ's revolutionary new software, Reflex, that offers an array of amazing forward thinking features.Denon DNHC4500 Pro Media Player and Controller


text: Whenever I go to KFC I feel disappointed if I get anything other than the Original fried chicken. However, I'm a fried chicken lover (I'm distinguishing fried chicken as in complete pieces, 8 per chicken, bones 'n' all, from chicken patty sandwiches, etc.); those who don't like this style of food probably wouldn't like KFC's main items. Can't say much about the sandwiches; I've liked them all right the few times I've tried them, but I like the plain chicken so much it just seems like a waste to get a sand


text:
Filed under: Trailers and Clips, Movie News, Video, Cinematical
A whole slew of trailers are popping up on the web this week. We got the full 'Captain America: The First Avenger' trailer last night, and now three more.
First up: Ace Ventura found his penguins!
His name is now Mr. Popper, as part of the classic children's book, and the animals have whittled down to a bunch of pesky penguins, but the goofiness remains. In this cinematic version of 'Mr. Popper's Penguins,' the man doesn't breed a whole bunch of them, but rather inherits some and watches them take over his life. This includes teaching them dance moves to the applicably chilly stylings of one Vanilla Ice.
Check it out for yourself after the jump, along with peeks into 'Last Night' and 'The Big Bang.'
Continue Reading


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In an interview with Bob McCown two days ago Colangelo mentioned that while everyone respects Jay in the organization, some of the players in their exit interviews voiced displeasure... Or at least that was what was implied when Colangelo referred to exit interviews with the players in this interview. Colangelo never comes out and directly said the negatives, he always pussy foots around it enough so that you can put two and two together.
Colangelo went on to say that the players respected Jay and listened to Jay but the guy could not get them to execute and he never held them accountable.
Source: Fan 590
I think some of the players didn't respect him. One prime example of a lack of respect by some of the players and then a lack of accountability on Jay's behalf was Julian Wright. When the kid refused to sub in he should have collected dust for the rest of the season. That guy is lucky to be in the league and he goes and pulls something like that? And what does Jay do? Hardly anything.


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Allen Iverson wants to return to professional basketball, according to comments he made during the Philadelphia 76ers' Game 6 win against the Boston Celtics on Wednesday.
When asked about retirement by ESPN's Lisa Salters, Iverson said he wasn't using that word, but acknowledged playing at the NBA level may not be an option.
"I want to play basketball so bad," Iverson said. "The way it is right now, I've accepted the fact that that might not happen, but I still want to play basketball, and if I can get an opportunity where it's going to make me happy at the end of my career, I'll take that opportunity.
"But I just love to play and I want to have another opportunity to play on the professional level."
Iverson delivered the game ball prior to Game 6 in Philadelphia, where he last played in the NBA during the 2009-10 season. Iverson's career took a significant downward turn during the 2008-09 season, when he was shipped from the Denver Nuggets to the Detroit Pistons. He languished in his role as a bench player and was not in the NBA when the 2010-11 season began.
Since his time in the NBA, Iverson has played for Besiktas in Turkey and also with U.S. All-Stars in China.


text:
New Page
Use the form on the right to contact us.
You can edit the text in this area, and change where the contact form on the right submits to, by entering edit mode using the modes on the bottom right.
1637 N. Ashland Ave
Chicago, IL 60622
Street-Level Youth Media is a non-profit, media arts literacy organization serving Chicago's youth. We teach audio engineering, mixing, video production, digital photography, online journalism, and more. If you are between the ages of 12 through 24, all of our programs and services are free.
If you live in Chicago and are between 12 - 24 years old, come take part in one or all of our media arts programs, book a private studio session, use our computer lab or join one of our clubs. We also host an open-mic on the first Friday of each month.


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I'm not against sports, but athletic fees are costing state students millions of dollars.
This is not fair, right or justified. They have a hard time just getting an education with the funds they have.
Athletics are not as important as getting an education, especially when they have to pay to subsidize the many programs they have.
Making college students pay so much per hour of credit just to help fund athletics is wrong.
Would anyone with common sense build a nice home next to Walmart on East Main Street?
Then why build a Walmart store in a neighborhood of nice homes on South Vancouver Avenue?
The answer "No, I don't think I would build next to Walmart" is reason enough to vote against the Walmart rezoning ordinance.
This is a different type of letter on the Walmart West Main site.
Even though I live close to the projected site, I am a fence sitter.
I have only one concern. About nine years ago, Mr. Bob Carpenter and I planted the little October Glory maple tree that stands on the west side of the property.
We babied and fretted and carried water across the street to keep the little thing alive. How is has flourished.
This tree is a memorial for the two brothers, Bob and Tom Carpenter and my brother-in-law, Sam Huddleston, who was Tom's roommate at Stella Manor Nursing and Rehab. All three of these men have passed on now and I miss them terribly.
So please, Walmart, if you get to put in your store, try to incorporate our little tree into you landscaping design. This is all I ask. Thank you.


text:
I am trying to find code to use for an image segementation program. I have found some code but am having trouble trying to get it running. The source code is too big to post, but it is all available to download at Image Segmentation. The problem i am having is an error that is coming up from the 'segment-image.h' file:
[Error] ... \segment-image.h:33: implicit declaration of function 'int random(...)'
Any help on getting this running would be much appreciated.


text:
The Bunny is a Legendary; Tediore manufactured rocket launcher. The Bunny is only dropped by the "chubby" enemies. The gimic of the bunny is when its reloading (since it's a Tediore) it bounces or "hops" along the ground until hitting a target, or otherwise.
EditDrop Guide
Chubby enemies can spawn anywhere on Pandora (but seem to drop more frequently in Caustic Caverns and Tundra Express). Can also get from super badass varkidscourtesy of (http://www.youtube.com/user/yoteslaya)
Top Wiki Contributors
Need assistance with editing this wiki? Check out these resources:
Open References & Sources (1)
What Links Here
Rare Loot | Legendary Rocket Launchers | Rare Rocket Launchers


text:
Pothole-palooza begins Monday, March 25
Wednesday, March 20, 2013
The Street Division will kick off its annual spring pothole-palooza on Monday, March 25. The pothole campaign is marked by an intensive push to repair reported potholes that have been caused by winter's freeze-thaw cycles. Potholes are prioritized by location, so potholes on main arterials receive a higher priority.
However, to repair potholes, the City needs help finding them! We are asking drivers who spot potholes to call and report them to the Pothole Hotline – 385-ROAD (7623). Citizens with smart phones can download the City's mobile request app to report potholes from www.springsgov.com/app. Potholes can also be reported through www.SpringsGov.com by clicking on "Customer Service" on the homepage.
When reporting a pothole, callers should provide detailed information such as street name, direction of traffic flow (north bound, south bound, etc.), the intersection, closest address (if known), side of the street, and location in the street such as left or right edge line or middle, inside or outside lane. Due to the huge influx of calls expected, citizens should not expect a personal reply to their request.
The City of Colorado Springs Streets Division maintains more than 1,500 center line miles of streets. A center line mile is the length of one mile of road regardless of the number of lanes. In the last 3 years, the City has filled an average of 25,500 potholes each year. Streets crews filled 28,821 potholes in 2012. While the dry winter reduced the amount of potholes created by freeze-thaw cycles, the aging of the street system has kept the number of potholes comparable to previous years.
The City does not repair potholes on County or State roads, such as South Academy south of Milton Proby (County) and Powers (State) and US 24 (State).
INTERVIEW/MEDIA REQUESTS: Contact Streets Operations Managers Amaro Montemayor at (719) 385-6730 or Bard Lower at (719) 385-6827 to arrange for interviews and/or take video of pothole crews in action.


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Federal Premium Gold Medal Paper Shotshell ammunition is Federal's premier target ammunition. This ammunition is trusted by countless competitive shooters looking for the most consistent loads available. This ammunition is loaded with the absolute best components including extra hard shot and the hot 209A primer. The resulting ammunition delivers some of the most consistent and uniform patterns of any commercially available shotshell ammunition; which in turn delivers more wins on the target shooting circuit. Available in several different loads, clays shooters will be sure to find the winning combination.
Technical Information
Gauge/Bore: 12
Shell Length: 2-3/4"
Shot Weight: 1-1/8 oz
Shot Size: #7-1/2
Shot Type: Lead
Ballistics Information:
Muzzle Velocity: 1180 fps
Technical Information
Ballistics Information:


text:
Eight screen cinema slimmed to six for opening after flooding issue temporarily rules out basement pair
PUBLISHED: 21:47 17 May 2014 | UPDATED: 21:47 17 May 2014
A multiplex cinema in Wisbech will open with six instead of eight screens because two are underground and have flooded.
The Light Cinema, part of the Tesco Extra complex in Cromwell Road, opens next Friday in time for half term but due to a flood problem not have all eight screens in use until the summer.
A cinema spokesman said: "There are two screens underground - they're flooded but only because the builders haven't got in yet.
"It's right next to the river and the water table is high there."
The spokesman said contractors had concentrated on getting the second floor done.
"They have tank water systems that are going to be in place to make sure it doesn't flood but it does require a lot more building work," he said. "The two screens will be open by summer."
The eight-screen cinema will create 47 jobs, with the majority of people hired from the Wisbech area.
The project has been 11 years in the planning and is being undertaken by cinema company The Light, which also has a cinema in New Brighton in the Wirral.
General manager Phil Dove said: "We are excited about being in Wisbech. It is a great opportunity for us because this town has a lot of potential. We hope to give a boost to its night time economy.
"There's a generation of people who are not going to the cinema and a generation of older people who have stopped going.
"Our aim is to encourage people back to have an enjoyable night out."
The cinema will hold events such as a kids club, holiday club, fancy dress screenings and autistic-friendly screenings.
Some films will be shown with Polish subtitles.


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I am Brenda Savage, and my husband Tony Down and I own Cozy Comfort RV Park in Dolores. Recently, we have had to call for help from the Montezuma County Sherriff's Department. As a business owner in Dolores, I have been appalled at the amazing lack of respect that the Sheriff's Department officers have had for me, when I have called for help to resolve issues, and even more amazed at the politeness with which they deal with the criminals. Something is terribly wrong. If you want actual law enforcement in Montezuma County, and especially in Dolores, be very careful how you cast your vote. And please, do cast your vote! If you are an upstanding citizen in Dolores, and if you might ever need help, make a change. What is happening in our town with law enforcement is completely unacceptable.
Brenda Savage


text:
Looking to keep the heat? In Sweet Love, best-selling editor Violet Blue creates a world of lusty and in-love couples who live out their fantasies with delicious results. These powerful scenarios are recipes for romance that real couples can use as inspiration for memorable explorations of their own.
This delectable collection will have you wishing for role-playing, exhibitionism, spankings, surprise threesomes, and much much more. Sweet Love's expertly crafted, explicit stories will really take you there.
©2010 Cleis Press (P)2011 Cleis Press
There are no listener reviews for this title yet.
"Love Violet Blue's books, but..."
If you've ever listened to Open Source Sex, Violet Blue's very much missed audio blog, you know this... The woman can read an erotic story better than almost anyone. Mark Smith? Not so much. It's just strange to hear stories written by a woman and from a woman's perspective read (badly) by a man. It just doesn't work.
Violet... I'd pay double for your books if you'd read them yourself!
Report Inappropriate Content
If you find this review inappropriate and think it should be removed from our site, let us know. This report will be reviewed by Audible and we will take appropriate action.


text: On Sun, 11 May 2008, Greg Lindahl wrote: > Last I saw someone doing this, IPMI sharing an ethernet port with the > host led to all kinds of weird ARP problems. Whereas a dedicated port > is much easier to configure. My favorite vendors all offer a > dedicated port... I have five racks of Dell gear that I need to figure out how that is going to work. This is my first experience at setting up and using the Dell Baseboard Management Controller. Power should be installed next week, so this is going to be a very busy week trying to get ready. Any suggestions, words of wisdom or web pointers would be appreciated. -- Matt It's not what I know that counts. It's what I can remember in time to use. _______________________________________________ Beowulf mailing list, Beowulf at beowulf.org To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf !DSPAM:4827b4ff81761923983023!


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WASHINGTON, DC, April 21, 2009—The current economic situation has countless Americans wondering where to turn for unbiased, ethical guidance and advice. To help consumers deal with the current turmoil, Certified Financial Planner Board of Standards, Inc. has developed a new a Consumer Webcast Series featuring CFP® professionals addressing key financial planning topics.
Each webcast discusses a specific area of financial planning and includes practical information and tips that consumers can apply to their personal finances in today's tough times. The topics include: Managing Debt: From Credit Cards to Foreclosures; Planning for Your Financial Goals; Young Professionals: Launching Your Financial Plan; and What to Know When Choosing a Financial Planner.
The 50-minute long videos are available in English and Spanish and include synchronized PowerPoint slide shows that make it easy for consumers to follow the presentations.
"We hope these webcasts will help consumers navigate the current situation and get an insight into the benefits of professional advice from CFP® practitioners who can help you make decisions based on your personal life goals and financial situation," said Marilyn Capelli Dimitroff, CFP®, Chair of CFP Board's Board of Directors.
The webcasts were recorded during educational workshops conducted at CFP Board's Financial Planning Clinics in 2008 in Washington, DC, and Miami. At those workshops, hundreds of consumers came away with valuable information and advice on a wide range of financial planning topics.
CFP Board will continue to update and enhance its Consumer Webcast Series Web site, which is available at www.CFP.net/learn/webcasts.asp. Consumers can also explore the www.CFP.net web site for a variety of articles and information on personal financial planning and for help on finding a CERTIFIED FINANCIAL PLANNER™ professional.
About CFP Board: The mission of Certified Financial Planner Board of Standards, Inc. is to benefit the public by granting the CFP® certification and upholding it as the recognized standard of excellence for personal financial planning. The Board of Directors, in furthering CFP Board's mission, acts on behalf of the public, CFP® certificants and other stakeholders. CFP Board owns the certification marks CFP®, CERTIFIED FINANCIAL PLANNER™ and federally registered CFP (with flame design) in the U.S., which it awards to individuals who successfully complete CFP Board's initial and ongoing certification requirements. CFP Board currently authorizes more than 59,000 individuals to use these marks in the United States. For more about CFP Board, visit www.CFP.net.
# # #
CFP® - The Recognized Standard of Excellence in Personal Financial Planning
CONTACT: Chris Wloszczyna, Director of Public Relations
CFP Board
E: email@example.com
© 2012 Certified Financial Planner Board of Standards, Inc. All Rights Reserved.
1425 K Street NW #800, Washington, DC 20005
phone: 800-487-1497 (Toll-Free) / 202-379-2200 | fax: 202-379-2299 | email@example.com
We welcome your feedback and invite you to complete a brief 5-question survey to help us improve your experience on CFP.net.
It's easy to participate and will take less than 2 minutes:
Click the "Yes" button below to continue your visit on CFP.net as intended. When finished, simply retrieve and complete the questionnaire that will appear in a new browser window.
Quick Links
Find a CFP® Professional
Verify Certification
Get Certified
Create an Account | Log In
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Brochures & Publications


text:
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Description: From Dear Stella Designs, this solid cotton broadcloth is 4 oz. per square yard and is perfect for quilting, apparel and home décor accents.
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text:
What does everybody think the starting line up is gonna be Tuesday in Miami? I think to give us a boost over the Heat, we need the following starters...
PG - Chris Duhon
SG - Nate Robinson
SF - Al Harrington
PF - David Lee
C - Darko Milicic
We need Duhon to cover Chalmers (That should be an easy matchup)
Nate Robinson can match Wade in scoring and keep him busy
Al Harrington has an easy advantage over the mentally troubled Michael Beasley
David Lee & Darko Milicic can provide us with the necessary strength we need in the paint against Haslem and O'neal
And if we need a boost off the bench, just call on Douglas's Defense, Gallo's 3 point shooting, & Chandler's toughness. Lets hope on a great playoff push from our boys
What do you guys think should be the lineup in Miami?


text:
Unfair commercial practices
Is it fair?
A European initiative in support of consumers
Consumers in the European Union should not be misled by inaccurate or misleading commercial claims by traders. This guide explains what commercial practices are considered unfair under EU law and how consumers can seek redress if they are cheated.
A consumer's guide to unfair commercial practices which are always prohibited under EU law. The guide provides a brief description and examples of each blacklisted practice.
The burning question for consumers will undoubtedly be: "How can I tell when a particular commercial practice is unfair? This section provides simple guide and many examples.
If you've been cheated, don't despair! There are mechanisms in place to help you resolve a dispute with a trader - even across borders.


text:
Dandelion Print Drapery Panel
- No Longer Available -
Dandelions find a fitting home on our soft, cotton voile drapery, as both share the same light and airy nature, serving as lovely symbols for the return of spring.
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