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|23rd week of 2012 patent applcation highlights part 48
|Patent application number
|SUPPLEMENT FOR CELL CULTIVATION MEDIA - A method of preparing a supplement for cell cultivation media, which comprises concentrating porcine blood by centrifugation and obtaining supernatant, adding agonist for activating platelets into the supernatant to obtain activated supernatant, and sterilizing the activated supernatant is presented. A supplement for cell cultivation media, which is made by the above method, a cell cultivation media comprising the supplement, and a use of the cell cultivation media in culturing or treating cells in tissue engineering or regenerative medicine is also presented.
|PRODUCTION AND EXTRACTION OF PROCYANIDINS FROM PLANT CELL CULTURES - A method of preparing cocoa oligomeric procyanidins from cocoa cell cultures grown in the presence of monosaccharide can increase production of procyanidins as follows: culturing cells sufficient to result in production of cocoa oligomeric procyanidins at a first rate; and introducing a monosaccharide to the cells sufficient for inducing the cells to produce the cocoa oligomeric procyanidins at a second rate that his higher than the first rate. The method can further include extracting the cocoa oligomeric procyanidins from the cells, and such extracting can occur between 1 day to 21 days after introduction of the monosaccharide. Optionally, the monosaccharide can be introduced in an amount about 0.5% to about to about 20% by volume of the culture medium. The monosaccharide can be glucose, sucrose, fructose, or the like. The monosaccharide can be introduced during or after a last phase of an exponential growth state.
|Method Of Forming Dendritic Cells From Embryonic Stem Cells - This invention relates to the culture of dendritic cells from human embryonic stem (ES) cells. Human ES cells are first cultured into hematopoietic cells by co-culture with stromal cells. The cells now differentiated into the hematopoietic lineage are then cultured with GM-CSF to create a culture of myeloid precursor cells. Culture of the myeloid precursor cells with the cytokines GM-CSF and IL-4 causes functional dendritic cells to be generated. The dendritic cells have a unique phenotype, as indicated by their combination of cell surface markers.
|METHOD AND SYSTEM FOR SOMATIC CELL NUCLEAR TRANSFER - Provided is a method for nuclear transfer. An exogenous donor nucleus is introduced into an enucleated oocyte and one or more enucleated sperm cells or one or more enucleate sperm cell fractions are introduced into the oocyte. The one or more sperm cells or one or more sperm cell fractions may be introduced into the oocyte either before, after, or simultaneously, with the donor nucleus. Also provided are cells and embryos produced by the method.
|Compositions For Treating Bacterial Infections - Polynucleotides encoding a mutant human carboxylesterase enzyme and polypeptides encoded by the polynucleotides which are capable of metabolizing a prodrug and inactive metabolites thereof to active drug are provided. Compositions and methods for sensitizing cells to a prodrug agent, inhibiting cell growth, treating drug addiction, and facilitating the metabolism of an organophosphate with this enzyme are also provided. In addition, a screening assay for identification of drugs activated by this enzyme is described.
|METHOD FOR PRODUCING T CELL POPULATION UNDER PRESENCE OF RETINOIC ACID - Disclosed is a method for producing a cell population containing memory-like T cells, said method being characterized by including a step for in vitro culturing of a cell population containing T cells or T cell precursor cells using a retinoic acid and a CD3 ligand. Further disclosed is a method for producing a cell population wherein the proportion of memory-like T cells is increased and wherein a desired gene is introduced with a high efficiency and is highly expressed.
|Method of Genetically Altering and Producing Allergy Free Cats - A transgenic cat with a phenotype characterized by the substantial absence of the major cat allergen, Fel d I. The phenotype is conferred in the transgenic cat by disrupting the coding sequence of the target gene with a specialized construct. The phenotype of the transgenic cat is transmissible to its offspring.
|NANOMATERIAL-CONTAINING SIGNALING COMPOSITIONS FOR ASSAY OF FLOWING LIQUID STREAMS AND GEOLOGICAL FORMATIONS AND METHODS FOR USE THEREOF - Compositions containing a transporter component and a signaling component and a method for using said compositions for analyzing porous media and flowing liquid streams, specifically for measuring pressure, temperature, relative abundance of water, pH, redox potential and electrolyte concentration. Analytes may include petroleum or other hydrophobic media, sulfur-containing compounds. The transporter component includes an amphiphilic nanomatenal and a plurality of solubilizing groups covalently bonded to the transporter component. The signaling component includes a plurality of reporter molecules associated with the transporter component. Said reporter molecules may be releasable from the transporter component upon exposure to at least one analyte. The reporter molecules may be non-covalently associated with the transporter component, or the reporter molecules are covalently bonded to the transporter component. Furthermore, said compositions and methods may be used to actively enhance oil recovery and for remediation of pollutants.
|ELECTROLUMINESCENT DIODE SENSOR - A senor uses a transduction mechanism of attenuating electroluminescence. Luminescence from a light emitting diode is attenuated as a consequence of direct interaction of an analyte and a electroluminescent material, An electroluminescent diode sensor (EDS) is fabricated in a way that allows the electroluminescent material in the diode to be exposed to gaseous, liquid or solid sample(s) which may affect the luminescence intensity of the diode,
|METHOD AND APPARATUS FOR DETERMINATION OF SYSTEM PARAMETERS FOR REDUCING CRUDE UNIT CORROSION - The invention provides a method and apparatus for determining the amount of various materials in a liquid sample. Because the apparatus is particularly resilient it can be used repeatedly with very harsh liquid samples such as boot water from an oil refinery. The apparatus uses at least one volume and/or concentration independent optical analysis method to determine at least one of: the pH, amount of chloride, and/or amount of iron in the sample. The optical property can be colorimetric, fluorescent or both and result from adding dyes, complexing agents, turbidity inducing compounds, and other optically effecting reagents to the sample. Because the measurements are concentration and volume independent they can be done continuously, quickly, and avoid the inconvenient start and stop procedures in prior art measurement regimens. The method further includes using a BDD cell to oxidize materials (such as sulfoxy compounds) that would otherwise interfere with the optical analysis and/or to sparge the sample with gas.
|Methods and Apparatus for Measuring Blood Coagulation - The present invention provides apparatus and methods for performing assays for determining the time required for a sample of blood to coagulate. The apparatus comprises reaction chambers coated with one or more clotting agent. A drop of blood or equivalent is placed at the sample application port, diluted, and contacted with the clotting agents in the reaction chambers. The diluted blood sample can be moved back and forth through the reaction chambers until blood clots. The blood clotting process forms fibrin stands that prevent the flow of the blood sample in the reaction chambers. The clotting time is the total time from the sample entering the reaction chambers to the time at which the waveform in the reaction chambers change, or the motion or flow of the sample ceases, and can be measured by turbidity.
|METHOD AND APPARATUS FOR DETERMINATION OF SYSTEM PARAMETERS FOR REDUCING CRUDE UNIT CORROSION - The invention provides a method and apparatus for determining the amount of various materials in a liquid sample. Because the apparatus is particularly resilient it can be used repeatedly with very harsh liquid samples such as boot water from an oil refinery. The apparatus uses at least one volume and/or concentration independent optical analysis method to determine at least one of: the pH, amount of chloride, and/or amount of iron in the sample. The optical property can be colorimetric, fluorescent or both and result from adding dyes, complexing agents, turbidity inducing compounds, and other optically effecting reagents to the sample. Because the measurements are concentration and volume independent they can be done continuously, quickly, and avoid the inconvenient start and stop procedures in prior art measurement regimens. The method further includes using a BDD cell to oxidize materials (such as sulfoxy compounds) that would otherwise interfere with the optical analysis and/or to sparge the sample with gas.
|MUTANT RAS POLYPEPTIDE CRYSTAL - An object of the present invention is to provide a co-crystal of a Ras polypeptide which adopts a conformation having a pocket on the molecular surface of Ras and GTP or a GTP analog, a production method for the crystal, and a screening method for a Ras function inhibitor based on information about the conformation obtained by X-ray crystallographic analysis using the crystal. The object is achieved by focusing on a mutation which adopts a conformation having a pocket on the molecular surface of Ras, acquiring a mutant Ras polypeptide having introduced therein such mutation, producing a co-crystal of the mutant Ras polypeptide and a GTP analog, and further subjecting the co-crystal to X-ray crystallographic analysis to acquire structural information about the conformation including information about the structure surrounding the pocket.
|BIOSENSOR PROVIDED WITH CODE ELECTRODE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR OBTAINING SENSOR INFORMATION FROM THE SAME - The present invention provides a biosensor having a code electrode, a method for manufacturing the same, and a method for obtaining sensor information on the same, in which a code electrode for providing sensor information such as correction information, the type of biosensor, etc. is provided in each biosensor such that a measuring device can obtain necessary information on each biosensor from the code electrode, thus solving a variety of conventional problems.
|MICROFABRICATION OF HIGH TEMPERATURE MICROREACTORS - Microreactors, methods of fabricating, and using such microreactors comprises a substrate having an outer periphery and composing two monolithic sections, each of said monolithic sections comprising two opposed main surfaces and one or more edges extending between the main opposed surfaces. One of the main surfaces from each of the monolithic sections are joined together at a substantially planar junction. The microreactor further comprises at least one microcapillary flow passage defined by surfaces within said substrate and having first and second ends. One or more inlets connect the outer periphery of said substrate with the first end of said microcapillary flow passage. One or more outlets connect the outer periphery of said substrate with the second end of said microcapillary flow passage, which may narrowingly taper. The substrate can be made from high purity fused silica. A metallic reagent and/or catalyst can be incorporated in the micro capillary passage.
|Novel gold nanoparticle aggregates and their applications - The invention is drawn to a method of using nanoparticle aggregates to form sensors and optical filters. Properly sized (60 and 200 nm) nanoparticle aggregates with cores having a sulfur-oxygen molecular species and a shell with a surface in contact with the core are obtained. Those nanoparticle aggregates have a first resonance profile to wavelengths between 350 nm and 1075 nm. A modified resonance profile for those nanoparticle aggregates is determined. The nanoparticle aggregates are then selectively sized by irradiating them with electromagnetic energy at sufficient intensity and spectral content to modify the first resonance profile towards the modified resonance profile. The resulting nanoparticle aggregates can be used as sensors or optical filters at a selected wavelength.
|VASOACTIVE HORMONE-BASED STRATIFICATION OF PATIENTS SUFFERING FROM DISEASES RELATED TO ENDOTHELIAL FUNCTION/DYSFUNCTION - The present invention relates to a method for the stratification of a subject having an acute or a chronic disease, wherein said disease effects endothelial function/dysfunction, comprising the steps of (i) taking a sample of bodily fluid from said subject; (ii) determining in said sample of bodily fluid the concentration of a vasoactive hormone or fragments thereof or precursors or fragments thereof having a length of at least 12 amino acid residues; (iii) stratifying said subjects into either of the categories: (a) responder to a medication for treatment of said disease, (b) non-responder to a medication for treatment of said disease not showing an unfavourable effect after having received said medication; (c) subjects showing an unfavourable effect after having received said medication. The invention also relates to the use of an antibody or a functional fragment thereof in the method according to the invention.
|HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION - A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
|METHOD OF INSPECTING AND PROCESSING SEMICONDUCTOR WAFERS - A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask
|ALGAINN-BASED LASERS PRODUCED USING ETCHED FACET TECHNOLOGY - A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs etching to form device waveguides and mirrors, preferably using a temperature of over 500° C. and an ion beam in excess of 500 V in CAIBE.
|METHOD OF APPLYING PHOSPHOR TO SEMICONDUCTOR LIGHT-EMITTING DEVICE - A method of applying a phosphor according to a light-emission characteristic of semiconductor light-emitting devices so as to increase a yield rate of manufacture with respect to a white light-emitting device chip, the method including the operations of testing light-emission characteristics of a plurality of light-emitting devices formed on a wafer; disposing a plurality of light-emitting devices having the same light-emission characteristics on a carrier substrate; applying a same phosphor to the plurality of light-emitting devices disposed on the carrier substrate; and separating the plurality of arrayed light-emitting devices. Thus, a white light-emitting device chip manufactured by using the method may emit almost the same white light.
|PHOTOLUMINESCENCE IMAGING SYSTEMS FOR SILICON PHOTOVOLTAIC CELL MANUFACTURING - A method of photoluminence (PL) imaging of a series of silicon wafers, the method including the step of: utilizing incident illumination of a wavelength greater than 808 nm. The present invention further provides a method of analysing silicon semiconductor material utilising various illumination, camera and filter combinations. In some embodiments the PL response is captured by a MOSIR camera. In another embodiment a camera is used to capture the entire PL response and a long pass filter is applied to block a portion of the signal reaching the camera/detector.
|DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate, a barrier pattern, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode. The barrier pattern protrudes from the base substrate. The source and gate electrodes are formed adjacent to opposite sides of the barrier pattern on the base substrate. The semiconductor layer is provided on the barrier pattern to connect the source electrode with the drain electrode, and the insulating layer covers the semiconductor layer, the source electrode, and the drain electrode. The gate electrode is provided on the insulating layer, and is overlapped with the semiconductor layer.
|LIGHT EMITTING DIODE PACKAGE WITH A PHOSPHOR SUBSTRATE - Provided is a light emitting diode (LED) package including a phosphor substrate; an LED chip mounted on the phosphor substrate; a circuit board mounted on the other region of the phosphor substrate excluding the region where the LED chip is mounted; an electrode connection portion for electrically connecting the LED chip and the circuit board; and a sealing member that covers the LED chip, the circuit board, and the phosphor substrate.
|ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE HAVING DOUBLE-LAYERED METAL PATTERNS AND METHOD OF FABRICATING THE SAME - An array substrate of an in-plane switching liquid crystal display device includes, among other features, a gate electrode and a gate line having a first double-layered structure consisting of a first barrier layer and a first low resistance metallic layer; a data line defining a pixel region with the gate line, the data line having a second double-layered structure consisting of a second barrier layer and a second low resistance metallic layer; a plurality of common electrodes disposed in a direction opposite to an adjacent gate line; a thin film transistor (TFT) near a crossing of the gate and data lines, each of the source and drain electrodes of the TFT having the same double-layered structure as the data line; and a plurality of pixel electrodes arranged in an alternating pattern with the common electrodes and disposed in the direction opposite the adjacent gate line.
|METHOD OF MANUFACTURING SEMICONDUCTOR LASER HAVING DIFFRACTION GRATING - A method of manufacturing a semiconductor laser having a diffraction grating includes the steps of forming a first semiconductor layer on a semiconductor substrate; forming periodic projections and recesses which constitute a diffraction grating in the first semiconductor layer; cleaning a surface of the first semiconductor layer with water; drying the surface of the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer. In drying the surface of the first semiconductor layer, after replacing water adhering to the surface of the first semiconductor layer with a water-soluble organic solvent, exposing the surface of the first semiconductor layer provided with the projections and recesses to an atmosphere containing the water-soluble organic solvent. At least one of the first semiconductor layer and the second semiconductor layer is composed of a p-type semiconductor.
|GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - Provided is a group-III nitride semiconductor laser device with a laser cavity of high lasing yield, on a semipolar surface of a support base in which the c-axis of a hexagonal group-III nitride is tilted toward the m-axis. First and second fractured faces to form the laser cavity intersect with an m-n plane. The group-III nitride semiconductor laser device has a laser waveguide extending in a direction of an intersecting line between the m-n plane and the semipolar surface. In a laser structure, a first surface is opposite to a second surface. The first and second fractured faces extend from an edge of the first surface to an edge of the second surface. The fractured faces are not formed by dry etching and are different from conventionally-employed cleaved facets such as c-planes, m-planes, or a-planes.
|METHOD OF MANUFACTURING DISPLAY APPARATUS - Provided is a method of manufacturing a display apparatus, including forming a drive circuit and a light-emitting portion on a substrate in which the forming the light-emitting portion includes forming a transparent anode electrode for applying a charge to an emission layer, forming a first coating layer and a second coating layer on the transparent anode electrode, removing the first coating layer by etching using the second coating layer as a mask, and forming a layer including the emission layer on a part of the transparent anode electrode from which the first coating layer is removed. A surface of the transparent anode electrode becomes as clean as a surface cleaned with ultraviolet irradiation.
|METHOD OF MANUFACTURING OPTICAL MATRIX DEVICE - According to a method of manufacturing an optical matrix device of this invention, an extension-promoting pattern that promotes extension of droplets printed and coated is formed on an insulation film as a foundation layer where printing patterns are to be formed, whereby the droplets extend along the extension-promoting pattern. Moreover, an extension-inhibiting pattern is formed at end portions of the printing patterns as to intersect the printing patterns, i.e., the extension-promoting pattern, whereby the extension-inhibiting pattern stops extension of the droplets extending along the extension-promoting pattern. Accordingly, control may be made of positional accuracy of the liquid droplets.
|METHOD FOR FABRICATING SEMICONDUCTOR LIGHTING CHIP - A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively.
|METHOD OF FABRICATING LIGHT EMITTING DIODE - Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.
|METHOD OF FABRICATING SENSORS HAVING FUNCTIONALIZED RESONATING BEAMS - Some embodiments relate to method of fabricating a sensor. The method includes providing a substrate wafer that includes a suspended beam; adding an adhesive layer to the substrate wafer such that the adhesive layer covers portions of the substrate without covering the suspended beam; positioning a cover wafer onto the adhesive layer such that the suspend beam is exposed to ambient air through openings in the cover wafer; and functionalizing the suspended beam by contacting the suspended beam with materials through the opening in the cover wafer.
|WAFER LEVEL PACKAGING PROCESS FOR MEMS DEVICES - A process for packaging micro-electro-mechanical systems (MEMS) devices comprises providing a lower cover wafer and an upper cover wafer, providing a semiconductor wafer including a plurality of MEMS devices on a substrate layer, bonding the semiconductor wafer to a first surface of the lower cover wafer, and bonding a second surface of the upper cover wafer to the semiconductor wafer. The first surface of the lower cover wafer and the second surface of the upper cover wafer define a plurality of hermetically sealed cavity sections when bonded to the semiconductor wafer such that each of the MEMS devices is located inside one of the sealed cavity sections. A plurality of holes are formed that extend from the first surface of the upper cover wafer to the second surface of the upper cover wafer after the upper cover wafer is bonded to the semiconductor wafer. A metal lead layer is then deposited in each of the holes to provide an electrical connection with the MEMS devices.
|MOVABLE JIG FOR SILICON-BASED THIN FILM SOLAR CELL - A movable jig for a silicon-based thin film solar cell comprises parallel electrode plates (
|DEPOSITION BOX FOR SILICON-BASED THIN FILM SOLAR CELL - A movable deposition box (
|MOUNTING OF SOLAR CELLS ON A FLEXIBLE SUBSTRATE - According to an embodiment, a method of manufacturing a solar cell includes depositing a sequence of layers of semiconductor material forming at least one solar cell on a first substrate; temporarily bonding a flexible film to a support second substrate; permanently bonding the sequence of layers of semiconductor material to the flexible film so that the flexible film is interposed between the first and second substrates; thinning the first substrate while bonded to the support substrate to expose the sequence of layers of semiconductor material; and subsequently removing the support substrate from the flexible film.
|NANOPARTICLE INKS FOR SOLAR CELLS - In a process for producing a solar cell, a sintering process performed on a nickel nanoparticle ink forms nickel silicide to create good adhesion and a low electrical ohmic contact to a silicon layer underneath, and allows for a subsequently electroplated metal layer to reduce electrode resistances. The printed nickel nanoparticles react with the silicon nitride of the antireflective layer to form conductive nickel silicide.
|METHOD OF FORMING RESISTANCE VARIABLE MEMORY DEVICE - A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.
|METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure is disclosed, which includes providing a substrate comprising a bottom surface and a growth surface opposite to the bottom surface; forming a buffer layer comprising a first surface which is not a C-plane substantially parallel with the bottom surface on the growth surface; forming a semiconductor structure on the buffer layer; forming at least one cavity in the buffer layer; extending the cavity along a main extending direction; separating the substrate and the semiconductor structure; wherein the main extending direction is substantially not parallel with the normal direction of the first surface.
|Methods for Forming Resistive Switching Memory Elements by Heating Deposited Layers - Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.
|Wafer Level Structures and Methods for Fabricating and Packaging MEMS - Methods of fabricating a Micro-Electromechanical System (MEMS) in a hermetically sealed cavity formed at a substrate level are provided. Generally, the method comprises: (i) forming a number of first open cavities in a surface of a first substrate and a number of second open cavities in a surface of a second substrate corresponding to the first open cavities; (ii) forming an actuator/sensor layer including a number of MEMS devices with electrically conductive regions therein; (iii) bonding the first substrate and the second substrate to the actuator/sensor layer so that at least one of the number of the first and second open cavities align with at least one of the number of MEMS devices to form a sealed cavity around the MEMS; and (iv) electrically connecting the electrically conductive regions of the MEMS device to a pad outside of the sealed cavity through an electrical interconnect. Other embodiments are also described.
|SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.
|METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.
|WIRING BOARD WITH BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A wiring board with a built-in electronic component includes a core substrate having a penetrating hole formed in the core substrate, an electronic component accommodated in the penetrating hole in the core substrate, a conductive pattern layer formed on a first surface of the core substrate and including a first conductive pattern and a second conductive pattern, and an interlayer insulation layer formed over the conductive pattern layer and the first surface of the core substrate. The second conductive pattern is formed adjacent to a periphery of the penetrating hole and contoured such that a sheet for positioning the electronic component in the penetrating hole is laminated horizontally with respect to the first surface of the core substrate over the penetrating hole.
|METHOD OF MANUFACTURING HIGH FREQUENCY DEVICE STRUCTURE - Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.
|CASCODED HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR - A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
|METHOD FOR FORMING METAL GATE AND MOS TRANSISTOR - The invention provides a method for forming a metal gate and a method for forming a MOS transistor. The method for forming a metal gate includes: providing a substrate; forming a sacrificial oxide layer and a polysilicon gate on the substrate; forming a silicon oxide layer on sidewalls of the sacrificial oxide layer and the polysilicon gate; forming a stop layer that covers the substrate; removing a part of the stop layer in the spacers; forming a second interlayer dielectric layer that covers the first interlayer dielectric layer, the spacers and the polysilicon gate; polishing the second interlayer dielectric layer to expose the spacers and the polysilicon gate; removing the polysilicon gate to form a trench; removing the sacrificial oxide layer in the trench; and forming a metal gate in the trench. The invention prevents from recesses and therefore metal bridge and metal residuals in the recesses.
|SEMICONDUCTOR DEVICE HAVING INSULATED GATE FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURING THE SAME - N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.
|Methods Of Forming Memory Cells - Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.
|NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.
|PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.
|HIGH ASPECT RATIO TRENCH STRUCTURES WITH VOID-FREE FILL MATERIAL - A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.
|INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
|Method of fabricating a semiconductor structure - The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.
|Self-Aligned Nanotube Field Effect Transistor and Method of Fabricating Same - A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
|METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Methods for fabricating a semiconductor device are provided wherein, in an embodiment, the method includes the steps of forming a gate electrode on a semiconductor substrate, forming a trench by recessing the semiconductor substrate in the vicinity of the gate electrode, doping an anti-diffusion ion into a portion of the semiconductor substrate in the trench, and growing an impurity-doped epitaxial layer on the semiconductor substrate doped with the anti-diffusion ion.
|METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING DEUTERIUM ANNEALING - A method of fabricating a semiconductor device is disclosed, the method generally including the steps of: forming a gate dielectric layer on a semiconductor substrate;forming a gate electrode on the gate dielectric layer;forming an etch stop layer on the gate electrode;forming a capacitor on the semiconductor substrate adjacent to the gate electrode;after forming the capacitor, forming a contact hole passing through the etch stop layer on the gate electrode;and, diffusing deuterium into the gate dielectric layer through the contact hole.
|METHODS FOR MANUFACTURING A PHASE-CHANGE MEMORY DEVICE - A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.
|SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.
|P+ POLYSILICON MATERIAL ON ALUMINUM FOR NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.
|INTEGRATED HIGH VOLTAGE CAPACITOR HAVING CAPACITANCE UNIFORMITY STRUCTURES AND A METHOD OF MANUFACTURE THEREFOR - The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (
|Method of Avoiding Resin Outflow from the Wafer Scribe line in WLCSP - A preparation process of wafer level chip scale packaging that prevents damaging a wafer in molding process is disclosed. In this process, a grinding grove is formed at a top side and around the edge of a wafer before molding is performed. The grinding groove effectively prevents the molding material from overflowing to the edge of the wafer, which avoids the damage of the wafer.
|STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI - A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion.
|III-V Compound Crystal and Semiconductor Electronic Circuit Element - Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
|PROGRAMMABLE METALLIZATION MEMORY CELL WITH PLANARIZED SILVER ELECTRODE - Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.
|METHOD OF FORMING PHOTONIC CRYSTALS - According to an embodiment of the present invention, a method of forming photonic crystals is provided. The method includes: forming a layer arrangement on a support substrate. The layer arrangement includes a first partial layer arrangement and a second partial layer arrangement, wherein the second partial layer arrangement is disposed over the first partial layer arrangement, wherein each partial layer arrangement comprises a first layer and a second layer, wherein the second layer is disposed over the first layer, and wherein the material of the second layer has a different etching characteristic than the material of the first layer. The method further includes removing at least one portion of the second layer and removing the first layer, wherein forming the layer arrangement occurs prior to removing the at least one portion of the second layer and the first layer.
|METHOD OF FORMING A HIGH CAPACITANCE DIODE - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
|PECVD DEPOSITION OF SMOOTH POLYSILICON FILMS - Smooth silicon and silicon germanium films are deposited by plasma enhanced chemical vapor deposition (PECVD). The films are characterized by roughness (Ra) of less than about 4 Å. In some embodiments, smooth silicon films are undoped and doped polycrystalline silicon films. The dopants can include boron, phosphorus, and arsenic. In some embodiments the smooth polycrystalline silicon films are also highly conductive. For example, boron-doped polycrystalline silicon films having resistivity of less than about 0.015 Ohm cm and Ra of less than about 4 Å can be deposited by PECVD. In some embodiments smooth silicon films are incorporated into stacks of alternating layers of doped and undoped polysilicon, or into stacks of alternating layers of silicon oxide and doped polysilicon employed in memory devices. Smooth films can be deposited using a process gas having a low concentration of silicon-containing precursor and/or a process gas comprising a silicon-containing precursor and H
|MANUFACTURING METHOD OF SILICON CARBIDE SINGLE CRYSTAL - A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.
|METHOD AND APPARATUS FOR ENHANCED LIFETIME AND PERFORMANCE OF ION SOURCE IN AN ION IMPLANTATION SYSTEM - An ion implantation system and process, in which the performance and lifetime of the ion source of the ion implantation system are enhanced, by utilizing isotopically enriched dopant materials, or by utilizing dopant materials with supplemental gas(es) effective to provide such enhancement.
|DUAL SPACER FORMATION IN FLASH MEMORY - A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed.
|Methods of Forming Semiconductor Devices - Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.
|METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening.
|SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O
|CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
|MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
|ALUMINUM ENHANCED PALLADIUM CMP PROCESS - A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.
|MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.
|METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.
|METHOD FOR MANUFACTURING INTERPOSER - A method for manufacturing an interposer equipped with a plurality of through-hole electrodes comprises a laser light converging step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region in the object; an etching step of anisotropically etching the object after the laser light converging step so as to advance etching selectively along the modified region and form a plurality of through holes in the object, each through hole being tilted with respect to a thickness direction of the object and having a rectangular cross section; an insulating film forming step of forming an insulating film on an inner wall of each through hole after the etching step; and a through-hole electrode forming step of inserting a conductor into the through holes so as to form the through-hole electrodes after the insulating film forming step; wherein the plurality of through holes are arranged such that the through holes aligning in the tilted direction are staggered in a direction perpendicular to the tilted direction as seen from a main face of the object.
|SEMICONDUCTOR DEVICE WITH THROUGH SUBSTRATE VIA - A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
|ANCHORED DAMASCENE STRUCTURES - An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps
|METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes sequentially forming an etch stop layer and a mold layer over a substrate, forming an open region by selectively etching the mold layer until the etch stop layer is exposed, transforming a surface of the mold layer into an insulation layer by performing a surface treatment, and forming a conductive layer inside the open region.
|METHOD FOR MANUFACTURING THROUGH-SILICON VIA - A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.
|Chemical Mechanical Planarization Composition And Method With Low Corrosiveness - A CMP composition and associated method are provided that afford good corrosion protection and low defectivity levels both during and subsequent to CMP processing. This composition and method are useful in CMP (chemical mechanical planarization) processing in semiconductor manufacture involving removal of metal(s) and/or barrier layer material(s) and especially for CMP processing in low technology node applications.
|OXIDE-RICH LINER LAYER FOR FLOWABLE CVD GAPFILL - The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.
|RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or general formula (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.
|METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE - A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.
|COMPOSITION FOR FORMING RESIST UNDERLAYER FILM FOR LITHOGRAPHY INCLUDING RESIN CONTAINING ALICYCLIC RING AND AROMATIC RING - There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1):
|PROCESSING ASSEMBLY FOR SEMICONDUCTOR WORKPIECE AND METHODS OF PROCESSING SAME - A processing assembly for a semiconductor workpiece generally includes a rotor assembly capable of spinning a workpiece, a chemistry delivery assembly for delivering chemistry to the workpiece, and a chemistry collection assembly for collecting spent chemistry from the workpiece. The chemistry collection assembly includes a weir assembly surrounding the rotor assembly and having a plurality of weirs. Methods for processing a semiconductor workpiece generally include moving at least one of the rotor assembly and the weir assembly.
|COMBINATORIAL PROCESS SYSTEM - A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.
|WET OXIDATION PROCESS PERFORMED ON A DIELECTRIC MATERIAL FORMED FROM A FLOWABLE CVD PROCESS - Methods of performing a wet oxidation process on a silicon containing dielectric material filling within trenches or vias defined within a substrate are provided. In one embodiment, a method of forming a dielectric material on a substrate includes forming a dielectric material on a substrate by a flowable CVD process, curing the dielectric material disposed on the substrate, performing a wet oxidation process on the dielectric material disposed on the substrate, and forming an oxidized dielectric material on the substrate.
|FILTERING ASSEMBLY AND MODULAR JACK USING SAME - A magnetic jack assembly includes a housing, circuit boards, shields and various filtering components. Multiple aspects of the assembly enhance manufacturability and facilitate automated manufacturing.
|RECEPTACLE CONNECTOR AND AN ELECTRICAL CONNECTOR USING THE SAME - A receptacle connector of the present invention is used as an electrical connector configured to connect two circuit boards. The receptacle connector includes: a housing in which a receiving space is formed, a connection target being inserted in the receiving space; a plurality of contacts being arranged parallel to one another, having a plurality of signal line contacts and a plurality of ground contacts, and being placed with every two adjacent signal line contacts for transmitting signals interposed between two ground contacts; a supporting member made of an electrically-insulating synthetic resin material, and configured to integrally support and fix thereto the plurality of contacts; and a common contact made of a conductive resin material and configured to electrically connect the plurality of ground contacts together among the plurality of contacts. The plurality of contacts integrated together by the supporting member are received in the receiving space.
|DAUGHTER CIRCUIT BOARD FOR INTERFACE SIGNAL CONVERSION - A daughter circuit board of an electronically commutated motor for interface signal conversion, having circuit units integrated on the daughter circuit and eight ports for communicating with a control system of a user terminal, the daughter circuit board being plugged into a motor controller for signal conversion so that the motor controller communicates with the control system of the user terminal. The eight ports include an input port of power supply, a port of mode selection, a signal port of PWM, a R/T port for data transmission between the daughter circuit board and the control system of the user terminal, a port of COM, a port for fault signal output, a port of power indication, and a port of speed feedback. The daughter circuit board is simple, easy to correspond with various control systems of user terminals, and accords to the latest electric standard thereby facilitating management and popularization.
|PLUG-IN SYSTEM - Exemplary embodiments are directed to a plug-in system having a lower part, on which busbars can be arranged, and an upper part which is made of electrically insulating material and is releasable from the lower part in a non-destructive manner on a top side arranged opposite the underside. Protective devices having electrical contacts can be arranged on the plug-in system. The upper part has openings through which the electrical contacts of the protective devices can make direct contact with the busbars. The openings are configured in such a manner that the plug-in system is shockproof to IP XXB. The upper part and lower part are latchable into one another or are screwable to one another in such a manner that the upper part is releasable from the lower part only from the underside of the plug-in system.
|TEST SOCKET - A test socket is provided including a socket board, socket pins and a guiding member. The socket pins are exposed to an upper surface of the socket board and are configured to be electrically contacted by external terminals of an object. The guiding member is disposed on an upper surface of the socket board and is arranged to guide the external terminals as a single unit to contact the external terminals with the socket pins. The guiding member is also configured to a center of the socket board with a center of the object.


text:
Use the AV input on a computer equipped with a capture card to connect the PC to AV equipment and save digital copies of videotapes, vinyl recordings and other media to the hard drive. For example, you could convert old albums into digital audio files by connecting the PC to a turntable, or convert family home videotapes into digital video by connecting to a VCR. You can later burn the converted video files to DVD and burn music files to CD or upload them to a personal audio device.
Connect audio cables to the audio "Input" jacks on the back of the computer's central processing unit, using the white plug for the left channel and the red plug for the right.
Insert the yellow video plug into the yellow video "Input" jack on the computer, if using an AV component.
Connect the plugs on the other end of the cables to the "Output" jacks of an audio or video device using the same color codes.
Video of the Day
Open the recording software on the computer by double-clicking the name of the program.
Insert a recording into the connected device, such as a videotape into a VCR or a cassette into a tape deck, and press "Play."
Click the "Record" button to capture the pre-recorded media from the device attached to the computer with the AV inputs. Click the "Stop" button when finished, then click the "File" tab and choose "Save" to create a name for the recording and store it on the computer.
Disconnect the AV component from the computer when not in use.

subset: commoncrawl


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Louisville chef Edward Lee is stopping in St. Louis tonight, August 13, to sign copies of his new cookbook, Smoke and Pickles: Recipes and Stories from a New Southern Kitchen at Taste (4584 Laclede Avenue; 314-361-1200) at 5:30 p.m. Oh, and he's inspired a special menu for us St. Louisans.
See also: - Taste's Grilled Asparagus with Crisp Poached Egg: One of 100 St. Louis Dishes You Must Eat Right Now - Taste's "Barbacoa": One of the 100 St. Louis Dishes You Must Eat Right Now - Taste's Kyle Mathis: Winner of Iron Fork's Mixology Competition and Featured Bartender of the Week
You might remember Lee from last year's Top Chef: Texas (he lasted fourteen weeks); he's also a three-time James Beard Foundation Award finalist. Though he grew up in Brooklyn, he considers Louisville his adopted hometown -- it's where he discovered the restaurant 610 Magnolia on a trip to the Kentucky Derby in 2002. A year later, Lee moved south and bought 610 Magnolia.
Jefferson's Reserve will provide a bourbon tasting featuring Lee's own bourbon sweet tea and Taste has whipped up some Smoke and Pickles-inspired hors d'oeurves: smoked coffee-pickled beet bruschetta with pumpernickel toast and whipped ricotta, pulled barbecue lamb necks on lamb-fat bacon cornbread with bourbon-pickled jalapeños, house-cured bresaola with parsnip and black pepper biscuits with blackberry ketchup, miso chicken tacos with a pineapple-pickled jicama slaw and garlic-puffed rice, puffed rice crackers with roasted pork shoulder topped with black barbecue sauce and jasmine pickled peaches, and pork cracklins.
Tickets are $50 and include admission, food and drink, and an autographed copy of Smoke and Pickles. You can get them here.
Gut Check is always hungry for tips and feedback. Email the author at firstname.lastname@example.com or follow her on Twitter.
Subscribe now to get the latest news delivered right to your inbox.


text:
Christopher Kelly, who had been one of Gov. Rod Blagojevich's key fundraisers and closest advisers, is set to plead guilty Jan. 16 in a federal tax-fraud case, court records show.
He was charged about a year ago with improperly using corporate funds to cover gambling debts.
Attorneys Michael Monico and Barry Spevack, who have represented Kelly, could not immediately be reached for comment.
--Jeff Coen


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Here is a four ingredient, vegan recipe for some seriously cozy-delicious noodles. These Golden Garlic Leek Chow Mein Noodles are the perfect addition to an easy weeknight meal. Simply add a few sides and dinner is served. Top with tofu triangles. Pair with a crisp slaw salad. These tender chow main noodles are infused with golden buttery, sweet leek, zesty garlic flavors. Try this easy recipe!..
I made this recipe even easier to prepare by using Annie Chun's FreshPak Noodles. They are pre-cooked, so all I had to do was open the bag and sauté with my ingredients. Plus, unlike most chow main noodles, the FreshPak variety are egg-free – making this dish totally vegan.
Golden Garlic Leek Chow Mein Noodles
1 FreshPak Chow Mein Noodles (170g) (or use traditional dry noodles)
1 tsp garlic powder
1 1/2 cups fresh or frozen leeks, chopped
2-3 Tbsp vegan buttery spread (Earth Balance)
optional: a few sprinkles of nutritional yeast (adds more golden color, a subtle cheesy flavor and nutrients)
salt/pepper to taste as needed
To Make:
1. Chop your leeks, if using fresh.
2. Place saute pan on stove over high heat. Add in one tablespoon of the vegan butter. Allow buttery spread to melt.
3. Add in the leeks. Saute for a few minutes, until leeks become tender.
4. Add in the noodles (if using cooked dry noodles instead of a FreshPak, be sure to drain noodles well before adding to pan.)
5. Add in the remaining buttery spread and garlic powder.
6. Saute until the flavors absorb into the noodles and noodles become tender.
7. Salt and pepper to taste. Add optional nutritional yeast.
Read more from Kathy on Kathy's blog, Healthy. Happy. Life!
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More on Family Kitchen:
Another Asian Noodle Recipe: Garlic Udon Noodles with Tofu and Veggies
Check out my 25 Healthy Foods to Add to Your Diet in 2012


text: Ok, so earlier I created a new hotmail account under a false name, for unrelated nefarious matters. Next thing I know the account receives an email from facebook!? So I get facebook to reset the password, it sends me the new password link to the hotmail account. I log into facebook and blow me down, it's a live account, with close to 400 friends. So, what do I do with it? Any ideas? p.s. The owner of the account is HOT! (for those who are interested!)


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To preserve and protect
The proposal by Blake Development Corporation to demolish 415 West Moreland Ave is a serious breach of the implicit, unwritten agreement we all live by in this National Historic District: that is, we will preserve the fine historic properties we've inherited if at all possible, rather than break up large parcels of land into sub-divisions with new construction. Yes, it costs more to preserve an older building. Yes, owners and developers forego a lot of money when they chose not to build out their lots to the maximum extent allowed by zoning laws. But we choose to live in Chestnut Hill anyway because it's an unusually beautiful place, and this is what we have to do to keep it so.
When my wife and I bought our 1890 Houston/Hewitt twin several years ago, as the former owner turned over the key he commented "You know, we don't really own these properties – we just hold them in trust for the next generation." He was absolutely correct.
Many people in the St. Martins neighborhood would simply like to clean up this distressed and neglected property as soon as possible. I'm sympathetic, but I cannot countenance the demolition of a fine Colonial Revival house (and a separate carriage house) by a highly-regarded American architect when it is not necessary, particularly when the developer plans to further damage the fine Moreland neighborhood by sub-dividing the 1-acre lot. This sets an ominous precedent which jeopardizes numerous iconic properties in Chestnut Hill!
Sam Blake is a well-regarded local developer who has made a success of upgrading and re-purposing Chestnut Hill buildings while respecting their historic features and design. I have urged him to re-consider his initial plan. In the long run, preservation builds higher real estate values for all of us.
Frank Niepold
Chestnut Hill
Tired of looking for parking
Just wanted to say that about half the time I want to shop in Chestnut Hill, I end up driving on to my home in Roxborough as I cannot find any place to park between Gravers and Evergreen. I would like to use Kilians, Weavers Way, and other places, too, but am not willing to keep driving around the block, and through parking lots.
Susan R. MacBride


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Companion Animal Care
Companion Animals - Cats -Dogs - Rabbits - Fish - Pets - Vegan - Vegetarian - Human Rights - Animal Rights - People - Animals - Love - Compassion - Peace - Justice - Righteousness - God - Bible - Jewish - Christian - Jesus - Christ - Holy Spirit - Soul - Spirit - Wisdom - Knowledge - Environment
Research by UNE Scientist Shows Dogs Thrive as Vegetarians
From ArmidaleExpress.com.au
In the case of dogs, Dr. Brown says, vegetarianism should be assessed purely from a nutritional perspective - i.e., whether the diet meets the dog's nutritional needs, maintains the dog's health, and is sufficiently enjoyable for the dog to eat enough of it.
Armidale scientist Wendy Brown is at the centre of groundbreaking international research that has found that dogs can thrive on a meat-free diet.
Dr. Brown was part of a team of scientists who monitored the health and performance of Siberian huskies over a 10-week sled-racing season.
They concluded that hard-working dogs can perform just as well on a meat-free diet as they do on a meat-rich diet.
Their results, published earlier this year in the British Journal of Nutrition (Vol 102, pp 1318-1323), add to the evidence that dogs fed an exclusively vegetarian diet can be just as healthy and happy as their meat-eating relatives.
Dr. Brown, the canine nutritionist from the University of New England who led the husky trial, is confident that dogs can thrive on a meat-free diet.
She warns dog owners, however, that preparing an adequate vegetarian diet for a dog is more difficult and time-consuming than they might think.
Dr. Brown has concerns, too, about some of the vegetarian dog foods that are becoming commercially available in growing numbers.
Many of these, she said, are untested.
"People manufacturing and buying vegetarian and vegan pet foods are often against testing, believing that even feeding trials are cruel," she said.
"But feeding trials can be done in a friendly way. For my own trials, I borrow people's pet dogs - some of them show dogs - and they are always well cared for. People visiting my kennels comment on how happy the dogs look. And they are.
"When I feed my own dogs, I want to know that what they're eating is nutritionally adequate.
"As dogs belong to the order Carnivora, it's often assumed that they are exclusively carnivorous, but in fact they are omnivores, belonging to the same superfamily within the Carnivora as the bamboo-eating giant panda and the omnivorous bear."
In a paper presented at the University of New England during the international conference Recent Advances in Animal Nutrition 2009 and published in the conference proceedings, Dr Brown addresses the common argument that vegetarians should not impose their own values on their pets.
"A similar argument is often raised when human parents impose their religious or moral beliefs on their children, particularly when the belief system differs from that of the ethnic majority or predominant culture," the paper says.
"In either case, it would be wise to assess the situation without prejudice."
In the case of dogs, Dr. Brown says, vegetarianism should be assessed purely from a nutritional perspective - i.e., whether the diet meets the dog's nutritional needs, maintains the dog's health, and is sufficiently enjoyable for the dog to eat enough of it.
Research has shown that vegetarian diets can meet these requirements, but that the preparation of a home-made vegetarian diet for a dog can be an exacting and time-consuming process.
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Continental Airlines (NYSE:CAL) announced it is expanding the number of its Presidents Clubs offering wireless Internet access, with all 28 clubs Wi-Fi-enabled by the end of 2004.
The airline currently offers the service at its five Presidents Clubs at Houston's Bush Intercontinental Airport, three at Newark Liberty International, and one at Cleveland Hopkins International.
The service, powered by Cisco Aironet Wi-Fi Access Points, enables any Presidents Club member with a Wi-Fi compatible computer or client card to access the Internet from anywhere in the club. Continental will have tip sheets available to help members log in to the service.
"Customers increasingly want to stay connected, both on the ground and in the air," said a Continental spokesperson. "Wireless Internet access in our Presidents Clubs and Verizon's JetConnect service onboard our aircraft let travelers stay in touch throughout their travels."
Continental Airlines is the world's seventh-largest airline with more than 2,300 daily departures to 126 domestic and 101 international destinations throughout the Americas, Europe and Asia. With 42,000 mainline employees, the airline has hubs serving New York, Houston, Cleveland and Guam, and carries approximately 51 million passengers per year. FORTUNE ranks Continental one of the 100 Best Companies to Work For in America, an honor it has earned for six consecutive years. FORTUNE ranked the company highest among major U.S. carriers in the quality of its service and products, and No. 2 on its list of Most Admired Global Airlines in 2003. For more company information, visit continental.com.
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I am not the only person who feels that some (most definitely not all) people on the left are holding the President to unrealistic standards. Here are three columnists writing about the original stimulus bill and the impending jobs speech.
Jonathan Chait in New York Times today on why he thinks Obama is getting a raw deal:
…the wave of criticism from the left over the stimulus is fundamentally flawed: it ignores the real choices Obama faced (and the progressive decisions he made) and wishes away any constraints upon his power.
The most common hallmark of the left's magical thinking is a failure to recognize that Congress is a separate, coequal branch of government consisting of members whose goals may differ from the president's.
Jonathan Alter defending the President in Bloomberg last week:
From the left: "He should have pushed for a much bigger stimulus in 2009.â€
That's the view of New York Times columnist Paul Krugman, now gospel among liberals. It's true economically but bears no relationship to the political truth of that period.
Ezra Klein, in Washington Monthly yesterday on how unrealistic it is to expect anything Obama proposes in his coming jobs speech to go anywhere:
The fantasy version of the [Congressional Republicans'] role can be found in Aaron Sorkin dramas and liberal op-ed columns, in which Obama's rhetoric stirs the hearts of some while his rallying of the people inspires fear in the others. Republicans then agree to meet with Obama and work out a compromise plan. In some versions of the fantasy, the result is a big compromise that includes deficit reduction and revenue-raising tax reform. At some point in the drama, a weaselly political adviser warns his boss that voting for the deal could cost him his job. "So what?†the boss snarls. "It's better to be an ex-congressman than an irresponsible congressman.â€
However, Jon Walker at FDL does not agree that Presidential authority is as constrained as his fellow commentators believe. With brio, he presents his plan for steamrolling any opposition to more federal stimulus:
Obama should acknowledge the economy is bad, lay out a big direct jobs plan, and demand the GOP pass the whole thing. When the Republicans quickly make it clear they won't pass the big jobs plan, Obama can publicly make it clear that Republican intransigence "forced†him to be creative with the powers he currently has. At this point, Obama should unilaterally implement his "Plan B,†creatively using unspent TARP money and using the Federal Housing Finance Agency (FHFA) to implement massive mortgage refinancing and own-to-rent programs. If done right, it's a substantial stimulus.
Readers: The President's jobs speech approaches. As Mel Allen used to say "You make the call"!


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By Texas Criminal Defense Lawyer Jeremy Rosenthal
(972) 369-0577
*Jeremy Rosenthal is an attorney licensed in the State of Texas and is Board Certified in Criminal Law. Nothing in this article is intended to be legal advice. For legal advice about any situation you should contact a lawyer directly. This forum and its contents are not subject to the attorney-client privilege.


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It seems to me that all of us who live in modern industrial democracies have a lot of hard thinking to do over recent economic news. Here are the essential facts which seem to point to difficult social and political conclusions.
The American economy began to slow down during the month of June. The index of leading economic indicators showed what was called a ''sharp'' drop. It appeared to be the first such decline in 21 months. It showed declines in such areas as factory orders, construction spending, prices of sensitive raw materials, and pressure on suppliers.
The news triggered a wave of exuberant buying on the stock market. In terms of both volume and price gains it was the biggest buying week in Wall Street history. It amounted to a massive expression of confidence in the health of the American economy.
Why is a slowing of the economy a sign of health?
Part of the answer is easy. The market had for months been held back by anxiety about a revival of inflation. The scale of government borrowing that will be necessary to fund the expected federal deficit could, by itself, force interest rates up to levels that would smother the recovery. The news of the slowdown lifted that anxiety from the market. It is expecting lower, not higher, interest rates in spite of the deficit.
But then we come to the next level of the problem. What else is happening in the American economy which can balance off the inflationary push of expected high federal deficits?
The answer comes in two parts. First, the productivity of American labor is up nicely. The output per man-hour in all nonfarm business in the US went up by 3.3 percent during the first quarter of the year. And second, wages did not go up appreciably.
The Bureau of Labor Statistics issued an employment cost index for June up eight-tenths of 1 percent, compared with a rise of 1.7 percent in May. It means that wages and salaries are remaining relatively stable.
Now we come to the politically hardest part of the problem.
The same week that showed economic stability setting off a massive upsurge in the stock market also brought an official Bureau of the Census report showing that the level of poverty in the US rose by nearly a million people in 1983 over 1982.
The same week brought news of a rise in the unemployment rate from 7.1 percent of the work force in June to 7.5 percent in July. This was the first rise in unemployment in 20 months. The trend had been down steadily. The July rise in joblessness seems to parallel the slowing in the economy. The demand for labor is slacking off at a time when any rise in the demand would probably be enough to set off a major rise in wage demands, hence inflationary pressure.
The Economist magazine, in its July 28 issue, puts much of this in a challenging perspective. It noted that between 1975 and 1983 Western Europe raised its output by almost as much as America, but that employment stood still in Europe, while it rose by one-sixth in America.
''The main reason,'' The Economist says, ''was that real wages in Europe went on rising, while in America they were cut. In 1973-82 British industrial workers' real hourly earnings went 10 percent up, and total British employment went 7 percent down; simultaneously American industrial workers' real hourly earnings went 11 percent down, and total American employment went 16 percent up.''
In the Soviet Union everyone, by law, has a job. There is no such thing as unemployment. The government makes work for everyone in some form or another; in forced-labor camps when all else fails. The Soviet economy is notoriously stagnant and inefficient. The communist countries that are doing better economically are the ones that have allowed the profit motive to revive, either openly or surreptitiously.
Few Western politicians will accept the idea that some poverty, some unemployment, and wages limited to the rise in productivity are necessary for a healthy economy. But how else does one explain the obvious health and strength of the American economy today? It makes a startling contrast to the stagnation of a full-employment economy in the Soviet Union and the rising-wages economy of West Europe.


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