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The BBC promised it would have it all: celebrity judges, great singers and a unique twist that would set it apart from the deluge of talent shows on television. When The Voice launched the Saturday before last, I – along with nine million others – had it marked down in my diary as a non-negotiable night in.
Since the new crop of 21st-century talent shows, Britain's Got Talent, Strictly Come Dancing and The X Factor, exploded on to our screens, the contests have become weekend staples. It seems that we need our fix of dancing dogs and spangly dresses at least once every seven days. But The Voice was meant to be different: a serious talent contest – one with integrity – that wouldn't judge contestants on their looks, instead focusing on "one thing and one thing only: the voice".
The first episode really delivered. The "blind" audition format, in which judges sit with their backs to contestants, turning around once they have committed to putting them through to the next round, was refreshing. The judges – Sir Tom Jones, pop sensation Jessie J, will.i.am from The Black Eyed Peas and The Script's Danny O'Donoghue – were likeable. It was worth switching on for Jessie J's outfits and Sir Tom's stories ("I was with Elvis Presley in Hawaii...") alone.
But last weekend, as 9.6 million viewers picked The Voice over the latest series of Britain's Got Talent (at least for the 20 minutes that they overlapped), it all fell apart – for me anyway. My naïve belief that the BBC had imported a fresh new format for a talent show – one that started in Holland and topped ratings worldwide – was shattered. The contestants proved to be exactly the same: decent voice, decent appearance, decently interesting back story that impressed the producers. The Voice is just another reality series like countless others before it. And if anything, it's worse – because it's disingenuous about what it represents.
I should have seen it coming, but I was duped by The Voice's pledge to put singing ability above appearance. Surely the show is designed for the Susan Boyles of this world: vocally gifted but not so aesthetically endowed? Instead, we've had the usual range of smoky-eyed teens and stubbly guitar-players – at worst a dubious hairstyle or "alternative" outfit. It makes a mockery of the integrity the show purported to have.
As for the auditions, the BBC has been open about the fact that performers don't step straight off the street on to the stage. Each has been carefully selected by the producers – and presumably this is not done blind. Once the audition stage ends – what next? There are two more weeks before the "battles" begin, in which each contestant will sing live in front of a studio audience. Sound familiar?
The problem with The Voice is that, like its stream of washed-up Nineties stars (Sean from 5ive and Five Star's Deniece Pearson are among those auditioning), we've seen it all before.
Once you strip away the fancy revolving chairs and watch the presenters trying to pad out what would otherwise be ad breaks, you're left with nothing but – as one ITV source put it – "a poor man's X Factor". So what happens next? The BBC worries that viewing figures "might drop off" as audiences get used to the format, and they could be right.
The Voice started well – but it's downhill from here. The talent show has been done to death, and contrary to what I'd hoped, a swanky new format isn't enough to revive it. The blind factor will keep us hooked for another two weeks, but after that, all we'll be left with is another bad excuse for a Saturday night in.


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2010 Volkswagen GTI: Strange Headlight Decision
May 20, 2010
Just look at this headlight and all its fine detailing. You've got the little logo there and all sorts of carefully constructed reflectors that look good whether the light is on or off. Clearly someone thought long and hard about this.
So then, why is it that the GTI doesn't have automatic headlights? I mean, all that effort and they couldn't figure out a way to price in a knob with an extra detent for the ol' "A" option. Seems like an odd oversight for a car that has so many details right.
Ed Hellwig, Senior Editor @ 5,820 miles

subset: commoncrawl


text: Trying to complete the set of base/refractor/atomics and one of the last cards I need is the MI4 Kevin Brown / Mike Piazza / Ivan Rodriguez Atomic. Theres one on COMC for way more than it should be priced at, and can't find another. Anyone have one they wanna sell?


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- Animal Feed[10]
- Apparel Agents[1]
- Food Agents[1]
- Biological Fertilizer[8]
- Organic Fertilizer[10]
- Other Fertilizers[8]
- Plant Food[2]
- Other Organic Chemical[1]
- Catalyst[10]
- Chemical Auxiliary Agent[10]
- Daily Chemicals[2]
- Feed Additives[10]
- Food Additives[10]
- Other Chemicals[6]
- Waste Management[10]
- Water Treatment[10]
- Detergent[4]
- Drain Cleaners[3]
Cellulase Enzyme Sukacell
SUKACell is acid cellulase which widely used in feed, textile, wastewater treatment and paper making industries.
SUKACell Acid Cellulase
Cellulase is an unbranched glucose polymer composed of anhydro-D-glucose units linked by 1,4-b-D-glucoside bonds. These glycosidic bonds can be hydrolysed by cellulolytic enzymes. The native structure of the cellulose is composed of crystalline and less organized amorphous regions.
SUKACell is an enzyme preparation obtained from the submerged fermentation of a high cellulase-producing microbial strain. It is widely used in feed, textile, wastewater treatment and paper making industries.
The 1,4-b-D-glucosidic linkages in cellulose, lichenin and cereal b-D glucans are hydrolyzed to release free glucose units through the successive action of cellulase enzymes.
The less organized amorphous region at the center of the cellulose chain is initially attacked by endoglucanase by random cutting of the b-1,4 glycosidic linkages within the chain thereby producing cello-oligosaccharides. Cellobiohydrolases I and II act on the cello-oligosaccharides from the reducing end and non-reducing end of the cello-oligosaccharides to release cellobiose. b-glucosidase act on the released cellobiose to produce bD glucose units.
SUKACell provides maximal benefit at pH 4.8 5.2 and at the temperature of 55 60 (131 140).
SUKACell is available in liquid preparation as:
SUKACell LQ10 (with enzyme activity of 10,000 U/mL)
SUKACell LQ20 (with enzyme activity of 20,000 U/mL)
SUKACell is available in solid preparation as:
SUKACell PW10 (with enzyme activity of 10,000 U/g)
SUKACell PW20 (with enzyme activity of 20,000 U/g)
Unit definition: The amount of enzyme needed to produce 1 mg glucose from carboxymethylcellulose (CMC) in one hour at specified conditions by the DNS method.
? For use as a feed additive, SUKACell can be added to the mix at a rate of 0.05-0.1%.
? For use in the textile industry, add SUKACell at the rate of 2.5-5 g/kg of fabric dissolved as 5:1 water : clothes ratio. The product can also be added at 5-10 g/kg of fabric dissolved as 10:1 water : clothes ratio.
? For the paper making industry, SUKACell is added based on the instructions of the technicians.
SUKACell is packaged in 25 kg/plastic drum and 1000 L/plastic drum for the liquid form while the solid preparation is packaged as 20 kg per box or film lined woven bag.
Alternative packaging is available upon request for smaller or larger volumes.
Store in a cool, dry place and away from direct sunlight. SUKACell maintains its activity for considerably longer time when stored at lower temperatures (below 25). The product should not be frozen.
SUKACell is non-toxic and biodegradable. However, unnecessary contact with the product should be avoided. Long term exposure to protein based products such as SUKACell may sensitize certain individuals to the product. Wash hands with warm soapy water after handling. Keep out of reach of children.


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Product overview
HALE is reliable supplier of products for the taxi business and partner of taxi and rental car companies. The export to more than 40 countries makes HALE an international provider with highest expertise and experience. HALE is direct supplier for the German automotive industry and certified not only according to ISO/TS 9001:2008 but also to EN ISO/TS 16949:2009, which qualifies HALE as automotive supplier worldwide.
In addition to taximeters, thermal paper printers and roof signs HALE currently offers complete systems and solutions for driver accounting, fleet management as well as for tracking and dispatching. These core products are completed with a range of service tools and accessories and comply with the requirements and needs of the taxi business.
Thanks to our long-term experience in the taxi business, we offer flexible innovations in response to changes in the market. Modern technology, unconditional product quality and easy operation characterize the HALE product range.


text:
It's free with no obligation - cancel anytime
Stately Craftsman home in spectacular Woodinville Location. Grand finishes throughout: stunning resort style master suite with Statuario Marble his and her vanities, heated bathroom floors, & a blend of rich stained & painted cabinets. Entertainment style main floor with spacious great room & heated outdoor living. Utility rooms on both floors & oversized 3 car finished garage make for easy living. High end appliances, air conditioning, Quartz counters, gorgeous flooring & custom walk in shower.
Don't worry! We'll never spam you or sell your details. You can unsubscribe whenever you'd like.
Listing Courtesy ofJohn L. Scott Everett


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[ACC PREVIEW] How competitive was the ACC in 2011? It had three teams reach the Women's College Cup -- and four make the final eight -- and none of them was
named North Carolina. Eight ACC teams made the final 16 and nine of its 11 members made the 2011 NCAA Tournament. All we know is the ACC will be just as competitive in 2012. Duke and Wake Forest,
ranked 1-2 in the ACC coaches' poll both return all 11 starters, and the ACC's top 10 scorers are all back.
Duke was the overwhelming favorite of ACC coaches, taking 10 of 11 first-place votes. It marks the first time a team other than North Carolina was selected first in the ACC preseason poll since the coaches' vote began in 1992.
The Blue Devils' list of returnees from last season's 22-4-1 team includes ACC Defensive Player of the Year Natasha Anasi, midfielder Kaitlyn Kerr and forwards Kelly Cobb, Laura Weinberg and Mollie Pathman, who combined for 25 goals and 24 assists.
Wake Forest is strong in the back with goalie Aubrey Bledsoe, a member of the 2011 Soccer America MVPs second team, and up front with 2011 ACC Offensive Player of the Year Katie Stengel (19 goals and 8 assists).
Florida State, one of the three semifinalists, won the ACC Tournament after going 5-5-0 in the regular season. Tiffany McCarty (18 goals, 6 assists) will lead the Seminoles' attack that has added Icelandic international Berglind Thorvaldsdottir.
While Duke, Wake and Florida State all went to the College Cup, Virginia lost in the quarterfinals at FSU.
The Cavaliers return five of their front six, including Soccer America Freshman of the Year Morgan Brian, top goal scorer Caroline Miller (15 goals) and Erica Hollenberg, who led the team with 10 assists.
The 2011 season was, to say the least, a down year for North Carolina, which finished the regular season with three straight defeats, including its first ever loss in the ACC Tournament.
But even without Lindsey Horan, who signed over the summer with Paris St. Germain, North Carolina welcomes one of the nation's best freshman classes led by U.S. U-20 goalie Bryane Heaberlin and U-17 star Summer Green.
(UPDATE: Indi Cowie, dubbed the best freestyle soccer player in the world, will red-short after injuring her knee this spring.)
Heaberlin is one of three Tar Heels along with Crystal Dunn and Kealia Ohai representing the USA at the Under-20 Women's World Cup in Japan.
Six other ACC players are on the U.S. U-20 team: Kassey Kallman (Florida State), Dayle Colpitts (Virginia Tech), Cobb and Pathman (Duke), Brian (Virginia) and Stengel (Wake Forest). (Virginia's Steve Swanson is the U-20s' head coach.)
The one coaching change in the ACC took place at Maryland, where Brian Pensky left for Tennessee and was replaced by his assistant, Jonathan Morgan.
2011 REGULAR SEASON. 1. Duke (8-1-1), 2. Virginia (7-2-1), 3. Wake Forest (5-2-3), 3. North Carolina (6-3-1). 5. Boston College (6-4-0).
2011 TOURNAMENT. Florida State beat Wake Forest 1-1 (3-1 on penalty kicks).
2011 NCAA TOURNAMENT. Duke lost in final, Florida State and Wake Forest lost in the semifinals, Virginia lost in the third round, Boston College, Maryland, North Carolina and Virginia Tech lost in the third round, Miami (Fla.) lost in first round.
2012 FAVORITE. Duke
2012 CONTENDERS. Wake Forest, Florida State, Virginia, North Carolina.
2012 CREAM OF THE CROP. D Natasha Anasi, Duke, jr.; F Tiffany McCarty, Florida State, sr.; F Katie Stengel, Wake Forest, jr.; G Aubrey Bledsoe, Wake Forest, jr.; M Morgan Brian, Virginia, soph.; M Kristen Mewis, Boston College, jr.; M Crystal Dunn, North Carolina, jr.; M Kaitlyn Kerr, Duke, jr.; M Kelly Cobb, Duke, soph.; D Ines Jaurena, Florida State, sr.; M Amber Brooks, North Carolina, sr.; F Caroline Miller, Virginia, sr.
2012 TOP NEWCOMERS. G Bryane Heaberlin, North Carolina; M/F Summer Green, North Carolina; F Berglind Thorvaldsdottir, Florida State; M Ashley Spivey, Maryland; M Cassie Pecht, Duke; F Lauren Bernard, Boston College; M Makenzy Doniak, Virginia; M Dria Hampton, Florida State (transfer); G Alexa Gaul, Boston College (transfer).
Email: Send releases to Soccer America
Friend Soccer America Facebook
Follow Soccer America Twitter


text: I will get ideas like this out of the blue, but I think that this one is entirely doable. Here is the premise. First you go down to your nearest tech store and buy a phone with prepaid minutes on it, the cheapest will do. Make sure it is active and it has a working number and such. Then you sign up for the service at brring*com, and use the number that you have for the cell phone. Get this all situated and have it active. Now, the best part. Sign up for any and every free phone offer you can find so that the telemarketers are ringing you nonstop. With enough effort you can easily hit 15-30 calls a day since I know people who get them without even wanting them. Set it/them on silent and let the money flow in.


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Finally. After four years of being bullied, Emily finally...
Everything about you
- by xXLouis_GirlXx
- Rating:
- Published: 2 Oct 2013
- Updated: 2 Oct 2013
- Status: In Progress
Siena and Louis have been together for six months. They are in their last year of high school along with some tore very close friends. Siena and Louis have planned out their whole future together, but in the last few months of high school things start to get bad. When Siena's worst enemy Chelsea starts getting flirty with Louis when she is off ill, she assumes the worst. But suddenly Siena's ex boyfriend shows up. What will happen when Louis sees the two of them together?
Join MovellasFind out what all the buzz is about. Join now to start sharing your creativity and passion
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Thursday, December 20, 2012
Yielding On A Single Track, Who Gets Priority?
The following day was more interesting as we got to cycle Kota Damansara community forest reserve led by Winston and some friends from KLMBH.
I believe many of you including me have never crossed our minds on this subject as who is to give way on this matter. Winston shared with the rider what is the universal understanding practised in US. I looked up Google "yielding on a single track" and got the same answer as what Winston told this rider.
The rider cycling down yields. Why? It sounds dangerous right? Well, the reasoning behind this is that it is harder to get going again on a climb than on a downhill.
So, there you have it. No more quarreling over who gets the right of way. If you are in a cycling group or club, please share this news to everyone.
Since we are on this subject of Trail Etiquette, I might as well add that as a cyclist, it is our duty to yield to hikers, people walking on the trail and animals such as horses, cows, etc.
Last photo is a note to myself. Never inspect one's fork on while moving on a tarmac road going downwards. Makes one look stupid doing the front endo before hitting the off road trail.
Tuesday, December 4, 2012
Kayuh Lasak 2012
This year's Kayuh Lasak is one of the best in terms of distance and difficulty. I am disappointed for not being able to get all 10 CP stickers - The only Kayuh Lasak without complete stickers (except for 2003 which is a long story). Missed out CP8 NOT because not fit but rather didn't reach the cut off time in time due to the spirit of brotherhood and keeping company to our friends who were experiencing cramps. I feel it is worth giving up the trophy of feel good over friendship. That inspires me to want to try to complete the whole trail of KL12 one day as I heard the trail from CP8 to CP9 is fantastic.
Thanks to my fellow members who went as your friendship counts a lot and the memories will last a lifetime.
To KOTRTies, it's been great knowing you guys since the very first, The 1 Hill Ride and going every year since then. I think it was a good move to have the last 2 previous rides start at Balik Pulau and the finale (hopefully not) back to where it started, Youth Park.
Thank you for: initiating the idea of a properly organised mtb jamboree in 2002 when one would think it's crazy to drive all the way to Penang just to cycle, the meaning of hardship of pushing up and going over obstacles, to learn what is fear when the moment comes, the indescribable exhilarating thrill when bombing down what is seemingly endless single track downhill, etc and the most important, the opportunity to get to know all of you. Thank you!
Friday, April 13, 2012
Chiang Mai Cycling Adventure
The furthest so far that I have have ever been on a cycling trip is to Hatyai and much nearer but still in Thailand, Betong and down south, Singapore.
My cycling members from ECC have traveled a number of countries and some even cycled from Bangkok to China. I have always envied about joining them on their adventures and finally decided to go to Chiang Mai with 5 friends on a 5 day cycling trip. Why Chiang Mai, well, it's supposed to be the mountain bike heaven with the mountains and hilly terrain. Well, if all goes well, this may be the first of many more overseas cycling expedition to come.
I have done a rough itinerary for the 5 days but since this is a free and easy trip, we might change the plan as the days go by. Hope we can do as much cycling as we possibly can for the next 5 days.
Chiang Mai, here we come!
SundayAfter checking in hotel and setting up our bikes.
i. Visit an ancient temple, Wat Prasing
ii. Visit another temple which is also a museum, Wat Ket Karam Museum
iii. Visit Tribal Museum
i. Cycle towards Hmong Village, distance 21km. Along the way, visit Umbrella Village and another temple Wat Phra Doi Suthep which is side by side.
ii. Have lunch or bring packed food along and eat at Hmong Village.
ii. After lunch and going around the Hmong Village, we start off road (Yippee!) Smuggler's Trail. 20km of downhill and pure XC trails towards Huai Tueng Thao Reservoir.
Then it's cycling back 13.5km on road to our hotel. This should take all day and estimate to finish around evening. Total cycling distance about 60km.
iv. Cycle and look for good makan and then do some night cycling around town.
Plan A (if we are going to spend all the time cycling and exploring around Chiang Mai town)
i. Cycle north along the river and do a loop coming back on the other side. Distance 60km.
ii. Check out the local bike shops.
iii. Free and easy after dinner. Maybe do some more night cycling.
Plan B (if we are going full cycling expedition)
i. Wake up early for breakfast.
ii. Cycle up north to Chiang Dao town. Distance 71km. All on road.
iii. Stay for the night.
iv. From Chiang Dao, cycle a bit more north and then turn East towards a small town called Phrao. Distance 42km.
v. Eat light lunch at Phrao (if can find because it is a very small town), then continue cycle East for another 24km. From my GPS map, the road looks interesting because of lots of zigzag. Hopefully going downhill!
vi. Cycle into off road trail. From the GPS map, it says 4x4 mountain track. Distance before we reach tarmac road. 61km! I have to highlight the distance because we would have cycled 85km already by now and there is still another 64km before we reach Chiang Mai town again. Total estimate distance would be 150km for the day.
Plan A (continue from Tuesday Plan A)
i. Cycle East 1 big loop. Distance 100km.
ii. or Cycle South and do a loop back.
iii. Finish early and relax the for the day.
iv. Maybe go to Night Baazar to see if there is anything interesting.
i. Shopping and pack bicycles.
ii. Arrange for transport to airport.
iii. Bye-bye Chiang Mai.
Tuesday, January 31, 2012
Of Mtb Jamborees and Races
Why? It is held in Melaka. So what's the big deal? It's organised by an event company and they are charging a really unreasonable fee of RM90. Then, the unveiling of the track, ....*drum roll*...
it's none other than our 2011 Burung Hantu track. We should be be feeling great that someone is using our trail but re-using the same trail and charging so much registration fee? Something is not right. Come on, don't you have any shame? We know you want to cari makan but not this way. Do your own reccee of the trails and better still, reduce the unreasonable registration fee.
A probe further revealed that although the event date is fixed and the starting venue is at a university, the university administrators have not received any application to use their facilities on that day. Well my fellow riders, think twice if you are thinking of taking part.
By the way, if any groups wants to cycle the Burung Hantu trail daytime on a weekend, do contact the Environment Cycling Club. I am sure they will be more than willing to lead the way.
Lately we have noticed the influx of mtb jamborees and races throughout the country. This is a good sign that shows the cycling community is growing. So much so that even if there are 2 events on the same weekend, both events can almost boast more of 1000 registrations.
The general registration fee of most event is RM50 with some exception where the organisers provide actual cycling jersey for additional RM20 - RM30. I think it is fair considering the number of manpower needed to organise and manned the events. However some clubs have seemed to have tasted the blood, so to speak and want more by charging so much more with little giving back to the participants in the form of goodies.
Last year I heard of 1 club which charged RM50 for their event and many seasoned riders felt shortchanged when the initial 40+km ride was shortened to only 37 km with mainly flats throughout the ride and made worse with a goody bag that contained 1 T-shirt and a packet of maggi mee. Ok, we also heard from new riders who showered praises of a good ride. Is it possible for future events to state "Suitable for new riders" so that we won't waste time traveling all the way and money with hotel stay?
Another thing that came to my attention is a coming event that charges RM80. It is a mtb race but why need to charge so high? There is nothing mentioned in their blog on what will be given for such an unreasonable amount of registration fee. From my understanding, the majority of us who are recreational riders will be subsidizing the prize money that professional riders will easily earn on the race day. Well, since I am not a professional rider or those that cari makan on events that has prize money, I will ride my usual playground and give a RM80 makan treat to my family.
Tuesday, November 15, 2011
Plentong Ride 13.11.11
Tommy Nelson (left) and me by the trail description
Distributing ride plates to everyone
When I was about 9 or 10 years old, my grandparents had 4 plots of paddy field. Those days we did everything by hand. Paddy saplings were planted by hand and so was the harvesting. The best time was just after harvesting, the fields still filled with water and you could play in the mud. Later during bath time, no matter how you scrub and washed with soap, you have to live with the mud smell for quite some time.
The ride at Plentong brought back memories of my childhood. Why? Because it was a muddy muddy ride. But don't be mistaken, not that it was not a pleasant ride, in fact it was a fantastic ride!
This event is held nearing year end where the monsoon season is starting and the trails are wet, slippery and muddy. There were so many river/stream crossings that I lost count. True to what I heard, the single tracks are awesome and fantastically long. Just as you exit a long single track trail, cross a road or an opening only to go into another long stretch of single track. Did I mention that we're cycling under the canopy of trees most of the time. It's a mountain bike heaven in Plentong! If only there weren't so many stream crossing. The amount of energy used up to carry the bike over a slippery bank takes up every ounce of energy that you are saving for the next phase.
When you have only 1 area to cross and there is a bee line of riders behind you, this is what happens. Everyone starts looking for alternative way to cross.
Helping Mei with the help of Tim, to repair her broken chain
I have been taking part in many jamboree & races throughout Malaysia and Plentong rates the best in my book. Toughest ride still goes to KLMBH Epic Ride in 2010.
My club riders were at the starting point early and we patiently waited at the starting arch only to be pushed back by late comers who conveniently took their place in front of us. Then a large group of riders formed their own starting point by the road beside the official one. The flag off was messy as both groups rushed into a bottle neck.
The organizers should also think of a better PA system. The speakers were placed at the wrong place (when it was working). Additional speakers pointing at the starting point would have been better. We couldn't hear clearly the announcement and naturally will not pay any attention. Electrical failure that made the PA system stop during flag off stole the thunder that everyone was expecting. A contingency plan of a loud haler would have saved the day and best of all, an air horn will do a better job than any state of the art PA system that doesn't work.
Other than the teething problems during flag off, the trail design is good. I cannot stop complimenting the single tracks that Plentong has. You guys are so lucky! The Check Point and Refuel stations are efficient and in my opinion, CP3 being the best, as the guys that manned it, brought the meaning of Check Point management to a higher level. They were enthusiastic, cheerful, helpful and welcomed every rider as if you are the Champion. As I was refueling my water bottle and had a banana, 1 guy will spray chain oil that my chains are crying for and one of them even quipped that massage is available. You guys rock!The next few photos are dedicated to the guys of CP3. Never before a check point deserves so much write up.
Click on this link to see them in action
I wish the organizers would have put in more effort on the river and stream crossing. With so many participants taking part, it would have been helpful to put logs for us to walk across rather than making us go in. Maybe shave the banks to make it easier to go in and out. Last but not least, if all is not possible, put a rope where we can pull ourselves out of the river/stream banks. I heard a rider getting angry for missing the cutoff time as he wanted to finish the ride but was held up at most of the obstacles.
Overall, I would think the organizers did a good job. Minor hiccups are bound to happen and any complains or grouses should be looked into and taken as a lesson for improvement. Whatever it is, PLEASE organize another one next year. I am now a staunch supporter.
Note of thanks to the friends photos that I got from facebook.


text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection – DMA Arbiter – Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) – Interrupt Controller with 5 External Inputs – General Purpose Interface (GPI) – Dual UART Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes Fully Static Design Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs Operating Range: 4.5V to 5.5V(1) -55°C to +125°C Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019 SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case) No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm 2 Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540 Package: 256 MQFPF; Bare Die Note: Rad-Hard 32-bit SPARC Embedded Processor TSC695F 1. For 3.3V capability see the TSC695FL datasheet on the Atmel site. Description The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications. The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300 KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface. Rev. 4118J–AERO–08/04 Block Diagram Figure 1. TSC695F Block Diagram 32-bit Integer Unit TAP 32/64-bit Floating-Point Unit Parity Gen./Chk. Clock & Parity Reset Managt Gen./Chk. Error Managt General Purpose Timer Real Time Clock Timer General Purpose Interface UART B UART A GPI bits RxD, TxD Pin Descriptions Watch Dog Interrupt Controller DMA Arbiter DMA Ctrl Access Controller Mem Ctrl Wait State Controller Ready/Busy Address Interface Add.+Size+ASI EDAC Data+Check bits Parity Gen./Check. Parities Interrupts For pin assignment, refer to package section. Table 1. Pin Descriptions Signal Type Active Description RA[31:0] I/O, RAPAR I/O RASI[3:0] I/O 4-bit registered address space identifier - RSIZE[1:0] I/O 2-bit registered bus transaction size - RASPAR I/O High Registered ASI and SIZE parity - CPAR I/O High Control bus parity - D[31:0] I/O 32-bit data bus - High 32-bit registered address bus Output buffer: 400 pF Registered address bus parity - CB[6:0] I/O DPAR I/O High 7-bit check-bit bus - Data bus parity - RLDSTO I/O High Registered atomic load-store - ALE O Low Address latch enable - DXFER I/O High Data transfer - LOCK I/O High Bus lock - RD I/O High Read access - WE I/O Low Write enable - WRT I/O High Advanced write MHOLD+FHOLD +BHOLD+FCCV MHOLD O Low Memory bus hold MDS O Low Memory data strobe - MEXC O Low Memory exception - PROM8 I Low Select 8-bit wide PROM - BA[1:0] O Latched address used for 8-bit wide boot PROM - ROMCS O Low PROM chip select ROMWRT I Low ROM write enable MEMCS[9:0] O Low Memory chip select Output buffer: 400 pF MEMWR O Low Memory write strobe Output buffer: 400 pF 2 - TSC695F 4118J–AERO–08/04 TSC695F Table 1. Pin Descriptions (Continued) Signal Type Active Description OE O Low Memory output enable BUFFEN O Low Data buffer enable Output buffer: 400 pF - DDIR O High Data buffer direction - DDIR O Low Data buffer direction - IOSEL[3:0] O Low I/O chip select - IOWR O Low I/O and exchange memory write strobe - EXMCS O Low Exchange memory chip select - BUSRDY I Low Bus ready - BUSERR I Low Bus error - DMAREQ I Low DMA request - DMAGNT O Low DMA grant - DMAAS I High DMA address strobe - DRDY O Low Data ready during DMA access - IUERR O Low IU error CPUHALT O Low Processor (IU & FPU) halt and freeze - SYSERR O Low System error - SYSHALT I Low System halt - SYSAV O High System availability - NOPAR I Low No parity - INULL O High Integer unit nullify cycle INST O High Instruction fetch FPU instruction flush FLUSH O High DIA O High Delay instruction annulled RTC O High Real Time Clock Counter output Used to check the execute stage of IU instruction pipeline - RxA/RxB I Receive data UART 'A' and 'B' TxA/TxB O Transmit data UART 'A' and 'B' GPI[7:0] I/O GPI input/output GPIINT O EXTINT[4:0] I EXTINTACK O High External interrupt acknowledge - IWDE I High Internal watch dog enable - EWDINT I High External watch dog input interrupt WDCLK I Watch dog clock - CLK2 I Double frequency clock - SYSCLK O System clock - RESET O Low Output reset SYSRESET I Low System input reset Input trigger Factory test mode Functional mode=00 High Software debug mode - Test (JTAG) clock - Test (JTAG) reset pull-up ≈ 37 kΩ High GPI interrupt External interrupt Input trigger Input trigger Input trigger Input trigger - TMODE[1:0] I DEBUG I TCK I TRST I TMS I Test (JTAG) mode select pull-up ≈ 37 kΩ TDI I Test (JTAG) data input pull-up ≈ 37 kΩ TDO O Low Test (JTAG) data output - VCCI/VSSI Main internal power - VCCO/VSSO Output driver power - Note: If not specified, the output buffer type is 150 pF, the input buffer type is TTL. 3 4118J–AERO–08/04 System Architecture The TSC695F is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. All other system support functions are provided by the core. Figure 2. System Architecture Based on TSC695F DMA Unit Boot PROM Ax[31:0] Xtd PROM Master Xchg Mem Glue Logic Local Memory Xtd RAM I/O 0 to I/O 3 DMAGNT DMAREQ DMAAS DPAR (BUFFEN, DDIR) CB[6:0] Xtd I/O (ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...) Xtd general RA[31:0] MEMCtrl Memory Interface FPU RAMCtrl DMA A[31:0] IU DMA Peripherals RAM Memory D[31:0] SYSCLK ALE (MEMCS[9:0], MEMWR, OE) (0 WS) User Application TSC695F 4 TSC695F 4118J–AERO–08/04 TSC695F Product Description Integer Unit The Integer Unit (IU) is designed for highly dependable space and military applications, and includes support for error detection. The RISC architecture makes the creation of a processor that can execute instructions at a rate approaching one instruction per processor clock possible. To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. • Fetch - The processor outputs the instruction address to fetch the instruction. • Decode - The instruction is placed in the instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address. • Execute - The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage. • Write - If no trap is taken, the processor writes the result to the destination register. All four stages operate in parallel, working on up to four different instructions at a time. A basic 'single-cycle' instruction enters the pipeline and completes infour cycles. By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of course, a 'single-cycle' instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can complete one instruction per cycle after the initial four-cycle delay. Floating-point Unit The FLoating Point Unit (FPU) is designed to provide execution of single and doubleprecision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard. The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address buses. The decode unit contains logic to decode the floatingpoint instruction opcodes. The execution unit handles all instruction execution. The execution unit includes a floating-point queue (FP queue), which contains stored floatingpoint operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floating-point loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU. The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address. 5 4118J–AERO–08/04 Instruction Set TSC695F instructions fall into six functional categories: load/store, arithmetic/logical/shift, control transfer, read/write control register, floating-point, and miscellaneous. Please refer to SPARC V7 Instruction-set Manual. Note: The execution of IFLUSH will cause an illegal instruction trap. On-chip Peripherals Memory Interface The TSC695F is designed to allow easy interfacing to internal/external memory resources. Table 2. Memory Mapping Memory Contents Boot PROM Extended PROM Start Address 0x 0000 0000 0x 0100 0000 Size (bytes) 128K → 16M Max: 15M Data Size and Parity Options 8-bit mode No parity/-No EDAC/-Only byte write 40-bit mode Parity + EDAC mandatory/-Only word write 8-bit mode No parity/-No EDAC/-Only byte write 40-bit mode Parity + EDAC mandatory/-Only word write Exchange Memory 0x 01F0 0000 4k → 512k Parity + EDAC option/-Only word write System Registers 0x 01F8 0000 512K (124 used) Parity/-Only word read/write access RAM (8 blocks) 0x 0200 0000 8*32K → 8*4M Parity + EDAC option/-All data sizes allowed Extended RAM 0x 0400 0000 Max: 192M I/O Area 0 0x 1000 0000 0 → 16M I/O Area 1 0x 1100 0000 0 → 16M I/O Area 2 0x 1200 0000 0 → 16M I/O Area 3 0x 1300 0000 0 → 16M Extended I/O Area 0x 1400 0000 Max: 1728M Extended General 0x 8000 0000 Max: 2G System Registers Parity option/-All data sizes allowed No parity/-All data sizes allowed The system registers are only writable by IU in the supervisor mode or by DMA during halt mode. Table 3. System Registers Address Map System Register Name 6 Address System Control Register SYSCTR 0x 01F8 0000 Software Reset SWRST 0x 01F8 0004 Power Down PDOWN 0x 01F8 0008 System Fault Status Register SYSFSR 0x 01F8 00A0 Failing Address Register FAILAR 0x 01F8 00A4 Error & Reset Status Register ERRRSR 0x 01F8 00B0 Test Control Register TESCTR 0x 01F8 00D0 TSC695F 4118J–AERO–08/04 TSC695F Table 3. System Registers Address Map (Continued) System Register Name Wait-state and Time-out Generator Address Memory Configuration Register MCNFR 0x 01F8 0010 I/O Configuration Register IOCNFR 0x 01F8 0014 Waitstate Configuration Register WSCNFR 0x 01F8 0018 Access Protection Segment 1 Base Register APS1BR 0x 01F8 0020 Access Protection Segment 1 End Register APS1ER 0x 01F8 0024 Access Protection Segment 2 Base Register APS2BR 0x 01F8 0028 Access Protection Segment 2 End Register APS2ER 0x 01F8 002C Interrupt Shape Register INTSHR 0x 01F8 0044 Interrupt Pending Register INTPDR 0x 01F8 0048 Interrupt Mask Register INTMKR 0x 01F8 004C Interrupt Clear Register INTCLR 0x 01F8 0050 Interrupt Force Register INTFCR 0x 01F8 0054 Watchdog Timer Register WDOGTR 0x 01F8 0060 Watchdog Timer Trap Door Set WDOGST 0x 01F8 0064 Real Time Clock Timer <Counter> Register RTCCR 0x 01F8 0080 Real Time Clock Timer <Scaler> Register RTCSR 0x 01F8 0084 General Purpose Timer <Counter> Register GPTCR 0x 01F8 0088 General Purpose Timer <Scaler> Register GPTSR 0x 01F8 008C Timers Control Register TIMCTR 0x 01F8 0098 General Purpose Interface Configuration Register GPICNFR 0x 01F8 00A8 General Purpose Interface Data Register GPIDATR 0x 01F8 00AC UART 'A' Rx & Tx Register UARTAR 0x 01F8 00E0 UART 'B' Rx & Tx Register UARTBR 0x 01F8 00E4 UART Status Register UARTSR 0x 01F8 00E8 It is possible to control the wait-state generation by programming a Wait-state Configuration Register. The maximum programmable number of wait-states is applied by default at reset. It is possible to program the number of wait-states for the following combinations: – RAM read and write – PROM read and write (i.e. EEPROM or Flash write) – Exchange Memory read/write – Four individual I/O peripherals read/write A bus time-out function of 256 system clock cycles is provided for the bus ready controlled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM, 7 4118J–AERO–08/04 Extended I/O and the Extended General areas. EDAC The TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR) is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled. The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-atone and stuck-at-zero failure for any nibble in the data word as a non-correctable error. Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a noncorrectable error. Memory and I/O Parity The TSC695F handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only parity or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR. Memory Redundancy Programming the Memory Configuration Register, the TSC695F provides chip selects for two redundant memory banks for replacement of faulty banks. Memory Access Protection • Unimplemented Areas - Access to all unimplemented memory areas are handled by the TSC695F and detected as illegal. • RAM Write Access Protection - The TSC695F can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments. • Boot PROM Write Protection - The TSC695F supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM. DMA DMA Interface The TSC695F supports Direct Memory Access (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power-down mode the processor is permanent tri-stated, and a DMAREQ will directly give a DMAGNT. The TSC695F includes a DMA session time-out function. Bus Arbiter The TSC695F always has the lowest priority on the system bus. Traps A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear. 8 TSC695F 4118J–AERO–08/04 TSC695F Synchronous Traps Table 4. Synchronous Traps Trap Priority Reset 1 Trap Type (tt) Comments – Sources: SYSRESET* pin software reset watchdog reset IU or System error reset 2.1 64h Severe error requiring a re-boot TSC695F enters (if not masked) in halt or reset mode Non-restartable, precise error 2.2 62h Error not removable, PC & nPC OK TSC695F enters (if not masked) in halt or reset mode Register file error 2.3 65h Special case of non-restartable, precise error. TSC695F enters (if not masked) in halt or reset mode Restartable, late error 2.4 63h Retrying instruction but PC & nPC have to be re-adjusted TSC695F enters (if not masked) in halt or reset mode 2.5 61h Retrying instruction TSC695F enters (if not masked) in halt or reset mode 3 01h Parity error on control bus Parity error on data bus Parity error on address bus Access to protected or unimplemented area Uncorrectable error in memory Bus time out Bus error Illegal Instruction 4 02h – Privileged instruction 5 03h – FPU disabled 6 04h – 05h During SAVE instruction or trap taken 7 06h During RESTORE instruction or RETT instruction 8 07h – Hardware Error Non-restartable, imprecise error Restartable, precise error 2 Instruction access (Error on instruction fetch) Overflow Window Underflow FPU exception Memory address not aligned Non-restartable error 9.1 Severe error, cannot restart the instruction Data bus error 9.2 Parity error on FPU data bus Restartable error 9.3 Can be removed restarting the instruction Sequence error 9.4 – Unimplemented FPop 9.5 – 9.6 Invalid operation Division by zero Overflow Underflow Inexact IEEE exceptions: 9 08h 9 4118J–AERO–08/04 Table 4. Synchronous Traps (Continued) Trap Priority Trap Type (tt) Comments Data access exception (Error on data load) 10 09h Idem "instruction access" System register access violation Tag overflow 11 0Ah TADDccTV and TSUBccTV instructions Trap instructions 12 80h to FFh Trap on integer condition codes (Ticc) Table 5. Interrupts or Asynchronous Traps Trap Priority Trap Type (tt) Comments Watchdog time-out 13 1Fh Internal or external (EWDINT pin) External INT 4 14 1Eh EXTINTAK on only one of EXTINT[4:0] Real time clock timer 15 1Dh – General purpose timer 16 1Ch – External INT 3 17 1Bh EXTINTAK on only one of EXTINT[4:0] External INT 2 18 1Ah EXTINTAK on only one of EXTINT[4:0] DMA time-out 19 19h – DMA access error 20 18h – UART Error 21 17h – Correctable error in memory 22 16h Data read OK but source not updated – UART B Data ready Transmitter ready 23 15h UART A Data ready Transmitter ready 24 14h External INT 1 25 13h EXTINTAK on only one of EXTINT[4:0] External INT 0 26 12h EXTINTAK on only one of EXTINT[4:0] 11h Logical OR of: IU hardware error masked IU error mode masked System hardware error masked Masked hardware errors – 27 It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register are cleared automatically when the interrupt is acknowledged. By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active high and to define the external interrupts to either be edge or level sensitive. 10 TSC695F 4118J–AERO–08/04 TSC695F Timers In software debug mode the timers are controlled by a system register bit and the external pin DEBUG. General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter function, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. Watchdog Timer Setting the external pin IWDE to VCC enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. Simultaneo usly, the timer starts counting a reset time -out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695F. UARTs Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART's are controlled by system register bits. The data format of the UART's is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART's provide double buffering, i.e. each UART consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART's generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART's is programmable. The clock is derived either from the system clock or can use the watchdog clock. General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be configured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input transition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution Modes Reset Mode Reset mode is entered when: – The SYSRES input is asserted – Software reset which is caused by the software writing to a Software Reset Register – Watchdog reset which is caused by a Watchdog counter time-out – Error reset which is caused by a hardware parity error 11 4118J–AERO–08/04 This RESET output has a minimum of 1024 SYSCLK width to allow the usage of Flash memories. The error and Reset Status Register contain the source of the last processor reset. Run Mode In this mode the IU/FPU is executing, while all peripherals are running (if software enabled). System Halt Mode System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU and FPU are frozen, while the timers (includeing the internal watchdog timer) and UART's are stopped. Power Down Mode This mode is entered by writing to the Power-down Register. In this mode, the IU and FPU are frozen. The TSC695F leaves the power-down mode if an external interrupt is asserted. Error Halt Mode Error Halt mode is entered under the following circumstances: – A internal hardware parity error. – The IU enters error mode. The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET. Error Handler The TSC695F has one error output signal (SYSERR) which indicates that an unmasked error has occurred. Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register. By default, an error leads to a processor halt. Parity Checking The TSC695F includes: – Parity checking and generation (if required) on the external data bus – Parity checking on the external address bus – Parity checking on ASI and SIZE – Parity checking and generation on all system registers – Parity generation and checking on the internal control bus to the IU All external parity checking can be disabled using the NOPAR signal. System Clock The TSC695F uses CLK2 clock input directly and creates a system clock signal by dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the application. It is highly recommended that only SYSCLK rising edge is used as reference as far as possible. System Availability The SYSAV bit in the Error and Reset Status Register can be used by software to indicate system availability. Test Mode The TSC695F includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register. 12 TSC695F 4118J–AERO–08/04 TSC695F Test and Diagnostic Hardware Functions A variety of TSC695F test and diagnostic hardware functions, including boundary scan, internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). Test Access Port The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These pins are: Instruction Register Debugging • TCK (input): Test Clock • TMS (input): Test Mode Select • TDI (input): Test Data Input • TDO (output): Test Data Output • TRST (input): Test Reset Five standard instructions are supported by the TSC695F TAP. Binary Value Name of Instruction Data Register Scan Chain Accessed 00. 0000 EXTEST Boundary Scan Register Boundary scan chain 00. 0001 SAMPLE/PRELOAD Boundary Scan Register Boundary scan chain 00. 0011 INTEST Boundary Scan Register Boundary scan chain 11. 1111 BYPASS Bypass Register Bypass register 10. 0000 IDCODE Device ID Register ID register scan chain The design is highly testable with the support of an On-Chip Debugger (OCD), an internal and boundary scan through JTAG interface. 13 4118J–AERO–08/04 Electrical Characteristics Absolute Maximum Ratings Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Military Range............................................... -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Supply Voltage................................................... -0.5V to +7.0V Input Voltage......................................................-0.5V to +7.0V DC Characteristics Table 6. DC Characteristics at VDD 5V ± 10% Symbol Parameter Min Typ Max Unit Test Conditions VIL trigger Input Low Voltage for trigger input – – 0.8 V VCC = 4.5 to 5.5V VIH trigger Input High Voltage for trigger input 3.0 – – V VCC = 4.5 to 5.5V Input Hysteresis for trigger input – 0.9 – V VCC = 4.5 to 5.5V TTL Input Low Voltage for TTL input – – 0.8 V VCC = 4.5 to 5.5V VIH TTL Input High Voltage for TTL input 2.2 – – V VCC = 4.5 to 5.5V VOL400 pF Output Low Voltage for 400 pF buffer – 0.3 0.4 V VCC = 4.5 to 5.5V IOL = 12 mA VOH 400 pF Output High Voltage for 400 pF buffer 2.4 0.3 – V VCC = 4.5 to 5.5V IOH = -16 mA VOL150 pF Output Low Voltage for 150 pF buffer – 0.3 0.4 V VCC = 4.5 to 5.5V IOL = 4 mA VOH 150 pF Output High Voltage for 150 pF buffer 2.4 4.3 – V VCC = 4.5 to 5.5V IOH = -6 mA – – 230 Icc OP Operating Supply Current for core processor – – 210 – – 170 VCC = 5.5V, f = 10 MHz – – 41 VCC = 5.5V, f = 25MHz – – 38 – – 30 ∆VT VIL IccPD 14 Power Down Supply Current for core processor VCC = 5.5V, f = 25 MHz mA mA VCC = 5.5V, f = 20 MHz VCC = 5.5V, f = 20 MHz VCC = 5.5V, f = 10 MHz TSC695F 4118J–AERO–08/04 TSC695F Capacitance Ratings Parameter Description Max CIN Input Capacitance 7 pF COUT Output Capacitance 8 pF CIO Input/Output Capacitance 8 pF AC Characteristics Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V Parameter Min (ns) Max (ns) t1 20 t2 Comment Reference Edge – CLK2 period – 40 – SYSCLK period – t3 9.75 – CLK2 high and low pulse width – t4 – 6.5 RA(31:0) RAPAR RSIZE RLDSTO output delay SYSCLK+ t5 – 12.5 MEMCS*(9:0) ROMCS* EXMCS* output delay SYSCLK+ t6 – 15 DDIR DDIR* output delay SYSCLK+ t7 – 23.5 MEMWR* IOWR*output delay formula: 13.5 ns + 1/4 t2 SYSCLK- or SYSCLK+ t8 – 20.5 OE* HL output delay formula: 10.5 ns + 1/4 t2 SYSCLK+ t9_1 11.5 – Data setup time during load SYSCLK+ t9_2 9 – Data setup time during load NOPAR = 0 rpa = rec = either 1 or 0 SYSCLK+ t10 5 – Data hold time during load SYSCLK+ t11 – 28 Data output delay SYSCLK- t12 8 – Data output valid to HZ – guaranteed by design SYSCLK+ t13 – 19 CB output delay SYSCLK+ t14 – 13 ALE* output delay SYSCLK- t15 – 21 BUFFEN* HL output delay formula: 11 ns + 1/4 t2 SYSCLK+ t16 – 15 MHOLD* output delay – guaranteed by design SYSCLK+ t17 – 15 MDS* DRDY* output delay SYSCLK+ t20 – 15 MEXC* output delay SYSCLK- t21 10 – RASI(3:0) RSIZE(1:0) RASPAR setup time SYSCLK+ t22 3 – RASI(3:0) RSIZE(1:0) RASPAR hold time SYSCLK+ t23 – 13 BOOT PROM address output delay SYSCLK+ t9 15 4118J–AERO–08/04 Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V (Continued) 16 Parameter Min (ns) Max (ns) t24 12 t25 Comment Reference Edge – BUSRDY* setup time SYSCLK+ 0 – BUSRDY* hold time SYSCLK+ t27 – 15 IOSEL output delay SYSCLK+ HL SYSCLK- LH t28 12 20 DMAAS setup time formula of max: 1/2 t2 SYSCLK+ t29 0 20 DMAAS hold time formula of max: 1/2 t2 SYSCLK- t30 12 – DMAREQ* setup time SYSCLK+ t31 – 15 DMAGNT* output delay SYSCLK+ t32 10 – RA(31:0) RAPAR CPAR setup time SYSCLK+ t33 3 – RA(31:0) RAPAR CPAR hold time SYSCLK+ t36 100 – TCK period - t37 10 – TMS setup time TCK+ t38 4 – TMS hold time TCK+ t39 10 – TDI setup time TCK+ t40 10 – TDI hold time TCK+ t41 – 20 TDO output delay TCK- t46 – 22 INULL output delay SYSCLK+ t48 – 22 RESET* CPUHALT* output delay SYSCLK+ t49 – 20 SYSERR* SYSAV output delay SYSCLK+ t50 – 20 IUERR* output delay SYSCLK+ t52 12 – EXTINT(4:0) setup time SYSCLK- t53 0 – EXTINT(4:0) hold time SYSCLK+ t54 – 15 EXTINTACK output delay SYSCLK+ t56 – 8.5 OE* LH output delay (no DMA mode) SYSCLK+ t57 – 9 BUFFEN* LH output delay SYSCLK+ t60 – 22 INST output delay SYSCLK+ t61 20 – Data output delay to low-Z – guaranteed by design formula: 10 ns + 1/4 t2 SYSCLK+ t80 12 t81 0 64 BUSERR* setup time SYSCLK+ BUSERR* hold time formula: 24 ns + t2 SYSCLK+ TSC695F 4118J–AERO–08/04 Figure 3. 150 pF Buffer Response (Data from simulation) 17 TSC695F 4118J–AERO–08/04 Figure 4. 400 pF Buffer Response (Data from simulation) 18 TSC695F 4118J–AERO–08/04 TSC695F Figure 5. OE*/400 pF Buffer Response (Data from simulation) 19 4118J–AERO–08/04 20 MDS* MHOLD* t17 FC1 CB [6:0] t60 FP1 DPAR INST FD1 t14 FA1 n ws D [31:0] OE* BUFFEN* MEMWR* DDIR ROMCS* MEMCS* [1] MEMCS* [0] ALE RA [31:0] SYSCLK CLK2 1 (RAM fetch) t14 t1 t8 t17 t4_1 t60 LP1 t17 t16 LC1 t9 t9 LD1 t9 LA1 n ws 2 (RAM load) t10 t10 t10 t17 t16 t56 t4_1 t2 t60 FA2 t17 FC2 FP2 FD2 n ws 3 (RAM fetch) t3 t11 t61 t7 SA1 t17 previous stored checkbyte t61 previous stored parity t11 t61 previous stored data t56 t6 t5 t5 t4_1 t13 m ws 4 (RAM store) SC1 SP1 SD1 t7 t3 t60 t12 t12 t12 t8 t6 t5 t5 t4_1 t17 FC3 FP3 FD3 FA3 n ws 5 (RAM fetch) Timing Diagrams Figure 6. RAM Fetch, RAM Load and RAM Store Sequence - n Waitstates for Read, m Waitstates for Write TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 FC1 CB [6:0] t4_2 FP1 DPAR LOCK RLDSTO INULL MDS* MHOLD* INST FD1 FA1 D [31:0] OE* BUFFEN* MEMWR* DDIR MEMCS* [1] MEMCS* [0] ALE* RA [31:0] SYSCLK 1 (RAM fetch) t8 t4_1 t60 t5 t5 t4_1 t56 t10 t10 t4_2 checkbyte from RAM t9 parity from RAM t9 byte from RAM t9 t10 t6 t2 t46 t16 t10 t61 checkbyte from RAM parity from RAM t10 t61 t9 t9 t56 t10 t61 t6 word from RAM t9 held to update the full word t8 t6 ALSA 2 (RAM atomic load store) t11 t11 t7 t16 checkbyte to RAM t13 parity to RAM word to RAM t7 t4_1 t46 t60 t12 t12 t12 t8 t6 t5 t5 t4_1 FC5 FP5 FD5 FA5 3 (RAM fetch) TSC695F Figure 7. RAM "Atomic-load-store" byte Sequence - 0 Waitstate 21 22 LOCK INULL MDS* MHOLD* INST CB [6:0] DPAR D [31:0] OE* BUFFEN* MEMWR* DDIR MEMCS* [1] MEMCS* [0] ALE* RA [31:0] SYSCLK FA1 1 (RAM fetch) FC1 FP1 FD1 t4_2 t60 t8 t5 t5 t4_1 LA1 t2 t9 t9 t9 LC1 LP1 LD1 t56 t4_1 2 (RAM double load) LA2 LC2 t4_2 t10 LP2 t10 LD2 t10 t8 t5 t5 t4_1 FA2 3 (RAM fetch) FC2 FP2 FD2 t56 t61 t61 t61 t6 t5 t5 t4_1 t11 t11 t7 t46 t13 SA1 t7 t16 t46 SC1 SP1 SD1 t4_1 4 (RAM double store) t11 t11 t7 t13 SA2 t16 SC2 SP2 SD2 t7 t60 t12 t12 t12 t8 t6 t5 t5 t4_1 FA3 FC3 FP3 FD3 5 (RAM fetch) Figure 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 FP1 DPAR INULL INST MDS* MEXC* MHOLD* FC1 CB[6-0] t9 FD1 FA1 D[31-0] BUFFEN* OE* IOWR* MEMWR* DDIR MEMCS*[1] MEMCS*[0] RA[31-0] ALE* SYSCLK 1 (RAM fetch) t8 t60 t10 t5 t5 t4_1 LA1 t9 LC1 t10 LD1 t5 t5 t56 t4_1 t16 t60 t14 t17 FP2 FC2 FD2 t56 internal error correction 2 (RAM load correctable data) LP1 1-bit error on 40-bit data load t8 t17 t16 made inside data correction FA2 t14 t2 3 (RAM fetch) FP2 FC2 FD2 t4_1 FA3 4 (RAM fetch) FP3 FC3 FD3 TSC695F Figure 9. RAM Load with Correctable Error - 0 Waitstate 23 24 FP1 DPAR INULL INST MDS* MEXC* MHOLD* FC1 CB[6-0] t8 t9 LC1 LD1 t10 t5 t5 t56 t4_1 t60 t16 FP2 FC2 FD2 t14 internal error detection 2 (RAM load) LP1 2-bit error on 40-bit data LD1 load t4_1 t60 t5 t5 FD1 FA1 D[31-0] BUFFEN* OE* IOWR* MEMWR* DDIR MEMCS*[1] MEMCS*[0] RA[31-0] ALE* SYSCLK 1 (RAM fetch) t17 FA2 t20 FP2 FC2 FD2 t14 t8 t17 t16 exception 3 (RAM fetch) t9 t20 FP2 FC2 FD2 t46 t60 t10 t56 t4_1 t2 FA3 4 (null cycle) FP3 FC3 FD3 t46 t60 t4_1 TA1 5 (RAM fetch) TP1 TC1 TA2 TP2 TC2 TD2 6 (RAM fetch) TD1 trap Figure 10. RAM Load with Uncorrectable Error - 0 Waitstate TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 INULL INST MDS* MEXC* MHOLD* D[31-0] OE* BUFFEN* IOWR* MEMWR* DDIR MEMCS*[1] MEMCS*[0] RA[31-0] ALE* SYSCLK t2 FA1 t9 1 (RAM fetch) t60 t10 FD1 t5 t60 t16 t56 t17 no data t5 t20 t17 t8 FA2 3 (RAM fetch) internal error unimplemented address LA1 2 (RAM load) t16 t20 fetch t9 t46 t60 t10 FD2 t8 t4_1 FA3 4 (null cycle) FD3 t46 t60 t56 t4_1 TA1 5 (RAM fetch) TD1 trap TA2 TD2 6 (RAM fetch) TSC695F Figure 11. RAM Load with Unimplemented Area Access - 0 Waitstate 25 26 MDS* MHOLD* INST D[31-0] OE* BUFFEN* IOWR* MEMWR* DDIR BUSRDY* IOSEL*[0] MEMCS*[0] RA[31-0] ALE* SYSCLK t4_1 FA1 t9 1 (RAM fetch) FD1 t60 t10 t61 t56 t15 t6 t5 t4_1 start of cycle t11 t7 t16 previous stored data t27 t2 (n-1) ws t24 SA1 rdy waiting 2 (i/o store) t24 SD1 t25 t7 end of cycle t16 t27 t57 t60 t12 t8 t6 t5 t4_1 FA2 FD2 3 (RAM fetch) Figure 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates) TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 MDS* MHOLD* INST D[31-0] OE* BUFFEN* IOWR* MEMWR* DDIR BUSRDY* IOSEL*[0] MEMCS*[0] RA[31-0] ALE* SYSCLK t56 FA1 t9 1 (RAM fetch) FD1 t60 t10 t8 t15 t5 t4_1 start of cycle t27 t24 t16 t60 data driven by external buffers (c.f BUFFEN*) t14 t2 (n-1) ws LA1 t24 rdy waiting 2 (i/o load) t25 LD1 t17 t9 t56 t17 t57 t10 end of cycle t27 t14 t5 t8 FA2 t16 t4_1 FD2 3 (RAM fetch) TSC695F Figure 13. I/O Load Sequence with BUSRDY* and n Waitstates (Timing for 0 ws = Timing for 1 ws) 27 28 MDS* MHOLD* INST D[31-0] BUSRDY* OE* BUFFEN* IOWR* MEMWR* DDIR EXMCS* MEMCS*[0] RA[31-0] ALE* SYSCLK FA1 1 (RAM fetch) FD1 t60 t61 t56 t15 t6 t5 t5 t4_1 start of cycle t16 t24 SA1 previous stored data t2 t24 t25 in between 2 (xchgRAM store) rdy waiting t11 t7 t7 n ws t24 SD1 t25 t7 t16 t7 end of cycle t57 t60 t12 t8 t6 t5 t5 t4_1 FA2 FD2 3 (RAM fetch) Figure 14. EXCHANGE RAM Store with BUSDRY* and n Waitstates TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 MDS* MHOLD* INST D[31-0] BUSRDY* OE* BUFFEN* IOWR* MEMWR* DDIR EXMCS* MEMCS*[0] RA[31-0] ALE* SYSCLK FA1 1 (RAM fetch) FD1 t60 t56 t15 t5 t5 t4_1 t14 t2 t16 t60 start of cycle t24 t25 n ws t24 data driven by external buffers (c.f BUFFEN*) t24 LA1 rdy waiting 2 (xchgRAM load) t17 t25 t9 t14 LD1 end of cycle t8 t17 FA2 t16 t57 t10 t5 t5 t4_1 FD2 3 (RAM fetch) TSC695F Figure 15. EXCHANGE RAM Load with BUSDRY* and n Waitstates 29 30 MDS* MHOLD* INST D[7-0] D[31-8] OE* BUFFEN* MEMWR* DDIR MEMCS*[0] ROMCS* BA[0,1] RA[31-0] RSIZE[0,1] ALE* SYSCLK FA1 1 (ROM fetch) t8 t17 t60 t15 t16 t5 t4_1 t4_1 start of cycle t14 t16 t5 0 t23 1 FA2 byte 1 (n-1) ws t23 10 t2 t9 (1 = fetch, FD2-0 t10 0 = load word) t9 FD2-1 t10 2 byte 2 (n-1) ws 2 (8-bit ROM fetch or load word) data driven by external buffers (c.f BUFFEN*) byte 0 (n-1) ws t9 3 t10 FD2-2 t23 (address mod. 4) byte 3 (n-1) ws t10 t9 FD2-3 t4 0 t17 t56 t57 t23 end of cycle t8 t17 t60 t15 FA2 t16 t5 t4_1 t4_1 3 (ROM fetch) Figure 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 MDS* MHOLD* INST D[31-0] OE* BUFFEN* IOWR* MEMWR* DDIR ROMCS* MEMCS*[0] RSIZE[0,1] BA[0,1] RA[31-0] ALE* SYSCLK 10 t9 FA1 start of cycle t60 t56 t15 t61 t6 t5 t4_1 t4_1 FD1 1 (RAM fetch) t16 t5 SA1 t11 t7 00 00 (n-1) ws 2 (8-bit ROM write) t16 byte D[7:0] SD1 t7 addr.=mod. 4 t60 t12 t8 t57 t6 t5 t5 t4_1 t4_1 t2 10 t9 FA2 3 (RAM fetch) t60 FD2 t56 t15 t61 t6 t5 t4_1 t23 t4_1 start of cycle t16 t5 SA2 t11 t7 00 01 t16 byte D[7:0] SD2 t7 addr.=mod. 4 +1 (n-1) ws 4 (8-bit ROM write) t12 t57 t6 t5 t5 t4_1 00 10 t23 t4_1 FA3 5 (RAM fetch) TSC695F Figure 17. 8-bit BOOT PROM 2x Store byte - n Waitstate 31 32 t4_1 FZ2 FS1 FZ1 RASI[3-0] RSIZE[1-0] t10 t9 FC1 DPAR CB[7-0] MHOLD* t10 t9 FP1 D[31-0] t5 t16 (pull-up on WE*) t10 t9 FD1 DDIR MEMWR* OE* DRDY* MEMCS*[9-0] WRT RD DMAAS DMAGNT* DMAREQ* t4_1 FS2 FA1 RA[31-0] t30 t4_1 FA2 ALE* SYSCLK t14 t31 t31 t31 t4_1 t4_1 t4_1 1 (RAM fetch) 2 (RAM fetch) (null cycle)lead-in t14 t33 t32 t32 t28 t33 t33 t8 t56 t17 t17 t14 t28 t32 t33 t33 t22 t6 t5 t7 t29 t21 10 (only word access) t32 t33 t7 t17 t30 t4_1 FZ2 t4_1 FS2 t4_1 FA2 FZ3 FS3 FA3 4 (RAM fetch) 5 (RAM fetch) cont' t17 t31 t31 t31 t8 t6 t5 t56 t5 early time for DMAREQ* desassertion D SAn (held to the end of RAM access) t22 t21 D SSn t32 lead-out t10 t10 t11 t12 t9 t9 t10 t9 D LD1 D LD1 FD2 D SDn (from RAM) (from TSC695F) (held to the end of RAM access) t10 t10 t11 t12 t13 t13 t9 t9 D LP1 D LP1 FP2 DSPn (from RAM) Parity generated by TSC695F if dpe =1, (from TSC695F) else, same timing as D[31-0] t10 t10 corrected parity if needed t13 t13 t9 t9 D LC1 FC2 D SCn (from RAM) t16 corrected data if needed t5 t29 t21 10 (only word access) t22 D LA1 (held to the end of RAM access) t22 t21 D LS1 t32 t14 t2 3 (DMA session) (0 cycle min) 1st DMA load (0 ws) (0 cycle min) nth DMA store (0 ws) Figure 18. DMA RAM load with or without Correctable Error and DMA RAM Store - 0 Waitstates TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 EXTINTACK EXTINT[i] INULL D[31:0] ALE* RA[31:0] SYSCLK t52 FD(-1) FA(-1) t53 FD0 FA0 FD1 FA1 Sampled FD2 FA2 Latched FD3 FA3 Prioritized FD4 FA4 Taken t54 TD0 TTA0 t54 TD1 TTA1 TSD0 TSA0 TSA2 TSD1 TSA1 TSC695F Figure 19. Edge Triggered Interrupt Timing 33 34 10 RSIZE[1:0] D[31:0] CPUHALT* SYSAV MHOLD* SYSHALT* FDn-1 09H RASI[3:0] ALE* FAn-1 RA[31:0] SYSCLK FDn 10 09H FAn t16 10 09H t14 FAn+1 t48 t49 t48 t49 t14 t16 FDn+1 10 09H FAn+1 FDn+2 10 09H FAn+2 Figure 20. Halt Timing TSC695F 4118J–AERO–08/04 4118J–AERO–08/04 D[31:0] CPUHALT* SYSAV MHOLD* SYSERR* IUERR* FDn-1 10 RSIZE[1:0] t50 09H RASI[3:0] ALE* FAn-1 RA[31:0] SYSCLK t50 10 09H FAn FDn t49 t16 t14 10 09H FAn+1 t48 t49 TSC695F Figure 21. External Error with Halt Timing 35 36 RESET* INULL ALE* RSIZE[1:0] RASI[3:0] RA[31:0] SYSRESET* SYSCLK FA n t46 t14 t48 FA n+1 t48 t14 t47 0H 4H 8H Figure 22. Reset Timing TSC695F 4118J–AERO–08/04 TSC695F Figure 23. External Error signaling with BUSERR* and BUSRDY* SYSCLK t24 BUSRDY* t80 t81 t80 BUSERR* t20 MEXC* 37 4118J–AERO–08/04 Package Drawings 256-lead MQFP-F Package 38 TSC695F 4118J–AERO–08/04 TSC695F 256-lead MQFP-F Pin Assignments Table 8. Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal 1 GPIINT 65 D[0] 129 RA[0] 193 DXFER 2 GPI[7] 66 RSIZE[1] 130 VCCO 194 MEXC 3 VCCO 67 RSIZE[0] 131 VSSO 195 VCCO 4 VSSO 68 RASI[3] 132 RAPAR 196 VSSO 5 GPI[6] 69 VCCO 133 RASPAR 197 RESET 6 GPI[5] 70 VSSO 134 DPAR 198 SYSRESET 7 GPI[4] 71 RASI[2] 135 VCCO 199 BA[1] 8 GPI[3] 72 RASI[1] 136 VSSO 200 BA[0] 9 VCCO 73 RASI[0] 137 SYSCLK 201 CB[6] 10 VSSO 74 RA[31] 138 TDO 202 CB[5] 11 GPI[2] 75 RA[30] 139 TRST 203 VCCO 12 GPI[1] 76 VCCO 140 TMS 204 VSSO 13 GPI[0] 77 VSSO 141 TDI 205 CB[4] 14 D[31] 78 RA[29] 142 TCK 206 CB[3] 15 D[30] 79 RA[28] 143 CLK2 207 CB[2] 16 VCCO 80 RA[27] 144 DRDY 208 CB[1] 17 VSSO 81 VCCO 145 DMAAS 209 VCCO 18 D[29] 82 VSSO 146 VCCO 210 VSSO 19 D[28] 83 RA[26] 147 VSSO 211 CB[0] 20 VCCI 84 RA[25] 148 DMAGNT 212 ALE 21 VSSI 85 RA[24] 149 EXMCS 213 VCCI 22 D[27] 86 VCCI 150 VCCI 214 VSSI 23 D[26] 87 VSSI 151 VSSI 215 PROM8 24 VCCO 88 VCCO 152 DMAREQ 216 ROMCS 25 VSSO 89 VSSO 153 BUSERR 217 MEMCS[9] 26 D[25] 90 RA[23] 154 BUSRDY 218 VCCO 27 D[24] 91 RA[22] 155 ROMWRT 219 VSSO 28 D[23] 92 RA[21] 156 NOPAR 220 MEMCS[8] 29 D[22] 93 VCCO 157 SYSHALT 221 MEMCS[7] 30 VCCO 94 VSSO 158 CPUHALT 222 MEMCS[6] 31 VSSO 95 RA[20] 159 VCCO 223 MEMCS[5] 32 D[21] 96 RA[19] 160 VSSO 224 MEMCS[4] 33 D[20] 97 RA[18] 161 SYSERR 225 MEMCS[3] 34 D[19] 98 VCCO 162 SYSAV 226 VCCO 35 D[18] 99 VSSO 163 EXTINT[4] 227 VSSO 39 4118J–AERO–08/04 Table 8. Pin Assignments (Continued) 40 Pin Signal Pin Signal Pin Signal Pin Signal 36 VCCO 100 RA[17] 164 EXTINT[3] 228 MEMCS[2] 37 VSSO 101 RA[16] 165 EXTINT[2] 229 MEMCS[1] 38 D[17] 102 RA[15] 166 EXTINT[1] 230 MEMCS[0] 39 D[16] 103 VCCO 167 EXTINT[0] 231 VCCI 40 VCCI 104 VSSO 168 VCCI 232 VSSI 41 VSSI 105 RA[14] 169 VSSI 233 OE 42 D[15] 106 VCCI 170 EXTINTACK 234 VCCO 43 D[14] 107 VSSI 171 IUERR 235 VSSO 44 VCCO 108 RA[13] 172 VCCO 236 MEMWR 45 VSSO 109 RA[12] 173 VSSO 237 BUFFEN 46 D[13] 110 VCCO 174 CPAR 238 DDIR 47 D[12] 111 VSSO 175 TXA 239 VCCO 48 D[11] 112 RA[11] 176 RXA 240 VSSO 49 D[10] 113 RA[10] 177 RXB 241 DDIR 50 VCCO 114 RA[9] 178 TXB 242 MHOLD 51 VSSO 115 VCCO 179 IOWR 243 MDS 52 D[9] 116 VSSO 180 IOSEL[3] 244 WDCLK 53 D[8] 117 RA[8] 181 VCCO 245 IWDE 54 D[7] 118 RA[7] 182 VSSO 246 EWDINT 55 D[6] 119 RA[6] 183 IOSEL[2] 247 TMODE[1] 56 VCCO 120 VCCO 184 IOSEL[1] 248 TMODE[0] 57 VSSO 121 VSSO 185 IOSEL[0] 249 DEBUG 58 D[5] 122 RA[5] 186 WRT 250 INULL 59 D[4] 123 RA[4] 187 WE 251 DIA 60 D[3] 124 RA[3] 188 VCCO 252 VCCO 61 D[2] 125 VCCO 189 VSSO 253 VSSO 62 VCCO 126 VSSO 190 RD 254 FLUSH 63 VSSO 127 RA[2] 191 RLDSTO 255 INST 64 D[1] 128 RA[1] 192 LOCK 256 RTC TSC695F 4118J–AERO–08/04 TSC695F Ordering Information Table 9. Possible Order Entries Temperature Supply Voltage Range Maximum Speed (MHz) Packaging Quality Flow TSC695F-25MA-E 5V 25°C 25 MQFP-F256 Engineering Samples TSC695F-25MA 5V -55° to +125°C 25 MQFP-F256 Standard Mil. 5962-0054001QXC 5V -55° to +125°C 25 MQFP-F256 QML-Q 5962-0054001VXC 5V -55° to +125°C 25 MQFP-F256 QML-V 5962R0054001VXC 5V -55° to +125°C 25 MQFP-F256 QMLV-RHA 951200301 5V -55° to +125°C 25 MQFP-F256 ESCC B TSC695F-25MB-E 5V 25°C 25 Die Engineering Samples 5962-0054001Q9A 5V -55° to +125°C 25 Die QML-Q 5962-0054001V9A 5V -55° to +125°C 25 Die QML-V Part-Number 41 4118J–AERO–08/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 e-mail [email protected] Web Site http://www.atmel.com Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4118J–AERO–08/04 /xM


text: This is easy but tedious. I don't have a lot of money for the job, but I'm not expecting you to do it free. Here's the job... We will look at one website's list of personnel, then copy a selected portion of that data to a second website's database. There is a feature (checkbox) so you can show all the section that is needed. It is a person by person copy and paste and there are multiple fields to paste.. Name Company Phone email password (all the same) website credits I will give detailed instructions, probably a jing video to whomever does this. I was going to post this at Scriptlance, but thought I'd try here first. This is not scraping content or doing anything illegal, simply that we don't have access to the DB from the website that contains the data. The website that will receive the data is a nonprofit organization that I help maintain. let me know if anyone is interested.


text:
This communication provides an update to the October 17, 2014 Delaware Health Alert regarding the ongoing Ebola virus disease outbreak.
The epidemic of Ebola virus disease (EVD) continues to unfold. Particularly affected are the West African countries of Sierra Leone, Liberia, and Guinea; but travel related cases have also shown up in other areas including Dallas, TX, and New York City.
Because of increased monitoring of travelers instituted by DPH in conjunction with CDC's Division of Global Migration and Quarantine, it is unlikely that patients responding "yes" to travel and/or exposure relevant to Ebola and complaining of symptoms will present to your non-hospital facility. Virtually all such patients would already be under monitoring by DPH.
There has been evidence of healthcare associated transmission of EVD in the United States, with two nurses who cared for a man with travel related EVD in Dallas, TX contracting the disease. Both nurses received immediate treatment and have recovered.
There has been no community (non-healthcare) associated transmission in the United States.
The epidemic continues to evolve. For an updated list of countries with ongoing high level transmission, visit the Centers for Disease Control and Prevention (CDC) website at http://www.cdc.gov/vhf/ebola/outbreaks/2014-west-africa/distribution-map.html
Based on currently available information, Ebola virus is only transmitted by patients who have symptoms. Transmission occurs when a susceptible individual comes in contact with blood or other bodily fluids of an infected individual.
Symptoms of EVD occur after an incubation period of two to 21 days and include:
The Division of Public Health (DPH) is providing the guidance below to outpatient facilities including, but not limited to, urgent care centers and outpatient clinics, in order to help with triaging and handling patients who may have had potential exposures to Ebola virus.
For non-hospital settings in which invasive procedures and aerosol producing procedures are NOT performed, DPH is recommending the following for the care of persons suspected of having been exposed to Ebola: **
An easy to understand graphic for PPE removal is available at http://www.who.int/csr/disease/ebola/remove_ppequipment.pdf?ua=1
The CDC also provides detailed guidance on PPE removal available at http://www.cdc.gov/vhf/ebola/hcp/procedures-for-ppe.html AND http://www.cdc.gov/vhf/ebola/hcp/ppe-training/index.html
**For facilities performing invasive procedures or aerosol generating procedures, see next section
DPH recommends that outpatient/non-hospital facilities consider deferring non-emergency invasive or aerosol-generating procedures on individuals with history of travel to affected areas or history of exposure to known Ebola cases until at least 21 days have passed since their last potential exposure.
If aerosol generating procedures (such as nebulizer treatments) or invasive procedures must be done in an outpatient setting, DPH recommends that such facilities follow CDC guidelines for PPE use in hospital settings available at link below and that the number of staff involved in the procedure be limited to the minimum number that can safely be involved http://www.cdc.gov/vhf/ebola/hcp/procedures-for-ppe.html.
When cleaning up after a suspected Ebola patient has been removed from your facility, you should follow CDC guidelines for cleaning available at http://www.cdc.gov/vhf/ebola/hcp/environmental-infection-control-in-hospitals.html
Cleanup should be done by individuals adequately attired in appropriate PPE, with proper attention to careful removal of PPE, as is done for those who have cared for the patient.
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<< -- 3 -- Keith Bramich A JAPANESE 'RIVERDANCE'?
Kaguyahime (sung by soprano Emi Sawahata) systematically exposes her
four untrue suitors:
The first man can't make it, and simply gives up.
Another, asked to bring a special bowl, delivers instead an ordinary
stone bowl from the mountains. 'If it were the true bowl, it would
be shiny', Kaguyahime exclaims, and the man is embarrassed.
The next suitor, asked to find a branch (of a tree) from the place called
Horai (a 'spirit mountain' in China, known for eternal youth), decides that
it will be easier to have a false one made. This is summarily dismissed
because it has no flowers.
The cloth made from the skin of fire rats ... well it shouldn't
burn, but this one actually bursts dramatically into flames, so again it's
a fake.
Does Otomo-no-Dainagon, the fifth suitor, win his girl? What he doesn't
know is that Kaguyahime is really the King of the Moon's daughter, and hence
a Princess. 'Is he still alive, or what?', she asks her real father of Otomo-no-Dainagon.
'What can I do now?' 'You've fallen in love with him, haven't you?' says
her father. 'I've only one thing to say to you, daughter -- follow your heart
and your feelings.'
Kaguyahime pleads with her father ... 'I want to tell him that a dragon
does exist in this world -- I want to show him ... I'll be one ...'
'I'll think of you, whatever you do', promises the King.
Continue >>


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For the most part, Dallas Mayor Mike Rawlings and the City Council are enjoying days of wine and roses, watching the cranes bob on major projects and neighborhoods transform.
But the departure of longtime City Manager Mary Suhm threatens to inject a sour note into council politics.
Hiring the city manager is the rare time council members can get near the patronage that could make them more influential.
Knowing this, they often move to hire a person that reflects their constituent base. In a perfect scenario, it would be someone they could control.
The competing interests are often based on race, as factions on councils past have insisted that the city make history and diversify by hiring minorities.
That was on the minds of city leaders in 1993 when John Ware, a black man, became Dallas city manager. In 1998, he was replaced by the city's first Hispanic city manager, Ted Benavides.
Suhm, a 35-year veteran of City Hall, got her shot when Benavides left.
Now, because of recent redistricting, the racial makeup of the council is fresh on the minds of its members. Will black members push for one of their own? What about Hispanics, who could see their numbers around the horseshoe dwindle from three members to two? That loss of clout could be critical in the selection.
Former Dallas Mayor Ron Kirk offers a simple solution.
"The council has the luxury of finding the best person for the job," Kirk said. "Hire the best person possible."
With no clear favorite working in city government, the next city manager could come from a national search. It's considered a great job: Dallas is one of the largest cities in the country with a strong-manager form of government.
And while the council politics could test Rawlings, Kirk noted it helped that demographic history had already been made.
"The goal should be to go out and get talent," he said.
Follow Gromer Jeffers Jr. on Twitter at @gromerjeffers.


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City of Steam Arkadia: combatThe game's combat system is very smooth and runs better then most browser games....
City of Steam Arkadia: graphicsThe Graphics are very well polished and stunning for this browser based game....
City of Steam Arkadia: questingQuesting is very simple to pick up and offers very nice story lines....
- Overview
City of Steam Arkadia is a free-to-play browser MMORPG with turn-based combat from developer Mechanist Games. City of Steam lets you play a medieval-techno-fantasy adventure that is both friendly to soloers and parties. This no download mmorpg requires you to install a browser plugin called Unity Web Player, which will allow your browser to display the game's high-quality 3D graphics and environments. City of Steam Arkadia is in a crumbling industrial metropolis called the World Machine. A millennium ago, an ancient group of conquerors known as the Paragons sought to harness the mystical energies that keep the World Machine running. Their greed and power proved to be their downfall, though, and they were mysteriously destroyed. But now trouble is stirring from the city-state of Nexus, the site of the Paragons' downfall. Players will grapple with this emerging threat.
As a new player, you will get to choose from a total of nine races now residing in the World Machine and who will explore the Nexus for their respective interests. There are the four human races, which are further subdivived into the Heartlanders, Avens, Ostenians and Stoigmari; the aristocratic sullen-skinned Draug; the charismatic elf-like Riven; the mischievous Goblins; the strong-willed Hobbes; and the gruff Orcs. Each of these races not only look different, but also start the game with different stats called vitals and passives. Vitals include such combat determiners as Physical Agility and Physical Strength while passives range from Attack to Reflex to Speed. This makes it important for City of Steam Arkadia players to choose the appropriate class that will make full use of your starting vitals and passives. Luckily, the game offers recommended classes for each race.
There are four available classes in City of Steam Arkadia -- The Arcanist who casts elemental spells; the stealthy Gunner who wields a pair of magical firearms; the full-armored Warder tasked with protecting their weaker charges; and the zealous Channeler who use instruments to inspire and trumpet doom in battle. Each of the classes has access to different weapons and armor, and also provide respective bonuses in vitals and passives.
Once you have chosen a race and a class in City of Steam Arkadia, you will be able to enter the world and play it either as a single-player RPG or a full-featured MMO. The game can be played solo with each character battling intelligent AI enemies in turn-based combat, or as a group for harder dungeon content. Aside from clearing bosses and collecting gear, characters also strive to explore more about their personal history which will unfold based on your chosen class and race. City Steam Arkadia follows the revenue model of other free browser games by running a cash shop for exclusive in-game items as well as game merchandise such as t-shirts and posters.
- News
New EU Server Coming to City of Steam ArkadiaDespite the mmo scene being more popular than ever, a lot of games have struggled to tread water. 2014 has been a year of sad anno...Read MoreSep122014
See the Sneak Peek for City of Steam Arkadia's 2.7 UpdateThere's been some heavy haze surrounding the City of Steam Arkadia 2.7 update, but this has thinned now that developers have confi...Read MoreJun282014
City Of Steam: Arkadia Lifts IP Block On Polish PlayersBack in December, Western hosts of City of Steam: Arkadia, Mechanist Games, enforced country-wide IP blocks on their Polish and Ru...Read MoreJun092014
City of Steam Arkadia reveals new crafting systemEver since City of Steam Arkadia rose from the ashes of its predecessor, thanks to the tactical re-acquisition of the CoS IP, by M...Read MoreMay282014>> All News
New Servers Coming to City of Steam: ArkadiaPlayers of the browser mmo, City of Steam: Arkadia, will be happy to know that the game is expanding. It's been announced that new...Read MoreApr212014
- Giveaways
City of Steam Arkadia Growth Pack GiveawayMMO-Play has teamed up with Mechanist Games to give away free City of Steam Arkadia Growth Pack Keys. ...Read MoreSep192014
City of Steam Arkadia New Server Pack GiveawayMMO-Play has teamed up with Mechanist Games to give away free City of Steam Arkadia New Server Pack Keys. &n...Read MoreMay082014
City of Steam Free Beta Items GiveawayMMO-Play has teamed up with R2Games to give away City Of Steam Free Beta Items Keys. Redeming th...Read MoreJul262013
City of Steam Closed beta key GiveawayMMO Play teamed up with Mechanist Games to give you access to the Closed Beta testing of the City of Steam.Test period will take p...Read MoreNov302012
City of Steam Alpha Key GiveawayGet your City of Steam alpha key for this weekend from MMO-Play and Mechanist Games! City of Steam is an upcoming 3D mmorpg that ...Read MoreJul312012
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Ref: BBBH18564_1527081104
Call on: 0131 569 0607
Or email: email@example.com
Please enter your details below and upload a CV.
I would like to thank Jemma for finding me a job suited to my skills and attributes. This is my first experience of using QED and I found Jemma to be very professional, helpful and friendly. Jemma took the time to understand the kind of role I was looking for based on my experience and with her help I have secured a great job.
February 2014
Dawn M, North Yorkshire


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Lite News killed itself
Just as Wall Street made bets on bets with credit default swaps and then watched investors bolt, print journalism mass-produced gossip about gossip, and now sees its audience flee.The whole thing is here.
Just as Wall Street made bets on bets with credit default swaps and then watched investors bolt, print journalism mass-produced gossip about gossip, and now sees its audience flee.The whole thing is here.
Considering the number of newspaper editors I've known who bullied both reporters and readers because they thought that they should be the centers of attention in the newspaper universe, I'm actually looking forward to the collapse. I was particularly "fond" of one such character who used to introduce himself "You, of course, know who I am, don't you?", and would throw tantrums if the answer was "No". He and another, who would start public vendettas against anybody who didn't give him the proper respect (as was joked in the Dallas journalistic community, "Having Fat Elvis's physique, Buddy Holly's glasses, and Phil Collins's hair won't make you a rock star"), are the type to blame everything else for why daily and weekly papers across the country are going under, when the one surefire way to make their papers better is for them to play Russian Roulette with an automatic.
That article is on the money.
And nice to see The Wire get a little plug. Soon, 50 people will have seen the greatest show ever broadcast.
The comparison is flawed because it implies two separate entities doing similar things, whereas Wall Street and the newspapers are all the result of the same oligarchy. A few people in charge of huge corporations have purchased the United States government, used their power to enrich themselves while running up tremendous risks, and are now using their power to have the United States government bail them out.
Control of the media was a necessary part of the coup and print newspapers fell into that. Independent newspapers like the Portland Tribune where I used to have a column, were controlled into fluffy submission by the manufactured public outcry if certain taboo subjects were touched upon.
Having no way to make newspapers required reading, or charge for their websites, the newspapers had to rely on their product. The public figured we get enough diluted brainwashing drivel for free - why pay for it?
The Internet is a shining beacon of light which is why the oligarchy is staying up late trying to think of ways to control it and ruin it too.
Freedom of information hangs in the balance and the situation gets more precarious everyday - precarious for us because we could turn on these computers one day, and have it be a completely different experience. Precarious for the powers that be because we could use these computers to spread the information that the oligarchs don't want you to have.
That's why these are treacherous times. The economic collapse is either an opportunity for us or them. Which will it be?
Based on the fact that the People of the United States have now been financially enslaved to keep the oligarchs from crumbling, the prognosis does not look good.
David Sirota isn't afraid to say the emperor has no clothes on. The No- news news paperspapers have long ago quit reporting and are just doing the bidding of government or Corp, whichever is hood-unwinking us at the moment.
Bill Mc Donald is on the money with his observation. Good-bye big O and good riddance.
Let us hope Internet stays free and under no obigation of Government nor big business...probably not going happen.
Long time ago reporters were working people, then they became journalist, a profession and became smarter than the rest of us in the process. Since they were smarter they didn't have to work as hard and we were to accept what they wrote. It just was.
Fine example if I may. A few years ago there was a bit of press over a report from the Institute for Medicine regarding the number of deaths annually from medical errors. The Big "OH!" carried an article on the front page, but how many follow up stories did they run on Oregon hospitals? None that I recall which is significant given that the numbers from the Institute for Medicine were something like between 44,000 and 100,000 annually. Those numbers suggest that there are between 500 and 1000 annually, or more in Oregon.
The Journalist don't have time to dig into issues, so we should just accept the point that the issue is not important.
It's true that corporatized newspapers degraded their product in the last 20 years, chasing after lofty stock-option enhancing quarterly reports. No doubt about it. But look around this culture; you really think the masses are interested in reading investigative reports? I'm not buying it.
Would you settle for newspapers covering the news? Instead we had fake news - President Bush using taxpayer money to pay newspaper columnists to spread PR.
Here's how I think it works: The oligarchs have a direction that they want government to follow. They give Congress and the White House their orders partly in exchange for campaign contributions but also in exchange for not being destroyed in the media.
The public is merely there as the worker ants who get stuck with the bill. The media is helpful in selling any message to them, but it's mainly there to dazzle them with whether or not Britney is wearing panties.
This TARP bailout was a gigantic opportunity to see the real power at work here.
Congress voted it down, so the oligarchs took it back and ordered them to vote yes.
Along the way, Henry Paulson stipulated that the money would be dished out by him to whomever he wanted with no oversight by Congress or the courts. In effect we were just here to provide the 700 billion to him. The people who used our government to make the mess, were now using our government to save their asses. It's hard not to say that this makes them in charge of America.
Now the stipulation of complete power by Paulson was changed to some congressional oversight but considering Congress works for the oligarchs that's no big deal. We still don't know who got the money.
Henry could have given his kid a thousand soccer stadiums and we would never be able to do a thing. The nearest anyone can figure out is that the people who got the money were those who Paulson knew from Wall Street and the Goldman Sachs days.
Matt Taibbi of Rolling Stone has managed to investigate this. You can read his article for free online. It's called "The Big Takeover." If you don't know who Joe Cassano is, you should read this just for that.
I doubt if the remaining newspapers will be printing any excerpts.
David Sirota is one of the finest policy wonks around, but I'm not buying his argument on the demise of newspapers. He seems to think there was an era in American journalism when the news media did a better job than they do today.
When I was in J-school 40 years ago, the media gave LBJ a pass on the Vietnam War for several years before events in 1968 forced it to reconsider and start truly covering the enormity of that war. Shortly afterward, reporters routinely genuflected before Henry Kissinger as if he were the pope of foreign policy. Sure, there was a spate of investigative reporting after Watergate, but mostly because newspaper publishers figured investigative reporting would increase readership. Eventually, the investigations got more trivial and even silly, devolving into "gotcha" journalism. But it was always so. You ever see the movie "The Front Page" (aka "His Girl Friday" in the best version, starring Rosalind Russell and Cary Grant)? That script was written in the twenties.
The failure of papers today isn't so much one of content, but of resources. Newspapers are owned by large conglomerates and often were acquired through highly leveraged transactions. I've seen studies that show newspaper readership is increasing, but the costs of doing business are increasing faster--especially the cost of paying off the loans used to finance the purchase of the paper. And ad revenue is not keeping pace. So papers first reduced their font size because it reduces the amount of paper used, paper being their number one cost. Then they slashed budges everywhere else, including the number of reporters and editors they employ.
By the way, the City Club is having a panel discussion on this very topic on Friday, April 17.
One of my foremost heroes, George Seldes, was a fearless journalist who quickly found out that writing unpleasant things about major advertisers (department stores were the leading advertisers of the day when he began) was a sure route to extinction as a reporter.
Some of his books, many of which contain his outrage about the press's failure to do its job without fear or favor:
# Witness to a Century: Encounters with the Noted, the Notorious, and the…
# You can't print that!: The truth behind the news, 1918-1928
# Lords of the press
# Sawdust Caesar;: The untold history of Mussolini and fascism
# Facts and fascism
# Even the Gods Can't Change History: The Facts Speak for Themselves
# Freedom of the press
# You can't do that
# Never Tire of Protesting
# 1000 Americans: The Real Rulers of the U.S.A.
# The people don't know;: The American press and the cold war
# Witch hunt; the technique and profits of redbaiting
# The Facts Are...: A Guide to Falsehood and Propaganda in the Press....
# Iron, blood and profits;: An exposure of the world-wide munitions racket
# Tell the truth and run
Great piece here, another example of why we won't have the archaic media to kick around much longer: their complicity with torture and refusal to challenge the Bush Torture gangsters: