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Multi-core processor
A multi-core processor is a single computing component with two or more independent actual processing units (called "cores"), which are the units that read and execute program instructions.[1] The instructions are ordinary CPU instructions such as add, move data, and branch, but the multiple cores can run multiple instructions at the same time, increasing overall speed for programs amenable to parallel computing.[2] Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package.
Processors were originally developed with only one core. In the mid 1980s Rockwell International manufactured versions of the 6502 with two 6502 cores on one chip as the R65C00, R65C21, and R65C29,[3][4] sharing the chip's pins on alternate clock phases. Other multi-core processors were developed in the early 2000s by Intel, AMD and others.
Multi-core processors may have two cores (dual-core CPUs, for example, AMD Phenom II X2 and Intel Core Duo), three cores (tri-core CPUs, for example, AMD Phenom II X3), four cores (quad-core CPUs, for example, AMD Phenom II X4, Intel's i5 and i7 processors), six cores (hexa-core CPUs, for example, AMD Phenom II X6 and Intel Core i7 Extreme Edition 980X), eight cores (octa-core CPUs, for example, Intel Xeon E7-2820 and AMD FX-8350), ten cores (deca-core CPUs, for example, Intel Xeon E7-2850), or more.
A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores, heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.
Multi-core processors are widely used across many application domains including general-purpose, embedded, network, digital signal processing (DSP), and graphics (GPU).
The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can be run in parallel simultaneously on multiple cores; this effect is described by Amdahl's law. In the best case, so-called embarrassingly parallel problems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core's cache(s), avoiding use of much slower main system memory. Most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem.[5] The parallelization of software is a significant ongoing topic of research.
- 1 Terminology
- 2 Development
- 3 Hardware
- 4 Software effects
- 5 Embedded applications
- 6 Hardware examples
- 7 Benchmarks
- 8 Notes
- 9 See also
- 10 References
- 11 Further reading
- 12 External links
The terms multi-core and dual-core most commonly refer to some sort of central processing unit (CPU), but are sometimes also applied to digital signal processors (DSP) and system-on-a-chip (SoC). The terms are generally used only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die; separate microprocessor dies in the same package are generally referred to by another name, such as multi-chip module. This article uses the terms "multi-core" and "dual-core" for CPUs manufactured on the same integrated circuit, unless otherwise noted.
In contrast to multi-core systems, the term multi-CPU refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other).
The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with an especially high number of cores (tens or hundreds).[6]
Some systems use many soft microprocessor cores placed on a single FPGA. Each "core" can be considered a "semiconductor intellectual property core" as well as a CPU core.[citation needed]
While manufacturing technology improves, reducing the size of individual gates, physical limits of semiconductor-based microelectronics have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some instruction-level parallelism (ILP) methods such as superscalar pipelining are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to thread-level parallelism (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs.
Commercial incentives
Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for complex instruction set computing (CISC) architectures. Clock rates also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s.
As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, Intel has produced a 48-core processor for research in cloud computing; each core has an x86 architecture.[7][8]
Technical factors
Since computer manufacturers have long implemented symmetric multiprocessing (SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known.
- Using a proven processing-core design without architectural changes reduces design risk significantly.
- For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency. This is due to three primary factors:
- The memory wall; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.
- The ILP wall; the increasing difficulty of finding enough parallelism in a single instruction stream to keep a high-performance single-core processor busy.
- The power wall; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "shrinking" the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall.
In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip.
The proximity of multiple CPU cores on the same die allows the cache coherency circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance of cache snoop (alternative: Bus snooping) operations. Put simply, this means that signals between different CPUs travel shorter distances, and therefore those signals degrade less. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often.
Assuming that the die can physically fit into the package, multi-core CPU designs require much less printed circuit board (PCB) space than do multi-chip SMP designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front-side bus (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns.[citation needed]
Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.[9]
Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the operating system (OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications.
Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. It has been claimed[by whom?] that if a single core is close to being memory-bandwidth limited, then going to dual-core might give 30% to 70% improvement; if memory bandwidth is not a problem, then a 90% improvement can be expected; however, Amdahl's law makes this claim dubious.[10] It would be possible for an application that used two CPUs to end up running faster on a dual-core one if communication between the CPUs was the limiting factor, which would count as more than 100% improvement.
The trend in processor development has been towards an ever increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.[11] In addition, multi-core chips mixed with simultaneous multithreading, memory-on-chip, and special-purpose "heterogeneous" (or asymmetric) cores promise further performance and efficiency gains,[12] especially in processing multimedia, recognition and networking applications. For example, a big.LITTLE core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (i.e. laptop computers and portable media players).
The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "heterogeneous" role.
The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,[13] includes these comments:
Chuck Moore [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface.
[...] Atsushi Hasegawa, a senior chief engineer at Renesas, generally agreed. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs.
[...] Anant Agarwal, founder and chief executive of startup Tilera, took the opposing view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.
Software effects
An outdated version of an anti-virus application may create a new thread for a scan process, while its GUI thread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (see thread-safety). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Although threaded applications incur little additional performance penalty on single-processor machines, the extra overhead of development has been difficult to justify due to the preponderance of single-processor machines. Also, serial tasks like decoding the entropy encoding algorithms used in video codecs are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm.
Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.
The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace[14] the traditional Network Processors that were based on proprietary micro- or pico-code.
Parallel programming techniques can benefit from multiple cores directly. Some existing parallel programming models such as Cilk Plus, OpenMP, OpenHMPP, FastFlow, Skandium, MPI, and Erlang can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called TBB. Other research efforts include the Codeplay Sieve System, Cray's Chapel, Sun's Fortress, and IBM's X10.
Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of numerical libraries to access code written in languages like C and Fortran, which perform math computations faster than newer languages like C#. Intel's MKL and AMD's ACML are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context.[15]
Managing concurrency acquires a central role in developing parallel applications. The basic steps in designing parallel applications are:
- Partitioning
- The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.
- Communication
- The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.
- Agglomeration
- In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation.
- Mapping
- In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.
On the other hand, on the server side, multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput.
Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores.
- Initially, for some of its enterprise software, Microsoft continued to use a per-socket licensing system. However, for some software such as BizTalk Server 2013, SQL Server 2014, and Windows Server 2016, Microsoft has shifted to per-core licensing.[16]
- Oracle Corporation counts an AMD X2 or an Intel dual-core CPU as a single processor[citation needed] but uses other metrics for other types, especially for processors with more than two cores.[17]
Embedded applications
Embedded computing operates in an area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors.
In addition, embedded software is typically developed for a specific hardware release, making issues of software portability, legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers.
As of 2010[update], multi-core network processing devices have become mainstream, with companies such as Freescale Semiconductor, Cavium Networks, Wintegra and Broadcom all manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in an SMP operating system. To address this issue, companies such as 6WIND provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the OS, while retaining full compatibility with standard OS APIs.[18]
In digital signal processing the same trend applies: Texas Instruments has the three-core TMS320C6488 and four-core TMS320C5441, Freescale the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family from Stream Processors, Inc with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and Picochip with three-hundred processors on a single die, focused on communication applications.
Hardware examples
- Adapteva Epiphany, a many-core processor architecture which allows up to 4096 processors on-chip, although only a 16 core version has been commercially produced.
- Aeroflex Gaisler LEON3, a multi-core SPARC that also exists in a fault-tolerant version.
- Ageia PhysX, a multi-core physics processing unit.
- Ambric Am2045, a 336-core Massively Parallel Processor Array (MPPA)
- A-Series, dual-, triple-, and quad-core of Accelerated Processor Units (APU).
- Athlon 64, Athlon 64 FX and Athlon 64 X2 family, dual-core desktop processors.
- Athlon II, dual-, triple-, and quad-core desktop processors.
- FX-Series, quad-, 6-, and 8-core desktop processors.
- Opteron, dual-, quad-, 6-, 8-, 12-, and 16-core server/workstation processors.
- Phenom, dual-, triple-, and quad-core processors.
- Phenom II, dual-, triple-, quad-, and 6-core desktop processors.
- Sempron X2, dual-core entry level processors.
- Turion 64 X2, dual-core laptop processors.
- Radeon and FireStream multi-core GPU/GPGPU (10 cores, 16 5-issue wide superscalar stream processors per core)
- Analog Devices Blackfin BF561, a symmetrical dual-core processor
- ARM MPCore is a fully synthesizable multi-core container for ARM11 MPCore and ARM Cortex-A9 MPCore processor cores, intended for high-performance embedded and entertainment applications.
- ASOCS ModemX, up to 128 cores, wireless applications.
- Azul Systems
- Vega 1, a 24-core processor, released in 2005.
- Vega 2, a 48-core processor, released in 2006.
- Vega 3, a 54-core processor, released in 2008.
- Broadcom SiByte SB1250, SB1255, SB1455; BCM 2836 quad-core ARM SoC (designed for the Raspberry Pi 2)
- ClearSpeed
- CSX700, 192-core processor, released in 2008 (32/64-bit floating point; Integer ALU)
- Cradle Technologies CT3400 and CT3600, both multi-core DSPs.
- Cavium Networks Octeon, a 32-core MIPS MPU.
- Freescale Semiconductor QorIQ series processors, up to 8 cores, Power Architecture MPU.
- Hewlett-Packard PA-8800 and PA-8900, dual core PA-RISC processors.
- POWER4, a dual-core PowerPC processor, released in 2001.
- POWER5, a dual-core PowerPC processor, released in 2004.
- POWER6, a dual-core PowerPC processor, released in 2007.
- POWER7, a 4,6,8-core PowerPC processor, released in 2010.
- POWER8, a 12-core PowerPC processor, released in 2013.
- PowerPC 970MP, a dual-core PowerPC processor, used in the Apple Power Mac G5.
- Xenon, a triple-core, SMT-capable, PowerPC microprocessor used in the Microsoft Xbox 360 game console.
- z10, a quad-core z/Architecture processor, released in 2008
- z196, a quad-core z/Architecture processor, released in 2010
- zEC12, a six-core z/Architecture processor, released in 2012
- z13, an eight-core z/Architecture processor, released in 2015
- Kalray
- MPPA-256, 256-core processor, released 2012 (256 usable VLIW cores, Network-on-Chip (NoC), 32/64-bit IEEE 754 compliant FPU)
- Sony/IBM/Toshiba's Cell processor, a nine-core processor with one general purpose PowerPC core and eight specialized SPUs (Synergystic Processing Unit) optimized for vector operations used in the Sony PlayStation 3
- Infineon
- Danube, a dual-core, MIPS-based, home gateway processor.
- Intel
- Atom, single and dual-core processors for netbook systems.
- Celeron Dual-Core, the first dual-core processor for the budget/entry-level market.
- Core Duo, a dual-core processor.
- Core 2 Duo, a dual-core processor.
- Core 2 Quad, 2 dual-core dies packaged in a multi-chip module.
- Core i3, Core i5 and Core i7, a family of multi-core processors, the successor of the Core 2 Duo and the Core 2 Quad.
- Itanium 2, a dual-core processor.
- Pentium D, 2 single-core dies packaged in a multi-chip module.
- Pentium Extreme Edition, 2 single-core dies packaged in a multi-chip module.
- Pentium Dual-Core, a dual-core processor.
- Teraflops Research Chip (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.[19]
- Xeon dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, and 18-core processors.[20][21][22][23]
- Xeon Phi 57-core, 60-core and 61-core processors.
- IntellaSys
- SEAforth 40C18, a 40-core processor[24]
- SEAforth24, a 24-core processor designed by Charles H. Moore
- NetLogic Microsystems
- XLP, a 32-core, quad-threaded MIPS64 processor
- XLR, an eight-core, quad-threaded MIPS64 processor
- XLS, an eight-core, quad-threaded MIPS64 processor
- Nvidia
- GeForce 9 multi-core GPU (8 cores, 16 scalar stream processors per core)
- GeForce 200 multi-core GPU (10 cores, 24 scalar stream processors per core)
- Tesla multi-core GPGPU (10 cores, 24 scalar stream processors per core)
- Parallax Propeller P8X32, an eight-core microcontroller.
- picoChip PC200 series 200–300 cores per device for DSP & wireless
- Plurality HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.
- Rapport Kilocore KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements".
- SiCortex "SiCortex node" has six MIPS64 cores on a single chip.
- Sun Microsystems
- MAJC 5200, two-core VLIW processor
- UltraSPARC IV and UltraSPARC IV+, dual-core processors.
- UltraSPARC T1, an eight-core, 32-thread processor.
- UltraSPARC T2, an eight-core, 64-concurrent-thread processor.
- UltraSPARC T3, a sixteen-core, 128-concurrent-thread processor.
- SPARC T4, an eight-core, 64-concurrent-thread processor.
- SPARC T5, a sixteen-core, 128-concurrent-thread processor.
- Texas Instruments
- TMS320C80 MVP, a five-core multimedia video processor.
- TMS320TMS320C66, 2,4,8 core dsp.
- Tilera
- XMOS Software Defined Silicon quad-core XS1-G4
- MIT, 16-core RAW processor
- University of California, Davis, Asynchronous array of simple processors (AsAP)
- University of Washington, Wavescalar processor
- University of Texas, Austin, TRIPS processor
- Linköping University, Sweden, ePUMA processor
The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.[25]
- ^ Digital signal processors (DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general-purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common in mobile phones. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.
- ^ Two types of operating systems are able to use a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.
See also
- Race condition
- Multicore Association
- Hyper-threading
- Multitasking
- PureMVC MultiCore – a modular programming framework
- Parallel Random Access Machine
- Partitioned global address space (PGAS)
- Thread
- CPU shielding
- OpenCL (Open Computing Language) – a framework for heterogeneous execution
- Ateji PX – an extension of the Java language for parallelism
- BMDFM (Binary Modular Dataflow Machine) – Multi-core Runtime Environment
- ↑ Margaret Rouse (March 27, 2007). "Definition: multi-core processor". TechTarget. Retrieved March 6, 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ CSA Organization
- ↑ "Rockwell R65C00/21 Dual CMOS Microcomputer and R65C29 Dual CMOS Microprocessor" (PDF). Rockwell International. October 1984.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ "Rockwell 1985 Data Book" Check
|url=value (help) (PDF). Rockwell International Semiconductor Products Division. January 1985.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Aater Suleman (May 20, 2011). "What makes parallel programming hard?". FutureChips. Retrieved March 6, 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Programming Many-Core Chips. By András Vajda, page 3
- ↑ Ryan Shrout (December 2, 2009). "Intel Shows 48-core x86 Processor as Single-chip Cloud Computer". Retrieved May 17, 2015.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ "Intel unveils 48-core cloud computing silicon chip". BBC. December 3, 2009. Retrieved March 6, 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Aater Suleman (May 19, 2011). "Q & A: Do multicores save energy? Not really". Retrieved March 6, 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Ni, Jun. "Multi-core Programming for Medical Imaging" (PDF). Retrieved 17 February 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Clark, Jack. "Intel: Why a 1,000-core chip is feasible". ZDNet. Archived from the original on 6 August 2015. Retrieved 6 August 2015.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors, ACM Computing Surveys, 2015.
- ↑ Rick Merritt (February 6, 2008). "CPU designers debate multi-core future". EE Times. Retrieved March 6, 2013.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Multicore packet processing Forum
- ↑ John Darlinton, Moustafa Ghanem, Yike Guo, Hing Wing To (1996), "Guided Resource Organisation in Heterogeneous Parallel Computing", Journal of High Performance Computing, 4 (1): 13–23 <templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Bright, Peter (4 December 2015). "Windows Server 2016 moving to per core, not per socket, licensing". Ars Technica. Condé Nast. Retrieved 5 December 2015.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Compare: "The Licensing Of Oracle Technology Products". OMT-CO Operations Management Technology Consulting GmbH. Retrieved 2014-03-04.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ Maximizing network stack performance
- ↑ 80-core prototype from Intel
- ↑ 15 core Xeon
- ↑ "Intel Xeon Processor E7 v3 Family". Intel.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ "Intel Xeon Processor E7 v2 Family". Intel.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ "Intel Xeon Processor E3 v2 Family". Intel.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
- ↑ "40-core processor with Forth-based IDE tools unveiled"
- ↑ "COSMIC Heterogeneous Multiprocessor Benchmark Suite"
Further reading
- Lua error in Module:Citation/CS1/Identifiers at line 47: attempt to index field 'wikibase' (a nil value).
- Khondker S. Hasan, Nicolas G. Grounds, John K. Antonio (July 2011). Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads. 17th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-11). Las Vegas, Nevada, USA. pp. 551–557. <templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
External links
- What Is A Processor Core?
- Embedded moves to multicore
- Multicore News blog
- IEEE: Multicore Is Bad News For Supercomputers
- Architecting solutions for the Manycore future, published on Feb 19, 2010 (more than one dead link in the slide)
- CS1 maint: Multiple names: authors list
- Articles with unsourced statements from February 2011
- Articles with unsourced statements from January 2009
- Articles with specifically marked weasel-worded phrases from December 2007
- Articles with unsourced statements from March 2015
- CS1 maint: Uses authors parameter
- Computer architecture
- Digital signal processing
- Microprocessors
- Parallel computing
- Flynn's taxonomy


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We understand every business is different, so we designed the BeyondTrust Privilege Partner Program with flexible participation levels based on your business goals and growth strategies. Ascend through Fulfillment, Silver, Gold and Platinum partner levels to gain increasing levels of benefits, resources and growth opportunities.
Why Partner with BeyondTrust
The BeyondTrust Privilege Partner Program is designed for value-added resellers, solution providers, and technology alliance partners. As a BeyondTrust partner, you have access to the technical guidance, sales alignment, enablement, and the competitive financial rewards you need to be successful.
The BeyondInsight IT Risk Management Platform is at the core of our partner value proposition. BeyondInsight can be configured for vulnerability management, privileged account management, or both. No matter where they begin, your customers have access to powerful, integrated platform that can be extended and augmented as their needs evolve – providing you with a clear path for additional sales opportunities.
Relentless Partner Focus
Focusing on our partners is part of our DNA. You'll stand out with state-of-the-art tools and resources designed to help you succeed.
Exceptional Profit and Growth
Realize lucrative margins with our competitive deal registration and incentive programs.
Dedicated Partner Team
Work smarter with expert assistance from channel account managers, sales engineers, and expert marketing professionals.
Why BeyondTrust for Your Clients
BeyondTrust believes preventing data breaches requires the right visibility to enable control over internal and external risks. We give your client the visibility to confidently reduce risks and the control to take proactive, informed action against data breach threats. And because threats can come from anywhere, we built a platform that unifies the most effective technologies for addressing both internal and external risk: privileged account management and vulnerability management.
We mitigate internal and external threats
Our integrated privilege and vulnerability management solutions reduce insider threats, shrink external attack surfaces, and contain any criminals who happen to find their way in.
We deliver actionable data
Our reporting and analytics capabilities provide clear, concise, prioritized information about risky assets and users in your clients' environments – plus the insight they need to take immediate action.
We've got your back
From world-class professional services to available 24x7 support, BeyondTrust is always there when you and your clients need us.

subset: commoncrawl


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Browse by Author/Editor
Group by: Type of Work | No Grouping
Jump to: Article
Number of items: 1.
Hancock, Cathryn and Herranz, T and Marco, J and Berry, F and Slater, P.R. (2012) Low temperature fluorination of Sr3Fe2O7-x with polyvinylidine fluoride: an X-ray powder diffraction and Mössbauer spectroscopy study. Journal of Solid State Chemistry, 186. pp. 195-203.


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Thought Leadership
April 14, 2009
McDermott Will & Emery, Boston, MA


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Justin Bieber Writes Breakup Song that May Have Been Inspired by Selena Gomez
Justin Bieber's love saga continues after the "Beauty and a Beat" singer wrote a new song for his on-again, off-again squeeze Selena Gomez.
The news comes days after both Bieber and SelGo performed Justin Timberlake's popular breakup tune, "Cry Me a River," at separate concerts.
Now, Us Weekly magazine is reporting that Bieber has a new song titled "Nothing Like Us," which is in his new album "Believe Acoustic," out for sale on Tuesday.
"It tells the whole story about how he broke up with her, she begged him to take her back, and then he decided he was done for good," an insider tells the entertainment publication.
"This is his answer to Selena."
Gomez and Bieber dated for two years before splitting back in November of last year, getting back together, and then breaking up again during their New Year's Eve celebration in Mexico.
The magazine says that the song implies that the Biebs did really love SelGo but could not deal with the 'she loves me, she loves me not' back and forth.
Gave you everything
Everything I had to give
Girl, why would you push me away
Lost in confusion, Like an illusion
You know I'm used to making your day
That's in the past now
We didn't last now
Guess that this is meant to be
Then Bieber goes on to say: "There's nothing like us / There's nothing like you and me together through the storm."
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Style # 206113
AVAILABILITY: Unavailable for immediate shipment.
Inject your look with ultra-chic flirty hues in this bebe logo polo sweater, featuring V-neckline, soft knit and casual collar. Try it with a pair of your favorite skinny jeans for an instant day look.
- 80% rayon, 15% nylon, 5% spandex
- Center back to hem: 22" (56 cm)
- Dry clean
- Imported
- Model is 5'9" and is wearing a US size S
Logo Polo Top is rated out of 5 by 2.
Rated 2 out of 5 by bebe92 from Not A Must Have I'm a logo freak and I have tons of bebe logo tops, but this top runs tiny after you wash it for the first time! The Cons are: see through, the material seems cheap. I bought the sunny lime color, it looks weird on me.
Date published: 2013-04-12
Rated 5 out of 5 by 65girl from This sweater is hot!!! I got this sweater in the calypso coral, the color is very flattering to my complexion. I am a 34D and it covered the ladies just fine. The sweater is very soft and has a nice stretch so it hugs my curves. I would highly recommend!
Date published: 2013-01-21


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Another week has ended and it's time to sit back and relax with some wine and live music! The Iron Plow stage is set for local singer-songwriters to swoon you while you enjoy a wine flight, wine by the glass/bottle and an artisan cheese & charcuterie menu. Live music weekends are Friday evenings and Saturday/Sunday afternoons. In the summer enjoy it all overlooking breathtaking vistas of the vineyard from our patio and live music outside. There is no cover charge for this event and we do permit outside food. See a full listing of musicians on our website at www.ironplowvineyards.com
- This event has passed.


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posted by Thom Holwerda on Tue 28th Feb 2006 18:51 UTC
At a special press event today, Apple introduced various new products. Besides the usual iPod/iTunes chit-chatter, they introduced a new Mac Mini with either a dual-core or single-core Intel processor. The new Mini sports the same form factor as the old one, and comes with an improved Front Row (support for playing streamed content using Bonjour), TV-out, and more. Note: Thanks go out to iLounge, MacCentral, and Engadget for providing live feeds.


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Local business hosted speech contest that helps persons become better public speakers
It was an exciting time in Moberly Saturday morning (Nov. 9), when individuals from across the state of Missouri met at GE Capital, to compete in the District 8 – Division E Toastmasters Table Topics and Humorous Speech Contest (hosted by Courage to Grow at GE Capital).
Toastmasters International is a non-profit educational organization that teaches public speaking and leadership skills through a worldwide network of meeting locations. The organization has more than 292,000 members in more that 14,350 clubs in 122 countries. Since 1924, Toastmasters International has helped people of all backgrounds become more confident in front of an audience.
Contest Master Ron Smith welcomed all in attendance.
All but one Table Topics (an event consisting of participants extemporaneously speaking on a topic posed to them ["Why should we listen to our hearts as well as our minds?" being Saturday's]) contestant left the room and Nathan Swan began the competition.
Table Topics Contestants were: Nathan Swan, Randima Dinalankara, Ahmed Unuku, Ramesh Chandrani, Beatriz Calmet-Chinn and Wayne Horine. Following the judging Table Topics winners were: First place – Ahmed Onuku; Second place – Wayne Horine, and Third place — Beatriz Calmet-Chinn.
Humorous Speech Contestants were: Sudharshan Anandan, Brandon Brown, Blythe Horine, Drew Lincoln, David Mallory, and Zachary Stafford. Winners announced were: First place – Sudharshan Anandan; Second place – Zachary Stafford, and Third place – Beatriz Calmet-Chinn.


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Low | High bandwidth
(Real player)
video on demand
from The Newsmarket
GENEVA/NEW YORK, 18 April 2005 More children than ever are going to school, in part because more girls are going to school: Thats the good news from UNICEFs latest Progress for Children report, focusing on gender parity in primary school attendance.
However millions of girls are still denied a basic education. While the gender gap in primary school attendance is shrinking globally, in many parts of the world it still yawns wide. The barriers keeping girls out of school in the developing world not only rob them of future opportunity, but impact their very health and survival.
Education is about more than just learning. In many countries its a life-saver, especially where girls are concerned, said UNICEF Executive Director Carol Bellamy, at the launch of the report. A girl out of school is more likely to fall prey to HIV/AIDS and less able to raise a healthy family.
The world has made impressive gains towards getting equal numbers of girls into primary schools as boys. Some 125 out of 180 countries for which data were available are on course to reach gender parity by 2005- a target set by the UN as part of the Millennium Development Goals.
Yet the global average masks huge pockets of inequity. Three regions -- Middle East/North Africa, South Asia and West/Central Africa -- will not meet the gender parity goal.
Gender parity is a prerequisite if the world is to achieve universal primary education by 2015, the target date set by the UN for a key Millennium Development Goal. The shrinking gender gap has helped reduce the total number of children denied a primary education. According to projections, fewer than 100 million children may be out of primary school by 2005, down from an estimated 115 million in 2001. Whatever the exact figure, it is clear that far too many are still shut out of the classroom, and at the present rate of increased school attendance, the goal of universal primary education by 2015 wont be met.
This report proves that our strategic focus on getting more girls into school is working to increase attendance rates for boys and girls in primary school, added Bellamy. But it also makes clear that a quantum leap is needed both to break down the barriers keeping girls out of school and to make school available to all children.
Gender disparity actually favours girls in two regions, Latin America/Caribbean and East Asia/Pacific. While addressing the gender gap is key to the goal of universal primary education, other barriers to childrens school participation need to be addressed as well. In Haiti, for instance, there are more girls than boys in primary school, but over 40 per cent of all primary-school-age children are denied an education.
The report gives a country-by-country snapshot of progress toward both goals of gender parity and universal primary education. It details wide differences between regions and between and within countries.
At the current rate of progress most countries in the Middle East/ North Africa, East Asia/Pacific and Latin America/Caribbean regions are on track to achieving universal primary education by 2015. At the other extreme most countries in sub- Saharan Africa and many in South Asia wont come close unless they greatly accelerate their rates of progress.
A fundamental barrier to increased access to education is poverty. Children from the poorest 20 per cent of households in the developing world are on average three times less likely to go to primary school than those from the wealthiest 20 per cent. This average ratio masks huge disparities between regions and between countries. In the CEE/CIS region, for instance, the poorest children are 1.6 times more likely to be out of school, but they are five times more likely to be out of school in the Republic of Moldova and Kazakhstan.
Another important factor determining a childs chances of going to school is the mothers education. Some 75 per cent of children out of primary school in developing countries have mothers who did not go to school. That proportion varies dramatically from region to region; 28 per cent in East Asia/Pacific as opposed to 80 per cent in West/Central Africa, South Asia and Middle East/North Africa.
The prevalence of HIV/AIDS, civil conflict, child labour, child trafficking and natural disasters all have a clear impact on access to schools and all tend to affect countries with already weak educational infrastructures.
Making universal primary education and gender parity in schools a reality will require some radical shifts in thinking and policies. All countries must begin to view education as a fundamental human right, not as an optional add-on where budgets allow. Kenyas decision to abolish school fees for primary schools, following in the footsteps of Tanzania and Uganda, is just such a dramatic shift in thinking.
To be sure, opening the school gate to all who wish to enter has put a massive strain on already over-burdened resources. Thats why international aid for education must be drastically increased. The UN estimates that an extra USD 5.6 billion per year will be required to achieve universal primary education -- no small sum. Some richer nations have already recognised the importance of this challenge. The UK government has pledged $2.68 billion over the next three years to help get more girls in school. Norway contributed $51 million to UNICEF supported education initiatives in 2003- 2004.
The goal of universal primary education with equal opportunity for girls and boys is realistic, added Bellamy. It is affordable, it is achievable and whats more, its our childrens birthright.
UNICEF, as one of the lead agencies in the United Nations Girls Education Initiative (UNGEI), is committed to narrowing the gender gap in primary and secondary education by 2005 and to ensuring that by 2015, all children complete primary schooling. UNGEI is a partnership that embraces the UN system, governments, donor countries, non-governmental organizations, civil society, the private sector, and communities and families.
Attention Broadcasters: B-roll of the event and the stories above will be fed on Monday, 18 April via UNIFEED through APTN. Visit: www.un.org/unifeed.
For further information contact:
Wivina Belmonte, UNICEF Media, Geneva, email@example.com
(41-22) 909 5712
Oliver Phillips, UNICEF Media, NY, firstname.lastname@example.com
(1) 212 326 7583
Kate Donovan, UNICEF Media, New York, firstname.lastname@example.com
(1) 212 326 7452
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from The Newsmarket


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First Look Store Review: Gene's Sausage Shop
- Location: Chicago, IL
- Website: genessausageshop.com
Gene's Sausage Shop at Delicatessen Meyer is now open for business in Chicago's Lincoln Square neighborhood. After two years of anticipation, we finally got a peek inside.
When the former Meyer Delicatessen closed its doors more than two years ago, it meant one less old-world institution in the neighborhood. But soon after, word came that Gene's Sausage Shop had purchased the space and would be opening a new location there.
Slowly but surely, the small deli with two narrow aisles was replaced by what looked to be a two-story sausage emporium.
On Saturday, Gene's Sausage Shop at Delicatessen Meyer opened its doors. We stopped by last night and found – in addition to cases and cases of sausage and other meats – a large selection of European specialty products, cheeses, beer, wine and liquor, produce and frozen sections, and bakery items.
There are also plans to open a roof deck in the spring.
• 1 A selection of headcheese.
• 2 You'll have to stare this guy down as you peruse the sausages.
• 3 Sausages and more sausages. Take your pick.
• 4 Kiska, or blood sausage, with barley.
• 5 The view from the second floor.
• 6 A shelf full of butters.
• 7 More butter!
• 8 Snack cheeses from Germany-based Hochland.
• 9 Dutch cheese and wooden shoes.
• 10 Various cuts of herring.
• 11 Crusty bread.
• 12 The upper level is devoted to beverages, including a large selection of teas.
• 13 The perfect glass for your Austrian beer.
• 14 A swanky wine display.
• 15 The old Meyer Delicatessen sign is hung prominently at the top of the stairs.
Related: Sausage: Cased Or Uncased?
(Images: Joanna Miller)


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81206 – 3″ Thin Wall PVC DWV Sch. 30 Adapter – Pack of 1
DWV * Drain-Waste-Vent
81206 – PVC Adapter for Vacuum – Pack of 1
Materials and Properties
Loc-Line: Vacuum Hose and Fittings
Colors: White
Material: Acetal Copolymer
PVC Adapter: PVC
Yes: Acids under 150F, Alcohols, Aromatic Solvents, Gasoline, Grease, Hydrocarbons, Oils, Salt Solutions
No: Chlorine, Acetone, Chlorinated Solvents, Bases Strong, Ethyl Acetate, Water Hotter than 150F
Melting Point: 329F
Maximum Operating Temperature: 170F (Repeated exposure to this temperature will cause fatigue)
Please note that all applications have variables and conditions that will affect the maximum working pressures. Testing suitability for your application is always recommended.
Lockwood Products Inc. does not warrant any particular application for it's products.
81206 – 3″ Thin Wall PVC DWV Sch. 30 Adapter – Pack of 1
DWV * Drain-Waste-Vent


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In order to establish greater interest in Lego for girls while appreciating the economic restraints set upon families in an increasingly difficult economy, I recommend that Lego consider a Modular Dollhouse line in minifigure scale. I need a better, mass appeal name for such a line/theme. 'Your Lego Home'.
In the sense that Corner Cafe was modular with Green Grocer, this theme would be a modular system for creating a single building.
Building in minifigure scale means more value, compared to the cost and size of bellville sets/parts. Also, being smaller means being affordable. Modularity incentivizes future purchases.
Sets could vary in size, but the smallest could start around 10 USD, and follow a closely ratcheted scale of 5 dollar increments going no higher than 50.
Each set would compromise enough parts to build a room, with enough parts to build at least 3/4 of a roof. Brick built furniture encouraged.
Alternative models and composite model instructions are a must. Hinge bricks and snappers would work fine for attaching multiple sets together.
A 50 USD set could contain 1/2 a house with a hinge in the middle, and smaller sets could easily attach to one side or the other of that big set.
This is also an opportunity for Lego to produce baseplates in new colors (could pretend it were carpet, but can also be tiled):
16x16 Dark Pink Baseplate
16x16 Dark Orange
16x16 Orange Baseplate
16x16 Red Baseplate
16x32 Dark Tan Baseplate
16x32 Dark Green Baseplate
16x32 Sand Blue Baseplate
Successive seasons of product could focus on different architectural styles.
Set Breakdown:
10USD Small Bedroom
15USD Library/Den
20USD Kitchen
25USD Entertainment Room. Pool table?
40USD Garage + Laundry. Bicycles (green ones!) and a nice brick car.
50USD Half a House. Staircase, bedroom, bathroom, dining room, living room.
Feedback welcome.


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Runaway Bride
Joannie Bertucci 10/18/2011 10:19:20 PMJulia Roberts never looked so lovely as a runaway bride! :-) Stunning floral Stacey and a marvelous finalist, congrats! #1416474
Stacey J. Meanwell 10/19/2011 3:37:41 AMThank you very much!! #9746031
Susan D. Royce 10/19/2011 5:15:06 AMGreat title and photo! Congratulations on your lovely finalist, Stacey. #9746294
The Judges at BetterPhoto.com 10/19/2011 11:34:35 AMUnique flower. #9747825
Merna L. Nobile 10/30/2011 10:26:37 AMMay your heart catch the joy of the moment and soar!
Stiletto Magnolia
Exif: F Number: 5.6, Exposure Bias Value: 0.00, ExposureTime: 1/500 seconds, Flash: did not fire, compulsory flash mode, ISO: 400, White balance: Auto white balance, FocalLength: 180.00 mm, Model: Canon EOS 5D
Uploaded on 9/30/2011 4:37:10 AM
Copyright for this gallery photo belongs solely to Stacey J. Meanwell. Images may not be copied, downloaded, or used in any way without the expressed, written permission of the photographer.
Log in to follow or message this photographer or report this photo.


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New Duke-based Integrative Health Coaching program
A free introduction talk about a new Duke-based Integrative Health Coaching program will ne held from 2-3:15 p.m. Saturday, Jan. 19 at the Center for Integrated Health and Healing, 89 Medical Park Drive, Brevard.
Speaker Leslie Morrill is a graduate of Duke Integrative Medicine's Health Coach training and a registered yoga therapist who has practices in Hendersonville and Brevard. She will explain the structure and benefits of the person-centered, non-clinical group program.
Participants may pre-enroll for the program at this time. To reserve space for the free talk, call 828-333-1537.
Republican Women Luncheon Jan. 22
The Henderson County Republican Women Luncheon will be held from noon to 1:30 p.m. Tuesday, Jan. 22 at the Cedars, 227 7th Ave. W., Hendersonville.
This month's meeting will feature guest speaker Susan Myrick, elections analyst with the Civitas Institute. She has more than 25 years of experience in campaigns and elections and is one of the leading experts on election matters in North Carolina.
In addition to her policy work, Myrick has experience with political campaigns and a decade of experience working for a county board of elections. Election reform is at the heart of the work she is doing with Civitas.
Myrick believes that the state's same-day and last-minute voter registration processes "are seriously flawed.
Myrick will briefly address four other facets of Civitas work before discussing the need for election reform in North Carolina. Those areas will include pro-growth tax reform; ramifications of the Racial Justice Act; expanding educational freedom; and Obamacare–state exchanges.
Send all luncheon reservations in by Jan. 18 and make checks payable in the amount of $14 to JoAnne Thomas. Note "Cedars" in the memo and mail to 5505 Wood Duck Way, Hendersonville, NC 28792. Call 828-685-0467 for more information.
Nominees accepted for Appalachian Trail Hall of Fame
Nominees for the Appalachian Trail Hall of Fame will be accepted now through Feb. 28 to recognize those who have made a significant contribution toward establishing and maintaining the 2,184-mile footpath that passes through 14 states from Maine to Georgia.
"This year, the third class to the Appalachian Trail Hall of Fame will be inducted," said Larry Luxenberg, president of the Appalachian Trail Museum Society, which oversees the Hall of Fame. "Nominees for 2013 should be people who have unselfishly devoted their time, energy and resources toward making the Appalachian Trail a national treasure."
Visit www.surveymonkey.com/s/BMVRMHX to submit nominees. Visit www.atmuseum.org for more information.
Community Briefs: Jan. 7
New Duke-based Integrative Health Coaching program


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Quest Award
From MeritBadgeDotOrg
Ranger, Quest, and TRUST Awards with cross-references for related Venturing Awards.
|Quest Award
Award is pinned immediately
above the seam of the left pocket.
The Venturing Quest Award builds directly on the Sports Bronze Award. It focuses on the traditions of sportsmanship and lifelong fitness. By teaching about non-traditional sports, this award allows Venturers to learn skills and fitness techniques they might never have a chance to encounter before.
After completion of the Quest Award, a medal may be awarded at a crew recognition ceremony (similar to a Boy Scout Court of Honor), organized by the youth Vice President - Administration.
Venturers may also earn:
- Sports Bronze Award
- Religious and Community Life Bronze Award
- Arts and Hobbies Bronze Award
- Outdoor Bronze Award
- Sea Scout Bronze Award
- Expert-level awards
In addition, four of the five bronze awards fulfill partial requirements for Venturers continuing on and earning expert-level awards:
- The Sports Bronze Award requirements are part of the Quest Award.
- The Religious and Community Life Bronze Award part of the TRUST Award.
- The Outdoor Bronze Award part of the Ranger Award.
- The Sea Scout Bronze Award is a duplicate of the Sea Scout Ordinary rank requirements, and is necessary on the trail to earning the Quartermaster Award.
Quest Award requirements
Complete requirements 1-5 and one of 6–10.
Quest Electives
View the change list (history) of these requirements. The text of these requirements may be locked. In that case, they can only be edited by an administrator.
Please note any errors found in the above requirements on this article's Talk Page.
- Venturers may complete requirements for the Sports Bronze Award and the Quest Award concurrently; however, a completed single requirement cannot be awarded as multiple credit to these two awards.
|Venturing portal
Related awards
Personal Development Awards
|Personal development-related awards
Sports Awards
|Sports-related awards
External links
- Venturing Bronze Award on the BSA scouting.org site.
- Venturing Quest Award on the BSA scouting.org site.
Program-level awards: Venturing Award • Discovery Award • Pathfinder Award • Summit Award
Expert-level awards: Quest Award • TRUST Award • Ranger Award
Boy Scouting ranks: Advancement for Venturers • Star rank • Life rank • Eagle Scout rank Award


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Posted 7 years ago
(16 items)
I am wondering if anyone would know an approx value of this box. There is no phonograph just the box don't know how rare this might be to find. I do know that the item that was in here would play the 78" records. Thanks for any help you can give.


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Check our map for the latest possible date to order for your region.
The most commonly found garden Iris is the bearded German Iris (I. germanica) and its numerous cultivars. Tall Bearded Iris begin blooming in early May in most parts of the US, and continue through mid-June, depending on weather. Tall Bearded Iris range in height from 28" to 48"! Modern hybrids of the Tall Bearded Iris carry wonderful combinations of color, form and bloom habits. We test hundreds of varieties in our fields to ensure that we offer our customers only the best plants on the market.
TIP: You can sort these pages by different characteristics, such as height or color, to help with your search.
-Maybe Next Season-
© Copyright 2018 Schreiner's Iris Gardens. All rights reserved. | Responsive Website Design by HEROweb | hosted eCommerce powered by MightyMerchant v5.3


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tell me more abt iso e super
Happy birthday! i wore Dzing! one day last week and thought of you. you know i bought it all because of you
Basenotes is an online guide to perfume and fragrance, featuring news, a database of fragrances, perfume glossary, fragrance forums, user reviews and more.


text: Reef is the world's leader in authentic, surf-inspired footwear for guys and girls. Reef enjoys a unique blend of surf and sensuality combined with fashion sensitivity. All of this blends together to create a vibrant, irreverent brand identity. Since the company's founding nearly 24 years ago, the product offering has expanded beyond footwear to include guy's apparel with some exciting new category offerings on the way. Spring 2008 marked a tremendous milestone in the Reef brand's history with the launch of girl's swim, sportswear and closed toed shoes. Reef is truly a lifestyle resource for fashionable, comfortable and innovative, quality product offerings that can be found on 5 continents and in over 100 countries around the world.


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|MS Word (32 KB)
April 19, 1993
Mr. Daniel R. Boehmer
Vice President, Servicing
Student Loan Marketing Association
1050 Thomas Jefferson Street, N.W.
Washington, D.C. 20007-3871
Dear Mr. Boehmer:
This is in follow-up to our meeting on January 12, 1993, and your subsequent letter of January 13, 1993. You have inquired whether release of personally identifiable information from student education records to a proposed student loan "Clearinghouse" would violate the Family Educational Rights and Privacy Act (FERPA). It is our understanding that the Clearinghouse would be established as an independent, not-for-profit corporation by a broad group of lenders, guaranty agencies and secondary markets participating in the Federal Family Education Loan Program (FFELP) to provide a central depository for information on the enrollment status of student borrowers. The Clearinghouse will enter into agreements with postsecondary educational institutions pursuant to which the institution will designate the Clearinghouse as its agent for the purpose of satisfying the institution's obligations under the FFELP to report information on the enrollment status of student borrowers to lenders and guaranty agencies. It is expected that the Clearinghouse will eventually provide this information directly to the National Student Loan Data System.
Under the proposed structure, the Clearinghouse will maintain an enrollment list containing the student's 1) name; 2) Social Security number; 3) enrollment status; 4) date of status change; and other data required to be disclosed under the FFELP regulations. In order for the Clearinghouse to provide current and accurate information on students' enrollment status to lenders, guaranty agencies, and the Department, it is necessary that participating educational institutions provide this information to the Clearinghouse on all of their students, not just those known by the institution to have applied for or received Federal financial assistance. The reason is that a guaranty agency or lender sends a student status confirmation report only to the educational institution identified in the student's application for aid. When a student transfers from the school that first awarded the student financial aid, or enrolls in a new school after having already entered loan repayment status, the second school often has no knowledge of the student's prior financial aid history. As a result, the guaranty agency or lender does not ask for, and the second school does not report, the current enrollment status of that student. Many of these students fail to obtain deferments on their loans and enter into default status without being located.
The information provided to the Clearinghouse will be obtained from the student's education records. See 20 U.S.C. §1232g(a)(4)(A); 34 CFR §99.3 ("Education records"). FERPA generally prevents a postsecondary educational institution from disclosing information from an education record without the student's prior written consent. 20 U.S.C. §1232g(b)(1); 34 CFR §99.30. One of the specified exceptions to this general rule provides for non-consensual disclosure of information from education records "in connection with a student's application for, or receipt of, financial aid." 20 U.S.C. §1232g(g)(1)(D); 34 CFR §99.31(a)(4). While this specific exception would clearly permit non-consensual disclosure of information to the Clearinghouse of records on students who had applied for or received financial aid, it would not permit disclosure of education records, or information from education records, about students who have not applied for or received financial aid.
However, nothing in FERPA prevents an educational institution from contracting with a person or entity outside the institution to perform services that the institution would otherwise provide for itself. As described above, it appears that the Clearinghouse will be established and operated to perform for educational institutions the reporting of student enrollment status that these institutions are otherwise required to perform under the FFELP. A guaranty agency or lender may ask any educational institution that participates in the FFELP for confirmation of student status, and the institution must search all of its education records in order to respond completely and accurately to that request. We believe that nothing in FERPA prevents an educational institution from entering into an agreement with the Clearinghouse to perform this service for it. Therefore, an educational institution subject to FERPA may disclose to the Clearinghouse information about all of its students, both those that applied for financial aid and those that did not, without prior written consent to the extent necessary to enable the Clearinghouse to perform the student status confirmation services it has been retained to provide on behalf of the institution.
The Clearinghouse should note that the definition of "education records" under FERPA includes records, files, documents, and other materials that are maintained by a person acting for the educational institution. This means that records on students maintained by the Clearinghouse would be subject to FERPA, although it is the educational institution that provided them, and not the Clearinghouse, that is subject to FERPA and liable for any FERPA violations by the Clearinghouse. Before an educational institution enters into this type of agreement, the institution should first be reminded of its recordkeeping obligations under 34 CFR §99.32. Further, the agreement should provide that the Clearinghouse may use information obtained from an institution's education records only for the specific purposes for which it is provided, that is, to report to guaranty agencies, lenders, and the Department on the enrollment status of students who have applied for or received financial aid. The agreement should specify that the Clearinghouse has no authority to disclose any information about students who have not applied for or received financial aid. The agreement should also specify that without the prior written consent of each student, the Clearinghouse has no authority to make any other disclosures of any information from education records, whether or not the student applied for or received financial aid.
I trust that the above information is helpful to you. Should you have additional questions or concerns regarding this matter or FERPA in general, feel free to contact me again.
LeRoy S. Rooker
Family Policy Compliance Office
cc: Mr. Wayne E. Becraft
Executive Director
National Association of
Collegiate Registrars and
Admissions Officers
Mr. William M. Mackie, Jr.
National Council of Higher
Education Loan Programs, Inc.


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Halil Yayla's birds, Gaziantep-Turkey
Video is in mp4 format.
Most Windows Media Players and Real Players will give you an error message playing it.
If not, you might get audio and not vide or the other way around.
If you experience these types of issues and if you like you can download the codec from this site:
I have tested the site and it seems virus free.
With this codec downloaded and ran in your PC you should be able to play all mp4 format videos from now on.


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The Henry and Stark County Health Department announces that a member of
their staff recently attended the 2012 Illinois Immunization and
Communicable Disease Conference.
The Henry and Stark County Health Department announces that a member of
their staff recently attended the 2012 Illinois Immunization and
Communicable Disease Conference. Sandy Sommer, RN Health Department
Director of Clinical Services, attended the conference held recently in
Sommer notes, "By attending this conference, participants obtained new
information in diagnosis, treatment, prevention and management of numerous
communicable diseases; acquired knowledge of infectious disease
interventions from experts in the fields of vaccine preventable disease,
communicable disease and tuberculosis; and learned how to recognize and
respond to emerging infectious diseases."
Areas of interest covered during the 2-Day conference included: Turn
Your World Upside Down: Immunizations, International Travel and STIs; I-Care
Overview: Policies, Benefits and Enhancements of Illinois' Immunization
Registry; The Intersection of Social Media and PublIc Health; Pertussis: Old
Disease, New Dilemmas; and Sharing Tuberculosis, Humans and Other Animals.
Those attending this conference included local and state public health
department officials and staff; community health center, hospital, and
physician clinics medical staff; school officials and nurses; and
immunization and communicable disease specialists.
For more information on the Immunization and Communicable Diseases
Control programs and services available through the Henry and Stark County
Health Departments call the Department at (309) 852-5272 or visit our
website at www.henrystarkhealth.com. or find us on Facebook at Henry and
Stark County Health Departments.


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Eileen McGinnis is a walker.
McGinnis, a Sun City resident who settled in her Willow Brook Village home 10 years ago, rides her bike regularly and plays Pickleball, but putting one foot in front of the other at her own pace and taking in the scenery is her preferred exercise.
"I just enjoy taking my time in walking. It's a great way to see things, especially if you are traveling," she said. "Walking just seems more relaxing."
McGinnis would like her friends and neighbors to experience how simply walking can improve mental and physical health, so it's no wonder that she signed up to be a neighborhood leader in Walk With Ease, a neighborhood walking program coming to Sun City's streets
in October.
"I'm looking forward to it. We all talk about starting new things, and unless you get a group together, you'll do it for maybe a week or two and then you kind of drop out of it," she said. "So I thought [this] would be a good way to get my neighbors to get in some kind of a walking program and get together, meet new people."
Walk With Ease is a free six-week neighborhood walking program offered in partnership with Sun City Hilton Head, the Arthritis Foundation, S.C. Department of Health and Environmental Control and Healthy Aging, and Hilton Head Hospital. The program is for individuals who want to ease into a fitness program, or those wishing to walk with a supportive group and improve their health. Beginning Oct. 1, Walk With Ease participants will walk for one hour three times a week with a Neighborhood Leader through Nov. 9.
"I encourage you to inspire those in your neighborhood who are new to regular physical activity to enroll in the Walk With Ease program," said Cherie Bronsky, the program manager at Sun City Hilton Head. "Our mission with this program is to reach out to those who are not currently active and to help them experience the life-changing benefits of physical activity!"
This is the first year that Sun City has organized a free neighborhood walking program. Bronsky believes this Walk With Ease program it will encourage residents who are new to exercise programs to get out of their homes and start moving.
McGinnis hopes participants will continue walking after Walk With Ease concludes.
"I think it's great that they're doing this. I think it'll be good for a lot of people," she said. "Even though we live in a great environment, I still see a lot of people who need a push. They need some sort of program to get them started on something and maybe meet some people. I hope they'll get committed to some sort of regular walk on their own, or break up into smaller groups and keep doing it."


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David Ruth
Amy Hodges
HOUSTON — (Sept. 4, 2012) — With the national convention right around the corner, the stakes have never been higher for the Democratic Party. Rice University historian Douglas Brinkley and political scientists Paul Brace, Mark Jones and Robert Stein are available to comment on the convention set for Sept. 4-6 in Charlotte, N.C.
Brinkley, a fellow in history at Rice University's Baker Institute for Public Policy and a professor of history, can comment the history of political parties and party conventions in the United States and their impact on the race for president.
Brace, the Clarence L. Carter Professor of Political Science, can discuss the American presidency, political parties, conventions, public opinion polls, electoral politics and candidates' positions on the various issues.
Jones, chair of political science and a fellow at the Baker Institute, can comment on local news angles, including Texas' role in the conventions.
Stein, the Lena Gohlman Fox Professor of Political Science, can discuss public opinion polls, voting behavior, electoral politics and public policy.
Rice University has a VideoLink ReadyCam TV interview studio. ReadyCam is capable of transmitting broadcast-quality standard-definition and high-definition video directly to all news media organizations around the world 24/7. For more information or to schedule an interview with Brinkley, Brace, Jones or Stein contact Amy Hodges at email@example.com or 713-348-6777.
This news release can be found online at http://news.rice.edu/2012/09/04/rice-experts-available-to-comment-on-party-conventions.
Follow Rice News and Media Relations via Twitter @RiceUNews
Related materials:
Douglas Brinkley bio: www.bakerinstitute.org/personnel/fellows-scholars/dbrinkley
Robert Stein bio: www.bakerinstitute.org/personnel/fellows-scholars/rstein
Mark Jones bio: www.bakerinstitute.org/personnel/fellows-scholars/mjones
Paul Brace bio: www.ruf.rice.edu/~pbrace
Located on a 300-acre forested campus in Houston, Rice University is consistently ranked among the nation's top 20 universities by U.S. News & World Report. Rice has highly respected schools of Architecture, Business, Continuing Studies, Engineering, Humanities, Music, Natural Sciences and Social Sciences and is home to the Baker Institute for Public Policy. With 3,708 undergraduates and 2,374 graduate students, Rice's undergraduate student-to-faculty ratio is 6-to-1. Its residential college system builds close-knit communities and lifelong friendships, just one reason why Rice has been ranked No. 1 for best quality of life multiple times by the Princeton Review and No. 4 for "best value" among private universities by Kiplinger's Personal Finance. To read "What they're saying about Rice," go to www.rice.edu/nationalmedia/Rice.pdf.
If you do not wish to receive news releases from Rice University, reply to this email and write "unsubscribe" in the subject line. Office of News and Media Relations – MS 300, Rice University, 6100 Main St., Houston, TX 77005


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Professional Training and Community Engagement at Alliant
Successful professionals understand and address the needs of the communities in which they work. Alliant's commitment to community engagement underscores our mission to train professionals who are able to work on issues and solve real-world problems in the communities in which they work. Our students tell us that among the activities that excite them the most about their education at Alliant is the prospect of making a real difference in the lives of the individuals, families, schools and organizations they encounter. In fact, many of our students describe this part of their education as the vital connection to the very passion that drew them to school in the first place.
We encourage all of our students to engage in community-based projects during their time at Alliant, and many of our programs actually require such projects or activities. In addition to benefiting the community, such projects help students learn to grapple with real-world, current and often the toughest social problems of today. It is not uncommon for the community work begun while a student to be continued long after graduation by our alums in their professional practices.
Alliant's consulting centers, clinics, placements in community service agencies and partnerships with school systems are some examples of how Alliant engages the community everyday.


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A Christian apologetics ministry dedicated to demonstrating the historical reliability of the Bible through archaeological and biblical research.
This article was originally published by Dr. Hasel in 1992, and was reproduced in Bible and Spade with permission. Though the article is 20 years old, it has still significant information about the Book of Daniel found amongst the Dead Seas Scrolls. Most importantly, the existence of Daniel in the DSS disproves the skeptical position that Daniel was originally written in the 2nd century BC. This position has been taken by skeptics to avoid the detailed prophecies in Daniel that ultimately came to pass, strong evidence for the divine authorship of Scripture.
The Dead Sea Scrolls have demonstrated that the Old Testament was accurately transmitted during this interval. In addition, they provide a wealth of information on the times leading up to, and during, the life of Christ...
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