text:
|Publication number
|Publication type
|Application number
|Publication date
|May 10, 2011
|Filing date
|Nov 14, 2006
|Priority date
|Nov 14, 2006
|Fee status
|Also published as
|Publication number
|Adam Bastian
|Original Assignee
|Howmedica Osteonics Corp.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (69), Classifications (6), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates to an apparatus for aligning medical instruments such as a cutting blade during a surgical procedure. More particularly, the present invention relates to an apparatus for aligning a resection guide for use in arthroplastic surgery of a patient's knee.
Arthroplasty is a known surgical procedure for replacing the knee joint which has been damaged due to disease or trauma. Total knee arthroplasty involves the replacement of portions of the patella, femur and tibia with artificial knee prostheses. In these prostheses, the articular surfaces of the bones are "resurfaced" with articular bearing components. One important aspect of these procedures is the correct resection of the bones. These resections must provide planes which are correctly angled in order to properly accept the prosthetic components.
Recently, various computerized navigation systems have been introduced to aid the practitioner during different surgical procedures. These systems include multiple video cameras which are deployed above the surgical site and a plurality of dynamic reference frame (DRF) devices, also known as trackers, which are attached to body parts and surgical instruments. The trackers can be LED devices or reflective spheres which are visible to the cameras. These trackers are attached to body parts and the surgical instruments and preferably include light emitting devices, such as light emitting diodes which are visible to the video cameras. The trackers communicate position information to a camera system located in the operating room. The camera system is connected to a computer which tracks the location of the tracker and the patient and displays the relationship on a CRT. Using software designed for a particular surgical procedure, a computer receiving input from the cameras guides the placement of surgical instruments such as cutting blocks for bone resection.
When using resurfacing type knee prostheses, the articular surface of the distal femur and proximal surface of the tibia are resurfaced with artificial knee components. Various apparatus are available to the surgeon for assisting in guiding a medical instrument such as a cutting blade for marking the femoral and tibial cuts which establish the desired resected surfaces. United States Patent Application Publication discloses one such apparatus for aligning the instruments during surgery. However, the disclosed apparatus is mechanically complex, and cumbersome and not intuitive to use. U.S. Pat. No. 5,681,316 is another example of a resection guide that is complex, cumbersome and not intuitive to use. Thus there is a need for a simple, easy to use and intuitive adjustable resection guide for aligning medical instruments during surgery.
The present invention overcomes the deficiencies of the prior art and provides a resection guide that is very simple in construction and simple and intuitive to use. The resection guide of the present invention has an alignment barrel having holes that pass through the entire cross-section of the alignment barrel. The longitudinal axis of at least two of the holes may be angled with respect to each other. By making the holes angled with respect to each other, locking of resection guide is enhanced. The alignment barrel also has a section that is of smaller cross section than the rest of the alignment barrel.
An alignment guide is mounted on the alignment barrel. The alignment guide may be mounted on the smaller section. The alignment guide can translate and rotate with respect to the alignment barrel. The alignment guide has holes that extend through it. The holes may be in a single row or may form more than one row or may be staggered. The holes are at a fixed distance from each other, for example, each hole is spaced 2 millimeters from the hole or holes next to it. The holes on the alignment barrel and the alignment guide are sized to allow a pin or a nail to be inserted through them. A resection plate is located at one end of the alignment guide.
The resection plate has a resection surface and a back surface. The resection plate has a wall extending from the back surface. The wall surrounds an opening that passes through resection plate. A tracker may be mounted in the opening.
In use, the resection guide is mounted on appropriate surface of a bone, for example, a distal femur as shown in
Once the resection guide is properly located on the anterior surface of the femur, a nail or bone pin is driven through one of the holes on the alignment barrel. The nail attaches the resection guide to the bone and fixes the resection surface in the medial-lateral direction and stops rotation of the resection surface so as to fix the internal-external rotation angle of the resection surface. However, at this time, the resection surface is not fixed in two planes, i.e., the resection surface can translate back and forth in the distal-proximal direction and it can also translate up and down along the length of the nail. Additionally, the resection surface can rotate around the nail and also around the alignment barrel.
Next, using the navigation system, the resection surface is positioned in position corresponding to correct varus/valgus rotation and a second nail is driven through another hole on the alignment barrel locking in the varus/valgus rotation. At this time, the resection surface is free to translate in the distal-proximal direction and rotate around the alignment barrel for adjustment of flexion-extension angle. Next, the resection surface is moved in distal-proximal direction to its correct position, and rotated to correct flexion-extension angle and a third nail is driven through one of the holes on the alignment guide. At this time, the resection surface is fixed in all three translational and all three rotational degrees of freedom. Next, the distal end of the bone is resected using the resection surface as a guide for the resection tool.
As used herein, when referring to bones or other parts of the body, the term "proximal" means closer to the heart and the term "distal" means more distant from the heart. The term "inferior" means toward the feet and the term "superior" means towards the head. The term "anterior" means towards the front part of the body or the face and the term "posterior" means towards the back of the body. The term "medial" means toward the midline of the body and the term "lateral" means away from the midline of the body.
An alignment guide 34 is mounted on alignment barrel 22. Alignment guide 34 may be mounted on section 32. Alignment guide 34 can translate and rotate with respect to alignment barrel 22. Alignment guide 34 has a rail 36 attached to a resection surface 38. Rail 36 may be attached to resection plate 38 at a right angle. Rail 36 has an upper section 40 and lower section 42 connected by a middle section 44. A slot 46 is formed in middle section 44. Slot 46 can house middle section 32 of alignment barrel 22, thereby allowing the alignment guide 34 to rotate and translate around alignment barrel 22. However, alignment guide 34 may be mounted on alignment barrel 22 in any manner that allows alignment. guide 34 to translate and rotate with respect to alignment barrel 22. Alignment guide 34 has holes 48 that extend through it. Holes 48 may be in a single row or may form more than one row or may be staggered. Holes 48 are at a fixed distance from each other, for example, each hole 48 is spaced 2 millimeters from the hole or holes next to it. Holes 28 and 48 (
Resection plate 38 has a resection plane or surface 52 and a back surface 54 proximally facing when guide 20 is mounted on the anterior femur. Resection plate 38 can be of any appropriate shape, for example, rectilinear shape. Resection plate 38 has a wall 56 extending from back surface 54. Wall 56 surrounds an opening 58 that passes through resection plate 38. Wall 56 has one or more smaller openings 60. The axis of openings 60 are at on angle, for example, 90� angle, to the axis of opening 58. In use, a tracker 62 may be mounted in hole 58. The portion of tracker 62 that snaps into opening 58 has balls on its surface. These balls snap into openings 60 to provide a firm seating for tracker 62 in the opening 58. Tracker 62 may be mounted using any other appropriate structure formed on the resection guide 20. For example, tracker 62 may be mounted in a groove or on a beam of appropriate cross-section. Tracker 62 can be used with a navigation system to locate resection guide 20 on the bone. However, resection guide 20 can be used without the aid of a navigation system. For example, resection guide 20 may be used with intermedullary or extramedullary alignment devices.
In use, resection guide 20 is mounted on appropriate surface of a bone, for example, the anterior surface of a femur. Resection guide 20 is placed on the bone using a navigation system that detects tracker 62 to locate resection guide 20 in three-dimensional space. The navigation system has software specific to the procedure being performed. The software ensures proper location of the resection guide 20. However, the surgeon can override the location of resection guide 20, as determined by the navigation system. Thus, the surgeon can locate resection guide 20 or resection surface 52 or both in a location he deems appropriate. Resection surface 52, after it is located and fixed in correct position, is used to guide the blade of the resection tool such as an oscillating saw blade 60 (
Referring to
Next, using the navigation system, resection surface 52 is positioned in position corresponding to correct varus/valgus rotation and a second nail 50B is driven through hole 28 on surface 26 and into the bone. At this time, resection surface 52 is free to translate in distal-proximal direction and rotate around alignment barrel 22 for adjustment of flexion-extension angle. Next, resection surface 52 is moved in distal-proximal direction to its correct position, and rotated to correct flexion-extension angle and a third nail 50C is driven through one of the holes 48. At this time, resection surface 52 is fixed in all three translational and all three rotational degrees of freedom. Next, the distal end of the bone is resected using resection surface. 52 as a guide for the resection tool.
In the above description, resection guide 20 is mounted on the anterior surface of the bone. Alternatively, resection guide 20 may be mounted medially or laterally for resection of the distal end of the bone.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. For example, the above description is for distal resection of a femur; however, resection guide 20 may also be used for resection of other bones, such as, for distal resection of tibia. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
|Cited Patent
|Filing date
|Publication date
|Mar 31, 1986
|Apr 12, 1988
|William Fargie
|Tibial cutting jig
|Jan 9, 1989
|Jun 19, 1990
|Dow Corning Wright
|Femoral surface shaping guide for knee implants
|Jan 30, 1989
|Mar 26, 1991
|Dow Corning Wright Corporation
|Tibial surface shaping guide for knee implants
|Oct 18, 1991
|Aug 10, 1993
|Kirschner Medical Corporation
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|Sep 19, 2002
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|Mar 26, 2002
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|Oct 9, 2001
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|Apr 10, 2003
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|Sep 11, 2003
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|Extramedullary fluoroscopic alignment guide
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|Jan 6, 2005
|Kumar Bobba Venkata Siva
|Process for the preparation of 4,4-dimethyl-6-ethynylthiochroman
|Jan 27, 2004
|Jan 27, 2005
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|Apparatus for aligning an instrument during a surgical procedure
|Jul 11, 2003
|Mar 3, 2005
|Ortho Development Corporation
|Knee balancing block
|Jan 13, 2004
|Mar 10, 2005
|Hudson Surgical Design, Inc.
|Methods and apparatus for femoral and tibial resection
|Dec 26, 2003
|Jun 30, 2005
|Steffensmeier Scott J.
|Adjustable resection guide
|Dec 26, 2003
|Jul 7, 2005
|Steffensmeier Scott J.
|Adjustable cut block
|Oct 29, 2004
|Jul 7, 2005
|Haines Timothy G.
|Methods and apparatus for orthopedic implants
|Oct 23, 2004
|Jul 7, 2005
|Haines Timothy G.
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|Nov 15, 2004
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|Adjustable surgical cutting systems
|Jan 14, 2004
|Jul 14, 2005
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|Howmedica Osteonics Corp.
|Knee computer-aided navigation instruments
|Jan 12, 2005
|Aug 18, 2005
|Zimmer Technology, Inc.
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|Feb 23, 2005
|Sep 15, 2005
|Pierre Couture
|Surgical universal positioning block and tool guide
|Nov 2, 2004
|Sep 22, 2005
|Grimm James E
|Navigated orthopaedic guide and method
|Mar 8, 2004
|Sep 22, 2005
|Grimm James E
|Navigated orthopaedic guide and method
|Mar 26, 2004
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|Hayden Adam I
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|Mar 31, 2005
|Oct 20, 2005
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|Oct 20, 2005
|Jody Stallings
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|Mar 9, 2005
|Oct 27, 2005
|Davis Kenneth P
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|Feb 26, 2003
|Nov 17, 2005
|Daniel Delfosse
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|U.S. Classification
|606/87, 606/88
|International Classification
|Cooperative Classification
|European Classification
|Dec 3, 2007
Owner name: HOWMEDICA OSTEONICS CORP., NEW JERSEY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BASTIAN, ADAM;REEL/FRAME:020202/0295
Effective date: 20071127
|Oct 29, 2014
|Fee payment
Year of fee payment: 4


text:
By idontevencareanymore - / Friday 23 May 2014 21:25 / United States - Jarrell
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incoherentrmblr | 21
Like father like son...
Zebediabolical | 36
My short dicked friend in high school once told me 'I may not hit bottom, but I sure beat the shit out of the sides.'
bobslawnservice | 16
If you are a woman who likes the feel of big cocks then having a big cock is important to your sexual satisfaction and it is possible that a small dude is not going to be compatible. Luckily there are many women out there who like different things.
My boyfriends penis is too large. It's about 7.8 inches long. The girth is far more impressive, easily thicker than my wrists. I know they come larger than this but for me, it's far too big. It hurts a lot, every single time. We've only had sex about 20 times and while I know one day I'll be "loose" enough to handle the girth, the feeling of it hitting the end of my canal is the most painful part and I can't imagine that ever being comfortable. i cant sit on him or "ride" him cause theres still like 3 inches of him under me when its all the way in. I usually bleed and pray that it will end quickly. I pretend that I enjoy it more than I do because I love him and want him to have fun and feel good about himself but I don't lie and say it's not painful. He also lasts over 45 minutes. It gets unbearable. since I'm not into it at all it gets very very very tiring, and by the end feels like his dick is coated in sandpaper. #49 his dick must be microscopic if you can't wear a tampon. You're not pushing it in far enough if it's uncomfortable.
KristaAaronn | 25
Even a tic-tac hurts going 100 miles an hour
Ok ok ok WOAH #78 what? my entire comment talks about how bad it is to have a boyfriend with a large penis. i hate it. i hate having sex with him. did you read what i wrote? i would much much much rather half the average size than this. ive never even had an orgasm. im sure your boyfriend satisfies you just fine. i dont even want to be satisfied, i just want to not feel excrutiating pain when i have sex. I don't care what sized penis your boyfriend has, nor do I think it matters for anyone's sex life. about the tampons, i used to be so tight i couldnt wear tampons either. in fact, with a mirror you couldnt even see the hole. my period was all messed up. thsts how closed up i was. it took a very long time for one finger to fit in there comfortably, but once it did i started to wear tampons and i think theyre great. all I meant was you're wearing it wrong. maybe not; maybe they're not right for you. For most woman, when inserted properly you shouldn't be able to feel them at all. I just assumed that if your boyfriends penis is bigger than a tampon, you should be able to wear them. It was a stupid joke... sorry
Ok ok ok. i understand, I sounded like those big girls who post to flat chested girls saying "I hate having double E's I would kill to have tiny boobs blah blah blah" when you know they flaunt it. I must have sounded like such an annoying boasting whore. i didn't mean it that way.
Ok. i stay with him because he'd the most wonderful lovely perfect guy I've ever met. For personal reasons, I always wanted to wait to have sex and after seeing the pain I was in he's decided it's a good idea for both of us. He is so supportive and only wants me to be happy, but I make sure he's satisfied. We've been together for a while and plan on getting married soon. We don't live togerher; but when we get married were going to make sure we sort these issues. I'm going to see a therapist about some personal issues and my fear of intercourse and we're going to try everything to make sure it's an enjoyable experience for both of us. Every other aspect of our lives is perfect and I couldn't be happier with him. He's not worth losing just because I'm not stretched enough yet
mcrlover4ever | 7
Lol it does
JBChristian | 45
OP will have to go John Hancock for that to happen.
By ihaveasushicat | 24
At least you were trying to be supportive and comforting? :( She will probably be embarrassed for telling you that when she's no longer drunk.
Nederlander95 | 14
Yeah that's my bad for not paying attention.
flipthebirdfuxku | 10
My family did the same thing to me, eighty miles from the city we lived in. I feel for you!
kingdomgirl94 | 27
What the fuck is wrong with your families??? How do you not notice a missing person or be enough of an ass to purposely leave someone in the middle of nowhere???
naaudisz30 | 3
.....it's Fml. of course it's our business >:)
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text:
Train of Thought – Millennials
1. 80s music is really strange if you actually listen to the words 2. Monday mornings are hard 3. AF3 club future
One woman's ordinary journey through an extraordinary world
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text:
Unsteady LES Inlet Conditions
Hi everybody!
I'm doing an LES study and I want to use results from a separate LES simulation as the inlet condition. It is suggested in the CFX manual but I can find no description on how to do this. The purpose is to remove the need for a long inlet where the boundary layer develops from the simulation.
Any clues?
Re: Unsteady LES Inlet Conditions
My best guess is that I need to incorporate the results from the previous simulation in a Junction Box routine which can be called from the solver to update the inlet boundary condition.
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text:
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text:
|Publication number
|Publication type
|Application number
|Publication date
|26 Apr 1994
|Filing date
|18 Dec 1991
|Priority date
|18 Dec 1991
|Fee status
|Also published as
|Publication number
|Leon C. Williams, Francis K. Tse, Robert F. Buchheit
|Original Assignee
|Xerox Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Referenced by (24), Classifications (9), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates generally to a digital signal processing apparatus, and more particularly to the control of digital image processing operations which may be applied to an array of digital signals which are representative of an image.
The following related applications and patents are hereby incorporated by reference for their teachings:
"Improved Automatic Image Segmentation", Shiau et al., Ser. No. 07/722,568, filed Jun. 27, 1991;
"Method and Apparatus for Implementing Two-dimensional Digital Filters", Clingerman et al., application Ser. No. 07/809,897 filed concurrently herewith;
U.S. Pat. No. 4,811,115 to Lin et al., Issued Mar. 7, 1989; and
U.S. Pat. No. 4,897,803 to Calarco et al., Issued Jan. 30, 1990.
The features of the present invention may be used in the printing arts, and, more particularly, in digital image processing and electrophotographic printing. In digital image processing it is commonly known that various image processing operations may be applied to specific areas, or windows, of an image. It is also known that the image processing operations to be applied to individual pixels of the image may be controlled or managed by a pixel location comparison scheme. In other words, comparing the coordinate location of each pixel with a series of window coordinate boundaries to determine within which window a pixel lies. Once the window is determined, the appropriate processing operation can be defined for the digital signal at that pixel location. In general, the window identification and management systems previously employed for image processing operations have been limited to rectangularly shaped, non-overlapping windows. In the interests of processing efficiency and hardware minimization, including memory reduction, a more efficient window management system is desired. Accordingly, the present invention provides an improved method and apparatus for the management of multiple image processing operations which are to be applied to a stream of digital signals representing an image.
Previously, various approaches have been devised for the control of digital image processing and window management, of which the following disclosures appear to be relevant:
U.S. Pat. No. 4,760,463
Patentee: Nonoyama et al.
Issued: Jul. 26, 1988
U.S. Pat. No. 4,780,709
Patentee: Randall
Issued: Oct. 25, 1988
U.S. Pat. No. 4,887,163
Patentee: Maeshima
Issued: Dec. 12, 1989
U.S. Pat. No. 4,897,803
Patentee: Calarco et al.
Issued: Jan. 30, 1990
U.S. Pat. No. 4,951,231
Patentee: Dickinson et al.
Issued: Aug. 21, 1990
The relevant portions of the foregoing patents may be briefly summarized as follows:
U.S. Pat. No. 4,760,463 to Nonoyama et al. discloses an image scanner including an area designating section for designating a rectangular area on an original and a scanning mode designating section for designating an image scanning mode within and outside the rectangular area designated by the area designating section. Rectangular areas are defined by designating the coordinates of an upper left corner and a lower right corner. Subsequently, counters are used for each area boundary, to determine when the pixel being processed is within a specific area.
U.S. Pat. No. 4,780,709 to Randall discloses a display processor, suitable for the display of multiple windows, in which a screen may be divided into a plurality of horizontal strips which may be a single pixel in height. Each horizontal strip is divided into one or more rectangular tiles. The tiles and strips are combined to form the viewing windows. Since the tiles may be a single pixel in width, the viewing window may be arbitrarily shaped. The individual strips are defined by a linked list of descriptors in memory, and the descriptors are updated only when the viewing windows on the display are changed. During generation of the display, the display processor reads the descriptors and fetches and displays the data in each tile without the need to store it intermediately in bit map form.
U.S. Pat. No. 4,887,163 to Maeshima discloses an image processing apparatus having a digitizing unit capable of designating desired areas in an original image and effecting the desired image editing process inside and outside the designated areas. A desired rectangular area is defined by designating two points on the diagonal corners of the desired rectangular area. During scanning, a pair of editing memories are used interchangeably to enable, first, the editing of thresholded video data from a CCD and, second, the writing of editing information for use with subsequent video data. The editing memories comprises a memory location, one byte, for each CCD element, said location holding image editing data determining the editing process to be applied to the signal generated by the respective CCD element.
U.S. Pat. No. 4,897,803 to Calarco et al., the relevant portions of which are incorporated by reference, discloses a method and apparatus for processing image data having an address designation, or token, associated with each data element, thereby identifying the element's location in an image. During processing of the image data, the address token for each data element is passed through address detection logic to determine if the address is an "address of interest," thereby signaling the application of an image processing operation.
U.S. Pat. No. 4,951,231 to Dickinson et al. discloses an image display system in which image data is stored as a series of raster scan pel definition signals in a data processor system. The position and size of selected portions of an image to be displayed on a display screen can be transformed, in response to input signals received from a controlled input device. The display device includes a control program store which stores control programs for a plurality of transform operations, such as rotation, scaling, or extraction.
The present invention seeks to overcome the limitations of the systems disclosed in the references by efficiently handling the control and management of the image processing effects selected for specific windows. The present invention also seeks to reduce the hardware complexity and/or memory requirements of such an image processing control system by reducing the amount of non-data information needed to identify the image processing operation that is to be applied to each data element.
In accordance with one aspect of the present invention, there is provided an apparatus for managing the processing of an array of digital signals representing an original image, in order to produce an array of modified digital signals. The image processing apparatus is able to operate on non-overlapping rectangular regions, or tiles, defined with respect to the input signal array, and to thereby identify image processing effects to be applied to the signals lying within the tiles. In response to the identified image processing effects defined for each signal, image processing hardware within the system is selectively enabled to process the signals.
Pursuant to another aspect of the present invention, there is provided an apparatus for managing the selection and control of the image processing effects to be applied to the image data, the apparatus having means for storing the effects within a block of memory which is accessible via an index or pointer value. The apparatus further including means for determining the effect pointer for each of a plurality of non-overlapping tile regions within the image data, and selectively enabling the image processing operations associated with those effects for signals within the regions.
Pursuant to another aspect of the present invention, there is provided a method for controlling the application of a plurality of image processing operations to a stream of digital image signals. The method operates with respect to a set of predetermined, non-overlapping tile boundaries by selectively controlling the utilization of hardware components through which the signals pass.
FIG. 1 is a block diagram illustrating the architecture of a system employing the present invention;
FIG. 2A is an example of an array of image signals which depicts the use of a pair of windows defined within the array, while FIG. 2B further illustrates the division of the image array of FIG. 2A;
FIG. 3 is a detailed block diagram of the two-dimensional (2 D) block of FIG. 1;
FIG. 4 is an illustration of the architecture for the tile control hardware used to implement the present invention;
FIG. 5 is a pictorial representation of the bit allocation of a control register used in the hardware;
FIG. 6 is a pictorial representation of the bit allocation of a window effects register used in the hardware; and
FIGS. 7A and 7B represent a flow chart illustrating the control steps executed by the present invention during processing a stream of digital input signals.
The present invention will be described in connection with a preferred embodiment, however, it will be understood that there is no intent to limit the invention to that embodiment. On the contrary, the intent is to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
The following description includes references to slow-scan and fast-scan directions when referring to the orientation, or directionality, within orthogonal arrays of digital image signals. For purposes of clarification, fast-scan data is intended to refer to individual pixel signals located in succession along a single raster of image information, while slow-scan data would refer to data derived from a common raster position across multiple rasters or scanlines. As an example, slow-scan data would be used to describe signals captured from a plurality of elements along a linear photosensitive array as the array moves relative to the document. On the other hand, fast-scan data would refer to the sequential signals collected along the length of the linear photosensitive array during a single exposure period, and is also commonly referred to as a raster of data. More importantly, these references are not intended to limit the present invention solely to the processing signals obtained from an array of stored image signals, rather the present invention is applicable to a wide range of video input devices which generally produce video output as a sequential stream of video signals.
For a general understanding of the image processing hardware module incorporating the features of the present invention, reference is made to the drawings. In the drawings, like reference numerals have been used throughout to designate identical elements. FIG. 1 schematically depicts the various components of a digital image processing hardware module that might be used in an electroreprographic system for the processing and alteration of video signals prior to output on a xerographic printing device.
Referring now to FIG. 1, which illustrates a possible image processing module architecture, image processing module 20 would generally receive offset and gain corrected video signals on input lines 22. The video input data may be derived from a number of sources, including a raster input scanner, a graphics workstation, or electronic memory, and similar storage elements. Moreover, the video input data in the present embodiment generally comprises 8-bit grey data, passed in a parallel fashion along the input data bus. Subsequently, module 20 would process the input video data according to control signals from microprocessor (μP) 24 to produce the output video signals on line 26. As illustrated, module 20 may include an optional segmentation block 30 which has an associated line buffer (not shown), two-dimensional filter 34, and an optional one-dimensional effects block, 36. Also included in module 20 is scanline buffer memory 38, comprising a plurality of individual scanline buffers for storing the context of incoming scanlines.
Segmentation block 30, in conjunction with its associated scanline buffer, which provides at least one scanline of storage, is intended to parse the incoming video data to automatically determine those areas of the image which are representative of a halftone input region. Output from the segmentation block (Video Class) is used to implement subsequent image processing effects in accordance with the type or class of video signals identified by the segmentation block. For example, the segmentation block may identify a region containing data representative of an input halftone image, in which case a low pass filter would be used to remove screen patterns. Otherwise, a remaining text portion of the input video image may be processed with an edge enhancement filter to improve fine line and character reproduction when thresholded.
Additional details of the operation of segmentation block 30 may be found in the pending U.S. patent application for "Improved Automatic Image Segmentation" (Ser. No. 07/722,568) by Shiau et al., the teachings of which are hereby incorporated by reference in the instant application. Another relevant reference is U.S. Pat. No. 4,811,115 to Lin et al. (Issued Mar. 7, 1989) which teaches the use of an approximate autocorrelation function to determine the frequency of a halftone image area. The relevant portions of U.S. Pat. No. 4,811,115 are hereby incorporated for its teachings with respect to halftone image identification.
One important aspect of incorporating the segmentation block in the image processing module is the requirement for a one scanline delay in video output. This requirement stems from the fact that the segmentation block needs to analyze the incoming line prior to determining the characteristics of the incoming video. Hence, the incoming corrected video is fed directly to segmentation block 30, while being delayed for subsequent use by two-dimensional filter 34, in line buffer memory 38.
Two-dimensional (2 D) filter block 34, incorporating the elements of the present invention, is intended to process the incoming, corrected video in accordance with a set of predefined image processing operations, as controlled by a window effects selection and video classification. As illustrated by line buffer memory 38, a plurality of incoming video data may be used to establish the context upon which the two-dimensional filter and subsequent image processing hardware elements are to operate. To avoid deleterious affects to the video stream caused by filtering of the input video, prior to establishing the proper filter context, the input video may bypass the filter operation on a bypass channel within the two-dimensional filter hardware. Further details of the two-dimensional filtering treatments are included in copending U.S. patent application "Method and Apparatus for Implementing Two-Dimensional Digital Filters", by Clingerman et al. U.S. application Ser. No. 07/109,897, the relevant portions of which are hereby incorporated by reference in the instant application.
Subsequent to two-dimensional filtering, the optional one-dimensional (1 D) effects block is used to alter the filtered, or possibly unfiltered, video data in accordance with a selected set of one-dimensional video effects. One-dimensional video effects include, for example, thresholding, screening, inversion, tonal reproduction curve (TRC) adjustment, pixel masking, one-dimensional scaling, and other effects which may be applied one-dimensionally to the stream of video signals. As in the two-dimensional filter, the one-dimensional effects block also includes a bypass channel, where no additional effects would be applied to the video, thereby enabling the 8-bit filtered video to be passed through as output video.
Selection of the various combinations of "effects" and filter treatments to be applied to the video stream is performed by μP 24, which may be any suitable microprocessor or microcontroller. Through the establishment of window tiles, various processing operations can be controlled by directly writing to the control memory contained within the 2 D block, from which the operation of the image processing hardware is regulated. More specifically, independent regions of the incoming video stream, portions selectable on a pixel by pixel basis, are processed in accordance with predefined image processing parameters or effects. The activation of the specific effects is accomplished by selectively programming the features prior to or during the processing of the video stream. Also, the features may be automatically selected as previously described with respect to image segmentation block 30. In general, μP 24 is used to initially program the desired image processing features, as well as to update the feature selections during real-time processing of the video. The data for each pixel of image information, as generated by the tiling apparatus and video classification described herein, may have an associated identifier or token to control the image processing operations performed thereon, as described in U.S. Pat. No. 4,897,803 to Calarco et al. (Issued Jan. 30, 1990). The relevant portions of U.S. Pat. No. 4,897,803 are hereby incorporated by reference for their teachings with respect to methods for controlling the processing of digital image data.
Referring now to FIG. 2A, which depicts an example array of image signals 50 having overlapping windows 52 and 54 defined therein; the windows are used to designate different image processing operations which are effects to be applied to the image signals in the array. In general, windows 52 and 54 serve to divide the array into four distinct regions, A-D. Region A includes all image signals outside of the window regions. Region B encompasses those image signals which fall within window 52 and outside of window 54. Similarly, region D includes all image signals within window 54 lying outside of window 52, while, region C includes only those image signals which lie within the boundaries of both windows 52 and 54, the region generally referred to as the area of "overlap" between the windows. It is commonly known to use windows, and even overlapping windows, to implement image editing functions for image arrays, or for mapping video displays. It is, however, less commonly known to identify independent and distinct regions within the image which are defined by the overlapping windows. For purposes of discussion, these independent areas or regions are referred to as tiles.
Referring also to FIG. 2B, where image array 50 of FIG. 2A has been further divided into a plurality of independent, non-overlapping tiles, the tiles are generally defined by transitions from the different regions identified in FIG. 2A. For instance, tile 1 is the region extending completely along the top of array 50. Tile 2 is a portion of the region that is present between the left edge of the image array and the left edge of window 52. Continuing in this fashion, region A of FIG. 2A is determined to be comprised of tiles 1, 2, 4, 5, 9, 10, 12, and 13. Similarly, region B is comprised of tiles 3 and 6, region D of tiles 8 and 11, and region C of tile 7. As is apparent from FIG. 2B, the tiles are defined along a fast-scan orientation. In other words, the transitions between regions A, B, C, and D that occur along the fast-scan direction define the locations of the tile boundaries. The directionality of the tile orientation is generally a function of the orientation in which the image signals are passed to image processing module 20.
In the present invention, the resolution of the tile boundaries is a single pixel in the fast-scan direction, and a single scanline in the slow-scan direction. The high resolution of the boundaries enables the processing of windows or regions having complex shapes, and is not limited to the purely orthogonal boundaries typically associated with the term windows. The image processing operations specified for each of the tiles which comprise a window or region are controlled by a window control block present within 2 D block 34 of FIG. 1. The origin of these regular or complex window shapes can be obtained from a variety of sources including, but not limited to, edit pads, CRT user interfaces, document location sensors, etc.
Referring now to FIG. 3, which further details the hardware design for the two-dimensional image processing block, block 34 of FIG. 1, window control block 80 is used to control operation of 2 D filter control block 82, as well as to send a window effects signal to the subsequent 1 D block, block 36 of FIG. 1, via output line 84. In operation, the two-dimensional filter, consisting of blocks 88a, 88b, 90, 92, and 94, generally receives image signals (SL0-SL4) from scanline buffer 38 and processes the signals in accordance with control signals generated by filter control block 82. More specifically, slow scan filter blocks 88a and 88b continuously produce the slow-scan filtered output context, which is selected by MUX 90 on a pixel-by-pixel basis for subsequent processing at fast-scan filter 92. Fast-scan filter 92 then processes the slow-scan context to produce a two-dimensional filtered output which is passed to MUX 94. MUX 94, controlled by filter control block 82, is the "switch" which selects between the filtered output and the filter bypass, in accordance with the selector signal from filter control 82, thereby determining the video signals to be placed on VIDEO OUT line 96.
Referring particularly to the operation of window control block 80, input signals are received from three sources. First, the timing and synchronizing signals are received via control signal lines 98. These signals generally include pixel clocking signals, and are used by both window control block 80 and by filter control block 82 to maintain control of the processed video output. Second, input data is received from microprocessor 24, via lines 100. The input data for filter control block 82 includes the filter coefficients and similar data necessary for operation of the two-dimensional filter. Input to the window control block generally comprises the tile boundary information, window effects data, and the window effects pointers for each of the tiles identified. Window control block 80 is implemented as a finite state machine which operates to selectively enable certain preprogrammed window effects, based upon the location of the video signal currently being processed, in relation to the array of image signals, as determined by corresponding tile boundaries. Third, the input from segmentation block 30 may be utilized, on a tile by tile basis, to override some or all of the window effects data based on the video classification determined by the segmentation block. The override of the window effects data enables the use of image processing operations that adjust dynamically to the image content.
As shown in FIG. 4, window control block 80 also includes random access memory (RAM) 110 which is organized to efficiently enable the real-time selection of the windowing effects to be applied to the video signals being processed by the 1 D and 2 D hardware elements. In the present embodiment, 1 D image processing block 36 receives video signals from 2 D image processing block 34, as well as window effects data from window control 80 within the 2 D image processing block. The 1 D image processing block, in one embodiment, is an application specific integrated circuit (ASIC) hardware device capable of implementing the one-dimensional image processing operations previously described. However, the functionality of 1 D image processing block 36 could be accomplished using numerous possible hardware or software signal processing systems. Moreover, additional functionality, not described with respect to the present embodiment, may be implemented by the windowing effects described. Accordingly, there is no intention to limit the present invention with respect to the functionality or design of the 1 D image processing block described in this embodiment.
Table A reflects the organization of the memory contained in the two-dimensional image processing hardware, block 34 of FIG. 1.
TABLE A______________________________________2D Memory MapAddress(hex) Access Contents______________________________________00 Write only 2D Hardware Reset01 Read/Write Control Register02-03 Read/Write Segment.Window Effects Enable Reg.04-11 Read/Write Filter 1 Coefficients12-1F Read/Write Filter 1 Coefficients20-3F Read/Write Window Effects List40-7F Read/Write Window Tile Lengths List80-9F Read/Write Window Effects PointersA0-A7 Read/Write Segmentation Window Effects______________________________________
The memory banks illustrated in memory 110 include addresses 40-9Fh, while window effects memory 112 comprises addresses 20-3Fh.
Although operation of the hardware will be described in detail with respect to FIGS. 8A and 8B, a brief description follows to provide an understanding of the basic hardware architecture. Ordinarily, the window effect output, line 84, is controlled by the window effects pointer value present on line 114. However, the window effects pointer would have been previously determined by the currently "active" tile, the information which is stored in memory 110. Additionally, address counter 116 and address loop counter 118 are utilized to provide indexing to memory 110 to correctly "activate" the appropriate tile during processing of each scan line. Likewise, FS (fast-scan) Tile Length counter 122 and SS (slow-scan) Tile Height counter 124, both of which are implemented as count-down counters in the present invention, are used to control the sequencing of window control block 80.
By considering FIGS. 4, 5 and 6, in conjunction with Table B1-B3, the details of the memory and control registers may be better understood. The convention employed for indication of binary data values in the following tabular representations of memory places a zero or a one where the binary level of the stored data is known; a "?" where the level is unknown or indefinite; and an "X" where the data bit is unused or unassigned.
Referring initially to FIG. 5, which depicts the bit assignment for the control register present at memory location 01h, the five most significant bits are unused, as indicated by the "X" in bit positions D3-D7. The least significant bit, D0 is used to select the memory bank, bank A or bank B, which is to be accessed when the hardware is initialized. The memory bank selected for initial access will also be the bank that is selected for subsequent programming via read/write access from μP 24 of FIG. 1. Bit position D1 of the control register is used to determine the memory bank, A or B, that is presently being used or accessed by the hardware, referred to as the "active" bank. Finally, bit position D2 is used to indicate to the hardware whether segmentation hardware block 30 has been installed and enabled.
TABLE B1______________________________________Window Effects Memory MapAddr Data(hex)Contents D7 D6 D5 D4 D3 D2 D1 D0______________________________________20 LSB of Window Effect 0 0 0 0 0 0 0 0#021 MSB of Window Effect X X X X 1 0 0 0#022 LSB of Window Effect 1 0 0 0 0 0 0 0#123 MSB of Window Effect X X X X 0 0 1 0#124 LSB of Window Effect 0 0 0 1 0 0 0 0#225 MSB of Window Effect X X X X 0 0 0 0#226 LSB of Window Effect 0 1 0 0 1 0 0 0#327 MSB of Window Effect X X X X 0 0 0 0#328 LSB of Window Effect ? ? ? ? ? ? ? ?#429 MSB of Window Effect X X X X ? ? ? ?#4...3E LSB of Window Effect ? ? ? ? ? ? ? ?#153F MSB of Window Effect X X X X ? ? ? ?#15______________________________________
Referring next to FIG. 6, in conjunction with Table B1, where the significance of bit positions for the window effects memory are illustrated, bit positions D0 through D11 are shown. Bit positions D0 through D7 straightforwardly correspond with the bits of the least significant byte (LSB) for each window. For example, address 22h of Table B1 contains the data for the LSB of Window Effect #1. Furthermore, bit positions D8 through D11 of FIG. 6 represent the associated least significant four bits of the MSB of Window Effect #1, as found in memory location 23h.
As shown by FIG. 6, bit position D0 determines whether the dynamic range adjustment will be carried out on all image signals lying within a tile. Typically, this adjustment would remap the input video signal to modify the range of the output video signal. Using Window Effect #1, as an example again, at bit D0 of address 22h, the binary value shown in Table B1 is a zero. Therefore, all tiles having pointers to Window Effect #1 will have no dynamic range adjustment applied to the video signals within the boundaries of the tile. Similarly, in bit position D1, the window effects memory in FIG. 6 controls the application of a tonal reproduction curve (TRC) adjustment operation. In general, this operation would be used to shift the relationship, or mapping, between an input video signal and an output video signal.
Moving now to consider bit positions D2 and D3 of FIG. 6, the two-bit value is determinative of the masking operation to be employed on the video signals treated by the window effect. As shown, the options include, no masking, masking to a minimum value (black), masking to a maximum value (white), or masking to a user specified value. Next, bit position D4 controls the application of a Moire reduction process to the video signals to eliminate aliasing caused by scanning of an original document with periodic structures (e.g., halftone patterns). In general, this feature injects a random noise signal into the video stream to reduce the periodicity of the input video signal. The threshold and screen selection is controlled by the binary values in bit positions D5 and D6. Selection between thresholded output or screened output is determined by the level of bit position D6, while position D5 selects between the threshold options or the halftone screen options. The last bit position, D7, is the least significant data byte for the window effects controls the video inversion feature. When enabled, this feature performs a simple "exclusive or" (XOR) operation on the video signal, thereby inverting the signal.
The remaining four bit positions are contained in the first four positions of the most significant data byte for each window effects memory location, for example address 23h, for Window Effect #1. Specifically, bit position D8 is used to enable or disable the video output suppression feature that actually acts as a gating device to stop output of the video, whenever the current window effect has the value in this position set to a logical one. From a practical perspective, this feature allows the actual removal of a portion of the video signal stream that lies within the tile, thereby enabling, but not necessarily limited to, image cropping. For example, suppression can also be used to remove undesired areas such as the binding margin when scanning or copying books. Bit positions D9 and D10 are used to select or bypass the two-dimensional filters which are part of the hardware on the 2D block of FIG. 1. Finally, the optional image segmentation hardware, block 30 of FIG. 1, is controlled by bit position D11. Essentially, the binary value in this position determines whether the image segmentation operation will be enabled within the tile using this window effect. As an illustration, consider Window Effect #0 in Table B1 (address 21h). Where bit position D11 contains a one, the segmentation chip would be enabled in all tiles having tile pointers which "point" to Window Effect #0. Hence, those tiles would allow segmentation hardware block 30 to determine the content of the video signals within the tile and thereby automatically select the appropriate image processing operations to be applied to the regions within the tile on a pixel-by-pixel basis. In these regions, some or all of the video effects normally associated with that tile's pointer may be overridden with effects stored within Segmentation Window Effects registers (not shown), locations (A0-A7h), as selected by the video classification (from the segmentation block) for that pixel. The Segment Window Effects Enable Register (02h) controls which effects may be overridden. As an example, it is usually desirable for the segmentation block to control the selection of filter application. However, in some regions of documents, especially forms, if the video is known to be of a specific type, it is desirable to prevent the automatic selection of the filter. Additionally, it is usually not desirable for the segmentation block to control image masking, however, in special applications this feature may be desirable.
Referring also to FIG. 4, in conjunction with Table B2, both of which illustrate details of the Tile Length memory, memory 110 includes tile length memory 140a and 140b in banks A and B, respectively, in addition to corresponding window effects pointer memory 142a and 142b.
TABLE B2______________________________________Tile Lengths Memory MapAddr. Data(hex) Contents D7 D6 D5 D4 D3 D2 D1 D0______________________________________40 F.S. Length - Tile #1 1 1 1 1 1 1 1 1 (LSB)41 F.S. Length - Tile #1 1 1 1 1 1 1 1 1 (MSB)42 F.S. Length - Tile #2 0 0 0 1 1 0 0 1 (LSB)43 F.S. Length - Tile #2 0 0 0 0 0 0 0 0 (MSB)44 F.S. Length - Tile #3 0 1 0 1 1 0 0 1 (LSB)45 F.S. Length - Tile #3 0 0 0 0 0 0 0 0 (MSB)46 F.S. Length - Tile #4 1 1 1 1 1 1 1 1 (LSB)47 F.S. Length - Tile #4 1 1 1 1 1 1 1 1 (MSB)48 F.S. Length - Tile #5 0 0 0 1 1 0 0 1 (LSB)49 F.S. Length - Tile #5 0 0 0 0 0 0 0 0 (MSB)4A F.S. Length - Tile #6 0 0 1 1 0 1 0 0 (LSB)4B F.S. Length - Tile #6 0 0 0 0 0 0 0 0 (MSB)4C F.S. Length - Tile #7 0 0 1 0 0 1 1 0 (LSB)4D F.S. Length - Tile #7 0 0 0 0 0 0 0 0 (MSB)4E F.S. Length - Tile #8 0 0 0 1 0 0 1 0 (LSB)4F F.S. Length - Tile #8 0 0 0 0 0 0 0 0 (MSB)50 F.S. Length - Tile #9 1 1 1 1 1 1 1 1 (LSB)51 F.S. Length - Tile #9 1 1 1 1 1 1 1 1 (MSB)52 F.S. Length - Tile #10 0 1 0 0 1 1 0 0 (LSB)53 F.S. Length - Tile #10 0 0 0 0 0 0 0 0 (MSB)54 F.S. Length - Tile #11 0 0 1 1 0 1 1 1 (LSB)55 F.S. Length - Tile #11 0 0 0 0 0 0 0 0 (MSB)56 F.S. Length - Tile #12 1 1 1 1 1 1 1 1 (LSB)57 F.S. Length - Tile #12 1 1 1 1 1 1 1 1 (MSB)58 F.S. Length - Tile #13 1 1 1 1 1 1 1 1 (LSB)59 F.S. Length - Tile #13 1 1 1 1 1 1 1 1 (MSB)5A Breakpoint #14 (LSB) ? ? ? ? ? ? ? ?5B Breakpoint #14 ? ? ? ? ? ? ? ? (MSB) . . .72 Breakpoint #26 (LSB) ? ? ? ? ? ? ? ?73 Breakpoint #26 ? ? ? ? ? ? ? ? (MSB)74 Breakpoint #27 (LSB) 0 0 0 0 0 0 0 075 Breakpoint #27 0 0 0 0 0 0 0 0 (MSB)76 S.S. Height - Tile #13 1 1 1 1 1 1 1 1 (LSB)77 S.S. Height - Tile #13 1 1 1 1 1 1 1 1 (MSB)78 S.S. Height - 0 0 1 0 0 0 0 0 Tiles #10, 11, 12 (LSB)79 S.S. Height - 0 0 0 0 0 0 0 0 Tiles #10, 11, 12 (MSB)7A S.S. Height- 0 0 0 1 0 0 1 0 Tiles #5, 6, 7, 8, 9 (LSB)7B S.S. Height- 0 0 0 0 0 0 0 0 Tiles #5, 6, 7, 8, 9 (MSB)7C S.S. Height- 0 0 0 0 1 1 0 0 Tiles #2, 3, 4, (LSB)7D S.S. Height- 0 0 0 0 0 0 0 0 Tiles #2, 3, 4 (MSB)7E S.S. Height - Tile #1 0 0 0 0 1 1 0 1 (LSB)7F S.S. Height - Tile #1 0 0 0 0 0 0 0 0 (MSB)______________________________________
While it is conceivable to utilize both banks of memory as one large tile length/pointer table, the present design is intended to enable the use of one bank for control of image processing while enabling the reprogramming of the other bank. By implementing this bank-switching approach for memory 110, the number of possible tiles that are treated within an array of image signals is no longer limited by the size of the memory, because the present system allows for the reprogramming and reuse of both banks, bank A and bank B, during processing of a single image. Table B2 contains an example of the data and organization of one bank of the Tile Length memory, 140a,b. An important feature of the Tile Length memory is the flexibility of configuration, thereby permitting the use of up to thirty tiles across a scanline. Moreover, the number of tiles per scanline could be increased by adding additional memory and address decoding logic.
In operation, one of the two banks is used by the window control state machine to direct the operation of the image processing hardware. More particularly, the Tile Lengths, and the associated Window Effects Pointers are used in conjunction to identify the specific window effects (Table B1) to be applied within each tile boundary. Although direct mapping of tile address and effects is possible, it is usually more efficient to implement the indirection of pointers to effects to minimize the required effect memory. However, this application should not be interpreted as solely limited to this strategy, but, to encompass all forms of tile to effect mapping strategies. Each of the 32 possible tile lengths contained in addresses 40h through 7Fh have an associated four-bit pointer value, as illustrated in Table B3.
TABLE B3______________________________________Window Effects Pointers Memory MapAddr. Window Access(hex) Effect Pointer D7 D6 D5 D4 D3 D2 D1 D0______________________________________80 Tile #1 X X X X 0 0 0 081 Tile #2 X X X X 0 0 0 082 Tile #3 X X X X 0 0 0 183 Tile #4 X X X X 0 0 0 084 Tile #5 X X X X 0 0 0 085 Tile #6 X X X X 0 0 0 186 Tile #7 X X X X 0 0 1 087 Tile #8 X X X X 0 0 1 188 Tile #9 X X X X 0 0 0 089 Tile #10 X X X X 0 0 0 08A Tile #11 X X X X 0 0 0 18B Tile #12 X X X X 0 0 0 08C Tile #13 X X X X 0 0 0 08D Tile #14 X X X X ? ? ? ? . . .9F Tile #32 X X X X ? ? ? ?______________________________________
Whenever a particular tile is identified as the current tile, for example Tile #6, a number, the fast-scan length, of subsequent video signals are processed in accordance with the window effect pointed to by the Window Effect Pointer for Tile #6, shown at address 85h in Table B3. Using the pointer 01h, the window effect at address location 22h-23h of Table B1, Window Effect #1, will be used to control the manner in which the video signals lying within Tile #6 will be processed.
Having briefly reviewed the configuration of the memory in window control block 80, the description will now turn to an explanation of the steps involved in the window control process. In one embodiment, these steps are controlled by a digital logic state machine operating in the window control block hardware, although it is also possible to implement the control structure in software which could then be executed on numerous microcontrollers or microprocessors. The following description assumes that the window control hardware and memory are in an operational state, having been reset and preloaded with tile length data, tile pointers, and window effects, as illustrated by Tables B1-B3. Preloading of the tile length and pointer data is accomplished via an external device, for instance μP 24, which writes data to a nonoperative memory bank via address multiplexer 144b of FIG. 4. Moreover, bank A may be programmed by μP 24 while bank B is being accessed for processing of video signals. The control of this bank switching capability is enabled by the combination of address multiplexers 144a and 144b.
Turning now to FIGS. 7A and 7B, which illustrate the general steps performed by the window control hardware, the process typically begins with initialization step 200, where the tile length and height pointers are initialized. The initialization includes a reset of address counter 116 to initialize the fast-scan pointer to address 40h, and slow-scan pointer to address 7Eh, the two extremes of the Tile Lengths memory (Table B2). In one embodiment, the fast-scan pointer value is maintained by an up-counter, while the slow-scan pointer is maintained by a down-counter. Once initialized, the slow-scan height is read at step 202, and loaded into SS Tile Height counter 124 of FIG. 4, step 204. The SS Tile Height counter, also a down-counter, will be decremented at the end of each complete scanline or raster of video signals. Next, the fast-scan pointer value is read and stored into a holding register (not shown) at step 208. The fast-scan pointer value is maintained in the holding register to allow the system to reuse that fast-scan pointer value at the beginning of each new scanline. Subsequently, the fast-scan length is read from the location pointed to by the fast-scan pointer, step 210, and FS Tile Length counter 122 is initialized with the value stored in the memory location pointed to by the fast-scan length pointer, step 212.
Following counter initialization, steps 200-212, the next pixel, or video signal is processed by the image processing hardware. As previously described, the window effect pointer for the tile in which the pixel is present determines the image processing treatment that the pixel will receive. Once the pixel is processed at step 216, the FS Tile Length counter is decremented at step 218. Next, the hardware determines if the end of the scanline has been reached, as determined from an End-Of-Line (EOL) or similar signal passed to 2 D hardware block 34 on control lines 98. If no EOL signal is detected by step 220, the FS Tile Length counter is checked, step 222, to determine if it has reached zero. If not, processing continues at step 216 where the next pixel within the tile will be processed. If the FS Tile Length counter is at zero, indicating that a tile boundary has been reached, the fast-scan pointer is incremented and the next FS Tile Length is read from the appropriate Tile Lengths memory bank, step 224.
When the end of a scanline has been reached, as determined in step 220, processing continues at step 228, where the SS Tile Height counter is decremented. Next, a test is executed to determine if the previous scanline was the last scanline, step 230, the determination being made once again by analysis of an End-Of-Scan (EOS) or similar signal which undergoes a detectable logic transition when all of the video signals within an input image have been processed. Like the EOL signal, the EOS signal is typically generated by an external source and transmitted to the 2 D hardware block via control lines 98. If an EOS signal has been detected, processing is complete and the window control process is done. Otherwise, the end of the image has not been reached, and processing continues at step 234. Step 234 determines if the SS Tile Height counter has reached zero. If not, the fast-scan tile pointer value previously stored in the holding register is reloaded as the current fast-scan pointer, step 236, and processing continues at step 210, beginning with the first video signal of the new raster. If the SS Tile Height counter has reached zero, the slow-scan pointer is decremented and the fast-scan pointer is incremented, step 238, thereby causing both pointers to point to the next pointer value. Subsequently, the pointers are compared at step 240 to determine if they point to the same location, thereby indicating that the tile length list in the current bank of memory has been exhausted. If the pointer values are equal, the banks may be switched, step 240, to select the previously idle bank as the currently active bank. Subsequent processing would then continue at step 200, as previously described. Alternatively, if the idle bank was not programmed, the system could exit the process. When the pointer values are not determined to be equal by step 240, processing continues at step 202 using the newly established pointer values as indexes into the Tile Lengths memory.
The allocation of memory within banks A and B has been designed to allow maximum flexibility to the electronic reprographics system in programming the control of tile processing. Any combination of fast-scan and slow-scan tile boundaries can be implemented, up to a total of 31 length/height values, with the present memory configuration. The requirement of the previously described embodiment for an intervening, zero-filled tile length, for instance locations 74h-75h in Table B2, is manifest from the test executed at step 240. However, an additional tile length/height value may be included if the test is modified to determine when the pointer values have crossed one another (e.g., when the fast-scan pointer is greater than the slow-scan pointer). Furthermore, the size of the memory banks may be increased to allow additional tile length/height data, however, this would also result in the need for larger pointer values and increased address decoding hardware.
Having described the functionality of the present invention, attention is turned now to an illustrative example of how the window control memory would be programmed to operate on an image array. The example is embodied in FIGS. 2A and 2B, and in Table B1-B3. Referring once again to FIG. 2A, where a pair of overlapping windows are shown in an array of image signals, array 50 was divided into four distinct regions by the overlapping windows. Furthermore, FIG. 2B illustrates how a series of non-overlapping tiles, oriented along the fast-scan direction, may be used to represent all or part of the four distinct regions. As indicated by the shading in FIG. 2A, four distinct image processing operations are to be applied to the four regions defined by windows 52 and 54. Table C illustrates an example of the four image processing effects that might be applied to the four regions of FIG. 2A.
TABLE C______________________________________ExampleWindow EffectPointer Region Effect______________________________________0 h A Segmentation1 h B Filter 1, Threshold 1, Invert Video2 h C Moire Away, Threshold 13 h D Threshold 2, TRC (enabled)______________________________________
Having defined the image processing effects, the window effects memory must be programmed as illustrated in Table B1. For example, Window Effect #1, address 22h-23h, has bits D7 of the LSB and D1 of the MSB set to a binary value of one to indicate inversion and filter selection, respectively. Moreover, the zeros in bit positions D5 and D6 of the LSB indicate a thresholded output using Threshold 1. In a similar fashion, the three remaining window effects are programmed in the window effects memory map. While additional window effects may be programmed at the residual memory locations in the Window Effects memory (Table B1), addresses 28h through 3Fh, they are left as unknowns in the present example, as no regions utilize those effects.
Having divided each of the regions of FIG. 2A into tiles, FIG. 2B, and having identified the window effects to be applied in each region, Table C, the only task remaining in preparation of the window control hardware is programming of tile length/pointer memory 110 of FIG. 4. First, the fast-scan length and slow-scan height of each tile must be determined. The lengths and heights of the tiles may be determined by the following equations:
FS Length=(FS.sub.finish -FS.sub.start);
SS Height=(SS.sub.finish -SS.sub.start).
For instance, Tile 7, has its upper-left corner at location (75,33), and its lower-right corner at (112,50). Hence, the fast-scan length (FS Length) of Tile 7 is thirty-eight and the slow-scan height (SS Height) is eighteen, these values being reflected as binary values in locations 4C-4Dh and 7A-7Bh, respectively, in Table B2. Generally, these values are placed in the appropriate memory locations in tile length memory 140a or 140b, depending upon the active memory bank selection. Second, the window effect identified for Tile 7, pointer value 02h, is written to memory location 86h in the corresponding pointer memory, 142a or 142b. Likewise, the values for Tiles 1 through 13 are calculated and placed in memory 110, to complete the programming operation. The binary values shown in Table B1-B3 are representative of the values which would enable processing of the image signals in accordance with the previous description, and, therefore are representative of a decomposition of overlapping windows into a set of non-overlapping tiles.
In recapitulation, the present invention implements an efficient tile management and control scheme to enable the selection of various image processing effects in complex overlapping windows that are defined within an array of image data. It is, therefore, apparent that there has been provided in accordance with the present invention, a method and apparatus for controlling the processing of digital image signals that fully satisfies the aims and advantages hereinbefore set forth. While this invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.
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|Image processing apparatus having area designation function
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|18 May 2009
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|U.S. Classification
|358/448, 358/443, 358/453, 382/282
|International Classification
|Cooperative Classification
|European Classification
|18 Dec 1991
Owner name: XEROX CORPORATION
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WILLIAMS, LEON C.;REEL/FRAME:005960/0284
Effective date: 19911212
|15 Aug 1997
|Fee payment
Year of fee payment: 4
|13 Aug 2001
|Fee payment
Year of fee payment: 8
|28 Jun 2002
Owner name: BANK ONE, NA, AS ADMINISTRATIVE AGENT, ILLINOIS
Free format text: SECURITY INTEREST;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:013153/0001
Effective date: 20020621
|31 Oct 2003
Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT, TEXAS
Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476
Effective date: 20030625
Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT,TEXAS
Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476
Effective date: 20030625
|5 Aug 2005
|Fee payment
Year of fee payment: 12


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Swift Reports on 2004 Operations, and 2005 Capital Budget
Swift Energy
|Tuesday, February 01, 2005
Swift Energy Company (NYSE:SFY) announced that 2004 production increased approximately 10% to 58.3 Billion cubic feet equivalent ("Bcfe"), with 42.0 Bcfe produced domestically and 16.3 Bcfe produced in New Zealand. This compares to 2003 production of 53.2 Bcfe (33.8 Bcfe domestic, 19.4 Bcfe New Zealand). The Company achieved these increases despite an announced slowdown in 2004 drilling activity in Lake Washington, which was implemented to allow space and time to conduct a proprietary 3-D seismic survey as well as to undertake significant facilities improvements.
Swift Energy's 2004 year-end proved reserves totaled an estimated 800 Bcfe, a decrease of 3% from 2003 year-end estimate of 820 Bcfe. This slight reduction of proved reserves resulted in part from focusing the Company's reduced drilling activity in Lake Washington on close-in proved undeveloped locations that helped optimize production in a high-price environment, but which also resulted in smaller additions to proved reserves.
Capital expenditures during 2004 totaled approximately $190 million, which included approximately $13.9 million of facilities work and $11.5 million of seismic costs. Capital expenditures in 2005 are projected to total between $200 and $220 million, net of dispositions, with much of the activity planned for Southern Louisiana in Lake Washington and the surrounding area.
Terry Swift, CEO of Swift Energy, commented, "Swift Energy's primary focus in 2004 was to grow production through development drilling and take advantage of the record level pricing in the commodity environment. We also expanded our strategic South Louisiana salt dome initiatives and prepared for a 2005 New Zealand exploration program, which we expect will provide a foundation for future reserves and production growth. The South Louisiana initiatives included the completion of the Lake Washington 3-D seismic survey, the purchase of a large adjacent 3-D data set, the construction of processing facilities and the acquisition of two strategic salt dome assets in Louisiana with geology similar to the Lake Washington area. We are pleased with our 10% organic growth in 2004 annual production. Although our 2004 finding and development costs were higher than anticipated, our global three year average finding and development costs(1) remain at approximately $1.47 per Mcfe."
Terry Swift continued, "We believe that with our newly acquired 3-D seismic data, our producing property acquisitions in the Bay de Chene and Cote Blanche Island areas, and our increased production capacity in Lake Washington, we have positioned the Company for 2005 reserves and production growth in the range of 7% to 12% from our core areas along the Gulf Coast and in New Zealand. Swift Energy's 2004 financial results are some of the best in our history, driven by outstanding profit margins."
2004 Production
Swift Energy's total production for 2004 increased approximately 10% to 58.3 Bcfe compared to 53.2 Bcfe produced in 2003. For the fourth quarter of 2004, our record production totaled approximately 15.9 Bcfe with domestic activity contributing approximately 11.3 Bcfe and New Zealand contributing approximately 4.6 Bcfe. This represents a 19% increase from the 13.4 Bcfe of production during the same quarter in 2003 and a 14% increase from the prior quarter in 2004, primarily as a result of completion of certain fourth quarter facility enhancements and well connections in both Lake Washington and New Zealand. Domestically, production grew 28% compared to the same quarter in 2003 and increased 11% from the prior quarter of 2004. New Zealand saw a 1% increase in production from the same quarter in 2003 and a 23% increase from the prior quarter in 2004. The average oil price received by the Company during the fourth quarter of 2004 is expected to exceed $44.00 per barrel globally. Also in the fourth quarter, the Company's estimated average prices received for natural gas are expected to exceed $6.00 per thousand cubic feet ("Mcf") domestically and $2.50 per Mcf in New Zealand, and for natural gas liquids the prices are expected to exceed $24.00 per barrel domestically and $16.00 per barrel in New Zealand.
2004 Reserves
Swift Energy's total proved reserves in 2004 decreased by 3% to approximately 800 Bcfe from 820 Bcfe in 2003, which as mentioned previously, resulted primarily from a slowdown of drilling activity in Lake Washington in order to allow for the implementation of a 3-D seismic survey and facilities improvements in the area. All of the Company's reserves are audited annually by H.J. Gruy and Associates, Inc, independent petroleum consultants. Proved developed reserves represented 56% of the total 2004 ending reserves. Over the past three years, Swift Energy has had average reserves replacement of approximately 205% of production, with a finding and development cost(1) of approximately $1.47 per thousand cubic feet equivalent ("Mcfe"). For 2004, the Company replaced 70% of its production with a finding and development cost(1) of approximately $4.63 per Mcfe. Higher finding and development costs are common during periods of decreased emphasis on step-out drilling. The strategic decision to slow down Lake Washington drilling in 2004 to acquire 3-D seismic for the area, while contributing to the increased finding and development costs in the short-term, will benefit the Company's future long-term drilling program.
Domestic reserves increased slightly to 653 Bcfe compared with 644 Bcfe of domestic reserves in 2003, while Swift focused 63% of domestic drilling on proved undeveloped reserves ("PUD"). Swift Energy's proved reserves in the Lake Washington area in Plaquemines Parish, Louisiana, increased 4% to 45.4 million barrels of oil equivalent (or 272.5 Bcfe) from 43.5 million barrels of oil equivalent (or 260.9 Bcfe) a year earlier, the largest increase in any of Swift Energy's core properties and the focus of the majority of the Company's 2004 capital expenditures, which were approximately $72.5 million in this area in 2004. This amount includes the seismic shoot in the third quarter which has just finished initial processing. This domestic reserves total also includes 43.4 Bcfe of proved reserves attributable to the recent South Louisiana acquisitions, which were closed at year-end.
In New Zealand, 2004 proved reserves declined by 16% to 147 Bcfe from 176 Bcfe in 2003. The main reason for the decline was that Swift Energy's 2004 drilling campaign was focused entirely on development drilling for PUD conversion and also a downward revision related to the Tariki and Manutahi sands in the Rimu/Kauri area.
2005 Capital Expenditure Budget
Swift Energy currently plans to spend $200 to $220 million in total capital expenditures in 2005, net of dispositions. There are not any acquisitions currently included in the 2005 capital budget. Approximately 80% of the budget is targeted for domestic activities, primarily in Southern Louisiana near Lake Washington and the surrounding area, with about 20% planned for activities in New Zealand. As previously mentioned, $15 to $20 million will be focused on activity at the newly acquired properties, Bay de Chene and Cote Blanche Island. The above amounts are net of approximately $5 to $15 million of non-core property dispositions that are planned for later in 2005. Swift's 2005 capital expenditures will begin at the low end of the range, and depending on commodity prices and operational performance, they may increase to the high end of the range.
Domestic Operations Update
During the fourth quarter 2004, Swift Energy completed the data acquisition phase of its 3-D seismic project in Lake Washington and began to process and correlate this data, which will play a key role in the Company's drilling program for 2005 and beyond. Swift Energy recently added a second drilling rig in the Lake Washington area and is continuing its focus on long-term planning for production growth and the enhancement of facilities in this field. The Company is in the planning and design stages to expand capacity at two of its production platforms, the CM3 and the 6700 platforms. The CM3 platform in the southern portion of the field processes sour crude production and is currently at capacity, while the 6700 platform is located in the central portion of the field and processes sweet crude and is near capacity. These expansions are expected to be completed in the third quarter of 2005.
Swift Energy drilled thirteen wells domestically in the fourth quarter of 2004 with eight successes. In the Lake Washington area, the Company successfully drilled two of three development wells and two of six exploration wells, all based on subsurface geology. Three of these wells are waiting on completion procedures. Swift Energy also completed two development wells in the AWP Olmos area in McMullen County, Texas and also successfully drilled a South Texas development well in Goliad County, Texas. In addition, Swift participated in the successful drilling of a well in Alabama that was operated by another company.
New Zealand Operations Update
In the fourth quarter of 2004, the Tariki-D1 well was drilled to a total depth of 8,570 feet and was completed in the Tariki sand. The Tariki-D1 well is currently cleaning up on a long-term production test with initial flow rates of approximately 1.0 million cubic feet per day, with 280 barrels of liquid per day. Further testing and evaluation will be required to establish production levels. Swift Energy also drilled the Kauri-E7 to a total depth of 9,843 feet. This well was completed in the Kauri sand and is waiting on fracture stimulation scheduled in the second quarter 2005. Swift Energy is currently drilling the Kauri-E8A well in the Rimu-Kauri area and the Karaka-A1 well, a shallow exploration well, as part of the Ballance JV on Petroleum Exploration Permit 38742 in the northern Taranaki Basin.
Company: Swift Energy more info
- Oil, Gas Companies Lay Off More Workers in Texas (Jan 18)
- Swift Energy Company CEO, CFO to Retire (Aug 10)
- Swift Energy Emerges From Bankruptcy (Apr 25)
- Oil, Gas Companies Lay Off More Workers in Texas (Jan 18)
- Swift Energy Company CEO, CFO to Retire (Aug 10)
- Swift Energy Emerges From Bankruptcy (Apr 25)


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Let me start with a kind thank you to Cécile Ribon, our incredibly talented and very artistic designer at Freshly Made Sketches, has created an interesting sketch for us this week. I say interesting because it has my nemesis, multiple circles. Sigh. All things considered, I think it turned out okay. Despite my phobia with circles, I got so involved in those that I missed a couple important points of the sketch, the division of the panel with a top and bottom and the sentient in the lower left corner. So, I'm not a very good example; don't forget to take a good look at the actual sketch below.
I saw this really cool video by Becca Feeken on adding foil borders to die cuts and I really wanted to try it. It shows how to use a Mini Minc and Circle Dies to create these foil bordered circle cutouts. NOTE: I used Nestabilities Dies for this project; the dies have the cutting edge in the middle of the dies and therefore, leaves a border on both the main panel and the cutout. I'm having some issues with my toner pritnter and that makes issues with the foil sticking solidly. I still have lots of learning and practicing to do with my Minc.
Anyway, for easy placement of the stamped images, I drew a circle with pencil around each hole onto the cardstock that would be behind it, stamped the images in Smoky Slate (exception: sentiment in Garden Green) and colored them with Prismacolor Watercolor Pencils. No water. Sidenote: It's soooooooo relaxing to stamp it up and take it out on the lanai to color while enjoying this glorious weather.
There are lots of tiny little places to add glitter and Glossy Accents… noses and eyes, string of lights, stars and ornament.
Here's the sketch that you really should follow more closely than I did!
I hope that you look at this sketch and say "Oh, cool!" and run to your craft room with an overabundance of ideas! But, first, don't forget to jump over to Freshly Made Sketches to see awesome designs that follow the sketch! I hope I see you in the gallery this week! Remember, stamping is therapeutic, so make sure you get lots of stamping time throughout the holidays!
Happy Stamping!


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Coastal Coffee Tables – As thrilling as it may possibly be to finally be capable to fulfil your lifelong dream of building your very own beach home, it is essential that you pursue this project with caution. With a quantity of considerations to make, functioning closely with your creating contractors can assist you make certain that your investment does not go in vain. Considerations you should be generating –
Know your Elevation
Just before you obtain the house, make positive you scrutinize the elevation certificate at great length. While it is unusual, a lot of properties demand that you adhere to 1st floor elevation specifications with regards to height. While this ought to not be a deal killer, remember that the added height to the foundation level may possibly add to your expense.
Bear in mind that land close to the ocean, river or a lake tend to be slightly smaller than ones you discover in landlocked locations. This setback can act as a key challenge when it comes to identifying a home styles that will accommodate your needs.
Understanding your Flood Zones
A massive number of coastal properties fall in flood zones. In most cases, this should not necessarily make you rethink your possibilities. Right after all, you are picking to create a residence by the beach to be close to the waters. Nevertheless, you need to have to understand from the new house builders Sunshine Coast how a lot this will influence your constructing price range. Most typically, creating on an ocean front house is the most high-priced in this regard.
Permissible Height
A expanding quantity of coastal communities all across Australia are amending their building codes to lessen the total permissible height for residential structures. This is to steer clear of the creation of darkness corridors due to high numbers of tall structures in residential localities. This proves to be rather difficult especially given that there is also the require for elevated foundations to accommodate for.
Choosing the Appropriate Design and style
Whilst selecting a design stay away from going the cookie cutter way and take into consideration aspects such as where you house is positioned. If you are moving to the coast, final issue you want to develop is a mountain chalet. Use this developing chance to develop an outstanding residence that looks best in its setting. Make sure your builders are in a position to share with a range of architectural choices.
Design tips to Contemplate
Take into account employing neutral textures, colours and décor items. Consider elements inspired by the sea and nature. Sea grass mats, shells dotted around the shelves, driftwood inspired coffee tables, bamboo blinds and linen curtains can all add to the charm of your beach property. Think about placing a glass hurricane lamp filled with sand and a candle as an crucial accessory for your coastal home.
All beach homes should be made in a way that there is abundance of light. This assists in the achievement of an airy and breezy ambiance indoors. If you are not able to bring in a lot of light, take into account painting your walls white and create minimalistic window designs full with see through curtains that are thin and flowy. Also take into account investing in light furniture and use nautical stripes to add to the coastal appear of your property. You can uncover cushions and all sorts of accessories that come in stripes of all hues. With a dependable designer and architect by your side, you can produce a decorative as well as functional space to reside in.


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Feel free to contact me with any questions.
"Jazz It Up! Two"
"Jazz It Up! One and Two" were made especially for a show entitled "JAZZ TONES" at the Pearl Street Gallery in Hartford, CT. This was a group show with my compadres "The Connecticut Fiber Arts Collective."
All images © by the artist, Karen Loprete, and are not to be copied, reproduced or distributed in any manner.
Last update 4/2/15. Website design by Holly Knott.