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US4937567A - Communication adapter for store loop communication system - Google PatentsCommunication adapter for store loop communication system Download PDF
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Programme control for peripheral devices
- G06F13/12—Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
This is a continuation of co-pending application Ser. No. 06/669157 filed on 11/07/84 now abandoned.
1. Field of the Invention
The present invention relates to communications systems in general and more particularly to devices for attaching devices, such as computers, terminals, I/O devices, etc. to said communications system.
2. Prior Art
The prior art utilizes several different types of communication highways for interconnecting nodes or stations. Each node is adapted to carry one or more data terminal equipment. The data terminal equipment communicates with other data terminal equipment via the medium which forms the communications highway.
The serial loop data communications system is a well known prior art communications highway. The basic serial loop data communications system consists of a length of communication media formed into a loop. The medium may be electrically conductive wires, coax cable fiber optics, conductors, etc. The two extremities of the communication media are connected to a central station which provides supervisory functions for the loop. Other stations which may include computers, terminal devices, etc. are serially connected to the loop. The system configuration is such that a sequence of electrical signals called a message originating at any station on the loop is available on a sequential basis to each active station on the loop. For example, a message originating at the supervisory station is available to the first active station on the loop. The message is next available to the second active station on the loop and so on until it is returned to the supervisory station.
The prior art has also disclosed several different techniques for controlling the loop communications system. U.S. Pat. Nos. 3,752,932 and 4,293,948 describe examples of such prior art control techniques. The patents seem to cover the techniques and procedures under which a station is allowed to dispatch and/or receive messages from the loop.
A necessary element in a loop communications system is the interface circuit arrangement which interconnects a data terminal equipment to the communication medium. The prior art abounds with different types of interface circuit arrangements. One of such circuit arrangements is disclosed in U.S. Pat. No. 4,424,565. In the patent the interface circuit connects a processor to a communication channel. The circuit is programmable and serves to dynamically translate the header portion of a data message on the channel, as it is received and thereby determine whether this data message is to be stored in the processor memory. If the message is to be stored, the interface circuit immediately converts the header field into a hardware address which is used to activate a specific location in the processor memory.
Still other types of communications adapters are disclosed in IBM Technical Disclosure Bulletin, Vol. 22, No. 8A, January 1980 (page 3059) and Vol. 13, No. 5, October 1970 (page 1151). These adapters are geared primarily to produce functions based upon the idiosyncrasies of the DTE and/or the protocol (set of rules used to control data movement on the loop) of the communications system.
It is therefore the object of the present invention to provide a more efficient multifunction communications adapter than was heretofore possible
It is another object of the present invention to provide a multi-function low cost adapter particularly suited to interconnect terminals to a communications highway in which the SDLC protocol is used to facilitate the exchange of messages on said highway.
These and other objects of the present invention are achieved by providing a single chip in which the multiplicity of functions, needed to interface a DTE (such as a point of sale terminal) with a loop communications system, are integrated.
The single chip interface circuit arrangement includes a microprocessor interface circuit means which interfaces the hardware portion of the adapter with a microprocessor. The input to the interface circuit means includes the microprocessor data bus and a plurality of control lines which are set and/or reset by the microprocessor. An interrupt line couples the adapter chip to the microprocessor. An internal data bus system and control line couples a plurality of control registers with the microprocessor interface means. The registers are used to store receive/transmit data, command data and status information. The contents, i.e., bit setting and/or resetting, in some of the registers, are provided by hardware circuitry. The contents reflect certain conditions detected on the loop or conditions inherent in the adapter. Similarly, bits in some of the registers are set as a result of signals presented at the microprocessor interface by the microprocessor. An internal modem interface (IMI) arrangement is coupled to the registers and depending on the setting of the registers and/or the status of the adapter the IMI enables and/or disables the transmitting and/or receiving function of the adapter.
In one feature of the invention a monitoring circuit is provided on the adapter chip and is controlled to observe data on the loop without affecting the electrical characteristics of the data This feature further enhances the reliability of the adapter since the microprocessor can make sure that the adapter clock can be synchronized with data extracted from the loop prior to putting the adapter on line.
The foregoing features and other advantages of this invention will be more fully described in the accompanying drawings.
FIG. 1 shows a schematic of an adapter.
FIG. 1A shows a schematic for a loop communications system. The adapter of the present invention may be used to attach terminals to the loop.
FIG. 2 shows a functional block diagram of the adapter.
FIGS. 3, 3A, 3B show a block diagram of the circuit components used in the adapter.
FIGS. 4, 4A-4D show a graphical representation of the control registers and the function which is generated from each bit in the registers.
FIG. 5 shows a block diagram of the monitoring circuitry.
FIG. 6 is a chart showing the signals necessary to select a particular register.
FIG. 7 is a schematic showing the relays which couple the adapter to the loop and the combinatorial logic circuits which control data flow into the adapter.
FIGS. 8 and 8(a) show logic circuitry which generates certain control signals.
Although the present invention may be used to attach any terminal or station to a loop communications system, it works well when it attaches a point of sale terminal to a loop communications system. As such, the invention will be described in that environment. However, this should not be construed as a limitation on the scope of the present invention since it is the intention that the invention should be interpreted to cover the system disclosed hereinafter and all reasonable extensions thereof
FIG. 1a shows a graphical representation of a loop communications system embodying the teaching of the present invention. The loop communications system includes a communication medium identified by numeral 10. The direction of signal traffic on the loop is unidirectional and is shown by the arrows. A store controller 12 is connected to the loop. The function of the store controller is to supervise the operation of the loop. To this end, the store controller generates poll signals and other necessary control information which enables one or all of the terminals identified by numerals 14 through 19 to transmit information on the loop. It should be noted that although three terminals are shown this should not be construed as a limitation to the scope of the present invention. As a practical matter, the number of terminals on the loop is determined by the size of the business establishment and the capability of the store controller for processing information from a large number of terminals and returning responses on a real time basis.
FIG. 1 shows the apparatus which attaches a terminal and/or the store controller to the communications medium. The apparatus comprises of a controller 18 and an interface circuit means 20. The controller 18 is connected over conductors identified by numeral 22 to the interface circuit means 20. The components of FIG. 1 are used in the terminals while interface circuit means 20 is used in the store controller. The controller 18 comprises of a main system microprocessor 24 which is coupled by a shared RAM interface means 26 to a communication processor identified by numeral 28. The details of controller 18 are given in patent application Ser. No. 637369 filed Aug. 3, 1984, and assigned to the assignee of the present invention. This being the case, details of the controller 18 will not be given here. Suffice it to say that in the preferred embodiment of this invention, microprocessor 24 is the 80286 microprocessor manufactured by the Intel Corporation and the microprocessor 28 is the 8051 microprocessor manufactured by Intel Corporation. Also, the shared RAM interface 26 allows for the passing of commands, status, and messages to be transmitted between the processors and the interface circuit means 20.
Still referring to FIG. 1, interface circuit means 20 includes hardware loop adapter (ADPT) means 30 coupled over electrical conductors to analog signal conversion (CONV) circuit means 32. The arrow depicts the direction in which electrical signals representative of data flow in the system. To this end the signal from the upstream segment of the loop enters into analog signal conversion circuit means 32, flows into hardware loop adapter means 30 from whence the signal can be transmitted over conductor 22 into controller 18 or the signal can be wrapped through hardware loop adapter means 30 and fed back onto the downstream segment of the loop. As will be explained subsequently, this wrapout capability, (i.e., taking data off the loop, wrapping it through the hardware adapter and sending it back on the loop) enables the adapter to check the accuracy of its transmit and/or receive clock before disturbing data flow on the loop.
FIG. 2 shows a functional block diagram for the communication adapter 20. The components which are internal to the broken line show internal components of the adapter while signals and/elements external to the broken line represent signals which exit and/or enter into the adapter. The adapter includes a microprocessor (micro proc) interface means identified by numeral 34. The microprocessor interface means 34 decodes the adapter registers (to be described subsequently) that the microprocessor wishes to read or write during a microprocessor bus cycle. As will be explained subsequently, the input line labeled chip select has to be active for the adapter to perform the decoding function. The microprocessor interface means 34 further includes an 8-bit bidirectional data bus and four control lines. The control lines are negative active chip select (for selecting the adapter), negative active read and write (for bus cycle definitions) and a register (reg) select line which determines whether the command/status registers (to be described subsequently) or the serializer/deserializer registers are being addressed. An interrupt line exits from the interface. The interrupt line becomes active when the adapter wishes to invoke the attention of the microprocessor. An oscillator line enters the microprocessor interface means 34. The function of the oscillator line is to provide basic clock signals to the adapter hardware.
Two sets of control lines adapted to carry control information and identified by numerals 36 and 38 exit the microprocessor means 34 and enters a bank of write registers identified by numeral 40 and a bank of read registers identified by numeral 44. An 8-bit data bus identified by numeral 46 couples the output of microprocessor interface means 40 to write register 40. Similarly, a data bus (8-bit) identified by numeral 48 interconnects the read registers 44 to the microprocessor interface means 34. Status information between write registers and read registers is exchanged on conductor 50. Details of the write and read registers will be given subsequently. Suffice it to say at this point that the read register primarily contains status and data which must be passed up to the microprocessor while the write register contains data to be transmitted on the loop and commands defining functions which the adapter must perform.
Conductor 52 interconnects write register 40 to internal modem interface (IMI) control logic means 54. The signals which are transmitted on conductor 52 from the write registers 40 are primarily control information. Likewise, conductor 56 interconnects the output of internal modem interface control logic means 54 to a bank of read registers 44. The information carried on conductor 56 is primarily status information. As will be explained hereinafter, the function of the internal modem interface control logic means 54 is to generate a modified set of the well-known and conventional RS-232 control signals which are used to enable/disable the receive logic function means 57 and the transmit logic function means 58. To this end, the internal modem interfaces control logic means 54, receives input from write register on conductor 52, inputs from transmit clock and logic means 60 on conductor 62, inputs from received clock and control logic means 64 on conductor 66 and signals on conductor 68 from loop driver circuitry (to be described subsequently). The internal modem interface control logic means 54 also generates control signals which are outputted on conductor 70. The signal on conductor 70 is used for controlling the relay (not shown) which physically connects the station to the loop.
Still referring to FIG. 2, transmit clock and control logic means 60 generates the clocks which are fed over conductor 72 into transmit logic function means 58. The transmit clock and control logic means 60 use an external oscillator (not shown) with a frequency of 14.7456 MHz as a base clock. This output clock is divided down by hardware circuitry to generate a clock used by the transmit logic function means 58. As will be explained subsequently, the adapter is capable of operating in two modes. The so-called primary mode where the station which is connected to the loop is performing the supervisory function on the loop and the secondary mode where the station which is connected to the adapter is not performing supervisory functions.
Stated another way, in the secondary mode the terminal has access to the loop but cannot perform any supervisory functions such as poll, etc. When the adapter is operating in the primary mode, the transmit clock is generated directly from the input oscillator. If the adapter is in the secondary mode, the transmit clock is generated from the input oscillator and the receive data via a phased locked loop. The phase locked loop insures that the adapter will not generate any delays between the data which is being received and those being retransmitted. The transmit logic function means 58 transmits a serial stream of data from the adapter on conductor 76 into logic conversion means 78. The logic conversion means 78 changes the TTL signal to a bipolar signal which is outputted onto the loop. The data which is transmitted from the transmit logic function means 58 uses the clock generated in the transmit clock and control logic means 60. If the adapter is reclocking data, data is received by the adapter and is passed through this function to be retransmitted on the loop. When the microprocessor places data in the serialized register (to be described later) for transmission on the loop, this function will transmit the data one bit at a time at the selected data rate.
This transmission is only done after an end of poll (EOP) character has been detected by the logic function means (to be described subsequently). The transmit logic function means also performs the SLDC bit insertion function. This function is a well known function, details of which are given in U.S. Pat. No. 3,752,932. Suffice it to say at this point that this function places a "0" bit after every string of five continuous one bits in the data portion of a message.
A clock correction feedback signal is generated by the transmit logic function means 58 and is fed back on conductor 80 to the transmit clock and control logic means 60. The feedback signal is used for synchronizing the clock with the data. Serial data to be transmitted on the loop is outputted from one of the registers in the bank of write register 40 on conductor 82 into the transmit logic function means 58.
The receive clock and control logic means 64 generates the clock used by the receive logic function means 57 to clock data bits into the receive latch (to be described later) and from there to the deserializer register (to be described later). This clock is generated from the base 14.7456 MHz oscillator and the received data via a phase locked loop. The phase locked loop ensures that the sample clock generated by the receive clock and control logic means will also be in the correct relationship with the incoming data stream so that the proper data is clocked into the deserializer register (to be described subsequently). The clock signal from the receive clock and control logic means 64 is fed over conductor 84 into the receive logic function means 57. Similarly, feedback error clock correction signal is fed over conductor 86 into the receive clock control logic means 64. Serial data is fed over conductor 88 into the read register 44. The receive logic function means 57 uses the clock generated by the receive clock and control logic means 64 to clock the receive data stream into the adapter. The data is then passed from an initial receive latch (to be described later) to the deserializer register. The data can then be read by the microprocessor.
The receive logic function means 57 also decodes three data bit patterns which have significance in the present loop communications system. The present loop communication system uses a loop communication protocol which is a subset of the well-known SDLC protocol. This protocol was invented by the assignee of the present invention. These patterns are given below in Table I with the least significant bit shown first.
TABLE 1______________________________________1. 0111 1111 = FE = the SDLC "EOP" character2. 0111 1110 = 7E = the SDLC flag character3. 0000 0000 = 00 = the SDLC shut-off character______________________________________
In the SDLC protocol these characters are not transmitted with the zero bit insertion. If any of these characters are received by the adapter, an interrupt will be generated to the microprocessor and the bits set in one of the registers (to be described subsequently). The receive logic function means will delete the zero bit that is received after the reception of the five consecutive one bits. This action removes the zero bit that was inserted by the original transmitting adapter The monitor circuit means 90 is connected over conductor 91 to TTL bipolar conversion means 78 and over conductor 93 to transmit logic function means 58. The monitor circuit means 90 allows the adapter to view the incoming data stream from the store loop without affecting the data thereon. When the circuit is activated by setting of bit 4 of the WRO register (to be described later), the receive data is brought into the adapter, passed through a combinatorial logic circuit (to be described subsequently) and placed back onto the store loop. This circuit allows the microprocessor program to ascertain if the clock that is being generated by the adapter can be locked into the data stream being produced by other terminals on the loop before the adapter's data retransmission circuitry is activated.
The bipolar to TTL conversion logic means 92 is coupled by conductor 94 to the receive logic means 57 and monitor circuit means 90, respectively. The function of the bipolar to TTL conversion logic means 92 is to receive bipolar signals from the loop converts the signal to a TTL logic level. The bipolar TTL signal is generated by an external analog circuit (to be described later).
FIGS. 3, 3A and 3B show a block diagram of the electrical circuitry used in the adapter. The circuitry includes a microprocessor interface means 35 which couples the adapter to the microprocessor. The microprocessor interface means 35 comprises of microprocessor interface decoding means 34 and bidirectional data bus 114, chip select (CS) line 104, read (RD) line 106, write (WR) line 108, register select (R/S) line 110, interrupt (INT) line 112 and oscillator (OSC) line 102. The functions performed by the control lines and the decoding means 34 have already been described and will not be repeated. Suffice it to say that decoding means 34 decodes the adapter register (to be described subsequently) that the microprocessor wishes to read or write during a microprocessor bus cycle. The chip select (CS) input line must be active for the adapter to perform any of the decodes.
The microprocessor interface decoding means 34 is coupled by internal data and control lines cabling system to the control registers. There are three write-only registers identified as WR0, WR1 and WR and four read-only registers identified as RD, RR0, RR1 and RR2. Each register is eight bits wide. The specific register that is being read or written to is defined by the read and write inputs, the register select input, data bit 0, and the state of bits 1 and 2 of WR1.
A simplex interrupt (INT) line 112 emerges from the microprocessor interface and a bidirectional data bus identified by numeral 114 forms external or microprocessor data bus into the chip. As described above, the adapter contains a plurality of control registers (to be described hereinafter) which perform command/status functions of the adapter. These registers are selected based on the status of the controlled lines and data bus at the microprocessor interface 34. By decoding the active lines the adapter interface is made to select the proper register which the microprocessor needs for reading or writing.
Referring to FIG. 6 for the moment, a chart showing how these registers are selected is given. The chart also contains information as to how the serializer 116 (FIG. 3) is selected to read out data for transmission onto the loop. The chart also shows how the deserializer 118 (FIG. 3) is selected to read data from the loop into read register 120. The first column of the chart identifies the registers, the second column represents the state of the register select input line 104, the third column represents the state of the read input line 106, the fourth column represents the state of the write input line 108, the fifth column represents the state of bit "0" of the data bus into the adapter, the sixth column represents the state of bit "1" of write register 1, and the seventh column represents the state of bit "2" of the write register 1. For example, in order to select write register 0 (WR0) the select input signal has to be in the "off" state (this assumes that a logical "0" represents an "off" condition and a logical "1" represents an on condition). The "read input" has to be "on." The "write input" has to be "off." The "DBO input" is "off," and bits 1 and 2 of write register 1 are in a don't care state. In a similar manner, the other registers, including the serializer and deserializer, can be selected by setting the appropriate lines and bit in accordance with the information shown in the chart.
Referring again to FIG. 3, read register (RD) 120 is connected over bus 124 to deserializer 118. The deserializer is connected over conductor 126 to receive control logic means 128. The function of deserializer 118 is to accept data from the loop, deserialize the data and store it into RD register 120. From the RD register the data is transmitted over the bus to the microprocessor.
The adapter is connected to the loop by loop interface means 140. The loop interface means comprises of relays (RLY) 130, 132, 134, 136 and 138.
As will be explained subsequently, depending on the setting of relay 130 and associated contact 132, 134, 136 and 138 data on the loop communications system can be diverted through analog circuit means 142 into receive latch 144 through receive control logic means 128 and into the deserializer which deserializes the data into a multiplex stream and stores it into read register 120. The receive counter 146 counts the data on a bit basis as it is fed into the deserializer. The data is then fed over the multiplexer bus 22 (FIG. 1) into the microprocessor. The status of the interface signals for selecting the deserializer is described above and shown in FIG. 6.
The data to be transmitted onto the communications system is written over the microprocessor bus into write register (WR) 122. The status of the interface control lines for selecting the serializer 116 is also shown in FIG. 6. The output from write register 122 is coupled over multiplexor bus 148 into the serializer 116. The function of the serializer 116 is to serialize the data which is delivered on the multiplexer bus into a bit stream and delivers the bit stream to transmit control logic 150. The output from transmit control logic 150 is fed into logical "and" circuit 152. The output from "AND" circuit 152 is fed into "OR" circuit block 154 and from the "OR" circuit into transmit (XMIT) latch 156. The signal is then transmitted into AND circuit 158 through OR circuit 160 from whence it is processed by analog circuit means 162 and then onto the communications system. As characters are fed from the serializer into transmit control logic 150 a transmit counter 164 keeps track of the bits. Also, control signals are fed into transmit control logic 150 from transmit clock logic control 165.
Still referring to FIG. 3, the control registers further include two write registers identified as write register (WR) 0, write register (WR) 1, and three read registers identified as read registers (RR) 0, read register (RR) 1 and read register (RR) 2.
The write registers can be written into by the control microprocessor over the data bus. Similarly, the read registers are written into by the adapter's hardware circuitry.
Referring to FIGS. 4-4d for the moment, a schematic representation of the registers and definitions for each bit are given. The bit definitions are also shown in abbreviated form in the registers of FIG. 3. The first column in each of these schematics represents the data bit (DB), the second and third columns give the state of the bit, for example, the bit could be in a logical "1"-state which is interpreted as being "on" or the bit may be in a logical "0" state which is interpreted in the present invention as being off. The fourth column gives the definition for the bit when that bit is set in a particular state. Abbreviations for the definitions are shown bracketed in the respective charts and non-bracketed in FIG. 3.
Write register 0 is used to control the various communication functions of the adapter. With respect to the graphical representation in FIG. 4c, the bit definition for write register 0 is as follows:
Bit 7 corresponds to the RS-232. signal "Data Terminal Ready". As stated before, RS-232 is a standard electrical and mechanical interface which is well known and defined by the EIA. When set active by the processor, the adapter will activate the relay and insert the terminal into the communications loop if bit 5 is not also set. It also allows the adapter to generate and transmit interrupt into the microprocessor.
Bit 6 corresponds to the RS-232 signal "Request to Send". When set active by the microprocessor, the bit activates the logic which will generate transmit interrupt into the microprocessor when the proper conditions are met.
Bit 5 corresponds to the RS-232 signal "Local Test". When set active by the processor, puts the adapter in a test mode of operation where the transmit data is wrapped to the receive data. The adapter is isolated from the loop when this bit is set;
Bit 4 When this bit is set. the adapter is placed in the "monitor mode" of operation. In this mode, the adapter does not reclock the store loop communications data as it passes through the adapter.
Bit 3 This bit enables/disables "bit insert," SDLC function which is necessary for the operation of the store loop communications network. As stated above, the insert feature is a special characteristic of SDLC protocol which requires that the data stream may not have more than five consecutive logical "1's". If five consecutive one bits are sent in the data stream to the adapter, the adapter will insert a zero bit. On receiving data from the loop, the adapter performs the same function. This function is known in SDLC as bit stuffing, and destuffing.
Bit 2 If set by the microprocessor, this bit will disable the adapter receive interrupts until the next flag character is recognized by the adapter.
Bit 1 This bit sets the adapter into the primary or secondary terminal mode of operation on the loop. As described above, the adapter is in a primary mode when the terminal which is attached to it is the controlling terminal that controls the entire loop. Among the control functions is the generation and transmittal of polls which gives each station the opportunity to place its data which is directed to the control station. Otherwise, all stations which are not running as a control station are running in the secondary mode.
Bit 0 This bit is part of the decode for WR 0. It must be set to a 0 when writing to WR 0.
When the adapter is running in the primary mode, a phase lock loop (PLL) is used to generate the clock that clocks in the receive data. The transmit data clock is generated from a count down of the input oscillator 102, FIG. 3. Likewise, if the adapter is running in the secondary mode, a PLL is used to generate the clocks for both the receive and transmit data.
With reference to FIG. 3, the bit definition for each of these functions in WR 0 is identified by the abbreviation in the respective bit position. To this end, in the bit 7 position (DTR) represents Data Terminal Ready. Similarly, RTS (in the sixth bit position) represents Request to Send, and so forth. The output from each of the bit positions of the WR 0 is transmitted over conductor 166 to general reset circuitry 168, CTS control logic 170, shut off (SO) latch 172, clock data latch 174, on line latch 176 and interrupt (IRPT) logic means 178.
It should be noted that except for bits RM and OL all the bits in read register (RR) 1 are similar to the bits in WR0 and are set simultaneously with the bits in WR 0. By setting bits in RR1 and WR 0 simultaneously, whenever the microprocessor is interrupted by the adapter hardware because of a set of conditions (to be described subsequently) the microprocessor can interrogate read register 1 to determine where to begin operating when the interrupt is serviced.
Still referring to FIGS. 3 and 4D, WR 1 is used to set the data rate at which the adapter is operating and to select the read register that will be read during the next microprocessor read operation to the adapter. The bit definition for the used bit in this register is given in FIG. 4D. It should be noted that the decode on bits 1 and 2 identified in FIG. 3 as pointers (PTR) are used to select one of the read registers. To convey this selection function, these bits are bracketed with a line exiting from and pointing to RR1, RR0, RR2.
Still referring to FIG. 3, in addition to the deserializer and read register 120 the microprocessor may read read register 1, read register 0 and read register 2. Read Register 0 (RR 0) is the interrupt register. It is used to indicate to the microprocessor the source of an interrupt generated by the adapter's hardware. Each bit definition is given in FIGS. 3 and 4. Bits 7 and 6--These bits are encoded by the adapter to indicate to the microprocessor that one of three types of characters have been received by the adapter. The following is the information that these two bits give the microprocessor for each of the four possible bit combinations.
1. Bit 7=0, Bit 6=0: The interrupt was not a receive interrupt.
2. Bit 7=0, Bit 6=1: The adapter has recived a data byte.
3. Bit 7=1, Bit 6=0: The adapter has received an EOP character.
4. Bit 7=1, Bit 6=1: The adapter has received a flag character.
Bit 5 This bit indicates that the source of the interrupt is that the transmit serializer is empty and the microprocessor may write the next transmit data byte to the serializer register.
Bit 4 This bit indicates that the source of the interrupt is that an overrun condition on the deserializer or an underrun condition on the serializer has occurred.
Bit 3 This bit indicates that the source of the interrupt is that a loss of carrier on the store loop has been detected by the adapter.
Bit 2 This bit is the status of the input to the adapter which indicates the condition of a carrier on the store loop. This bit is not an interrupt source.
Bit 1 This bit indicates that the source of the interrupt is that a transmit shut-off character has been received by the adapter.
Bit 0 This bit is the status of the internally generated adapter signal which corresponds to the RS-232 signal "Clear to Send." This bit is not an interrupt source.
Except for Bits 0 and 3, the bits in RR1 correspond directly and indicate the state of the bits defined in WR0.
The two most significant bits in RR2 correspond directly and indicate the state of the two most significant bits 7 and 6 in WR 1 which are set to select the adapter data rate. Bits 1 and 0 are the only other bits used in RR2. The definition of the function of these bits are as follows:
Bit 1--If this bit is a 1, it indicates that the transmitted data from the adapter is being converted from a single TTL signal to a bipolar TTL signal correctly.
Bit 0--This bit indicates the status of the received data reclock function. If the adapter is reclocking the received data before transmitting it onto the store loop, this bit will be a 1. Also, bit 1 known as the loop driver (LD) bit is set from loop driver means 184. The function of the loop driver is to monitor the analog circuit means 162 and to set the latch when the circuit is operating in a satisfactory condition. Likewise, bit 0 (RR2) is set from the clock data latch 174. It should be noted that the appropriate signals which are used to provide the function emanating from each block are labeled on lines going into the blocks.
Still referring to FIG. 3, the interrupt line 112 emanating from the adapter is brought active for any of the following reasons:
1. An SDLC flag character (hexadecimal 7E) was received.
2. An SDLC EOP or "go ahead" (hexadecimal FE) was received.
3. A data byte has been received.
4. The transmit data serializes empty.
5. There has been either a serializer or deserializer overrun.
6. The adapter detects the absence of any data on the loop. (If no message is being transmitted, the primary station should be idling the loop by transmitting flag characters.) The absence of data will cause an RLSD interrupt.
7. An interrupt will be generated if the adapter is in secondary mode, transmitting and receiving a "Shut-Off" command. As stated before, the causes of the generated interrupt are found by reading register RR0.
FIG. 5 shows a block diagram of a circuitry which enables the adapter of the present invention to either monitor the loop data stream or bring the data into the receive circuitry and reclock out of the adapter through the transmit circuitry. To implement this function, the adapter has to be placed in the monitor mode by setting bit 4 in Write Register (WR)0. In monitor mode the received data stream is passed through combinatorial logic, by passing the transmit circuit, and passed out of the adapter. The feature allows the control microprocessor to receive data from the loop without altering it.
Still referring to FIG. 5, the facility for performing the monitor function includes a receive data clocking means 186. The receive data clocking means receives a stream of incoming data from the loop on conductor 192. The data on conductor 192 is clocked into receive data clocking means 186 by the receive data clock. The output from the RX data clock means 186 is fed over conductor 194 to the deserializer 118, FIG. 3. The data can then be shipped up from the deserializer into the microprocessor where the microprocessor can make sure that the adapter's clocking facility is working satisfactorily before data is disrupted on the loop.
Still referring to FIG. 5, the output signal from the received clocking means 186 is fed into combinatorial logic means 188. Transmitted data from the adapter's serializer is fed over conductor 196 into the combinatorial logic means 188. Also, control signals are supplied on conductor 198 into the combinatorial logic means 188. As will be explained subsequently, the function of the control signals on conductor 198 is to select one of the data streams on conductor 196 or 200 for transmission into transmit data clocking means 190. Transmit data clock 202 clocks the data out of the transmit clocking means 190. The output from transmit data clocking means 190 is fed over conductor 204 into combinatorial logic means 192. Another source of data into combinatorial logic means 192 is the loop data which is supplied on conductor 206. The control signals on conductor 208 select which one of the data sources should be transmitted to the combinatorial logic means 192 onto the loop.
As stated previously, this circuit allows the adapter to monitor the data on the loop, reclock the data on the loop through the adapter circuits or transmit data originating at the terminal which the adapter couples to the loop. When the appropriate bit is set in WR0, the received data stream is supplied on conductor 206 into the combinatorial logic means 192 from whence it is retransmitted back on the loop without being disturbed by the adapter.
FIG. 7 shows the interface that couples the adapter to the serial loop communications system. The figure also shows the details of the logic and combinatorial circuitry which performs the monitor mode function shown as block diagram in FIG. 5. In order to simplify the description common numerals are used to identify the combinatorial logic circuits which are shown in block diagram form in FIG. 5. To this end, the receive data clocking means 186 (FIG. 5) is represented by "D" Latch 186 in FIG. 7. Similarly, the combinatorial logic means 188 (FIG. 5) is represented in FIG. 7 by AND circuits 206, 209, 210 and OR circuit 212. The other combinatorial logic in this figure is self-explanatory and a detailed description will not be given. It should be noted that the control signal on conductor 208, FIG. 5, is supplied by the signals Clock Data and Clock Data (FIG. 7). Also, the control signal which is supplied on conductor 198, FIG. 5, is represented in FIG. 7 by control signal CTS, PRI, CTS, TX data etc. The definition and function for each of these signals have already been given above and will not be repeated here.
Referring to FIGS. 8 and 8a for the moment, the combinatorial logic circuit which is used to generate the Clock Data, Clock Data are shown in FIG. 8 while the combinatorial logic circuit which generates a pick Relay Signal is shown in FIG. 8a. The Clock Data and Clock Data are generated from set/reset latch 214. The output from a four-way AND circuit 216 is coupled to the set terminal of the latch. Also, the output from a three-way AND circuit 218 is connected to the reset terminal of the latch. Likewise, the relay signal is generated from the output of the D latch 220. The input of the latch is supplied from two two-way AND circuits identified by numerals 222 and 224, respectively.
Referring again to FIG. 7, the flow of data through loop relay input into the adapter logic and back out again is shown. The relay in FIG. 7 has its contact in the "unpicked" condition. In the "unpicked" condition, data flows directly through the relay and does not enter the analog logic. In the "picked" condition data flows into analog circuitry (not shown in FIG. 7 but shown in FIG. 3) which converts the bipolar signal to a logical level. This logical level signal is processed by the hardware adapter. FIGS. 8 and 8A show the circuits that generate the control signals "pick relay" and "Clock Data" in FIG. 7. Following is a list of signals used in the circuits and the definitions for the signals.
RX Clock This clock is synchronized to the receive data stream and used as the sample clock for received data. It is derived from the Sys Clock adapter input.
TX Clock This clock is used to place transmit data values onto the loop. It is derived from the Sys Clock adapter input.
CTS "Clear to Send" becomes active under two conditions. (1) If the terminal is a primary or controlling terminal on the loop, CTS will become active whenever the software activates the "Request to Send" (RTS) signal. (2) If the terminal is a secondary or "slave" terminal on the loop, CTS will become active whenever RTS has been activated and the last byte in the data stream, an EOP (End of Poll), has been recognized by the adapter hardware.
PRI "Primary" is set by the software controlling the adapter to indicate whether the adapter is the primary (the signal would be active) terminal on the loop, or if the terminal is a secondary terminal (the signal would be inactive).
TX Data This is the bit data stream that is to be placed on the loop by the adapter.
DTR "Data Terminal Ready" is a signal set by software indicating that the terminal should be placed into the loop by picking the relay. It is used in conjunction with LTST.
LTST "Local Test" is a software activated signal which indicates that the terminal is in self-test mode and should not be placed on the loop. When this signal is active, the adapter will transmit a data stream through the "unpicked" relay contacts and receive the data exactly as if the data was from an upstream terminal. All other control signals would be set during this wrap test as if the terminal was operating on the loop.
MMS "Monitor Mode Select" is set by software whenever the software wishes to monitor the loop data stream but not possibly disrupt it by reclocking through the TX data latch.
EOP "End of Poll" is a hardware activated signal which is set whenever the last character in a data stream is detected. This character is an EOP character.
RLSD "Received Line Signal Detect" is a hardware activated signal which indicates that the RX Clock has been synchronized to the RX data stream and that a valid data stream has been recognized by the hardware.
SYS Clock "System Clock" is the oscillator input to the adapter.
This completes the description of the adapter.
The above-described multi-function integrated circuit adapter may be used for attaching any data processing terminal to a loop communication system. In one application the present adapter is used to interface microprocessors in a point of sale terminal to a store communication loop. Preferably, the store loop architecture is a derivative of the IBM Synchronous Data Link Control (SDLC) communication architecture. This is a well-known architecture and details will not be given here. Suffice it to say that the architecture is very efficient in enabling machines to communicate with one another. The above-described single chip adapter contains the following logical functions:
1. An 8-bit parallel data bus processor interface which uses four control lines to read and write data and command/status to the adapter. All input and output signal levels are TTL compatible.
2. A modified RS-232 command/status interface to the microprocessor.
3. Serialization of transmitted and deserialization of received adapter data.
4. Two separate integrated digital phase locked loops used for transmit and receive clock.
5. Given a single input oscillator, one of four different data rates can be selected.
6. Transmit and receive data may be wrapped internally to the chip for diagnostic purposes.
7. The "0" bit insertion and deletion necessary for SDLC transmission reception is done by the adapter.
8. Facilities for generating an interrupt to the microprocessor are provided.
9. Recognition of SDLC "EOP" or "Go Ahead" flag and Shut-Off characters.
10. The adapter can be configured for either primary or secondary terminal operation.
11. The adapter controls the relay that connects the terminal to the store loop and as a result is transparent to the microprocessor.
12. The adapter provides facilities for allowing the terminal to monitor the loop data flow without reclocking the data as it goes in and out of the adapter.
13. The adapter provides facilities for the secondary terminal to remove itself from the loop without disrupting any data flow that may be on the loop when the command to disconnect is given.
Claims (20)
Priority Applications (2)
|Application Number
|Priority Date
|Filing Date
|US66915784 true
|US07014176 US4937567A (en)
|Communication adapter for store loop communication system
Applications Claiming Priority (1)
|Application Number
|Priority Date
|Filing Date
|US07014176 US4937567A (en)
|Communication adapter for store loop communication system
Related Parent Applications (1)
|Application Number
|Priority Date
|Filing Date
|US66915784 Continuation
Publications (1)
|Publication Number
|Publication Date
|US4937567A true US4937567A (en)
Family Applications (1)
|Application Number
|Priority Date
|Filing Date
|US07014176 Expired - Fee Related US4937567A (en)
|Communication adapter for store loop communication system
Country Status (4)
|US4937567A (en)
|EP0180822B1 (en)
|JPS61114631A (en)
|DE3586617D1 (en)
Cited By (6)
|Publication number
|Priority date
|Publication date
|US5256863A (en) *
|Comark Technologies, Inc.
|In-store universal control system
|WO1997032287A2 (en) *
|Dcns, Inc.
|Point of sale printer and interface
|US6006147A (en) *
|Chrysler Corporation
|Translator and voltage check module for hand-held vehicle tester
|US20070147115A1 (en) *
|Fong-Long Lin
|Unified memory and controller
|US20070233933A1 (en) *
|Jeremy Wang
|Hard disk drive cache memory and playback device
|US20150279544A1 (en) *
|Abb Technology Ag
|Transformer Having An Interlocking Core Frame
Citations (7)
|Publication number
|Priority date
|Publication date
|US31852A (en) *
|S J Olmsted
|US3764977A (en) *
|Honeywell Inf Systems
|Solid-state modem control
|US3937882A (en) *
|Vadic Corporation
|Full-duplex communication system on a two wire line
|US4007449A (en) *
|Honeywell Information Systems Italia
|Control device for local connection of a peripheral unit through a modem interface for remote connection
|US4332029A (en) *
|Harris Corporation
|Automatic alignment system for a digital modem
|US4425664A (en) *
|Bell Telephone Laboratories, Incorporated
|Multiport programmable digital data set
|US4529979A (en) *
|Hitachi, Ltd.
|Remote return loop control in a data transmission system
Family Cites Families (2)
|Publication number
|Priority date
|Publication date
|JPS6022540B2 (en) *
|Hitachi Ltd
|JPS6354265B2 (en) *
|Tokyo Shibaura Electric Co
Patent Citations (7)
|Publication number
|Priority date
|Publication date
|US31852A (en) *
|S J Olmsted
|US3764977A (en) *
|Honeywell Inf Systems
|Solid-state modem control
|US4007449A (en) *
|Honeywell Information Systems Italia
|Control device for local connection of a peripheral unit through a modem interface for remote connection
|US3937882A (en) *
|Vadic Corporation
|Full-duplex communication system on a two wire line
|US4425664A (en) *
|Bell Telephone Laboratories, Incorporated
|Multiport programmable digital data set
|US4332029A (en) *
|Harris Corporation
|Automatic alignment system for a digital modem
|US4529979A (en) *
|Hitachi, Ltd.
|Remote return loop control in a data transmission system
Cited By (9)
|Publication number
|Priority date
|Publication date
|US5256863A (en) *
|Comark Technologies, Inc.
|In-store universal control system
|WO1997032287A2 (en) *
|Dcns, Inc.
|Point of sale printer and interface
|WO1997032287A3 (en) *
|Dcns Inc
|Point of sale printer and interface
|US6006147A (en) *
|Chrysler Corporation
|Translator and voltage check module for hand-held vehicle tester
|US20070147115A1 (en) *
|Fong-Long Lin
|Unified memory and controller
|US20070233933A1 (en) *
|Jeremy Wang
|Hard disk drive cache memory and playback device
|US7519754B2 (en) *
|Silicon Storage Technology, Inc.
|Hard disk drive cache memory and playback device
|US20090150588A1 (en) *
|Silicon Storage Technology, Inc.
|Hard Disk Drive Cache Memory and Playback Device
|US20150279544A1 (en) *
|Abb Technology Ag
|Transformer Having An Interlocking Core Frame
Also Published As
|Publication number
|Publication date
|EP0180822A2 (en)
|EP0180822B1 (en)
|JPS61114631A (en)
|DE3586617T2 (en)
|DE3586617D1 (en)
|EP0180822A3 (en)
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text:
Archived posting to the Leica Users Group, 2004/05/19[Author Prev] [Author Next] [Thread Prev] [Thread Next] [Author Index] [Topic Index] [Home] [Search]
It'll come unstuck......;-) (seriously though, you're absolutely....) -----Original Message----- From: email@example.com [mailto:email@example.com] On Behalf Of Douglas Herr Sent: Wednesday, May 19, 2004 11:54 AM To: Leica Users Group Subject: RE: [Leica] The "discipline" of using only one lens "B. D. Colen" <email@example.com> wrote: > Odd, but when I'm working, I DO try to make every shot count - whether > it's on a roll or 36, or a 1 gig card of apx 256 shots...They don't > all work, but I do try... ;-) Agreed, otherwise why push the button? Doug Herr Birdman of Sacramento http://www.wildlightphoto.com _______________________________________________ Leica Users Group. See http://leica-users.org/mailman/listinfo/lug for more information

subset: commoncrawl


text:
Back to School is a full featured Left 4 Dead and Left 4 Dead 2 campaign. The storyline is not interfere with none of this games and offer completly new setting of Borden city, struggling to survive in an epidemic apocalypse alongside with original 4 heroes. They are getting a chance to save themselves, since USA marines are coming in town and not falling back this time. But during the battle apogee something goes terribly wrong and local school - the most safe place in city - turns out to be a death trap.
Only registered members can share their thoughts. So come on! Join the community today (totally free - or sign in with your social account on the right) and join in the conversation.
Another six screenshots. Several previously unseen locations of the fifth chapter, along with church location, which is familiar to some of you.


text:
This article comes to us courtesy of SF Weekly's The Snitch.
Healthy San Francisco, the city's attempt at universal healthcare, has helped many local residents who don't have health insurance receive affordable medical treatment. But who is hasn't helped entirely are San Francisco's transgender residents seeking certain medical procedures, such as gender reassignment surgery.
But as Justice John Roberts proved last month -- times are a changin'.
Supervisor Scott Wiener is hoping his colleagues today will continue that change and support his resolution urging the Department of Public Health to withdraw exclusions in the healthcare system and allow members of the transgender community receive procedures that currently are only allocated for non-transgender people.
"This is a glaring inequity in the system," Wiener told SF Weekly. "In San Francisco, we value healthcare, but we also value treating people equally ... this is a way to do just that."
What exactly does this mean for the transgender community? Wiener explained that currently, a non-transgender female patient who needs a hysterectomy would be covered under Healthy SF, but a transgender female-to-male patient would not be -- and isn't that discrimination?
Currently, gender reassignment surgery is considered elective, however, as Wiener notes in his resolution, plenty of "studies have concluded that receiving medically necessary transition related treatment results in a dramatic drop in suicidality, an overall improvement in mental health, a reduction in HIV infection, a decline in substance abuse rates, and an increase in socioeconomic status for transgender people."
Wiener says that he worked with the DPH every step of the way in drafting the resolution and that the department is on board with his plan. It has received widespread support thus far so Wiener expects it will pass at the Bord of Supervisors meeting today with little debate.
And although a resolution won't make any changes to the law, it's definitely a good start for San Francisco.
For more San Francisco politics and beyond, follow The Snitch on Twitter.


text:
Xcllusive Business Sales
Phone: 02 9817 3331
Xcllusive Business Brokers
202/230 Victoria Rd,
Gladesville, NSW 2111
Phone: 02 9817 3331
Fax: 02 8212 5899
Food/Hospitality for sale
Business Details
Great Bakery with a strong potential - Wholesale and Retail - TUMBARAMBA
Over $1M in sales and profits of $262,000. Sale price is $450,000 + Stock.
Here is a rare opportunity to buy a well established Bakery that dominates the area. The Bakery caters to the wholesale market as well as to the general public in the wider area. With a shop at the center of town, it has a strong presence and recognition. This sale presents an opportunity to the potential purchaser to capitalise on a well-established and growing business whose reputation has seen them establish a loyal client base.
Business Highlights
Only bakery in the area
Strong and constant sales
Strong recognition of brand
Long term lease
Partially refurbished facilities
Annualised Turnover of $1M approximately
Potential to build on existing client base and grow the business
Owner is prepared to provide training/support as well as one of the owners is willing to stay as employee. Sale price includes all bakery equipment
To find out more about this impressive business inquire today.
Asking Price $450,000 + SAV
Summary »
- Business Category: Food/Hospitality
- Business Sub Category: Bakery


text: > > > I apologize advance for my extreme lack of knowledge in linux development> > of any kind. I am only presuming to post to this list under the advice of> > a friend.> > > > I want to make it impossible for daemons to be started under any UID> > that is greater than 100, except for UID 65534.> > > > Some suggested that I make a patch for my kernel that would do something> > such as:> > > > if UID > 100 and UID != 65534> > then "do not open socket"> > ... which means that your lusers will be unable to use email, news, FTP> *and* HTTP (i.e. no web for them). Is that *really* the thing you want?> no..her problem is she wants to stop users >100 && !=65534 from BINDING to ports, not connecting to them.-Tony.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-.Anthony J. Biacco Network firstname.lastname@example.com Intergrafix Internet Services "The best way to predict the future, is to invent it."http://cygnus.ncohafmuta.com http://www.intergrafix.net.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-._.-.-To unsubscribe from this list: send the line "unsubscribe linux-kernel" inthe body of a message to email@example.com read the FAQ at http://www.tux.org/lkml/


text:
I can get through with the ablution
Le 8 juillet 2016, 04:20 dans Humeurs • 0
For instance, I could acquire bogus ceremony girl's accouterment a acclimatized CS:GO Skins, Nevertheless, I anxiously broke and bogus a absent accretion for ceremony one of my daughters.Then, it was their job to accumulated their accretion and put the clothes in their drawer.I apprehension to myself how able this plan is.
At least, I can get through with the ablution and dry diplomacy a little quicker by teaching the girls to put their own clothes in their drawer.As a bulk of fact, I acquainted ambrosial conceited about it.After all, they were accepting old abounding to help.Julie was 12, Cherise 10, Jamie 8 and Anissa 6.Yes, I was ambrosial beholden of my annual about the girls helping, although I did usually acquire to ask them added than already to put their clothes in their chest of drawers.
Almost every day is laundry day with four accouchement unless you are alarming ill or acquire a bogie god mother.The bedding were usually afflicted and apple-pie on Saturday and the abject of the clothes, just about every day.This authentic morning was like all the Cheap CSGO Skins For Sale.


text:
Security at Wisbech's Horsefair Shopping Centre has been recognised as the best in the country.
Roger Vanhinsbergh, the centre's security officer, has won a national award from the British Security Industry Association (BSIA).
In March, Roger won BSIA's Regional Security Personnel Award for Service to the Customer in the Midlands and subsequently progressed to the national awards held in London.
Roger was presented with the national award for Service to the Customer, from Baroness Smith, Labour's Shadow Home Affairs Minister for private security.
He said: "Getting nominated for the regional award was such an achievement so winning this is pretty unbelievable. I love working at the Horsefair and helping out the local community, so it's great to have my work recognised at this level."
Roger, who has worked at the Horsefair for over seven years, was nominated for the award by his managers for consistently exceeding the high standards required of him and always going "the extra mile" to help others.
Kevin Smith, manager of the Horsefair Shopping Centre, said: "These were awards for security personnel from all industries, not just for shopping centres, so it's great to see Roger and the Horsefair leading the way.
"Roger has made a significant contribution to making Wisbech town centre a much safer place."
Gary Clarke, managing director of City Security, who employ Roger, said: "The difference he has made to the local community is something special. It is no exaggeration to say that he has singlehandedly reduced the local area's crime rate."


text:
The Rockstar Games label was founded in 1998 to create the most innovative and progressive interactive entertainment. It is a wholly owned subsidiary of Take-Two Interactive Software, Inc.
No mods were found matching the criteria specified. We suggest you try the mod list with no filter applied, to browse all available. Add mod and help us achieve our mission of showcasing the best content from all developers. Join now to share your own content, we welcome creators and consumers alike and look forward to your comments.


text:
Although First Presbyterian Christian Academy is not the victor in Under Armour's Finding Undeniable challenge, school representatives still consider the experience a win.
The Liberty County Board of Commissioners took little action during their Tuesday meeting, but they heard a host of updates on capital projects and discussed taking on a local contractor preference policy.
A local civic organization has completed about 10 percent of a daunting mission: turning shoes into water.
Now that you're likely putting your stockings away and the new year is here, it's time to shift gears and think about how best to part ways with your Fraser fir.
Though their football team is not yet established, more than 120 supporters of First Presbyterian Christian Academy will travel to St. Petersburg, Fla., on Thursday for the Under Armour All-America High School Football Game.
A Liberty County student who allegedly received hand-written notes containing sexual content from a middle-school teacher last year has filed suit against the Liberty County School System seeking more than $15,000 in damages.
If your New Year's resolution is to rediscover the finer things in life, the Hinesville Area Arts Council has upcoming events aimed to help you succeed.
As the days on my 2011 calendar have flown away, I've started wondering why we make such a big deal about the New Year.
While many will toast the New Year this weekend with a fizzy libation in hand, Liberty County law enforcement officers will dedicate their weekend to ensuring area residents safely enjoy their bowl games and black-eyed peas.
In the final of our four-part retrospective, the Courier recalls the top headlines from October through the end of 2011.
Though 2011 Liberty County property tax bills are just now hitting mailboxes, Tax Commissioner Virgil Jones is spreading the message that property owners don't have to wait for their invoices to make payments.
In the third of a four-part retrospective, the Courier recalls the top headlines from July through September of 2011.
During the Thursday meeting, the Ludowici City Council also heard updates from auditor Christopher Lightle, who was brought on after city clerk Tara Manning was suspended earlier this month. At the Dec. 13 meeting, Lightle, an accountant with Karp, Ronning and Tindal Certified Public Accounting, presented a preliminary report that noted concerns about lack of budgetary controls, adopted financial controls not being enforced, duplicate payments for some services, cash accounts not being recorded accurately and financial statements not being reported monthly.
The Ludowici City Council suspended Police Chief Richard Robertson with a 2-1 vote during Thursday's called meeting.
In the second of a four-part retrospective, the Courier recalls the top headlines from April through June of 2011.
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text:
United States, Appellee
Kevin P. RUSSELL, Technical Sergeant
U. S. Air Force, Appellant
No. 96-1399
Crim. App. No. 31730
United States Court of Appeals for the Armed Forces
Argued January 15, 1998
Decided June 12, 1998
For Appellant: Captain Tishlyn Taylor (argued); Colonel Douglas H. Kohrt (on brief); Colonel David W. Madsen and Major Ormond R. Fodrea.
For Appellee: Lieutenant Colonel Michael J. Breslin (argued); Colonel Brenda J. Hollis (on brief); Captain Libby A. Brown.
Military Judge: J. Jeremiah Mahoney
Opinion of the Court
CRAWFORD, Judge:
Contrary to his pleas, appellant was convicted by officer members of wrongfully using marijuana in violation of Article 112a, Uniform Code of Military Justice, 10 USC § 912a. The convening authority approved the sentence of a bad-conduct discharge, 3 months' confinement, and reduction to the lowest enlisted grade. The Court of Criminal Appeals affirmed the findings and sentence following our remand. 46 MJ 413 (1997).
We specified the following issue for review:
We hold that appellant failed to present sufficient facts to prevail on the ultimate issue.
Appellant tested positive for marijuana on three different occasions--September 14 and October 4 and 5 of 1994. At trial, appellant denied using marijuana and presented a good-character defense. Appellant testified that his brother was visiting him during the times he tested positive and speculated that his brother had spiked his meals.
Appellant's brother did not testify at appellant's court-martial. Appellant testified that he tried to contact his brother through their family, but his brother did not have a permanent address. Appellant also testified that his brother had been arrested twice for possessing 14 pounds of marijuana. Appellant stated that his brother cooked and made tea for him during the brother's visit.
Appellant's defense counsel did not request a subpoena or ask for any assistance in trying to locate appellant's brother.
As part of his clemency package, appellant submitted a letter from his brother to the convening authority. The letter informed the convening authority that the brother had added marijuana to appellant's spaghetti sauce without appellant's knowledge or consent.
The Sixth Amendment guarantees a criminal defendant "Assistance of Counsel for his defence." We have stated: "Under both the Sixth Amendment to the Constitution and Article 27, UCMJ, 10 USC § 827, a military accused is guaranteed the effective assistance of counsel at the pretrial stage.... A military accused is also guaranteed the effective assistance of counsel at trial and post trial." United States v. Fluellen, 40 MJ 96, 98 (1994) (citations and footnote omitted); see also United States v. Carter, 40 MJ 102, 105 (1994).
This Court has unanimously adopted the test for ineffective assistance of counsel established in Strickland v. Washington, 466 U.S. 668, 687 (1984). United States v. Scott, 24 MJ 186 (1987). The Strickland test uses a two-pronged inquiry to determine whether an appellant had ineffective assistance of counsel. The first prong is whether counsel's conduct was "below an objective standard of reasonableness." Strickland, 466 U.S. at 688. Courts strongly presume that counsel has provided "adequate assistance." Id. at 690. The second prong is whether there was prejudice. Id. at 692.
As we stated in Fluellen, 40 MJ at 98, "It is important for counsel to evaluate all of the evidence and determine the strategy that is most likely to be successful." Prior to trial, counsel should decide, as a tactical matter, whether to call witnesses "because of their potential for impeachment and corroboration of the prosecution's case." Id. The accessibility of a witness is one of the criteria "that may affect what a reasonably competent attorney could be expected to have done under the circumstances...." United States v. Cronic, 466 U.S. 648, 666 (1984).
To establish that trial defense counsel's conduct was below an objective standard of reasonableness, an appellant has the responsibility to bring to an appellate court's attention facts rather than mere speculation. The Missouri Court of Appeals has stated that, to raise ineffectiveness of counsel for failure to investigate a witness, "a movant must allege the specific information that counsel failed to discover, that a reasonable investigation would have disclosed the information, and that the information would have aided the movant's defense." McLaurin v. State, 755 S.W.2d 341, 342 (1988). Similarly, we hold that, to raise ineffectivess of counsel for failure to locate a witness, an appellant must allege specific information that counsel could have located the witness after a reasonable investigation, that the witness would have been available to testify, and that the substance of the witness's testimony would have assisted the appellant's defense. See Doucette v. State, 463 A.2d 741, 745-46 (Me. 1983).
On remand of this case to the lower court, appellant did nothing to advance either the deficiency prong or the prejudice prong of Strickland from a speculative matter to a factual one. Appellant should have explained why trial defense counsel could have found his brother with reasonable diligence. He could have shown that trial defense counsel would have been able to locate the witness from information provided by appellant, his family and friends, or through official records such as a driver's license, insurance, or social security number. Additionally, appellant could have obtained an affidavit from his brother indicating that the brother would testify that he had put marijuana in appellant's food.
Appellant did not do any of these things. He has not put forward enough facts for this Court to hold that his trial defense counsel was ineffective. Appellant's conclusory allegations of ineffective assistance of counsel are not sufficient to overcome the presumption of competence afforded to counsel. See State v. McLain, 403 N.W.2d 16, 19 (N.D. 1987).
The decision of the United States Air Force Court of Criminal Appeals upon further review is affirmed.
Chief Judge COX and Judges GIERKE and EFFRON concur.
SULLIVAN, Judge (dissenting):
The majority opinion rebukes appellate defense counsel for dropping the ball when this case was remanded to the Court of Criminal Appeals. The majority states:
On remand of this case to the lower court, appellant did nothing to advance either the deficiency prong or the prejudice prong of Strickland from a speculative matter to a factual one. Appellant should have explained why trial defense counsel could have found his brother with reasonable diligence. He could have shown that trial defense counsel would have been able to locate the witness from information provided by appellant, his family and friends, or through official records such as a driver's license, insurance, or social security number. Additionally, appellant could have obtained an affidavit from his brother indicating that the brother would testify that he had put marijuana in appellant's food.
Appellant did not do any of these things. He has not put forward enough facts for this Court to hold that his trial defense counsel was ineffective.
The record before me shows a different picture. This Court remanded to the appellate court below on April 9, 1997, for that court to examine the issue of ineffective assistance of counsel with regard to the failure of defense counsel "to locate appellant's brother, a critical witness to the defense of innocent ingestion." Appellate government and defense were notified by the Judge Advocate General of this action on or about April 11, 1997. Nevertheless, the lower appellate court issued its second opinion on May 21, 1997, without soliciting any pleadings or any other information from the parties.
I would remand this case again to provide the parties a full and fair opportunity to contribute to the just resolution of this case and to provide this Court a complete record upon which we can decide the issue of effective assistance of counsel. In my view, either the decision of the court below was premature or appellate counsel did not effectively represent his client. Our Court remanded this case to the court below to consider whether there was ineffective assistance of counsel with regard to appellant's brother, a critical witness. We did this because we found the record too incomplete for us to make the legal determination of ineffective assistance of counsel. If we had had a complete record, we could have answered this question ourselves without the prior remand.
Once the case got to the court below, there was no additional factfinding done or any effort to complete this record. Perhaps in the future we should be more clear in our directions of how to gain more facts to complete a record when we remand. I hope in the future this is not necessary. General Patton often said, "Leadership consists of telling soldiers what you want done, not how to do it."
In this case, a fair appeal cannot take place unless the record is complete. I would remand and clear up the factual record by affidavit or otherwise before making the legal determination of effectiveness of counsel.


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With Gold Reaching an 'All-Time' Record High of $1,350 per oz., When Is the Right Time to Sell My Unwanted Gold Jewelry?
Oct 13, 2010, 09:00 ET from USGoldBuyers.com
NEW YORK, Oct. 13 /PRNewswire/ --This is a relevant question that many people ask themselves before deciding to part ways with their unwanted gold jewelry. Many have accumulated jewelry from a divorce or past relationship while others pass these precious metals down as estate pieces. Consumers may feel guilty selling jewelry that has sentimental value and are therefore difficult to let go. Subconsciously, keeping these unwanted items can be painful; having a ceaseless reminder of the individual who broke your heart or passed away. Should you sell estate jewelry or a coin collection that you've inherited? Some may cherish certain items and have them passed down from generation to generation but the rest may be sold and the cash can be converted to something useful. "With gold prices breaking 'all-time' record highs, 31 grams of 14 KT gold at around the $1,350 mark fetches you approximately $710 per oz. It is a great way to pay your bills, take a much needed vacation, or generate some extra income," states Jose Caba, Account Representative from www.USGoldBuyers.com.
Other consumers have discovered old, unwanted or broken jewelry collecting dust in dresser drawers. Wedding rings, earrings, necklaces, bracelets, and even gemstones that have been broken for years may be too high-priced to repair but too valuable to throw away. "Many of our clients have a hard time giving up old jewelry, especially if it has sentimental value, but here at www.USGoldBuyers.com we offer the highest prices for your gold which makes it a little easier to part ways." - Kevin Morris, Public Relations Director.
Sometimes a piece of jewelry is out-dated or out-of-style. Whether or not you no longer like yellow gold and prefer white gold, silver, or platinum, you may recycle your unwanted jewelry by selling to a reputable buyer and upgrade to more stylish treasures. "Not only are consumers selling their unwanted jewelry at a record pace, the economic recession has pushed many to seek new opportunities by learning to buy & sell gold and other precious metals from our sister company called www.USGoldBuyersAcademy.com." – Alan Silverman, Project Manager.
Although critics and investors warn gold is the latest frenzy and its bubble will eventually burst, the average consumer is taking advantage of record breaking prices and cashing in on the highest payouts in years. Before deciding to sell gold, it is in the consumer's best interest to research a company before conducting business with them. Reading testimonials and confirming they are accredited by the Better Business Bureau and licensed by the Dept. of Consumer Affairs are great ways in determining the credibility and reputation of a precious metals company. Rather than finding the right time to sell, the real key to getting the most out of your unwanted jewelry is finding the right buyer.
CONTACT: Kevin Morris, +1-212-764-7586, email@example.com
SOURCE USGoldBuyers.com


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A statistical model of the network of connections between brain regions
April 19, 2012
Researchers at the University of Cambridge have developed a simple mathematical model of the brain which provides a remarkably complete statistical account of the complex web of connections between various brain regions.
The brain shares a pattern of connections that is similar to other complex networks such as social networks and the Web. However, until now, it was not known what rules were involved in the formation of the human brain network.
The scientists, from the Behavioral and Clinical Neuroscience Institute in the University of Cambridge Department of Psychiatry, and the National Institute of Mental Health in the U.S., discovered that the network can be modeled as a result of just two different competing factors: a distance penalty based on the cost of maintaining long-range connections between various brain regions, and a second term modeling the preference for links between regions sharing similar input.
Professor Ed Bullmore, lead author on the paper, explains the dynamic between the parameters they identified: "There is a huge amount of evidence that the wiring of brain networks tends to minimize connection costs. Less costly, short-distance connections are much more numerous than more costly, long-distance connections. So our model realistically includes a distance penalty on long-distance connections, which will tend to keep connection costs low.
"However, we found that cost control alone was not enough to reproduce a wide range of network properties. To do that, we had to model an economical trade-off between cost control and another term which favoured new, direct connections between regions that shared similar input or were otherwise already indirectly linked."
The model not only increases our understanding of healthy brains, but the researchers believe it could also provide unique insight into disorders such as schizophrenia.
Dr Petra Vertes, one of the authors of the paper, said: "Our model hints at possible mechanisms behind schizophrenia, which will be interesting to investigate further. We have been able to model the disease by tuning the parameters to allow a greater probability of connection between distant brain regions. This result echoes some prior neuroimaging results which suggest that brain networks in schizophrenia may be associated with an abnormal trade-off between connection costs and other topological properties of brain networks."
Ref.: Petra E. Vértes, et al., Simple models of human brain functional networks, PNAS, 2012; DOI:10.1073/pnas.1111738109


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I have no doubt that this is true. Follow the money.
And this:
Thomas L. Friedman Wants Us "to be China for a day," to "authorize the right solutions"
This story cannot be true. Liberals love liberty. They stand like Cincinnatus ready to defend it to the death. Money won't sway them at all. They speak truth to power!
China has the one child policy (population control) and roving hi-tech execution vans -what's not for a liberal/progressive/humanist to love there?
An anti-communist being forced out by an American university? Gee, who'da thunk it? < /sarc >


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Mai Fete Island
Mai Fete is one of two islands located on the Lyman Lakes. The island earned its moniker for playing host to the annual Mai Fate pageant, a Carleton tradition that began in 1918. Each Wednesday evening of Spring term, the senior class gathers on Mai Fete to barbecue and celebrate their final term together.
44.4629993794682 -93.1517994403839


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I was preparing a big project documentation, then I added a screenshot to the blog while editing, when I saved it, it showed me absolutely nothing. Now I cannot by any means see my draft blog contents.
Is there any way to retrieve that version of my draft contents please as it is very crucial?
Kind regards,
B Gupta
The blog I need help with is landmapblogdotnet.wordpress.com.


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Quick jump helps Greenwich firefighters save house from blaze
Updated 10:15 pm, Saturday, August 30, 2014
Fire trucks from stations throughout town sped up into the backcountry Saturday night as flames erupted through the roof of a house on Round Hill Road.
No one was injured in the blaze, but people were home at the time -- a fact that helped Greenwich firefighters save the house.
"The wife smelled smoke ... which made all the difference," said Fire Chief Peter Siecienski.
Because the fire was reported by phone call, by someone who could describe what was happening, dispatchers knew immediately that this was in fact a working fire and knew to respond in full. Most calls that come in through automatic alarm only don't actually involve flames.
Engines from the North Street Station were first on the scene, in just under 10 minutes, Siecienski said, followed by Round Hill units.
"Just about every unit in the town of Greenwich responded to this fire at one time," the chief said.
Getting a jump on the response is particularly important in the backcountry, where there are no hydrants and water supply is a concern. Tanker trucks from the Cos Cob station and Banksville, N.Y., sped to the scene to provide water for hoses, which also were fed via a private dry hydrant on a Mooreland Road property that pumped water from a nearby pond.
Still, it took firefighters on scene roughly an hour from the 5:30 p.m. call to extinguish the flames. Firefighters sprayed hoses from ladder trucks through the roof, while others worked from inside on the third floor of the house.
"There was some living area on the floor, but also several confined spaces that caused our firefighters some trouble," Siecienski said.
The roof of the house was destroyed and there was severe damage to the third floor, plus water damage to lower floors, but the structure itself was saved.
Siecienski said about 100 firefighters responded to the scene, plus many Greenwich police units and ambulances from the Greenwich Emergency Medical Service, although no one, including firefighters, needed medical attention.
Trucks from Connecticut Light & Power and Connecticut Natural Gas also responded.
Siecienski said the cause of the fire was not known and under investigation Saturday night.


text: On Thu, 8 May 2003, Hubert Feyrer wrote: > On Thu, 8 May 2003, Thomas Klausner wrote: > > I plan to rip out the parts in bsd.pkg.mk as proposed in PR 21097. > > Any objections (with arguments)? > > Well, do you know in what places we depend on that behaviour? > > I'm far from it, but a few things I remember: > - pkg size calculation (for pkg_info -sS) depends on it "pkg_info -S", as is it is now, isn't all that useful. It's wrong in detail, because the calculation is made at build time without regard for the sizes of the dependencies that the user will actually need. Furthermore, when you talk about packages that top a pyramid of dependencies, it's not even clear what the value means. Certainly, the user might like to know how much space he needs to install a given package with its dependencies, but "pkg_info -S" doesn't give you a clue in that regard. See PR 11433. > - pkg_add has a quick check if all depends are non-conflicting, > withouth possibly downloading things unnecessarily first What scenario is this defending against? In any case, with fewer dependencies, there would be both fewer conflicts, and less opportunites for something not needed to be downloaded. Frederick


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Rabid fans of "Jericho" will only have to wait a couple of more months until the show returns. CBS announced the drama about a town that survives a nuclear attack, will return Feb. 12 at 10 p.m.
If the writers' strike doesn't end soon, midseason shows will be the only new shows in town. Here's hoping that's not the case.


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The DLCS Difference
Dermpath Lab of Central States (DLCS) is a full-service dermatopathology laboratory founded in 1984 by Dr. Tom Olsen. Our team of highly trained board-certified dermatopathologists has been serving physicians and patients for over 30 years. As a national leader in skin pathology, we stand by our commitment to quality, efficient service, and education – all essential to our dedication to patient care.
Our technical team incorporates the newest developments in advanced and molecular testing into our laboratory. DLCS invests significant resources into technology such as digital pathology and lab software systems to provide unparalleled security and efficiency.
DLCS serves as a teaching facility for Wright State University's Boonshoft School of Medicine. Our physicians serve on the faculty at various local universities and provide virtual teaching programs for residency programs nationwide.
Our focus on quality care, combined with state-of-the-art processing and cutting-edge technology, brings the best care possible to you and your patients.
Notice of Security Incident
On April 12, 2017, Dermapathology Laboratory of Central States ("DLCS") became aware of a security incident related to the information portal used for viewing its pathology reports. Upon learning of the incident, DLCS immediately launched an investigation into the matter. Following the investigation, DLCS determined that between October 6, 2013 and April 12, 2017, a vendor that provides information portal services to DLCS failed to properly configure a temporary folder to prevent unauthorized access to the pathology reports of 69 DLCS patients. The patient health information contained in the pathology reports includes patient names, demographic information, Social Security numbers, and clinical information.
DLCS' investigation, which included a sophisticated forensic analysis by a third party and internal reviews of both DLCS and vendor systems, found no evidence of the information having been accessed or obtained by any unauthorized individual or to otherwise suggest criminal fraud or identity theft. Nevertheless, out of an abundance of caution, and in compliance with applicable notification laws, DLCS issued personal notice to those 69 patients that may have been affected by this incident.
If you believe that you did not receive a personal notice due to an address change, wish to confirm whether or not you may have been affected by the security incident, or have additional questions, please call (800) 532-3232 for more information, including credit monitoring eligibility.
DLCS takes very seriously its role of safeguarding patient information and has taken numerous corrective action steps to mitigate potential harm resulting from this incident and to prevent the occurrence of future security incidents.
Our Services
- A highly trained team of board-certified dermatopathologists
- Participation in the majority of healthcare plans
- Friendly customer service and billing staff
- 24- to 48-hour turnaround time
- State of the art in-house lab technologies including molecular studies and advanced testing
- Access to DLCS physicians for consultation anytime


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Soil moisture a different story at 2013 Sunbelt Expo Field Day
By MARTY STEINER
Georgia Correspondent
MOULTRIE, Ga. — Colquitt County, Georgia is generally regarded as the most diverse agricultural county east of the Mississippi. It is natural for a major agricultural exposition to have begun there, and to continue to grow.
The Sunbelt Agricultural Expo began in 1978 on the site of an old World War II Army Air Force training base, Spence Field. This October three-day event now includes more than 1,200 commercial vendors and educational exhibitors spread across 100 acres, and sees more than 200,000 visitors.
In 1987, the expo began a Field Day to tour and present findings of research on the major row crops of the Southeast. There has almost always been a working research farm from the beginnings of the Sunbelt Expo, but a formal tour program didn't begin until under the first farm manager, Darrell Williams. The farm would later be named for Williams upon his death in 2009.
Now in his second year, the farm is managed by Michael Chafin. This year, more than 400 participants boarded Kubota tractor-drawn trams to tour the 600-acre research farm. There were 30 stops during the four-hour tour, with presenters at each stop making short comments and offering informational materials.
Attendees were able to examine actual results of new and improved varieties in an actual commercial-scale environment. Crops include cotton, corn, soybeans, peanuts, hay and even sesame. These same fields will become equipment demonstration and test drive areas at the Expo in October.
Technology underlies almost every presentation. Seed varieties, chemical agents and, of course, equipment all reflect some form of technology.
Water management continues to dominate attention there. Last year "drought" was the word, but after record-setting, almost daily torrential rains this year, the trams struggled through gravel-filled areas with some fields displaying standing water.
Various chemical development companies addressed moisture-related fungi and other crop moisture threats. The cool, wet spring had delayed planting of some crops, though.
Presenters included universities and corporations. A number of universities maintain year-round facilities at the Expo site, as do trade associations and various governmental agencies. Among the universities are the University of Georgia and the University of Florida.
Marcus Evans, director of Field Services and Industry Information for the Georgia Peanut Commission, was one of the attendees. He owns and operates multiple southern Georgia farms and produces a number of commodity crops. With 26 years on the commission, he has attended almost every Field Day.
He observed, "We've had peanut trials and tests every year and even now, have a dedicated, full-time Peanut Commission building on-site at the research farm."
The importance of this annual Field Day was underlined by the presence of the Georgia State commissioner of agriculture, Gary Black, an assistant to U.S. Sen. Johnny Isakson (R-Ga.), as well as a number of state legislators and leaders from the state's peanut and cotton commissions.
Field Day is just an introduction to the 36th annual Sunbelt Ag Expo, which will take place Oct. 15-17. To learn more, visit http://sunbeltexpo.com
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About CSSR
We are a Canadian academic society oriented to the scholarly study of religion.
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