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Responsible Mining
B2Gold is committed to responsible mining. Simply put - this means doing the right thing. Our business decisions incorporate careful consideration of people's health and safety, environmental protection, and community well-being.
Responsible Mining Report
On June 14, 2019, B2Gold launched its third annual Responsible Mining Report. The report provides a detailed overview of the Company's economic, governance, environmental and social performance in 2018, and was compiled in accordance with the Global Reporting Initiative Standards, Core option and the G4 Mining and Metals Sector Disclosures.
Click here for our 2018 Responsible Mining Report, Raising the Bar
B2Gold Canadian CSR Fund
B2Gold invests in sustainable projects in education, environmental conservation, health and livelihoods throughout the world where we operate. As a Canadian company, we are also committed to supporting Corporate Social Responsibility ("CSR") initiatives at home.
Beginning in 2019, our Canadian CSR Fund will be focusing its support on registered charities in the Metro Vancouver area* that address social issues related to: health, children, and people at risk.
If you believe that your organization contributes to these social issues and would benefit from B2Gold's support, please fill in the application form and send to firstname.lastname@example.com. We accept applications at any time, however we only review these three times a year.
*Projects in British Columbia or Canada will be considered if they are highly attractive and exceed in meeting project criteria.
Social Responsibility Policy
B2Gold is committed to making a positive impact in the communities where we work. We recognize that our role in social responsibility extends to all aspects of our activities including health, safety, environment and social. We will understand and integrate social factors into our decision-making process at all stages of our activities - from exploration and operations through to closure and reclamation.
Our social responsibility commitments include:
- Engaging regularly, openly and honestly with our host communities and all stakeholders.
- Understanding the views of people impacted by our operations and considering these in our decision making.
- Respecting and avoiding negative impact on existing cultures and heritage in our host communities.
- Ensuring that our social responsibility is evident in our commitments to responsible health, safety and environmental performance.
- Making positive contributions to society by investing in community development projects in the communities where we operate.
- Committing to sustainable community development in areas of health, education and economic development.
- Respecting human rights and acting with due diligence to avoid infringing on the rights of others, addressing adverse impacts that occur, and facilitating access to remedy.
- Respecting the rights and interests of Indigenous Peoples, and identifying and understanding the interests and perspectives of Indigenous Peoples when seeking to develop or operate a mining activity.
- Sharing our social responsibility commitments with our supply chain.
- Building awareness and capacity to identify, understand and manage the social impacts of our presence.
Employees, contractors and suppliers are expected to demonstrate awareness and act with behavior that supports the intention of this policy.
Community Investment
Many of the regions where B2Gold is working are characterized by low levels of economic development, limited infrastructure and a lack of social support systems for at-risk communities. The opportunity for a mining company to make a positive impact, while operating in these areas, is a fundamental driver of our commitment to responsible mining.
Our community investment programs are focused on sustainable principles that can strengthen a community, provide alternative livelihoods and contribute to alleviation of poverty.
B2Gold's community investment priorities are in areas of public health, education, and small-scale economic development through livelihood generation. Many of our efforts are in partnership with locally based NGOs who have valuable expertise that are critical to successful outcomes.
We work closely with communities to create and implement integrated development programs that take into account local issues, concerns and needs. Recognizing that all mines have a finite life, we are focusing on long-term sustainable development that is independent of our activities.
Education for All in Nicaragua
Investing in community education is one of B2Gold's passions. We believe that education is the foundation for empowering people and enabling a positive transformation in their communities. B2Gold invests in community education programs at all of our major projects world-wide.
Near the mine at El Limon, Nicaragua, B2Gold's "Education for All" program is based on a holistic approach encompassing teacher training, improving access to educational materials, and changing behaviours and attitudes through the celebration of reading. This program is positively impacting teachers and an estimated 350 children in the 13 communities near the mine.
One B2Gold sponsored program with a highly visible impact is the "BiblioBus". This mobile library on a bus visits various communities every month making reading a real event in communities that have limited access to books. Children excitedly line-up whenever the bus comes to town to learn about the world through reading and exchange the book they have read for a new book.
B2Gold also distributes school supplies to help poor or marginalized children attend school wherever we are operating or exploring. We also provide scholarships and bursaries for youth in the Philippines, Namibia and Nicaragua. These programs are part of our commitment to making a meaningful and lasting commitment in the communities where we work.
Creating Alternative Livelihoods in Rural Philippines
A driving philosophy of B2Gold's Community Investment strategy is to assist communities in developing sustainable livelihoods which do not depend solely upon mining activity.
At the Masbate project in the Philippines, B2Gold has supported the development of vegetable farming in areas which did not traditionally support this activity with excellent results.
The initial breakthrough was to encourage farmers to recognize the possibility of growing crops in soil types which were not previously used for this activity. Initially, these crops were sold to the mine's kitchen, but as production increased a small demand for the produce was developed in the local community. Further success by the farmers led to the need to construct a covered market area to expand their commerce. We welcomed the opportunity to finance the construction of this facility.
B2Gold is currently introducing the concept of Integrated Farming as the next step in helping make farming operations sustainable. In a model Integrated Farm, organic waste from livestock is used to improve crop yields that can in turn supply better feed for the livestock. Integrated Farming practices achieve better productivity, reduce negative impacts on the environment, and improve quality of life for farmers.
To date, 943 people have benefitted from these and a range of other projects including fishing, livestock production, sewing, and many agriculture projects. B2Gold's livelihood projects are intended to alleviate poverty and contribute to a sustainable future for the 8 communities near the Masbate Mine.
Measuring Impacts from Investments in Health
When people are not healthy, it can be difficult to take advantage of available opportunities to improve their lives. Therefore, B2Gold believes that an investment in Community Health underpins the success of other initiatives intended to alleviate poverty. Making a positive impact in the communities in which we work is a commitment at B2Gold, so we invest in Community Health wherever we have active projects.
At the Masbate project in the Philippines, B2Gold has initiated and supported several health projects aligned with the priorities of the 8 communities neighboring the mine. In addition to sanitation and water supply projects, these initiatives include support for local health care workers, the establishment of pharmacies serving the local communities, stocking those pharmacies, and providing business management assistance.
In Namibia, the government has been combating major health epidemics such as HIV/AIDS, tuberculosis, and polio. B2Gold supports these initiatives as well as working with local stakeholders to identify other regional health issues that are critically impacting public health. B2Gold projects are focusing on child nutrition, pre-natal care, OBGYN care, and providing needed medical supplies in outlying hospitals.
To ensure that our investments in health initiatives are making meaningful and positive contributions, B2Gold has started measuring the impact of various projects. The Las Brisas school in Managua is one example from Nicaragua.
B2Gold collaborated with the Fabretto Children's Foundation to build and equip a cafeteria and a perimeter wall at Las Brisas School in Managua. The project benefits primary students with reinforcing school security and providing some balanced meals during the school day.
The improvements were made in 2012 and one year later the project is already making a measureable positive impact on the children's health. The Fabretto project has benefitted 413 children, who received nearly 56,000 school lunches in 2012. Improved weight and nutrition standards have already been evident in 11% of the children.
The project also provides education benefits through increased school enrollment, better daily attendance, improved academic performance and increased parent involvement and interest in the school.
B2Gold recognizes the interplay between health and education as the foundation for people to build a better future, and is committed to sustainable community development wherever we work.
Working with Artisanal and Small-Scale Miners
It is estimated that between 20 and 30 million artisanal and small miners are working worldwide, with many of them producing gold. The areas around most of B2Gold's mines and projects globally are also home to small miners. We recognize that many communities maintain their livelihood through artisanal and small mining and we are committed to supporting livelihoods.
In some regions there is a strong history of artisanal mining, sometimes spanning several generations, and individuals wish to continue a tradition of mining. Other individuals are dependent on small mining, but would prefer an alternative livelihood, if such opportunities can be found.
In the Philippines and Nicaragua, B2Gold supports more than 2,600 small miners through professional relationships. We support artisanal miners in the formation of cooperatives and we purchase and process ore from small miner cooperatives. Unlike most artisanal mining activities, B2Gold does not use mercury to produce gold. As a result, the ore purchase arrangement reduces the negative health impacts of mercury on miners and their families, benefits the environment while providing some economic stability for the miners.
In Nicaragua, B2Gold has also created a "Small Miners Affairs" group which actively works to manage issues related to small mining, including support programs, technical solutions, and alternative livelihood projects.
Finally, initiatives with various government and NGO partners are being advanced to provide additional alternative ore processing options and to address safety and environmental risks associated with small-scale mining activity.
Our commitment to pursuing a relationship with artisanal and small-scale miners is driven by concern for the safety of miners and their families, concern for their impact on the environment and a commitment to sustain or improve their livelihoods.
Occupational Health & Safety
B2Gold is committed to the protection and promotion of the safety, human health, and welfare of its employees, communities, and stakeholders.
Occupational Health & Safety Policy
B2Gold Corp. is committed to the protection and promotion of the human health, safety and welfare of its employees. B2Gold's objective is to achieve and maintain zero workplace injuries and occupational illnesses as we believe that all injuries and occupational illnesses are preventable. We further believe that health and safety considerations are integral to and compatible with all other management functions in the organization and that effective health and safety management will enhance rather than adversely affect production or costs.
To achieve this, B2Gold will:
- Utilize the B2Gold OHS Standards and project management systems to identify and eliminate or mitigate occupational health and safety hazards/risks;
- Ensure compliance with all applicable statutory obligations, relevant industry guidelines and internal and external safety and health standards;
- Ensure that management holds employees and contractors accountable for their safety and health performance;
- Establish clearly defined occupational health and safety programs complete with clearly established targets and performance indices;
- Make working safely a condition of employment;
- Ensure that all employees and contractors are trained to understand their health and safety responsibility in accordance with the Company's policies and procedures;
- Ensure that all employees and contractors use proper personal protective clothing and the correct equipment for the task;
- Recognize and reward safe behaviour by employees and contractors;
- Prepare for and maintain capability to effectively respond to emergencies and crises;
- Investigate the causes of accidents and incidents and develop effective preventative and remedial actions; and
- Monitor, assess and audit our operations to ensure continuous improvement of our occupational health and safety performance.
All employees, contractors and site visitors of B2Gold are expected to adhere to the commitments defined in this policy.
La Libertad Mine Receives Occupational H&S Award
La Libertad Mine is B2Gold's largest operation in Nicaragua, with more than 1,400 full time staff and contractors. B2Gold is committed to the implementation of superior occupational health and safety management practices and recognizes that a safe operation will protect its workers and deliver superior results for all stakeholders.
In October 2012, La Libertad mine's implementation of these health and safety principles was recognized by Nicaragua's National Counsel for Safety and Hygiene and the Ministry of Labour. La Libertad was distinguished by the Counsel as a Corporate Leader in the area of worker health, safety and hygiene. The Corporate Leader designation is the top prize awarded in Nicaragua in the area of occupational health and safety.
B2Gold is committed to minimize the impact on and conserve the quality of the environment in areas where we operate.
Environmental Policy
B2Gold Corp. is committed to minimizing the impact on and conserving the quality of the natural environments in areas where we operate. As part of our corporate environmental commitment, B2Gold will provide sufficient resources to ensure environmental risks are adequately addressed during all phases (exploration, design, construction and closure) of each project.
To achieve this, B2Gold will:
- Utilize the B2Gold Environmental Standards and project management systems to identify and eliminate or mitigate environmental impacts;
- Apply a proactive risk-management approach to safeguard and protect the environment;
- Ensure compliance with all applicable statutory obligations, relevant industry guidelines and internal and external environmental standards;
- Foster and maintain an environmentally responsible culture, behaviour and awareness within the workplace;
- Encourage open dialogue and maintain processes for receiving and responding to stakeholder concerns with respect to our environmental commitments;
- Encourage workforce behaviours that promote environmental stewardship;
- Conserve and protect local water resources;
- Adopt appropriately funded reclamation strategies for B2Gold operations from exploration through closure;
- Prepare for and maintain capability to effectively respond to emergencies that involve hazardous substances; and
- Monitor, assess and audit our operations to ensure continuous improvement of our environmental performance.
All employees, contractors and site visitors of B2Gold are expected to adhere to the commitments defined in this policy. B2Gold is proud of its commitment to the environment and will continually strive to improve our environmental performance and reduce our environmental impact.
B2Gold is committed to the conservation of biodiversity and integrated approaches to land use planning at our operations.
Biodiversity Policy
B2Gold Corp. is committed to the conservation of biodiversity and an integrated approach to land use planning. This commitment includes respecting legally protected areas and species, understanding the interfaces between mining and biodiversity, identifying areas of our operations that may have a negative impact on biodiversity, and implementing mitigation measures for impacts on biodiversity and the rehabilitation of affected areas.
To achieve this, B2Gold will:
- Maintain natural ecosystems and manage protected areas that may be either directly or indirectly impacted by our project activities;
- Respect indigenous people's rights and values for natural resources and involve them in developing and agreeing on appropriate management strategies for potential impacts;
- Comply with all applicable statutory obligations relating to biodiversity;
- Provide employee awareness programs related to the protection of biodiversity;
- Conserve biodiversity by identifying and avoiding potential habitat destruction and exploring and implementing mitigation strategies when loss of habitat is unavoidable;
- Conduct impact assessments and apply risk management when situations identify potential adverse impacts on biodiversity;
- Consult with relevant stakeholders on issues relating to biodiversity;
- Adopt reclamation and closure strategies that protect the biodiversity of areas impacted by our operations.
B2Gold Corp. recognizes that mining has the potential to result in significant impacts on biodiversity. Biodiversity conservation and the mitigation of potential biodiversity impacts are supported by the organization's senior management.
Going Beyond Compliance for Biodiversity Conservation
The town of Santo Domingo is located roughly 110 kilometres east of Managua and is home to about 12,000 people. The area has a mining history dating back to the mid-1800's, and cattle farming is also an important local activity. The Santo Domingo project, located near the town, is being developed as part of B2Gold's largest operation in Nicaragua – the La Libertad Mine.
The development of a mining project has impacts on the surrounding flora and fauna. As part of its commitment to the conservation of biodiversity, B2Gold has established a Wildlife Refuge as a measure to mitigate the potential impacts of the Santo Domingo project on the local flora and fauna. The Santo Domingo Wildlife Refuge has been established on 84 hectares of land purchased by B2Gold.
The Refuge provides protected habitat for the relocation of flora and fauna from the Santo Domingo project area. The first phase of the Santo Domingo Wildlife Refuge consists of the rescue of plants and animals. As of the 3rd quarter of 2013, more than 11,000 plants (trees, orchids, etc.) and over 400 animals - including species of amphibians (63%), reptiles (21%), mammals (10%) and crustaceans (6%) – have been rescued and relocated to the Wildlife Refuge. This flora and fauna rescue and relocation program is the first of its kind in Nicaragua.
To manage the Wildlife Refuge, B2Gold has collaborated with the local community and the Friends of the San Juan River Foundation. Members of the local community have been trained in theoretical and practical aspects of plant and animal care, in safe capture methods for animals, and Flora and Fauna Rescue Brigades have been established. A Management Plan for the Refuge has been developed and implemented in alignment with the guidelines of the Ministry of Environment and Natural Resources.
Trained Officers monitor the relocation efforts, the biodiversity, and the anthropogenic use and/or impacts within the Refuge. Future plans include the installation of an interpretation centre and interpretative footpaths. The Wildlife Refuge is helping to ensure the long term viability of the biodiversity in the area surrounding the Santo Domingo project.


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UART character matching used for address matching on a register-by-register basis
An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match registers for special framing characters. Further, however, address bits are provided within the serial data, and additional matching bits are provided for matching those address bits along with the character data within the matching registers. In this way, not only is framing data detected by the detection of special characters, but a microcontroller can determine when it is being addressed in a multidrop, address bit protocol system by matching the address bit and address data.
Latest Advanced Micro Devices, Inc. Patents:
1. Field of the Invention
The invention relates to microcontrollers, and more specifically, to a microcontroller having an improved asynchronous serial interface.
2. Description of the Related Art
Specialized microcontrollers with integrated communication features are becoming particularly attractive for communications applications. A microcontroller, or an embedded controller, is uniquely suited to combining functionality onto one monolithic semiconductor substrate (i.e. chip). By embedding various communication features within a single chip, a communications microcontroller may support a wide range of communication applications.
Microcontrollers have been used for many years in many applications. A number of these applications involve communications over electronic networks, such as telephone lines, computer networks, and local and wide area networks, in both digital and analog formats. In communications applications, a microcontroller generally has a number of integrated communications peripherals in addition to the execution unit. These can be low and high speed serial ports, as well as more sophisticated communications peripherals, such as a universal serial bus (USB) interface, and high level data link control (HDLC) channels.
An asynchronous serial communications port is one such common additional feature in a microcontroller. An asynchronous serial link allows the microcontroller to communicate with other devices or over data lines by sequentially sending and receiving bits of data. The "asynchronous" nature indicates these ports do not provide a separate clock signal to clock the data. Instead, the rate at which data is sent and received must be predetermined or prenegotiated, and independently controlled on both the sending and receiving ends. This data rate is known as the baud rate, which is the inverse of one bit period. The baud rate is generally one of a number of predefined rates, which are standard within the industry. Such rates include 1200, 2400, 4800, 9600, 19.2K, 28.8K, 33.3K, and 54K baud and high data transfer rates.
Due to the prevalence of serial data communication, many microcontrollers include one or more asynchronous serial ports (ASPs) which can transmit and receive data one bit at a time. Such microcontrollers typically employ interrupt signals to notify the microprocessor core that an ASP requires services. An ASP typically issues an interrupt request signal when a data unit has been received by the ASP and needs to be transferred from the ASP to an external memory unit, when the ASP is finished transmitting a data unit and the next data unit to be transmitted must be transferred from the external memory unit to the ASP, or when an error occurs.
An ASP can be configured for a variety data formats, although historically seven or eight data bits are typical values. A number of nine-bit serial protocols, however, have been developed using microcontrollers, including a nine-bit asynchronous serial protocol in conjunction with direct memory access. Such protocols are described in U.S. patent application Ser. No. 08/807,103, now U.S. Pat. No. 5,896,549 entitled A MICROCONTROLLER WHICH IS CONFIGURABLE TO TRANSFER DATA TO AND FROM ONE OR MORE ASYNCHRONOUS SERIAL PORTS USING DIRECT MEMORY ACCESS, filed Feb. 4, 1997, by John P. Hansen and Melanie D. Typaldos, and U.S. patent application Ser. No. 08/775,262, now U.S. Pat. No. 5,978,865 entitled A MICROCONTROLLER HAVING HARDWARE FEATURES SUPPORTING 9-BIT SERIAL PROTOCOLS DURING DMA DATA TRANSFERS TO AND FROM ONE OR MORE ASYNCHRONOUS SERIAL PORTS, filed Feb. 4, 1997, by John P. Hansen, Ronald W. Stents, and Melanie D. Typaldos, both of which are commonly assigned and hereby incorporated by reference. These protocols are also described in the Am186E S Users Manual and Am186ED Users Manual, both by Advanced Micro Devices, Inc. of Sunnyvale, California. As described in those applications, and as discussed below, a separate control bit is set or reset to act as the ninth data bit during transmission and reception of data. To support DMA using such 9-bit protocols, when that particular bit is received as a certain value, an interrupt is caused to indicate that the ninth data bit has in fact been set.SUMMARY OF THE INVENTION
In a system according to the invention, a microcontroller provides an asynchronous serial port that includes character matching registers. These registers cause an interrupt or an appropriate status bit to be set within an asynchronous serial port when a data item matching the stored character is received. According to the invention, however, this character matching is extended to support address matching. Specifically, an extra address bit match value is provided in a register corresponding to the character matching registers such that if the address bit match value is set and address bits are being employed in the serial protocol, a character does not match in the corresponding character matching register unless the address bit is also set.
In this way, certain of the character matching registers can be set to match data being transmitted over the asynchronous serial port, while other of the character matching registers can be set to match a particular address transmitted during an address frame. This is particularly useful in multidrop systems, where the microcontroller can be programmed to perform an interrupt to the execution unit when a particular address--the address programmed for the particular peripheral device implementing the microcontroller, for example--is received over the asynchronous serial port.BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a block diagram of a typical microcontroller implemented according to the present invention;
FIG. 1B is a schematic pinout diagram of the pinouts for the microcontroller of FIG. 1A;
FIG. 2 is a block diagram illustrating the relationship between the asynchronous serial port, the DMA controller, and their registers to the microcontroller of FIGS. 1A and 1B;
FIG. 3 is a timing diagram illustrating the use of address bits within an asynchronous serial frame according to the invention;
FIG. 4 is a diagram illustrating the DMA unit data compression according to the invention;
FIG. 5 is a diagram illustrating the DMA unit data expansion according to the invention;
FIGS. 6A-6E are block diagrams illustrating register contents in a DMA unit according to the invention;
FIGS. 7A-7G are block diagrams illustrating the register contents in the asynchronous serial port according to the invention; and
FIG. 8 is a block diagram illustrating the implementation of multidrop asynchronous protocol.DETAILED DESCRIPTION OF INVENTION RELATED APPLICATION
The following related applications are hereby incorporated by reference:
U.S. patent application Ser. No. 08/920,930, now U.S. Pat. No. 5,958,024 entitled A METHOD AND APPARATUS FOR SUPPORTING HIGH DATA RATES OVER AN ASYNCHRONOUS SERIAL LINE USING DMA, filed Aug. 7, 1997 by Melanie D. Typaldos and Patrick E. Maupin.
U.S. Patent Application, bearing Attorney Docket No. A97323US, entitled COMPRESSION AND DECOMPRESSION OF SERIAL PORT DATA AND STATUS USING DIRECT MEMORY ACCESS, filed concurrently, by David A. Spilo and Melanie D. Typaldos.
Turning to FIG. 1A, shown is a block diagram of a typical microcontroller M implemented according to the invention. Such a microcontroller is preferably implemented on a single monolithic integrated circuit.
The microcontroller M preferably includes an internal bus 100 coupling, an execution unit 124, system peripherals 174, memory peripherals 176 and serial communication peripherals 172. The execution unit 124 in the disclosed embodiment is compatible with the AM186 instruction set implemented in a variety of microcontrollers from Advanced Micro Devices, Inc., of Sunnyvale, Calif. A variety of other execution units could be used instead of the execution unit 124. The system peripherals 174 include a watch dog timer (WDT) 104 for generating non-maskable interrupts (NMIs), microcontroller resets, and system resets. An interrupt controller 108 for supporting thirty-six maskable interrupt sources through the use of fifteen channels is also provided as a system peripheral. One disclosed system peripheral is a three channel timer control unit 112. The timer control unit 112 includes three 16-bit programmable timers. Another system peripheral is a general purpose direct memory access (DMA) unit 116 with four channels 0-3. A programmable I/O unit 132 of the microcontroller M supports user programmable input/output signal (PIOs). In the disclosed embodiment, forty-eight PIOs are provided.
The memory peripherals 176 of the disclosed microcontroller include a DRAM controller 170, a glueless interface 168 to a RAM or ROM, and a chip select unit 126. In the disclosed embodiment, the DRAM controller 170 is fully integrated into the microcontroller M. Also in the disclosed embodiment, the chip select unit 126 provides six chip select outputs for use with memory devices and eight chip select outputs for use with peripherals.
A low speed serial port implemented as a universal asynchronous receiver/transmitter (UART) 136 is provided as a serial communication peripheral. The low speed UART 136 is typically compatible with a standard 16550 UART known to the industry. Another serial communication peripheral in the disclosed embodiment is a synchronous serial interface (SSI) 140. Preferably the microcontroller M acts as a master in the synchronous serial interface 140, which is a standard synchronous serial channel.
The microcontroller M in the disclosed embodiment is particularly well suited to communications environments. To this end, the serial communication peripherals 172 of the microcontroller M include a number of high speed communication controllers, including a High-level Data Link Control (HDLC) controller 144, a Universal Serial Bus (USB) controller 146, and a high speed serial port (HSUART) 148. The disclosed HDLC controller 144 provides four HDLC channels 164. The HDLC channels 164 and the USB controller 146 can be written to and read from by a "SmartDMA" unit 150, a unit which provides for chained buffers that are accessed via pairs of DMA channels. The SmartDMA unit 150 allows for a high degree of packetized transfer without excessive execution unit 124 intervention. The SmartDMA unit 150 preferably consists of four SmartDMA controllers, SmartDMA0-3, that each consists of a pair of DMA channels.
The HSUART 148 serves to form an asynchronous serial link across a bus to devices external to the microcontroller M. The asynchronous nature indicates that the HSUART 148 does not provide a separate clock signal to clock the data. Instead the rate at which data is sent and received must be predetermined or determined through autobauding and independently controlled on sending and receiving ends. This data rate is known as the baud rate. It should be understood that the microcontroller M may include multiple HSUARTs 148.
The disclosed HDLC controller 144 also includes an interface multiplexer 162. This multiplexer 162 couples the four HDLC channels 164, four time slot assignors (TSA) 166, and a number of external buses. Specifically, using the time slot assignors or otherwise, the HDLC channels 164 can be selectively coupled to a pulse code modulation (PCM) highway, a general circuit interface (GCI), an ISDN oriented modular interface revision 2 (IOM-2) serial bus, a data carrier equipment (DCE) serial interface, and other general and specific interfaces that often use packetized communication. Further, the HDLC channels 164 support HDLC, SDLC, Link Access Procedures Balanced (LAPB), Link Access Procedures on the D-channel (LAPD), and PPP, and as noted above, each include an independent time slot assignor 166 for assigning a portion of a serial frame to each HDLC for isochronous or isochronous-type communication.
Turning to FIG. 1B, shown are illustrative pinouts for the microcontroller M implemented according to the invention. Illustrated are clock pinouts for the clock 102, address and address/data bus pinouts to the bus interface unit 120, bus status and control pinouts, again generally for the bus interface unit 120, timer control pinouts coupled to the timer control unit 112, USB control and transceiver control pinouts for the USB controller 146, synchronous serial controller pinouts for the synchronous serial interface 140, programmable I/O pinouts for the programmable I/O unit 132, reset control pinouts, memory and peripheral control pinouts coupled to both the chip select unit 126 and the bus interface unit 120, DMA control pinouts for the general purpose DMA unit 116 and the SmartDMA unit 150, HDLC channel/DCE interface/PCM interface pinouts for coupling to the HDLC controller 144, UART pinouts for the low speed UART 136, and high speed UART pinouts for the HSUART 148. All of these pinouts, of course, are illustrative, and a wide variety of other functional units and associated pinouts could be used without detracting from the spirit of the invention. For example, a number of both the communications and general purpose peripherals from FIG. 1A could be eliminated, or added to, without detracting from the spirit of the invention.
The techniques and circuitry according to the invention could be applied to a wide variety of microcontrollers and other similar environments. The term "microcontroller" itself has differing definitions in industry. Some companies refer to a processor core with additional features (such as I/O) as a "microprocessor" if it has no onboard memory, and digital signal processors (DSPs) are now used for both special and general purpose controller functions. As here used, the term "microcontroller" covers all of the products, and generally means an execution unit with added functionality all implemented on a single monolithic integrated circuit.
Turning to FIG. 2, further illustrated are the DMA unit 116 and the high speed UART 148, here described as an asynchronous serial port (ASP) 148. This is further described in previously incorporated application entitled A METHOD AND APPARATUS FOR SUPPORTING HIGH DATA RATES OVER AN ASYNCHRONOUS SERIAL LINE USING DMA. The ASP 148 can support an asynchronous serial protocol that employs an "address bit" as an extra serial bit.
Referring to FIG. 3, illustrated is an asynchronous serial transmission employing such a protocol. After a start bit 200, the ASP 148 transmits or receives 7 or 8 data bits 202. These are standard data bits sent in an asynchronous protocol, low order bit first. After the 7 or 8 data bits 202, however, the address bit protocol supported by the ASP 148 provides for an optional address bit AB 204. This address bit is typically either the 8th or 9th bit transmitted or received by the ASP 148, and is typically used in applications such as multi-drop applications that require one master device to control multiple slave devices. Although called an address bit, this bit can act as an extended bit that effectively causes interrupts within the slave devices for flow and other control. This address bit protocol is known to the art.
After the optional address bit AB 204, an optional parity bit PB 206 is then followed by a stop bit ST 208, and then an optional second stop bit ST 2210.
Returning to FIG. 2, the DMA unit 116 and the ASP 148 have additional features according to the invention that may be useful in sending and receiving data that employs an address bit AD 204 as illustrated in FIG. 3. These features are best understood by examining a set of registers within the DMA unit 116 and the ASP 148, here shown as DMA registers 212 and ASP registers 214. The DMA registers 212 will be further discussed in conjunction with FIGS. 6A-6E, and the ASP registers 214 will be further discussed in conjunction with FIGS. 7A-7G.BYTE-TO-WORD EXPANSION AND WORD-TO-BYTE COMPRESSION DMA UNIT
In one aspect of the microcontroller M according to the invention, the DMA unit 116 can compress and decompress data during transfers between a source and a destination that have two differing data sizes. For example, the DMA unit 116 can read data byte-by-byte from a source memory block, and write each read byte of data as the low (or high) order byte of consecutive words in a destination memory block. Conversely, the DMA unit can read the low order byte of consecutive words of data from a source block, and then store those read bytes consecutively in a destination block. This is especially helpful in conjunction with the ASP 148 when it is used in an extended read and write mode. As further discussed below in conjunction with FIGS. 7A-7G, and as previously described in the concurrently pending application METHOD AND APPARATUS FOR SUPPORTING HIGH DATA RATES OVER A ASYNCHRONOUS SERIAL LINE USING DMA, the ASP 148 can read in 7 or 8 bit data units over a serial line, but store that data into a 16-bit word along with both an address bit and status bits corresponding to that I/O read. These are further illustrated in FIG. 7G, discussed below, but to summarize, parity errors, overrun errors, framing errors, character matches, breaks, the address bit, and other status can be stored along with 7 or 8 bits of data actually received. When this is performed using DMA, this allows the execution unit 124 to go back and examine the received data to determine where any errors may have occurred or address bits may have been set, and process the data accordingly.
But once errors are examined and address bits are processed, typically the received data no longer needs that associated status. That is, the execution unit 124 can then simply store the data as 7 or 8 bit data within bytes instead of as words.
It is at this point that the DMA unit 116 is especially advantageous. Referring to FIG. 4, illustrated is the DMA unit 116 processing data from the ASP unit 148 as discussed. The DMA unit 116 stores this data in a memory 216 as a series of data and status bytes within a block 218, shown as DATA1, STATUS1, DATA2, STATUS2, etc. So, each 7 or 8 bit data value DATA1-DATAn occupies 16 bits when combined with its associated status byte STATUS1-STATUSn.
The DMA unit 116, however, can then be programmed by the execution unit 124 to perform a transfer from the block 218 to another block 220 in the memory 216, but this block to include simply a number of the consecutive data values DATA1-DATAn but without the associated status. The DMA unit 116 first reads the first data item DATA1 and from the block 218 then writes it to the destination location DATA1 in the block 220. Then, however, the DMA unit 116 increments the destination address within the block 220 by 1 but simultaneously increments the source address in the block 218 by 2. Therefore, the next data item read from the block 218 is DATA2 (STATUS1 is skipped), which is then written as a byte in the destination block 220 immediately after the first data item DATA1. This is repeated, compressing the data such that the original 16-bit data and status values are now simply 8-bit data values.
Turning to FIG. 5, the reverse is illustrated for writes by the ASP 148 of external data. Here, a source data block 222 contains data that the microcontroller M should transmit to an external asynchronous serial line. This data includes four data items DATA4 that each occupy 7 or 8 bits within a byte of memory. The DMA unit 116 is programmed to read the first of these data items DATA1 in the block 222, and then write that data item DATA1 into a destination block 224. Then, the source address within the data block 222 is incremented, but the destination address within the destination block 224 is incremented by 2. Thus, the next data item DATA2 is read from the source block 222, but is written 2 bytes later into the destination block 224.
Before that data is actually transmitted, it may be desirable for the execution unit 124 to clear address bits that are stored in the intervening bytes of the data items DATA1-DATA4 in the destination block 224. Here, three address bits 226 are shown cleared, and one address bit 228 set.
The DMA unit 116 is then programmed to perform word-size writes to the ASP 148 using the extended write capability of the ASP 148. The low order bit of the high order byte is then used as the address bit for transmission of data, resulting in four illustrated data items 230, 232, 234, and 236, the first of which has its address bit set and the remainder of which do not.
The DMA unit 116 may include more than one DMA channel, and those DMA channels can be implemented as circular buffers. It would be further possible to implement two channels in FIG. 4 such that one channel was reading extended data from the ASP 148 and then writing it into a circular buffer implemented as the buffer 218, and then a second channel was reading from the buffer 218, compressing the data into the destination buffer 220.
By providing compression and decompression of data by the DMA unit 116, the execution unit 124 is relieved of the processing overhead required to strip or add unneeded status information from or to data before the DMA unit 116 sends or receives data to the ASP 148.
Turning to FIGS. 6A-6E, illustrated are five of the DMA registers 212 employed to implement the compression and decompression according to the invention. In FIG. 6A, illustrated is a general purpose DMA channel "x" control register GDxCON0 300. (Note with four channels, the "x" would be from 1 to 4.)
The GDxCON0 register 300 includes a number of standard general purpose DMA control bits, such as a start/stop bit ST 302, an auto start bit AST 304, a terminal count stop bit TC 306, an interrupt enable bit INT 308, a priority field P 310, and a DMA request source field DSEL 312.
The GDxCON0 register 300 also includes a transfer size bit TS 314. This bit selects whether the channel will transfer a byte of data at a time (TS=0, or 1'b0), or will transfer a word at a time, (TS=1'b1). With the compression and decompression functions according to the invention, the TS bit 314 will generally be set to 0 for byte size transfers.
Turning to FIG. 6B, illustrated is a second general purpose DMA control register GDxCON1 316. The GDxCON1 register 316 also includes a number of standard DMA bits, such as a source address space select bit SM/*IO 318, a source address wrap field SAW 320, a destination address space select bit DM/*IO 322, and a destination address wrap field DAW 324. The SM/*IO bit 318 and the DM/*IO bit 322 select whether the source and destination space will be memory or I/O.
When the source or destination address space is to be in memory, generally it is desirable to increment or decrement a source and destination address after the data is sent or received. To this end, two fields are provided, a source increment field SINC 326 and a destination increment field DINC 328. These are 4-bit 2's complements values that are added to the source and destination pointer after each transfer. For example, if the SINC field 326 or the DINC field 328 are 0, there is no increment. If they are equal to a binary 1, or 4'b0001, the fields are incremented by 1. If they equal 4'b0010, the pointers are incremented by 2 bytes, if equal to 4'b0011, incremented by 3 bytes, and so on. For negative values the opposite is true. For example, using 2's complement format, if the SINC or DINC fields 326 or 328 are equal to 4'b1111, the source or destination address will be decremented by 1 after the transfer.
By providing a separate SINC field 326 and DINC field 328, and further by providing that the amount of increment or decrement is independent of the size of the data item, compression or decompression of data using DMA can be affected. This is further discussed below again in conjunction with FIGS. 4 and 5.
Turning to FIGS. 6C and 6D, illustrated are source address registers 330 and destination address registers 332. Finally, turning to FIG. 6E, illustrated is a transfer count register 334. These are all well understood in conjunction with the DMA design.
Returning to FIGS. 4 and 5, and given the registers described in FIGS. 6A-6E, the programming and operation of the DMA unit 116 for compression is better understood. In FIG. 4, for the transfer between the ASP 148 and the destination block 218, the DMA unit 116 is programmed with a set of values 336. Specifically, the source is set to be from an I/O location, and to increment by 0 after each transfer (appropriate for an I/O location), and the destination is set to memory and is set to increment by 2 after each transfer. Further, the data size is set to a word. This provides that each transfer will be a 16-bit extended serial read value from the ASP 148, which is stored word-by-word in the destination block 218.
For the compression function, the DMA unit 116 is programmed with a set of values 338. Specifically, the source is set in memory (and the source address 330 will be set to the start of the source block 218), and is set to increment by 2 after each transfer. The destination is also set in memory, but the destination address is incremented by only 1 after each transfer. Finally, the transfer size is set for 1 byte. This means that 1 byte will be read from the source block 218 and written to the destination block 220 as DATA1. The source address 330, however, will then be incremented by 2, while the destination address 332 will only be incremented by 1. Then a second byte of data, DATA2, will be read from the source block 218 and written immediately after DATA1 in the destination block 220. Thus, unneeded status information in STATUS1 is skipped.
Of note, the destination block 220 could be programmed to actually overlap with the source block 218 because after the data is read from the source block 218, it is no longer needed. Thus, the source buffer can literally be used as the destination buffer, saving memory space.
Turning to FIG. 5, the expansion capability of the DMA unit 116 is illustrated by a set of programmed values 340. Here, the source block 222 of 8-bit data is expanded by setting the DMA unit 116 to transfer from memory to memory, by setting the SINC field 326 to a value of 1, but setting the DINC field 328 to a value of 2. The transfer size bit TS 314 is set to 0, such that data is transferred a byte at a time. With this programming, a data byte is read from the source block 222 and written to the destination block 224, but the next data byte consecutively read from the source block 222 is written 2 bytes later in the destination block 224. The execution unit 124 can then appropriately set or reset the address bits AB, in the destination block 224, and institute a second DMA transfer to the ASP 148.
Here, a set of programmed values 342 is used, which provide for a source in memory and destination in I/O space, and provide for a source increment SINC 326 value of 2 and no destination increment. Further, the transfer size bit TS 314 is set to 1 for word transfers. This results in the extended data being written to the ASP 148, so that it can control the 9th, address bit on its transmission of serial data.
Therefore, by providing independent controllability of the source increment and destination increment independent of the size of the data being transferred, compression and decompression of memory can be affected. This could be used for a variety of other functions in which it was desirable to compress word data into byte data, or vice versa.CHARACTER MATCHING USING ADDRESS BITS
Turning to FIGS. 7A-7G, illustrated are certain of the ASP registers 214 that implement another feature according to the invention. FIG. 7A illustrates 6 character match bytes employed by the ASP 148 for matching characters of received data. Specifically, three registers HSPM0 400, HSPM1 402, and HSPM2 404 contain 6 character match values MCHR0 406 through MCHR5 415.
The operation of these byte size values MCHR0 406 through MCHR5 415 is better understood in conjunction with FIG. 7G, which illustrates an asynchronous serial port 418 receive register HSPRXD 416. This register contains a 7 or 8 bit value received data RDATA 418, but also contains 8 status bits 420 through 434.
Historically, only the received data RDATA 418 was compared to the match character values MCHR0 406 through MCHR5 415. When the RDATA value 418 matched one of those matched character values, a status bit was set in a status register, illustrated below in conjunction with FIG. 7D, and an interrupt was generated if an appropriate mask value was set, illustrated below in conjunction with FIG. 7E. Historically, the address bit AB 204, would be reflected as first a bit within the extended data of the HSPRXD register 416 (here the address bit value AB 434), and could also be found in the status register discussed below in conjunction with FIG. 7D. The address bit would not, however, be used to match with one of the character matched values MCHR0 406 through MCHR5 415.
According to the invention, additional bits are provided such that when set, the address bit value AB 434 is matched in addition to the RDATA value RDATA 418.
This is better understood in conjunction with a high speed serial port control register HP CON0 436, illustrated in FIG. 7C. This register in part provides configuration settings to determine whether an address bit is going to be employed (indicated by an ABEN bit 442), whether the parity bits PB 206 will be used (indicated by a parity enable bit PEN 440), whether 7 or 8 bit data will be used and thus whether the D7 bit of the bits 202 will be used (indicated by enable bit D7 444), and whether the second stop bit ST2 210 will be used (indicated by a second stop bit enable bit STP2 446). When data writes, an address bit set or reset bit AB 438 sets or resets the transmitted address bit, as long address bit communication is enabled (controlled by the ABEN bit 442).
All of these bits 438 through 446 affect the length of a transmitted frame. In the disclosed embodiment, and historically, however, even if the receive data 418 is 7-bit data (the D7 bit 444 false) and an address bit is enabled (the ABEN bit 442 is true), the RDATA 418 would not include the address bit. Instead, that would still be stored in the high order byte of the HSPRXD register 416 as the address bit AB 434. Thus, that bit would never be matched with any of the match characters MCHR0 406 through MCHR5 415.
According to the invention, however, additional match character address bit MATCH bits are provided in a second control register HSPCON1 448. Specifically, this register 448 includes a match enable bit MEN 450, which when true, enables the character matching of the MCHR0 406 through MCHR5 415. According to the invention, however, additional character matching bits are provided. Three match address bits MAB2 452, MAB1 454, and MAB0 456 effectively become an address bit matching bit for the three match registers HSPM0 400 through HSPM2 404 when the address bit is enabled by the ABEN bit 442 of the control register HSPCON0 436.
For example, when the MAB2 bit 452 is 0 and the ABEN bit 442 is 1, a received character must have its address bit AB 204 clear to match characters in the HSPM2 register 404. When the MAB2 bit 452 is set, and the ABEN bit 442 is true, a received character must have its address bit AB 204 set in order to match characters in the HSPM2 register 404. The MAB1 bit 454 and the MAB0 bit 456 similarly correspond to the HSPM1 register 402 and the HSPM0 register 400.
Thus, these additional bits in the HSPCON1 register 448 provide for address matching for corresponding ones of the HSPM0 register 400 through HSPM2 register 404. The ASP 148 could be set up where one of the registers HSPM0 400 through HSPM2 404 was set for character matching, while the other two were set for address matching.
The HSPCON1 register 448 further includes an extended write bit 458 and an extended read bit 460, which provide, when true, that 16-bit data will be read from a transmit register HSPTXD 462 (see FIG. 7F) or received in the receive register HSPRXD 416 (see FIG. 7G). When these values are disabled, only 8-bit data is stored in those registers, and the address bit and the match status can only be determined by reading a status register HPSTAT 464 (see FIG. 7D). That status register 464, among other things, includes a match bit MATCH 466 which is set true if the incoming data is a character or address match (as appropriate) to one of the HSPM0-HSPM2 registers 400-402 and an address bit AB 468 which is set true if the incoming data has its address bit set. An interrupt mask register HSPIMSK 470 correspondingly passes on the match bit MATCH 466 and the address AB 468 as interrupts.
Turning to FIG. 8, illustrated is a multidrop system in which the address bit matching according to the invention could be used. A host system 500 transmits serial data to multiple multidrop peripherals 502, 504, and 506. Each of these peripherals includes a microcontroller M of its own 508, 510, and 512. Each of these can be programmed such that it had a unique address 1, 2, and 3 for the peripherals 502, 504, and 506. Each can be placed into an idle mode where received characters are effectively dumped by each of the peripherals 502, 504, and 506 until one of the peripherals has an address match. For example, the microcontroller 508 of the peripheral 502 could be programmed such that the MCHR0 byte 406 contained the appropriate addressing information, including the "1" address assigned to the peripheral 502, and its associated address matching bit MAB0 456 would be set, along with the address bit enable ABEN 442. In this way, when the host 500 sent a frame of asynchronous data with the appropriate address matching MCHR0 406 to the peripheral 502, that data would match the character in MCHR0 406 and the address bit being set would match the MAB0 456 bit. Therefore, the match bit MATCH 466 would be set in the HPSTAT register 464, and, assuming the match interrupt was set to pass in the HSPIMSK register 470, an interrupt would be passed to the execution unit 124 so that the peripheral 502 could be awaken and set to process subsequent data.
Thus, providing both character matching and address matching independently for certain of the match address registers, the asynchronous serial port according to the invention could not only detect the start and end of data frames based on matchable character data, but can also detect when a particular microcontroller is being addressed in a multidrop system by also matching the address bit. This provides for added flexibility in applications of the microcontroller M.
While techniques according to the invention have been described in conjunction with asynchronous communication ports, they can similarly be used with synchronous communication ports for compression and decompression and for address matching.
The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the details of the illustrated apparatus and construction and method of operation may be made without departing from the spirit of the invention.
1. A microcontroller comprising:
- an execution unit for executing instructions; and
- an asynchronous serial port supporting address bits, comprising:
- a plurality of character matching registers that upon the asynchronous serial port receiving asynchronous data that matches one of the plurality of character matching registers, causes a character match to be indicated; and
- a plurality of address match bits associated with the plurality of character matching registers, such that a character match indication can be further conditioned by the match of an address bit on received data.
2. The microcontroller of claim 1, wherein the address match bits are held in a different register than the character match registers.
3. The microcontroller of claim 1, wherein the UART is a high speed UART.
4. The microcontroller of claim 1, wherein the transmission and reception of address bits is enabled by an address bit enable bit in a control register.
5. The microcontroller of claim 1, wherein the character matching and address bit matching is configurable for matching 8 bits of character data plus an address bit.
6. The microcontroller of claim 1, wherein the character matching and address bit matching is configurable for matching 7 bits of character data plus an address bit.
7. The microcontroller of claim 1, wherein an interrupt is generated upon a character match.
8. An asynchronous serial port supporting address bits, comprising:
- a plurality of character matching registers that upon the asynchronous serial port receiving asynchronous data that matches one of the plurality of character matching registers, causes a character match to be indicated; and
- a plurality of address match bits associated with the plurality of character matching registers, such that a character match indication can be further conditioned by the match of an address bit on received data.
9. The microcontroller of claim 8, wherein the address match bits are held in a different register than the character match registers.
10. The asynchronous serial port of claim 8, wherein the UART is a high speed UART.
11. The asynchronous serial port of claim 8, wherein the transmission and reception of address bits is enabled by an address bit enable bit in a control register.
12. The asynchronous serial port of claim 8, wherein the character matching and address bit matching is configurable for matching 8 bits of character data plus an address bit.
13. The asynchronous serial port of claim 8, wherein the character matching and address bit matching is configurable for matching 7 bits of character data plus an address bit.
14. The asynchronous serial port of claim 8, wherein an interrupt is generated upon a character match.
15. A method of address matching in a multidrop asynchronous serial configuration, comprising:
- providing a peripheral on a multidrop asychronous serial line;
- programming the address of a peripheral on the asynchronous serial line into a character match register;
- enabling address bit matching for the character match register; and
- when a frame of data is received that matches the character data and the character match register and the address bit is set, determining that the peripheral is being addressed.
|May 22, 1984
|Hollaar et al.
|August 15, 1989
|Wagner et al.
|November 24, 1992
|Peterson et al.
|May 13, 1997
|Fung et al.
|September 14, 1999
|December 7, 1999
|Lau et al.
|January 25, 2000
|Krick et al.
|March 21, 2000
- Using the Am186.TM.ES and Am188.TM.ES Microcontrollers in Communications Applications, Advanced Micro Devices, Inc., Apr. 2, 1997. AM186.TM.EM and Am188.TM.EM Microcontrollers User's Manual, Advanced Micro Devices Inc., pp. i through viii, 9-1 through 9-13, and 11-1 through 11-8.
Type: Grant
Filed: Jun 1, 1998
Date of Patent: Aug 15, 2000
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Inventor: Melanie D. Typaldos (Buda, TX)
Primary Examiner: Thomas C. Lee
Assistant Examiner: Thuan Du
Law Firm: Akin, Gump, Strauss, Hauer & Feld, LLP
Application Number: 9/88,610
International Classification: G06F 1312; G06F 1320;

subset: commoncrawl


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Two years ago, on December 20, 2007, Nataline Sarkisyan died. She was just 17 years old. Her mother and father grieve the loss of their angel. And every Christmas season from now until they pass from this earth, the Sarkisyan family will embrace Nataline's memory and wonder what might have been.
Nataline needed a liver transplant. Her insurance company wouldn't pay. In spite of protests by friends, family, bloggers and even the nurses of the California Nurses Association/National Nurses Organizing Committee, the insurance company held fast until it was too late for Nataline. The denial of care decision was reversed, but she died without the transplant.
This December 20th, we heard much about the great victory coming in the Senate with the health insurance reform bill touted by the President as historic. Having passed one major hurdle with the vote taken early Monday, the Senate bill will likely pass sometime before Christmas Eve and will then need to be reconciled with the House effort before the President can sign whatever Congress presents him and claim his full measure of political victory. "Seven Presidents have tried and failed," we hear already as the rhetoric advances much more readily than real healthcare reform
But what about Nataline? And all the others?
Make no mistake, given the chance, Republicans would protect no life, no health as a matter of right outside of the womb. It seems the staunch conservatives' love of God and his laws claimed to forbid abortion ends in the birth canal when survival of the fittest and market-based healthcare becomes the right of those financially privileged babies and parents while the poor ought to quake in the shame of their entitlement mentalities.
And the Republicans simultaneously trashed any "government run" healthcare while scaring the bejeebers out of seniors about having some cuts to Medicare benefits. As a man who has only spent four years of his life on this planet without government run healthcare (through the VA and his Congressional position), John McCain should know better. He does know better. They all know better.
This is no criticism of one party or person alone or a left-leaning advocate blaming the left for its failure. This legislation just doesn't protect us from the healthcare denials and financial ruin so many people have suffered in this nation. This legislation is not the protection of a human right.
But what of children like Nataline under this new and already proclaimed as historic Senate health reform effort? Would future Nataline's have a better chance at survival under this reform? In a word: No. In fact, in order to maximize profits and to do an end-run around a few of the insurance restrictions this bill would put in place, the potential will now be much greater that more deaths like that of the young Nataline Sarkisyan will be required for the insurance giants to hold onto their profit margins.
Those who support the bill will argue that insurance companies will no longer be able to use pre-existing conditions to deny coverage. OK. And insurance companies will not be able to rescind policies retroactively, except in cases of fraud and the like. OK. And insurance companies will not be able to impose lifetime caps on benefits, though "reasonable" annual benefit caps will still be allowed (wink, wink). OK.
But where are the protections against denying treatment ordered by physicians like the ones who argued for Nataline's liver transplant? Where are the immediate avenues to appeal that would offer the only way to really save lives like Nataline's when insurance companies practice medicine and deny treatments? There are no such protections in any of the reform plans in Congress or even envisioned by the President.
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Nataline's death would still be a more profitable decision than approving her treatment.
If Nataline had received her liver transplant, would she have lived to go to college? Have her dad give her away in marriage? Have children? Grandkids? To become the fashion designer she longed to be? We cannot answer that without fail.
But what we do know is that her doctors believed the chances were good enough to try. It was her insurance company's bottom line that was the deciding factor – ask Wendell Potter, the former CIGNA spokesman who is now talking from outside the industry, how this played out inside CIGNA, if you wonder even a bit about the process. Market-based insurance means just what it says. It is not patient-based healthcare; it is market-based health industry profit. Nataline's death protected that bottom line.
This weekend I heard that insurance company stocks have reached their most profitable place of the past 52 years since the passage of the Senate's health bill seemed more assured. (See today's Reuters article: http://www.reuters.com/article/idUSN2123786320091221?type=marketsNews) The insurance industry is most pleased today.
So, how does our healthcare future look in this nation under either the Democrats or the Republicans? How many more Nataline's will we tolerate before we demand we truly reform the system to strip the profit motive from the medical-care decision-making process? I do not know. Apparently our capacity to watch our fellow citizens suffer is quite high.
All I know today is that my friends, the Sarkisyan family, are grieving again. Two long years since that horrible day and just an instant since they said goodbye to Nataline, it seems all at once. Such is the grief of a parent. And they are good enough and decent enough people that they would spare every other parent in this nation a similar fate by seeing true healthcare reform place the medical decisions – the life and death choices – in the hands of those medical professionals who have the best motives possible for the outcomes rather than protection of stock prices and CEO salaries and bonuses.
Where is our collective compassion? Can we embrace Nataline's memory and ask our elected officials if what they are proposing for us protects our children in the future? If we don't, we will see more not fewer Nataline-like stories in the holiday seasons to come.
Dickens wrote long ago in his holiday tale, "A Christmas Carol" of Tiny Tim Crachit, the child struggling with illness within a family with hard-working parents who could not provide him enough healthcare for his condition. Though that classic was written long ago with characters eventually rescued by an enlightened Scrooge, we see no such enlightenment forthcoming in this healthcare debate in modern America in 2009. We are not moving more aggressively away from those tales of horror but more surely toward an emboldened policy of healthcare based on privilege and on greed.
As Dickens wrote: "This boy is Ignorance. This girl is Want. Beware them both, and all of their degree, but most of all beware this boy, for on his brow I see that written which is Doom, unless the writing be erased."
Of all we can say of this healthcare reform effort, let's not be ignorant about who wins and who loses, at least. This has not been about the Nataline Sarkisyan's of America. And this holiday season, God help us, every one.


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A lovely motor car... and it fits in the garage!
Looks pretty smart I reckon.
...and it has my favourite number plate!
...in Keast white! (Why pay more for any other colour?)
A happy face.
Easy to learn the layout and the dials and info.
We couldn't afford to get the model with the sat nav, but haven't got lost yet!
Would you believe the rear seats are heated too!!
Smart looking 2 Litre turbo diesel. Quite economical.
We've tested out the rear compartment and can fit large "esky" and 2 bikes! Plus other stuff.
Yep... it can even tow our avan quite comfortably.
We look forward to many many road trips in this IX35.
Thanks Steve, and Country Motor Co. Bomaderry, Sth Coast.


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Learn about Oconto's spectacular waterfowl with David Hafmann, manager of the Oconto Marsh. We'll start with a presentation at the Library at 5:30pm, and then a visit to the Marsh at 6:15pm. A limited number of field glasses will be available. Participants are responsible for their own transportation.
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Kim here with another savory recipe! This recipe is from my Savory Cooking Cookbook by Mary Cech, that I absolutely love. Like I've said before, I want to bake, but I don't necessarily want something sweet. Well, this bread did not disappoint. It's very moist, tender, cheesy, and, although I used whole wheat flour, it really did feel more like white flour, which is what I told my Dad I used when he asked. Whenever I bake with whole wheat, my dad, before eating whatever it is, will ask, "Is this white flour or no?" I'll lie and say it's white flour, then he'll eat it and say it's great.
This is great for brunches, breakfasts, or a side-dish at dinner. Or sliced for a great lunch or a snack anytime. Peckish at midnight? Slice yourself some chili cheese bread for a midnight snack. If you're a hobbit, have a little, or a lot, at elevenses. If you're a trucker, why not pack some on the go to eat during those long stretches of nothingness (in Ohio)? Going on a picnic? This literally screams picnic food! If you just ate another meal, have some bread anyway. And for elves, it's a great alternative to lembas bread. (Why? Don't know, but I challenge you to try it, elves!) It's literally always a good time to eat this. It's so tasty, it's hard not to eat the whole thing. The only time I would not bake this bread is during Thanksgiving, simply because I'd rather eat the sweet potatoes, and I would resent you for putting me in such a dilemma.
A/N: I think when I made this I used 2 cups shredded cheese, when it only calls for one. I remember telling everyone that is has the same amount of cheese as it has flour. Um… oops? Add as much cheese as you want, I'm sure it'll come out great no matter what!
Here's the recipe
2 cups whole wheat flour
2 teaspoons sugar
1 tablespoon baking powder
1 teaspoon black pepper
1 teaspoon salt
1 cup shredded cheddar cheese
1 cup milk
1/3 cup vegetable oil
1 egg
one 4 oz can peeled green chiles, drained
3 tablespoons finely chopped jalapenos
1/2 cup finely chopped red bell pepper
Preheat the oven to 375 degrees Fahrenheit, and butter an 8X3 inch loaf pan. Mix flour, sugar, baking powder, pepper, salt, and cheese together until well combined. In a separate bowl, whisk the milk, oil, egg, green chiles, jalepenos, and red pepper in another bowl. Pour the wet ingredients over the dry ingredients. Pour the moist batter in the prepared loaf pan and place in oven for about 45 minutes, or until the top is golden brown and springs back when gently pressed.
Technically, you're supposed to let it cool – but who does this?


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Downings win a second Junior B title with victory over Letterkenny Gaels
Donegal Junior B final
Downings captain James McBride being presented with the Junior B Championship cup in O'Donnell Park on Sunday by county chairman Sean Dunnion. Photo Thomas Gallagher INDD101016 TG5
Downings are celebrating Junior B championship success following their five point win over Letterkenny Gaels Sunday's final in O'Donnell Park.
Downings 2-8
Letterkenny Gaels 0-9
James McBride and Martin McBride scored the goals, one in each half, for a Downings wide who were the better team over the 60 plus minutes.
Joe Friel polished off a good move with Letterkenny Gaels' first and the game's opening score on seven minutes.
But Downings, after early Letterkenny Gaels pressure, settled and the sides were level in the 16th minute when Maxi Curran kicked a well struck point after turning his marker and knocking over from 30 metres.
Curran was in the thick of the action again three minutes later when he was fouled and Chris Carr converted from 20 metres for the lead point.
With Chris Carr and John Doherty getting a grip in the middle of the field and Maxi Curran and Shane McClafferty in fine form up front the scores flowed for Downings.
And by the time Marc Browne blew for half-time they had opened up a sizable six point lead.
Carr with another close in free, Shane McClafferty - after Carr rattled the crossbar - and Curran with his second kicked the points for Francie McHugh's men.
And James McBride added the icing to the half when he first timed to the net for a 1-5 to 0-2 lead after Maxi had once again done all the spade work. Aidan Hanley scored Letterkenny Gaels' second point late in the half as Downings went in 1-5 to 0-2 in front at half-time.
Downings moved seven clear early in second half thanks to a super point on the run from wing back Brian Boyce.
That was on 34 minute,s but the champions did not score again for the best part of a quarter hour as Letterkenny Gaels clawed their way back into the game.
Thanks to two Charlie McCreevy pointed frees and one from each Niall McManus and Alan Harrington, the Gaels cut the margin to three points, 1-6 to 0-6 by the end of the third quarter.
Niall McManus missed a glorious opportunity to reduce the gap to two from a close in free from a tight angle.
But the chance was missed and Downings pulled away again with a glorious three minute spell as they reeled off 1-2 without reply to open up an eight point lead.
Substitute Martin McBride accounted for 1-1 with the goal coming at the end of a sweeping move involving Shane McClafferty and Martin Cullen.
Midfielder John Doherty kicked the other point for a 2-8 to 0-6 lead with a little over ten minutes remaining.
The champions did not score again as Letterkenny Gaels put on a late push with points from Gerard Gibbons, Joe Friel and Declan McFadden.
DOWNINGS: Brendan McGee; Ciaran McTeague, Marty McLaughlin, Conor Shiels; Gerard McGee, Hugo Davis, Brian Boyce (0-1); Chris Carr (0-2, 2f), John Doherty (0-1); Barry McBride, Maxi Curran (0-2), Martin Cullen; Luke McBride, Shane McClafferty (0-1), James McBride (1-0). Subs: Eric Roberts for B.McBride 38, Martin McBride (1-1) for L.McBride 38, Naoise Cullen for McGee 42, Paul Coyle for Curran 54, Seamus McLaughlin for Doherty 59, Patrick McGeever for Cullen 60.
LETTERKENNY GAELS; Stephen Doherty; Aaron Diver, Bobby Carey, Anthony McDaid; Aaron Stewart, Tommy Daly, Eoin Kelly; Shane Gildea, Declan McFadden (0-1); James McGlynn, Oisin Cannon, Charlie Creevy (0-2, 2f); Joe Friel (0-2), Alan Harrington (0-2, 2f), Aidan Hanley. Subs: Noel Gildea for Daly 30, Niall McManus (0-1) for A Hanley, h/t, Ger Gibbons (0-1) for S.Gildea 46, Paul McKenna for Harrington 54.
REFERRE: Marc Brown (Four Masters).


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Trump's Nominee and the Court
We want our Supreme Court justices to be above reproach. We know that humans are flawed in many ways, but a person who sits in judgement of the most important decisions in the land needs to be honorable and fair.
For those of us who are old enough to remember Anita Hill and her agonizing testimony before an all-male panel of Senators, we know the result of that hearing gave us Clarence Thomas. In my opinion, Justice Thomas is a biased judge. But this isn't just my opinion, the Smithsonian's National Museum of African American History and Culture left him out of their displays and mentioned Anita Hill's bravery instead.
There are many in the black community who believe that some of the decisions and votes from Clarence Thomas actually turned back the clock for African-Americans in this country. Judge Thomas' wife, Virginia Thomas, is a well-known conservative and attorney who founded Liberty Consulting and the advocacy (lobbying) group Liberty Central. She is also a columnist for The Daily Caller and has previously worked at The Heritage Foundation. If you remember, Trump got his list of potential judges for the Supreme Court from this foundation. Virginia Thomas has more influence here than even the president.
Now we have a woman who has come forward to accuse Donald Trump's nominee for the Supreme Court of sexual assault when he was a teenager. Just as we had with Justice Thomas, one woman could stand between him and his lifetime appointment to the court. Will this simply be another Anita Hill moment with nothing really changing, or will the #MeToo movement finally be able to block a nomination to the highest court?
One of the things the protectors of the president are asking is, "Why did this woman wait so long to bring this up?" They wonder out loud, "Why now?" It's rather bewildering that those same people will watch TV shows about cold cases that are reopened and solved without asking that same question. Sure, technology, DNA and time have a way of bringing the truth to the surface in those shows, why not follow that same kind of logic in this real-life, critical discussion?
Brett Kavanaugh is probably not a serial rapist, but just writing those words could generate a key word connection on the internet. If reposted by enough people, the connection between the nominee's name and that label could become a search result on Google. The jury is not only public opinion, but also the fuel for the mathematical algorithms working their magic on the search terms people use. We saw what the internet did to Rick Santorum. He is forever linked with "anal sex" when people search his last name.
I watched hours and hours of the Senate confirmation hearings and, objectively speaking, I found Kavanaugh to be quite knowledgeable about case law and the tradition of precedent. At the same time, I felt that he was much too political to be on the Supreme Court. He seemed to be pitching for the job, like a greasy whore politician. It's what he couldn't remember that bothered me most. And who spends $60,000 on baseball tickets?
In the past, we've put some far-right lunatics on the court. People of today's generation may not remember the name Lewis F. Powell Jr., but this associate justice was appointed to the Supreme Court by Richard Nixon. He did more to help large corporations and rich people than any other justice. We wouldn't have the Citizen's United decision or the Hobby Lobby debacle without the road being paved by Justice Powell. If we could remove a few layers of decisions in the court, we would know the big print may giveth but the fine print taketh liberty away.
It's likely going to be another wild week in Washington. Once again, Trump has created more fodder for the news networks with no greatness. He's taken the memory of almost 3,000 dead souls in Puerto Rico and thrown them into the trash. He's a womanizer and abuser of women's rights and knows his base doesn't care. The Great Orange Leader is only playing a character President. He's not a real statesman.
Will the members of the Senate judiciary committee ignore the testimony of one woman from California? There are probably more secrets and lies in the thousands of memos that Brett Kavanaugh wrote while working for George W. Bush. That's the reason Republicans don't want people to see them. Hopefully this one woman will make them realize that they should look at everything this man has said and done in the past. Why the rush?
The good news is that anything which makes Donald Trump look bad will be dismissed. It might take the Donald a little longer to figure this one out, but in the end, he will pluck another name from that long list of conservative judges provided by the Heritage Foundation. Like a novice at the track picking a horse, Trump will point to a name he likes and lay down another bet.
A person who could breeze right through the Senate would be Merrick Garland. He's a good judge and an objective thinker but, unfortunately, he's not on the sacred list. There is a reason that the people don't get to vote on Supreme Court justices, I mean look what happened when they decided who should be president.
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BOOK ONE (IF GOD COULD TALK) A Cable TV talk show host is approached by a friend who offers a guest for his show who has never been on TV before. The Diary of a TV Journalist is the story about the host of the show and his executive producer vetting the guest and attempting to determine what would happnen If God Could Talk…
BOOK TWO (IF GOD COULD CRY) One of the most eye-opening stories about terrorism. The famous cable TV talk show host, Jonas Bronck, leaves New York on a quest for truth. He finds himself in the middle of terror and personal torment in the name of journalism. He once again asks, If God Could Cry, would he be crying for us, or with us?
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text: The singularly uninspired account of how agnostic sportswriter Bryan (Dogleg Madness, 1988) entered a fundamentalist seminary, studied and argued over the Bible, joined a missionary expedition to El Salvador--and found his life unchanged. Bryan spent the spring term of 1989 in residence at Criswell College in Dallas, a stronghold of Southern Baptist conservatism. His stated purpose was investigative rather than theological: He was interested in fundamentalism, intended to write a book on the subject, and wanted to know more about it. The reality turned out to be more complex than he had imagined. His classmates were quite likable, by and large, and his teachers (despite the precision of their creed) were remarkably open. Their obvious, almost single- minded dedication to biblical Christianity fascinated Bryan, who had abandoned Methodism in his youth and seems never to have found an adequate substitute. Throughout, he compares them with ``liberal Christians'' (who, he says, try to accommodate their faith within the framework of modern philosophy) and credits them with more consistency and passion. More than once, Bryan claims, he was tempted to present himself for baptism, and in a Catholic church in El Salvador he began to understand the reality conveyed by the ideas of ``sin'' and ``redemption.'' His story remains essentially voyeuristic throughout, however, because at no point does he seem willing to meet his classmates on their own terms. His skepticism is never relinquished long enough to make his encounter with theism seem like more than a diversion, and this undermines the significance of the whole undertaking. A disappointing tale, which tries without much success to provide new insights on an unfamiliar world.