text: ® ® TOPSwitch-GX Forward Design Methodology Application Note AN-30 Scope This application note is for engineers designing an AC-DC power supply using TOPSwitch-GX in a single-ended forward converter. It addresses single input voltage 230 VAC or doubled 115 VAC input, but does not address universal input (85 V to 265 V) designs. The document highlights design parameters that are fundamental to the use of TOPSwitch-GX in a singleended forward converter. It offers a procedure to compute transformer turns, output inductance and other design parameters. This procedure enables designers to build an operational prototype in the shortest possible time. Refinement of the prototype hardware after bench evaluation will lead to a final design. Introduction The single-ended forward converter topology is often the best solution for AC-DC applications that require higher powers and higher output currents than are practical from flyback converters. The forward converter extends the power capability of TOPSwitch-GX to greater than 200 W for high current outputs. The feature set of TOPSwitch-GX offers the following advantages in single-ended forward designs: • • • • • • • • • • Built-in soft-start Built-in under-voltage lockout Built-in adjustable current limit Programmable duty cycle reduction to limit duty cycle excursion at high line and transient load conditions Higher efficiency (typically >70%) Very good light-load efficiency Voltage mode control for simpler loop designs with magnetic amplifier post-regulators Built-in remote on-off Low component count Improved EMI The design methodology presented here is sufficiently general to cover a variety of single-ended forward designs, including power supplies for personal computers. It provides for multiple outputs with coupled inductors, independent multiple outputs, and outputs with both linear or magnetic amplifier post regulators. Snubber Output Inductor + 2CIN Non-Doubled AC INPUT Doubled Primary Clamp Circuit RA Output Capacitor Clamp Diode VO – + VDB – + VDB – + VZ – RB Under-Voltage Lockout Sense RC D L CONTROL 2CIN + Bias Voltage – CVS RD TOPSwitch-GX C U1 S TL431 with Frequency Compensation FEEDBACK CIRCUIT F PI-2817-121201 Figure 1. Typical Configuration of TOPSwitch-GX in a Single-Ended Forward Converter. December 2002 AN-30 IAUX VAUX NAUX LMAIN NP IMAIN VAUXREF Optional LC Post Filter Choose Connection DC Stacked or Conventional NMAIN + VMAIN – Output Return MAG AMP MAG AMP Control IMAINMA NB Optional LC Post Filter LMAINMA VMAINMA IIND + LIND VIND NIND – ILOAD + Input Voltage from VAUX, VMAIN, VMAINMA or VIND Linear Post Regulator – ILOAD + Any Output Voltage Less Than Input Voltage – PI-2818-121201 Figure 2. General Output Options for the Forward Converter Described in the Methodology. This document does not address the design of magnetic amplifiers nor linear regulators. It determines design parameters for the transformer and the inductors, but does not give construction details for those magnetic components. Such details are deferred to other application notes and component suppliers. References [1] through [6] are good sources of information for the design of transformers and inductors. Software for design of magnetic amplifiers is available from [5]. Reference [1] is also an excellent resource for other important topics in power electronics. Design Methodology Overview The methodology assumes the reader knows the theory of operation of the forward converter and the fundamentals of power supply design. It is a companion to the PI Expert software for forward converter design (available from the Power Integrations Web site). Designers are advised to check Power Integrations' Web site at www.powerint.com for the latest application information. This presentation uses a typical combination of output options for illustration of the methodology (see Figure 2). This document 2 B 12/02 AN-30 gives the basic expressions illustrating the methodology. The PI Expert software uses more complex versions of these expressions containing additional parameters to account for non-ideal effects. Thus, results from the software may not exactly match the computations from expressions in this document. circuit that is common in voltage mode systems with a two-pole response. The frequency compensation will in general require two zeros and two poles to obtain the phase margin desired for most applications. While the design of the feedback circuit is a separate topic beyond the scope of this application note, the general topology of the circuit is discussed. This document assumes a non-doubled input configuration. PI Expert includes modified expressions for both doubler and non-doubler input configurations. To simplify the expressions, all outputs are assumed to operate in continuous conduction mode, consistent with the worst case design at maximum load. At lower load conditions it is possible for individual outputs to operate in discontinuous conduction mode. Output Options Salient features of the output circuits are illustrated in Figure 2. Multiple secondary windings of the transformer may be configured in many different ways to give several options for regulated and unregulated output voltages. The methodology begins with an explanation of the general converter topology. It then presents the design flow, showing the major tasks in a high level flowchart. After a review of the nomenclature and definitions of variables, it discusses the details of the design procedure. Rationale, assumptions and expressions are given to help the designer enter parameters and interpret results. A complete list of variables used in the expressions follows in Appendix A. Appendix B offers a procedure for hardware verification. A worked example is presented in Appendix C. General Converter Topology Figure 1 shows a typical single-ended forward converter using TOPSwitch-GX. Detail is focused on the primary side of the transformer because the circuits on the secondary are conventional and covered in other literature. Resistors RA and RB set the under-voltage lockout threshold. Resistor network RA, RB , RC, and RD with capacitor CVS adjusts the maximum duty ratio as a function of the input voltage. This methodology gives the procedure to determine proper values for the resistors and the capacitor. Another key element in the use of TOPSwitch-GX is the primary clamp (CCP, D1, VR1, VR2 and VR3 in Figure 10) which resets the transformer flux and limits the maximum drain voltage. This methodology assumes use of this Zener-capacitor clamp circuit. Guidance for selection of components for this particular clamp is included in this application note. All applications will have only one main output. This is the voltage that is regulated directly by TOPSwitch-GX through the optically isolated feedback circuit. In general, any number of auxiliary outputs may be derived from other secondary windings and regulated indirectly by means of a coupled inductor that they share with the main output. The secondary windings for the auxiliary outputs may be configured in two different ways. The conventional configuration connects one side of the auxiliary winding to the main output return. This connection is used when the auxiliary output is the opposite polarity of the main output. An alternative configuration, sometimes known as the DC stacked connection, has one side of the auxiliary winding referenced to the main output instead of the output return. It has the advantage of better regulation of the auxiliary output voltage than the non-stacked arrangement, but is limited to outputs that are greater in magnitude and of the same polarity as the main output voltage. Any number of unregulated output voltages may be derived from circuits that do not share an inductor with any other outputs. They are related to the main output only through separate secondary windings on the transformer. Their inductors are independent of the others. These outputs typically are referenced to the output return, but alternatively they may be referenced to any potential that the isolation of the transformer will tolerate. Multiple tightly regulated voltages may be obtained with either linear or switching post regulators. These external regulators may be added to any output, including the main output. They are simply additional loads on those output voltages. The topic of clamp circuits is deferred to a separate application note. Designers may choose to use their own clamp circuits with the restriction that resonant clamps, (for example, LCD clamps–inductor/capacitor/diode) and reset windings are not recommended. The internal current sense of TOPSwitch-GX does not allow the high reset current of a resonant clamp to be excluded from the sensed drain current. A particularly useful type of switching post regulator is the magnetic amplifier, which uses a saturating magnetic element as an independently controlled switching device. While a magnetic amplifier can in theory be operated from any output, this methodology restricts the connection to the main output only. This methodology uses an ordinary optically isolated feedback Since it is not possible to treat every combination of output B 12/02 3 AN-30 options in this presentation, the methodology will be restricted to those that are typical for power supplies in personal computers. Therefore, this methodology allows the following options: Start • One main output • A maximum of one auxiliary output that may be DC stacked to the main output or referenced to output return • A maximum of one independent output • A maximum of one magnetic amplifier post regulator that operates from the secondary winding for the main output • Any number of linear post regulators that may operate from any output Get system requirements Select output topology Choose design parameters Estimate peak primary current Select TOPSwitch-GX from current and power guidelines Design Flow Are parameters within TOPSwitch-GX boundaries? No Figure 3 is an abbreviated flowchart of the major tasks in the design methodology. The important decision blocks involve the selection of the proper TOPSwitch-GX device for the application, and the designer's satisfaction with the overall design. Yes Design transformer Compute operational parameters All designs begin with the definition of requirements. The next section discusses the parameters a designer needs to know before the design can start. TOPSwitch-GX selection OK? No Yes Determine component stress Compute output inductance Design satisfactory? No Yes Determine control and clamp components Evaluate prototype on bench Check Assumptions No Adjust Design parameters Performance satisfactory? Yes Design complete PI-2819-121301 Figure 3. Flowchart Showing Major Tasks in the Design of Forward Converters with TOPSwitch-GX. 4 B 12/02 Parameters for the forward converter are dominated by the output specifications. The designer will have to choose a topology that is appropriate for the application. An application that calls for only one output is simplest, while a requirement for several outputs with complex loading needs careful consideration. It may be necessary to go through several designs to select the most satisfactory configuration. Knowledge of system requirements and selection of the output topology allow the designer to compute the magnetic parameters. These are turns ratios for the transformer and the coupled inductor (if the design has an auxiliary output), plus values of inductance for independent outputs and the output inductor for the magnetic amplifier (also called mag amp). The output inductor for the mag amp is different from the inductive switching element (sometimes called a saturable reactor, saturable core, or saturable choke), that is not addressed in this note. The peak primary current can be computed from the turns ratios established for the transformer along with the ripple current in the output inductors. This allows selection of the appropriate TOPSwitch-GX. It must have sufficient current limit to handle the maximum steady-state load and must have enough additional margin to accommodate peak loads and transients. Another consideration in the selection of the TOPSwitch-GX is power dissipation in the device. A device that can handle the steady-state and peak primary currents does not guarantee ability to meet thermal limitations – this is an independent consideration. AN-30 The efficiency of the power system is an important consideration in every design. The designer should have a goal for the efficiency of the system at the start of the design, based on reasonable allowances for power lost in the specific areas of the power supply. The efficiency goal should take into account losses in the transformer, inductors, output rectifiers, and clamp circuits. Most high power designs have some form of power factor correction (PFC). The type of PFC will affect the efficiency. For example, the voltage drop on a passive PFC (a large inductor in series with the AC line input) will reduce the minimum input voltage at the converter, and will also reduce system efficiency. Total system efficiency should consider losses in the AC input circuit, including the EMI filter, that are not part of this design methodology. Only a bench evaluation can determine the actual efficiency of the power supply. If the efficiency is not satisfactory, the designer must revise the values of component parameters or change the output topology for a repeat design. If the requirements call for a holdup time, the designer must determine the amount of bulk input capacitance that is required to achieve the specified holdup time from the designated input voltage. It is often necessary to adjust parameters by iteration to meet the objectives of the design. PI Expert performs the calculations to allow the designer to see the interactions of the variables immediately. After the values of the major power components are determined, the designer needs to check voltage and current stress to select components with the proper ratings. Then the designer can choose values for small signal components that set voltage detection thresholds and other control parameters. The final step is an evaluation of a prototype on the bench. This is the only way to confirm that the design is satisfactory, and to get necessary information to adjust the parameters if a redesign is necessary. Definition of Variables Table 1 gives a set of system parameters that should be known at the start of the design. The list is general, so all the parameters will not necessarily be relevant to all applications. Some values will be given by the system specification, while others are the designer's choice. The notation in this document uses descriptive subscripts to keep track of variables. Quantities that refer to the main output are designated with the subscript MAIN. Variables associated with an auxiliary output are identified by the subscript AUX, and those related to an independent output have the subscript IND. Name Description η fL Total system efficiency AC mains frequency fS IAUX IIND IMAIN TOPSwitch-GX switching frequency Current from auxiliary output Current from independent output Current from main output IMAINMA Current from magnetic amplifier tH VACMAX Holdup time Maximum AC input voltage VACMIN Minimum AC input voltage VACNOM Nominal AC input voltage VACUV VAUX AC under-voltage threshold VAUXREF Auxiliary output voltage Auxiliary output reference voltage VDROPOUT Lowest DC bus voltage for regulation VDSOP VHOLDUP Maximum drain-to-source voltage DC bus voltage at start of tH VIND VMAIN VMAINMA Independent output voltage Main output voltage Magnetic amplifier output voltage Table 1. System Parameters Needed to Start a Design. These conventions are used to identify voltages, currents, and components. When there is more than one output in a category, the individual members are distinguished by numbers appended to the subscript, as in IND1, IND2 and IND3 for three independent outputs. Quantities related to the magnetic amplifier have MA appended to the subscript, as in MAINMA referring to the magnetic amplifier on the secondary winding for the main output. This notation has the generality necessary to expand the allowable output options. Turns ratios on magnetic components are designated by lower case n with appropriate subscripts, while actual numbers of turns are distinguished by upper case N with identifying subscripts. There are a few other variables and notations that need definition. Figure 4 shows a section of output circuitry that identifies some important electrical quantities. Each output of a forward converter has two diodes. One is designated the forward diode and the other is the catch diode. Associated quantities have or C appended to their respective subscripts. F B 12/02 5 AN-30 The peak DC bus voltage (non-doubled) is VDMAINF + – RLMAIN VMAX = VACMAX 2 LMAIN + Forward Diode NP RP RSMAIN NMAIN – VDMAINC + (1) while the DC bus voltage at the valley of the ripple at the minimum steady state AC input is VMAIN Catch Diode 2 VMIN = 2VACMIN – PI-2820-121301 Figure 4. Output Circuit with Parameter Definitions. Voltage drops on diodes have subscripts with the prefix D for the conduction drop and PIV for the reverse blocking voltage. The only exception to this convention is for drain-to-source voltages, which will be obvious from context. Figure 4 also shows series resistances that the designer can include to get better predictions of performance. 1 − tC 2 PO 2 fL − ηDC CIN (2) where PO is the total output power, tC is the conduction time of the bridge rectifier, ηDC is the efficiency exclusive of losses in the AC input circuit, and CIN is the capacitance at the input to the converter. Use 3 ms for tC and use the total system efficiency η for ηDC if no better estimates are available. A good initial value for CIN is 1 µF per watt multiplied by PO. The designer should carefully choose the value of tC when using passive PFC input (a large inductor in the AC line), since this approach significantly increases the diode conduction time. Also, the voltage waveform will deviate from a sinusoid, causing some error in the prediction of Equations (1) and (2). Detailed Design Procedure This methodology guides the designer through a procedure that determines parameters for prototype hardware. After bench evaluation, the designer refines the parameters to meet all requirements. Remember to use the input voltage to linear regulators, not the regulated output voltage, to compute the total output power. The dissipation in the linear regulator is part of the load on the converter. The nominal DC bus voltage is defined to be The design can start with knowledge of only the most basic system requirements. For example, the forward voltage drops on diodes and the resistances of transformer windings are seldom known very accurately at the beginning of a new design. Results of the design with default values will guide the designer to select particular components with known parameters. Figure 5 gives an expanded flowchart that includes the detailed steps which follow. Step 1. Establish system requirements. Determine the parameters in Table 1. These should be available from a system specification of the power supply's application. The software will compute and display the maximum and minimum DC bus voltages to the converter from the AC inputs. The need to know maximum and minimum voltages is obvious. The optional nominal input voltage VACNOM helps determine the turns ratios of the transformer. The goal is to set the unregulated output voltages at their nominal values when the input is at its nominal value. The designer may choose any value between VACMAX and VACMIN to be the nominal value. 6 B 12/02 VNOM 1 PO − tC 2 fL 2 2 = V + V − ACNOM ACNOM 2 ηDC CIN (3) This is simply the midpoint between the peak and valley of the ripple voltage on the input capacitor (non-doubled). Step 2. Set ripple current in the output inductors. Choose the ripple current factor K∆I. Figure 6 shows how it is related to the average output current. K∆I is a useful parameter for design because it directly influences the size of the output inductor. It also affects the peak primary current and the RMS current in the output capacitors. AN-30 1. Establish system requirements (specifications & output topology) Review requirements Check assumptions Adjust design parameters 2. Set inductor current ripple 3. Calculate transformer turns ratios 4. Estimate primary current No 5. Choose TOPSwitch-GX 14. Inductor size satisfactory? Operation within TOPSwitch-GX guidelines? Yes No Yes 15. Calculate component values for external DCMAX reduction 6. Design transformer 16. Calculate resistor values for optional external UVLO circuit 7. Check peak primary current No 17. Choose components for clamp circuit Operation within TOPSwitch-GX guidelines? 18. Choose components for feedback circuit Yes 8. Determine input capacitance 9. Calculate stress on rectifiers Construct hardware prototype Evaluate thoroughly on bench Determine limits of operation 10. Calculate RMS ripple current in output capacitors Is performance satisfactory? No Yes 11. Calculate parameters for coupled inductor Design complete 12. Calculate inductance for independent outputs 13. Calculate output inductance for magnetic amplifier PI-2831-020502 Figure 5. Expanded Flow Chart Showing Detailed Steps in Forward Design Methodology. B 12/02 7 AN-30 I K∆I = ∆I IO IO ∆I DTS (1-D) TS t TS = 1 fS PI-2821-121401 Figure 6. Inductor Current Showing Definition of K∆I. The ripple current in the inductor depends on the converter's operating point. In general, K∆I will change with the duty ratio according to the relationship K∆I = K∆I 0 (1 − D) (4) where K∆I0 is the limit as the duty ratio approaches zero. The expression that relates K∆I0 to the inductance L for a given generic output is K ∆I 0 = VOUTPUT + VD( OUTPUT )C (5) LIOUTPUT fS across multiple outputs at minimum load is obtained when I K∆I ≤ 2 MINIMUM I MAXIMUM (6) where IMINIMUM and IMAXIMUM are the respective minimum and maximum average output currents. The common K∆I at full load allows calculation of the inductance. The designer has the option to change any value of any inductor to suit particular requirements. The change in inductance will change the K∆I for that particular inductor. where VD(OUTPUT)C is the voltage on the catch diode when it is conducting. For coupled inductors, K∆I indicates the ripple component of the total ampere turns, not ripple current on any individual winding. K∆I will be between 0.15 and 0.3 for most practical designs. The K∆I corresponding to the highest input voltage is used for calculations. All dependent quantities should then be computed for the designer's inspection. Since the duty ratio at the highest input voltage will usually be very small, K∆I0 is usually a very good approximation to the worst case K∆I. Step 3. Calculate turns ratios for the transformer. Turns ratios on the transformer are computed with respect to the main output winding. The primary-to-main turns ratio is fixed by the input and output voltages and the maximum duty ratio, which is limited by the maximum drain-to-source voltage that is set by the designer. The maximum duty ratio to guarantee reset of the transformer is If any outputs have nonzero minimum load, use the minimum load as a guide for the upper limit on K∆I. The best regulation 8 B 12/02 DMAX _ RESET ≤ 1 − VDROPOUT ≤ 0.74 VDSOP (7) AN-30 where VDROPOUT is the DC bus voltage at the end of the holdup time and VDSOP is the maximum drain-to-source voltage on the TOPSwitch-GX during operation. The minimum recommended value for VDROPOUT is 130 V, while VDSOP is usually less than the breakdown voltage of 700 V by a comfortable safety margin. A safety margin of 15% is typical, giving 600 V for VDSOP. The maximum duty ratio for the converter occurs at VDROPOUT. This must be reduced as a function of line voltage from the DCMAX of TOPSwitch-GX by external circuitry in Step 15. The recommended maximum duty ratio DMAX for the forward converter application depends on the operating input voltage range. For a 3:1 operating range (VMAX:VDROPOUT) 70% is typical. As the operating range reduces so does the value of DMAX. For a 2:1 operating range a value of 50% would be selected. First, compute the turns ratios for the primary and the auxiliary winding. The turns ratio on the primary of the transformer is nP = (VMAIN VDROPOUT − VDS 1 − DMAX + VDMAINC ) + VMAIN + VDMAINF DMAX (8a) Where VDS is the average drain-to-source voltage during the on-time of TOPSwitch-GX: When VDMAINF and VDMAINC are the same value VDMAIN, this equation simplifies to: − VDS ) DMAX (V nP = DROPOUT VMAIN + VDMAIN VAUX + VDAUXC − VAUXREF VMAIN + VDMAINC LMAINLK I MAINSEC DMAX fS VMAIN DNOM = VMAIN + VDMAINC (11) VNOM − VDMAINF + VDMAINC nP This allows a better estimate of the turns ratio that will produce the desired independent output voltage. nIND = VIND + VDINDF DNOM + VDINDC (1 − DNOM ) VMAIN + VDMAINF DNOM + VDMAINC (1 − DNOM ) (12) Finally, compute the turns ratio for the bias winding so that the bias voltage is greater than eight volts. This value is the CONTROL pin voltage, 5.8 V, plus the 2.2 V saturation voltage of the optocoupler's phototransistor at VDROPOUT. The turns ratio for the bias winding is then (13) (8b) (9) Equation (8) is valid for systems where the leakage inductance of the transformer is negligible. This is a reasonable assumption because the leakage inductance must be minimized for low power dissipation and proper operation of the clamp circuit. Leakage inductance reduces the effective duty ratio on the secondary circuits by delaying the turn-off of the catch diodes. The effect can be significant in designs with very high output currents. To compute the turns ratio for the primary winding when leakage inductance is a consideration, subtract the constant δD = Next, compute the duty ratio DNOM that corresponds to the nominal input voltage. 8 volts + VDB n B ≥ nP VDROPOUT The turns ratio for the auxiliary winding is nAUX = from DMAX in Equation (8). In Equation (10), LMAINLK is the leakage inductance of the secondary winding of the main output, IMAINSEC is the winding current required to turn off the catch diode of the main output, and fS is the switching frequency. Note that in the DC stacked connection for the auxiliary output, the winding for the main output carries the current of the main output plus the current of the stacked auxiliary outputs. (10) where VDROPOUT is the minimum DC bus voltage for regulation and VDB is the voltage drop on the rectifier for the bias voltage. Check that the breakdown voltage on the phototransistor of the optocoupler is higher than the bias voltage at the highest transient input voltage. Step 4. Calculate the primary current. Find the peak and RMS values for the primary current. This is a preliminary estimate from the system parameters. It allows the designer to assess the suitability of his application for TOPSwitch-GX as early as possible. Figure 7 shows typical primary current waveforms for forward converters with and without a magnetic amplifier post regulator. Figure 7(a) is without a magnetic amplifier, whereas Figure 7(b) shows the effect of one magnetic amplifier post regulator. TOPSwitch-GX determines the duty ratio D to regulate the main output, whereas the post regulator sets DMA independently by its own local feedback to regulate the output voltage from the magnetic amplifier. B 12/02 9 AN-30 IP IP IPP DMA TS IPP DTS DTS (1-D) TS t 0 (1-D)TS t 0 TS = 1 fS TS = 1 fS (a) (b) PI-2822-121401 Figure 7. Typical Primary Current Waveforms for a Converter Without Magnetic Amplifier (a) and with a Mag Amp (b). The computation is simply the reflection of peak currents in the secondary circuits by the ideal turns ratios of the transformer. Using the principle that the sum of the ampere turns for an ideal transformer is zero, the instantaneous primary current for a transformer with W secondary windings is just IP = 1 W ∑ ij n j nP j = 1 (14) where ij is the current in the secondary winding with turns ratio nj. Thus, for a transformer with three secondary windings, the primary current would be the sum i 1n 1+i 2 n 2+i 3 n 3 divided by the turns ratio of the primary. Note that since all turns ratios are defined with respect to the main output winding, the turns ratio of the main output winding is 1. Equation (14) may also be used with the actual number of primary turns NP substituted for the turns ratio nP, and the actual secondary turns Nj substituted for the turns ratios nj. This estimate does not include the effect of magnetizing current in the transformer, which will be determined after the transformer is designed. The magnetization current will raise the peak value of this estimate by typically less than 10% worst case. The computation in PI Expert includes the ripple current in the output inductors to find the peak primary current. Ripple current is ignored to calculate the RMS value. The resulting error in the RMS current is less than 1% for practical values of 10 B 12/02 inductance and current. The RMS current is computed at the duty ratio that corresponds to VACMIN because worst case steadystate resistive losses occur at that operating point. Step 5. Choose the appropriate TOPSwitch-GX device. Select a TOPSwitch-GX according to the requirements for peak primary current and acceptable power dissipation. For operation of the converter in continuous conduction mode it is recommended to operate the device at no more than 80% of its current limit for ordinary thermal design. To reduce device dissipation it is possible to use a TOPSwitch-GX device that has a lower RDS(ON) when the current limit is adjusted accordingly. Lowering ILIMIT externally (using a programming resistor to the X pin), takes advantage of the lower RDS(ON) of the larger device while maintaining the same level of overload protection. The external current limit reduction factor is KI = External Current Limit Data Sheet Current Limit (15) where 0.4 ≤ KI ≤ 1.0, and is set by the value of a resistor connected between the X pin and SOURCE pin. Refer to the TOPSwitch-GX data sheet for details. With external current limit reduction, the actual (external) current limit is I XLIMIT = I LIMIT K I (16) AN-30 Remember to check the maximum and minimum tolerance on ILIMIT from the data sheet for the selected device. Allow margin to guarantee that the peak primary current IPP is less than the minimum value of IXLIMIT at high temperature. With minimum device ILIMIT, check that IPP ≤ 0.96 I LIMIT for K I = 1 (17) IPP ≤ 0.86 I XLIMIT for K I < 1 Adjust the system specifications if the peak current is too high for the largest device. While some specifications are fixed, others are adjustable at the discretion of the designer. Raising the minimum input voltage will give lower peak current. Step 6. Design the transformer. The transformer design can be either completed in-house or delegated to a qualified supplier of custom magnetics. An outside supplier needs to know the turns ratios and the recommended restrictions on flux density to start a design. Even if the ultimate design will be done outside, it is beneficial to do a rough design in-house. A proposed design with actual numbers of turns on each winding will reduce the time required to obtain a satisfactory transformer. Compute the turns for the other power windings. N P = nP N MAIN N AUX = nAUX N MAIN (21) N IND = nIND N MAIN Round NP downward to the next integer. Round NAUX and NIND to the nearest integer. Compute the turns for the bias winding. 8 volts + VDB NB = NP VDROPOUT (22) Round NB upward to the nearest integer value. Designers should use copper foil instead of wire for windings of few turns that carry high current. It is very important to the success of the design to minimize leakage inductance. Compute an estimate of the peak magnetizing current. The maximum recommended flux density for this application is The primary inductance in henries is BPEAK ≤ 0.3 tesla (3000 gauss) (18) and the recommended maximum change in flux density per switching period (AC flux density) is BM ≤ 0.2 tesla (2000 gauss) (19) The constraint on BM sets the minimum number of turns for a particular core, while the limit on BPEAK restricts the maximum transient duty ratio. Although peak flux density under steadystate conditions can be calculated, the designer should allow sufficient margin to avoid saturation under transient conditions. To start the design, select a core that is likely to meet the size and efficiency requirements of the application. Since the voltages and turns ratios are determined, all that remains is to find the actual number of turns and the size of wire for each winding. 2 µ AN LP = 0 e P le + lg µr (23) where µ0 is the permeability of free space, Ae is the effective area, le is the effective path length in the core and lg is the length of the air gap (see Zero Gap Transformer section). The dimensionless relative permeability µr is given by µr = AL le 400πAe (24) Units in the above two expressions are the SI basic units with the exception of inductance coefficient AL, which has the conventional units of nH/turn2. With no gap, the primary inductance in henries is simply Compute the minimum turns for the main output. N MAIN V + VDMAINF ≥ MAIN BM Ae fs 2 LPNO GAP = AL N P × 10 (20) where Ae is the effective area of the core. Units in the above expression are volts, tesla, meter2 and hertz. Round NMAIN upward to the next integer value. −9 (25) Now the peak magnetizing current is given by I MP = VMIN DMAX LP fS (26) Units in the above expression are amperes, volts, henries and hertz. The magnetizing current should be less than 10% of the primary current for reasonable power dissipation in the clamp circuit. B 12/02 11 AN-30 Estimate the power lost in the core from the manufacturer's data on the core material, operating frequency and BM. Copper losses may be estimated from the resistance and RMS current in each winding. If the estimates indicate excessive loss, repeat the design with a larger core. Zero Gap Transformers For highest efficiency in this application with the simple Zener clamp circuit, it is recommended that the transformer core have no air gap. While an air gap reduces the remnant flux density and stabilizes the primary inductance, it increases the stored energy that must be processed by the clamp circuit. With the use of a suitable reset scheme, transformer saturation is not a problem in the absence of an air gap. Using this methodology and the recommended clamp scheme, the design restricts peak flux density and the clamp circuit produces negative magnetizing current during reset. The negative magnetizing current during reset prevents flux build-up in the transformer during successive switching periods. Even with no intentional gap in the transformer core, mechanical imperfections will always give a finite effective gap (when calculating with PI Expert a value of 0.02 mm is used). If an air gap is desired for other reasons, it should be as small as possible. Step 7. Check primary current. Use the actual number of turns from the design of the transformer to compute the peak and RMS current on the primary. Primary current was estimated in Step 4 with an ideal turns ratio before the transformer was designed. Add the peak of the magnetizing current to obtain actual peak of the primary current under steady-state conditions. Designers should be aware that the primary current observed on prototype hardware may be lower than predicted because the circuit that resets the flux in the transformer allows a negative average magnetizing current, as mentioned previously in Step 6 in the section on Zero Gap Transformers. The design, however, must allow for conditions when the magnetizing current adds to the reflected secondary currents. Step 8. Determine the input capacitance for holdup time. The holdup time must be specified at a minimum voltage VHOLDUP. This is often, but not always VMIN. For maximum flexibility, this methodology allows the designer to determine the value of input capacitance required to obtain a given holdup time from an arbitrary input voltage. If a DC voltage is specified to mark the beginning of the holdup time, the minimum required input capacitance is CIN ≥ 12 B 12/02 2 POt H ( 2 2 ηDC VHOLDUP − VDROPOUT ) (27) where PO is the total output power that corresponds to the efficiency at the DC bus, ηDC and tH is the holdup time. If an AC voltage VACHOLDUP is specified to mark the beginning of the holdup time, the minimum required input capacitance (no doubler) is 1 2(t H − tC ) + 2P fL CIN ≥ O 2 (28) 2 ηDC 2VACHOLDUP − VDROPOUT where tC is the conduction time of the AC input rectifiers and fL is the frequency of the AC power line. Again, note that tC will increase significantly if the design has passive PFC. The efficiency ηDC excludes losses in the AC input circuit and EMI filter. No power is dissipated in the AC input circuit during the holdup time because the AC input is disconnected. The lower system efficiency η that includes the AC input losses would give a value of CIN that is larger than required. Compare the value from Equation (27) or (28) with the estimate for CIN in Step 1. Adjust CIN in Step 1 and repeat the calculations until the computed value is approximately the same as in Step 1. Step 9. Calculate stress on rectifiers. PI Expert calculates voltage and current stress on rectifiers for guidance in selection of appropriate components. The recommended derating factor for peak inverse voltage is 80%. Derating for the currents is generally not necessary. Thus, the recommended voltage rating for the input bridge rectifier is VPIVAC = 1.25 2VACMAX (29) Current ratings for rectifiers are average values, not RMS. The current rating for the bridge rectifier is computed from I DAVBR = PO ηDC VLL (30) where VLL is the average DC bus voltage at the lowest steadystate line voltage (no doubler). 1 PO − tC 2 fL 2 2 VLL = VACMIN + VACMIN − 2 ηDC CIN (31) AN-30 Calculations of the peak inverse voltage on the output rectifiers use VMAX, VDSOP, and the output voltages with the turns on the transformer windings. Calculations of worst case average current in the catch diodes are with the duty ratio that corresponds to the maximum input voltage. A very good approximation to the average rectifier current is then just the output current. Current in the forward diodes is computed with DMAX. Note that with DC stacked outputs, the rectifiers on the main output must conduct the sum of the currents of the main and auxiliary outputs. output. The computation is based on K∆I, which considers the total ampere turns of the coupled inductor, not just the current in one winding. The inductance of the winding for the main output, valid for only the DC stacked configuration, is LMAIN = VMAIN + VDMAINC N K∆I 0 I MAIN + I AUX LAUX + 1 fS N LMAIN (34) In general, the stress will be different for the forward diode and the catch diode on the same output. Designers will have to consider the one with the greater stress when choosing components that contain both diodes in the same package. PI Expert gives the designer the turns ratio, the total ampere turns, and the peak energy stored in the inductor. The designer has the option to change these parameters by adjustment of the K∆I for each inductor. Step 10. Calculate RMS ripple currents in output capacitors. Currents in the output capacitors are computed at the maximum loads. In continuous conduction mode, the RMS ripple current is given by These quantities assist the designer to obtain an appropriate inductor of either his own design or one from a qualified supplier. Bench evaluation of the prototype will determine if fine adjustment of the turns is necessary in the final configuration. I RMS = K∆I IOUTPUT 2 3 (32) where K∆I is for the particular output under consideration. This expression is reliable for independent outputs and for a main output with no coupled inductors. For converters with auxiliary outputs, Equation (32) is only an estimate. Ripple currents in the individual windings of coupled inductors depend on magnetic coupling coefficients, parasitic voltage drops, and other quantities in the circuit that are difficult to predict. Therefore, designers must evaluate prototype hardware on the bench to confirm that the assumptions of the design are valid for a particular application. Step 11. Calculate parameters for the coupled inductor. The coupled inductor allows the auxiliary outputs to have better regulation than independent outputs, with the penalty of increased complexity of the inductor. PI Expert allows two options for the topology of the auxiliary output. The auxiliary output may be referenced to the main output voltage for the best regulation or to output return when necessary. The reference must be at output return to obtain a negative auxiliary output with a positive main output. Turns ratios for the coupled inductor are the same as the ratios for the transformer. The turns ratio of a coupled inductor for a converter that has one auxiliary output is, in terms of the actual number of turns, N LMAIN N MAIN = N LAUX N AUX (33) Step 12. Calculate inductance for independent outputs. Calculation of the inductance for independent outputs is straightforward and similar to the computation of the parameters for the coupled inductor. Design of the component is simplified because there is no turns ratio associated with an inductor that has only one winding. PI Expert computes the inductance and the peak stored energy. This information is useful for selection of magnetic cores from catalogs. Step 13. Calculate output inductance for the magnetic amplifier. PI Expert computes the output inductor for a magnetic amplifier post regulator in the same way as for an independent output. It does not address the magnetic switching element. Step 14. Adjust output inductors if necessary. The designer may modify the K∆I of any inductor to accommodate special requirements. If the value or the estimated physical size of the computed inductor is not satisfactory, adjust the individual K∆I to achieve the desired result. Step 15. Calculate component values for external reduction of DCMAX. The maximum duty ratio (DCMAX) of TOPSwitch-GX must be restricted to avoid saturation of the transformer during transient loading. A network of four resistors and a capacitor (RA, RB, RC, VZ, RD and CVS in Figure 1 and Figure 1 of Appendix B) determines a variable upper limit on the duty ratio. Adjustment of the maximum duty ratio with input voltage allows enough deviation beyond the steady-state operating point to respond to transients while maintaining enough time in every switching cycle for the transformer to reset. Inductance is computed for the winding that is on the main B 12/02 13 AN-30 100% DUTY RATIO (%) DMAX_RESET 74% DCMAX DXDO DLL_RESET DRESET DMAX_ACTUAL DHL_RESET DXMAX D DXHL DLL_ACTUAL DHL_ACTUAL 0% VDROPOUT VUVLO VMIN VMAX VIN PI-2823-121701 Figure 8. Boundaries of Voltages and Duty Ratio Related to the Selection of RA, RB, RC and RD with CVS in Figure 1. The resistor network also sets the threshold for line undervoltage lockout. Protection from over-voltage is generally not a concern for this topology since it uses a Zener clamp to provide a hard limit on the drain-to-source voltage. The resistors are matched to the capacitor to form an integrator with an appropriate time constant to give a cycle-by-cycle duty ratio limit. The integration of the voltage on the bias winding gives the external duty ratio limit a desirable relationship to the flux in the transformer. The circuit adjusts the duty ratio limit to set an upper bound on the volt-second product, and to balance the volt-second product during TOPSwitch-GX on and off times. The dynamic nature of the circuit allows greater freedom and precision in the design without interference from the line over-voltage threshold limit. Figure 1 shows the locations of resistors RA, RB, RC and RD with capacitor CVS. Several important quantities related to their values are illustrated in Figure 8. The broken vertical lines in Figure 8 mark the boundaries of the DC bus voltage for minimum and maximum operating voltages, the line undervoltage lockout threshold, and the lowest input voltage that will guarantee regulation of the output. The broken horizontal line shows the maximum guaranteed duty cycle of TOPSwitch-GX. A value of 74% is recommended for design. 14 B 12/02 The lowest curve is the duty ratio D that corresponds to steadystate operation at a given input voltage. The straight line with negative slope is the maximum duty ratio DRESET that will still guarantee reset of the transformer for a given VDSOP. The converter must always operate with D less than DRESET to avoid saturation of the transformer. The curved line between the D and DRESET lines is the external duty ratio limit DXMAX that is set by the resistors. The designer must choose the components to set the curve of DXMAX at a desired position between the boundaries of DRESET and D for a given set of specified voltages. PI-Expert prompts the user to enter several parameters that are important to the computation of the resistor values. Some parameters are from the TOPSwitch-GX data sheet while others are design choices. The software suggests default and typical values. The designer can enter maximum and minimum values to check worst case situations. The components are calculated to satisfy the constraints of four parameters: DXDO (external duty ratio limit at VDROPOUT), DXHL (external duty ratio limit at VMAX), VUVLO (input voltage where the TOPSwitch-GX starts switching), and the maximum transient input voltage VOV that is greater than VMAX. AN-30 While there are four resistors, only three are unknown because RA and RB are identical by definition. They are connected in series to keep the voltage across each one below its maximum rating. The three unknown resistors and one capacitor make four unknown quantities that are determined by the four constraints. Figure 8 illustrates the general case where DXDO is between the actual duty ratio DMAX_ACTUAL and DMAX_RESET at the input voltage VDROPOUT. If the converter is not required to respond to transient loads at the end of the holdup time, DXDO and DMAX_ACTUAL can be set to DMAX_RESET. Since response to transient loads is usually required at VMAX, the designer will want to set DXHL at a comfortable margin between DHL_ACTUAL and DHL_RESET. Begin with the computation of values for RA and RB to set the line under-voltage threshold VACUV. RA = RB = VACUV 2 2 IUV (35) where VACUV is the AC input voltage (non-doubled) required for the converter to start, and IUV is the line under-voltage threshold current of the L pin of TOPSwitch-GX from the datasheet. Choose the nearest standard resistor value for RA and RB. Define intermediate variables to make the expressions easier to write and interpret. D − DIL 2 mIL ≡ IL1 I L 2 − I L1 (36) DIL + IL mIL (37) RAB ≡ RA + RB (38) VBZL ≡ VDB + VZ + VL (39) I LD 0 ≡ voltage, and the voltage on the L pin as shown in Figure 1. The Zener diode is chosen as required to raise the curve of DXMAX at the low input voltages. It may not be necessary in all applications. The Zener voltage is 6.8 V in this example. Next, select a value for DXHL that is between DHL_ACTUAL and DHL_RESET. DHL _ ACTUAL = (VMAX VMAIN + VDMAINC N − VDS ) S − VDMAINF + VDMAINC NP DHL _ RESET (40) V = 1 − MAX VDSOP (41) Find the range of permissible values for DXDO. To compute the upper and lower bounds on DXDO, define the intermediate variable KXDO. V K XDO ≡ mIL I LD 0 − MAX RAB NB V − VBZL DROPOUT D NP − XHL N mIL V MAX B − VBZL NP (42) The upper bound for DXDO is then V DXDO < mIL I LD 0 − DROPOUT − K XDO RAB (43) and the lower bound for DXDO is In Equation (36), DIL1 and DIL2 are respectively the values of DCMAX at currents IL1 and IL2 into the L pin. Obtain these values from the data sheet. Use the typical values at first. Then check that the circuit will perform properly at the high and low ends of the tolerance range. DXDO V mIL I LD 0 − DROPOUT RAB > K XDO 1+ DXHL (44) Choose an appropriate value for DXDO between DMAX_RESET and DMAX_ACTUAL that also satisfies the boundaries of (43) and (44). Next, compute the intermediate constants r1 and r2. In Equation (37), DIL is the value of DCMAX at current IL into the L pin. Use the same DIL1 with IL1 or DIL2 with IL2 as in Equation (36). Either pair will give the same result. ILD0 has a physical interpretation that cannot be realized: if the duty ratio reduction characteristic continued along its linear slope, it would reach zero at the current ILD0. NB − VBZL DXDO VDROPOUT NP r1 ≡ VDROPOUT DXDO I LD 0 − − RAB mIL (45) The voltages VDB, VZ and VL are respectively the forward drop of the rectifier in series with the Zener diode and RC, the Zener B 12/02 15 AN-30 VIN RUVA 2 TOPSwitch-GX CONTROL Pin VB DMAX v + vB + 4vA vC = B 2vA (50) RD mIL (51) RUVB where Q1 2N3906 vA = 3.3 K TOPSwitch-GX X Pin vB = VBZL + I LD 0 RD − RUVC R RC N − VIN D + B mIL RAB N P (52) 5K V vC = RC I LD 0 − IN RAB Remote ON/OFF TOPSwitch-GX SOURCE Pin PI-2824-121701 Figure 9. External Under-Voltage Lockout Circuit. NB − VBZL DXHL VMAX NP r2 ≡ V D I LD 0 − MAX − XHL RAB mIL (46) Now choose an appropriate value for the capacitor. Proper choice of the capacitor allows the converter to operate safely with transient input voltages greater than VMAX. The line overvoltage feature of TOPSwitch-GX is not used in the conventional fashion in this application. The circuit operates in an over-voltage mode that reduces the maximum duty ratio further by reduction of the switching frequency. The value of the capacitor CVS is chosen to give the desired behavior in the over-voltage mode. Select an input voltage VOV greater than VMAX that marks the onset of over-voltage operation. Then compute the maximum duty ratio DXOV that corresponds to the specification in the TOPSwitch-GX data sheet for the Line Over-Voltage Threshold Current IOV. DXOV = DIL − mIL ( IOV − I L ) Compute the values for the resistors RD and RC. r1 − r2 DXDO − DXHL (47) RC = r1 − DXDO RD (48) RD = Finally, compute the capacitor value as VOV IOV − (1 − DXOV )TS − t R( ON ) RAB CVS = KOVHYS IOVHYS RD ( Verify that the parameters are within the desired range with the actual component values. IUV ( RA + RB ) 2 (54) Here DIL, mIL and IL are the same as in Equations (36) and (37). Select the nearest standard resistor values for RC and RD. VACUV = (53) ) (55) where (49) This is the AC input voltage (non-doubled) where the converter will begin to operate. TS is the switching period 1/fS in normal operation tR(ON) is the Remote ON Delay IOVHYS is the hysteresis of the IOV threshold KOVHYS is a constant selected by the designer. The external duty ratio limit at any DC bus voltage VIN may be computed from the expression The first three parameters are taken from the data sheet. The constant KOVHYS is selected to provide sufficient ripple voltage 16 B 12/02 AN-30 on the capacitor for reliable operation of the circuit. The recommended range for KOVHYS is 3 to 5. Choose the nearest standard value for capacitor CVS. These expressions to compute the component values have been simplified for ease of presentation. Some variables related to parasitic elements have been ignored. If any of the results are not satisfactory, choose different standard values for the resistors or a different voltage for the Zener diode. Gross deviations from the desired results may require different values for the parameters chosen at the beginning of this step, since some sets of parameters may not be compatible. Step 16. Calculate values for resistors in optional external under-voltage lockout circuit. The resistor network that determines the characteristics of the external duty ratio limit sets the minimum voltage where the converter begins to operate. The contributions of current from the bias voltage create too much hysteresis for the circuit to be useful as an under-voltage detector after the converter begins to operate. Therefore, the external under-voltage circuit in Figure 9 is recommended for applications where a positive turnoff threshold is desired. Choose a value VACUVL for the turn-off threshold and a value VACUVX that is approximately midway between VACUVL and VACUV: VACUVL < VACUVX < VACUV VUVX = VACUV 2 (57) VUVX = VACUVX 2 (58) 2 VUVL = 2VACUVL CCP NP NMAIN D1 VR1 D VR2 VR3 (59) (60) TOPSwitch-GX CONTROL C S Primary Return PI-2825-121701 Figure 10. Recommended Clamp Circuit. resistor that can dissipate PRUVA watts. 2 RUVA 2V = MAX PRUVA (61) A typical resistor for this purpose will have a power rating of PRUVA = 125 mW. Choose the nearest standard value for RUVA. Then compute RUVB and RUVC. RUVB Define the intermediate variable v1 that considers the voltage VC(SHUNT) on the CONTROL pin and the base-emitter voltage on the transistor. v1 = VC ( SHUNT ) − VBEQ1 VIN (56) The corresponding DC bus voltages (non-doubled) are 1 − tC 2 PO 2 fL − ηDC CIN RCS CCS NB V − v N UVL 1 = RUVA P V − VUVL UVX (62) v RUVC = RUVA 1 VUVX (63) Choose the nearest standard values for RUVB and RUVC. Then check VACUVL and VACUVX with the actual resistor values. Compute the approximate value of RUVA to meet the constraint of maximum power dissipation. Assume a 50% derating for a B 12/02 17 AN-30 VAUX VMAIN LF R3 C1 R5 R6 R1 NP CF NMAIN C2 R4 R2 U1 TL431 R7 RTN U2 PI-2826-121901 Figure 11. General Configuration of Feedback Circuit for Forward Converter with TOPSwitch-GX. VUVL R v1 UVB + 1 RUVC = RUVB N B + RUVA N P 1 PO − tC 2 fL V = UVL + 2 ηDC CIN (64) 2 VACUVL VACUVX = v1 RUVA 1 + RUVC 2 (65) (66) If VACUVL and VACUVX are not satisfactory, adjust the values of the resistors. Step 17. Choose components for the clamp circuit. Figure 10 shows connections for the elements of a Zener clamp circuit that is suitable for many applications. Capacitor CCP, diode D1 and the string of Zener diodes are on the primary side of the transformer. Resistor RCS and capacitor CCS are on the secondary side of the transformer. 18 B 12/02 This arrangement limits the voltage on the drain of the TOPSwitch-GX to approximately the sum of the voltages of the string of Zener diodes. It also recovers most of the energy from leakage inductance and magnetization inductance, and returns it to the input or delivers it to the output. Select the Zener diodes to limit the drain voltage to VDSOP. Choose the voltage, size and number of diodes in the string to achieve the desired VDSOP and to handle the power dissipation. This arrangement is adequate for applications where the clamp circuit dissipates less than 5 W. Capacitor CCP supplements the natural stray capacitance on the drain node to absorb energy that comes mostly from the leakage inductance. The value must be selected empirically because it is difficult to predict natural stray capacitance and leakage inductance accurately enough to calculate a proper value. Energy not absorbed by the capacitance will be dissipated in the Zener string, so CCP cannot be too small. If CCP is too large, its voltage will change too slowly to allow the transformer to reset during transients. Typical values for CCP are in the neighborhood of 2 nF. Diode D1 must be a slow recovery type such as a 1N5407. The recovery of D1 removes enough charge from CCP to stabilize its voltage and to discharge some of its stored energy into the primary of the transformer. This energy returns to the input on the next switching cycle. AN-30 The remaining components are connected across the forward diode on the main output. Energy from leakage inductance on the secondary and magnetization inductance of the transformer charges CCS when the TOPSwitch-GX turns off. The energy from CCS is delivered to the output during the next switching cycle. Resistor RCS provides damping for oscillations that would otherwise occur from the resonance of CCS with stray inductance. Typical values are in the neighborhood of 0.1 µF for CCS and 1 Ω for RCS. The resistor must dissipate power that corresponds to the charge and discharge of CCS each cycle. It typically will dissipate less than 1 watt. Proper values must be determined empirically from evaluation of prototype hardware. Step 18. Choose components for the feedback circuit. The pulse width modulator in TOPSwitch-GX sets the duty ratio according to the current into the CONTROL pin. TOPSwitch-GX senses the drain current for protection only, and does not use it for control purposes. Thus, forward converters with TOPSwitch-GX operate with a voltage-mode control that modulates the converter's duty ratio directly according to an error signal from the regulated output voltage. Voltage mode control provides sufficient loop bandwidth and is fully able to meet all the specifications for PC Main and other high power applications. The general configuration of the feedback circuit for a forward converter with TOPSwitch-GX is illustrated in Figure 11. It shows a typical connection of a TL431 voltage regulator with an optocoupler and components for frequency compensation. There is an optional connection to VAUX to improve the regulation of the auxiliary output by sharing regulation with the main output. This general technique is common in all types of multiple output regulators. While the design of the feedback loop is beyond the scope of this application note, it is useful to consider the general circuit of Figure 11. The components are chosen to provide regulation of output voltages and to shape the frequency characteristics of the control loop. Proper design of the feedback components is important not only for the stability of the system, but also for transient response of the output. Inductor LF with capacitor CF reduces high frequency noise on the main output. As such, it introduces phase shift in the small signal response that would make loop compensation difficult if the only feedback for the main output were taken from the voltage on CF. To avoid difficulties with the feedback loop, information about the main output is taken from two places. Low frequency information that is most important to the DC regulation comes mainly through the path formed by resistor divider of R5, R6 and R7. The voltage on R7 is the reference voltage of the TL431 when VMAIN and VAUX are at their desired values. High frequency information that is most important in the transient response comes through the path formed by the optocoupler's diode and R2. This same technique is commonly used with TOPSwitch-GX in flyback converter applications. The values of R1, R3, R4, C1 and C2 are chosen to shape the frequency response. The choices are influenced by the components on the CONTROL pin and equivalent series resistance of the output capacitor, which can be important features of the loop gain. Designers must make proper measurements of loop gain and transient response on prototype hardware to confirm that the converter performs as desired under all specified conditions. Evaluation of Prototype Hardware The design that results from the steps of the previous section contains the uncertainties of the initial assumptions. Performance must be validated with measurements on prototype hardware before the design is complete. At this stage in the procedure, the designer will have enough information to build a circuit that will operate at nominal conditions for evaluation on the bench. The designer must test the circuit at all the limits of specified performance. Measurements will indicate which changes to the original assumptions are necessary. A successful design is obtained after repetition of the procedure with parameters adjusted from measurements on the hardware. The evaluation should include observation of the drain-tosource voltage on TOPSwitch-GX under steady state operation and transient conditions. Apply power to the converter slowly with minimum loads. Then exercise the loads on the outputs in different combinations, first at the nominal input voltage and then at the extremes of input voltage. Observe the behavior at various static loads before going to transient loading. Check for excessive power dissipation in the clamp circuit. A useful technique is to monitor the average current in the string of Zener diodes in the clamp circuit with a low value resistor in series. A capacitor in parallel with the resistor will develop a voltage proportional to the average current through the diodes. The product of this voltage and the clamp voltage gives an indication of the power dissipation in the Zener diodes. Monitor the drain current when the output has steady-state overload and during transient loading. The waveform will provide important information about the operation of the converter and the limits of the design. Check that the current B 12/02 19 AN-30 limit of the TOPSwitch-GX is sufficient for all the specified conditions. Check that the transformer does not saturate under all steadystate combinations of line and load. Verify the proper design of the circuit to limit maximum duty ratio with the procedure in Appendix B. Check the ripple on all the output voltages with several combinations of input voltage and output loading, particularly if the design uses a coupled inductor. Verify that the undervoltage thresholds are within design limits for startup and for shutdown. Key Design Considerations While the design of forward converters with TOPSwitch-GX has much in common with designs that use discrete transistors and controllers, some important differences must be considered. Attention to these items will significantly reduce the time to arrive at a successful design. • A proper clamp circuit is required to control the maximum drain voltage. Resonant clamp circuits are not recommended. While the example clamp circuit in this document is suitable for moderate power levels, the circuit will need modification to adapt to applications that require the dissipation of more power. • Leakage inductance of the transformer affects the power dissipation in the clamp circuit. High leakage inductance will prohibit the use of simple clamp circuits. Be aware that a magnetic amplifier post regulator will greatly increase the effective leakage inductance of the transformer. • The primary inductance of the transformer affects the power dissipation in the clamp circuit. Maximize the primary inductance to reduce the magnetizing current and the energy that must be processed by clamp circuit. • Use a slow diode for the rectifier D1 in the clamp circuit. A fast diode will greatly increase the amount of energy that the clamp must dissipate. • Remember that the components RCS and CCS on the secondary are important components of the clamp circuit. Failure to include this network will cause excessive power dissipation in the clamp components on the primary. 20 B 12/02 • Confirm in bench evaluations that CCP in the clamp circuit on the primary is not too large. Perform transient load tests at low and high input voltages. Monitor the drain voltage waveform for volt-second balance to be certain that the transformer does not saturate. • Check the temperature of the Zener diodes VR1, VR2 and VR3 in the clamp circuit under maximum load at low input voltage and with repetitive transient loading. If the power supply does not have a latching shutdown for fault conditions, check it under a sustained short circuit on the output. There could be excessive heating if CCP is too small, the primary inductance of the transformer is too low, or if the leakage inductance it too high. • Match the current limit to the load. Use the X pin to program the current limit lower, especially if a larger TOPSwitch-GX is selected for thermal or efficiency reasons. References [1] R. W. Erickson and D. Maksimovic, ´ Fundamentals of Power Electronics, Second Edition. Kluwer Academic Publishers, 2001. ISBN 0-7923-7270-0. [2] Colonel Wm. T. McLyman, Transformer and Inductor Design Handbook, Second Edition. Marcel Dekker, Inc., 1988. ISBN 0-8247-7828-6. [3] Colonel Wm. T. McLyman, Magnetic Core Selection for Transformers and Inductors, A User's Guide to Practice and Specification, Second Edition. Marcel Dekker, Inc, 1997. ISBN 0-8247-9841-4. [4] Colonel W. T. McLyman, Designing Magnetic Components for High Frequency dc-dc Converters. Kg Magnetics, Inc., 1993. ISBN 1-883107-00-8. [5] Micrometals Inc., 5615 E. La Palma Avenue, Anaheim, CA 92807 USA; www.micrometals.com. [6] MAGNETICS, P.O. Box 391, Butler, PA 16003-0391 USA, www.mag-inc.com. AN-30 Appendix A Table of Nomenclature Name in AN-30 Description δD Difference between actual and effective duty ratio that results from leakage inductance in the transformer. Total system efficiency (lower case Greek letter eta). Efficiency excluding losses in AC input circuit and EMI filter. Used in computation of input capacitance required for holdup time. ηDC ≥ η. Permeability of free space (4π x 10-7 H/m). Relative permeability of ferrite core material (lower case Greek letter mu). Dimensionless. Effective cross-sectional area of transformer core. Inductance coefficient of ungapped transformer core. Maximum AC flux density in transformer core. Maximum flux density in the power transformer. Total bulk capacitance at the DC input to the converter. Capacitor in circuit for external reduction of DCMAX. η ηDC µ0 µr Ae AL BM BPEAK CIN CVS D1 D DHL_ACTUAL DHL_RESET DIL DIL1 DIL2 DLL_ACTUAL DLL_RESET DMA DMAX DMAX_ACTUAL DMAX_RESET DNOM DRESET DXDO DXHL DXOV DCMAX fL fS ij IAUX IDAVBR IL Diode in primary clamp circuit. Duty ratio of TOPSwitch-GX at a given operating point. Duty ratio at the highest operational DC input voltage VMAX. Maximum duty ratio to guarantee reset of the transformer at DC input voltage VMAX. Maximum duty ratio at current IL. The DCMAX at current IL1 into the L pin of TOPSwitch-GX. The DCMAX at current IL2 into the L pin of TOPSwitch-GX. Duty ratio at lowest steady state DC input voltage VMIN. Maximum duty ratio to guarantee reset of the transformer at DC input voltage VMIN. The duty ratio of the magnetic amplifier. The maximum duty of TOPSwitch-GX at the lowest operational DC input voltage VDROPOUT. Actual duty ratio of TOPSwitch-GX at the lowest operational DC input voltage VDROPOUT. Maximum duty ratio to guarantee reset of the transformer at DC input voltage VDROPOUT. This is less than maximum duty cycle DCMAX. Duty ratio at nominal input voltage. Maximum duty ratio to guarantee reset of the transformer at a given operating point. Highest maximum duty cycle as set by current into the L pin of TOPSwitch-GX with external components. Occurs at DC input voltage VDROPOUT. The lowest maximum duty cycle as set by current into the L pin of TOPSwitch-GX with external components at DC input voltage VMAX. The maximum duty ratio that corresponds to IOV. Maximum default duty cycle of TOPSwitch-GX (see Data Sheet). AC line frequency. TOPSwitch-GX switching frequency. Instantaneous current in secondary winding j of the transformer. Output current of the auxiliary output Current rating for the bridge rectifier. Current into the L pin of TOPSwitch-GX. B 12/02 21 AN-30 Name in AN-30 Description IL1 IL2 Current into the L pin of TOPSwitch-GX to give DCMAX of DIL1. Current into the L pin of TOPSwitch-GX to give DCMAX of DIL2. Intermediate variable to compute values of components in circuit for external reduction of DCMAX. Output current of the main output. Output current of the magnetic amplifier on the secondary winding for the main output. Current in the secondary winding of the main output required to stop conduction of the main catch diode. Maximum average output current for a specific output. Minimum average output current for a specific output. Peak value of the magnetizing current of the transformer referred to the primary winding. Output current of the independent output. Average current on a given output. Line over-voltage threshold current for the L pin of TOPSwitch-GX (see data sheet). Hysteresis of the IOV threshold (see data sheet). Instantaneous current in the primary of the transformer. Peak current in the primary of the transformer. RMS current in an output capacitor. . Hysteresis in line under-voltage threshold current (see data sheet). TOPSwitch-GX current limit with external current limit reduction. External current limit reduction factor. Maximum theoretical value of the ripple current factor for an output inductor, approached as D goes to zero. Ripple current factor for an output inductor at a given operating point. Constant used to compute value of capacitor in circuit for external reduction of DCMAX. Intermediate variable to compute values of components in circuit for external reduction of DCMAX. Effective path length of transformer core. Length of air gap in transformer core. Inductance of the coupled inductor measured at the winding for the main output with other windings open. Leakage inductance of the transformer on the secondary winding for the main output. Output inductor in the magnetic amplifier regulator on the secondary winding for the main output. Maximum Duty Cycle Reduction Slope (a positive number). Inductance of the primary of the transformer with all other windings open. Turns ratio of the auxiliary output winding with respect to the main output winding. Turns ratio of the independent output winding with respect to the main output winding. Turns ratio of secondary winding j of the transformer with respect to the main output winding. Turns ratio of the primary winding with respect to the main output winding. Actual number of turns for secondary winding j on the transformer. Number of turns for the auxiliary winding on the transformer. Number of turns for the bias winding on the transformer. Number of turns for the independent winding on the transformer. Number of turns for the main output winding on the transformer. ILD0 IMAIN IMAINMA IMAINSEC IMAXIMUM IMINIMUM IMP IIND IOUTPUT IOV IOVHYS IP IPP IRMS IUVHYS IXLIMIT KI K∆I0 K∆I KOVHYS KXDO le lg LMAIN LMAINLK LMAINMA mIL LP nAUX nIND nj nP Nj NAUX NB NIND NMAIN 22 B 12/02 AN-30 Name in AN-30 Description NP PO PRUVA Number of turns for the primary winding on the transformer. Total output power of the power supply. Power dissipation in the resistor RUVA. Intermediate variable to compute values of components in circuit for external reduction of DCMAX. Intermediate variable to compute values of components in circuit for external reduction of DCMAX. r1 r2 RA RAB Resistor in the network that sets the line under-voltage threshold VACUV. Intermediate variable to compute values of components in circuit for external reduction of DCMAX. RB Resistor in the network that sets the line under-voltage threshold VACUV. RC RD Resistor in circuit for external reduction of DCMAX. Resistor in circuit for external reduction of DCMAX. RLMAIN RP RSMAIN RUVA RUVB RUVC tC tH tR(ON) Resistance of the winding of the output inductor for the main output. Resistance of the primary winding of the transformer. TS v1 vA vB vC VACHOLDUP VACMAX VACMIN VACNOM VACUV VACUVL VACUVX VAUX VAUXREF VBZL VDAUXC VDB VDINDC VDINDF VDMAIN Resistance of the secondary winding for the main output. Resistor in optional external under-voltage lockout circuit. Resistor in optional external under-voltage lockout circuit. Resistor in optional external under-voltage lockout circuit. Conduction time of the bridge rectifier. Holdup time. Remote ON Delay of TOPSwitch-GX. (See data sheet). Switching period of TOPSwitch-GX, equal to 1/fS. Intermediate variable to compute resistors in optional external under-voltage lockout circuit. Intermediate variable to compute values of DXMAX. Intermediate variable to compute values of DXMAX. Intermediate variable to compute values of DXMAX. Steady state AC input voltage that corresponds to the beginning of the holdup time. Maximum steady-state AC input voltage. Minimum steady-state AC input voltage. AC input voltage where independent output voltages should be at their nominal values. Minimum AC input voltage where converter must start. AC input voltage where the converter shuts off with optional external UVLO circuit. AC input voltage where the optional external UVLO circuit enables the TOPSwitch-GX when input voltage is rising from zero. Voltage on the auxiliary output. Reference voltage for the auxiliary output in the DC stacked topology. This is usually VMAIN. Intermediate variable in the computation of components for DCMAX reduction circuit. Voltage drop on the catch diode of the auxiliary output when the diode is conducting. Voltage drop on the diode of the bias winding when the diode is conducting. Voltage drop on the catch diode of the independent output when the diode is conducting. Voltage drop on the forward diode of the independent output when the diode is conducting. Voltage drop on the catch diode and the forward diode of the main output when the two are identical. B 12/02 23 AN-30 Name in AN-30 Description VDMAINC VDMAINF VDROPOUT VDS VDSOP VHOLDUP VIN VIND VL VLL VMAX VMAIN Voltage drop on the catch diode of the main output when the diode is conducting. Voltage drop on the forward diode of the main output when the diode is conducting. Lowest DC input voltage that will guarantee a regulated output. Average drain-to-source voltage on the TOPSwitch-GX during its on-time. Maximum drain-to-source voltage on the TOPSwitch-GX during operation. DC input voltage that marks the beginning of the holdup time tH. Voltage on the bulk input capacitance CIN. Voltage on the independent output. Voltage on the L pin of TOPSwitch-GX with positive current. Average DC input voltage at VACMIN . Maximum DC input voltage, equivalent to the peak value of VACMAX. Regulated DC voltage on the main output. Regulated DC voltage from the magnetic amplifier derived from the secondary winding for the main output. Valley of the rectified AC input voltage at VACMIN. Nominal DC input voltage. Midpoint between peak and valley of the ripple voltage on CIN when the AC input voltage is VACNOM. Recommended voltage rating for the bridge rectifier. DC input voltage corresponding to VACUV. DC input voltage corresponding to VACUVL. Minimum DC input voltage for TOPSwitch-GX to start, set by resistor on from DC input voltage to L pin. DC input voltage corresponding to VACUVX. Voltage of the Zener diode in the DCMAX reduction circuit. Number of secondary windings on the transformer. VMAINMA VMIN VNOM VPIVAC VUVH VUVL VUVLO VUVX VZ W 24 B 12/02 AN-30 Appendix B Procedure for Verifying Duty Ratio Reduction Circuit Predictions from analytic expressions are only as accurate as their inputs. It is always advisable to confirm the desired operation of circuits with actual hardware before they are released to production. Reduction of the maximum duty ratio of TOPSwitch-GX is particularly important in the forward converter application. Therefore, users are strongly advised to follow this simple procedure to confirm the correct operation of the circuit to reduce the maximum duty ratio. Add the circuits and instrumentation as shown in Figures B1 and B2 to the forward converter under evaluation as described in the steps below. This setup allows independent adjustment of the input voltage and the regulated main output voltage while monitoring the current into the L pin. 1. Connect the AC input section in the non-doubling configuration. Add enough extra bulk capacitance in parallel with CIN to make the ripple voltage negligible. Alternatively, the converter may be operated from a high voltage DC power supply instead of from the AC source. Insert the parallel combination of a 100 Ω resistor and a 0.1 µF capacitor in series with the L pin. Monitor the voltage across the resistor with a digital voltmeter. Place a 1 kΩ resistor in each lead of the voltmeter to avoid interference from common VIN RA Added Bulk Cap 1800 µF 400 V CIN CCP NP RB 0.1 µF 50 V U1 TOP247Y D L X RD VZ 100 Ω CONTROL S RC F C CVS To PWM Regulator Circuit NB RTN 1 kΩ To On/Off Circuit Monitor Drain Current with Oscilloscope to Determine Duty Ratio 1 kΩ Digital Voltmeter L pin Current Monitor Circuit (190 µA is 19 mV) PI-2845-112102 Figure B1. Setup to Measure Current into LINE-SENSE (L) Pin. B 12/02 25 AN-30 where DIL is the minimum DCMAX at the IL of 190 µA, and the other terms are as they are defined in the text and Appendix A. mode noise. Monitor the current in the DRAIN pin of TOPSwitch-GX with a current probe and an oscilloscope. Connect an adjustable low voltage DC power supply to the feedback circuit as shown in Figure B2. 2. Set the oscilloscope to read the duty ratio from the waveform of the TOPSwitch-GX drain current. Most digital oscilloscopes will provide a direct readout of the numerical value. 5. Adjust the duty ratio to DIL by forcing the main output to regulate at a higher voltage. To do this, reduce the voltage of the bench power supply from 15 V until the duty ratio measured from the drain current is DIL. 3. Adjust the low voltage DC power supply to 15 V. 6. Verify that the current into the L pin is within 5% of IL. The voltmeter should read 19 mV when IL is 190 µA. 4. Operate the converter at full load. Adjust VIN to the value that corresponds to the duty ratio limit specified in the data sheet for a device at the low end of the tolerance range. The DC input voltage for these conditions is given by If it is not possible to adjust the circuit to meet these conditions, the circuit is not guaranteed to operate properly with all devices in the specified range of tolerance. Repeat the design with revised parameters. R VBZL + I L RD + C DIL VIN = NB RC 1 + RD + N P RAB DIL (B1) VMAIN Main Output Regulator Added Network to Adjust Regulated Output OPTO + 1N4148 3.3 kΩ _ 0 VDC to +15 VDC Adjustable Power Supply 3.3 kΩ TL431 RTN Start with the adjustable power supply at 15 V. By lowering the output of the external supply a threshold will be reached where the diode will become forward biased. Lowering the adjustable supply further will force the main output to a higher regulation voltage. PI-2846-041502 Figure B2. Circuit to Adjust Main Regulated Output Voltage to Higher Value. 26 B 12/02 AN-30 Appendix C Introduction This appendix describes a worked example that shows how to use the TOPSwitch-GX forward design spreadsheet, to calculate values for key components, such as the input capacitance, transformer number of turns and duty cycle reduction circuitry, used on the EP-12 145 W doubled mains prototype board. The design spreadsheet can be found in the PIXls utility as part of the PI Expert design tool version 4.0.3 and above. The worked example and spreadsheet uses the same design equations as presented in the design methodology. However, rather than following the flow chart in the methodology, the worked example follows the order of the spreadsheet. Thus step (a) in worked example does not correspond to step 1 from AN-30, and so on. Since the EP-12 has a doubler input stage, the calculations within this document address the design in the doubled mode. Note that both AN-30 and the design spreadsheet assume single input voltage ranges. Universal input designs are not supported. Step by Step Example for EP-12 Note: All user inputs are in column B and all calculated results are in column F of the spreadsheet. Step (a). Enter the Power supply Output specifications: VMAIN , IMAIN , VMAINMA, IMAINMA, VAUX1 and IAUX1 Enter the mainwindingoutputvoltage VMAIN = 5 V (VMAIN, B3) Enter the main winding full load current IMAIN = 12 A (IMAIN, B4) Enter the mag-amp winding output voltage VMAINMA = 3.3 V (VMAINMA, B5) Enter the mag-amp winding full load current IMAINMA = 12 A (IMAINMA, B6) Enter the auxiliary winding output voltage VAUX1 = 12 V (VAUX1, B7) Enter the auxiliary winding full load current IAUX1 = 4 A (IAUX1, B8) Step (b). Define system requirements: VACMAX , VACMIN , fL, fS , VO , PO , η, tH Set minimum AC input voltage = 90 V. Set maximum AC input voltage = 132 V Line frequency fL = 50 Hz Power supply Efficiency Estimate: If no better value available use 75%. Hold-up time tH = 16 ms Set bridge rectifier conduction time. If no better value available use default value tC = 3 ms (VACMIN, B14) (VACMAX,B15) (fL, B19) (EFF, B22) (th, B21) (tc, B20) Step (c). Calculation of Minimum and Maximum DC input voltages: VMIN , VMAX The spreadsheet calculates the maximum DC input voltage, VMAX , at AC high line and minimum DC input voltage VMIN , at AC low line for which the supply remains in regulation under steady state operating conditions. For the EP-12 prototype, these values are calculated as follows VMAX = 373 V VMIN = 188 V (VMAX, F17) (VMIN, F16) Step (d). Determine dropout voltage: VDROPOUT The dropout voltage determines the point where the converter looses regulation, at the end of holdup time, due to reaching maximum duty cycle. The dropout voltage, VDROPOUT, and maximum duty cycle are linked. For a higher dropout voltage the designer has to enter a lower value for DMAX_GOAL and for a lower dropout voltage the designer should entger higher value of DMAX_GOAL. This ensures the operating duty-cycle is within an acceptable range. B 12/02 27 AN-30 As an initial estimate for a 3:1 operating range (VMAX : VDROPOUT), DMAX_GOAL = 0.7 and for a 2:1 operating range, DMAX_GOAL = 0.5. In EP-12 prototype the dropout voltage is low, to maximize holdup time, so a relatively high value for DMAX_GOAL has been selected. (Operating range is 373 V to 132 V or 2.8:1). Set dropout voltage VDROPOUT = 132 V (VDROPOUT, F24) Set the maximum duty-cycle DMAX_GOAL = 0.7 V (DMAX_GOAL, F25) Step (e). Determine the bulk capacitance: CIN The spreadsheet checks for the input capacitance value based on hold-up time and output power. The user should decide on a hold-up time first and then try different values of input capacitance such that no warnings are shown. This indicates that with the chosen capacitor value, it is possible to meet the desired hold-up time. Assume 1µF/W for doubled mains applications as a starting point. We thus have CIN = 1µF/W x 147.6 W = 147.6 µF Select next larger standard value. Note: The EP-12 design has a double input configuration. A doubler circuit has two capacitors in series, each of which have a value which is twice that calculated above. Selecting the next larger standard value for twice 147.6 µF, we have 2 x CIN = 330 µF, 200 V The actual value entered in the spreadsheet is CIN = 165 µF (CIN, B18) Step (f). Selection of Rectifier diode drops (Vf): VDMAIN , VDMAINMA , VDAUX1 , VDB The spreadsheet automatically selects the type of rectifier (ultra-fast or Schottky) based on the output voltage. The corresponding diode drops are listed as follows: The voltage drop on main winding rectifier diode VDMAIN = 0.5 V (VDMAIN, F41) The voltage drop on mag-amp rectifier diode VDMAINMA = 0.5 V (VDMAINMA, F42) The voltage drop on auxiliary winding diode VDAUX1 = 0.7 V (VDAUX1, F43) The voltage drop on bias winding rectifier VDB = 0.7 V (VDB, F45) The values calculated by the spreadsheet may be overridden by entering the desired voltage drop in column B (B41 to B45). Step (g). Selection of Bridge Rectifier Diode based on peak inverse voltage and average rectifier current: VPIVAC , IDAVBR The recommended voltage rating for input bridge rectifier is given in Equation (29). VPIVAC = 467 V (VPIVAC, F49) Current ratings for rectifiers have average values not RMS values. The current rating for the bridge rectifier can be calculated from Equation (30) in AN-30. IDAVBR = 0.714 A (IDAVBR, F50) Step (h). Selection of Ripple current factor: K∆I K∆I is defined in AN-30. It is a ratio of the ripple in the output current to the average current in the output inductor. This determines the size of the output inductor. As recommended in AN-30 choose K∆I between 0.15 and 0.3. For the EP12 design, this value was selected as K∆I = 0.15 Step (i). Selection of TOPSwitch-GX and related parameters: IP , KI , RX, VDS The operating peak drain current is calculated as IP = 2.45 A (KDI, B27) (IP, F84) Select an appropriate TOPSwitch according to peak primary current as well as for power dissipation. The TOP247Y was selected and has a minimum current limit of 3.34 A. Current limit should be externally programmed to approximately 8-12% above the operating peak drain current, that is IXLIMIT = IP x 1.11 = 2.45 x 1.11 = 2.712 A. 28 B 12/02 AN-30 The external current-limit reduction factor is given by Equation (15) in AN-30 KI = 2.712 = 0.81 3.34 Set external current limit reduction factor KI = 0.81 (KI, B35) The external current limit is reduced from 3.34 A to 2.712 A using a current limit-program resistor. The external current limit resistor is calculated by the spreadsheet as RX = 7.78 kΩ (RX, F36) TOPSwitch switching frequency fs = 132 kHz (FS, D34) On the prototype board an 8.3 kΩ resistor was used. The larger value was required to compensate for the additional voltage drop caused by the remote on-off circuit. The spreadsheet also estimates the ON state drain to source voltage drop. VDS = 8.1 V (VDS, F38) Step (j). Selection of the "R-FACTOR" The R-Factor is an estimate of percentage of power lost in the transformer windings, diode and PC board trace resistance. Typically this value is less than 10% for most well designed power supplies. Use this value if no better data are available. R-Factor = 9% (RFACTOR, B61) Step (k). Selection of number of turns for transformer windings: NMAIN , NP , NAUX1, NB The number of turns for all outputs are calculated by the spreadsheet. In EP-12 these values are as follows: Number of turns on main winding NMAIN = 3 (NMAIN, F64) Number of turns on Primary winding NP = 45 (NP, F67) Number of turns on auxiliary winding NAUX1 = 4 (NAUX1, F69) Number of bias winding turns NB = 6 (NB, F68) Check all outputs on prototype hardware to conform that they are within acceptable limits. Step (l). Selection of Optocoupler and Transformer Core Parameters. Selection of Optocoupler: VCEO The bias winding should provide a minimum of 8 V on the collector of the photo transistor at the lowest operating voltage. When no external under-voltage circuit is used the lowest operating voltage may be much lower than expected. Increase bias turns to increase minimum bias voltage. At higher input voltages the collector voltage should not exceed VCEO, the collector to emitter breakdown voltage. The spreadsheet calculates this maximum blocking voltage imposed on the optocoupler as: VCEO = 49.8 (VCEO OPTO, F120) Select an optocoupler with a high blocking voltage. Typically a 60 V (VCEO) optocoupler is used. Transformer core parameters: M, L, BM, BP Set safety margin M. Use 3 mm for margin wound with 115 VAC doubled input. Set to zero if triple insulated secondary windings are used. In the EP-12 prototype 3 mm margin is selected. Enter margin M = 3 mm (M, B62) Calculate the number of primary layers. Start with 1 layer, and check for warnings. The spreadsheet calculates the primary side wire cross sectional areas based on number of layers, number of turns and bobbin winding width. In the EP-12 prototype 1 layer corresponds to a wire size of AWG 26, but due to skin effect is not fully utilized. Using 0.8 layers, does not fill up the bobbin entirely, but has an acceptable winding resistance and current density. Enter number of layers L = 0.8 (L, B63) B 12/02 29 AN-30 The spreadsheet also calculates the wire gauge as (AWG-28). Maximum operating flux density, BM, is the flux density under conditions of full load, and high line. The spreadsheet calculates and returns this value. Check that this value is less than 2000 gauss. BM = 1816 gauss (BM, F74) Peak flux density is the maximum allowable flux density in the core under transient conditions. This value is also calculated by the spreadsheet. Check that this value does not exceed 3000 gauss. BP = 2884 gauss (BP, F75) Step (m). Transformer design parameters: Verify that the maximum and minimum limits of the TOPSwitch-GX duty-cycle reduction parameters for both high-end and lowend tolerance parts lie within the reset and regulating limits for any given input voltage. Reset parameters: DMAXRESET , DLLRESET , DHLRESET Referring to the curve in Figure 8 these three parameters define the core-reset curve for the transformer. DMAXRESET = 0.79 (DMAX RESET, F145) DLLRESET = 0.63 (DLL RESET, F152) DHLRESET = 0.36 (DHL RESET, F157) Max duty-ratio (Low-end Tolerance part) parameters: DXDOMIN , DXLLMIN , DXHLMIN To ensure correct operation with devices at the higher and lower ends of the maximum duty-ratio, the spreadsheet provides calculations assuming tolerance limits. Referring to Figure 8, the parameters with MIN correspond to the parameters for the low-end tolerance part. Duty-ratios corresponding dropout voltage, low-line input voltage and high line input voltages are listed. These duty-ratios at the corresponding voltages define the lower limit curves for the maximum duty-cycle reduction circuit. This curve should be above the DACTUAL curve. DXDOMIN = 0.70 (DXDO MIN, F146) DXLLMIN = 0.55 (DXLL MIN, F150) DXHLMIN = 0.24 (DXHL MIN, F155) Max duty ratio (High-end tolerance part) parameters: DXDOMIN , DXLLMIN , DXHLMIN Again, referring to Figure 8, the parameters with subscripts MAX correspond to the parameters for the high-end tolerance part. Duty-ratios corresponding dropout voltage, low-line input voltage and high line input voltages are listed. These duty-ratios at the corresponding voltages define the higher limit curves for the maximum duty-cycle reduction circuit. This curve should be below the DRESET curve. DXDOMAX = 0.79 (DXDO MAX, F147) DXLLMAX = 0.67 (DXLL MAX, F151) DXHLMAX = 0.35 (DXHL MAX, F156) To guarantee smooth operation, these 4 curves namely the regulation duty cycle (DACTUAL ) curve, the low-end tolerance part (DMIN) curve, the high-end tolerance part (DMAX ) curve and the core reset (DRESET) curve should never intersect each other. This guarantees that the power supply will not drop out of regulation and also ensures that there will be no transformer saturation. In the EP-12 example, the parameter DXDOMAX exceeds parameter DMAXRESET. This could POSSIBLY cause transformer saturation ONLY during load transients or during shut down of the converter, which is NOT hazardous. Regulating duty-ratio parameters: DMAXACTUAL, DLLACTUAL, DHLACTUAL Referring to Figure 8, these three parameters correspond to the operating duty-ratio at dropout, low line input and high line input respectively. DMAXACTUAL = 0.69 (DMAX ACTUAL, F144) DLLACTUAL = 0.40 (DLL ACTUAL, F149) DHLACTUAL = 0.23 (DHL ACTUAL, F154) 30 B 12/02 AN-30 Step (n)-Step (p). Calculation of RMS Ripple currents in output capacitors, parameters for the coupled inductor and stresses on the rectifier diodes. Calculations of RMS Ripple currents in output capacitors: IRMS MAIN , IRMS MAINMA, IRMS AUX1 The RMS currents in the output capacitors, for each individual output is calculated by the spreadsheet. The values for EP-12 supply are as follows: IRMS MAIN = 0.52 A (IRMSMAIN, F108) IRMS MAINMA = 0.52 A (IRMSMAINMA, F109) IRMS AUX1 = 0.17 A (IRMSAUX1, F110) For the auxiliary output this ripple current calculation is only an estimate. This value varies with the coupling co-efficient, parasitic voltage drops and other quantities which are difficult to predict. Choose output capacitors to meet the above ripple current requirements. Parameters for the coupled output inductor, and mag-amp inductance: LMAIN , LMAINMA The turn's-ratio for the coupled choke is the same as that of the transformer. NLMAIN 3 = 4 N LAUX The inductor is computed by the spreadsheet L MAIN = 10.1 µH (LMAIN, F68) An inductor value of 10.2 µH was tried in the EP-12 design. Bench evaluation of the prototype for fine adjustment led to satisfactory performance with this value for the inductor. The mag-amp inductance is calculated by spreadsheet. This is calculated as 12.4 µH . LMAINMA = 12.4 µH (LMAINMA, B90) First select the closest standard value. If performance is not satisfactory, a more accurate inductor should be wound. For the EP-12 design a standard 15 µH inductor was found to be satisfactory. PIV stress on Rectifier diodes: VPIVMAIN, VPIVMAINMA, VPIVAUX1, VPIVB The spreadsheet calculates the peak inverse voltage that is imposed on the rectifier diodes. Main output rectifier peak inverse voltage = 29.5 V (VPIVMAIN, F114) MagAmp output rectifier peak inverse voltage = 29.5 V (VPIVMAINMA, F115) Auxiliary output rectifier peak inverse voltage = 34.9 V (VPIVAUX1, F116) Bias winding output rectifier peak inverse voltage = 102.1 V (VPIVB, F118) Choose rectifier diodes with PIV ratings typically 120% of the ratings calculated above. B 12/02 31 AN-30 Optional Under-Voltage Lockout Circuit: RUVA, RUVB , RUVC The external under-voltage lockout circuit is shown in Figure 9. The circuit sets the minimum input voltage that should be present before the TOPSwitch-GX is enabled. The circuit also sets the voltage at which the converter is shut off during power down. Step (q). Selection of RUVA RUVB & RUVC: Under worst-case input voltage conditions power dissipation in RUVA must not exceed 150 mW. The spreadsheet calculates the value of this resistor. In EP-12 this resistor is: RUVA = 2.23 MΩ (RUVA, F126) Choose closest standard value; RUVA = 2.2 MΩ, 0.5 W Choose VACUVL and VACUV and select RUVB & RUVC: Choose a value for VACUVL and VACUV such that VACUVL <VACUVX <VACUV where VACUVX is the voltage at which the external under-voltage lockout circuit enables the TOPSwitch-GX during start-up. This value is automatically calculated by the spreadsheet. Set the voltage at which the converter shuts off with the external UVLO circuit, VACUVL = 67 V. Enter the voltage at which the converter should begin its steady state operation VACUV = 80 V. This means that the voltage at which the external UVLO circuit enables the TOPSwitch-GX while the input voltage is rising, VACUVX must lie within the limits 67 V <VACUVX < 80 V. The spreadsheet returns a value for voltages VACUVX and VACUVL. Check that these values are within acceptable limits. The spreadsheet returns the following values for resistors RUVB & RUVC. RUVB = 523.73 kΩ RUVC = 75.91 kΩ (RUVB, F127) (RUVC, F128) If the calculated value of the resistors is unavailable, use closest available standard values. Back calculate for VACTUAL and VACUVX and check that they are within acceptable limits. For EP-12 the values of resistors are as follows RUVB = 560 kΩ RUVC = 75 kΩ Back calculating to check for VACUVL and VACUVX we have VACUVL = 67.5 V VACUVX = 70.36 V both within reasonable limits. 32 B 12/02 (VACUVL ACTUAL, F130) (VACUVX ACTUAL, F131) AN-30 Circuit for Reduction of Maximum Duty Ratio Figure C1 shows the external circuit for limiting the maximum duty cycle of the TOPSwitch-GX. From DC Bus RA RB RC RD TOPSwitch-GX L-Pin VZ 6.8 V Bias Winding CVS TOPSwitch-GX SOURCE -Pin PI-2888-061302 Figure C1: Components that make up external duty-ratio limiting circuit. Step (r). Selection of duty-cycle limiting circuit components: RA, RB, RC, RD, VZ, CVS Selection of RA, RB These resistors provide L pin current that is proportional to the input voltage. The calculation formula for these resistors is as in Equation (35) of AN-30. RA = RB = 2.25 MΩ. Selecting closest standard values: Select RA = 2.26 MΩ, 0.5 W (RA, F137) Select RB = 2.26 MΩ, 0.5 W (RB, F138) Selection of Zener: VZ The Zener diode increases the dynamic range of operation by allowing the low line duty-ratio to be a higher value, while still avoiding saturation. The Zener diode should be used only in designs that operate over a very wide range of duty-cycle. Whenever needed, a 4 V-9 V Zener diode should be used. In EP-12 this value is set at 6.8 V, as this is the maximum value of the Zener that avoids core saturation at low line, while allowing extended operating range. Choose any standard low power (500 mW) Zener diode. Choose 6.8 V Zener diode BZX79-C6V8, VZ = 6.8 V (VZ F134) Selection of Duty-Ratio limits: DXDO , DXHL Note that the spreadsheet takes default inputs corresponding to DXDO and DXHL. These values are based on the low-end parts. It can be seen by looking at the curves for core saturation (DRESET) and the operating duty cycle (D), that the attempt here is to place the maximum limiting duty-ratio (DMAX) curve approximately mid-way these two limit curves. Figure C2 shows an example curve taken from the design spreadsheet where the DRESET limit is violated. Figure C3 shows an example where the regulation limit, DACTUAL is violated. Selection of Overvoltage onset level VOV This determines the voltage at which frequency reduction commences. In EP-12 the default value was used. VOV = 380 (VOV, F135) B 12/02 33 AN-30 DUTY CYCLE PARAMETERS (see graph) DMAX ACTUAL DMAX RESET DXDO MIN DXDO MAX 0.67 0.79 0.68 0.78 DLL ACTUAL DXLL MIN DXLL MAX DLL RESET 0.46 0.52 0.64 0.69 DHL ACTUAL DXHL MIN DXHL MAX DHL RESET Warning Duty cycle at minimum DC Bus voltage Duty cycle minimum limit at minimum DC Bus voltage Duty cycle maximum limit at minimum DC Bus voltage Minimum duty cycle to reset transformer at low line High Line Duty-Cycle Parameters Duty cycle at minimum DC Bus voltage !!! < 103% of operating duty cycle at max DC Bus voltage: increase DXHL MIN, decre Duty cycle maximum limit at maximum DC Bus voltage Minimum duty cycle to reset transformer at high line Duty Cycle vs DC Bus Voltage 0.8 0.9 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0.0 100 DX MAX exceeds D RESET which means transformer saturation may occur at this point 0.8 PI-2892-121302 0.9 V DROPOUT V OV D RESET DX MAX DX MIN D ACTUAL 0 100 150 150 200 200250 300250350 400300450 350 400 DC Bus Voltage, V DC Bus Voltage, V D_ACTUAL Figure C2. Example of DRESET Limit Violation. 34 0.23 0.13 0.24 0.36 Dropout Duty-Cycle Parameters Operating Duty cycle at DC Bus dropout voltage Transformer Reset Minimum duty cycle at DC Bus dropout voltage Device Min Duty cycle limit at DC Bus dropout voltage Device Max Duty cycle limit at DC Bus dropout voltage Duty Cycle vs. DC Bus Voltage Duty Cycle 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 B 12/02 D_RESET DX_MIN DX_MAX V_OV V_DROPOUT 450 AN-30 DUTY CYCLE PARAMETERS (see graph) DMAX ACTUAL DMAX RESET DXDO MIN DXDO MAX 0.67 0.79 0.69 0.78 DLL ACTUAL DXLL MIN DXLL MAX DLL RESET 0.46 0.56 0.66 0.69 DHL ACTUAL DXHL MIN DXHL MAX DHL RESET 0.23 0.30 0.39 0.36 Warning Dropout Duty-Cycle Parameters Operating Duty cycle at DC Bus dropout voltage Transformer Reset Minimum duty cycle at DC Bus dropout voltage Device Min Duty cycle limit at DC Bus dropout voltage Device Max Duty cycle limit at DC Bus dropout voltage Duty cycle at minimum DC Bus voltage Duty cycle minimum limit at minimum DC Bus voltage Duty cycle maximum limit at minimum DC Bus voltage Minimum duty cycle to reset transformer at low line High Line Duty-Cycle Parameters Duty cycle at minimum DC Bus voltage Duty cycle minimum limit at maximum DC Bus voltage !!! > reset duty cycle at VMAX : decrease DXHL MAX, increase VDSOP Minimum duty cycle to reset transformer at high line Duty Cycle vs DC Bus Voltage Duty Cycle vs. DC Bus Voltage 0.9 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 D ACTUAL exceeds DX MIN curve - hence low tolerance device will cause supply to drop out of regulation 0.8 PI-2891-121302 0.9 Duty Cycle 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 V DROPOUT V OV D RESET DX MAX DX MIN D ACTUAL 0.2 0.1 0.1 0.0 100 0 100 150 150 200 200 250 300 250350 400300450 350 400 450 DC Bus DC Bus Voltage, V Voltage, V D_ACTUAL D_RESET DX_MIN DX_MAX V_OV V_DROPOUT Figure C3. Example of DACTUAL (Regulation) Limit Violation. B 12/02 35 AN-30 Selection of RC The value of RC is calculated by the spreadsheet. In EP-12 this value is calculated as: RC = 40.26 kΩ (RC, F139) Choose closest standard available value, RC = 43.2 kΩ, 0.125 W Selection of RD The value of RD is automatically calculated by the spreadsheet. In EP-12 this value is calculated as: RD = 126.70 kΩ (RD, F143) Choose closest standard available value, RD = 130 kΩ, 0.125 W Selection of Capacitor CVS The capacitor CVS is also estimated by the spreadsheet. For EP-12, the value from the equation is approximately 93 pF. If the calculated value is unavailable choose next higher standard available value. Choose CVS = 100 pF, 100 V (CVS, F141) 36 B 12/02 AN-30 Spreadsheet A 1 B D F G INPUT INFO OUTPUT UNIT ACDC_TOPGXForward_Rev_1.03_061802 Copyright Power Integrations Inc. 2002 2 OUTPUT VOLTAGE AND CURRENT 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 VMAIN IMAIN VMAINMA IMAINMA VAUX1 IAUX1 VIND1 IND1 PO 5 12 3.3 12 12 4 Volts Amps Volts Amps Volts Amps Volts Amps 147.6 Watts I ACDC_TOPGXFwd_061802_r103.xls: TOPSwitch-GX Forward Transformer Design Spreadsheet EP12 PC Main power supply Main output voltage Main output current Magamp output voltage Magamp output current Auxiliary output voltage Auxiliary output current Independant output voltage Independent output current Total output power ENTER APPLICATION VARIABLES VACMIN VACMAX VMIN VMAX CIN fL tc th EFF VHOLDUP VDROPOUT DMAX GOAL VDSOP KDI REF AUX1 90 132 AC volts AC volts 188 Volts 373 Volts uFarads Hz mSeconds mSeconds 165 50 3.0 16.0 0.75 188 Volts 132 Volts 0.70 580 Volts 0.15 DC Stack 132 0.7 1 Minimum AC input voltage. Input voltage doubler circuit is assumed. Maximum AC input voltage. Input voltage doubler circuit is assumed. Minimum DC Bus voltage at low line input Maximum DC Bus voltage at high line input Equivalent bulk input capacitance. Input voltage doubler circuit is assumed. Input AC line frequency Estimate input bridge diode conduction time Minimum required hold-up time from VDROPOUT to VHOLDUP Efficiency estimate to determine minimum DC Bus voltage DC Bus voltage at start of hold-up time (default VMIN) DC Bus Voltage at end of hold-up time Maximum duty cycle at DC dropout voltage Maximum operating drain voltage Maximum output current ripple factor at maximum DC Bus voltage Enter one ('1') for DC stacked , zero ('0') Independent winding ENTER TOPSWITCH VARIABLES TOPSwitch Chosen Device ILIMIT fS KI RX ILIMITEXT VDS top247 TOP247 3.348 124000 0.81 3.852 132000 Universal Power Out Amps Hertz 7.78 kOhm 2.712 Amps 8.1 Volts Doubled 115V/230V 165W From TOPSwitch-GX datasheet From TOPSwitch-GX+H76 datasheet Ilimit reduction (KI=1.0 for default ILIMIT, KI <1.0 for lower ILIMIT) Maximum current limit resistance to ensure KI >= 0.81 setting External current limit TOPSwitch-GX average on-state Drain to Source Voltage DIODE Vf SELECTION VDMAIN VDMAINMA VDAUX1 VDIND1 VDB 0.5 0.5 0.7 0 0.7 Volts Volts Volts Volts Volts Main output rectifiers forward voltage drop (Schottky) Magamp output rectifiers forward voltage drop (Schottky) Auxiliary output rectifiers forward voltage drop (Ultrafast) Independent output rectifiers forward voltage drop (Schottky) Bias output rectifier conduction drop BRIDGE RECTIFIER DIODE SELECTION VPIVAC IDAVBR 467 Volts 0.773 Amps Maximum voltage across Bridge rectifier diode Average Bridge Rectifier Current TRANSFORMER CORE SELECTION Core Type Core Bobbin AE LE AL BW LG MAX R FACTOR M L NMAIN eer28l EER28L EER28L_BO 9% 3.0 0.80 0.814 7.55 2520 21.8 0.02 9% P/N: P/N: cm^2 cm nH/T^2 mm mm % mm 3 PC40EER28L-Z BEER-28L-1112CPH Core Effective Cross Sectional Area Core Effective Path Length Ungapped Core Effective Inductance Bobbin Physical Winding Width Maximum actual gap when zero gap specified Percentage of total PS losses lost in transformer windings; default 10% Transformer margin Transformer primary layers Main rounded turns TRANSFORMER DESIGN PARAMETERS NP NB NAUX1 VAUX1 ACTUAL NIND1 VIND1 ACTUAL BM BP LP MIN IMAG 45 45 6 4 11.63 Volts 0 0.00 Volts Primary rounded turns Bias turns to maintain 8V minimum input voltage, light load Auxiliary rounded turns (DC stacked on Main winding) Approx. Aux output voltage with NAUX1 = 4 Turns and DC stack Independent rounded turns (separate winding) Approximate Independent output voltage with NIND1 = 0 turns 1816 2884 3.419 0.189 Maximum operating flux density at minimum switching frequency Maximum peak flux density at minimum switching frequency Minimum primary magnetizing inductance (assumes LGMAX=20um) Peak magnetizing current at minimum input voltage Gauss Gauss mHenries Amps B 12/02 37 AN-30 A 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 38 B D OD_P AWG_P F G 0.33 mm 28 AWG I Primary wire outer diameter Primary Wire Gauge (rounded to maximum AWG value) CURRENT WAVESHAPE PARAMETERS IP IPRMS 2.451 Amps 1.460 Amps Maximum peak primary current at maximum DC Bus voltage Maximum primary RMS current at minimum DC Bus voltage LMAIN WLMAIN KDIMAIN 10.0 uHenries 2286 uJoules 0.150 Main / Auxiliary coupled output inductance (referred to Main winding) Main / Auxiliary coupled output inductor full-load stored energy Current ripple factor of combined Main and Aux1 outputs LMAINMA WLMAINMA KDIMAINMA 12.3 uHenries 888 uJoules 0.150 Magamp output inductance Magamp output inductor full-load stored energy Current ripple factor for Magamp output LIND1 WLIND1 KDIIND1 0.0 uHenries 0.0 uJoules 0.000 Independent output inductance Independent output inductor full-load stored energy Current ripple factor for Independent output 15.61 Amps 2.42 Amps 0.00 Amps Maximum transformer secondary RMS current (DC Stack) Maximum transformer secondary RMS current (DC Stack) Maximum transformer secondary RMS current INDUCTOR OUTPUT PARAMETERS SECONDARY OUTPUT PARAMETERS ISMAINRMSLL ISAUX1RMSLL ISIND1RMSDLL IDAVMAIN IDAVMAINMA IDAVAUX1 IDAVIND1 12.3 9.3 3.1 0.0 Amps Amps Amps Amps Maximum average current, Main rectifier (single device rating) Maximum average current, Magamp rectifier (single device rating) Maximum average current, Auxiliary rectifier (single device rating) Maximum average current, Independent rectifier (single device rating) IRMSMAIN IRMSMAINMA IRMSAUX1 IRMSIND1 0.52 0.52 0.17 0.00 Amps Amps Amps Amps Maximum RMS current, Main output capacitor Maximum RMS current, Magamp output capacitor Maximum RMS current, Auxiliary output capacitor Maximum RMS current, Independent output capacitor 29.5 29.5 34.9 0.0 102.1 Volts Volts Volts Volts Volts DIODE PIV VPIVMAIN VPIVMAINMA VPIVAUX1 VPIVIND1 VPIVB VCEO OPTO 49.8 Volts No derating Main output rectifiers peak-inverse voltage Magamp output rectifiers peak-inverse voltage Auxiliary output rectifiers peak-inverse voltage Independent output rectifiers peak-inverse voltage Bias output rectifier peak-inverse voltage Optocoupler Maximum optocoupler collector-emitter voltage UNDER-VOLTAGE LOCKOUT CIRCUIT PARAMETERS VACUVL VACUV VACUVX RUVA RUVB RUVC 68 78 68 2.23 523.73 75.91 VACUVL ACTUAL VACUVX ACTUAL AC volts AC volts AC undervoltage lockout voltage; On-Off transition AC undervoltage lockout voltage; Off-On transition MOhm kOhm kOhm Resistor RUVA value Resistor RUVB value Resistor RUVC value 67.50 AC volts 70.36 AC volts Actual AC undervoltage lockout voltage; On-Off transition Actual AC undervoltage lockout voltage; Off-On transition DUTY CYCLE LIMIT CIRCUIT PARAMETERS VZ VOV 6.80 Volts 380 Volts RA RB RC RD CVS 2.20 2.20 40.26 126.70 92.98 DUTY CYCLE PARAMETERS (see graph) DMAX ACTUAL DMAX RESET DXDO MIN DXDO MAX Caution 0.69 0.79 0.70 0.79 DLL ACTUAL DXLL MIN DXLL MAX DLL RESET 0.47 0.55 0.67 0.69 DHL ACTUAL DXHL MIN DXHL MAX DHL RESET 0.23 0.24 0.35 0.36 B 12/02 MOhm MOhm kOhm kOhm pF Zener voltage used within DLIM circuit Approximate frequency reduction voltage (determines CVS value) Resistor RA value Resistor RB value Resistor RC value Resistor RD value Capacitor CVS value Dropout Duty-Cycle Parameters Operating Duty cycle at DC Bus dropout voltage Transformer Reset Minimum duty cycle at DC Bus dropout voltage Device Min Duty cycle limit at DC Bus dropout voltage !!! >DMAXRESET from VMIN to VDROPOUT. NOT hazardous Duty cycle at minimum DC Bus voltage Duty cycle minimum limit at minimum DC Bus voltage Duty cycle maximum limit at minimum DC Bus voltage Minimum duty cycle to reset transformer at low line High Line Duty-Cycle Parameters Duty cycle at minimum DC Bus voltage Duty cycle minimum limit at maximum DC Bus voltage Duty cycle maximum limit at maximum DC Bus voltage Minimum duty cycle to reset transformer at high line AN-30 A B D F G I 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.5 PI-2890-121302 Duty Cycle vs DC Bus Voltage Duty Cycle vs. DC Bus Voltage Duty Cycle 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 0.6 0.5 0.4 V DROPOUT V OV D RESET DX MAX DX MIN D ACTUAL 0.4 0.3 0.2 0.1 0.3 0.2 0.1 0.0 100 0 150 200 250 300 350 400 450 DC Bus V 100 150 200 250 300 350 Voltage, 400 450 DC Bus Voltage, V D_ACTUAL D_RESET DX_MIN DX_MAX V_OV V_DROPOUT B 12/02 39 AN-30 For the latest updates, visit our Web site: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. The products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations' patents may be found at www.powerint.com. The PI Logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power Integrations, Inc. PI Expert is a trademark of Power Integrations, Inc. ©Copyright 2002, Power Integrations, Inc. WORLD HEADQUARTERS AMERICAS Power Integrations, Inc. 5245 Hellyer Avenue San Jose, CA 95138 USA Main: +1 408-414-9200 Customer Service: Phone: +1 408-414-9665 Fax: +1 408-414-9765 e-mail: [email protected] EUROPE & AFRICA Power Integrations (Europe) Ltd. Centennial Court Easthampstead Road Bracknell Berkshire, RG12 1YQ United Kingdom Phone: +44-1344-462-300 Fax: +44-1344-311-732 e-mail: [email protected] SINGAPORE Power Integrations, Singapore 51 Goldhill Plaza #16-05 Republic of Singapore 308900 Phone: +65-6358-2160 Fax: +65-6358-2015 e-mail: [email protected] TAIWAN Power Integrations International Holdings, Inc. 17F-3, No. 510 Chung Hsiao E. Rdl, Sec. 5, Taipei, Taiwan 110, R.O.C. Phone: +886-2-2727-1221 Fax: +886-2-2727-1223 e-mail: [email protected] CHINA Power Integrations International Holdings, Inc. Rm# 1705, Bao Hua Bldg. 1016 Hua Qiang Bei Lu Shenzhen Guangdong, 518031 China Phone: +86-755-8367-5143 Fax: +86-755-8377-9610 e-mail: [email protected] KOREA Power Integrations International Holdings, Inc. Rm# 402, Handuk Building 649-4 Yeoksam-Dong, Kangnam-Gu, Seoul, Korea Phone: +82-2-782-2840 Fax: +82-2-782-4427 e-mail: [email protected] JAPAN Power Integrations, K.K. Keihin-Tatemono 1st Bldg. 12-20 Shin-Yokohama 2-Chome Kohoku-ku, Yokohama-shi, Kanagawa 222-0033, Japan Phone: +81-45-471-1021 Fax: +81-45-471-3717 e-mail: [email protected] INDIA (Technical Support) Innovatech #1, 8th Main Road Vasanthnagar Bangalore, India 560052 Phone: +91-80-226-6023 Fax: +91-80-228-9727 e-mail: [email protected] APPLICATIONS HOTLINE World Wide +1-408-414-9660 APPLICATIONS FAX World Wide +1-408-414-9760 40 B 12/02