text:
Redundant read bus for correcting defective columns in a cache memory
A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.
Latest IBM Patents:
- Dynamically subscribing to management information and method and system for dispensing thereof
- Personalized video interjections based on learner model and learning objective
- Method and system for rateless and pollution-attack-resilient network coding
- Enhanced substrate includes a carbene-coated metal foil laminated to a substrate that includes glass fiber impregnated with a base polymer
- Support system for cellular based resource sharing service
The present invention relates generally to memory circuits and, more particularly, to the implementation of column (or bit line) redundancy in a cache memory architecture.BACKGROUND OF THE INVENTION
In high density Static Random Access Memories (SRAMs), redundancy is widely used to improve fabrication yield. Redundancy basically involves adding extra word lines and/or extra bit lines to at least one memory sub-array.
As known by those skilled in the art, a memory array includes a plurality of K sub-arrays, each including N pairs of bit lines arranged in columns with memory cells connected therebetween. In a 1-bit wide organization (i.e. 1 output data available), a 1 bit common read bus passes through the whole memory array and the different sense amplifiers are dotted all together thereon. In this case, the bit line or column redundancy is easily implemented by adding a spare sub-array and dotting the redundant sense amplifiers on the common read bus. For instance, if up to 2 defective columns have to be corrected in one memory sub-array, 2 redundant columns have to be added in the spare sub-array. FIG. 1 illustrates this prior art approach.
As shown in FIG. 1, a conventional 1-bit wide memory circuit architecture 10 includes memory sub-array 11-0, which is represented in a typical bit wide organization, wherein the number N of columns is 64. A row of memory cells of sub-array 11-0 is activated for a READ operation by applying an appropriate voltage level on the word line (e.g. WL1), and simultaneously, only one pair of bit lines (e.g. BLT1, BLC1), forming one column over 64, is selected by applying a selection signal (e.g. BD-1) on the corresponding column sense amplifier 12 (e.g. 12-1).
The binary content of the selected memory cell (e.g. MC11) is then read, i.e. the differential voltage appearing between the bit lines is sensed by the corresponding column sense amplifier. Note that the column sense amplifiers of the memory sub-array 11-0 will be referred to below as the normal sense amplifiers. Note also that the WRITE circuitry has not been shown or represented for sake of simplicity. Selection signals BD-1 to BD-64 include bit line (1/64) and memory sub-array (l/K) decode information as known by those skilled in the art. All the output terminals of normal sense amplifiers 12-1 to 12-64 are dotted to a 1-bit common read bus 13. Assuming the sense amplifiers are of the differential type, the common read bus 13 comprises two wires, for the true and complement output signals, as illustrated in FIG. 1. If the sense amplifiers were of the single ended type, only one wire would have been required. A final common sense amplifier and off-chip driver block 14 is connected to the common read bus 13 to generate the 1-bit final output data.
Redundancy is made apparent from FIG. 1 by the presence of a spare sub-array 11'-0 comprised of N'=2 redundant cell columns that are connected in a standard manner to two redundant sense amplifiers 12'-1 and 12'-2 specifically dedicated to redundancy and controlled by selection signals RE-1 and RE-2. The outputs of these redundant sense amplifiers are dotted to the common read bus 13. As a result, all single (or double) failed cell column in memory sub-array 11-0 can be repaired, by substituting one (or two) redundant cell columns to the failed one(s). However, care must be exercised, because normal data and redundant data, respectively generated by the normal and redundant sense amplifiers, are output on the same common bus 13. As a matter of fact, once redundant data must be selected, the normal sense amplifiers of the defective memory cell column must be disabled in order not to mix the respective electrical signals on the common read bus 13. The switching operation between the normal and redundant sense amplifiers is realized by means of the bit (or column) decoding circuitry and also by means of a failed bit address detector or bit address comparator. The bit decoding circuitry is implemented with known multi-layer decoding techniques. A memory chip having no redundant cells is distinct in that one of these decoding layers can be inhibited by a signal which is provided by the bit address comparator. The latter recognizes the occurrence of a failed address previously tested and stored as explained below in a ROM using laser blown fuse techniques. The failed address is programmed (or written) with the help of an on-chip fuse for each address bit weight. Whether or not this fuse is blown depends on the binary identification of a given bit address which may be tested and recognized to exhibit a fail symptom. When all column address bits match with the programmed failed bits, the compare function (XOR function) is done in parallel on each bit and, in that case, a selection signal is generated and referred to as the RE (Redundancy Enable) signal to enable the appropriate redundant sense amplifier, and the corresponding BD signal is disabled.
The byte-wide organization is directly derived from the 1-bit wide organization. In a byte-wide organization, eight output data bits (i.e. a byte) instead of one are generated. Thus, a 8-bit common read bus passes through the whole memory array. The normal sense amplifiers are dotted on this common read bus with respect to their respective bit weight. If a fail occurs in one column of the memory array, that means one bit failed in a byte. The immediate solution (and the easiest from a circuitry point of view) would be to replace the defective byte by a redundant byte. Consequently, to be able to correct two defective columns in the memory sub-array, sixteen redundant columns are then required in the spare array. Such a byte-wide memory circuit architecture is illustrated in FIG. 2, and referred to generally by reference numeral 15.
Referring to FIG. 2, memory sub-array 16-0 is comprised of N=64 columns organized in eight blocks of eight memory cell columns each. A bit of a special weight corresponds to each block. The number of blocks M is determined by the length of the binary word that is selected to organize sub-array 16-0. In the instant case of a byte-wide organization, the word is comprised of eight bits, i.e. M=8. The number of memory cell columns per block, in this instance, eight, is purely illustrative. This number is related to the number of selection signals, and thus to the number of bytes stored in sub-array 16-0. The first eight normal sense amplifiers 17-1 to 17-8 of the differential type, are connected to the first eight memory cell columns of sub-array 16-0 and the outputs are dotted to the first sub-bus 18-0, which is comprised of two wires. These correspond to the first bit (bit 0 or LSB) of the byte to be output. Similar construction applies to other cell column blocks. To output one byte over eight of the memory sub-array, the normal sense amplifiers 17-1 to 17-8 are adequately selected by a selection signal BD-1 to BD-8 for each bit weight. As a result, the common read bus 18 comprises eight 2-wire sub-busses referenced 18-0 to 18-7 to generate the output byte in totality, whose bits are referred to as bit 0 (LSB) to bit 7 (MSB) in FIG. 2. To each sub-bus, e.g. 18-0, corresponds a final sense amplifier connected in series with a buffer to form an element, e.g. 19-0, of a block generically referenced with reference numeral 19. The full output byte is available at the output terminals of the eight elements 19-0 to 19-7.
In this instance, the spare sub-array 16'-0 is now comprised of 2.times.8=16 columns to be able to still correct two defective columns in memory sub-array 16-0. Spare array 16'-0 therefore comprises sixteen redundant sense amplifiers 17'-1 to 17'-16 that are dotted, two by two, on each of the eight sub-busses 18-0 to 18-7. The redundant sense amplifiers are controlled by two selection signals RE-1 and RE-2 to select up to two redundant bytes stored in the spare sub-array 16'-0 to be output by block 19. Note that, if binary words of 64 bits instead of 8 bits were used, this would mean that the spare sub-array 16'-0 should include 2.times.64=128 redundant columns.
The above problem of redundancy is even more acute in cache memories. The large performance gap between the central processing unit (CPU) and the main memory has made the use of cache memories an important factor for any present and future high performance processor. In cache memory architectures, the 4-way and 8-way set associative cache organizations are the most extensively used to date in order to meet the high speed objectives of the mainframe manufacturers. In the 4-way set associative cache organization, which is the standard to date, 4 data sets (bit, byte, . . . ) have to be generated by each memory sub-array and one over 4 of these data sets will be subsequently selected through the so-called late select signals LS0 and LS1. In the meantime, this provides a means of initiating additional logical functions (e.g. address translation) in parallel and then to decide later in the system cycle which data set is correct and must be used by the CPU. For example, assuming the data set format is the byte, 4 bytes have to be available at the same time and the final selection is done through a 1/4 multiplexer circuit controlled by four control signals derived from the two late select signals via a decoder circuit. Note that, in regard to the other address signals, these two late select signals are valid later in the cycle. As a result, a 32 bit common read bus now has to be used. If 2 defective columns still need to be corrected with the conventional byte-wide organization of FIG. 2, the number of spare cell columns will increase up to 32.times.2=64, as will now be explained in more detail in conjunction with FIG. 3.
Referring now to FIG. 3, a conventional byte-wide circuit architecture of a 4-way associative cache memory with embedded column redundancy is referred to generally by reference numeral 20. Memory sub-array 21-0 is comprised of N=64 memory cell columns sub-divided in M=8 blocks, which are connected to 64 normal sense amplifiers 22-1 to 22-64. The selection signals are referenced as SEL-1 and SEL-2. With this architecture, four memory data read busses 23-0 to 23-3, each comprised of eight 2-wire sub-busses are required to convey the four byte format data sets: SET0 to SET3. As a result, 32 bits out of 64 are output from sub-array 21-0, depending upon the selection made by selection signals SEL-1 and SEL-2. Still referring to FIG. 3, the two first normal sense amplifiers 22-1 and 22-2, of the first memory cell block, are dotted on the LSB0 sub-bus of bus 23-0, and so on up through normal sense amplifiers 22-7 and 22-8, whose outputs are connected to the LSB3 sub-bus of bus 23-3. Similar construction applies to other cell column blocks. All these connections, i.e. four groups 23-0 to 23-3 of eight 2-wire sub-busses, form main read bus 23.
In order to be able to still correct up to 2 defective columns in sub-array 21-0, the spare sub-array 21'-0 necessitates N'=64 columns. The dedicated redundant sense amplifiers are referenced 22'-1 to 22'-64. The two first redundant sense amplifiers 22'-1 and 22'-2 are connected to the LSB0 sub-bus of bus 23-0, and so on up through redundant sense amplifiers 22'-63 and 22'-64, that are connected to the MSB3 sub-bus of bus 23-3. Likewise, the selection signals are referenced RE-1 and RE-2.
The circuitry which will be described below is an example of a conventional design using standard logic circuits that could be implemented to render operative the memory cache circuit architecture of FIG. 3. All four LSB sub-busses LSB0 to LSB3 are connected via bus 24-0 to a 1/4 multiplexer element 25-0, and so on for each bit weight, until the MSBs are reached, as shown in FIG. 3. The eight 1/4 multiplexer elements 25-0 to 25-7 are grouped in multiplexer block 25. The multiplexer block 25 is controlled by a combination of the late select signals LS0 and LS1 via a 1/4 decoder circuit 26. Each one of the eight multiplexer element outputs is connected to a sense amplifier/buffer element 27-0 to 27-7, respectively, whose assembly forms block 27. The selected full byte is available at the output terminals of the elements 27-0 to 27-7. Selection signals SEL-1 and RE-1 are generated by circuit 28-1 comprised of conventional components: a RS flip-flop latch 29, a bit address comparator 30, a 3-way AND gate 31, and an inverter 32. The output of bit address comparator 30 is applied to the SET (S) input of latch 29. Signal BR-1 which is output by latch 29 is applied to one input of the 3-way AND gate 31 and selection signal BD-1 (as defined above with respect to FIGS. 1 and 2) is applied to its other input. The signal which is output by AND gate 31 is referenced SEL-1, while signal RE-1 is derived from signal BR-1 via inverter 32. A symetric circuit 28-2 generates signal BR-2 and selection signals SEL-2 and RE-2. Signal BR-2 is also applied to one input of the 3-way AND gate 31 of circuit 28-1. Similarly, signal BR-1 is applied to the corresponding 3-way AND gate of circuit 28-2. In such 4-way set associative cache SRAMs, wherein the bit addresses are only valid during a short period of time and usually are no longer valid when the late select address bits occur, the role of latch 29 is thus to "memorize" a given logic state when the bit address comparator 30 recognizes a faulty address combination stored therein. As known by those skilled in the art, bit address comparator 30 is fed with the column address bits from the CPU and compared with a table of defective addresses stored in a ROM. With standard memory architectures such as illustrated in FIGS. 1 and 2, latch 29 would not be necessary.
Although described in a 4-way set associative cache memory organization, the architecture of FIG. 3 could be generalized to a P-way set associative cache memory as well, wherein P=8, 16, . . . Note that in this case, the number of read busses and data sets is still equal to P. Finally, FIG. 3 also illustrates other memory sub-arrays, e.g. 21-1 to 21-K, and corresponding optional spare arrays 21'-1 to 21'-K.
Operating behavior of the cache memory architecture of FIG. 3 will now be briefly described. An electrical signal is developed on the 64 bit line pairs or columns corresponding to a given decoded row of the memory sub-array 21-0. 32 normal data out of 64 forming the four data sets SET0 to SET3 are selected by the normal sense amplifiers addressed by the appropriate selection signal i.e. either SEL-1 or SEL-2. The two following cases are to be considered depending upon whether or not redundant replacement is required.
In the first case, at least one selected cell column is defective. This implies that redundancy replacement is required. The bit address comparator 30 detects a match between the bit (or column) address provided to the memory by the CPU and the bit address stored as corresponding to a defective column of memory sub-array 21-0. The normal sense amplifiers corresponding to the 32 data wherein at least one faulty data has been recognized, are disabled by means of the BR signals (because latches 29 in circuits 28-1 and 28-2 are now reset), thereby preventing the corresponding selection signal (SEL-1 or SEL-2) to turn on any of them. Reciprocally, either the RE-1 or RE-2 selection signal is activated in order to turn on one of the groups of 32 redundant sense amplifiers to output 32 valid data. The reading of sub-array 21'-0 is achieved in the same way as for the reading of the memory sub-array 21-0. Finally, the LS0 and LS1 signals are delivered to the multiplexer elements 25-0 to 25-7, via decoder circuit 26, to select 8 data out of 32 to output the final byte.
In the second case, the selected cell columns in the memory sub-array 21-0 are free from any defect, and thus there is no need for redundancy replacement. Signal BD-1 (or BD-2) is not inhibited by the bit redundancy BR signal, because latch 29 has not been set. Next, 8 data out of 32, i.e. one data set among SET0 to SET3, are selected by means of the eight 1/4 multiplexer elements 25-0 to 25-7 driven by the 4 decoded LS0/LS1 signals to output the desired final 8 data. It must be noticed that with the implementation shown in FIG. 3, the redundant sense amplifiers are connected to the read busses 23-0 to 23-3. Therefore, they must be isolated therefrom when there is no defective columns in sub-array 21-0. This isolation is made through signals RE-1 and RE-2, which are forced to zero. Indeed, circuits 28-1 and 28-2 generate adequate RE-1 and RE-2 signals so that the two groups of 32 odd and even redundant sense amplifiers: 22'-1 to 22'-63 on the one hand, and 22'-2 to 22'-64 on the other hand, are inhibited.
The above implementation of column redundancy in a cache memory as described in conjunction with FIG. 3 exhibits some deficiencies.
A major inconvenience is the size of the spare array which increases from 16 (FIG. 2) to 64 columns (FIG. 3) in a 4-way set associative cache implementation. As a consequence, in that instance, the size of the spare array 21'-0 is the same as that of the memory sub-array 21-0.
Moreover, the number of redundant columns is dependent on the number of the late select signals. A 4-way set associative cache memory requires two LS address signals: LS0 and LS1 and thus four decoded LS address signals are generated at the output of decoder 26. Should P=8, i.e. a 8-way implementation adopted, this would imply three LS address signals and thus eight decoded LS address signals instead of four, the number N of cell columns in the spare array 21'-0 would then increase to 128. In all respects, the solution of FIG. 3 would become rapidly prohibitive from a consumed silicon area point of view and in terms of circuit complexity.
In addition, the decision to use the redundant or the normal 32 data depends on the content of an address whose 2 bits are the late select bits, that are determined only late in the system cycle. As explained above in conjunction with the first case, if redundancy is required, it is necessary to activate the redundant sense amplifiers, then to drive the multiplexer elements before the selected byte (normal or redundant) is output. Therefore, as the late select access time must be very short, it becomes more and more difficult to implement the column redundancy in cache memories without adding extra delay.
For the reasons outlined above, heretofore, there has been no known cache memory, which efficiently implements column redundancy. Consequently, only word line redundancy has been widely used so far in standard cache memory architecture.OBJECTS OF THE INVENTION
Therefore, it is a primary object of the present invention to provide an efficient implementation of column redundancy in a cache memory architecture.
It is still another object of the present invention to provide column redundancy in a cache memory architecture whose operation is independent of the number of late select signals.
It is further another object of the present invention to provide implementation of column redundancy in a cache memory architecture whose spare array size is only determined by the number of defective cell columns to be replaced in the memory sub-array.
It is another object of the present invention to provide implementation of column redundancy in a cache memory architecture that is able to generate the redundant byte without extra delay.SUMMARY OF THE INVENTION
Generally, the present invention relates to efficiently implementing column redundancy in a cache memory architecture to reach high speed performance.
The invention basically involves the use of a separate redundant read bus fully dedicated to redundancy, fed by a single spare sub-array which is common to all the memory sub-arrays of the cache memory. As a result, the redundant sense amplifiers are no longer dotted with the normal sense amplifiers on a common read bus. The redundant sense amplifiers are dotted to the redundant read bus and the normal sense amplifiers are connected to a main read bus comprised of 4 read busses in the case of a 4-way set associative cache memory organization. Consequently, both the normal and redundant 32 data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers, i.e., on the main and redundant read busses respectively. When the two late select address signals LS0 and LS1 become valid, then the correct information, i.e. the correct 8 data among the 32 to be output, can be immediately selected via a 1/4 multiplexer provided with an INHIBIT (INH) input. The multiplexer is normally controlled by the four decoded signals (derived from the two late select address signals) generated by a decoder, unless redundancy is required. In this case, the information generated by the bit address comparator and stored in a latch, combined with the information generated by a late select address comparator, forces the multiplexer via the INHIBIT input, to select the redundant read bus instead of one read bus of the main read bus, to output the redundant byte as the selected one.
With this implementation, the number of redundant cell columns do not increase with the number of late select address signals that are used.
It is preferable to use a very high speed late select address comparator circuit to improve the overall access time, because this circuit intervenes in the critical path of the cache memory architecture and because the final fetch decision is done later in the cycle. To that end, an appropriate high speed LS address comparator circuit is also described in more detail hereinbelow.BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features, aspects and advantages will be more readily apparent and better understood from the following detailed descripton of the invention, in which:
FIG. 1 shows the prior art implementation of column redundancy in a standard 1-bit wide SRAM memory architecture.
FIG. 2 shows the prior art implementation of column redundancy in a standard byte-wide SRAM memory architecture.
FIG. 3 shows the implementation of FIG. 2 when adapted to fit the specific requirements of a 4-way set associative cache organization.
FIG. 4 (which includes FIG. 4A and FIG. 4B) shows the implementation of column redundancy in a byte-wide 4-way set associative cache memory architecture according to the basic principle of the present invention mainly based on the use of a separate redundant read bus.
FIG. 5 shows the detailed structure of a 1/4 multiplexer with an INHIBIT function that can be used as part of the memory architecture of FIG. 4.
FIG. 6 Shows a high speed BiCMOS late select address comparator that can be used as part of the memory architecture of FIG. 4 for high speed performance.
FIG. 7 illustrates the timing diagram which shows the various signal waveforms at different nodes/terminals of the cache memory architecture of FIG. 4.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring initially to FIG. 4, there is shown an implementation of column redundancy in the 4-way set associative cache memory architecture in accordance with the present invention. The architecture is referred to generally by numeral 33, all N1=64 cell columns of memory sub-array 34-1 are connected via normal sense amplifiers 35-1 to 35-64 to four read busses 36-0 to 36-3 corresponding to the four data sets SET0 to SET3, respectively, in similar manner to that described above in conjunction with FIG. 3. The bundle of read busses 36-0 to 36-3 constitutes the main read bus 36. Likewise, all other memory sub-arrays 34-2 to 34-K are similarly connected to the four read busses. According to the present invention, the memory architecture 33 is provided with a separate redundant read bus 37 and a single spare sub-array 34'-1 that are both common to all memory sub-arrays 34-1 to 34-K. Spare sub- array 34'-1 comprises N'=16 cell columns and is able to replace up to two defective cell columns in any of the memory sub-arrays. The two first redundant sense amplifiers 35'-1 and 35'-2 are connected to the LSB sub-bus referenced LSBR of redundant read bus 37, and so on, two by two, until the two last redundant sense amplifiers 35'-15 and 35'-16, which are dotted to the MSB sub-bus MSBR of bus 37. All LSB sub-busses LSB0 to LSB3 are connected via output bus 38-0 to 1/4 multiplexer element 39-0 having an INHIBIT (INH) input, and so on for each bit weight, until the MSBs are reached. The bundle of output busses 38-0 to 38-7 constitutes the main output read bus 38. In addition to these connections, each sub-bus of the redundant read bus 37, is also connected to its corresponding multiplexer element depending on its bit weight, e.g. sub-bus LSBR is connected (as part of sub-bus 38-0) to multiplexer element 39-0. All the multiplexer elements 39-0 to 39-7 forming multiplexer block 39 are controlled by the four decoded LS address signals generated by decoder circuit 40 and by the INH signal, as will be explained below. Each output of the multiplexer elements 39-0 to 39-7 is connected, via a data out wire OUT 0 to OUT 7 to its corresponding final sense amplifier/buffer element 41-0 to 41-7 which are grouped to form block 41, where the final byte to be output is available. The circuits referenced 28-1 and 28-2, shown and described in conjunction with FIG. 3, are now adapted because of the presence of redundant read bus 37. Unlike circuit 28-1 (28-2) in FIG. 3 which was concerned with the generation of a specific selection signal SEL-1 (SEL-2), the normal sense amplifiers 35-1 to 35-64 are now directly driven by the bit decode signals BD-1 and BD-2. The redundant sense amplifiers are still driven by selection signals RE-1 or RE-2. Logic circuit 42-1 comprises LS address comparator 43 driven by the late select address signals LS0 and LS1, to generate a redundant late select (RLS) signal, bit address comparator 44, RS flip flop latch 45 and 2-way AND gate 46. Structure and function of bit address comparator 44 are similar to the conventional bit address comparator 30 of FIG. 3. The output of bit address comparator 44 is connected to the SET input S of latch 45, whose output is connected to one input of 2-way AND gate 46. Signal RE-1 corresponds to the signal which is output by bit address comparator 44 after inversion in inverter 47. RLS signal which is output by LS address comparator 42 is applied to the other input of AND gate 46. Circuit 42-2 has a similar construction to generate RE-2 and INH-2 signals, which are ORed in 2-way OR gate 48. The signal that is output by the OR gate 48, referred to as INH signal, is applied to the INH input of each of the multiplexer elements of block 39, in addition to the four decoded LS address signals as mentioned above.
With the implementation of FIG. 4, the two redundant bytes of spare sub-array 34'-1 may be substituted for any pair of defective bytes irrespective of the memory sub-array 34-1 to 34-K in which they are located.
Operating behavior of cache memory architecture of FIG. 4 will be described hereinafter. The circuits shown in FIGS. 5 and 6 are described below.
FIG. 5 shows a 1/4 multiplexer element appropriate for FIG. 4 with an INH input, typically element 39-0, which handles the LSB bits. It basically comprises a three-level cascode current switch logic tree, driving two emitter-follower circuits (not shown) to supply the complementary circuit output signals: respectively, the IN PHASE Vout and OUT OF PHASE Vout signals at wires referenced OUT 0. Circuit 39-0 is biased between a first supply voltage, a positive voltage VH=5V, and a second supply voltage, the ground GND. The logic tree comprises bottom, middle and top stages 49A, 49B and 49C dotted at the tree output nodes OUT and OUT. Each current switch comprises a pair of input transistors connected in a differential amplifier configuration. As far as the first pair of LSB bits are concerned, i.e. LSB0 and LSB1, the bottom stage 49A at the first level comprises input transistor TX11 which is driven by signal LS0. At the second level, middle stage 49B comprises input transistors TX21 and TX22 driven by signals LS1 and LS1. Finally, at the third level, top stage 49C comprises four input transistors TX31 to TX34. The bases of transistors TX31 and TX32 are connected to read sub-bus LSB0 and the bases of transistors TX33 and TX34 are connected to read sub-bus LSB1. The common collector of transistors TX31 and TX33 is connected to load RCC1 with output node OUT connected therebetween. The common collector of transistors TX32 and TX34 is connected to load RCC2 with output node OUT connected therebetween. The bottom stage is supplied by a constant current I, determined by a conventional current source comprised of transistor TY1, the base of which is connected to a fixed reference voltage VR (delivered by a reference voltage generator not shown) and resistor REE. The constant current, given by relation I=((VR-VBE(TY1))/REE), flows through either transistors TX11 and TX21 or TX22 and one transistor over four of the third stage. At any stage, the constant current flows through the transistor which receives the highest base voltage. Similar construction and reasoning apply to read sub-busses LSB2 and LSB3, with transistor TX12 in the bottom stage, transistors TX23 and TX24 in the middle stage, and transistors TX35 to TX38 in the top stage. Circuit 39-0 further comprises transistors TX13 in the bottom stage and transistors TX39 and TX40 in the top stage for the INHIBIT function. The base of transistor TX13 is driven by the INH signal; its emitter is dotted with the common emitter of transistors TX11 and TX12. The collector of transistor TX13 is dotted with the emitters of transistors TX39 and TX40, whose bases are connected to the 2-wire read sub-bus LSBR. The collectors of transistors TX39 and TX40 are tied to nodes OUT and OUT, respectively.
When no redundancy is required, the INH signal is lower than any LS0 or LS0 signal (by construction), and transistors TX13, TX39 and TX40 are off. The redundant sub-bus LSBR is therefore isolated from output nodes OUT and OUT. It remains a conventional cascode based multiplexer whose conductive transistors are determined by the voltage levels of the four decoded signals LS0, LS0, LS1 and LS1. Depending upon the levels, one out of four sub-busses LSB0 to LSB3 will be connected to the output nodes for data transfer on the two wires referenced OUT 0.
On the contrary, when redundancy is required, the INH signal is superior to any LS0 or LS0 signal, and current I flows through TX13, then in either transistor TX39 or TX40 depending on the data present on the LSBR sub-bus, while transistors TX11 and TX12 are off. The data present on the LSBR sub-bus is output to output nodes OUT and OUT for being transferred.
FIG. 6 shows the schematic of a high speed BiCMOS late select address comparator 43 that can be advantageously used in the memory architecture of FIG. 4. This circuit is very fast because of its cascode construction. Now turning to FIG. 6, late select address comparator 43 (implemented in a BiCMOS technology that offers the process steps necessary to produce polysilicon-chromium microfuses), is able to detect one defective cell column address. It comprises two identical elementary circuits 50 and 51 each driven by LS signals LS0 and LS1, and including a specific fuse F0 and F1, respectively. Basically, circuit 50 is formed with well known collector dotted transistors forming a two-level current switch cascode. In the bottom level, transistors pair TZ11 and TZ12 has its common emitter loaded by resistor RE1 connected to GND. In the first half of circuit 50, the base of transistor TZ11 is connected to a transfer gate TG1 whose other connection is tied to VX, a reference voltage. The common node A formed between fuse F0, tied to VH, and a current source 10 is connected to one gate electrode of the transfer gate TG1 and via inverter 53, and transfer gate TG1 and via inverter 53 are both connected to the other gate electrode of TG1 and the gate electrode of FET T1. FET T1 is connected in parallel between the base of transistor TZ11 and the ground, and its role is to prevent the base from being floating, but preferably maintained at a potential close to GND. Similar complementary construction applies to the second half of circuit 50 for transistor TZ12, FET T2 and transfer gate TG2, still driven by the potential of node A.
Collectors of transistors TZ11 and TZ12 are respectively connected to the emitters of transistors TZ21 and TZ22 on the one hand, and transistors TZ23 and TZ24 on the other hand. The bases of transistors TZ21 and TZ24 are connected to signal LS0, while the bases of transistors TZ22 and TZ23 are tied to VR. Collectors of transistors TZ21 and TZ23 are dotted and loaded by resistor RC1 in parallel with antisaturation diode D1 at node C. Likewise, collectors of transistors TZ22 and TZ24 are dotted and loaded by resistor RC2 in parallel with diode D2, this latter connection forming node D. Similar construction applies to circuit 51 as illustrated by FIG. 6, and the dotted collectors of transistors TZ25 and TZ27 on the one hand, TZ26 and TZ28 on the other hand are respectively connected to nodes C and D.
Emitter follower output stage 52 is comprised of transistors T6 and T8 connected in series with output node E coupled therebetween. The base of transistor T6 is connected to node D. The base of transistor T8 is tied to Vx and its emitter loaded by resistor RST. Diode connected transistor T7 operates as a voltage shifter for transistor T6 emitter potential. The signal RLS which is output by circuit 43 is available at node E thereof. One current source TZ11 or TZ12 in conjunction with resistor RE1, and one current source TZ13 or TZ14 in conjunction with resistor RE2, are made active according to the value exhibited by the two fuses F0 and F1 (blown or unblown). Transfer gates TG1 or TG2 and TG3 or TG4 show low or very high impedance value depending on whether or not F0 or F1 have been laser blown, respectively. Consequently, current sources TZ11 and TZ12 are mutually exclusive; it is the same for current sources TZ13 and TZ14. The signal that results from the comparison between the LS0/LS1 signals and the bit configuration stored in the F0/F1 fuses appears at node D. For any of the four F0/F1 combinations, there will be only one LS0/LS1 signal combination where no current is pulled at node D. In this case, voltage at node D is very close to VH. The output signal RLS at node E will be derived from this signal appearing at node D minus two Vbe's.
For example, assuming that the fuses F0 and F1 are not blown, node A and B each have potential equal to VH. As a result, the VX supply voltage is applied to the base of transistors TZ11 and TZ13 that are turned on, while transistors TZ12 and TZ14 are turned off. The current flowing through TZ11 flows in transistors TZ21 or TZ22 depending on LS0 signal voltage>VR, or LS0 signal voltage<VR, respectively. The current flowing through TZ13 flows in transistors TZ25 or TZ26 depending on LS1 signal voltage>VR or LS1 signal voltage<VR, respectively. Consequently, node D is always low (VH-Vbe (D1)) except if LS0 and LS1 signals are at a high voltage. In the latter case, node D potential is equal to VH, and RLS signal is high (logic 1). The redundancy scheme is used as soon as the output level of bit address comparator 44 is high.
The detailed truth table of comparator 43 given below illustrates the other situations:
______________________________________ F0 F1 LS0 LS1 RLS ______________________________________ blown blown 0 0 1 blown blown 0 1 0 blown blown 1 0 0 blown blown 1 1 0 blown -- 0 0 0 blown -- 0 1 1 blown -- 1 0 0 blown -- 1 1 0 -- blown 0 0 0 -- blown 0 1 0 -- blown 1 0 1 -- blown 1 1 0 -- -- 0 0 0 -- -- 0 1 0 -- -- 1 0 0 -- -- 1 1 1 ______________________________________
Thus, RLS signal is high (i.e. equal to VH-Vbe (T6)-Vbe(T7)) if the late select address signals LS0 and LS1 have been recognized by the comparator, as explained above. Only if these two LSO and LS1 signals are high, the redundancy is used.
Overall operation of the novel cache memory architecture of the present invention will be better understood in conjunction with FIG. 7, which shows the timing diagram thereof.
A memory operation starts on the leading edge transition of the clock system CS signal (down-going transition). Memory operation is completed by means of self-timing and pulsed circuit techniques. The description of the different phases which contribute to the memory operation will be discussed now whether bit redundancy is used or not.
In the first system cycle we will assume that the bit redundancy circuits have to be used, on the contrary in the second cycle, where we assume that the normal circuits are used, i.e. redundant cells data are not transferred through the multiplexer.
Bit redundancy used (left side of FIG. 7):
The leading edge of signal CS activates a number of different functional circuits in parallel. It resets the RS flip-flop latch 45 (or leaves it reset when the bit redundancy has not been used in the previous cycle) and triggers the word and bit address decoding operation. One result of this address decoding is the selection of one of the BD-1 or BD-2 signals in a given sub-array (one out of K). In parallel, the bit address is compared with up to two failed bit addresses stored in the bit address comparator 44. In the present case, the comparison result will be positive, then latch 45 will be set and either RE-1 or RE-2 signal will be activated, thus allowing 8 out of 16 redundant sense amplifiers (35'-1 to 35'-16) to transfer the cell data content on the redundant read bus 37. Note that, when the redundancy is used, both the normal read busses and redundant bus are activated and propagate their respective cell content. In FIG. 7, only the LSB signals on the read sub-busses LSB0 to LSB3 and redundant sub-bus LSBR are shown for sake of illustration. Later in the cycle, the two valid LS0 and LS1 signals are applied. LS0 and LS1 signals are compared in the LS comparator 43, as explained in conjunction with FIG. 6, then the RLS signal is raised and finally the INH signal will activate multiplexer element 39-0 in such a manner that the redundant data LSBR is transferred to the sense amplifier/buffer element 41-0 output, as the desired final output signal. Generalization to the full byte SETR can be readily deduced from the above.
Bit redundancy not used (right side of FIG. 7):
The leading edge of signal CS resets the RS flip-flop latch 45, which was set in the previous cycle due to bit redundancy utilization. Down-going transition of CS signal still triggers the word and bit address decoding operation. As previously described, BD-1 or BD-2 signal is activated in a selected given sub-array. Bit address is compared with the two failed bit address stored in the bit address comparator 44, but now the comparison result is negative, thus latch 45 is kept reset and neither RE-1 or RE-2 signal will be activated. As a consequence, none of redundant sense-amplifiers (35'-1 to 35'-16) is powered-up. Later in the cycle, the two valid LS0 and LS1 signals are applied. LS0 and LS1 signals are compared within LS comparator 43, but in this case, the INH signal will stay at a low level irrespective the RLS signal is raised or not. Consequently, the multiplexer element 39-0 will use a normal 1/4 path and will transfer one data among the four read sub-busses LSB0 to LSB3 to the output, for instance, data LSB2 as illustrated in FIG. 7.
In summary, the proposed architecture enables selection of both normal and redundant columns if a faulty bit address is recognized by the bit address comparator. The final decision being made subsequently by the combination of late select address signals that are valid later. The disclosed architecture has the following advantages from a performance point of view.
1) It does not increase the address and late select access time.
2) It does not increase the number of spare columns compared with a classical SRAM design. For instance, to correct 2 single faults, only 16 spare columns are required if a byte-wide 4-way set associative cache memory organization is used.
3) The number of spare columns do not depend on the late select address signal number.
While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Thus, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the appended claims.
1. A P-way associative cache memory provided with a system clock, comprising:
- P memory read busses, each of said busses transporting memory data sets, each of said memory data sets being M bits long;
- at least one word-wide organized memory sub-array comprising memory cell columns arranged in q words, each word being M bits long, said memory sub-array being coupled to one of said memory read busses and being controlled by a first set of control signals that enables said memory data sets to be available at said memory read busses;
- a first set of sense amplifiers coupling one of said columns to one of said P memory read busses;
- a single redundant read bus for handling redundant data sets, each said redundant data sets being M bits long;
- one redundant memory sub-array comprising columns, said redundant memory sub-array being coupled to said redundant read bus and being controlled by a second set of control signals that enables said redundant data sets to be available at said redundant read bus;
- a set of redundant sense amplifiers, wherein each of said redundant sense amplifiers is coupled to one of said columns of said redundant memory sub-array and to said single read bus;
- P multiplexers respectively coupled to said P memory read busses, to said single redundant read bus and controlled by decoder means, said multiplexers being responsive to signals provided by said memory read busses and by said redundant read bus,
- said decoder means for generating signals to control said multiplexers; being provided with at least one input and a plurality of outputs, said outputs generating decoding signals that selectively activate at least one of said multiplexers, and said at least one input provides said decoder with late select address signals; and
- at least one logic circuit responsive to defective columns in said at least one memory sub-array, said logic circuit generating a signal for selectively inhibiting said multiplexers, wherein said at least one logic circuit comprises:
- a bit address comparator means identifying an address corresponding to a defective column in said at least one memory sub-array; and
- a late select signal address comparator means generating a redundant late select address signal in response to said late select address signals,
- said identified address corresponding to said defective column and, generated redundant said late select address signal controlling said generation of said inhibit signal to said multiplexers, wherein said inhibit signal and said generated signal from said decoder means control operation of said multiplexers so that
- two columns of said redundant memory sub-array replace two defective columns of said memory sub-array irrespective of the location of said defective columns within said memory sub-array.
2. The P-way associative cache memory as recited in claim 1, wherein said system clock having a clock cycle provides timing to said memory sub-array and to said redundant memory sub-array, and wherein said redundant late select address signal is generated later in said clock cycle than signals indicative of a column address in said at least one memory sub-array.
3. The P-way associative cache memory as recited in claim 1, wherein columns in each of said memory sub-arrays are respectively coupled to said memory read busses in accordance to a predetermined bit weight criteria.
4. The P-way associative cache memory as recited in claim 1, wherein columns in each of said at least one redundant memory sub-array are selectively coupled to said memory read busses in accordance to a predetermined bit weight criteria.
5. The P-way associative cache memory as recited in claim 1, wherein said at least one logic circuit further comprises:
- an AND-gate responsive to said address corresponding to said defective column and to said redundant late select signal as its control signals, for selectively outputting said inhibit signal.
6. The P-way associative cache memory as recited in claim 1, wherein said P-way associative cache memory is selected from a group consisting of a 4-way, 8-way, and 16-way associative cache memory.
|March 15, 1994
|February 1989
|December 1989
- "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", by Tod Williams, et al., I.E.E.E. Journal of Solid-State Circuits 23 (1988) Oct., No. 5, New York.
Type: Grant
Filed: Jun 6, 1995
Date of Patent: May 6, 1997
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Bertrand Gabillard (Paris), Philippe Girard (Corbeil-Essonnes), Dominique Omet (Evry)
Primary Examiner: Hoa T. Nguyen
Attorneys: Richard Lau, H. Daniel Schnurmann
Application Number: 8/466,563
International Classification: G06F 1100;


text:
Nordson SELECT
Global Directory
Features and Benefits
- Precise on-demand drop-jet application of flux to target locations without overspray.
- Provides true no-clean processing since flux is mitigated by solder nozzle without flux residue or ionic contamination.
- Compatible with alcohol-based, water-soluble or rosin-based flux chemistries up to 33% solids content or fluxes as low as 2.5 pH.
- Modular design allows for easy servicing providing fully maintainable and serviceable production environment.
- Ideal for micro flux deposition of flux to small solder sites with unparalleled accuracy and minimal flux consumption.
-Compatible with Novo® 102, 103, Cerno® 102IL, 103IL, 105IL, Integra® 103ILD and Flux & Preheat models
Overview. The FluxJet Precision Drop-Jet Flux Dispenser is designed to control and dispense single drops of flux or a continuous flux pattern as small as 2 mm wide ideal for single terminations close to adjacent SMT components. The continuous deposition is perfect for fluxing headers, connector pins or other multi-pin through-hole components.
The SWAK-OS 4.0 software integrated with the FluxJet Precision Drop-Jet Flux Dispenser's electronic control module provides the necessary on/off and drop frequency control of the drop-jet.
Integrated Solution. The FluxJet Precision Drop- Jet Flux Dispenser fully integrates with closed-loop process controls embedded in Nordson SELECT's SWAK-OS 4.0 software providing seamless operation for your selective soldering process. Nordson SELECT's closed-loop process controls enable sucessful results for a full range of soldering applications and ensures stable and repeatable results for high-yield production.
Experience. With over a decade of selective soldering experience and more than a thousand systems currently in production, Nordson SELECT is committed to providing innovative solutions for all selective soldering needs. Our global support network, including state-of-the-art application development labs, provides customers with world-class know-how and application expertise.
FluxJet Precision Drop-Jet Dispenser
Compatible Flux Chemistries:
Alcohol-based fluxes
Water-soluble fluxes
Rosin-based fluxes
High solids content fluxes
Low pH fluxes
Nozzle orifice size: 130 μm standard
Practical drop size: 2-4 mm (adjustable)
Drop Frequency: 0-90 Hz
Practical deposition range from PCB: 12-55 mm
Max. solids content: 33%
Min. pH: 2.5
Application Note:
The Nordson SELECT FluxJet Precision Drop-Jet Flux Dispenser is recommended for no-clean processing when printed circuit boards will not be cleaned after selective soldering. The FluxJet Precision Drop-Jet Flux Dispenser can be integrated side-by-side with a standard atomizing spray flux applicator to create a dual fluxing system capable of both site-specific flux deposition and mass flux application.

subset: commoncrawl


text:
I love our yard.
It's one of main reasons we bought our house a few years ago. And after living here for awhile now, we've come to see that there is so much more to the outside of our house than just our backyard.
We have so many wonderful places to have fun and enjoy the outdoors at home!
Swing Set
Last Fourth of July, we put in a swing set for the kids. The kids play on it nearly everyday from spring through fall. It's the best "home improvement" we've made so far ;) I wish we would've built it sooner - they love it so much!
Like I said earlier - it's one of the main reasons we bought this house a few years ago: it's private, large, flat, and has tons of mature trees for shade. Perfection.
It's the best backyard for family time!
|Lots of mature trees = lots of piles of leaves!
It's so satisfying to grow your own veggies! We grown lots of veggies (and 1 fruit!) the past 4 summers at this house, but our favorites have been the strawberries, green beans, banana peppers, and cherry tomatoes.
And my fave garden recipes? Homemade garden salsa and strawberry shortcake. What are yours?
This house came with humongous and mostly barren landscaping beds. But over the past 4 springs/summers, we've slowly been improving them...one free "hey-we're-splitting-our-perennials-would-you-like-some" plant at a time.
|Last summer's dining room window garden
We're not completely done yet, but I love how they are turning out! We just need to add a little ground cover in some spots and let everything grow larger to fill in.
|Our Mary Garden this Spring
What weirdos love their driveway? We do!
We have a pretty large and flat driveway which is perfect for sidewalk chalk and riding bikes - or both!
The only downfall is...
|Training starts early at our house ;)
Upstairs Patio
This is my new favorite space because we finally got patio furniture for it this summer! Now, we can finally use it! Jim and I love reading out there, having a snack, or chatting - just the two of us.
Walking Trails and Lakes
Now this is my favorite part about our area - the fabulous lakes. We have 2 we can access easily from our house - the Little Lake and the Big Lake. (Very clever names we came up with!)
|Just a little mommy taking her baby for a walk ;)
They have sidewalks all the way around, wooded islands, fountains, and tons of wildlife like swans, turtles, ducks, frogs, and more. They are just so beautiful...and fun to walk around and enjoy!
|We love watching the swans raise their little one(s) every year!
When we bought this house, I would've never dreamed how much we would love and enjoy every aspect of our yard. It has the perfect outdoor spaces for our family. We can never move now ;)
So what are your favorite outdoor spaces at home? I'd love to hear about what you and your family enjoy the most!
Hope you're having a beautiful summer!
|The first rose of this summer...St. Therese of Lisieux, pray for us!


text:
It has been a whale of a high school baseball season for Pierson/Bridgehampton. At the same time, it wasn't a bad season for Southold, either.
In Southold's case, it was a matter of entering the season with only three returning players from last year in Luke Hansen, Billy Burns and Joe Hayes. And then, as if that wasn't enough, the First Settlers lost their first seven games of the season. Somehow, Southold managed to put the pieces together under its new coach, Greg Tulley, and qualify for the playoffs. READ


text:
Currently Shopping by
Wall Stickers
Childrens Wall Stickers in UK
Choose from a wide variety of cute childrens animal wall stickers for kids and Kids Wallpapers Borders to decorate your child's room. We have every kind of childrens bedroom wall stickers such as glow in the dark, pets, flowers and a lot more. The childrens wall decals are made with safe materials to ensure your child never gets harmed by them.
The removable wall stickers for kids can be taken off anytime without dirtying the walls. When your child gets bored with them they can be easily removed and replaced with new children's wall stickers. Our down to earth prices make it easy for you to provide a new every week so the room is always filled with surprises.


text:
The Tournament of Books' nod to graphic novels comes with this entry: Building Stories by Chris Ware. I wasn't familiar with his work before this showed up on the ToB shortlist, but right after that, he did the post-Newtown New Yorker cover that I found very touching in an understated way. So I was ready to crack this open.
But, if you didn't already know, this isn't really a book. Or it's several books. In a box. With pamphlets and newsprint. When you open the box (pictured above), this is what you see:
Cut off the protective plastic, spread everything out, and here's what you have:
There are no instructions, no suggested navigation. Just a pile of varying types of print matter, all illustrated, some bound like books, some like newspaper, one like a Little Golden Book, one like a folded-up board game.
So that flummoxed me a bit, as I'm a traditional "start at the beginning and make my way to the end" type of reader. After dithering for a bit, I went back to the way the stories were packaged, and read them in that order.
It probably doesn't matter. They're not packed in chronological order. Most of the stories involve the inhabitants of a specific building, but as I got deeper into them, one character in particular took center stage. Her life as a single, lonely woman evolves as she eventually marries and has a child, moves to the suburbs, worries that she's losing herself, especially as an artist.
There are also a couple of stories about a bee. I found the bee annoying. I was much more interested in the people. Having been where the main character is, I found her story compelling, then wondered how I would have found her story back when I was post-college. Would I have found her narcissistic and boring? Probably. I saw a review on Amazon that complained about just that thing, and yet I found many of her stories really interesting and downright moving. There's one pamphlet that focuses on her, and there's no text at all, and it's not quite clear where it begins or ends (it's printed on both sides with no noticeable "start here" point), but it ended up reminding me of that amazing sequence from the movie Up, that tells the story of Carl and Ellie's marriage without a single word. I was moved, and that was surprising, given that overall I found the artwork kind of flat. Often I could only tell the characters apart by their hair color.
It's a mixed bag. Some things were successful, some not so much, and yet I found myself anxious to get back to it and start the next story, and found myself thinking about it after I finished it. The format, crazy as it is, seems to work with the story--how we live our disjointed lives, the different stages sometimes seemingly random in occurrence, parts of the past coming into the present unexpectedly, occasionally in a haunting kind of way.
I also found it interesting that the only blurb came in the way of a gold sticker on the exterior packaging, with a rave review from--can you guess? Who would you expect to blurb a literary graphic novel?
J.J. Abrams.
I don't think it'll last long in the ToB, but I applaud them for including it.


text:
Every time I walk through Central Park I'm stricken with major JFK, Jr. fantasies. All those casual strolls...rolls on Olmstead's finely planned lawns with a (grrrrr) blonde...some nice displays of casual athleticism while wearing a perfectly placed stocking cap. It's all something I wouldn't mind recreating with a similar specimen. In my earlier 20s, I tried to recreate the "casual athleticism" component by myself -- armed with a ball and lacrosse stick. Figured I'd get in some practice with that cradling technique, look fabulous doing it and find someone to help round out the rest of the JFK, Jr. experience. After 10 minutes, I lost control of the ball, hit a man in the head and went home in shame. Ever since, I've limited myself to the strolling bits. If you don't have access to C-Park to induce similar madness, this Central Park bridge photo by Bradford Robotham photo may do the trick. Thank god for fall.
2 comments
fall is the best one, i think
Paul Pincus says:
Subscribe to: Post Comments (Atom)


text:
Check out Kay Cola "Good Girl" Video, the latest visual from Kay Cola, released on Monday, February 13th, 2012. Kay Cola continues to impress with each new leak, and Kay Cola "Good Girl" Video is no exception. It's strengthens Kay Cola's already impressive body of work, which has seen positive change over the years. We're most definitely anticipating Kay Cola's next offering.
Let us know what you think, folks.
Check out the latest video from Kay Cola, Kay Cola "69 [Official Video]" Video.
If you dig this, visit Kay Cola's profile for the latest info, news, songs, and mixtapes. Remember to follow Kay Cola on Twitter.


text:
Zünd at Airtec 2016
At the Airtec 2016 in Munich (October 25 to 27), Zünd will be giving first hand insights into its innovative digital cutting technologies specially
developed for processing composites. Whether carbon, glass or natural fiber, Zünd has what it needs to get it done.
Zünd digital cutters are used for prototyping as well as serial production and offer workflow solutions that are perfect for every type of manufacturing environment. Zünd Cutters are available in 17 different sizes, from 1330 x 1600 mm to 3210 x 3200 mm. Zünd cutters are modular by design. With their built-in flexibility, they can be configured to meet an exceptionally wide range of cutting requirements. The Zünd G3 is the digital cutting system especially tailored to the requirements of the composites industry. The modular cutting system is ideally suited for composites applications, tailored to meet the demands typical of the highly dynamic aerospace industry and is guaranteed to deliver exceptional productivity along with an unusually quick and reliable ROI. The G3 cutter is CE and UL certified. Powered by the user software Zünd Cut Center with its open interface, G3 cutters can be quickly and easily integrated in any type of production environment. High-performance CAM software options support the user in maximizing material yield through automatic nesting.
The Zünd tool palette ensures the appropriate tool is always at hand. For many composites applications, Zünd recommends the robust Power Rotary Tool – PRT, one of the company's flagship high-capacity tools that has proven consistently that it can stand up to the rigorous demands of cutting carbon fiber or fiberglass. The tool and cutting system are protected from statically charged and/or abrasive dust particles, and for cleanly cutting materials with a lower melting point, it is possible to reduce the rpm of the rotary blade. As an air-driven tool with a long cutting stroke, the powerful Pneumatic Oscillating Tool – POT is particularly well suited for cutting honeycomb materials and rigid foams. The Zünd R62, a custom router bit, is recommended for routing cured parts cleanly and efficiently.
The Zünd G3 cutters have an impressively broad installation base, proving their reliability on a daily basis. The company's list of references comes with many renowned customers involved in the aerospace and aviation business.


text:
About ARUP Genetics
ARUP Laboratories is a national clinical and anatomic pathology reference laboratory offering in excess of 3,000 tests and test combinations, ranging from routine screening tests to highly esoteric molecular and genetic assays. ARUP provides laboratory testing services to more than half of the nation's university, teaching, and children's hospitals, as well as to regional hospital networks, multihospital groups, and military and government facilities.
ARUP, a nonprofit enterprise of the University of Utah, has a full-service genetics laboratory offering testing in molecular genetics, cytogenetics, biochemical genetics, and maternal serum screening, with experience in sequencing, MLPA, fluorescence in-situ hybridization (FISH), microarray, and biochemical assays. Most of the new test development taking place at ARUP is occurring within the Genetics Division, led by more than 15 medical directors, all of whom hold faculty appointments at the University of Utah. Our team of genetic counselors are an integral part of our laboratory and serve as an invaluable resource to our clients and ordering healthcare providers. ARUP's genetic laboratory personnel, including our medical directors and genetic counselors, are available to answer your questions about test ordering, results interpretation, and logistical issues.
ARUP Genetics is committed to providing the highest-quality service to help you deliver exceptional care to your patients. Our priority is the patient. We work with our clients to ensure that genetic testing is ordered appropriately, even if that means that we perform fewer tests. ARUP's team of genetic counselors routinely reviews all complex genetic test orders to ensure proper test utilization and will recommend test order modification when appropriate. These efforts have helped our clients improve patient care by canceling duplicate, inappropriate, and unnecessary tests, saving time, money, and potentially preventing missed diagnoses. Our routine review of complex test orders has proven to save clients thousands of dollars each month. Working in partnership with healthcare providers, ARUP genetic counselors discuss the clinical indication for testing, along with any other pertinent information, to ensure that the testing ordered will provide the information needed in the most cost-effective manner possible. This partnership ensures that the most clinically appropriate, and often less expensive, tests are performed.
Contact ARUP Genetics for more information on our genetic services.


text:
Already a member?
Sign in
May 2009, Volume :39 Number 5 , page 11 - 12 [Free]
Join NursingCenter to get uninterrupted access to this Article
After working many years in a hospital, I took a job in a long-term-care facility. My supervisor and other nurses often "borrow" medications prescribed for one resident and give them to another. For example, if a resident dies or leaves the facility, my supervisor may cross off his name on his medication packet and write the name of another resident who gets the same drug. She says this eliminates waste and saves time.
My supervisor became irritated when I questioned her. She says they've worked this way "forever" and that I'm just used to doing things differently in the hospital. Are standards really so different outside the hospital?-C.C., ILL.
No. The practice you describe is unacceptable in any setting. Besides being fraudulent, it's unsafe for patients and far outside accepted standards of care established by the nursing and pharmacy professions and regulatory bodies such as The Joint Commission (TJC). The facility and clinicians participating in this substandard practice could lose their licenses and be subject to other penalties if an injured resident sues or if the fraud is discovered by agencies that oversee residential facilities.
Refuse to participate in this illegal practice and submit an event report to give facility administrators a chance to correct the situation. You should also ask to see the facility's policy and procedure on medication administration as an approach to exposing the problem. Many resources are available to support your position, such as your state's Pharmacy Practice Act, the Institute for Safe Medication Practices (http://www.ismp.org), and TJC National Patient Safety Goals (http://www.jointcommission.org/patientsafety/nationalpatientsafetygoals).
If medication administration policy doesn't change, we advise you to look for another job to protect your license. You may also have a professional obligation to report fraudulent and substandard practices to the appropriate licensing agency.
At the hospital where I work, nurses document medication administration in two places: a paper-based medication administration record (MAR) that's eventually thrown away, and the electronic medication administration record (eMAR), which becomes a permanent part of the patient's medical record. In some cases, medications charted on paper don't make it into the eMAR. Management wants us to find these drugs and enter them into the eMAR-for other nurses, if necessary. I disagree with this policy. Am I right to be uncomfortable with this?-B.K., VA.
Yes, for several reasons. For one, it's poor policy because it opens the door to errors, patient injury, and inaccurate or fraudulent documentation. Expecting nurses to document medication administration in two places doubles the risk of errors. In addition, documenting for another nurse isn't acceptable except in certain specific circumstances, such as during a code when a scribe is designated. The facility should have a policy and procedure to address these exceptions.
In general, however, documenting for someone else exposes you to legal liability if a mistake is made. In the case of a potentially missed medication, the responsible nurse should make a late entry to document what actually happened according to facility policy.
Depending on how the eMAR is set up, documenting a late entry electronically can raise problems not encountered with paper-based MARs. For example, the system may close out before a nurse can make a late entry. If your facility has a policy permitting one nurse to document for another in limited circumstances, it should have a mechanism (for example, a drop-down box) that will clarify that one nurse is documenting on another nurse's behalf after consulting with her. Communicate all your concerns to management and offer to help improve and streamline the system according to best practices promoted by recognized authorities. For more on the benefits and pitfalls of electronic documentation systems, see "Playing it Safe with Bar Code Medication Administration" on page 32 of this issue.
I work in a large community hospital. Last week, we nurses received an alarming notice with our paychecks. It stated that "effective immediately, all licensed staff will be held accountable" for medication errors and various other mistakes, such as transcription errors or failing to report lab results on the day received. Disciplinary action ranges from a verbal warning for the first offense to a 3-day suspension with probable termination for the fourth offense. My manager says nurses will be "more careful" if their jobs are on the line.
I'm afraid this policy will backfire by discouraging nurses from reporting errors and close calls. Are harsh policies like this a new trend?-K.R., N.Y.
On the contrary. Experts in medication safety have long recognized that a punitive "name, shame, and blame" policy simply drives errors underground. Afraid of retribution, clinicians avoid reporting errors or near misses, allowing hazards and risky circumstances to flourish. The current trend is toward a "just culture" that's both fair to clinicians who make errors and effective in reducing risks.1,2
The medication administration process has many elements, and errors can be introduced at any point. A just culture encourages process changes that strengthen each link in the chain and remove incentives for risky shortcuts, work-arounds, and other unsafe behaviors.
To make meaningful process changes, management needs to track actual and potential errors and evaluate why they occurred. In the words of one expert, a just culture "rewards reporting and puts a high value on open communication[horizontal ellipsis]It is a culture hungry for knowledge."3
Advocates for a just culture have created a Just Culture Community to share information and ideas. Check it out at http://www.justculture.org, and work to change the culture in your facility.
1. Institute for Safe Medication Practices. Our long journey towards a safety-minded Just Culture. Part I: where we've been. ISMP Medication Safety Alert!! 2006;11(18):1-2. [Context Link]
2. Institute for Safe Medication Practices. Our long journey towards a safety-minded Just Culture. Part II: where we're going. ISMP Medication Safety Alert!! 2006;11(19):1-2. [Context Link]
3. Marx D, Comden SC, Sexhus Z. Our inaugural issue-in recognition of a growing community. The Just Culture Community News and Views. 2005;1:1. [Context Link]
Join NursingCenter on Social Media to find out the latest news and special offers
Connect with us on Facebook, Twitter, Linkedin, YouTube and Pinterest.
Copyright © 2019, Wolters Kluwer – Terms & Conditions – Privacy Policy – Disclaimer -- v188.8.131.52


text:
Technologies, services, and partnerships are evolving rapidly, which create challenges and opportunities for mobility managers. NCMM tracks the most important news to keep you updated on the information and ideas that impact your efforts and communities. View in-depth resources on these evolving mobility strategies on NCMM's By Topic pages.
Think we're missing something? Send us news and ideas (firstname.lastname@example.com) to include here, on the By Topic pages, or on our blog.
Autonomous Vehicles
Health Care Access
Mobility as a Service (MaaS)
Older Adults
On-Demand Transportation Services
People with Disabilities
Shared Use
Header Image Credit: Marco Verch, Flickr, CC BY 2.0


text:
Awesome Experience
So after a lot of planning, I was successful of organizing a iftar party with my seniors and batchmates. A lot of mishaps and misunderstandings but in the end we had a pleasant time. We enjoyed some really good food in an equally ecstatic ambience. In the eye soothing environment with the touch of mouthwatering dishes, they created the perfect combination. Sorry I didn't take any picture of the platter but I can say it looked far better than the one I uploaded. It had more on quantity as well. I would say it is enough to fill an average person. At first we had initial plan of 30+ persons meet and reserved accordingly. But many of our last minute cancellations made our number 17. So we had to cancel our reservation on the eleventh hour. They had no chance of taking in new guests. They could have charged us for all 30 platter. But they did not do that. They charged for the 17 platters only. Moreover all the other 13 plates ware on the house. You don't see such hospitality this days. And their service and behavior was up to the mark as well. Taste -8/10 Ambience -10/10 Service -9/10
Other Ratings
We waited for...10 min(s) (Dine-in)
We spent...Approx. TK 450 ()
Comments (0)
A nice place to hangout
I tried their pasta & prawn tempura which was full of flavor & delicious. Cafe memoir is a good place to hangout if you like shisha & not getting any place at uttara then this is the place to come. They have a friendly & new way of service which is eye catching. Very nice interior.
Comments (0)


text:
Published at Sunday, May 26th, 2019 - 17:50:01 PM. Coffee Table. By Emeraude Flament.
Find a coffee table that fits your room size, meets your essential needs, enhances your color theme, and accents your decor. You don't want cups of hot coffee on the floor where a small child could step in them and get burned. People are less likely to spill the coffee if it is on a coffee table to begin with.
Whilst a dining table might be out of reach for small children a coffee table is the perfect height for tiny fingers to investigate. Many small children have a particular fascination for coffee tables, spending hours investigating the treasures that they can hold.
Fresh Posts
Tag Cloud
About ▪ Contact ▪ Terms of Service ▪ Privacy Policy ▪ Cookie Policy ▪ Copyright ▪ Sitemap
Any content, trademark's, or other material that might be found on the Seattleoutdoorart website that is not Seattleoutdoorart's property remains the copyright of its respective owner/s. In no way does Seattleoutdoorart claim ownership or responsibility for such items, and you should seek legal consent for any use of such materials from its owner.


text:
Business Plan - Purchasing Objectives
Establishing the purchasing requirements is an operational function in any business with physical stock supplies. Purchasing activities involve sourcing and obtaining supplies as well as paying for them. Many forms of business activity require some kind of stock supplies. Stock supplies required could include raw materials, component parts, trading stock or job materials.
The purchasing objectives and the management aim for the purchasing function should be to obtain the best possible supply terms. Because the major concern in negotiating supply terms is the cost of supplies, your main purchasing objective should be measured in the average gross profit margin. The gross profit margin is calculated as the percentage of gross profit made on the sale of the stock item. It measures how cheaply you purchase stock supplies.
Inventory (Stock) Turnover Considerations
When considering stock as part of your purchasing objectives, a low turnover rate may point to overstocking, obsolescence, or deficiencies in the product line or marketing effort. However, in some instances a low rate may be appropriate, such as where higher inventory levels occur in anticipation of rapidly rising prices or shortages. A high turnover rate may indicate inadequate inventory levels, which may lead to a loss in business. Assume cost of sales is $70,000, beginning inventory is $10,000, and ending inventory is $9,000. The inventory turnover equals 7.37 times ($70,000/$9500).
Back to What's in a Business Plan from Purchasing Objectives


text:
After listening to the first strains of Beethoven's Ode to Joy, we followed the directions, and took the elevator to floor 8, and then walked up to floor 9.
What an awesome surprise! Floor 9 is an open air floor where all the bells are housed, so the experience is like being inside a gigantic music box, while it is being played. It's amazing to be able to hear and feel the music at the same time!
The view is beautiful, and you can watch the performer strike the thin wooden handles that comprise the keyboard and foot pedals. Except for the clock chime, there is no automation of any kind-- the music is an actual performance by the live carillonneur playing the instrument, whose origins can be traced directly to 16th century Europe.
More information:
Burton Memorial Tower
- designed by Albert Kahn
- 212 feet high
Charles Baird Carillon
- total of 53 bells
- largest weighs over 24,000 lbs
This link to The Charles Baird Carillon, as well as the link in the first paragraph give much more information.
Want to see and hear it for yourself? The carillon and observation deck are open to the public Monday through Friday from 12:00-1:00 PM every day that classes are in session.
You might also want to stop into Ashley's for a pint before or after you visit. Choose from 70 beers on draft, and 90+ bottles, including many beers brewed in Michigan. Here is an excellent article from The Michigan Daily that does a great job in describing the experience.


text:
My reconciliation with Kwankwaso underway, says Ganduje
Governor Abdullahi Umar Ganduje of Kano State has raised the hope that the rift between him and his predecessor, Senator Rabiu Musa Kwankwaso would soon be resolved, describing it as a "minor in-house quarrel."
"The situation is under control. It is an in-house problem, which is under control, we are talking about it," Ganduje said, after his meeting with President Muhammadu Buhari at the Presidential Villa, Abuja yesterday.
The relationship between Ganduje and Kwankwaso, under whom Ganduje had served for two terms as a deputy governor, has been anything but cordial, culminating in the impeachment of the Chief Whip of Kano State House of Assembly, Zubairu Mamuda Madobi on Thursday, for daring to refuse to follow his colleagues to pass a vote of confidence on Ganduje as the leader of the ruling
All Progressives Congress, (APC) in the state.
Madobi, along with a few of his colleagues in the House, had decided to pitch his tent with Kwankwaso, the immediate past governor of the state, as the leader of the party in the state.
The governor played down the effect of the row between him and Kwankwaso on the fortune of the APC in the state, even though he admitted that reconciliation efforts were ongoing between them, assuring that the party will continue to hold the grip of the political lever in the state. "Yes, reconciliation is ongoing and it will work. We have been together for long. We are politically brothers and friends. Therefore, we will make sure that we do not allow things to continue to fall apart. We shall put heads together to make sure that there is peace and stabilise in the state," the governor said.
Asked if he would continue to wear the famous Kwankwasiya red cap, for which the group, while it was intact was known for, he showed his head to the reporters and asked, "What are you seeing on my head now?"
While giving an assurance of the impending reconciliation between the two of them, Ganduje, however, gave a hint of possible alteration of some of the policies, which he also took part in as the deputy under Kwankwaso, such as the overseas scholarship programme of the state government.
No comments yet


text:
An Ode to Women in Technology
This post is part of Ada Lovelace Day, in honor of women excelling in technology.
Quick. Who was the first computer programmer?
The answer: Ada Lovelace
She wrote the first "program" for Charles Babbage's analytical engine. Babbage conceived the idea only to perform calculations, but Lovelace saw beyond that purpose to the possibility that that first "computer" could calculate Bernoulli numbers.*
My decade-plus in the technology world has showered me with blessings. One of these is the women that have guided and inspired me. Here are a few that I want to thank profusely for their guidance, support, and inspiration:
Michelle opened the door.
Lisa illuminates just how big the world can be.
Liz inspires with her burning intelligence and amazing poise.
Cyd shows how art, spiritual, and professional life coexist.
Christina creates new worlds with her ability to reinvent herself.
Kit helps me see the practical path and how to plot my own.
Stephanie embodies true wisdom, creativity, and focus.
And, last, but not least, thanks to Mom for being completely open. Without her example, no doubt that it would be far more difficult to recognize the amazing women that surround me.
At the IA Summit this past week in Memphis, it was brought to our attention that the UX community is blessed to have so many women that actively lead our practice. I thank my lucky stars every day.
*The analytical engine was never built, but let's not blame Lovelace for the failure of the men around her.
Photo credit: Thanks to kpwerker for her great Flickr photo.
Tuesday, March 24, 2009
Subscribe to: Posts (Atom)


text:
The vision for Osborne & Collins has always been to operate across the South East with a focus on providing a competitively priced, first class service for clients, ensuring the work is conducted with integrity and with constant personal contact with the client. These values remain core to our business today having grown strongly since it began in 1978. The company became limited in 1994 and is now regularly turning over more than 1 million a year employing around 30 permanent staff.
Within the electrical contracting and construction industries O&C has built a reputation for quality and is fully accredited to provide a comprehensive range of contracting services for clients operating across a wide range of sectors. This reputation is built on our expertise for managing highly complex industrial projects as well as being competitive for smaller, more specific requirements while always remaining an easy and trustworthy company to do business with.
- We combine quality workmanship, experience and competitive pricing
- We work to ensure every project is efficiently managed and completed on time and on budget
- A first-class reputation for exceptional service and standards
- 35 year's experience and a real focus on customer satisfaction


text:
Tax Dodgeball for Real Estate Professionals
Clarion Hotel
1230 Congress Street
1230 Congress Street
Portland, ME
Michael Sheehan will give a presentation at this breakfast seminar April 30, co-sponsored by Preti Flaherty. Other topics include: capital gains planning, with attention to carried interest structures; ways to plan around the passive activity rules, and avoid the new 3.8% Medicare surtax; and structuring real estate projects to monetize tax credits in light of the Historic Boardwalk decision and recent Safe Harbor guidance issued by the IRS.
Registration is required for this event.


text:
2018 Suzuki Burgman 650 Executive
For Sale in Ladson, SC 29456
Velocity Powersports (843) 940-8156 ext 101
2018 Suzuki Burgman 650 Executive
The Burgman 650 ABS* Executive provides you an outstanding riding experience through an advanced transmission with two fully automatic modes (Drive and Power) plus optional manual shifting. A reliable and robust DOHC, liquid cooled engine utilizes design elements from the legendary Hayabusa to provide all the performance you and #8217;ll ever need – and then some. This urban smart and travel-ready scooter is equipped with spacious ergonomics, smooth suspension, and a plush seat with adjustable lumbar support, ample storage compartments, and an aerodynamically designed remotely adjustable windscreen. Additional amenities only available on the Executive model include heated grips for the rider, a supportive backrest for the passenger, and a heated seat for both the rider and the passenger.
Features m… read more at http://VelocityPowersports.mycyclesearch.com/s/39435289?service=11 Click here for more.


text:
"Being an ambassador has provided me opportunity to network with other preservice and full-time educators throughout New Jersey and see things from different perspectives, which has helped me become more knowledgeable about classroom practices and policies. It has allowed me so many opportunities, such as attending the NEA-SLC in D.C., that aren't offered in regular college of education courses." - Morgan Ivich Seton Hall University
"Being an ambassador and an active member of NJSEA has been an incredible and irreplaceable part of my learning and growth during my first year of college. I had the opportunity to attend several preservice workshops that have sparked my interest and increased my knowledge on various educational topics. Additionally, I have met many extraordinary future educators, and I've greatly enjoyed discussing our shared passion. It is important to lifelong learning as a teacher, and being an ambassador not only allows for but also encourages personal growth." - Amanda Rebelo, Seton Hall University
"Being an ambassador exposed me to opportunities and responsibilities I wouldn't have known about otherwise. I have gained professional confidence and a network of colleagues throughout the past two years. Over the years, the fellow peers and teachers I have worked alongside of have greatly impacted my professional awareness, and I hope to continue making an impact in their professional growth as I continue working with NJSEA, as well." - Courtney Earnest, Rider University
"Being an ambassador has given me so many amazing opportunities that I otherwise wouldn't have had. I've been able to attend various professional development events with other like-minded preservice educators and made connections with both preservice and full time members. Through events and networking, NJSEA has also given me countless new tools for my educational toolbox, allowing me to grow as an educator, learner, and activist." - Kalie Mehaffy, The College of New Jersey
"Being an ambassador for NJSEA has provided me the chance to network, immerse myself in educational issues, and grow both professionally and personally. My time as an ambassador has been marked with exciting traveling opportunities, such as the Summer Student Leadership Conferences in Orlando and Washington D.C. There have also been scholarships to attend informative workshops on interesting topics, such as special education and urban schools. All of these events have included chances to form relationships with preservice educators like myself from campuses all over New Jersey. Being an ambassador has increased my confidence and helped prepare me to make the transition from a college student to a full-time NJEA member and teacher." – Deanna Kollar, Rowan University
"Being an ambassador has opened new doors for me and exposed me to opportunities that I would have never known existed. I am very grateful for the people I met along the way and the professional development I have gained; for instance, at the leadership retreat, I was able to connect with other ambassadors, step out of my comfort zone, and learn more about my future as an educator. I have learned so much more about educational topics and policies and became a better person and future educator from this experience. I am excited to keep growing with NJSEA." – Sandra Perls, Rowan University
"When the ambassador program jump-started, I was not chosen to represent my school. Rather than taking it as a failure, I rose to prove I was worthy. Becoming an ambassador was a reward to myself as well as a lesson. From not being chosen, I rose strong, put in the extra effort, networked to increase membership, attended EVERY event possible, and stepped outside my comfort zone. The tasks set to ambassadors require dedication, creativity, and time – among other requirements. Although, being an ambassador sometimes feels like a thankless job, the reward is seen through our monthly membership updates, the swarm of yellow bags at the AC convention, the successful local chapter events, the Spring Conference, and the attendees of the National Education Association Student Leadership Conference. I realized that I was looking for the reciprocation of appreciation and approval rather than standing on my own two feet and giving myself credit. To be an ambassador is to be strong; it is to believe in yourself and this organization; it is to be the voice for your future students and for your future profession!" – Jessica Quijano, The College of New Jersey
"Without NJSEA, I wouldn't have had access to as many of the professional development opportunities that being an ambassador offers, such as the Atlantic City convention, events across campuses, and other PD that is typically only for full-time members. I've made so many connections with other passionate educators, preservice and full-time alike, which have shown me the strong community education fosters. This is my second year as an active ambassador and first year as the Publications Chair, and it has been one of the most worthwhile experiences of my educational career thus far. NJSEA has given me the tools to become a better educator, peer, and lifelong learner." - Chelsea Hahn, The College of New Jersey
Thinking about joining? Take advantage of all the opportunities available to you as a preservice educator.
What has being an NJSEA ambassador done for you? Share your thoughts.
Leave a Reply.
New Jersey Preservice Education Association (NJSEA)
As the preservice branch of the New Jersey Education Association (NJEA), we aspire to empower, excite, and inspire all future educators about their upcoming teaching careers in public education.
Social Media
Facebook: New Jersey Student Education Association
Twitter: NJEAstudents
Instagram: NJEAstudents
Snapchat: NJEAstudents
YouTube: New Jersey Student Education Association
Pinterest: NJEA Students
June 2017


text:
the very worst sort of people are those who have long been professing Christians, but who are destitute of grace, having a name to live, and yet being dead. Alas! there are people like that among our deacons, and among our church-members, and we cannot get them out; and, as long as they remain, they exert a most baneful influence. It is dreadful to have dead members where every single part of the body should be instinct with divine life; yet in many cases it is so, and we are powerless to cure the evil. We must let the tares grow until the harvest; but the best thing to do, when you cannot root up the tares, is to water the wheat, for there is nothing that will keep back the tares like good strong wheat. I have known ungodly men who have had the place made so hot for them that they have been glad to clear right out of the church. They have said, "The preaching is too strong for us, and these people are too Puritanical and too strict to suit us." What a blessing it is when that is the case! We did not wish to drive them away by preaching the truth; but as they went of their own accord, we certainly do not want them back, and we will leave them where they are, praying the Lord, in the greatness of His grace, to turn them from the error of their ways, and to bring them to Himself, and then we shall be glad to have them back with us to live and labour for the Lord.
Spurgeon on the unregenerate in the church
C. H. Spurgeon, The Soul-Winner: (or) How to Lead Sinners to the Saviour, (London: Marshall Brothers, Ltd., 1912), Under: "Chapter 6 – How to Induce Our People to Win Souls".
Leave a Comment


text:
NEW YORK, NEW YORK, December 12th, 2007 - Demonstrating how its DPS Kiosk 7000 turnkey photo finishing and printing kiosk can be a profit center for businesses in a wide array of retail, hospitality and other commercial businesses, Mitsubishi Digital Electronics today announced that -Wall Drugs in South Dakota had successfully deployed a DPS Kiosk 7000 at its legendary roadside mall and attractions near the Badlands National Park and close to many other tourist attractions in the state .
The system, with integrated credit card capabilities, was sold and installed by Ideal Gifts Photos and provides Wall Drugs with a worry-free revenue generator and customers with an intuitive, useful service., Wall Drug needed to increase the profitability of its photo department, while at the same time providing a fast and easy service to the large number of tourists in the area. After getting its start in 1931 by offering free ice water to travelers passing through South Dakota, Wall Drug has gone on to become one of the most famous roadside attractions in America, offering a wonderland of recreational amenities to as many as 15,000 customers a day in the summer.
With so much to see and do in the area, servicing the imaging needs of its customers was a crucial addition to the company's offerings. Tyler Swift, head of the photo department at Wall Drug, along with its owners, decided on the Mitsubishi DPS Kiosk 7000 after examining numerous other possibilities.
"We wanted a reliable, cost effective kiosk that our customers could use without us having to have a staff person present all the time," said Swift. "After looking at a lot of options, we decided the Mitsubishi was the best way to go because it's so fast and easy for the customers to use without assistance."
The DPS Kiosk 7000 allows Wall Drug customers to simply insert their digital camera card and, through the use of a large, easy to use touchscreen, to quickly and easily print out photos or empty the card onto a CD. Though Wall Drug offers extra digital cards, Swift has found many customers prefer to use the one they have and the DPS7000 allows them to empty that card onto a CD and continually re-use it. This comes in handy as they go from the Badlands to Mount Rushmore to the many other attractions in that part of the state.
The DPS Kiosk 7000 is a compact system that can be mounted on a pedestal or positioned on a countertop and has a wide range of printer hookups, offers numerous print sizes in addition to CD burning, and features Bluetooth wireless technology as well.
About Mitsubishi Digital Electronics America, Inc.: Headquartered in Irvine, CA, Mitsubishi Digital Electronics America, Inc., is a subsidiary of Mitsubishi Electric Corporation (MELCO) of Tokyo, Japan, a worldwide leader in premium quality imaging and presentation products that lead the industry in technology innovation, performance and reliability.
Mitsubishi Imaging Products is unequaled in its commitment to the marketplace with over two decades of manufacturing experience and technology leadership. Every Mitsubishi printer and time-lapse recorder is backed by a network of dedicated professionals and an outstanding service and support program. Mitsubishi's printers and time-lapse recorder products are made available to customers through a network of authorized dealers and distributors throughout the United States and South America.


text:
Welcome to Olive City Care Home!
Providing Compassionate Elderly Care in Corning, CA & Surrounding Communities
The decision to send a loved one into assisted living is a significant and often difficult decision for you and your family. In order to provide peace of mind for both you and your loved one, it's important to find an environment that will feel as close to home as possible while still providing the support that you and your family needs. Luckily, Olive City Care Home makes finding a quality elderly care home in Corning CA a simple and comforting process.
At Olive City Care Home, we provide comprehensive, long-term assisted living and care services for the elderly. We have served the seniors of Corning, CA and surrounding communities such as Tehama-Glenn and Butte Counties for 20 years.