{'fraction_non_alphanumeric': 0.030680728667305847, 'fraction_numerical': 0.0, 'mean_word_length': 5.365853658536586, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design Representation And Transformation For High Level Synthesis In Resource Constrained System

High-Level Synthesis is the process of mapping a behavioral description at the algorithmic level to a structural description in terms of functional units, memory elements and interconnections (e.g. multiplexers and buses). The intermediate format for High-level synthesis can be represented in Control Data Flow Graph (CDFG), Data Flow Graph (DFG), Control Flow Graph (CFG), Finite State Machine (FSM), Finite State Machine using Data path (FSMD) or Codesign Finite State Machine (CFSM). The primary goal is to suggest a new theoretical approach to Hardware/Software codesign partitioning and scheduling for a Resource-Constrained System. The approach is based on data path for CDFG model that capture the design information from the source file specified by VHDL language from its equivalent separate Control Flow Graph and Data Flow Graph. This paper discusses helpful optimization method for HW/SW partitioning and High-Level Synthesis tools.