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Cache Tag Array Fault Tolerance Method Based on Redundancy and Similarity of Adjacent Cache Line Tag Bits

As an important part of the computer system, cache is susceptible to soft errors caused by radiation. To protect the cache from soft errors, we propose a write-back L2 cache tag array fault tolerance method based on redundancy and similarity of adjacent cache line tag bits. First, 2-way interleaved parity is adopted to clean line tag bits, and the error is detected and recovered from the next level of memory. Then, according to the 1:1 division ratio, dirty line tag bits are divided into two parts: high bits and low bits. For high bits, 2-way interleaved parity is adopted to detect errors, and the similarity of adjacent cache line tag bits is adopted to correct errors. For low bits, dual redundancy is adopted to detect and correct errors. Cache fault injection and tolerance experiments show that the fault tolerance rate of the proposed method in this paper is 98.89%, which is superior to the previous methods.