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Design and implementation of area-delay-power efficient CSLA based 32-bit array multiplier

Addition and Multiplication are two important mathematical operations that can be performed in every digital circuit. The performance of multiplier depends on adder, hence there is a need to use an efficient adder for multiplication. Definitely an efficient Adder can be utilized to enhance the performance of DSP system. This paper presents lower area, energy efficient 32-bit Array Multiplier based on optimized Carry Select Adder. The proposed Multiplier gives high performance by saving 41% power, less delay by 27% with less area by reducing the slices up to 11.83% and LUTs by 7.6% when compared to conventional CSLA based Array Multiplier.