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Implementing An Improved Image Enhancement Algorithm On FPGA

As image enhancement works with the initial raw inputs at the front end of the image processing applications, it can be considered as a backbone of image processing, and offers a wide range of area of applications, and also have started being used in medical field over the past decade. On the other hand, these image enhancement techniques are bit demanding in choice of processing units when it comes to implementation due to the demand of high resolution. In this paper we present an improved image enhancement algorithm in terms of performance and its implementation on FPGA to satiate the necessity of high speed, powerful, and cost-effective processing unit by providing flexibility, parallelization, pipelining and reconfigurability. The FPGA implementation was obtained using High Level Synthesis from MATLAB specifications and implemented an improved image enhancement algorithm on Cyclone V by using Intel Quartus Prime CAD tool suite. We have considered an X-ray image size of 1000x1920p for implementation and achieved a quantitative improvement in PSNR values and hardware resource utilization along with the better visual interpretability by our proposed improvements.