{'fraction_non_alphanumeric': 0.0375, 'fraction_numerical': 0.011785714285714287, 'mean_word_length': 4.657239057239058, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of High-Speed Quaternary D Flip-Flop Based on Multiple-valued Current-mode

A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.


Introduction
Two-valued logic has been well developed and widely used in the field of electronic and information. However, with the increasing demands for smarter, smaller and faster, the deficiencies of two-valued logical systems begin to appear. It becomes pretty difficult to meet the all requirements including high-speed switching, low-power dissipation and low-consumption of chip area simultaneously. Based on this, more and more attention has been paid to multiple-valued logical systems [1][2][3][4] . One of multiple-valued logic circuit techniques is the multiple-valued current-mode (MVCM) circuitry which performs arithmetic and logic operation with current mode [5][6][7] . The potential advantage of MVCM integrated circuits is to decrease the number of wires and devices, since a wire is able to transmit more than 1-bit data and the linear sum is easy to be obtained by simply connecting wires together [7][8][9] . This paper demonstrates a new type of quaternary D flip-flop (DFF) based on multiple-valued current-mode and employing dynamic multiple-valued source-coupled logic (MVSCL) for high-speed sequential circuit of VLSI systems. A MVSCL circuit employs precharge-evaluation mode to decrease the power dissipation, its threshold detectors use differential-pair circuit (DPC) to work under small-swing signals, and thus fast swhiching can be achived [10] .

Fundamental Principles of Dynamic MVSCL Circuits
A general structure of sequential multiple-valued (MV) circuits based on the current-mode is shown in Figure 1, which is composed of three main units, threshold detectors, storage elements and output generators [9][10][11] . In a MVSCL circuit, both of the threshold detector and the output generator are implemented with DPCs. DPCs can operate at small-swing input voltages in the threshold detector and switch the output currents on or off in the output generator, so low-power dissipation and high-speed for such a MV circuit can be realized [12] .  Figure 1. Diagram of sequential multiple-valued circuits The dynamic MVSCL circuits generally consist of four components, linear sum, I-V convertor, comparator (CMP) and output generator [11] . The schematic diagrams of these basic components are shown in Figure 2. An input current signal I(X) firstly is converted into a voltage signal V(X) by the I-V converter. Then the comparator compares the V(X) with a reference voltage V(T) and generates the two-valued differential-pair output signal (G, G′). The logical function of comparators is described by Eq. (1).
The main function of output generators is to produce multiple-valued current-mode differential output signals (Y, Y′) depending on the two-valued differential input signals (G, G′), and its logical function is described by Eq. (2).

Threshold Detectors Based on Dynamic SCL and DPC
According to the logic characteristics of the comparator described in equation (1), two threshold detectors are needed for transforming the input quaternary signal V IN into the corresponding binary differential-pair signals. In order to design the two threshold detectors, three comparators named CMP1, CMP2 and CMP3 are designed which thresholds are set as V 0.5 , V 1.5 and V 2.5 , respectively. The first threshold detector is composed of CMP2, as shown in Figure 3, by which the binary output (G A ,G A ′) is  Figure 4, by which the binary output( G B ,G B ′) is obtained [13] . The three thresholds V 0.5 , V 1.5 and V 2.5 are set as 0.6V, 1.2V and 1.6V. The encoding between quaternary input V IN and binary output (G A ,G B ) are described by Eq. (3)~(4).

Principles of the Quaternary D Flip-Flop
The proposed quaternary D flip-flop is based on the master-slave mode, its scheme diagram is shown in Figure 5. The master latch consists of two threshold detectors and four pass-gate-invertor latches which are effective at the same clock logic level as these threshold detectors. The slave latch simply consists of four pass-gate-invertor latches which are effective at the inverted clock logic level with the master latch. The pass-gate-invertor latch consists of a clock-controlled CMOS pass-gate and a CMOS invertor. The output generator is designed with no any clock signals. The input quaternary signal V IN firstly compares with the three reference threshold voltages, V 0.5 , V 1.5 and V 2.5 , and generates binary differential-pair signals (G A ,G A ') and (G B ,G B ') depengding on the comparation. These generated siganls are transimited to the pass-gate-invertor latches of the master latch and then to the slave latch. If the master latch is effective at the positive phase of clock, the slave latch should be effective at the reverted phase. In this case, the final output V OUT of the quaternary DFF produced by the output generator comes out on the trailing edge of the clock signal, which is four-valued and corresponding to the original four-valued input signal V IN .

Output Generator
The optimized schematic of the Output Generator is shown in Figure 6. There are two branches, I 0 and 2I 0 , and which one is closed or not is controlled by the signals applied at the gates of these transistors. The currents of the two branches can be summed and form a four-valued output, 0, I 0 , 2I 0 , 3I 0 , by wiring them together. Every gate of these transistors is driven by the two-valued outputs of the Slave Latches, (Q A ,Q A ′) and (Q B ,Q B ′), so the generated current signal I OUT corresponds to the original input signal V IN . The current I OUT is able to be converted into a corresponding voltage V OUT by a PMOS transistor used as an I-V converter.

Evaluation
An evaluation of the presented quaternary DFF is conducted by HSPICE simulation at 100MHz and 1GHz with a 0.18μm CMOS technology. Figure 7 indicates this simulation, in which the clock period is 10ns (100MHz), the input is quaternary voltage signal, and the output quaternary voltage signal is generated on the trailing edge of the clock. Table 1 indicates the input signal, output signal in this simulation, output signal in theory and sequential analysis.  Figure 7. Results of the simulation Table 1. Input, output in the simulation and output in theory A contrast with those D flip-flop reported in some reference is summarized in Table 2. The delay of the quaternary DFF in this paper is about 74% reduction while the number of transistors increases a little by comparison with the corresponding binary implementation. The number of transistors decreases significantly while the delay becomes a little longer by comparison with the quaternary implementation using a 90nm CMOS process.

Conclusion
A novel quaternary D-type flip-flop based on multiple-valued current-mode is demonstrated by a circuit structure using DPC together with dynamic SCL. The delay of the quaternary DFF is improved significantly while the hardware complexity almost has no increase by comparison with the corresponding binary implementation. The threshold detector based on DPC makes it possible to obtain distinguishable multiple-value interval for high reliability and to obtain sufficient current driving capability for fast switching speed. The compactness of the quaternary circuitry presented makes it possible to cost little chip area and to decrease power dissipation. In addition, it is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential method of realizing high-performance VLSI systems.