{'fraction_non_alphanumeric': 0.03220338983050847, 'fraction_numerical': 0.01440677966101695, 'mean_word_length': 5.183246073298429, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Power-bandwidth trade-off on TSV array in 3D IC and TSV-RDL junction design challenges

Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for three-dimensional (3D) ICs. In this paper, we study the signal integrity issues of TSV-based 3D IC with high-speed signaling based on 3D electromagnetic field solver and SPICE simulations. Unlike other existing works, our study focuses on an array of TSVs and includes power and bandwidth trade-off between different signaling and termination techniques, such as single-ended, differential and reduced-swing signaling. From our study, to achieve the best power efficiency, unterminated single-ended reduced-swing signaling should be applied, while terminated single-ended signaling can provide the maximum bandwidth. Beyond TSV, critical design challenges for the junction structure between TSVs and RDL traces are also revealed and analyzed. Result shows that at 20GHz, the fanout-like junction structure could cause more than 10dB return loss (S11) degradation when changing TSV pitch from 50μm to 200μm and even contribute more insertion loss (S21) than the TSV itself.