{'fraction_non_alphanumeric': 0.026525198938992044, 'fraction_numerical': 0.015030946065428824, 'mean_word_length': 5.431818181818182, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs

Convolutional Neural Networks (CNNs) have been widely used in the field of computer vision. Due to the computational complexity of CNNs, their computational efficiency has become a major concern. Field Programmable Gate Array (FPGA) is an ideal embedded device for accelerating CNNs due to its parallelism and programmability. However, the key challenge is how to efficiently deploy CNNs on embedded platform FPGA. Based on the inherent parallelism of CNNs, this paper proposes an efficient parallel accelerator architecture with two processing element (PE) arrays to accelerate CNNs through layer-wise calculation. Using three tile strategies, the accelerator can be reconfigured to accelerate different CNNs, including VGG, and tiny-YOLO v2. Consuming 448 dsps, the experimental results show that the accelerator can reach a peak performance of 164.25 Giga Operations Per Second (GOPS) on VGG-16 and 138.77 GOPS on tiny-YOLO v2. Compared with previous research, this accelerator achieves enhanced power efficiency and performance density.