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A real time high definition architecture for the Variable-Length Reference Frame Decoder

Video coding systems, especially for high definition videos, require a large external memory bandwidth to encode a single video frame. Many modules of the current video encoders must access the external memory to read or write a huge amount of data. This process requires a large memory bandwidth, and also implies in large power consumption, since memory accesses are one of the main power demanding element in current digital systems. In this sense, this paper presents a real time high definition hardware architecture for the variable length reference frame decoder. This is the decoder used by the Reference Frame Context Adaptive Variable-Length Coder (RFCAVLC). The RFCAVLD (Decoder) was described in VHDL and synthesized to an Altera Stratix 4 FPGA. The proposed design is able to reach real-time encoding for WQSXGA (3200 × 2048 pixels) videos at 34 fps. The synthesis results achieved by the designed architecture indicate that this solution can be easily coupled to a complete video encoder system, with negligible hardware overhead and without compromising throughput.