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Automated S/TEM Sample Preparation for Semiconductor Process Support

The semiconductor industry has unquestionably entered the realm of nanotechnology. Critical dimensions of many features are specified in nanometers. Gate oxides are only a few nanometers thick. Barrier and seed layers for copper processes are not much more. Gate lengths are forecast at less than 20 nm by the end of the decade. Additionally, the drive to increase device density is leading to the adoption of FinFET and other new transistor designs that include complex three-dimensional structure. Even conventional planar CMOS designs now incorporate processes such as damascene interconnects that are inherently three dimensional. The combined need for higher spatial resolution and cross-sectional imaging of complex structures has led to a significant increase in the demand for scanning transmission electron microscopy (STEM) and (TEM) in semiconductor manufacturing operations.