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Deadlock Free Hardware Router with Dynamic Arbiter

Network on Chip (NoC) architecture is slowly replacing Bus-based Multicore architecture as it has better throughput, which improves the performance of the whole system. Till now a lot of architectures and required arbitration circuitry have been proposed but most of them are vulnerable to deadlock. While calculating the performance, this deadlock correction circuitry is often missing and the loss in performance due to packet-drops is not specified. In this paper, an advanced router based on odd-even routing scheme that is free from deadlock is proposed. Of course, with slightly decreased network throughput due to limited packet turns. Using this scheme, a high speed hardware router is designed. It is smaller in size as it does not need a deadlock correction circuitry but at the same time is 8.498 times faster than conventional network processor-based router. Although inflexible to software changes unlike software-based routers, this router can be used in high performance chip circuitry.