{'fraction_non_alphanumeric': 0.018924302788844622, 'fraction_numerical': 0.0, 'mean_word_length': 5.320754716981132, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A secure scan chain test scheme exploiting retention loss of memristors

Insertion of scan chains, as the most common DFT technique, provides a powerful way for the structural testing of integrated circuits (IC). However, it can be easily misused by unauthorized parties to acquire critical design information. Scan-based attacks are one kind of side channel attacks that reveal the comprehensive information of IC design noninvasively. Reports have shown many successful scan based side channel attacks against the main stream cryptographic systems, such as RSA, AES, etc. On the other hand, current countermeasure schemes are limited to either the incomplete protection of scan information or the massive redesign complexity. In this paper, we proposed a new secure scan chain design technique using a memristor array. By utilizing the natural and highly unpredictable degradation in the memristor cells, the proposed technique can provide the truely random scan confusion with little design overheads.