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InAs Nanowire MOS Capacitors

We present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr/Au metallization as one of the capacitor's electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.


1
The development of wrap-gate nanowire (NW) field effect transistors (FETs) is opening promising perspectives for future high-performance electronic devices [1,2]. NWs allow the integration of semiconductor materials with reduced lattice-matching constraints [3,4] and offer the intriguing possibility of growing III-V structures on Si substrates, thus introducing high-mobility and optically-active elements on a Si platform [5]. However, many of the key parameters of the NWs such as doping level and carrier distribution are still difficult to determine in a direct and conclusive way. For conventional FETs it is possible to take advantage of capacitance-voltage (CV) characterizations to determine, in a precise way, carrier concentration and interface properties of planar metal-oxide-semiconductor (MOS) stacks.
Similar measurements have been largely unavailable for semiconductor NWs because of the extremely small capacitance of these nanostructures (down to aF). Recent experimental studies showed that such a small capacitance can be detected using bridge measurements together with appropriate screening [6]. Here we demonstrate CV measurements of small arrays of vertical NWs, where the NW capacitance can be easily separated from the parasitic capacitance between the gate connection and the conducting substrate. Our vertical fabrication protocol is scalable and thus enables parallel processing, which is crucial for a systematic investigation of the device properties.
The device structure is presented in Fig. 1. NW arrays (Fig. 1a) were obtained by selfassembled growth in a chemical beam epitaxy (CBE) system. NW fomartion is guided by gold nanoparticles that are deposited on a doped InAs (111)B substrate [7]. A number of arrays was defined in parallel with various nanoparticle sizes to study radius dependance.  Differently from conventional MOS capacitors, here we expect the NW to become insulating in the depletion limit and C to approach zero instead of a finite depletion capacitance.
Indeed, here the observed saturation C → C 0 corresponds to the NW depletion, as proved by comparison with four bare pads of the same geometry (black curve). The presence of C 0 is not linked to the NWs and it is rather due to both the parallel capacitance between the pad and the substrate as well as the one between the probe tips and the substrate.
Hysteresis effects are analyzed in Fig. 2 The shift between C ↑ and C ↓ does not depend strongly on the sweep speed (about 150 mV/s in our case) and time-dependent measurements indicate that capacitances tend to relax from C ↑ (V ) towards C ↓ (V ) on a timescale τ ≈ 30 mins. We conclude that C ↓ (V ) results from an equilibrium distribution of charges at the capacitor's interfaces while a long-lived out-ofequilibrium distribution is present along C ↑ (V ). This effect can be evaluated quantitatively in a simple way if one assumes that trapped charges are located exactly at the NW surface: in that case the addition of a surface charge density ∆σ s will shift an ideal C(V ) curve as where S NW = 2πr NW L NW and L NW are the surface and length of the gated NW, respectively, while C ox is the oxide capacity 2πεL NW / log(1 + d ox /r NW ). The value of ∆σ s depends on the biasing history of the device, thus we obtain the different hysteresis cycles for different sweep swings. Figure 2b shows the average surface charge where ∆C is the capacitance swing of the cycle and we used an average L NW = 680 nm (from SEM imaging of the devices), ε = 15ε 0 [8,9] and C ox = 1.78 fF. The plot reports the loop integrals for the various device groups we studied: for V swings below ≈ 0.5 V we obtain ∆σ s < 1.0 × 10 11 cm −2 , which seems very promising for device applications of NW as wrap-gate transistors [10]. Note however, that the hysteresis in surface charge becomes much larger if the bias sweep extends further into the depletion region.
To further analyze the data, we performed detailed calculations for the capacitance on the basis of a Poisson-Schrödinger code similar to Refs. [11,12].  This shift can be attributed to the difference between the work function of Cr (4.5 eV) and the electron affinity of InAs (4.9 eV for zincblende lattice) as well as negative fixed charges (with areal density ∼ 8 × 10 12 cm −2 ) trapped in the oxide. As the electron affinity of the nanowire is uncertain due to the uncommon wurtzite structure exhibiting a larger band gap [13], this estimate for the density of fixed charges is probably too large. It is crucial to note here that we assumed that only electrons in the conduction band are able to contribute to the C(V ) at our frequency. We interpret the discrepancy between fit and experiments for V < 0 V as due to the effect of screening of slow trap states in the InAs gap [14], which indeed start becoming important at V ≈ 0 V in our simulations. Consistently with this interpretation, we observed experimentally that such discrepancies becomes larger as the frequency is decreased and a clear C(V ) step develops, similarly to what has been reported in previous studies on planar structures [15].