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MMC-based phase partitioning for data intensive applications

In this paper, we present a technique based on Matrix Model Computation (MMC) in order to improve the performance of embedded systems that run data-intensive applications. Unlike traditional techniques that consider a loop nest in a data-intensive application as one execution phase, the proposed technique aims at efficiently dividing a loop nest into multiple execution phases in order to improve the utilization of dynamic memory management schemes in a more efficient way. The target architecture is an embedded processor with software-managed on-chip memory components with multiple levels in the hierarchy. The experimental results presented using single-core embedded architecture show significant performance improvements over available dynamic memory management schemes.