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A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters

A high-speed and high-resolution comparator intended to be implemented in a 12 bit 100 MHz pipeline analog-to-digital converter (ADC) for frequency wireless local area network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mum TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8 ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0 mW of power with 5.0 V voltage supply.