{'fraction_non_alphanumeric': 0.018393030009680542, 'fraction_numerical': 0.003872216844143272, 'mean_word_length': 5.422360248447205, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Implementation of an Efficient Multiplier Architecture over a Conventional Methods using Ancient Indian Vedic Sutra

Fast multiplication is very important in processing of digital signals like DSP for convolution, Fourier Transform, etc. Many conventional methods are used for designing a multiplier for processing a digital signal. In this paper, A fast method for multiplication based on Ancient Indian Vedic mathematics is proposed. The whole of Vedic mathematics is based on 16 sutras (formulae). Among the various methods of multiplication in Vedicmathematics, Urdhava Tiryakbhyam (Vertically and Crosswise) is discussed in detail. This is the general multiplication formula applicable to all cases of multiplication. For implimentation of a efficient Architecture simple Boolean logic is combined with Vedic formulas, which reduces the partial products and sums generated in one step. The coding is done in VHDL and synthesis is done using Xilinx ISE 9. 1i simulator. Results are compaired with several conventional techniques.