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Modifying VM Hardware To Reduce Address Pin Requirements

This paper presents a simple modification of a computing system’s virtual memory hardware that can sharply reduce the number of pins required to transmit address information between a single chip processor and off-chip memory. By partitioning the virtual memory system’s translation lookaside buffer so that the virtual page numbers are stored in a cache on the processor chip and corresponding real page numbers are stored in a set of registers at the memory, it becomes possible to transmit a small index from the processor to memory instead of the page nmnber itself. Trace driven simulations indicate that this technique can significantly reduce the number of pins required to transmit address information between processor and memory. Because this technique makes use of existing virtual memory hardware, it can eliminate address pins without significantly changing computing system design, cost, or performance.