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A NOVEL FOUR QUADRANT CMOS ANALOG MULTIPLIER FOR ARTIFICIAL NEURAL NETWORKS

A novel four quadrant CMOS analog multiplier to use in artificial neural network designs is presented. Its major advantage over other four-quadrant multipliers is that it is combination of low power consumption and high frequency response. The proposed multiplier was realised by using square-law of the MOS transistor operating in the saturation region. Therefore, four transistors constituting the input cell of the multiplier operate in the this region. Their sources and gates are connected to the ground to cancel the body effect. The simulation results show that the proposed circuit has a 2.98 mW power consumption at 3.3V supply voltage. 3dB Bandwidth is up to about 23MHz and THD is about %0.48 for Vp-p=0.7V at 100KHz. The low power consumption and high 3-dB bandwidth make it suitable for use in the implementation of artificial neural networks.