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Variable-accuracy bit-serial multiplication with row bypassing for ultra low power

This paper revisits bit-serial computing and proposes a novel near-threshold serial multiplier with row bypassing and variable precision. A key challenge in the design of Internet-of-Things sensors is to maintain low energy consumption for longer life time. Variable-accuracy computing has attracted significant interest over the decades as a means of balancing energy and accuracy. To illustrate the proposed technique, a design has been developed and synthesised using the ST 65nm CMOS logic process. Results show that at low sampling rates the proposed design significantly outperforms conventional bit-serial and state-of-the-art parallel implementations in terms of both average power and total energy consumption, despite the longer operation time of the bit-serial design. Compared with conventional bit-serial architecture, a few number of extra gates are needed to achieve additional energy savings via the dynamic reduction of bit precision.