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Simultaneous wire sizing and wire spacing in post-layout performance optimization

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By defining a cost function to trade-off between interconnect delay and routing area, we formulate wire sizing and wire spacing problem (WSSP) into a constraint-optimization problem and develop a heuristic algorithm to solve it. The preliminary experiments are promising.