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IR Aware Cell Placement and Clock Tree Performance Optimization in FPGA Memories

Field Programmable Gate Array (FPGA) Memories are synchronous pipelined circuits that rely on the distribution of the clock to achieve the timing requirements. The density of FlipFlops (FFs) are higher in such designs. This paper discusses a novel method and algorithm for reducing the simultaneous switching current demand to address IR hotspots by the staggered placement of these FFs. The higher current demands from a small section of high resistive Power Distribution Network (PDN), is redistributed to other unused sections of the Network. This approach improves the performance of clock network distribution by reducing the clock insertion delay and max skews. Application of proposed algorithm reduces IR-drop by 32.5% and improves clock insertion delay by 36.5%.