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A novel framework for disparity estimation in FPGA

Real-time Stereo vision is an immerging technique inspired from human visual system that computes the disparity between correspondence points in multiple images captured from corresponding camera. High resolution images are necessary to provide good quality auto stereoscopic displays which can be used to produce stereo without the need of 3-D glasses. The aim of this paper is to calculate the disparity map for stereo vision using local window based matching algorithm known as SAD (Sum of Absolute Differences). By using FPGA in implementation of system hardware, pipelining and parallelism is achieved. Stereo matching acts as a key function in disparity estimation. It is used to calculate the depth map estimation from stereo image pair. Zedboard ZYNQ XC7Z020 was used for real time hardware implementation with 15 disparity levels. The system verification was done using Middlebury Benchmark Dataset in Xilinx ISE Design Suite 14.2.