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GaAs MESFET with Source-Connected Field Plate for High Voltage MMICs

In this paper we show the results of a source-connected field plate development effort for MMIC-compatible planar HV MESFETs. It is shown that best power performance is obtained from this process using devices incorporating both gate-connected and source-connected field plates. INTRODUCTION Over the past decade, the maximum operating voltages of microwave transistors based on compound semiconductor technology have been steadily increasing, enabling the design of higher performance electronic systems at lower overall cost. Regardless of the semiconductor material used, field plates are a common feature of high voltage FETs. The specific implementation of a field plate its geometry, resistivity, dielectric composition and thickness – can have a profound impact on its influence over device operation. Another equally important variable is the connectivity of the field plate – whether it is electrically connected to the gate, the source, or even externally biased as a fourth terminal of the device. Despite numerous reports on various field plate configurations [1-5], remarkably little has been published directly comparing the effects of different field plate configurations [6]. Field plates enhance high voltage operation through multiple mechanisms. One mechanism is the influence on the electric field at the drain edge of the gate electrode. By reducing the field at this location, the off-state gate-drain breakdown is increased. This is exclusively an electrostatic effect; therefore, either source-connected field plate (SCFP) or gateconnected field plate (GCFP) devices should exhibit this improvement. Another mechanism is the mitigation of surface trap effects, resulting in higher RF current in the device. RF modulation of a field plate could have a significant effect upon this mechanism which would represent an advantage for GCFP FETs. Both of the aforementioned mechanisms depend strongly upon the quality of the semiconductor passivation. A third mechanism, not exclusive to high voltage operation, is the influence on FET capacitances. The desired effect is the reduction of gate-drain capacitance through shielding. This is an electrostatic effect clearly not obtainable with a GCFP alone. Of course, the introduction of parasitic MIM capacitance between a SCFP and gate, or the increase in electrical gate length due to the MIS element of a GCFP causes unavoidable detrimental effects from the increase of gate-source capacitance. Achieving improved device performance with field plates requires careful selection of the field plate variables. While these effects can be evaluated through 2-dimensional device simulation, doing so accurately in a predictive fashion is exceedingly difficult owing principally to uncertainty in the parameters associated with the non-idealities of the materials, especially traps in the GaAs, both in the bulk material and at its surface. This leaves empirical evaluation as the only practical approach. This paper will report on the results of such an investigation into the effects of sourceand gate-connected field plates on planar, ion-implanted GaAs MESFETs. DEVICE STRUCTURE The high voltage MESFET device technology used in this work is Tyco Electronics’ HVMSAG process. This process is an extension of 10V MSAG power FET technology, based on a refractory metal gate, planar, ion-implanted GaAs MESFET. The HVMSAG FET achieves operation up to 28V through optimization of active layer parameters and spacings and gate structure, including a GCFP, as shown in Figure 1. This HV FET has been developed as a robust, highly manufacturable process for fabricating high voltage power MMICs operating at S-band and lower frequencies [7]. Figure 1. Simplified cross section of the HVMSAG gateconnected field plate ion implanted MESFET. To investigate the possibility of improving performance of the HVMSAG FET through the addition of a SCFP as shown in Figure 2., two new mask layers were added to the process flow: a metallization layer for the SCFP electrode and a dielectric glassivation layer for this new metallization to provide environmental protection equivalent to the existing process. In this structure, the MIM capacitor dielectric layer of the existing MMIC process flow serves as the interlevel dielectric isolating the SCFP from the GCFP. GCFP gate n n+ n+ ohmic Drain