{'fraction_non_alphanumeric': 0.019966722129783693, 'fraction_numerical': 0.0033277870216306157, 'mean_word_length': 5.201030927835052, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reconfigurable Vector Extensions inside the DRAM

Near-data processing is emerging as a response to the low memory bandwidth and the high energy costs associated with the data transfer between the processor and the main memory. Proposals that move the execution of vector instructions to the DRAM device present good trade-offs in terms of performance, energy consumption and area. Since these previous proposals usually operate at the frequency of the DRAM, they lose opportunities for improvements due to the long clock period of the memory devices. In this paper, we propose Reconfigurable Vector Extensions (RVX), which use Coarse-Grained Reconfigurable Arrays (CGRAs) to execute vector instructions inside the DRAM. Our mechanism reconfigures the functional units inside the memory in order to combine them and thereby reduce the operation time of the near-data instructions, fully leveraging the potential of near-data processing in the main memory. Comparing to previous near-data processing approaches that move vector instructions to the DRAM, our proposal enables performance gains of up to 31% and reduces the energy consumption by up to 76% of the functional units inside the memory device.