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A Bit-Parallel Pipelined Multiplierless DCT

The central idea of the implementation proposed in this paper is the binary-lifted DCT that based on Loeffler's factorisation. The design is focused on a multiplierless 1-D DCT. The realisation is also applicable to a 2-D computation. Effect of image size and word length are investigated and reported. Architecture with true DCT compatibility is also suggested. Word length of 12 – 16 bits show enough resolution for general applications. The data rate can be increased by parallelism and pipelining. Of its compact area (or gate counts), the implementation suits widerange applications.