{'fraction_non_alphanumeric': 0.02389843166542196, 'fraction_numerical': 0.0074682598954443615, 'mean_word_length': 5.203703703703703, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation

As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.