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Physical layer design of nanoscale silicon photonic interconnection networks

In the continual drive toward improved microprocessor performance, power efficiency has emerged as a prime design consideration. At the chip scale, the trend toward multi-core architectures and chip multiprocessors (CMPs) for driving performance-per-watt via increases in the number of parallel computational cores is dominating new commercial releases. The role of the interconnect and associated global communication infrastructure is becoming central to the chip and ultimately computing system performance. On-chip photonic communication has been recently explored to address the communication requirements in future high-performance CMPs. We have developed a photonic network simulation environment that uniquely incorporates physical layer silicon photonic device models. We report on the design optimization of the network micro-architecture layout and photonic switching fabric organization. The event-driven network simulator establishes physical layer metrics for the silicon photonic devices and provides a measure of the network performance-per-Watt requirements derived from device characteristics.