{'fraction_non_alphanumeric': 0.02187182095625636, 'fraction_numerical': 0.003051881993896236, 'mean_word_length': 5.690476190476191, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A low-skew, low jitter receiver circuit for on-chip optical clock distribution

As deep sub-micron CMOS technology continues to scale, typical H-Tree and other balanced clock distribution schemes are becoming increasingly vulnerable to greater variation, propagation delay, crosstalk and other parasitics introduced by decreasing gate lengths and line widths. An alternative to balanced electrical clock distribution networks is the use of an optical distribution network at the global level. Light can be distributed to multiple receivers across the chip with low skew. Efficient and variation-robust optoelectronic conversion can enable this technology to become a viable alternative. However, variation in the optical network can and will effect the optical signal received at the receiving photodetector. Thus, variation-robust optical receiver circuit design and analysis is a critical step toward implementation of on-chip optical clocks. A third-generation receiver circuit has been designed using a fully-differential architecture and operates at 2GHz. The advantages of differential signaling are primarily common-mode and power-supply rejection, enabling high-bandwidth amplifiers. Offset compensation circuitry has been developed to counteract mismatch effects common in modern deep sub-micron processes while replica feedback biasing and a process-compensated current reference developed by Intel have been incorporated for stable biasing. Using the mentioned circuit techniques, variation and noise analysis, which quantify receiver skew and jitter due to individual sources of variation and noise, reveal ∼120ps of skew and ∼35ps of worst-case jitter. The receiver circuit and associated test circuitry has been laid out and awaits fabrication. Thesis Supervisor: Duane S. Boning Title: Professor of Electrical Engineering and Computer Science Thesis Supervisor: Michael Perrott Title: Assistant Professor of Electrical Engineering and Computer Science