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Combined simulation and emulation setup for complex image processing algorithms in VHDL

Developing cost-efficient dedicated hardware implementations of complex, high-throughput applications remains a challenging task. Typically high-level description languages (such as C) are used to develop these applications. The translation of these high-level descriptions into VHDL and hardware requires a systematic development and test methodology.
 A clear separation between communication and computation enables extensive testing of individual components of the application. In order to reduce testing time, a combination of simulation and emulation on a fast prototyping platform is established for each of the components. A testbench, running on the host PC, provides the stimuli both for the simulation as well as for the emulation. By differentiating the simulation and emulation environments only by their communication link with the host PC, a seamless transition between both environments is enabled. As a result of this approach, the debug cycle during system integration is minimized.
 The proposed methodology is used to validate the FPGA implementation of a denoising video application supporting up to 1080p @ 60 Hz. Measurements using the proposed setup for this denoising application show a speed up of more than a factor of 250 of the emulation compared to the simulation of the hardware.