{'fraction_non_alphanumeric': 0.015137180700094607, 'fraction_numerical': 0.0, 'mean_word_length': 5.335329341317365, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Toward Accurate Performance Evaluation using Hardware Counters

On-chip performance counters are gaining popularity as an analysis and validation tool. Various drivers and interfaces have been developed to access these counters. Most contemporary processors have between two and six physical counters that can monitor an equal number of unique events simultaneously at fixed sampling periods. Through multiplexing and estimation, an even greater number of unique events can be monitored using round-robin scheduling of event sets. When program execution is sampled in multiplexed mode, the counters are interfaced to a subset of events (limited by the number of physical counters) and are incremented appropriately. At this sampling slice, the remaining events in the set do not access the counters, but the respective counts of these events are estimated. Our work addresses the error associated with the estimation of event counts during multiplexed mode. We quantify this error and propose new estimation algorithms that result in much improved accuracy.