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Soft IP Compiler for a Reed‐Solomon Decoder

In this paper, we present a soft IP compiler for the Reed‐Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed‐Solomon decoder with appropriate sub‐architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.