{'fraction_non_alphanumeric': 0.027114967462039046, 'fraction_numerical': 0.0, 'mean_word_length': 5.640287769784172, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multi-core chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In this work, we illustrate the sensitivity of various applications on a theoretical four-socket system to the latency of their coherency traffic, and show that current solutions, such as Quick Path Interconnect (QPI) and HyperTransport (HT), could benefit greatly from a lower latency communication medium. Then, we propose a silicon photonic inter-chip network that achieves very low-latency and falls within a reasonable power budget.