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Impact of Different Technology Node on the Delay and Power Dissipation of 6T SRAM Cell

In this paper, the timing performance and power dissipation of 6T static random-access memory (SRAM) cell for different technology nodes are observed, and the impact of varying supply voltage on each technology node is also analyzed. The simulation of the 6T SRAM cell is done using the Pyxis Schematic tool by Mentor Graphics. For this simulation, different technology nodes, i.e., 130nm, 90nm, 65nm, and 45nm BSIM CMOS process, are used. Finally, it summarized the performance of the 6T SRAM cell in terms of propagation delay, power dissipation (static and dynamic power), and power delay product (PDP).