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UIS-Failure of DMOS Power Transistors

It is a major concern in the design of power devices to achieve the largest possible SOA. The latter is limited by the failure of the device under specific operating conditions. It is not always clear, however, how the device actually runs into a failure mode and thus, which design and technology parameters influence the SOA. The SOA for DMOS power transistors under normal operation (i.e. ) has been addressed elsewhere [1]. Also, the failure under unclamped inductive switchingconditions (UIS) has been attributed to the switching of the parasitic BJT caused by the rise of the intrinsic base resistance with temperature [2]. As our numerical analysis shows, this explanation is not complete; the failure is temperature-driven indeed, but the increase of the base resistance is only one contribution to the failure mechanism. For the specific device investigated, it can be shown that the increase in intrinsic carrier density with temperature is an important key to understanding the failure under UIS conditions, unless the current is extremely high. Moreover, since the actual device consists of several hundreds DMOST-cells, an uniform current distribution among all cells must be ensured in order to safely dissipate the generated heat. However, there exists an unstable operating point, where a slight deviation from the uniform current distribution leads to current crowding concentrated in the hot spot occurring in one single cell of the chip array. The device consists of an array of several hundred cells. Such a cell is schematically depicted in fig. 1; due to symmetry, only one half of the structure is shown. Several partial current flows are indicated which are needed in the further analysis.