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AN EFFICIENT FPGA IMPLEMENTATION OF AES ALGORITHM

The Advanced Encryption Standard can be programmed in software or built with pure hardware. But Field Programmable Gate Arrays (FPGAS) offer a faster and more customizable solution, since the entire algorithm can be executed in a single tick of clock cycle. This research deals with the implementation of AES algorithm in FPGA using Verilog Language. Software is used for simulation and optimization of the synthesizable Verilog code. All the transformations of both Encryption and Decryption are simulated using an iterative design approach for minimizing the hardware consumption. The design uses an iterative looping approach with block and key size of 128 bits and lookup table implementation of S-box. The FCSR used for key generation make the algorithm more secure, and the usage of Vedic multipliers instead of normal multipliers increases the throughput. This gives low complexity architecture and easily achieves low latency.