{'fraction_non_alphanumeric': 0.023121387283236993, 'fraction_numerical': 0.0038535645472061657, 'mean_word_length': 4.772222222222222, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Area-aware optimization of XOR-AND Graph based on Reed-Muller logic expansion

XOR-AND Graph (XAG) is a logic representation method for Boolean functions. A major advantage of using XAG is that it is efficient for cryptography and security applications in which the number of AND gates relates to the multiplicative complexity. A Reed-Muller logic expansion is used in this paper to develop an area-aware optimization method for XAG. The logic functions can be represented in several ways by Reed-Muller logic based on different polarities. To find an area-efficient representation of the logic network, the cuts of the logic network are enumerated and then the mixed polarity conversion algorithm is utilized. When the representation is improved over the existing one, we replace the existing cut. Following the experimental results over EPFL benchmark suites, the proposed method can optimize XAG size. Compared with the best known results, we achieve a reduction of up to 50% and an average reduction of 14% in the number of XOR gates.