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An Enhanced DSP Block Architecture for FPGA Supporting Multi-operands Addition Operation

The DSP block can effectively improve the performance of arithmetic operation in FPGA. However, the commercial FPGA does not directly support multi-operands addition operation which is used in multiple application scenarios such as FIR. Using traditional DSP block to realize multi-operands addition operation will take up a lot of logic resources and affect the performance. In this paper, three Multiplier or Addition Blocks (MABs) are proposed, which enable the DSP block to directly support multi-operands addition operation with high performance. Besides, an index to measure the area utilization rate of DSP block performing addition operation is proposed. Compared with the traditional method, the design proposed in this research can realize multi-operands addition operation by only using DSP block without occupying other logical resources in FPGA. Based on Stratix-IV DSP block architecture, this experiment replaces multiplier with the MABs proposed in this paper. We use SMIC 40nm standard CMOS process to design and complete the implementation of the overall circuit. The experimental results show that the proposed design can realize two sets of eight 18-bit signed number addition operation at the cost of additional 7.48% area without affecting the existing functions of DSP block and the performance can reach 500MHz.