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The application and optimization of SDRAM controller in multicore multithreaded SoC

An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed controller reduces execution time by up to 48% than the original structure and improves the throughput of SDRAM data bus by 29%.