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Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack

As device-scaling challenges increase, three-dimensional (3D) integrated circuits (ICs) are receiving more attention for system performance enhancements, due to their higher interconnect densities and shorter interconnect lengths. However, because of the limited contact area and the higher circuit density, the cooling of 3D ICs is more challenging. In order to assess appropriate cooling solutions for 3D chip stacks in various uses, we need better understanding of the total thermal resistance of 3D chip stacks. This calls for precise thermal resistance measurements and thermal modeling for each component of a 3D chip stack. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. With regard to the thermal resistance measurements of interconnections, Yamaji et al. found it difficult to measure the thermal resistance of interconnections with the laser-flash method and pointed out that care was necessary for uniform temperature distribution in the sample when using the laser-flash method on heterogeneous specimens, such as stacked chips with interconnections. Considering this concern, we use a steady-state method for the thermal resistance measurements of the interconnections. The thermal resistance of 200μpitch-C4 (Pb97Sn3) joined samples is measured and the thermal conductivity of C4 is derived to be 18 – 24 W/mC. Also the thermal resistance of a silicon with various interconnection pitches and diameters is modeled and the relationship of thermal resistance to interconnection pitch and diameter is obtained. The thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.