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Endurance enhancement of write-optimized STT-RAM caches

Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high density, and near zero leakage, which are highly desired for on-chip caches. A few drawbacks of STT-RAM such as high write latency and limited endurance, have to be taken care before it can replace SRAM at the LLC. Prior works have either tried to optimize the write latency or endurance. In this paper, by considering write-optimized STT-RAM, we propose endurance improvement techniques by reducing the maximum number of writes, global write variation, and the average number of writes. We take care of low retention time of write-optimized STT-RAMs using a refresh mechanism. We employ refresh-aware cache replacement policies wherein the cache blocks that are about to expire are preferred to the recently refreshed cache blocks. This refresh-aware policy, when combined with the recency information of the cache blocks, enhances both performance and endurance of STT-RAM LLC. We show that our refresh-aware policy achieves the maximum lifetime improvement of 32.5% for single-core and 70.7% for muti-core compared to STT-RAM with no wear leveling. When we combine recency information with our refresh-aware policy, there is a slight improvement in the performance.