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Design of 128-Bit of Magnitude Comparator Using DPL Logic

This paper proposes the design of 128 bit magnitude comparator with double pass transistor logic (DPL). In higher bit comparator, due to successive comparisons its performance degrades. So DPL overcomes the major problem of voltage degradation and noise margin, which helps in exact comparisons of higher bits. 4-bit and 8-bit comparator modules are used to implement 128 bit of magnitude comparator. This 128 bit comparator is designed in cadence environment using gpdk 180nm technology with power dissipation of 4.27mw and a delay of 1.01ns.