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Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node.

In this paper, lateral gate-all-around nano-plate transistors (NP-FETs) for 3.5 nm technology node were optimized and compared with other nodes such as 7 nm and 5 nm node devices. The transistors' electrostatic was analyzed using a 3D TCAD simulation. We firstly optimized physical parameters such as channel radius and thickness. The NP-FETs for 3.5 nm node had better gate controllability due to smaller channel thickness and therefore showed an advantage in subthreshold swing (S.S.). However, parasitic resistance and capacitance, and low bias condition of scaled device lowered on-current level. These problems of smaller device were also related to limitation of RC-delay performance. Accordingly, the scaled device with optimized physical parameters showed ~1% decrease in delay performance compared to 5 nm node device. In order to improve RC-delay performance, trenched contact method and channel strain engineering method were separately applied for the same device. For each engineering technique, the on-current boosting was successful, showing ~14% faster RC-delay performance with strain engineering and ~18% faster RC-delay with trenched contact method.