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An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a small channel-to-channel crosstalk and low ambient temperature dependency.


Introduction
The Large High Altitude Air Shower Observatory (LHAASO) is a multipurpose complexity which consists of different detectors for high energy gamma ray and cosmic ray detection [1]. A Water Cherenkov Detector Array (WCDA) in LHAASO will be built to survey the gamma ray sources at energies higher than 300 GeV. The WCDA is configured with four 150 m × 150 m water pools adjacent to each other. Each pool has 900 PMTs which face upward to observe the Cherenkov light produced in water by secondary particles induced by air showers [2].
The PMT signals are transmitted to the electronics via 30m coaxial cables. The signal dynamic range of the PMT is from 1 P.E. to 4000 P.E. Within the large dynamic range, both precise time and charge measurement are required [3], as listed in Table 1. These requirements bring quite a few challenges in the readout electronics design. Firstly, the PMT signal varies from 1 P.E to 4000 P.E. and thus a large dynamic range signal processing capability of is required. Secondly, high time and charge measurement resolution within the full dynamic range is challenging, especially for 1 P.E signal, the peak current of which is as low as 60 μA (it will be further attenuated by the 30-m cable). This requires the readout electronics to have a sufficiently low noise level.
Lastly, considering a 1-4000 dynamic range, the reflection of large signals would influence the measurement of subsequent small signals; therefore, high precision impedance matching is required.
However, the performance of these ASICs is not in full compliance with the requirement of WCDA in LHAASO.
In this paper, we present the design of a front-end ASIC for the time and charge measurement, to fulfill the requirement of LHAASO WCDA, with all the analogue circuits integrated within one chip. Details will be described in the following sections.

Basic structure of the ASIC
The detailed diagram of the anode channel is shown in Fig. 2. The anode input current signal is converted to a voltage signal on the termination resistor. Then this voltage signal is split into two paths inside the ASIC. One path is for time measurement and the other is for charge measurement.
In the time measurement part, the signal is amplified by two amplifiers, and outputs of these two amplifies are fed into two discriminators, for which two different thresholds are selected. The thresholds are equivalent to 1/4 P.E. and 3 P.E. (user controlled in the test), respectively.
The above design is aimed to avoid time resolution deterioration caused by noise or interference in the baseline of large input signals.
The pre-amplifier of time measurement part adopts a non-inverting amplification structure which features a high input impedance to avoid degrading the impedance matching precision, and it contains a differential input Operational Transconductance Amplifier (OTA), marked as A1 in Fig. 2.
As for the charge measurement part, the input signal is firstly amplified by the OTA A2 which has a smaller bandwidth than A1. Then the amplified signal is filtered by an RC 4 shaping circuit, and then driven output by a class-AB buffer which has a rail-to-rail driving capability.
The shaper employs a four-order passive low-pass filter with three OTAs as the isolation stages; with this structure it is easier to achieve good stability compared with active filters, e.g., Sallen-Key filter [11].

Pre-amplifier design
Considering the high precision and large dynamic range requirements, the pre-amplifier should have the feature of low noise and large output swing. Since the noise and output swing of pre-amplifier is dictated by the OTA, the performance of the OTA should be optimized carefully.
The OTA A1 (in Fig. 2) employs two-stage amplifier with miller compensation structure (as shown in Fig. 3).
The first stage incorporates differential input pair with active current mirror loads and the second is configured as common-source stage. As stated in the literature [12], the input equivalent noise density is given by the following denote the power spectral density of resistor R 1 , R 2 and OTA, respectively).
For a large close loop gain 2 And the integrated input RMS noise can be calculated as In Eq.
(3) f 3dB denotes the 3 dB bandwidth of the preamplifier, which is dictated by the input signal spectrum.
And the 3 dB bandwidth of pre-amplifier is optimized to be 150 MHz within which 99% power of the PMT waveform is concentrated through FFT analysis. Therefore the Eq. (3) implies that small input RMS noise can be obtained by lowing the input RMS noise density. The noise density of OTA and R 1 can be approximately expressed as In Eq. (4) g m1 and g m3 denote the transconductance of input The input noise contribution of OTA is designed to approximate to the amount of R 1 , which balances the total input noise density and power dissipation . Through simulation the transconductance of input pair and current mirror load are optimized to be about 6 mS and 2 mS, respectively, when the power dissipation is 3.6 mA Fig. 4 shows the simulated results for gain and equivalent input noise density of pre-amplifier. The simulated bandwidth is 146 MHz at the gain of 7 and total equivalent input noise is estimated to be 50 μV RMS (from DC to 1 GHz), which corresponds to 1/60 P.E., well beyond the measurement requirement even for 1 P.E. signal. Moreover, the OTA A1 has a high Power Supply Rejection Ratio (PSRR) of 62 dB, which is better than that of the single-ended input OTA often employed as the low noise pre-amplifiers [4][5][6][7][8]. In addition to low noise requirement, the large output swing also demands the OTA of pre-amplifier is power hungry. Therefore the optimization of OTA are trade-offs between noise, power consumption, voltage headroom and bandwidth.

Low temperature drift design
The actual environmental temperature of the experiment will vary from 0 ºC to 50 ºC and temperature variation may influence the performance of the ASIC.
Therefore a low temperature drift design for this ASIC is necessary. For charge measurement, the small signal transfer function of shaping circuit is a low-pass filter with gain about 40 dB, and both the gain and bandwidth may vary with temperature. By using the transfer function of the shaping circuit and inverse Laplace transform, the output peak value for RC n filter can be calculated as: where A v and τ is the gain and time constant of the shaping circuit, respectively. Furthermore, the bandwidth is inversely proportional to τ, hence the peak value of output is proportional to the Gain Bandwidth Product (GBP).
The overall gain of shaping circuit equals to the product of close loop gain in each amplifier stage. And the close loop gain transfer function of single amplifier can be calculated as: Eq. (7)    The gain and bandwidth are optimized to have negative and positive correlation with temperature, respectively, therefore the overall GBP changes very little with temperature (as shown in Fig. 7). According to Eq. (6) the temperature insensitive GBP implies that the shaping circuit output would have very weak dependency with temperature. The overall charge measurement temperature drift will be presented in the next section.

Output buffer
To drive large swing shaping signal out of the chip, the shaping circuit demands an analog rail-to-rail output voltage buffer with high driving ability. The shaping signal will be driven to an external ADC through cable in the test.
Hence the resistive load of output buffer is 50 Ω and parasitic capacitance is estimated to be about 10 pF. For an output peak reaching to 1.8 V, the output buffer needs to provide 36 mA dynamic current. To reduce the quiescent power dissipation of output buffer, the output buffer employs class-AB structure which is shown in Fig. 8 [13,14].

Simulation
A series of simulations were conducted to evaluate the performance of this ASIC.  As for charge measurement, the peak value of the shaper output corresponds to the input charge. We quantified the peak value with ideal a 12 bit 2 V input range ADC to obtain the charge transfer curve as shown in Fig. 14. By utilizing two readout channels, the charge measurement can cover 4000 dynamic range with a sufficient overlap. Moreover, by simulating the output noise of shaper, the simulated charge resolution can be obtained. As shown in Fig. 15 the simulation results are better than 5% in the full dynamic range.  Fig. 16, Fig. 17 and Fig. 18 show the temperature dependency of time resolution, charge transfer curve and charge resolution, respectively. Within the temperature range of 0 ºC to 50 ºC, time resolution remains better than 350 ps, charge measurement results vary within ±1% and charge resolution remains better than 6%. After fabrication of the ASIC, we set up a test platform in the laboratory and conducted a series of tests, which will be presented in the next sections.

Circuits performance 4.1 Laboratory test set-up
A dedicated test board was designed to test this ASIC.
The block diagram of test platform is constructed as shown in Fig. 19. We used an arbitrary waveform signal generator      The ASIC is marked in the middle with a yellow rectangle.  Fig. 22 are waveform test results of the kernel nodes in the ASIC, which concord well with those in Fig. 11. The test results indicate that this prototype ASIC functions well.

Noise performance
The noise performance is investigated by measuring the output noise (RMS value) of three main blocks: pre- The results are listed in Table 2 well, which indicates that this ASIC has good noise performance, beyond the application requirement (30% charge resolution @ 1 P.E.).

Time measurement
As shown in Fig. 19, the signal source generates two synchronous signals: one is fed into the evaluation board through an attenuator as the input signal; the other is sent to the oscilloscope as a reference signal. The delay between the "T_out" in Fig. 19 and the reference signal is

Charge measurement
As shown in Fig. 19, the shaper output "Q_out" is imported to an ADC on the backend digitization board.
With the logic of the FPGA device in the same board, the peak value of the ADC output signal can be obtained, which correspond to the charge measurement results.   Table 2) into account, and hence it has a greater impact on the dynode channel charge resolution.

Crosstalk
Channel isolation can be evaluated by counting error hits caused by crosstalk due to neighboring channels. No error hits or charge performance deterioration was observed when large signals are imported to the neighboring channel. It indicates that this ASIC achieves a good channel-to-channel isolation performance.

Ambient temperature dependency
We also conducted temperature drift tests on this ASIC.
The test temperature range is tuned from 0 ºC to 50 ºC which covers the temperature variation of the real experiment environment.

Conclusions
This paper presents the design and testing of an analogue front-end ASIC prototype for PMT signal readout. This ASIC aims to fulfill precise time and charge measurement requirement in LHAASO WCDA. The circuits are optimized to be low noise, high dynamic swing, and temperature insensitive. A series of tests have been conducted to evaluate its performance. Test results indicate that the time resolution is better than 350 ps in the full dynamic range and charge resolution is better than 10% @ 1 P.E. and better than 1% for input signals larger than 300 P.E. Meanwhile, this ASIC has been proven to have high channel-to-channel isolation and weak ambient temperature dependency.