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DVFS-enabled power-performance trade-off in MPSoC SW application mapping

Heterogeneous MPSoCs are seen as the solution to tackle performance and power demands in the embedded domain. Their HW and SW complexity necessitates an automatic approach to find the most efficient task-to-processor mapping of parallel applications. Tight power budgets require efficient task mapping, and optimally setting the voltage and frequency of each processor. This paper proposes a novel heuristic that minimises the average power consumption, while meeting performance constraints. Integrated into an industrial SW mapping framework, the applicability is validated using three different case studies and representative benchmarks. Moreover, the power-performance trade-off is discussed. A comparison with the optimal solution complements the evaluation, revealing a loss of 19% by the heuristic, but 700× faster execution.