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Reducing design verification cycle time through testbench redundancy

Design flows for modern-day system-on-chip (SoC) designs focus on reducing the design cycle time, but not on design verification time. Nearly 70% of SoC design cycle time is consumed by design verification (Raynaud, 2003). Most functional verification happens through simulation. This paper proposes a technique by which the simulation times of time consuming verification steps can be reduced. The proposed technique exploits the testbench redundancy during functional simulations to reduce simulation time. We demonstrate how the testbench redundancy can be exploited to gain valuable cycle time during memory BIST simulations.