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Reduced complexity recovery architecture in QAM software receiver

In this paper, we present the design and implementation of a new architecture for phase and frequency synchronization in coherent QAM demodulator used in modern digital communication systems. This architecture utilizes the non data aided carrier recovery for synchronization, which is based on the DC error tracking behavior of a control loop. We exploit the hardware-software co-design in this architecture, which makes it flexible for different design parameters. The early-late gate technique as a conventional symbol timing recovery is also addressed within the proposed framework. Hardware-software implementation in field programmable gate array (FPGA) and its issues are presented for different data rates.