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Concurrent Optimization of Technology and Design for Nano CMOS

As we move to 45nm and beyond, our ability to manage the need for increased integration together with the drive for higher system performance and lower power presents many challenges to technology and design. It has become no longer possible to consider technology advancement without considering the overall optimization of the transistor and circuit design for full entitlement together with the cost of the chip. This paper looks at the key challenges and technology discontinuities that we face as we move into the nano CMOS regime, and some of the approaches being developed to address them