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High-performance fully-recessed enhancement-mode GaN MIS-FETs with crystalline oxide interlayer

In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ∼ 780 °C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).