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Enhancing the lifetime of STT-RAM with MRU replacement algorithm

Recent trends on Emerging Technologies of Non-Volatile Memory (NVM) were considered as better alternatives for SRAM. Spin-Transfer Torque Random Access Memory (STT-RAM) is a type of NVM having less leakage power and high cell density. Besides its advantages, NVM has low write endurance and high error rates. This paper proposes a mechanism of enhancing the lifetime of STT-RAM. The Sliding mode based ECC architecture has been proposed to evenly distribute the write of ECC bits across data bits. This is necessary because the ECC part which is used to maintain reliability of NVM will wear out early as compared to the data part, since the write are unevenly distributed. In the proposed method, the MRU replacement algorithm has been implemented to improve the lifetime of the cache block and it was observed that the improvement was 4x when compared to the LRU replacement algorithm.