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Performance evaluation of time and frequency domain equalizers

This paper presents performance evaluation of two implementations of an equalizer: a time domain equalizer (TDE) based on the Least Mean Squares (LMS) algorithm and a frequency domain equalizer (FDE) based on the Fast LMS algorithm. The comparison between the two algorithms is based on the computational complexity and resources. The computational complexity of the two algorithms is analyzed by simulation of the TDE and FDE at at two levels of abstraction: the design specification based on floating point arithmetics using Simulink, and the design implementation based on fixed point arithmetics using Xilinx's System Generator tool. The models are used to measure both floating-point and fixed-point signal-to-noise ratio (SNR) errors based on the two algorithms and provide error estimation for the design specification and design implementation. We analyze the resources used in the implementation of the two algorithms by providing FPGA implementations in System Generator. Our analysis shows that the FDE is more efficient in terms of computational complexity and resources.