{'fraction_non_alphanumeric': 0.07623888182973317, 'fraction_numerical': 0.0038119440914866584, 'mean_word_length': 5.015267175572519, 'pattern_counts': {'":': 0, '<': 12, '<?xml version=': 0, '>': 12, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A novel CMOS inverter composed of a junctionless NMOSFET and a gated N−-N-N+ transistor for ULSI applications

In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N<sup>−</sup>-N-N<sup>+</sup> transistor for driver and load, respectively. Also, the gated N<sup>−</sup>-N-N<sup>+</sup> transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N<sup>−</sup>-N-N<sup>+</sup> transistor is enhanced significantly. Besides, the layout area of the novel CMOS inverter are reduced more than 46.1% because of its unique shared contacting for output node, when compared with the conventional layout area.