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Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures

A compelling confluence of technology and application trends in which the cost, execution time, and energy of applications are being dominated by the memory system is driving the industry to 3D packages for future microarchitectures. However, these packages result in high heat fluxes and increased thermal coupling challenging current thermal solutions. Conventional design approaches utilize design margins that correspond to worst case temperatures and process corners leading to a significant impact on system level performance. This paper advocates a design approach based on microarchitecture adaptation to device-level temperature-dependent delay variations to realize average case performance that is superior to which can be achieved by using worst case design margins. We demonstrate this approach with adaptation principles for the last level cache (LLC) in a 3D many-core architecture. We propose and evaluate two adaptation mechanisms. In the first case, the access time to the LLC from the L1 tracks the LLC's temperature-delay variations. In the second case, the processor DVFS state tracks the LLC temperature as a negative feedback. Compared to a worst case design baseline, the full system simulation results show that both approaches increase the IPC by over 20 percent, and improve the energy efficiency by up to 3 percent.