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Bipolar Device Modeling for VLSI Layout Verification

Today, layout verification for VLSI is a crucial part of IC design. However, for applicability, this must be both fast and accurate. Layout-to-circuit extractors can meet both these constraints. They quickly convert a layout into an equivalent network that accurately models that layout. Subsequently, circuit simulation and network comparison are convenient tools that enable accurate prediction and verification of the circuit before fabrication, thus reducing design costs. The accuracy of this method depends greatly on the network that models the layout. Therefore, not only the extraction of layout parasitics, such as interconnect resistances and coupling capacitances, is important, but also that of the (full-custom)devices. In particular, it is difficult to create an accurate equivalent network for circuits containing bipolar devices, because they generally show a complex topology. This paper describes a method for extracting such bipolar/BiCMOS circuits. The method distinguishes between the extrinsic and intrinsic parts of bipolar devices. The extrinsic parts are modeled by discrete, passive circuit elements, such as resistances and (non-linear) capacitances. For the intrinsic parts, for which several device models exist, the model parameters are computed by combining device geometries and process data.