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Software-Based Testing of Sequential VHDL Descriptions

In this paper, we propose a new approach of high level testing for functional VHDL descriptions of sequential circuits. The main motivation is two-fold. On the one hand, we elaborate an approach for design validation. And, on the other hand, we deal with the problem of hardware testing at the functional level. Furthermore, the chosen test method, i.e. mutation testing, allows us to work with a fault model at the software level on the VHDL descriptions; and this approach has already shown its efficiency on combinational descriptions. In order to tackle the specific problem of sequential circuits, the description is modified so that the state variables are made observable and controllable. A case study allows us to show the efficiency of this test set for design validation through software test metrics and for the hardware testing through the classical stuck-at-fault coverage.