{'fraction_non_alphanumeric': 0.024096385542168676, 'fraction_numerical': 0.0, 'mean_word_length': 5.648, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Power Consumption Analysis in CMOS Static Gates

This paper addresses power consumption in CMOS logic gates through an study considering the design and technology points-of-view. Through SPICE simulations, the relationship between charge/discharge and short-circuit components of dynamic power consumption are investigated both considering different logic gates and its evolution through technology scaling. Experimental results show that dynamic power consumption is still the main source of power dissipation in standard cell based design, whereas the short-circuit component seems to decrease through technology scaling. Static power consumption, on the other hand, keeps growing at each new node, and research effort has to be made to overcome it. Keywords— CMOS, digital circuits, power dissipation, shortcircuit, logic gate.