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High Speed DSP Block for FPGA Devices Using a Programmable Adder Graph

Multiple constant multiplications (MCM) is an optimization technique that is well-suited to DSP implementations. Using MCM, all coefficient multiplications are grouped into one efficient block of wired shifts and adds. A disadvantage of using MCM is the requirement of knowing the filter coefficients a priori. Due to this limitation, MCM optimizations cannot be used in many applications. We propose a programmable adder graph (PAG) circuit that can implement multiplication using shift and add techniques without prior knowledge of the multiplier value. The PAG circuit allows any programmable device to be optimized using MCM for a wide range of DSP applications, including adaptive filters.