{'fraction_non_alphanumeric': 0.033083645443196, 'fraction_numerical': 0.008114856429463172, 'mean_word_length': 4.937037037037037, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Variable Length Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit

This paper presents the implementation of a Variable Length Decoder (VLD) on a TriMedia/CPU64 (FPGA-based) Reconfigurable Functional Unit (RFU). The VLD decodes run-level symbols coded as Variable-Length Codes (VLC) following the MPEG standard. The RFU consists mainly of an Altera FPGA core, and is embedded into the TriMedia as any other hardwired functional unit, i.e., it receives instructions from the instruction decoder, reads its input arguments from and writes the computed values back to the register file. Variable-length decoding is an awkward computational part of MPEG decoding. Since the location of a symbol in the stream depends of the data which precedes it, every symbol has to be decoded before the following one can be. In order to balance the complexity and the efficiency of the RFU-mapped decoder, we propose a VLD computing facility which returns a single VLC symbol (run/level pair or end-of-block) per operation. Briefly, the VLD is implemented as a parallel lookup into FPGA’s Electronic Array Blocks (EAB), followed by a selection of the proper result. Since each EAB can implement a lookup table of 8 inputs, the VLC symbols have been partitioned into classes according to this FPGA architectural characteristic. When mapped on an ACEX EP1K100 FPGA, our VLD computing resource exhibits a latency of 7 TriMedia cycles, and uses 6 EABs and 16% of the logic cells of the device. Keywords— Reconfigurable computing, variable-length decoder, VLIW processors, field-programmable gate array.