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The probability logics for nanoscale inverters cascade

Device failure is an important consideration in nano-scale design. This paper presents a probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on Markov random field and statistical physics. The basic logic gates are probabilistically characterized. The effectiveness of the method is demonstrated by an inverter and the inverter cascade. Our analysis shows that the device probability distribution highly depends on the system structures and other performance parameters.