{'fraction_non_alphanumeric': 0.029069767441860465, 'fraction_numerical': 0.0048449612403100775, 'mean_word_length': 5.707792207792208, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

In-memory computing with analog nonvolatile memories can accelerate the in situ training of deep neural networks. Recently, we proposed a synaptic cell of a ferroelectric transistor (FeFET) with two CMOS transistors (2T1F) that exploit the hybrid precision for training and inference, which overcomes the challenges of nonlinear and asymmetric weight update and achieves nearly software comparable training accuracy at the algorithm level. In this paper, we further present the circuit-level benchmark results of this hybrid precision synapse in terms of area, latency, and energy. The corresponding array architecture is presented and the array-level operations are illustrated. The benchmark is conducted by multilayer-perceptron (MLP) + NeuroSim framework with comparison to other capacitor-assisted (e.g., 3T1C + 2PCM) hybrid precision cell. The design tradeoffs and scalability are discussed between different implementations.