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Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

A new all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all-digital tuning of a digitally-controlled oscillator (DCO). In this paper, we present novel time-domain modeling and simulation techniques of the ADPLL phase detection mechanism as well as the frequency perturbation and phase noise characteristics of the DCO. The modeling principles are demonstrated for a GSM standard and validated through experimental results.