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Cell library techniques using advanced transistor structures

Aggressive performance and power goals for coming process generations are forcing rethinking of some of the basic assumptions of CMOS transistors, and leading to innovative approaches such as strained silicon and metal gates. These methods have implications for the design of standard cells, embedded memories, and other library components. This paper examines these new trends and shows how they affect the design of these components, and by extension, the systems-on-chip built from them.