{'fraction_non_alphanumeric': 0.01950078003120125, 'fraction_numerical': 0.00078003120124805, 'mean_word_length': 5.682291666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Bandwidth management with a reconfigurable data cache

With ever larger FPGA devices, hardware engineers are increasingly relying on automated tools to generate complex designs. However, relatively little attention has focused on automatically generating components of the memory hierarchy. Conventional cache research (despite its extensive study) rarely offers designs that map well to FPGAs. Here we propose an approach that uses compiler technology to analyze an application's predominant array access patterns and then generates a data cache customized for the application. The generic reconfigurable data cache component and the technique used to automatically configure it are described. To demonstrate the feasibility of the proposed approach, a prototype has been implemented. We use the convolution as a representative multimedia operation, and show the benefit of the reconfigurable data cache. Even though the computational structure for convolution is easy to generate automatically (from high-level source code), the resulting design alone is memory-bound and not faster than a comparable microprocessor. However, with the addition of the customized reconfigurable data cache, the resulting system runs 5/spl times/ faster and outperforms the reference microprocessor.