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Optimization of a 61.44 GHz BiCMOS HBT integrated PLL for ultra-fast settling time

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.