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LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications

This paper presents a novel power and reliability-aware task mapping approach in many-core platforms for hard realtime applications which is called LORAP. The LORAP contrives a task mapping scenario to meet the predefined reliability threshold ensuring minimum power consumption overhead. It drastically decreases task mapping time complexity and uses slack time of running applications to apply a heuristic DVFS to reduce the power consumption overhead. The quantitative reliability modeling of this paper uses effective failure rate based on instruction footprints of the task which is obtained using a new low complexity AVF calculations algorithm. Proposed novel 4-step iterative approach is applicable to an unlimited number of fault types. All parts of the platform including cores, links, and routers are assumed to be prone to failures. The Mixed Non-Linear Programming (MNLP) optimization technique is used to find the task mapping solution. Results show that LORAP reaches the solution with up to 1005% higher than the exhaustive approach and also it only imposes power consumption up to 18.2% higher than optimal solution.