{'fraction_non_alphanumeric': 0.01906941266209001, 'fraction_numerical': 0.0038138825324180014, 'mean_word_length': 4.8053097345132745, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Low-Latency Modulation Scheme for Solid State Drive

Due to density and performance considerations, the current Flash memory wordline contains more cells than the legacy file-system sector size. Read operation can obtain a page size that is equal to wordline length. However, the typical workload has random read instructions with a standard sector size of 4KB. Therefore, the question arises whether the fact that the read sector is shorter than the page size can be used to reduce the number of data sensing operations. In other words, can a data sector be extracted from a wordline by using fewer sensing operations required to read the whole page? In this paper, we develop a data modulation scheme for low-latency random sector read, referred to as Sector Packing. Our technique reduces latency in multiple bits per cell architecture and can also improve device throughput. For example, in QLC with 16KB pages, latency is reduced by 34%. Two implementation architectures are offered. The first increases channel data traffic and do not require any NAND changes but only in the controller. The second architecture requires adding a small hardware overhead inside the NAND, resulting in reduced data transmission over the SSD channel. Sector Packing is scalable as the gain is higher with more bits per cell.