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Efficient Bump-Pad Geometries to Relax Design Rules Required for High Density I/O Area Array Packaging

Continuous increase in density of interconnection is demanded as a result of advances in the performance of electronic devices. Because a finer design rule is necessary in the conventional routing design to achieve the higher density, especially in the chip-to-package connection, this trend will bring various problems in both its manufacturing process and reliability. To avoid such a risk, approaches from an escape routing design standpoint might be expected to give an effective solution. This paper presents a design method efficient to relax the severe demands for an ultra-fine wiring rule that leads to a costly manufacturing process and a poor interconnection reliability. This method has been developed focusing on a bump-pad geometry that provides an efficient hybrid channel allowing a higher routability. A specific pad geometry ldquomicrovillirdquo type hybrid channel has been revealed to be applicable in both square grid and hexagonal arrays and to achieve a notable relaxing in trace width and spacing. With this hybrid channel, traces with twice the width become allowable for escape routing compared with the conventional geometry. The effects of this relaxation, not only on manufacturing cost but also on the performance and reliability of packaging, are discussed.