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Design of Low Power Gain-Cell eDRAM for 4Kb Memory Array in 130nm CMOS

Gain-cell (GC) embedded dynamic random-access memory (eDRAM) provides high density, low leakage power, small size, and two-port functionality. However, GC-eDRAM requires power-hungry periodic refresh cycles to maintain data compared to conventional SRAM, owing to its dynamic storage mechanism. In this work, low-power design techniques, which are single-supply three-transistor (3T) GC-eDRAM and 4T GC-eDRAM with internal feedback, are proposed to improve the power consumption by extending the data retention time (DRT). The topology of a single supply 3T GC consists of a transmission gate (TG) in the write port that has the self-dampening effect of charge injection (CI) and clock feedthrough (CF), which allows the transmission of a strong initial data level. The topology of the 4T GC with internal feedback consists of two additional transistors that provide an internal feedback mechanism to suppress the deterioration of the weaker data level. Both methods provide a lower data decay rate and a stronger initial data level that helps to prolong the DRT and subsequently reduce the periodic refresh cycles, resulting in lower power consumption.