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Efficient Design of Integrated Antennas on Si for On-Chip Wireless Interconnects in Multi-Layer Metal Process

In this study it has been shown that the transmission gain of an integrated dipole antenna on a Si chip used for an on-chip wireless interconnect is drastically reduced in a multi-layer metal interconnect scheme when a second metal layer is placed above the antenna at the usual interlayer metal distance. The best way to preserve high gain of the integrated antenna in such a multi-layer metal process is to design an antenna with excitation vertically through the Si substrate. In the presence of the upper metal layers, the vertically excited field mode propagating through the Si substrate does not cause any significant reduction in the power transmission of the antenna. Simulations of the structures have been carried out using the ANSOFT high frequency structure simulation (HFSS) program employing the three dimensional finite element method. A simple analytical model has also been developed, and the results are presented for comparison.