{'fraction_non_alphanumeric': 0.0156128024980484, 'fraction_numerical': 0.0078064012490242, 'mean_word_length': 5.104761904761904, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Global conflict avoidance using block placement strategies in multi-level caches

Eliminating the conflict misses in the caches has been a foremost field of research in cache memories. Although several cache addressing/indexing techniques have been demonstrated, most of them discuss about eliminating conflict misses for various memory access strides in a solo cache system. In this paper we present the analysis of the scenarios where conflicts arise at different levels of caches in a multilevel cache system. In this paper, we propose two block placement schemes least-XOR and full-XOR for multi-level caches. These placement strategies reduce the scenarios where two addresses conflict with each other at multiple places in multi-cache system and thus improves the global miss rates which are fairer indicator of performance than the local miss rate. These schemes do not require any additional hardware to the existing indexing hardware on the chip. We evaluate these schemes on sixteen memory intensive spec2000 benchmarks and show that there is a significant improvement over the traditional scheme for various performance measures such as cache miss rates, memory traffic, and CPI reductions. These schemes can achieve about 10-20% reduction in L2 and L3 cache miss rates.