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A Memristor-based Scan Hold Flip-Flop

The scan based design-for-testability (DfT) has been widely adopted in modern integrated circuits (ICs) design to facilitate manufacture testing. However, the transitions in scan cells result in much test power consumption during testing. The scan hold flip-flop (SHFF) can insulate the transitions in scan chain from the circuit under test to reduce test power while incurring much area overhead. We propose to solve this problem by adopting a memristor-based D flip-flop (DFF) into SHFF. The new design breaks down the design structure of conventional CMOS scan cells and adopts memristors into SHFF to reduce the number of transistors and hence the chip area. The functionality of the proposed design is verified to be correct by HSPICE simulation. Compared with the conventional SHFF cells, the area overhead is reduced 26.5%