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A fully symmetrical 60GHz transceiver architecture for IEEE 802.15.3c application

This paper presents a new multi-conversion super heterodyne architecture for 60GHz broadband wireless application. The proposed design consists of a three-stage conversion with the help of a 24GHz VCO and a divider. The local oscillator frequency stands far away from RF and both IF signals reduce inter-modulate interference. The first and second mixers sharing the same 24GHz VCO relax the complexity and lowering power consumption of both VCO and PLL. Reusing of LO signal without frequency doublers or triplers for multiple conversions reduces power, area and improves efficiency. The topology is symmetrical about the transmitter and receiver sections. This unique feature reduces any circuit mismatches and provides a balance load for the VCO. The proposed design is simulated with ADS at the system level. The transceiver shows high sensitivity and indicates low power design on chip.