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A behavioral model of integer-N PLL frequency synthesizer for reference spur level simulation

The major effects defining reference spurs level of the integer-N phase-locked loop (PLL) frequency synthesizer are described. The behavioral model of the PLL for evaluating reference spurs level has been developed in CAD Keysight ADS. The model takes into account time delay between output signals of the phase-frequency detector (PFD) and delay in the PFD reset path; charge pump current mismatch; charge pump current leakage; charge pump switching time mismatch. The design issues of SOI CMOS PLL functional blocks (FB) based on the proposed behavioral model, have been provided.