{'fraction_non_alphanumeric': 0.013768115942028985, 'fraction_numerical': 0.0036231884057971015, 'mean_word_length': 5.453271028037383, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Expected current distributions for CMOS circuits

The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper presents a new static switching current estimation algorithm based on the idea of "Expected Current Distributions" (ECDs). Unlike previous "expected waveform" approaches, ECDs model not only the expected value of switching current waveforms over all time, but also the variances and covariances of all waveform segments as well. This extra information allows a switching current waveform to be modeled by a random process with both first and second order ensemble statistics. This specification provides the power spectral density of the switching current and allows the use of traditional frequency domain noise analysis to simulate the behavior of the switching current in the electrical supply network. An ECD simulation procedure is described and results are presented for the ISCAS85 combinational benchmark circuits. Estimated quantities include total average and RMS VDD current, the autocorrelation function of the total VDD current waveform, and per-gate average and RMS VDD currents. The results show speedups of up to 100 x and good agreement with respect to figures obtained using dynamic logic simulation and statistical mean estimation.