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An FPGA implementation of future video coding 2D transform

Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an FPGA implementation of FVC 2D transform is proposed. The proposed FVC 2D transform hardware can perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, DST-VII operations for 4×4 and 8×8 transform units. It uses two reconfigurable datapaths for all 1D transforms. It implements multiplications with constants using DSP blocks in FPGA. The proposed FPGA implementation, in the worst case, can process 54 8K Ultra HD (7680×4320) video frames per second. The proposed FPGA implementation has up to 29% less energy consumption than the FPGA implementation of FVC 2D transform hardware in the literature.