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Designing of Low Power 16-Bit Carry Select Adder with Less Delay in 45 nm CMOS Process Technology

Designing of power-efficient and high speed digital logic systems is very crucial task. Numbers of adders are designed and provide tradeoffs between power, delay and area. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions This work uses a simple and an efficient gate-level modification using 45nm CMOS Process Technology, which drastically reduces the area and delay of the CSLA. Based on this modification 16-bit Carry Select Adder (CSLA) architectures have been developed and compared with the regular CSLA architecture developed in 180nm CMOS process technology. The proposed design has reduced area and delay to a great extent when compared with the previous CSLA developed in 180 nm. This work estimates the performance of the proposed designs with the regular designs in terms of delay, area and power are implemented in Tanner (S-edit) tool. The results analysis shows that the proposed CSLA structure developed in 45 nm technology is better than the regular CSLA developed in 180nm technology.