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Verification and Fault Localization for VHDL Programs

Introduction During the last decades, hardware-design languages like Verilog and VHDL have become very common for designing digital circuits. These languages allow designers to specify and test the behavior of circuits before they are produced. This helps to avoid incorrect designs and saves money, providing that the designs are rigorously tested. If faulty behavior is identified through verification, the location of the error in the source code is of interest. Finding this root cause of the misbehavior is not always as easy as expected. The source code is usually huge. Furthermore, it is often written by one team of hardware designers and tested by another team. Because hardware designs are becoming ever more complex, verification is becoming a bottleneck in the design flow. Hence, verification and fault localization are both important issues for hardware designers and their companies. Both are imperative for ensuring quality of the hardware designs, reducing time to market, and avoiding costly re-designs. As a consequence, they reduce the overall design costs.