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Innovative Panel Plating for Heterogeneous Integration


 Panel plating requirements are much more demanding as more applications migrate from silicon to panel assembly such as Panel Level Fan Out (PLFO) to leverage the large sizes of the panels. More recently, Heterogeneous Integration (HI) like Intel's Embedded Bridge (EMIB) or various other embedded die concepts are also pushing the boundary for typical panel structures. Line widths and spaces less than 10 Microns, thickness uniformity better than 10%, via topology free of voids and the same height as the redistribution lines are critical.
 Traditional Panel plating tools are mostly for bulk processing and are not designed to handle these additional requirements. A new tool was required to overcome these challenges. An electroplating process with a single panel per reservoir approach is used. An overhead transporter brings the individual panels that have been pre-loaded in a rigid panel holder designed to handle large currents as well as reduce the warpage to a series of plating reservoirs as well as pre and post processing steps with the tool.
 The first process is to reduce voiding by removing all air in a vacuum chamber and then inserting degassed water in the same chamber to “prewet” the panel. Panels are then typically immersed in an acid bath known as an activation step before processing in the plating cells. The plating cells are customized for each metal layer but often include a fine alignment feature, a current uniformity optimizing shield, multiple anode channels for dynamic uniformity along with an agitation mechanism to produce a uniform thin boundary layer at the panel surface. This whole mechanism needs to be very close to the panel, yet still allow some warpage typically associated with panel manufacturing.
 This paper will demonstrate that it is possible to achieve better line density, bump thickness uniformity and void free vias to allow semiconductor like assembly for Heterogeneous Integration on a standard Printed Circuit Board (PCB) instead of more expensive semi additive processes or silicon interposers