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Predictive Warp Scheduling for Efficient Execution in GPGPU

Today's general-purpose graphics processing units (GPGPUs) offer phenomenal performance to applications from a variety of fields. Despite its memory-latency tolerant parallel architecture, GPGPU cores do not attain optimal performance with most of the memory-intensive applications which add a significant load on memory-resources. The existing thread scheduling mechanism is not optimized to address this challenge for latency-sensitive applications. In this paper, we propose a warp-scheduling policy that defers the execution of all those warps which will potentially cause long-latency memory-stalls, to prevent the resulting congestion in interconnect network and DRAM bandwidth. The proposed policy uses a predictor in each core of the GPU to predict whether or not the data can be retrieved from the L1-cache at the time of increased congestion to effectively reduce the number of warps that can be paused and keep the cores active. This translates to an average performance improvement of 11.6% and up to 41.2% over the state-of-the-art scheduling policies across a diverse selection of applications with a 4.2% increase in average power consumption.