{'fraction_non_alphanumeric': 0.022972972972972974, 'fraction_numerical': 0.002702702702702703, 'mean_word_length': 5.5, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Area-efficient and high-speed binary divider architecture for bit-serial interfaces

This paper proposes a low-complexity binary divider for high-speed serial interfaces. In contrast that the previous parallel dividers require a large amount of hardware costs, the proposed divider achieves a low-complexity division by targeting the serial interface that is widely used for the recent digital communications. By modifying the linear feedback shift register (LFSR) architecture for polynomial division, the high-speed processing element is newly introduced to handle the serialized dividend input. As a result, the proposed serialized architecture reduced the area-time complexity by 75 times compared to the previous slow parallel divider.