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Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

In this paper, two implementation methods to optimize a 1024-bit RSA processor are presented. The Montgomery algorithm is used and modified considering large bit modular multiplication. We propose two architectures for 1024-bit RSA processing in order to reduce the required hardware resources and to achieve speed improvement. One reduces the hardware resources using the L-R (left to right) binary method, and the other achieves speed improvement using the R-L (right to left) binary method. We have implemented two single-chip 1024-bit RSA processors based on the proposed architectures in 0.5-/spl mu/m SOG technology using Verilog-HDL. As a result, it is shown that each architecture contributes to speed improvement and area saving.