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Design and implementation of timing acquisition in IEEE 802.11a wireless LANs

This paper presents an implementation of timing synchronization for the IEEE 802.11a wireless LAN applications. The implementation is based on a multi-stage architecture with three feed-forward stages. In this architecture, the first two stages are targeted for coarse and fine frame detection, while the last two stages are for coarsely and finely finding the symbol timing. The basic operations are cross autocorrelations in the first and the third stages, and autocorrelations in the second stage. Considerations have been paid to achieving a low-complexity solution. The IC implementation results show that the designed timing acquisition is fast, robust and accurate.