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A Novel Framework for Procedural Construction of Parallel Prefix Adders

Parallel prefix adder is a type of adder design which emphasizes the parallelism on carry propagation, and it can tradeoff between the circuit size and the logical depth. This paper proposes structural-decomposition and procedural-construction of feasible parallel prefix adder structures. “Join”, “insertion” and “interleaving” are introduced as basic operations for constructing feasible parallel prefix diagram (the core structure of a parallel prefix adder) in this paper, and it is demonstrated that well-known benchmark structures are all successfully decomposed/constructed in this novel framework. Our proposed framework provide us a novel, compact and expandable representation of individual parallel prefix structures, which might be used in search-based design optimizations.