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A new method to implement a constant operand multiplier

In this paper we present a new method to implement constant operand multiplier. The structure is optimized in point of view of surface occupation and time execution. The principle of the new method based on a compression of four partial products into one row. The method proofs its availability for both signed and unsigned multiplication. Simulation results using FPGA implementation technology show an improvement of proposed algorithm performances compared to DADDA multiplier.