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Investigation of independent gate operation in junctionless silicon nanotube FET using 3D numerical simulations

In this paper, we investigate the independent gate operation in Junction-less Silicon Nanotube FET (JLSiNT-FET) device using TCAD 3D simulations. JLSiNT-FET has two gates (inner gate and outer gate), in which one gate voltage can be varied at a time, by fixing the other gate voltage constant to achieve a dynamic threshold voltage of the device. ON current (Ion), OFF current (IOFF), ION/IOFF ratio and Threshold voltage (Vth) are extracted from the saturated ID-VG characteristics in the independent gate operation mode. As the effective gate oxide thickness of inner and outer gates are different even the physical gate oxide thicknesses are same, the asymmetric performances occur in the independent gate operation.