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A Preliminary Performance Evaluation of the Seamless Parallel Processing System Architecture

In this paper, the results of a preliminary performance evaluation of the Seamless parallel processing system are presented. Seamless is a latency tolerant multiprocessor architecture based on RISC processors. Evaluation is performed with a hybrid experimental and simulation based approach utilizing both discrete event simulation and experimentation on an Intel iPSC/860. The results show that communication in Seamless has the potential for substantially better performance than message passing systems for medium grained parallelism and is no worse for both large and fine grained parallelism. Further, its communication mechanism substantially reduces the amount of buffering overhead with respect to asynchronous send based primitives. Finally, we show the performance to be robust with respect to changes in communication speed and latency. A Preliminary Performance Evaluation of the Seamless Parallel Processing System Architecture