{'fraction_non_alphanumeric': 0.018072289156626505, 'fraction_numerical': 0.012048192771084338, 'mean_word_length': 4.833333333333333, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
PFAL based power efficient mux based decoder

Low power circuit techniques have become indispensable need of the hour for VLSI design. One such low power technique which has gained popularity over the past decade is adiabatic technique. It is based on the concept of reusability of power. In this paper, a positive feedback adiabatic logic (PFAL) based mux decoder is proposed. The decoder has been designed in 180nm CMOS technology and simulated using SPICE. The PFAL based decoder outperforms the conventional CMOS based decoder in terms of power dissipation. A significant reduction of 41.867% in power dissipation has been achieved in the proposed mux decoder.