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A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft error rate (SER) analysis is also pursued to confirm the findings of the critical charge-based analysis. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A novel memory scheme with the proposed NVSRAM cells is proposed for tolerating MBU; in this scheme, only the error detection circuitry is required, because error correction is provided by the non-volatile elements of the NVSRAM cells. Simulation results show that the proposed scheme is very efficient in terms of delay and number of transistors (as measure of complexity). Moreover, the very high critical charge of some of the proposed cell designs reduces the number of MBU appearing as errors at the outputs of the memory, thus further reducing the error detection hardware required by the proposed scheme. An extensive evaluation and comparison of different schemes are presented.