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A system approach for partially reconfigurable architectures

The increasing logic density of current Field Programmable Gate Arrays (FPGA) enables the integration of whole systems on one programmable chip. Using concepts of partial dynamic reconfiguration allows the adaptation of complex systems to changing requirements at run-time. In this paper we present a realisable approach for dynamic system integration on Xilinx Virtex FPGAs. In contrast to existing approaches that consider fixed slots for module placement, our approach allows fine-grained placement of modules with variable width along a horizontal communication infrastructure. By simulation we show that the proposed 1D-approach outperforms 2D-approaches by means of the device utilisation and external fragmentation.