{'fraction_non_alphanumeric': 0.012727272727272728, 'fraction_numerical': 0.016363636363636365, 'mean_word_length': 4.861702127659575, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Analysis and Design of the Taper Isolated Dynamic RAM Threshold Transistor for VLSI dRMs

A single buried channel nMOS transistor is shown to provide two dynamically programmable threshold voltages by spatially confining a hole packet at the Si/SiO2 interface, to provide a ROM like memory cell called the Taper Isolated dRAM. This cell is 3x smaller than a standard capacitor cell, has 10x less leakage at high temperature and potentially has a 2–3x speed advantage in a large array, and a 100x better immunity to alpha particle induced soft errors.