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Large Scale Asynchronous Low-power VLSI Systems for Event- driven Sensory and Neural Processing

This dissertation investigates a low-power temporal event encoding imaging sensory system front end and a neural computation analog VLSI backend embedded within a custom scalable architecture enabling highly energy efficient processing of these event streams. We explore the differences in event encoding and conventional computing emphasizing that computation and communication are data- driven and energy costs scale with information transfer and processing. The application of this principle in the imaging sensory system increases efficiency by ensuring that light intensity information is gathered only when and where warranted by temporal change and spatial proximity. This temporal contrast detection imager having 128x128 pixel array die size of 5x5mm² and pixel size of 33x33[mu]m² is fabricated in 0.18[mu]m CMOS. With supporting asynchronous event-driven information compression we achieved 1.52nJ per pixel event detection and readout. Similarly for neural computation slow but densely arrayed neural units are fabricated on a 4x4mm² die in 90nm CMOS. We present a 65-k integrate-and-fire array transceiver (IFAT) on a single die implementing 65-k neurons each with two compartments and four conductance based programmable analog synapses at 18.2 Mevents/s per each quadrant at sustained peak synaptic event throughput and 22pJ per synaptic input event in average. Operating at very low power the IFAT is robust to noisy inputs and high throughput is enabled by an asynchronous two-tier micro- pipelining scheme. This system is formed in a tree based hierarchical address event routing (HiAER) architecture. HiAER is implemented in 5 Xilinx Spartan-6 FPGAs enabling 262k neurons and 262M synapses on a level of hierarchy, at 3.6x10⁷ synaptic events per second per each 16k-neuron node in the hierarchy