{'fraction_non_alphanumeric': 0.034013605442176874, 'fraction_numerical': 0.026239067055393587, 'mean_word_length': 4.392670157068062, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An adaptively biased stacked power amplifier without output matching network in 90-nm CMOS

In this paper, a high gain high efficiency 3-stacked power amplifier (PA) without the need for an output matching network is presented. With the transistors stacked in series, the drain-gate and drain-source voltage swings on each transistor is relaxed while a high output power is delivered. The stacked PA is designed such that the output can drive the load directly without any impedance matching network to save chip area, simplify the design, and avoid the loss introduced by the on-chip passive components. An adaptive bias network is integrated to dynamically adjust the bias of the PA according to the input power level that effectively enhances the efficiency at power backoff. Implemented in 90-nm CMOS process, the proposed PA features a power gain of 17.2 dB at 32 GHz, a 3-dB bandwidth from 28.2 GHz to 35.7 GHz, a saturated output power of 17.6 dBm, a peak power-added-efficiency (PAE) of 25.3%, and a PAE at P1dB of 11.5%.