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A Bus Encoding Comparison for Low Power

With the continued scaling of digital circuits, power consumption is becoming an increasingly important issue. The power required to perform computations rapidly decreases, however the energy required to power large buses and interconnect has not been as fortunate. This is due to non-uniform scaling (aspect ratios increased [2]) and sidewall fringing effects. These buses can also have a capacitance which is several orders of magnitude above internal circuit nodes making a single bus transition equivalent to several hundred circuit transitions [4]. With the inclusion of the Miller Effect this figure is even worse. So it becomes necessary to study methods to lower the power consumption of these lines. A popular technique to limit the power consumption has been to reduce the switching activity through the encoding of data on these highly capacitive global lines. This project makes an objective comparison between several proposed encoding methods in terms of reducing power consumption.