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A Data-Flow Platform for Implementing Algorithm-Dependent ASIC Hardware Using Data-Driven Processors

The design details of a new data driven processor (DDP) which simplifies data management and processor hardware is demonstrated. The processor consists of an input port for handling external real-time data, a second input port for exchanging networked inter-processor data, a multi-port RAM, a flag memory, an ALU and a controller. The key benefit of this processor is to be able to handle real-time streaming data through a dedicated port while exchanging data with other processors on a network. Each processor is identical with the exception of the ALU which is custom-tailored for a specific task to simplify processor hardware. Algorithm-dependent wireless communication and multimedia tasks can be implemented using software development on a network of DDPs. This work implements the base-band portion of a simple direct sequence spread spectrum (DSSS) transmitter using a software platform that requires four networked DDP cores. The transmitter design produced one chip for every 15 clock cycles and 225 clock cycles to process one symbol. This resulted in 11 MBit/sec transmission bandwidth which required 825 MHz clock frequency to reach 802.11b WLAN rate