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FPGA Based Architectures for H. 264/AVC Video Compression Standard

The H.264/AVC (as known as MPEG-4 part 10) [1, 2] is a video coding standard that has been developed to achieve significant improvements, in the compression performance, over the existing standards. The main blocks of a H.264/AVC encoder are the motion estimation, the motion compensation, the intra prediction, the loop filter, the entropy coder, the forward and inverse quantization and the forward and inverse transforms. The H.264/AVC decoder is formed by entropy decoder, motion compensation, intra prediction, loop filter, inverse quantization and inverse transforms [1]. This work focuses on the design of high performance architectures for the H.264/AVC standard.