{'fraction_non_alphanumeric': 0.018763796909492272, 'fraction_numerical': 0.005518763796909493, 'mean_word_length': 5.3426573426573425, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes

This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.