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Physical Design Analysis of USB 3.0 Architecture

This paper presents the the physical layer design of USB 3.0. Power analysis of various transmitter and receiver blocks used in the physical layer of USB 3.0 has been carried out. Three different techniques for analyzing the power of encoder/decoder circuit has also been implemented using Analyzer of Xilinx 13.4. The power is calculated at two different frequencies i.e. 200MHz and 20MHz. All the designs have been implemented using Verilig HDL