{'fraction_non_alphanumeric': 0.044581091468101464, 'fraction_numerical': 0.05073020753266718, 'mean_word_length': 4.2926829268292686, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 1, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers

This brief describes a novel Wideband Pre-Distortion (WPD) mechanism as a linearization technique for bandwidth-limited CMOS power amplifiers (PAs). The WPD comprises a common-source amplifier and a hybrid feedback mechanism blended with both active and passive networks to secure a flat gain response from 800 MHz till 3.3 GHz, while maintaining >30% power added efficiency (PAE) at a maximum linear output power of 20 dBm throughout the band of operation. The WPD generates unique gain and phase cancellation mechanisms on-chip therefore alleviating the 3rd-order intermodulation product (IMD3) for an operating bandwidth of 2.5 GHz. Measurement results on 180 nm CMOS, with a supply voltage of 3.3 V indicate that the WPD-PA produces a saturated output power of 24 dBm, in addition to a power gain of 15.5 dB and a peak efficiency of 35.5% at 2.45 GHz. The WPD-PA delivers a maximum linear output power of 20-dBm with an adjacent channel leakage ratio (ACLR) of −30 dBc and error vector magnitude (EVM) of 3.42%, 2.34% and 2.76% at 0.8, 2.45 and 3.3 GHz when measured with the 20-MHz LTE signal. The corresponding maximum linear PAE ranged between 31 to 34%. The chip area is 1.28 mm2.