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Design of a double balanced square law CMOS up-conversion mixer with improved input isolation technique for high frequency applications

In this paper, a square law CMOS double balanced mixer is designed in IBM 90nm technology with improved input isolation technique for high frequency applications. Responses of the circuit is demonstrated when a 1GHz signal is up converted by a 19GHz carrier. Conversion gain (S21) of the mixer is 11.4dB with 4.5GHz Bandwidth (17.3GHz to 21.8GHz) and the input-output matching parameters (S11 and S22) are −18dB and −18.8dB respectively. Noise figure of the circuit is 6.1dB and the power consumption is 9.25mW, the power supply being 1.2V. It achieved an input referred 1dB compression point of −10.8dBm and the IIP3 is about 0dBm. The mixer has the flexibility of being used as a single balanced one as well. The input isolation is improved and is better than −15dB at the input frequencies of interest, which makes this simple circuit attractive for high frequency applications. The group delay distortion was analyzed with the help of a three tone test signal and was found satisfactory.