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Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders

Binary arithmetic coding is a key part of recent video compression standards. Its throughput is limited by the inherent dependencies existing in the algorithm. As a consequence, a higher bin parallelism leads to lower clock frequencies. This paper presents an architecture able to exceed limits existing in previous hardware implementations. The architecture exploits less probable symbols as starting points for long series of bins coded in one clock cycle. The evaluation for four possible cases of the range value allows its update in the pipeline before the delayed selection based on actual value. The adaptive division into series is proposed to make long series more frequent. To shorten critical paths, rMPS variables computed for symbols coded in the same clock cycle are first summed and then added to the low register. Up to 16 bypass-mode symbols can be processed in parallel with context-coded symbols in one clock cycle. The architecture is generative, i.e., its throughput can be scaled with resources without strict limits. For example, the binary arithmetic coder synthesized on 90nm TSMC technology which consumes 101.4k gates and operates at the 570 MHz has the average throughput of 13.4 bins per clock cycle for the high-quality H.265/HEVC compression.