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Evaluation of Digitally Controlled PLL by Clock-Period Comparison

For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.