{'fraction_non_alphanumeric': 0.026, 'fraction_numerical': 0.01, 'mean_word_length': 4.530386740331492, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Novel Area-Delay Efficient Carry Select Adder Based on New Add-one Circuit

In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (Cin=1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.