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Parallel Modelling Paradigm in Multimedia Applications: Mapping and Scheduling onto a Multi-Processor System-on-Chip Platform

Multi-processor systems have appeared as a promising alternative to face the difficulties of creating even faster uni-processor systems using latest technologies. Emerging design paradigms such as Multiprocessor System-ona-Chip (MpSoC) offer high levels of performance and flexibility and at the same time promise low-cost, reliable and power-efficient implementations. However, the design complexity of such systems have increased tremendously. One source of the complexity stems from highly parallel heterogeneous nature of the underlying hardware architecture, which poses many challenges for mapping of an application to the architecture. This motivates the development of a unified programming paradigm that facilitates the mapping by hiding the architectural complexity and exposing the parallel resources of the architecture. To enable design reuse, such a programming paradigm has to support a smooth translation of sequentially-coded software algorithms into their parallel implementations. In this paper we address the parallelization of sequential multimedia applications written in C/C++ for their mapping and scheduling onto a flexible MpSoC platform. We show that using our approach an architecture-independent multi-threaded model of a MPEG–2 video decoder algorithm can be obtained with only few modifications to an existing sequential implementation of the algorithm.