{'fraction_non_alphanumeric': 0.020161290322580645, 'fraction_numerical': 0.0, 'mean_word_length': 5.422413793103448, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Study on self-heat effects in integrated circuits with hot-spot and electro-thermal coupling methods

The self-heat effects in integrated circuits have great impact on circuit performance and power consumption. Based on HSPICE circuit simulator and improved Hot-Spot thermal analysis, this paper presents a new fast electro-thermal relaxation method to study the self-heat effects. Given the layout information and the input signal pattern, the developed method may calculate the temperature distribution of a chip, and investigate the chip performance under the distribution. With infrared thermal image system, the measured temperature distribution of the facsimile thermal printing head ASIC chip agrees very well with the simulation result.