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Optimization Assessment of a New Extended Multilevel Converter Topology

In this paper, a novel general circuit for multilevel converter is presented. To produce all voltage levels, two methods are provided for selecting the amplitudes of sources. The proposed cascade structure is optimized for producing maximum levels with the least number of IGBTs, drivers, and dc sources. The proposed circuit is compared with other recommended multilevel converters. The comparison results prove the merits of proposed structure in terms of utilizing the least number of IGBTs and gate drivers. Also, the value of blocking voltage of all switches in the presented topology is low. The performance of the presented multilevel converter is indicated through simulated and experimented circuits.