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Automatic Control Of Inverters In Electrical Networks: Capture Range And Cycle Slipping

The paper discusses one of the issues of interaction of inverter electrical systems with control systems based on special models of the phase-locked loop, called Enhanced Phase-Locked Loop.


Introduction
In the electric power industry, synchronization with the grid is often used in systems with inverters and rectifiers (for example, in the solutions of Transconverter LLC and SIEMENS AG). Grid-tie inverters are used as grid-to-grid converters for solar panels and wind turbines [1,2], as an essential part of the drive for regenerative braking of trains, and as an auxiliary converter in an electronic non-dissipative load. The use of transistor rectifiers (power factor correctors [3]), providing both sinusoidal phase currents and their in-phase to the corresponding phase voltages is associated with the widespread use of nonlinear loads that distort the shape of the consumed current. At the same time, standards of the International Electrotechnical Commission rigidly limit the emission of higher harmonic components into the network. The growing demand for power factor correctors is associated with the development of autonomous electric transport, which quickly recharges storage batteries, as well as rail transport powered by an alternating current contact network. Recently, developers of aviation electrical equipment for fully electrified aircraft (Aeroelectromash, Technodinamika) have shown attention to power factor correctors. Direct use of classical PLLs [4][5][6] for synchronizing inverters and power factor correctors is rare. This is due to rather low frequency compared to frequencies in wireless communication traditional for PLLs. In addition, the nature of the noise and the in-phase requirements introduce even more problems. To solve these problems, the Enhanced Phase-Locked Loop (EPLL) [7] was proposed, which in addition to synchronizing in frequency and phase allows to determine the amplitude of the input signal.
here, v is the estimate of the amplitude of input voltage u sin(θ ref (t)) with frequency ω ref , phase θ ref (t), and amplitude u; x is the state of the Loop filter with parameters τ 1 and τ 2 ; is the phase difference between input signal and Voltage-Controlled oscillator (VCO, Inverter) output signal; ω free e = ω ref − ω free vco is the initial frequency difference; K vco is the input gain of frequency control.
The resulting system of non-autonomous nonlinear differential equations makes it hard to apply control theory to determine stability of pull-in and lock-in. To solve this problem, the classical averaging theory by the Krylov-Bogolyubov [8][9][10] can be adapted to phase-locked loop systems [11][12][13][14]. This approach allows one to consider an autonomous nonlinear system of differential equations of the classical PLL, under the conditions of a slowly varying input frequency.
The next step after averaging is to study the global and local stability of the resulting system, which has an infinite number of equilibrium states: unstable and stable, alternating with each other. Global analysis can be carried out using the Lyapunov function for the case of a proportional-integrating filter [15], which shows the infinity of the pull-in range.
When applied to power grids, the concept of cycle slipping [15,16] is of particular importance: when two power grids with a large phase difference are connected, a short circuit may occur; also, additional noise and other undesirable effects may appear. To determine the frequency band which guarantees absence of these effects, the definitions in [15] can be generalized for arbitrary limit values of the phases (different from ±π). In this case, the calculation of the indicated ranges can be done either numerically, similar to the classical PLL, or using analytical estimates using Lyapunov functions. Figure 2 shows an example of inverter implementation in MATLAB Simulink environment. For the parameters shown in Figure 2 in case K vco = 0.01 lock-in range can be estimated at 2.5 Hz and during the transient process the phases of the inverter and the mains differ by more than π with an initial frequency difference of 5 Hz, which can lead to a short circuit. With K vco = 1 the lock-in range can be estimated at 52 Hz and with the same other parameters, EPLL allows one to be out of phase at a minimal level. 1 4. Lock-in range for discrete-time EPLL Note that stability results for continuous-time PLL model (2) do not translate directly for its discrete-time analog:

Simulation in Matlab Simulink
where θ k = θ e (T s k) is a sampled phase difference with sampling rate 1 Ts and x k is a state variable for proportionally-integrating loop filter. System (4) describes operation of EPLL implemented in microcontroller. It is easy to see, that periodic solutions for (4) always exists: Therefore, unlike continuous case (2), system (4) is not globally stable for all ω e , i.e. pull-in range is empty. This simple example shows, that it is necessary to study discrete-time systems separately to obtain adequate results.

Conclusion
The paper describes the problem of auto-tuning inverters in electrical networks, describes the main approaches to the analysis of the pull-in range and the lock-in range. Further analysis of higher-order filters is possible using frequency methods [17], computer modeling, and practical implementation of prototypes.