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Trapped hole enhanced stress induced leakage currents in NAND EEPROM tunnel oxides

The stress induced tunnel oxide leakage current occurring in NAND EEPROM memory cells after a large number of WRITE/ERASE (W/E) cycles has been investigated for different W/E pulses. A model for the stress induced leakage current is proposed in which the presence of both holes and neutral oxide traps are a necessary condition for the stress induced leakage current to occur.