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Stress Evaluations of Silicon Nitride Chips Bonded onto Copper Substrates via SAC Soldering, AuSn Soldering, and Copper Sintering

Power electronic modules require multi-layer architectures, where the layers provide dedicated functions, e.g. active semiconductor chip, electric conduction layer, heat spreader, insulation layer. All the layers have different material properties, like coefficients of thermal expansion. Due to their mismatch, local stresses are induced, which can cause electronic failure in packaging technologies. In this regard, new materials need to be developed, which provide high thermo-mechanical stability. In addition, innovative interconnect processes are required, which minimize the formation of stresses. Silicon nitride (Si3N4) chips with polycrystalline and multi-phase morphology are investigated. The chips are sintered to copper substrates using a Cu(II)formate/polyethylene glycol sinter paste. In reference to the sintered copper interconnect, SAC and AuSn solder interconnects are also analysed. The final assemblies are studied using micro-Raman spectroscopy. The frequency changes of the E1g vibrational mode at ca. 860 cm−1 are observed to detect intrinsic tensile and compressive local stresses. Stress values between 640 and 400 MPa are detected in the Si3N4/AuSn/Cu assemblies, while in all other assemblies stress relaxation appears very efficient.