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A Noise Aware CML Latch Modelling for Large System Simulation

Modern high speed communication systems often employ both analog and digital blocks. This poses a challenge for simulation of closed loop system dynamics in presence of non-idealities in any of the analog blocks. Due to the size and complexity of such systems it is not possible to do full system level simulation with circuit level models. The presence of digital control blocks makes it difficult to elevate block level observations to system level performance. A major challenge is the difficulty in estimating the error rate at the output of digital latches (continuous-time to discrete-time domain crossing boundaries) in the presence of noise and non-ideal analog input signals. Simplistic models used currently are often inadequate in capturing the long term effects of non ideal behavior at the block level. In this paper we propose a simulation framework to estimate latch transition probabilities in the response to distorted input and clock waveforms in presence of white noise. The evaluated transition probabilities can then be used to estimate system performance in an event driven Markov chain based model.