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A Design Flow for the Precise Identification of the Worst-Case Voltage Drop in Power Grid Analyses

Modern IC designs contain hundreds of millions of transistors and new approaches of multicore chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow using innovative results of our recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine using industrial EDA tools and perform power grid verification using a custom hierarchical design.