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A real-time FPG-embedded faults classification system powered by phasor estimation and supervised learning algorithms

This paper specializes in developing a real-time faults classification system powered by phasor estimation and supervised learning algorithms. The classification system is embedded in a low-cost Field-Programmable Gate Array (FPGA) programmed using VHSIC Hardware Description Language (VHDL) code, exploiting the flexibility in its parallel architecture and real-time execution that imply faster processing speeds than microcontrollers. The phasor estimation is driven by a nonrecursive Discrete Fourier Transform (DFT) and the supervised learning-based classifier model is conducted by a Support Vector Machine (SVM). Experimental tests corroborate the system performance and its reliability under different fault conditions.