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Fast bit-pipeline rank filter

The major benefit of disclosed low hardware complexity bit-pipeline rank filter is the reduction in hardware complexity and the increase in processing speed, due to identical pipelined stages and the absence of mask bits. FPGA realization of this filter significantly reduces the number of used logic elements and registers in comparison with best prior art methods, while at the same time increases maximum operating frequency. One rank sample result is available at the output per each clock cycle, thus enabling real-time nonlinear image processing.