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An Algorithm-Agile Cryptographic Co-processor Based on FPGAs

Cryptographic algorithm agility, or the capability to switch between several encryption algorithms, has become a desirable feature due to the algorithm-independent design paradigm of modern security protocols. Moreover, applications such as cell encryption in ATM networks require the ability to quickly change ciphers. A promising answer to algorithm agility in hardware is reconfigurable logic. This contribution describes the design and implementation of an algorithm-agile cryptographic co-processor board. The core of the board is an FPGA which can be dynamically configured with a variety of block ciphers. The FPGA is capable of encrypting data at high speed through an ISA bus interface. The board contains a RAM with a collection of FPGA configuration files. In addition, the algorithms can be added or deleted during operation. The co-processor board also contains other reconfigurable logic and a microprocessor for control functions, and high-speed FIFOs for data storage. We report about the general design, our experiences with this proof-of-concept implementation, and recommendations for future work.