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Time prediction in High Level Synthesis

Many tools and environments have been developed to aid hardware designers to carry out the implementation of Application-Specific Integrated Circuits (ASICs). Most of them are aimed at implementing the lower level details of a target circuit with project constraints such as: area, timing, power consumption and so on. At a higher level, these tools have been written in hardware description languages (HDLs) to attend different objectives: algorithms, hardware, communication, specification and environments. High-level simulations are often referred to as behavioral, because only the overall behavior of component devices is made externally visible. On the other hand, structural simulation represents a more precise description of components. The growth of system complexity has made gate-level hardware design increasingly difficult. We discuss the needs of actual system specification with time prediction. Instead of using events in time, also known as reactive model, we use the transformational system technique, where an implicit list with local dependencies of data are defined together with a list-scheduling. We use a hierarchical structure of components, an object-oriented language, to this propose an environment aimed at a transformational model in a simple HDL.