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Assessment of charge-induced damage from High Density Plasma (HDP) Oxide Deposition

Plasma CVD oxides play a critical role in back-end process integration of the sub-0Spm node interconnect. In particular, HDP-CVD offers unique solutions to ILD challenges by achieving gap-filling of small geometries without void formation, while maintaining a high oxide quality with low etch rate and hydrogen content [I]. The HDP-CVD process uses a SiH4, 0 2 , Ar chemistry and an Inductively Coupled Plasma (ICP) source to generate a high density plasma on the order of 1E12 ions/cm3. Sufficient concentration of ions at low-pressure is provided to simultaneously sputter the depositing silicon dioxide at high efficiency when an RF bias is supplied to the wafer substrate. Thus, gap-filling of sub-0.5 p n geometries (like the one shown in Fig.1) is achieved by creating a faceted oxide profile that counteracts the “cusping” step coverage profile from PECVD-like deposition [I]. However, the use of ICP high density plasma (with substantial sputtering component) may stress the gate oxide of CMOS devices similar to our recent observation of severe charging caused by ICP metal etch [2]. In this paper we will assess the damage to transistors with 35 to 60A gate oxide when HDPCVD is used at metal level for interlevel dielectric (ILD) and poly level for poly-metal dielectric (PMD) applications.