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Synthesis of Early Output Quasi Delay-Insensitive Combinational Circuits

Problems related to the clock signal are increasing nowadays in the design of synchronous systems in nanometer technology. Asynchronous circuits are an alternative design because they operate by event, so they do not use the clock signal. An essential class of asynchronous circuits that are robust to PVT (process, supply voltage, temperature) variations is the class called quasi delay insensitive (QDI). However, QDI circuits have high overhead in the area due to signal coding, which uses delay-insensitive code and the excessive use of C elements. This paper proposes an architecture based on basic gates to implement QDI combinatorial circuits (QDI_CC) that require a reduced number of C elements in most applications. The QDI_CC circuits implemented in the new architecture interact with the environment in early output; therefore, they are robust in interacting with the environment, requiring a simple timing assumption. The proposal provides to be promising for a set of ten benchmarks comparing the proposed method with three methods from the literature. Our proposal obtained an average reduction of 65.3% in the number of transistors.