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A fully FPGA-based real-time simulator for the cascaded STATCOM

A real-time simulation for the Cascaded STATCOM fully implemented on field-programmable-gate-arrays (FPGA) is proposed in this paper. The switching-function model for the STATCOM is employed, where the IGBTs and diodes are taken as ideal switches, to reduce the amount of calculation. With the help of external circuit calculation, the operation in dead-time period is taken into consideration, which makes all of the operation modes covered. To eliminate the reverse current of diode in discretized simulation, a simple measure and approximation is taken by setting the negative calculated current zero. Full parallelism and deep pipelining are employed in FPGA implementation to minimize the latency. To make a full comparison, a Simulink-based STATCOM model and a 30A 380V scale-down STATCOM prototype were built respectively. The simulation and experiment show that the results from real-time simulator match those from Simulink model and the prototype pretty well, which demonstrate the effectiveness of the proposed real-time simulator for the Cascaded STATCOM.