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Opportunities for reduced power dissipation using three-dimensional integration

The opportunities for reducing power dissipation using three-dimensional integration, particularly the power needed to switch the interconnects, are investigated. In a three-dimensional implementation, both the gate pitch and the total interconnect length in gate pitches can be reduced from the values required in a two-dimensional implementation. The simultaneous scaling of these two values leads to an overall reduction in the interconnect power by roughly a factor of the square root of the number of strata. For example, use of four strata leads to roughly a 50% reduction in total interconnect power. The reduction in interconnect lengths leads to smaller interconnect capacitances, offering the opportunity to lower transistor power as well.