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Tolerance Analysis Using Behavioral Models

This paper describes a hierarchical approach to tolerance analysis, which we apply to mixed analogue-digital circuits using behavioural simulation. Statistical behavioural models are characterized at the cell-level using the Monte Carlo method and device-level simulation. At the cell-level, we characterize the behavioural model for a given number of circuit instances, which reflect manufacturing tolerances. This allows the behavioural parameters to be described with statistical information giving the nominal, standard deviation, correlation values as well as the distribution. The statistical behavioural models are then combined to allow efficient simulation at the higher circuit-level. We demonstrate the method using a 6-bit ADC, and give comparisons between results obtained from behavioural and device-level simulation. Full statistical performance variation can be obtained with significant improvement in computational speed.