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Design guideline for CMOS drivers with considerations of simultaneous switching noise

This paper describes a design guideline for CMOS drivers considering the simultaneous switching noise (SSN) on the power bus. This guideline employs two practical design parameters: the gate propagation delay of the active (or switching) drivers and the noise on the outputs of the quiet drivers. From the SSN model including the quiet drivers, the formulas for these design parameters are derived and used for constructing our design guideline. A safe area satisfying the given constraints on the design parameters is obtained as a function of the MOSFET channel width and the effective inductance of the power bus. The proposed formulas for design parameters and the design guideline for the drivers are confirmed through HSPICE simulation using a level 28 MOSFET model of a 0.35 /spl mu/m CMOS process.