{'fraction_non_alphanumeric': 0.05090497737556561, 'fraction_numerical': 0.03619909502262444, 'mean_word_length': 4.462962962962963, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully reconfigurable 3-tap baud-spaced feed-forward equalizer (FFE). The TX uses a segmented tailless current mode logic (CML) driver topology. The key architectural and circuit techniques include the thermometer-encoded driver slices, the clock phase selection circuits to perform segment reassignment to different FFE taps, and coarse–fine tuning of the FFE tap weights. The measured energy efficiencies for PAM-4 signaling are 1.33 pJ/b at 128 Gb/s with 1-Vppd output amplitude and 1.0 pJ/b at 112 Gb/s with 0.6-Vppd output amplitude. These results represent the highest data rate and best energy efficiencies reported to date.