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Extensions of open core protocol and their high level verification using system verilog and UVM

Today's scenario of semiconductor technology is a tremendous innovation, System on chip (SOC) design is of a great number of Intellectual property (IP) Cores which requires an efficient protocol for all types of operations. Large scale SOC gets more demanding due to the unavoidable importance for IP reuse, complexity and abridging the design time while encouraging IP core reusability for SOC designs. Extended modes of a non-proprietary protocol like Open core protocol (OCP) are more efficient. OCP comes under socket based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of Extended OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.