{'fraction_non_alphanumeric': 0.019672131147540985, 'fraction_numerical': 0.005245901639344262, 'mean_word_length': 5.577586206896552, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and Analysis of Ultra-Low Power Adiabatic Computational Subsystem Based on Symmetric Stacking

A novel design is proposed for the implementation of low power efficient charge recovery logic (ECRL) based adiabatic driven computational subsystem. An ultra-low power adiabatic ECRL circuit operates primarily in subthreshold regime, and is reported to consume less power as compared to CMOS implementation. Multiplier is considered a common building block in today's computation intensive design, included for various applications, however the same optimum design flow does not suit for ultra-low power applications. Higher order multiplier subsystem designed for ultra-low power requirements, involves multiple stages including compression module to reduce partial products, and generate product. The novelty of the proposed design is in applying specifically 6:3 compressor circuit to eliminate XOR gate in the critical path of the ECRL based adiabatic logic, leading to a compact layout, significant reduction in power, and performance improvement. The paper analyzes ECRL based sub-threshold driven adiabatic logic applied on 6:3 compressor circuit and further implements the same on a higher order 8 × 8 Wallace tree multiplier module. The symmetric stacking modified ECRL based adiabatic Wallace tree multiplier is recommended for ultra-low power and non-time critical driven biomedical applications. The proposed design was implemented in Cadence, and the simulation results for 45 nm technology node are reported.