{'fraction_non_alphanumeric': 0.02081165452653486, 'fraction_numerical': 0.003121748178980229, 'mean_word_length': 5.413333333333333, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Accelerating FinFET MOL Process Development Using Design for Inspection Methodology

This paper demonstrates application of the voltage contrast-based Design for InspectionTM (DFI) methodology to accelerate development of a logic FinFET technology. Two features of DFI make it extremely effective – in-line detection of electrically active defects, including systematic marginalities, and an ultra-dense design of test structures for process window metrology. This work focuses on 14nm FinFET process development and shows specific use cases for DFI to speed up the development cycle. DFI test structures are designed for middle of line (MOL) critical fail mode detection and process window characterization and they are tested at the contact (M0) layer with a high speed electron beam tool. Two systematic fail mode examples, related to Active and Gate Contacts, are discussed, with the data collected on a large number of wafers during technology development.