{'fraction_non_alphanumeric': 0.024549918166939442, 'fraction_numerical': 0.007364975450081833, 'mean_word_length': 4.635944700460829, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
FPGA implementation of an indoor broadband power line channel emulator

Power line communication is an emerging technology in the field of communications that aims to use the power line as a medium to send and receive data. Several studies have been conducted to characterize the power lines [1], [2], [3], [4],. These studies guide PLC modem designers to create a more robust design. However, it is not practicable to test modems in a live power line network. This research aims to create an emulator capable of replicating the behavior of a typical indoor power line channel and use it as a test bed for PLC modem The emulator is implemented on Virtex 6 FPGA and FMC 151 for the analog front end. The power line channel model uses Zimmerman's channel transfer function [5] as reference. Analysis are done by comparing theoretical results with the hardware results which are done in MATLAB and Xilinx respectively. Several features such as addition of noise are also within the emulator and can be selected by the user to improve the realism of the emulator. Lastly, channel parameters such as SNR (signal to noise ratio) and RMS (root mean square) delay spread are obtained to ensure the quality of the channel produced.