{'fraction_non_alphanumeric': 0.024282560706401765, 'fraction_numerical': 0.0051508462104488595, 'mean_word_length': 4.690376569037657, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Chip Package Interaction and mechanical reliability impact on Cu/ultra low-k interconnects in Flip Chip package

The chip package interaction (CPI) induced by the mismatch in coefficient of thermal expansion (CTE) between chip and package in a flip chip ball grid array (FCBGA) and its impacts on the mechanical reliability of Cu/ultra low-k interconnect were investigated using finite element analysis (FEA). 3D and 2D multi-level sub-modeling technique was used to link the deformation from the package level to the interconnect level. The energy release rate (ERR) at the critical interface in interconnect structures was calculated using a modified virtual crack closure technique to analyze the impact of CPI on the reliability. First, the CPI in a four metal-layer interconnect model was investigated. The ERR at upper layer was higher than that at the lower layer, when the same low-k ILD is used for all layers. However, the ERR at M3 interface becomes 35% higher than the M4 level when TEOS is used in the M4 level. The interconnect design and the mechanical properties of ILD were found to be important to control CPI. Then, the ERR dependence on the crack length was analyzed using seven and nine metal-layer interconnect model. The ERR was found to increase with the crack length which indicates that the crack will keep growing once it propagate.