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A 14.5-bit ENOB, 10MS/s SAR-ADC with 2nd order hybrid passive-active resonator noise shaping

A new 2nd order noise shaping (NS) based successive approximation register (SAR) ADC is presented in this paper. In comparison to earlier research, this paper considers hybrid passive-active integrators to compensate for the phase error of the passive integrator. To realize the resonator noise shaping in high-speed asynchronous SAR-ADC, the hybrid passive-active sigma-delta modulator (SDM) is introduced as a multi-input feedforward loop filter to overcome the noise barrier of the conventional asynchronous SAR-ADC generated from the CDAC, quantizer, and dynamic comparator. The proposed noise shaping technique significantly reduces the ADC power consumption and area compared with the active SDM noise shaping approach while overcoming the shortcomings of passive SDM, such as large-area penalty, low resolution, and low speed. It consists of a very low power forward gain G and a positive feedback path across a 1st order passive switch capacitor (SC) integrator to desensitize the capacitor ratios under PVT variations. Extensive circuits simulation verifications and system-level results have been used to validate the effectiveness of the proposed NS SAR-ADC. The simulation results show that the proposed SAR ADC consumes 0.88mW at maximum speed, with an SNDR of 89.43 dB and SFDR 98.64 dB within 0.1 fs oversampling frequency.


I. INTRODUCTION
In modern communication systems, several high-precision analog-to-digital converters need to be used. To meet the requirements of high precision and wide bandwidth, a series of new ADC structures have successively appeared. Noise shaping successive approximation ADC (NS SAR-ADC) is one of the most popular structures studied in recent five years. While the conventional SAR-ADC has low power consumption and a small area [5][6][7], the comparator's noise, offset, quantization noise, and the CDAC thermal noise limits its accuracy. The sigma-delta ADC is the most used structure to achieve high precision, but due to the need for many opamps in this structure, its power consumption is high, and the area is large. The NS-SAR ADC structure is a hybrid SAR-ADC and sigma-delta modulator (SDM) that inherits both advantages. It has the characteristics of low power consumption of the SAR ADC and a considerable potential to achieve high precision of sigma-delta ADC. Moreover, NS SAR-ADC requires a lower oversampling ratio (OSR) than the traditional sigma-delta modulator, thus increasing the bandwidth of the circuits. References [7][8][9] described methods for reducing the inputreferred noise and offset of SAR ADC using a time-domain comparator to reduce the total power at the cost of a slow conversion, making it less desirable for high-speed applications. The SDM is the most critical candidate architecture considering oversampling and noise shaping techniques from a high-resolution perspective. An active integrator based on opamps is the critical component, typically power-hungry and challenging to scale. SAR ADC with an SDM significantly improves the capability of a noise-shaping (NS) SAR-ADC to overcome the deficiencies mentioned above, making it a preferred approach for delivery of both high resolutions and low power consumption simultaneously [1][2]. The authors [1] proposed a noise-shaping technique using FIR and IIR filters. For sampling the residue voltage, a two-tap charge-domain FIR filter is utilized. An IIR noise shaping filter constructed from operational amplifiers serves as an integrator to enhance noise shaping. Nevertheless, an active integrator is introduced, which inevitably deteriorates the energy efficiency and scalability of the circuits. In [3], the authors have proposed a first-order noise shaping without the requirement of opamps Using passive integrators, the design has high efficiency without interrupting the normal SAR-ADC operation. In this case, the zero of [3] is set at 0.5, indicating poor noise shaping and the resulting signal attenuation of 6 dB. Furthermore, in recent research publications [4][5][6], second-order passive shaping techniques are proposed to increase the DC attenuation in the NTF(z), where the values of α and k, which refers to the capacitor ratios and comparator gain, should be increased significantly, as explained in Section II-A, which inevitably increase the area of the chip and the power. Therefore, the loop dynamics in terms of ADC speed and stability will be significantly impacted because the CDAC settling time is one of the most critical bottlenecks for highspeed SAR-ADC. This paper proposes a second-order low-power hybrid passiveactive NS-SAR ADC architecture to overcome the aforementioned problems. In contrast to prior works, the passive-active integrators based on low gain open-loop opamp are used in the loop filter instead of conventional opamp-based active integrators. Zeros in the system are determined solely by the capacitor ratio and positive feedback compensation, insensitive to process, voltage, or temperature (PVT) variations. Moreover, a resonator is introduced in the loop to achieve wide noise-shaped bandwidth.
Aside from noise shaping techniques, the choice of capacitive CDACs is also of critical importance. It has been demonstrated that DAC switching schemes such as monotonic switching (MS) provide very good energy efficiency. Compared to conventional structures, this topology reduces switchingrelated energy losses by 81% [10]. The MS structure degrades ADC performance due to variations in the common-mode level offset within the comparator. To stabilize the dynamic amplifier's input common-mode (CM) level, a common-modestabilization (CMS) circuit is proposed within the NS SAR ADC architecture. This paper is organized as follows; Section II focuses on the fundamental theory of noise-shaping SAR-ADC and design considerations. Section III details the proposed NS SAR-ADC architecture, including proposed noise shaping architecture and detailed circuits implementation. Section IV describes the extensive simulation results from the system and circuits levels and other building block designs. Section V summarizes the paper's conclusions.

II-A Passive integrator vs. Active integrator
where C S is sampling capacitor and C i is integrating capacitor. As opposed to the ideal active integrator transfer function (1), the passive integrator's transfer function (2) exhibits both gain and phase error. Due to the built-in analog trade-offs, the passive transfer function cannot be modified to resemble an ideal active transfer function. First, to reduce gain error, C S must be greater than C i , which results in an increase in phase error. Furthermore, C i should be greater than C S to reduce phase error, which leads to increased gain error. Thus, there is a trade-off between sizing C i and C S . The feedforward gain of the comparator usually can compensate for the gain error in NS SAR-ADC, while noise shaping is not properly performed if excessive phase error occurs. Since the phase error is crucial, it shifts the pole of the integrator and, therefore, the zero of the NTF of the loop filter as well, according to (3). This pole shift flattens the low-frequency part of the noise transfer function, which in turn significantly reduces the effect of noise shaping within the bandwidth.
Similarly, as shown in Fig.1(c), the works published in [5][6], [9] with 2 nd order passive noise shaping have severe limitations, which refers to the DC suppression and stability requirement. To satisfy the noise shaping capability and stability requirement, the 2 nd order passive noise shaping requires excessive capacitor ratios, α 1−2 Comparator gain for noise-shaping, which dramatically reduces the ADC's speed and large area penalty and inevitably introduces considerable kickback noise and dynamic power for the comparator, as discussed below. Assume the complementary capacitive-DAC (CDAC) has a capacitor value equal to C, and Stability analysis from the Jury array gives: To reduce the phase error, α 1 and α 2 must assume large values. Also, the reduce the gain error and ensure stability, the comparator gain must be large. In the passive NS SAR multi-input latch comparator, as depicted in Fig.2, the gain is provided by the input transistors. Increasing the gain at the expense of increasing the size of the input transistors has severe limitations due to non-idealities associated with the multi-input dynamic latched comparator that limits the resolution of passive NS SAR ADC. The non-idealities associated with a typical multi-input dynamic latched comparator are offset voltage, thermal noise, and kickback noise. The kickback noise can be problematic when it comes to high-speed SAR ADC, causing the settling time and the accuracy of the decision to be significantly affected. While upsizing the input MOS pair M1,2(a-c) of the comparator can increase the gain and reduce thermal noise, it will have an adversary effect on increasing the kickback noise due to higher drain-gate parasitic capacitances of the input MOS pair.
The Kickback noise is dynamic in nature, as the input MOS pair in the whole comparison process can operate in a variety of regions (such as cut-off, saturation, or triode), which will have a significant impact on the accuracy of the decision [22]. The full expression of kickback noise of multi-input latched comparator can be written as: where V cm is the common-mode level of V p and V n . CGB is the equivalent capacitance between the gate and substrate, Cgs and Cgd are the gate-source and gate-drain overlap capacitances, respectively. WLCox refers to the gate oxide capacitance, including the input pair (M1a-M2a) used for the normal SAR conversion and input pairs (M1b-M2b, M1c-M2c) used for noiseshaping. In the passive noise-shaping techniques described in the literature, the feedforward gains 1,2 implemented at the inputs of the comparator need to be substantially large to guarantee stability according to (4d), while high α 1 and α 2 must be large to reduce the passive integrator's phase error.
Since increasing the gains results in increased kickback noise charges, induced at the gate of the input MOS pair M1-2 during both comparison and latch operations, that will degrade the ADC resolution.
The previous analysis concludes that the multi-input comparator gains 1,2 must be large enough to improve the NTF(z) at its DC suppression, satisfying the stability requirement while maintaining small enough to reduce dynamic power and kickback noise, leading to a design tradeoff. We can find in the available 2 nd order passive NS SAR ADC in the literature, the area of the integrator capacitor is around four times larger than the CDAC capacitor (α 1,2 ≅ 4) and that limits the speed and increases power consumption. Also, the resolution of the ADC is limited by the kickback noise of the multi-input comparator due to high gains 1,2 values.

II-B Direct 2 nd order SDM implementation-based noise shaping analysis and its limitations
To improve the noise shaping performance compared to passive implementation, direct noise shaping is derived from an ideal 2 nd order SDM. The ideal noise transfer function, NTF ideal ( ), is implemented as shown in Fig.3(a)-(b). Since the ideal noise transfer function has no stability issues, it is used directly. Its corresponding loop filter transfer function is: When the normal SAR-ADC conversion is done, the input signal Vin is converted directly into digital outputs through the comparator. Therefore, the STF is always equal to 1 in the NS   SAR-ADC. Note that the normal SAR-ADC residue after conversion is a low-frequency DC signal and that dictates the choice of the SDM architecture. Two main design strategies could be applied in NS SAR-ADC. The first one refers to the direct implementation method is to use a lower-resolution SAR-ADC (< 8bit) with a noise-shaping module with a strong shaping capability. This strategy is implemented with an active opamp-based integrator, including multiple high-performance opamps, which consume much static power. The second strategy is to use a medium-resolution SAR-ADC (~10-bit) with a noise-shaping module with medium-shaping capability, composed of a very low-power active integrator or passive integrator and consumes less power. Fig.3(a)-(b) shows system-level and circuit-level implementation of the direct implementation refers to the first strategy. When clock 1 is high, the first stage and the feedforward path sample the normal SAR-ADC conversion residue. The second integrator stage samples the previous value from the first stage integrator output. When the clock 2 is high, the first stage integrator starts its integration, and at the same time, the second stage integrator and the feedforward path transmit the value sampled in the first half cycle through the output. However, unlike opamp-based sigma-delta modulator design trade-offs, the proposed SAR-ADC requires the SDM input signal to be a DC value, and the amplitude is around 1 LSB of the standard 10bit SAR ADC without NS, which significantly relieves the slew rate requirement of the opamp. The integration phase has to have a speedy settling response during noise shaping before the comparator works in the following conversion cycle. Consequently, the approximated unity-gain bandwidth of the opamp has to be very high, leading to high power consumption. In addition, opamp with a finite DC gain will introduce higherorder harmonics at the ADC output. As a result, the opamp has to have a fast settling time and large DC gain, but it has a relaxed slew rate requirement.  Fig. 4 illustrates a technique that utilizes positive feedback across a passive 1 st order SC integrator, which is inspired by [17][18] and can compensate for the phase error. Moreover, it is possible to compensate for the second stage integrator phase error with an input gain . A detailed illustration of the block diagram of the proposed SAR-ADC is shown in Figure 5.   With resonator (c)

FIGURE 8. (b)-(c) Passive-active noise-shaping NTF(z) with/without zero optimization
The proposed NTF(z) has two zeros which refer to as z1 = 1 − α 1 , and z2 = 1 − α 2 (1 − β). The closer the zero of the NTF(z) to 1, the stronger the NS capability is, which means the integrator is closer to ideal. Compared with the entirely passive noise shaping techniques, the essential advantage of the proposed solution is that increasing to improve the noise shaping capability will not introduce extra power and kickback noise to the comparator. Since The open-loop gain and compensation factor β simultaneously work toward achieving better shaping ability, significantly reducing the noise and improving the resolution of the ADC. A better shaping requires a smaller α 1 value that is limited by the KT/C noise. The zero location of z 2 is determined by β , while β is set at approximately one to minimize the phase error of the secondstage passive integrator. Moreover, the KT/C noise of the second-stage passive switched capacitor integrator is referred to as the input and will be divided by the opamp gain, so the size of the second-stage integrator capacitors has a negligible effect on the thermal noise. While the lower limit of thermal noise is considered in the first stage passive integrator sampling capacitor C s1 since α 1 , α 2 are designed to be around 0.15~0.25 in the proposed ADC. The minimum Cs1 is given by: where K represents the Boltzmann constant, T is the absolute temperature, N is the effective number of ADC bits and V FS represents the full-scale input. The second stage output noise is simply equal to the equivalent RC integrator shown in Fig.  1 (b). Thus, the SC resistor R acts the same as a resistor in terms of thermal noise power which will not influence the noise in the output spectrum. The second stage input-referred noise can be written as: Author Name: Preparation of Papers for IEEE Access (February 2017) VOLUME XX, 2022 1 Fig.8 shows the proposed loop filter designed with passiveactive architecture and resonator feedback to improve the ADC noise-shaping performance and bandwidth further. In our proposed noise-shaping module, conjugate zeros are introduced in NTF(z) by adding a local negative feedback loop at the input and output of two cascaded passive-active integrators. The local feedback changes the loop filter poles, making them shift away from DC to enhance the noise shaping performance. To evaluate the performance of the proposed noise shaping module with a resonator, the complete transfer function of the proposed sigma-delta modulator is written as the following, and the simulation of the resonator effect is shown in Fig.8 (b)-(c).
Reference [17][18] uses a low-gain Opamp with a positive feedback circuit in a discrete-time sigma-delta modulator to solve the gain and phase errors caused by the passive switched capacitor integrator. However, its input signal amplitude is limited to a small range. The ratio of rail-to-rail voltage swing to maximum input swing is 55%. However, in a noise-shaping SAR-ADC, the input signal is first converted fully by the conventional high-speed SAR-ADC and then integrated through the noise-shaping block, and the signal entering the noise-shaping block has a small amplitude. Therefore, this active-passive hybrid noise shaping technique is much more suitable for noise-shaping SAR ADC compared with the sigma-delta modulator. The capacitor ratios α 1 and α 2 are composed of capacitance ratios, which have high immunity to process variations. The opamp gain G is designed by simple common-source amplifiers. The proposed NTF and pole-zero stability analysis in Fig.7 shows great robustness of the circuits under gain variations. It has demonstrated that with significant variations of , the proposed NS SAR ADC can maintain its stability as long as α 1 and α 2 can be small enough, and the limitations of parameters are the thermal noise of the ADC. Moreover, second-order noise-shaping designed in an activeactive module, which realizes an ideal NTF, will not be a proper candidate for two reasons: (1) high sensitivity for the discrete-time loop dynamics compared with the proposed hybrid passive-active solution and (2) common-mode noise leakage from the SAR regular conversion. Like the previous analysis, the stability analysis of active-active noise shaping arrangement is the following: Apply Jury Array for stability gives: { Den(1) = G 1 α 1 G 2 α 2 > 0 Den(−1) => G 1 α 1 G 2 α 2 − 2G 1 α 1 + 4 > 0 −2 The active-active module has more strict stability requirements compared with (9c) and (12). Fig.9 and Fig.10 demonstrate the active-active module's stability variations and common-mode noise leakage problems. The system simulation of stability analysis shown in Fig.9 is performed while considering enough design margin of thermal noise from the switch capacitor integrator with, α 1 = 0.25 , α 2 = 0.15 , β = 1 as a typical example. Compared with the proposed technique stability plot in Fig.7, the stability requirements are stricter, making the circuits more sensitive to PVT variations. Moreover, as shown in Fig.10, CM noise leakage is severe due to the low opamp gain, which reduces the ADC noise shaping performance. Since the open-loop opamp with low gain will be greatly affected by the common-mode noise suppression from the SAR conversion, the passive stage based on bottom plate sampling is selected as the first stage in the proposed design. While the ideal solution for a low-power NTF implementation is an active-active architecture using an open-loop opampbased integrator, the variations in the integrator coefficients and the DC gain of the opamp will impact the stability of the entire discrete-time loop dynamics, and it will be sensitive to PVT variations. Equations (12a)-(12c) demonstrate that the gain coefficients G 1,2 are highly related to stability, which is relatively difficult to achieve compared to the proposed passive-active implementation. Fig.11 shows the proposed asynchronous SAR ADC architecture. This ADC design adopts the bottom-plate sampling method to minimize charge injection and clock feedthrough from the sampling capacitor during the sampling phase. The bottom-plate sampling mainly takes advantage of disconnecting the sampling capacitor bottom plate so that the leakage charge from the sampling switch will not be injected into the sampling capacitor top plate. Another advantage is that when the proposed NS-SAR-ADC is under the sampling phase, the noise-shaping module can still perform its 2 nd integration (refer to Fig.10 & Fig.14) before the subsequent cycle conversion starts. Therefore, it significantly improves the speed of the ADC. A multi-input-based comparator shown in Fig.12 (a) and a self-ring clock generator shown in Fig.12(b) are used to perform the summation function for the coefficients at the differential nodes DACP and DACN. Fig.13 shows the proposed low gain open-loop amplifier with positive feedback.

III. CIRCUITS IMPLEMENTATIONS AND DISCUSSIONS
As the amplifier includes a built-in adding function for superimposing the signal in the positive feedback path, the required power is very low since gain and speed requirements are relaxed. Another important design aspect is that the biasing current is implemented with a constant-gm biasing to remove the resistor process dependency according to (13a-13c) owing to ratio of the resistors. During the normal conversion process of the proposed SAR ADC, the conventional monotonic switching scheme moves the comparator input common-mode level monotonically towards VSS or VDD, causing the conversion gain of the comparator to vary with the input, which would introduce signal-dependent offset to the ADC, degrading the linearity and noise-shaping performance of the ADC. The comparator in the preamplification phase has a significant influence on the offset voltage of the comparator [12] and can be written as: where ∆V TH is the mismatch between the threshold voltages of the inputs , ∆S S is the input pair size mismatch, and ∆R R is the Loading pair resistance mismatch. In accordance with equation (14), the offset voltage is affected by mismatches in the devices and their bias conditions. The static term in the expression does not impact the precision of the ADC. Moreover, the overdrive voltage has an impact on the second term. MS scheme results in a gradual decrease in the input CM level of the comparator as the MS scheme is employed. To stabilize the comparator input common-mode voltage, [23][24][25][26] introduced an additional DC voltage source. The DC voltage reference buffer requires a large driving capacity, introducing extra power consumption. This work proposes the use of identical capacitors in the common-mode-stabilization (CMS) array whose bottom plates will undergo a transition from VSS to VDD to compensate for the CM drop of the MS CDAC as shown in Fig.11. The CMS capacitors are approximately half the size of their MS DAC counterparts. The OR gate that implements the VSS to VDD transition has two inputs: 1P-2P and 1N-2N, respectively. Due to the majority of CM variation occurring around the MSB, CMS is applied to only the first two MSB bits. As a result of the i th comparison, the voltage swing on each side of the DAC is derived as follows: where ∆V pi and ∆V ni are the i th positive and negative voltage swings on both sides of the DAC. C u is the unit capacitance, C T is the total capacitance of the DAC, and B i is the i th comparison result. It should be noted in (15)-(16) that the MS network and CMS network are both represented in the first and second terms, respectively. Regardless of the value of B i , the summation of ∆V pi and ∆V ni remains zero. Therefore, the input CM remains constant at the moment of comparison.   Figure 14 shows the proposed NS SAR-ADC timing diagram where the normal SAR-ADC conversion is complete before phi1. The common-mode level remains constant around VDD/2, and the passive integrator1 and active integrator2 are operating when phi1, phi2, and phi2, phi3 are switched on, respectively. The CMS circuits allow the comparator to maintain a low offset and prevent metastability.Another advantage of the bottomplate sampling is that the sampling clock phi3 can also be used as integrator2 integration clock since the new cycle has not yet started during the input sampling phase, increasing the conversion time and improving the ADC speed. The proposed circuits level implementation is working under a 1.8V power supply, 10MHz sampling clock rate, and the dynamic comparator is working under a 150MHz asynchronous clock. Fig.15 shows the power spectrum before and after noise shaping, in which the input signal frequency is about 250KHz, which is within 1/4 of the ADC bandwidth to include the 3 rd order harmonics in the bandwidth.

DACP
The designed conventional high-speed asynchronous SAR-ADC without noise shaping shown in Fig.15(a) can achieve only 9.01-bit effective number of bits (ENOB). Fig.15(b) and Fig.15(c) show the proposed 2 nd order hybrid passive-active noise-shaping SAR-ADC with/without a resonator formed by a negative feedback path between the proposed two cascaded VOLUME XX, 2022 1 passive/active integrators. The negative feedback loop is introduced to change the position of the zeros of the NTF(z) so that the bandwidth of the ADC can be further improved and noise suppression capability is strengthened. The signal-tonoise and distortion ratio (SNDR) is improved by 5dB, which demonstrates very good agreement with the system-level simulation results from Fig.6. The performance comparison with other works is summarized in Table I.

V. CONCLUSION
The paper proposed a novel high-speed SAR-ADC with 2 ndorder noise shaping. The noise shaping technique is designed as a passive-active arrangement, utilizing a low-gain, openloop amplifier with positive feedback. This implementation reduces the area required for passive integrator noise shaping and compensates for the gain and phase errors from passive implementation. The common-mode stabilization technique is applied along with the monotonic switching technique, which prevents the common-mode level shift during SAR conversion and helps to improve the circuit's performance. The circuits simulation results in 180nm achieving an SNDR of 89.4 dB, an SFDR of 98.6 dB, and a THD of 0.0003%. The power consumed is 880 μW at a supply voltage of 1.8V.