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Efficient encoding and decoding algorithm used in Reed-Solomon codes for multiple fault-tolerance memories

With the increasing density of transistor and the probability of MBUs (Multiple Bits Upsets), Hamming code is not enough to provide required reliability in memories. Therefore multiple error correction codes are necessity. In this paper, Reed-Solomon (RS) codes are proposed to protect memories against MBUs which can achieve higher error correction capability (e.g. 8 bits). Besides a novel and low overhead multiplication algorithm is proposed and used in RS codes encoding and decoding process. At last, the encoder and decoder are implemented using Verilog HDL and validated through a number of simulations. The experiment results show that compared with other ECCs, RS code has higher error correction capability and lower area overhead.