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Reconfigurable-hardware-based digital signal processing for wireless communications

This paper presents, index mapping, a technique to efficiently map a widely used class of digital signal processing algorithms onto a space/time paradigm with immediate representation as the partitioning and scheduling map of a small, I/O efficient, hardware array. When applied to reconfigurable FPGA based hardware architectures with downstream sea-of-gates optimization methods, the resulting systems form a dynamic signal processing environment with the best mix of performance and flexibility for wireless applications. Herein, index mapping is demonstrated with a mapping of the fast Fourier transform (FFT) onto an FPGA computing machine, the reconfigurable processor (RCP).