{'fraction_non_alphanumeric': 0.02406159769008662, 'fraction_numerical': 0.0038498556304138597, 'mean_word_length': 5.117647058823529, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Power and variability analysis of CMOS logic families @ 22-nm technology node

Technology scaling driven by the benefit of integration density, high-speed of operation and low-power dissipation, has overcome many barriers over the last four decades. Currently, it is facing even more hurdles, which are more critical than earlier. One of them is variability. Variability is becoming a metric of equal importance as power, delay, and area. This work attempts to perform power and variability analysis of the most popular CMOS logic families to identify the logic family that consumes minimum power dissipation and offers narrowest spread (i.e., minimum variability) in the design metrics of NAND/AND circuits. This paper explores the challenges of designing ultralow-power and robust circuits with unreliable devices in highly scaled technology node such as 22-nm. The logic families offering minimum power dissipation and variability are reported to aid the designer in selecting the best logic famility depending on specific requirements.