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A Programmable Load/Store Unit on C-based Hardware Design for FPGA

This paper proposes to introduce a programmable load/store unit (LSU) to C-based hardware design for an FPGA. The LSU provides flexible memory access methods that can hide memory access latency for hardware modules generated by a high-level synthesis tool. The hardware module with the LSU can treat efficiently not only simple streaming accesses but also sophisticated accesses such as image processing. The LSU is evaluated using two case studies. The result shows that the LSU can significantly reduce the burden of designing the dedicated memory access circuits and the hardware modules with the LSU achieve a speedup of 16.5 and 27.3 times compared with an embedded processor.