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Enabling incremental RET to exploit hierarchical structure across multiple designs for sub-100 nm lithography

Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional optical proximity correction (OPC) tools process design layouts in a sequential mode layer by layer to ensure stability of the resolution enhancement technology (RET) corrections. A typical sub-100 nm design layout is very large and OPC expands the data volume significantly. The large data volumes and long run-times associated with conventional OPC are becoming critical bottlenecks for manufacturing turn-around time. In a full-chip layout comprised of a library of cells, a cell may be instantiated thousands of times. Aprio's incremental OPC technology applies a design-like methodology that exploits the hierarchical structure of the layout. OPC is applied once per master cell rather than once per cell placement. The master cells are reused and can be instantiated across different designs. These pre-OPC'ed cells are reconverged or "stitched" together at their interacting halo areas to build up proximity-corrected, hierarchical layouts. This alleviates the need to run OPC sequentially on multiple designs where the master cell is instantiated, thus leading to significantly reduced run-time and data size. We are able to extend this to applications such as manufacturing engineering change order (ECO) handling and design re- spins without the need to rerun the entire OPC layout. Since our incremental technology can "stitch" together previously OPC corrected areas and cells, we are able to combine less complex areas along with "critical-care" areas leading to a more robust final layout that is optimally designed for manufacturing.