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Automated approach to Register Design and Verification of complex SOC

Today's designs contain several hundreds to thousands of registers and memory elements. Starting from documentation to design implementation to verification of each single register, each bit and its property involves a lot of time and complexity. Use of a single source, written in a high-level register and memory modeling language like SystemRDL, for documentation, design and verification helps to reduce this complexity. The paper describes this methodology which provides an almost zero-time, low maintenance, and reusable register design and verification system. A complete solution from SystemRDL to RTL and documentation, to a complete reusable VMM based register verification environment, the Register Abstraction Layer-RAL, is discussed The paper presents useful RDL constructs for modeling scalable register descriptions, like registers arrays, regfiles and register field instantiation. Also presented are constructs for modeling standard register types like interrupt enable and interrupt status register. A few useful field properties and their mapping to hardware implementation are discussed. Commercially available register automation tools can be used to generate several outputs from SystemRDL input. This includes document, RTL, C headers, verification components and other custom outputs which may be required. Challenges encountered while setting up the flow with third party tools are discussed. An example comprising a set of read-write and status registers is provided to help in understanding the transition of the input to the outputs formats. Once setup, the flow is repeatable and can be used across block, cluster (Sub chip-level) and chip level, with lot of reuse of code and environment