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A simple and accurate method to predict offset voltage in dynamic comparators

In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE level 1 model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.