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Modeling Lateral Parasitic Structures of Multiterminal Devices in Smart-Power Technologies

In this work we describe an improved compact model for MOS transistors built in an advanced vertical smart-power technology that includes the effects of lateral parasitics. Deriving the topology of the model on the basis of physical structure and layout geometries, we extended multiterminal compact models to correctly predict influence of both vertical and lateral parasitic couplings between each component and the collector of the power device. The described approach guarantees physical meaning for model parameters, a clear definition of the parameters extraction procedure and a similar model structure for parasitic components for bipolar devices as well. Simulation results obtained by using the proposed models show good agreement with experimental data for both single device in test struc-