{'fraction_non_alphanumeric': 0.008934707903780068, 'fraction_numerical': 0.0006872852233676976, 'mean_word_length': 5.471111111111111, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and implementation of WDF for digital down converter on FPGA for LTE application

As technology is growing wireless communication is also rapidly growing and finding potential application in industries. Development of highly efficient DDC architecture is very important since with rapid technology growth need for complex services are increasing demanding for high data rate transmission and high speed multimedia services. In DDC system two major operations are carried out. First one is frequency translation and second is channel filtering. Different chain of decimation filters can be used to perform channel filtering and decimation operation. Digital IIR filter known as Wave Digital Filter is used as decimator as it offers guaranteed stability, low passband sensitivity and regular structures and also lower order to meet the desired specifications. This paper describes the modeling and analyzing of the Lattice WDF structure using Simulink blocks and Xilinx black box to be implemented in DDC system as first stage to perform decimation operation. The design parameters are sampling frequency, passband frequency, stopband frequency, passband ripple and stopband attenuation defining the gamma and alpha coefficients of the WDF. The proposed filter performs decimation by factor of 2 and also resulting in overall less resource utilization on implementing the modified DDC system on FPGA platform making it attractive for LTE application.