{'fraction_non_alphanumeric': 0.03274336283185841, 'fraction_numerical': 0.02920353982300885, 'mean_word_length': 4.683417085427136, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Wideband Power Amplifier in 45 nm CMOS SOI Technology for X Band Applications

A fully-integrated wideband power amplifier (PA) operating in 9-15 GHz range is implemented in a standard 45 nm CMOS SOI technology. The PA is designed with three dynamically-biased stacked Cascode cells (6 stacked transistors) to overcome the low breakdown voltages of nanoscale CMOS transistors. The stacked Cascode cells ensure stable operation and facilitate high gain, and high optimum load impedance, leading to high output power, high efficiency and good linearity characteristics over the entire bandwidth. The unbalanced amplitude and phase of drain-source voltage signals caused by internodal parasitic capacitance are equalized by adjusting the sizing of transistors. With a supply voltage of 4.8 V at 12 GHz, the measured saturated output power and linear power are 22.5 dBm and 19.2 dBm, respectively, while the peak power-added efficiency (PAE) is 19.2%. At a reduced power supply of 3.6 V, the PA achieves peak PAE of 25.7% where the drain efficiency reaches 40.7%. Including its pads, the PA occupies a compact chip area of 0.22 mm2.