{'fraction_non_alphanumeric': 0.015996878657822865, 'fraction_numerical': 0.0039016777214202106, 'mean_word_length': 5.442211055276382, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Relating Surface Topography to Impedance Behavior in Solder Mask Coated Circuit Boards

To manufacture circuit boards, thin film metallic patterns are first designed and deposited onto FR4 substrates to form the circuit electrodes, followed by a subsequent deposition of a solder mask coat to better insulate the electrodes and prevent cross talking between them. Because this manufacturing process can deposit multiple circuits on the same board, it is often assumed that all circuits on the same electrical circuit board are identical and exhibit similar electrical responses. However, the electrical response of circuit boards is a multi-variate function of solder mask heterogeneity, exposure conditions, humidity, type of manufacturing technique, and sample surface topography among other factors. In this paper, identical circuits on the same solder mask coated board demonstrate a “dual” behavior response in its impedance response; a “high impedance” response and a “low impedance” response as seen in Fig. 1. Although this “high” or “low” behavior can be characterized by the impedance magnitude, the impedance phase angle also provides a means to distinguish the dual behavior responses measured. To gain better insight into the factors that drive the resulting impedance behavior measured, circuit topography was characterized to tie surface roughness parameters to electrical measurements. 3D surface profiling was done on five interdigitated circuits containing 25 pairs of electrodes each. All circuits examined were located on the same board and received no exposure treatment to isolate only the relationship between surface topography and impedance behavior. Each circuit examined showed three distinct regions classified by surface height. The tallest region corresponded to the positive electrode, the second tallest region to the negative electrode, and the lowest region to the solder mask. For each region measured on each interdigitated circuit, the surface roughness parameters were calculated using the Keyence VK-X3000 software and then averaged to represent the overall topography of the respective regions. The impedance measurements were then analyzed in the context of the respective region average height profiles and surface roughness parameters for each circuit to find relationships between surface roughness and electrical behavior. This paper introduces a new approach to understanding impedance behavior of solder mask coated circuit boards with respect to the circuit topography and roughness parameters.
 
 
 
 
 
 Figure 1
