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Built-in Self-Test Circuits for All-digital Phase-Locked Loops

This paper presents the design of an all-digital built-in self-test (BIST) circuit for all-digital phase-locked loops (ADPLLs). It measures clock jitter of the ADPLL and tests the PLL function blocks. The BIST circuit does not break the PLL loop. The jitter measurement circuit takes a frequency divider as a timing amplifier to linearly enlarge the input jitter. The vernier ring oscillator-based time-to- digital converter quantizes the jitter into digital codes, and the cycle-controlled delay line generates a self-test clock which avoiding using an external reference clock. The proposed BIST circuit for jitter measurement was implemented with standard cells and fabricated in 65nm CMOS process. The measured jitter error is about 11.32% with input frequency range 100-300MHz.