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Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuits

The gate disturb degradation mechanism in silicon-oxide-nitride-oxide-semiconductor (SONOS) FETs with a highprecision threshold voltage (Vth) tuning function, which is designed to compensate for the Vth mismatch in order to achieve high-performance analog circuits, was investigated in detail. A tendency for an unintended positive Vth shift under typical bias conditions in analog circuits was identified. The main cause of the positive Vth shift was determined to be the physical damage induced in the SONOS FETs during programming for Vth tuning. It was found that the use of a thicker block layer effectively suppressed this damage during programming. SONOS FETs that used a thicker block layer to reduce gate disturb degradation demonstrated excellent data retention characteristics, and data retention for ten years could be guaranteed.