{'fraction_non_alphanumeric': 0.025619128949615714, 'fraction_numerical': 0.011101622544833475, 'mean_word_length': 5.136125654450262, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A comparison of ILP based global routing models for VLSI ASIC design

The sub-micron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today's chip designs. Global routing is one of the key subproblems in circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several Integer linear programming (ILP) based global routing models are fully investigated and compared. Experimental results obtained show that the proposed combined model (WVZM) can optimize several global routing objectives simultaneously and effectively. In addition, a new global routing framework that combines a pure integer programming (IP) model (RNWO) with a sequential router is further developed to improve the wire-length, total number of vias and congestion by about 11%, 49% and 86% respectively with 6x speedup compared to a traditional maze router. It also produces 48% less total overflow and 19% less CPU time with similar wire-length compared to Fengshui 5.1.