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Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits



With the reducing size of the devices, the leakage power has also increased exponentially
in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the
leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes
the leakage power without any complexity in the circuit. However, the power-gating technique suffers
from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique
to minimize leakage power in MTCMOS circuits.



The objective of the paper was to propose a new technique which effectively minimizes leakage
power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can
well be implemented in high-speed low-power digital integrated circuits.



A new power-gating structure has been proposed in this paper. The new proposed technique
includes three parallel NMOS transistors with variable widths which are functional during the active mode
to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS
footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology
to implement a 32 bit adder circuit.



The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation
energy. The technique reduced the leakage power effectively at room temperature as well as
higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%,
64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and
the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the
proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the
parallel transistor, variable-width, CR and Modified-CR techniques, respectively.



The proposed technique offers significant reduction in leakage power, reactivation noise and
reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at
higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can
be easily implemented in high-speed low-power digital circuits.
