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Embedded System for Network Flow Identification

This paper presents the design and implementation of an embedded system for real-time network flow identification. The system identifies data flows based on packet inspection. The main advantage of this system is that it reduces significantly the processing time required for the flow identification. For the hardware implementation, a Xilinx Virtex-II Pro FPGA device and the Xilinx embedded development kit (EDK) software are used. This embedded system represents the first step for designing a reconfigurable router with QoS (quality of service) support