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Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis

Zero-defect VLSI design is a goal one must try to reach and CAD tools provide an increasingly important support to designers. High-level automated synthesis and formal verification are cooperating approaches to this end. The paper analyzes the general framework of digital design and the relationships between synthesis and verification as far as functional correctness is concerned, showing their limits, mutual dependencies, and how they can and should work together.