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Scaling challenges and solutions beyond 10nm

10nm and beyond nodes face significant challenges in pitch scaling and delivering better chip performance at iso power. Increased parasitics and variability due to gate pitch (CPP) and metal pitch scaling require significant innovation in materials, patterning, conformal, higher aspect ratio filling and high selectivity atomic layer etching. Multi-pattern lithography with regularity and restrictive design rules have allowed us to move far beyond 193i single patterning capabilities. However, continued pitch scaling at advanced node will require EUY, at the least, on few critical layers. Innovation such as air gap insertion is in not only a backend metal solution but also in frontend of processing to reduce parasitic capacitance and poses significant challenges in manufacturing. Advanced device architectures such as GAA and Tunnel FET nanowires transistors will further add their own set of manufacturing challenges at advanced nodes in terms bending free suspended channels, conformal deposition and etching of gate stack materials, spacer formation and source/drain epitaxy. In reality, industry will rise to these challenges with innovation and yet be pragmatic in choosing innovation that meets high volume manufacturing requirements.