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Nanoelectronics and Nanospintronics: Fundamentals and Materials Perspective

The performance of digital electronics and information processing has been growing exponentially for the past decades. Scaling of the complementary metal oxide semiconductor (CMOS) technology has continued in the past half century in a scenario never evident in other industries. This industry has driven the unprecedented advance of electronics and thus in turn innovation of the information technology, producing immense impact in many facets of our daily life. The scaling has followed a simple practical observation of reducing the feature size by a factor of 2 for every 18 months first by Moore, known as Moore’s Law, and this scaling has made it possible to increase the functional throughput (density times speed) and scale down the cost of devices and chips. This advancement of semiconductor industry may be captured in Fig. 1 for the CMOS technology memory., which illustrates the advancement of Si CMOS and its anticipated targets in accordance with the ITRS roadmap. (It is noted that memory is used as an example, since memory will be first to reach the feature size limit and it is not constrained by the power dissipation issue (to be discussed later). The scaling will continue as long as it is physically possible and fiscally affordable to manufacturers and customers. Indeed, even though Si has low electron mobility and is an indirect-gap semiconductor lacking the applicable optical emission property, Si still wins over other materials such as III-V compounds, e.g., GaAs, InP and others. Because of convenient passivation of stable SiO2 and the compact self aligned CMOS structure, Si has become the mainstream electronic material for scaling the feature size, functionality throughput (F=density × speed) and the cost, following the Moore’s law stated above. The related materials issues in the past and in the near future are to assure the scaling and to continue the increase of the density and functionality at low cost. Fig.1: Trend of the Si MOSFET gate length for DRAM and FLASH in the research and production levels. The number of transistors per chip will reach the number of neurons in