{'fraction_non_alphanumeric': 0.025675675675675677, 'fraction_numerical': 0.002702702702702703, 'mean_word_length': 4.7890625, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Asymptotically efficient retiming under setup and hold constraints

We present a polynomial-time algorithm for retiming synchronous circuits with edge-triggered registers under setup and hold constraints. Given a circuit G and a target clock period c, our algorithm computes in O(V/sup 3/ E) steps a retimed circuit that achieves c and is free of hold violations, where V is the circuit's gate count, and E is the number of wires in the circuit. This is the first polynomial-time algorithm ever reported for retiming with constraints on both long and short paths. The asymptotically efficient operation of our algorithm is based on a novel formulation of the timing constraints as an integer monotonic program with O(E/sup 2/) inequalities.