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Performance evaluation of 6T, 7T & 8T SRAM at 180 nm technology

The high-speed system and shrinkage in technology lead to more complexity with higher power dissipation. This paper presents the design, simulation and analysis of 6T, 7T and 8T SRAM cells. The analysis has been done for dynamic power, static power, rise time, fall time, delay, and bandwidth measurements for SRAM cells at gdpk180 technology. The Cadence Virtuoso tool is used for drawing schematic, layout editing, design rule checking (DRC), layout versus schematic (LVS) to check whether layout matches the schematic and RCX. An attempt is also made to find out delay, static power, and dynamic power at different supply voltages. Results illustrate the static power dissipation is almost same for all the SRAM cells whereas dynamic power has the least value of 5.45 μw for 7T SRAM cell and 10.26 μw, the most for 8T SRAM cell. All the simulation results are carried out at fixed 27°C temperature.