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Increasing the energy efficiency of pipelined circuits via slack redistribution

Technology scaling and rising clock frequencies have made active and leakage power and power density major concerns. Traditional power-reduction techniques, such as dynamic voltage scaling, multi-VDD, gated-VDD, and multi-threshold designs, exploit the slack available in non-critical operations/modes and non-critical areas of the circuit. This limits the amount of power reduction when the circuit is balanced or the critical path dominates the power consumption. We present a systematic technique in which time borrowing (TB) (or slack passing) is used to enhance the effectiveness of such traditional low-power techniques that exploit the timing characteristics of a circuit. This is in addition to TB done for performance or even when TB opportunities for performance do not exist. We also propose non-uniform TB, in which not all primary output gates of a pipeline stage borrow equal amounts of time, to reduce power when TB for performance cannot be done. Two ways to distribute slack for low-power operation in a pipeline circuit are discussed and the effectiveness of TB for low-power is demonstrated using a high-performance 32-bit enhanced multiple output domino logic adder and an 8 x 8 Wallace tree multiplier. Slack redistribution improves the energy savings obtained using traditional low-power techniques as follows: maximum 22% and average 19% extra active energy savings for the adder and maximum 45% and average 37% extra sub-threshold leakage power savings for the multiplier.