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Efficient Design and Implementation of DFA Based Pattern Matching on Hardware

Pattern matching is a crucial task in several critical network services such as intrusion detection. In this paper we present an efficient implementation of the DFA with optimized area and optimized memory by the introduction of state minimization algorithm. By using minimized DFA the clock frequency reduces to 40% of the original and the area also reduces to 30%. This optimized architecture of DFA is simulated and synthesized using VHDL on the Xilinx ISE 12.4..