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Fast locking PLL with all-digital locked-aid circuit

A fast locking PLL with all-digital locked-aid circuit is proposed and analyzed. The proposed topology is based on two tuning loops: a frequency detector and a phase detector. A frequency detector is used for accelerate frequency locking time, and a phase detector is used to adjust fine phase error between reference and feedback clock. The proposed PLL circuit is designed based on the 0.35um CMOS process with 3.3V supply voltage. Experiment result shows that the locking time of the proposed PLL can be reduced over 87.5% in comparison with PLL that without locked-aid circuit.