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Challenges and key potential technological innovations for scaling MOSFETS through the end of the roadmap

The overall trends and challenges in logic MOSFET scaling are discussed from the perspective of the 2003 International Technology Roadmap for Semiconductors. Critical scaling challenges include gate leakage current and polysilicon gate depletion, difficulty in controlling short channel effects, etc. To address these, key innovations include high-k gate dielectric, metal gate electrode, strained silicon channel for enhanced mobility, and eventually, non-classical CMOS devices (e.g.. FinFETs).