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Efficient Main-Memory Hash Joins on Multi-Core CPUs: Does Hardware Still Matter?

The architectural changes introduced with multi-core CPUs have triggered a redesign of main-memory join algorithms. In the last few years, two diverging views have appeared. One approach advocates careful tailoring of the algorithm to the parameters of the architecture (cache sizes, TLB, and memory bandwidth). The other approach argues that modern hardware is good enough at hiding cache and TLB miss latencies and, consequently, the careful tailoring can be omitted without sacrificing performance. In this paper we resolve this conflict through an extensive experimental analysis of the design space using different algorithms and architectures. We have taken the algorithms presented in previous work and reimplemented them so that their results are comparable. We have run these optimized algorithms on the same datasets and compared their performance results. Our results are conclusive: hardware still matters. Join algorithms that take into consideration the architectural constraints perform far better than counterparts which rely on the hardware to hide the overhead of cache misses. In the paper, we explore a broader set of cardinalities and data distributions than in the original papers and show that these parameters also play a significant role in the overall performance.