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VLSI implementation of a quasi-ml, energy efficient fixed complexity sphere decoder for MIMO communication system

This paper presents a low power VLSI implementation of a novel Multiple-Input Multiple-Output (MIMO) decoder which combines Fixed Complexity Sphere Decoder (FSD) algorithm, real-valued lattice formulation and Pair-wise sorted QR decomposition (P-SQRD) searching approach to simultaneously improve the throughput, bit error rate (BER) and complexity. Two-stage approximate sorting scheme with minimum data swapping is adopted to realize a power efficient architecture. This ASIC is implemented in IBM 90 nm 8 metal layer standard CMOS technology with core area of 1.3 mm2. This design supports 4×4 antenna array with flexible modulations from BPSK to 16-QAM. At 0.8V core power supply, the estimated peak data rate exceeds 1.44Gbps. The estimated energy efficiency is 15.4 pJ/bit which is 50% better than the other state of the art SDs [1], [7].