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An area-efficient DLL based on a merged synchronous mirror delay structure for duty cycle correction

A DLL(Delay Locked Loop) with DCC(Duty Cycle Correction) has become an essential block in high speed memory and digital circuits. An SMD(Synchronous Mirror Delay) structure is widely used both for skew reduction and for DCC. In this paper, an area-efficient DLL structure based on the merged dual SMD is proposed. The merged structure allows the forward delay array to be shared between the DLL and the DCC, yielding a 25% saving in the number of the required delay cells. The designed chip was fabricated using a 0.25-µm one-poly, four-metal CMOS process. Measurement of the fabricated chip showed that the duty cycle of the output clock is corrected to within ±3% for the input duty variation of ±30% in the frequency range from 400MHz to 600MHz with the lock time within three clock cycles.