{'fraction_non_alphanumeric': 0.026905829596412557, 'fraction_numerical': 0.0, 'mean_word_length': 5.504854368932039, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Mechanism and Improvement of On-Resistance Degradation Induced by Avalanche Breakdown in Lateral DMOS Transistors

On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.