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A highly reliable butterfly PUF in SRAM-based FPGAs

This paper presents a butterfly physically unclonable function (PUF) implementation in SRAM-based field programmable gate arrays (FPGAs). To avoid output instability, we propose a delay difference test to identify reliable slices (mapped to which butterfly PUF cells are highly reliable) and then PUF reliability is significantly improved by selective mapping PUF cells to reliable slices, which is validated in experimental results.


Introduction
Physically unclonable function (PUF) [1][2][3], an innovative hardware security technology, exploits physical randomness derived from uncontrollable integrated circuit (IC) manufacturing process [4] to generate high-security secret keys. Good randomness in PUF outputs comes from highly symmetrical placement and isometric routing [5], i.e., no systematic skews in the circuit implementation, only in this way can the minute and random mismatches induced by manufacturing process dominate the PUF outputs.
Having been implemented with a nominally symmetric layout, the PUF outputs are likely to change from time to time (i.e., poor reliability) [6] when the fluctuation caused by operating conditions and thermal noise is greater than or close to the manufacturing mismatch. The conventional method to improve PUF reliability is based on the use of error correction codes (ECC), while the approach significantly increases the complexity and cost of the design, and worse, the correcting code could reveal some important information. Another widely used method is mismatch selection, for instance, adjusting ring oscillator (RO) configuration to select maximum frequency difference between two ROs with the same layout, and then the authors in [7] greatly improve RO PUF reliability.
While in the case of simple-structure PUFs (e.g. SRAM PUF and butterfly PUF), it is quite difficult to perform an accurate mismatch estimation since propagation delay of each chain is too small to be measured. Based on multiple enrollment tests in different environmental conditions, a methodology to identify unreliable bits is proposed in [8] in which choosing only the reliable ones in the PUF implementation leads to high reliability. However, the approach is not recommended due to high complexity, time consuming, and limited precision (inability to cover all operating conditions). In this paper, we propose a novel mismatch estimation approach in SRAM-based field programmable gate arrays (FPGAs), utilizing the effect of load adjustment (fan-outs increasing/decreasing) on chain delay, to identify reliable slices (large delay difference between two chains) and then selective mapping PUF cells to the reliable slices, effectively improving PUF reliability.
Our proposed butterfly PUF cell actually is a simple SR NAND latch (can be compactly mapped to single slice) as shown in Fig. 1 in which four Dtype flip-flops (DFFs) surround the latch (avoid direct connection to external routing resources) in order for a highly symmetrical layout. And appending one buffer to each chain is to facilitate fan-out insertion for load adjustment. It should be noted that, in the paper, a fan-out insertion (to a chain) is implemented by connecting one node in the chain to an input port of an adjacent look up table (LUT). According to the Post-Place & Route Static Timing, each inserting a fan-out, chain delay is increased by 8 picoseconds, while actually the mean delay increment in three ML605 platforms (equipped with a 40 nm Virtex-6 FPGA) is about 3.4 ps as shown in Fig. 2.  A LUT has 6 inputs, thus mapping a 2-input NAND to single LUT has 30 choices. Taking four LUTs and four DFFs (one slice) into consideration, and then mapping the PUF cell to one slice has a large number of configuration cases. With the help of FPGA Editor, PUF is implemented with a highly symmetric case with negligible delay difference between the two chains (the mismatch nominally is just 4 ps).

PUF Output
As shown in Fig. 1, firstly, the latch state is initialized when setting CLR to 1, then Y1Y2=11. Then by applying a low-to-high transition on TEST, both outputs, i.e., Y1 and Y2, go towards changing their value from 1 to 0. Since there may be slight propagation delay difference between the two chains, one chain may change its value sooner than the other, which causes the slower one to keep its state. This means that Y1Y2=01 (PUF outputs 0), if chain1-chain2<0, and Y1Y2=10 (PUF outputs 1), otherwise.
To have an in-depth understanding of PUF output, two chains' delay difference, determined by both manufacturing mismatch (marked in green) and the fluctuation (marked in yellow), is illustrated in Fig. 3 in which manufacturing mismatch follows a similar Gaussian distribution [9]. As shown in Fig. 3a, when manufacturing mismatch mapped to a slice is small, PUF output swings between 0 and 1. This means that the PUF cell cannot produce reliable bit when operating conditions change, in other words, the slice is unsuitable to be mapped since corresponding PUF cell does not show a strong preference to any of the two states (0 and 1). In the complementary case shown in Fig. 3b, PUF output has always been a state due to a large manufacturing mismatch and thus suitable for PUF purpose.

Improving PUF Reliability
The basic idea of improving PUF reliability is to selectively place PUF cells to reliable slices, mapped to which the manufacturing mismatch between the two chains is large, in such a way that the bit flipping can be considerably reduced (i.e., high reliability). To identify the reliable slices, in this paper, we exploit the influence of load adjustment (fan-outs increasing/decreasing) on chain delay to determine the manufacturing mismatch.
As illustrated in Fig. 4a, if manufacturing mismatch is small, two PUF outputs in both cases of respectively inserting fan-outs to chain1 and chain2 are different. Fig. 4b shows an opposite case where manufacturing difference is large and thus the PUF outputs in both cases are same. Obviously, based on whether the PUF outputs in both cases are same, we can determine whether the manufacturing mismatch is larger than the setting value, i.e., delay increment of each fan-out insertion multiplied by the number of inserting fan-outs. In other words, we can identify the desirable manufacturing mismatch through configuring corresponding number of fan-outs insertion. The setting value directly affects the efficiency of the method. Using a low value introduces the risk of under-testing, i.e., some of the slices which cause PUF unreliability remained undetected during enrollment test. If the value is too high, there is the risk of over-testing, i.e., more suitable slices are eliminated then needing more enrolled slices. It should be noted that the delay difference test is easily implemented in SRAM-based FPGAs due to rich routing resources and dynamic partial reconfiguration (DPR) capabilities.

Experimental Results
In the experiment, multiple groups of fan-outs insertion on three ML605 platforms are chosen to validate the effectiveness of our proposed reliability improvement methodology. As shown in Table I, firstly, 300 instances of butterfly PUF cells are implemented and each slice is defined as reliable slice if corresponding PUF instance outputs in both cases (respectively inserting fan-outs to chain1 and chain2) are same at enrollment test (enrollment environment is 25 degrees Celsius and 1 V). Then, we implement a 128-bit PUF which mapped to 128 reliable slices and the PUF is tested 630 (7*9*10) times under a wide range of operating conditions (changing the temperature from 20 degrees Celsius to 80 degrees Celsius in 10 degrees Celsius steps and the core voltage from 0.8 V to 1.2 V in 0.05 V steps), the PUF cell remaining unchanged in all measurements is considered as reliable cell.
As shown in Table I, taking chip1 for example, when the number of fanouts insertion is 1, the number of detected suitable slices is 245. Unsurpris-IEICE Electronics Express, Vol.*, No.*, [1][2][3][4][5][6] ingly, the test coverage is lower than 100%, i.e., not all unreliable slices have been detected, thus the reliability probability is 78.9%. Increasing the number to 4, the number of defined reliable slices is 186 and the test coverage is larger than 100% (PUF reliability is 100%). It is clear that our proposed reliability improvement methodology can effectively improve PUF reliability.
The NIST statistical test suite [10], established for evaluating random number generators, here is used to prove PUF randomness. In this experiment, 99 128-bit PUF bitstreams are implemented in three ML605 platforms. Table II gives detailed test result from which we conclude that our proposed PUF passes the randomness test and acquires good randomness.

Conclusion
The fluctuation caused by operating conditions and thermal noise may damage PUF's ability to reproduce the identical output. In the paper, we propose a novel manufacturing mismatch estimation to identify reliable slices and then selective mapping effectively improves PUF reliability.