{'fraction_non_alphanumeric': 0.031007751937984496, 'fraction_numerical': 0.0, 'mean_word_length': 4.872727272727273, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels

We present designs for high-speed bus-invert coding on FPGAs. The purpose is to reduce switching activities on off-chip buses driven through dual-data-rate outputs. For bus-invert coding, the performance-limiting unit is the majority voter circuit. In order to support very high data rates, we use both pipelined and approximate solutions for this unit. The approximate solution is optimized for LUT-based FPGAs and achieves high performance at lower hardware costs, at an only slightly decreased efficiency. We give performance figures for the algorithms and the circuitry.