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A content addressable memory for use in CEBAF's CLAS detector level 2 triggering system

A collaboration of researchers from CEBAF, CNU and NASA is designing a 256/spl times/32 specialized Content Addressable Memory (CAM) for the level 2 triggering system in CEBAF's CLAS detector. These integrated circuits will find tracks and the momentum and angle of each track within 2 microseconds of an event. The custom CAM can operate as conventional memory, performing read and write operations, and can additionally perform independent byte compare operations across all words simultaneously. It is this compare feature which makes these CAMs attractive for identifying tracks passing through drift chambers by linking together segment number triplets within the CAM. Simulations have indicated that less than 16 K triplets need to be stored for each sector of the detector. This implies the level 2 triggering can be performed with 64 CAM chips per sector, or 384 total. Each data channel into a sector CAM array is buffered in a FIFO and is designed to handle aggregate data rates up to 750 Mbs for three channels (one channel/superlayer). The architecture of the level 2 trigger and details of the CAM chip design are discussed along with a performance report on our prototype CAMs.