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Cache optimization for an embedded MPEG-4 video decoder

Video decoders are an important component in modern networked multimedia systems. TMS320DM642 is suitable for implementation of embedded video decoder. However, the high data rate, large sizes, and distinctive memory access patterns of MPEG-4 video decoders exert a particular strain on cache. This paper proposes an optimization method to allocate the memory of TMS320DM642. In cache-SRAM-SDRAM structure, the SRAM negotiates the unbalance of the cache and the SDRAM in speed and capacity. Due to its importance, a cache-based memory allocation mode is proposed to make full use of the SRAM. According to this mode, the SRAM is divided into three sections: the data exchanging section, the core code and variables storage section, and the rest of the SRAM which is set as cache for the other codes and data management. The experiment results show the proposed solutions can improve the MPEG-4 decoding speed by almost 25%. This cache optimization method has been integrated into the developed embedded MPEG-4 video decoder. The decoder can perform real time decoding with bitstreams coded under two channels 4CIF or eight channels CIF frame size which is the typical requirement of networked video surveillance applications nowadays