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Low power circuit techniques for optimizing power in high speed SRAMs

As we are migrating toward low supply voltages, the threshold and supply voltage fluctuations will begin to have larger impact on the speed and power specification of SRAMs. Here, we present different techniques which minimize the effect of operating condition's variability on the speed and power of SRAM. A 2MB SRAM is designed with umc90nm technology having power supply of 1V. Firstly, the floor plan of SRAM uses hierarchical and divided word line approach which helps in reducing power by switching on only that part of SRAM which is being accessed. Secondly, SRAM major power is consumed by sense amplifiers, so replica based circuits are used which have replica memory cells and bitlines used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulse widths to limit bitline swings. We implement the replica circuits by using bitline capacitance ratioing and compared it with standard chain of inverters techniques. Furthermore, a partial power gating technique is also implemented in local word driver which also reduces power. This SRAM is also tested at various process corners.