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Esterel as Modeling Languages for the Semi-Formal Validation of a DSP System

We propose a modeling methodology which enables the semi-formal validation of hardware digital designs. A software model of the system to verify is developed using the C++ and Esterel languages. They allow to build a fast and accurate model which may also be formally analyzed. This is the key point of our validation methodology since test cases are automatically generated to increase the state coverages. This paper describes the use of C++ and Esterel for modeling and of automatic test generation for verifying a DSP System in the family of the new Texas Instruments’ TMS320C55x.