{'fraction_non_alphanumeric': 0.01793103448275862, 'fraction_numerical': 0.0020689655172413794, 'mean_word_length': 5.780373831775701, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
HEVC decoder optimization in low power configurable architecture for wireless devices

High Efficiency Video Coding (HEVC) is the new video compression standard, reducing bitrates nearly at half compared to H.264, offering potentially significant power savings for wireless video transmission at the network interface. This reduction in bitrate is achieved by a series of computationally expensive algorithms, thus making imperative to optimize HEVC decoding in order to provide a low-power implementation that can be used in mobile devices. Extending the Instruction Set Architecture (ISA) of a configurable microprocessor with new instructions for a target application can reduce the total effort of the application, thus reducing operating frequency and eventually power. The flexibility and relatively low design effort of such microprocessors - compared to hardwired Application-Specific-Integrated-Circuit (ASIC) designs - reduces the time space for adoption of HEVC and makes them an efficient alternative for wireless devices. We propose an efficient quarter-pixel interpolation filter implementation for HEVC using new custom-made instructions and other techniques for optimization of motion compensation, implemented on a configurable microprocessor architecture. Simulation results show a four times acceleration on average of the interpolation filter module over the reference HEVC software and an overall doubling in decoder performance.