{'fraction_non_alphanumeric': 0.017167381974248927, 'fraction_numerical': 0.0, 'mean_word_length': 5.226666666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Fully parallel FPGA decoder for irregular LDPC codes

One of the most significant current discussions in error correction coding is on the replacement of state-of-the-art codes by new innovative solutions. We propose a scalable parallel FPGA architecture for LDPC decoding. Regular and irregular codes are supported by the presented architecture. The architecture can be easily utilized in hardware applications. The performance of synthetized decoders is presented.