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Effects of Dummy Gate on Breakdown and Degradation of LDMOSFETs

For the first time, the effects of dummy-gate geometry and bias on breakdown and degradation of LDMOSFETs are quantified both theoretically and experimentally. First, the effects of dummy-gate geometry and bias are analyzed numerically by using a 2-D physical device simulator. Second, the simulated 2-D effects are approximated by a ldquodummy-gate chargerdquo in 1-D analytical solutions. Third, the 1-D analytical solutions are calibrated against breakdown and degradation characteristics measured on LDMOSFETs of different dummy-gate geometries and biases. The validated solutions can then serve as the basis for optimizing the design and operation of LDMOSFETs with the best tradeoff between performance and reliability.