{'fraction_non_alphanumeric': 0.00927643784786642, 'fraction_numerical': 0.0, 'mean_word_length': 6.012987012987013, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Including the impact of connecting vias in the performance metric evaluation for board-level optimization of decoupling capacitors

Existing decoupling capacitor optimization techniques tend to neglect the impact of via parasitics while evaluating the performance metrics. This work demonstrates that ignoring the impact of connecting vias can produce optimistic results leading to functional failure. An efficient method for including via-parasitics in the performance metric evaluation is presented for more accurate design optimization.